From 11f330ed223f524cbbdbe2433599990a69b8f380 Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Tue, 3 Sep 2019 11:53:37 +0300 Subject: Add tests for ECP5 architecture --- tests/ecp5/memory_synth.v | 2121 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 2121 insertions(+) create mode 100644 tests/ecp5/memory_synth.v (limited to 'tests/ecp5/memory_synth.v') diff --git a/tests/ecp5/memory_synth.v b/tests/ecp5/memory_synth.v new file mode 100644 index 000000000..a6172de61 --- /dev/null +++ b/tests/ecp5/memory_synth.v @@ -0,0 +1,2121 @@ +/* Generated by Yosys 0.9+36 (git sha1 7e8f7f4c, gcc 8.3.0-6ubuntu1 -Og -fPIC) */ + +(* top = 1 *) +(* src = "memory.v:1" *) +module top(data_a, addr_a, we_a, clk, q_a); + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _000_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _001_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _002_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _003_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _004_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _005_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _006_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _007_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _008_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _009_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _010_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _011_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _012_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _013_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _014_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _015_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _016_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _017_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _018_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _019_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _020_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _021_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _022_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _023_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _024_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _025_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _026_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _027_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _028_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _029_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _030_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _031_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _032_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _033_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _034_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _035_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _036_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _037_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _038_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _039_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _040_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _041_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _042_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _043_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _044_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _045_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _046_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _047_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _048_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _049_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _050_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _051_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _052_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _053_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _054_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _055_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _056_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _057_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _058_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _059_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _060_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _061_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _062_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _063_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _064_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _065_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _066_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _067_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _068_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _069_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _070_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _071_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _072_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _073_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _074_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _075_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _076_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _077_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _078_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _079_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _080_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _081_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _082_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _083_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _084_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _085_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _086_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _087_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _088_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _089_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _090_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _091_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _092_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _093_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _094_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _095_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _096_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _097_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _098_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _099_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _100_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _101_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _102_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _103_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _104_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _105_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _106_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _107_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _108_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _109_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _110_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _111_; + wire _112_; + wire _113_; + wire _114_; + wire _115_; + wire _116_; + wire _117_; + wire _118_; + wire _119_; + wire _120_; + wire _121_; + wire _122_; + wire _123_; + wire _124_; + wire _125_; + wire _126_; + wire _127_; + wire _128_; + wire _129_; + wire _130_; + wire _131_; + wire _132_; + wire _133_; + wire _134_; + wire _135_; + wire _136_; + wire _137_; + wire _138_; + wire _139_; + wire _140_; + wire _141_; + wire _142_; + wire _143_; + wire _144_; + wire _145_; + wire _146_; + wire _147_; + wire _148_; + wire _149_; + wire _150_; + wire _151_; + wire _152_; + wire _153_; + wire [3:0] _154_; + wire [3:0] _155_; + wire [3:0] _156_; + wire [3:0] _157_; + wire [3:0] _158_; + wire [3:0] _159_; + wire [3:0] _160_; + wire [3:0] _161_; + (* src = "memory.v:4" *) + input [6:1] addr_a; + (* src = "memory.v:5" *) + input clk; + (* src = "memory.v:3" *) + input [7:0] data_a; + (* src = "memory.v:6" *) + output [7:0] q_a; + (* src = "memory.v:5" *) + input we_a; + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:92" *) + LUT4 #( + .INIT(16'bxxx0xxx0xxx0xxx1) + ) _162_ ( + .A(1'h0), + .B(1'h0), + .C(addr_a[5]), + .D(addr_a[6]), + .Z(_147_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:92" *) + LUT4 #( + .INIT(16'bxxx0xxx0xxx1xxx0) + ) _163_ ( + .A(1'h0), + .B(1'h0), + .C(addr_a[5]), + .D(addr_a[6]), + .Z(_148_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:92" *) + LUT4 #( + .INIT(16'bxxx0xxx0xxx1xxx0) + ) _164_ ( + .A(1'h0), + .B(1'h0), + .C(addr_a[6]), + .D(addr_a[5]), + .Z(_149_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:96" *) + LUT4 #( + .INIT(16'bx1x0x0x0x0x0x0x0) + ) _165_ ( + .A(1'h0), + .B(we_a), + .C(addr_a[5]), + .D(addr_a[6]), + .Z(_153_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:96" *) + LUT4 #( + .INIT(16'bx0x0x0x0x0x0x1x0) + ) _166_ ( + .A(1'h0), + .B(we_a), + .C(addr_a[5]), + .D(addr_a[6]), + .Z(_150_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:96" *) + LUT4 #( + .INIT(16'bx0x0x0x0x1x0x0x0) + ) _167_ ( + .A(1'h0), + .B(we_a), + .C(addr_a[5]), + .D(addr_a[6]), + .Z(_151_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:96" *) + LUT4 #( + .INIT(16'bx0x0x0x0x1x0x0x0) + ) _168_ ( + .A(1'h0), + .B(we_a), + .C(addr_a[6]), + .D(addr_a[5]), + .Z(_152_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:130" *) + LUT4 #( + .INIT(16'hf000) + ) _169_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_136_), + .Z(_000_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:132" *) + LUT4 #( + .INIT(16'hfccc) + ) _170_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_136_), + .Z(_001_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:135" *) + LUT4 #( + .INIT(16'hfaaa) + ) _171_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_136_), + .Z(_002_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:137" *) + LUT4 #( + .INIT(16'hfeee) + ) _172_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_136_), + .Z(_003_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:140" *) + LUT4 #( + .INIT(16'hf101) + ) _173_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_136_), + .Z(_004_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:142" *) + LUT4 #( + .INIT(16'hfdcd) + ) _174_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_136_), + .Z(_005_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:145" *) + LUT4 #( + .INIT(16'hfbab) + ) _175_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_136_), + .Z(_006_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:147" *) + LUT4 #( + .INIT(16'hffef) + ) _176_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_136_), + .Z(_007_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:150" *) + PFUMX _177_ ( + .ALUT(_001_), + .BLUT(_000_), + .C0(_132_), + .Z(_008_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:151" *) + PFUMX _178_ ( + .ALUT(_003_), + .BLUT(_002_), + .C0(_132_), + .Z(_009_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:152" *) + PFUMX _179_ ( + .ALUT(_005_), + .BLUT(_004_), + .C0(_132_), + .Z(_010_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:153" *) + PFUMX _180_ ( + .ALUT(_007_), + .BLUT(_006_), + .C0(_132_), + .Z(_011_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:154" *) + L6MUX21 _181_ ( + .D0(_008_), + .D1(_009_), + .SD(_128_), + .Z(_012_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:155" *) + L6MUX21 _182_ ( + .D0(_010_), + .D1(_011_), + .SD(_128_), + .Z(_013_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:156" *) + L6MUX21 _183_ ( + .D0(_012_), + .D1(_013_), + .SD(_140_), + .Z(q_a[4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:130" *) + LUT4 #( + .INIT(16'hf000) + ) _184_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_137_), + .Z(_014_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:132" *) + LUT4 #( + .INIT(16'hfccc) + ) _185_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_137_), + .Z(_015_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:135" *) + LUT4 #( + .INIT(16'hfaaa) + ) _186_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_137_), + .Z(_016_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:137" *) + LUT4 #( + .INIT(16'hfeee) + ) _187_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_137_), + .Z(_017_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:140" *) + LUT4 #( + .INIT(16'hf101) + ) _188_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_137_), + .Z(_018_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:142" *) + LUT4 #( + .INIT(16'hfdcd) + ) _189_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_137_), + .Z(_019_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:145" *) + LUT4 #( + .INIT(16'hfbab) + ) _190_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_137_), + .Z(_020_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:147" *) + LUT4 #( + .INIT(16'hffef) + ) _191_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_137_), + .Z(_021_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:150" *) + PFUMX _192_ ( + .ALUT(_015_), + .BLUT(_014_), + .C0(_133_), + .Z(_022_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:151" *) + PFUMX _193_ ( + .ALUT(_017_), + .BLUT(_016_), + .C0(_133_), + .Z(_023_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:152" *) + PFUMX _194_ ( + .ALUT(_019_), + .BLUT(_018_), + .C0(_133_), + .Z(_024_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:153" *) + PFUMX _195_ ( + .ALUT(_021_), + .BLUT(_020_), + .C0(_133_), + .Z(_025_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:154" *) + L6MUX21 _196_ ( + .D0(_022_), + .D1(_023_), + .SD(_129_), + .Z(_026_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:155" *) + L6MUX21 _197_ ( + .D0(_024_), + .D1(_025_), + .SD(_129_), + .Z(_027_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:156" *) + L6MUX21 _198_ ( + .D0(_026_), + .D1(_027_), + .SD(_141_), + .Z(q_a[5]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:130" *) + LUT4 #( + .INIT(16'hf000) + ) _199_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_138_), + .Z(_028_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:132" *) + LUT4 #( + .INIT(16'hfccc) + ) _200_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_138_), + .Z(_029_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:135" *) + LUT4 #( + .INIT(16'hfaaa) + ) _201_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_138_), + .Z(_030_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:137" *) + LUT4 #( + .INIT(16'hfeee) + ) _202_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_138_), + .Z(_031_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:140" *) + LUT4 #( + .INIT(16'hf101) + ) _203_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_138_), + .Z(_032_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:142" *) + LUT4 #( + .INIT(16'hfdcd) + ) _204_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_138_), + .Z(_033_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:145" *) + LUT4 #( + .INIT(16'hfbab) + ) _205_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_138_), + .Z(_034_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:147" *) + LUT4 #( + .INIT(16'hffef) + ) _206_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_138_), + .Z(_035_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:150" *) + PFUMX _207_ ( + .ALUT(_029_), + .BLUT(_028_), + .C0(_134_), + .Z(_036_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:151" *) + PFUMX _208_ ( + .ALUT(_031_), + .BLUT(_030_), + .C0(_134_), + .Z(_037_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:152" *) + PFUMX _209_ ( + .ALUT(_033_), + .BLUT(_032_), + .C0(_134_), + .Z(_038_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:153" *) + PFUMX _210_ ( + .ALUT(_035_), + .BLUT(_034_), + .C0(_134_), + .Z(_039_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:154" *) + L6MUX21 _211_ ( + .D0(_036_), + .D1(_037_), + .SD(_130_), + .Z(_040_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:155" *) + L6MUX21 _212_ ( + .D0(_038_), + .D1(_039_), + .SD(_130_), + .Z(_041_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:156" *) + L6MUX21 _213_ ( + .D0(_040_), + .D1(_041_), + .SD(_142_), + .Z(q_a[6]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:130" *) + LUT4 #( + .INIT(16'hf000) + ) _214_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_139_), + .Z(_042_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:132" *) + LUT4 #( + .INIT(16'hfccc) + ) _215_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_139_), + .Z(_043_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:135" *) + LUT4 #( + .INIT(16'hfaaa) + ) _216_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_139_), + .Z(_044_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:137" *) + LUT4 #( + .INIT(16'hfeee) + ) _217_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_139_), + .Z(_045_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:140" *) + LUT4 #( + .INIT(16'hf101) + ) _218_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_139_), + .Z(_046_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:142" *) + LUT4 #( + .INIT(16'hfdcd) + ) _219_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_139_), + .Z(_047_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:145" *) + LUT4 #( + .INIT(16'hfbab) + ) _220_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_139_), + .Z(_048_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:147" *) + LUT4 #( + .INIT(16'hffef) + ) _221_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_139_), + .Z(_049_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:150" *) + PFUMX _222_ ( + .ALUT(_043_), + .BLUT(_042_), + .C0(_135_), + .Z(_050_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:151" *) + PFUMX _223_ ( + .ALUT(_045_), + .BLUT(_044_), + .C0(_135_), + .Z(_051_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:152" *) + PFUMX _224_ ( + .ALUT(_047_), + .BLUT(_046_), + .C0(_135_), + .Z(_052_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:153" *) + PFUMX _225_ ( + .ALUT(_049_), + .BLUT(_048_), + .C0(_135_), + .Z(_053_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:154" *) + L6MUX21 _226_ ( + .D0(_050_), + .D1(_051_), + .SD(_131_), + .Z(_054_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:155" *) + L6MUX21 _227_ ( + .D0(_052_), + .D1(_053_), + .SD(_131_), + .Z(_055_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:156" *) + L6MUX21 _228_ ( + .D0(_054_), + .D1(_055_), + .SD(_143_), + .Z(q_a[7]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:130" *) + LUT4 #( + .INIT(16'hf000) + ) _229_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_120_), + .Z(_056_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:132" *) + LUT4 #( + .INIT(16'hfccc) + ) _230_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_120_), + .Z(_057_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:135" *) + LUT4 #( + .INIT(16'hfaaa) + ) _231_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_120_), + .Z(_058_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:137" *) + LUT4 #( + .INIT(16'hfeee) + ) _232_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_120_), + .Z(_059_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:140" *) + LUT4 #( + .INIT(16'hf101) + ) _233_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_120_), + .Z(_060_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:142" *) + LUT4 #( + .INIT(16'hfdcd) + ) _234_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_120_), + .Z(_061_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:145" *) + LUT4 #( + .INIT(16'hfbab) + ) _235_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_120_), + .Z(_062_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:147" *) + LUT4 #( + .INIT(16'hffef) + ) _236_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_120_), + .Z(_063_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:150" *) + PFUMX _237_ ( + .ALUT(_057_), + .BLUT(_056_), + .C0(_116_), + .Z(_064_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:151" *) + PFUMX _238_ ( + .ALUT(_059_), + .BLUT(_058_), + .C0(_116_), + .Z(_065_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:152" *) + PFUMX _239_ ( + .ALUT(_061_), + .BLUT(_060_), + .C0(_116_), + .Z(_066_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:153" *) + PFUMX _240_ ( + .ALUT(_063_), + .BLUT(_062_), + .C0(_116_), + .Z(_067_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:154" *) + L6MUX21 _241_ ( + .D0(_064_), + .D1(_065_), + .SD(_112_), + .Z(_068_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:155" *) + L6MUX21 _242_ ( + .D0(_066_), + .D1(_067_), + .SD(_112_), + .Z(_069_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:156" *) + L6MUX21 _243_ ( + .D0(_068_), + .D1(_069_), + .SD(_124_), + .Z(q_a[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:130" *) + LUT4 #( + .INIT(16'hf000) + ) _244_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_121_), + .Z(_070_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:132" *) + LUT4 #( + .INIT(16'hfccc) + ) _245_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_121_), + .Z(_071_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:135" *) + LUT4 #( + .INIT(16'hfaaa) + ) _246_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_121_), + .Z(_072_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:137" *) + LUT4 #( + .INIT(16'hfeee) + ) _247_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_121_), + .Z(_073_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:140" *) + LUT4 #( + .INIT(16'hf101) + ) _248_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_121_), + .Z(_074_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:142" *) + LUT4 #( + .INIT(16'hfdcd) + ) _249_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_121_), + .Z(_075_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:145" *) + LUT4 #( + .INIT(16'hfbab) + ) _250_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_121_), + .Z(_076_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:147" *) + LUT4 #( + .INIT(16'hffef) + ) _251_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_121_), + .Z(_077_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:150" *) + PFUMX _252_ ( + .ALUT(_071_), + .BLUT(_070_), + .C0(_117_), + .Z(_078_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:151" *) + PFUMX _253_ ( + .ALUT(_073_), + .BLUT(_072_), + .C0(_117_), + .Z(_079_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:152" *) + PFUMX _254_ ( + .ALUT(_075_), + .BLUT(_074_), + .C0(_117_), + .Z(_080_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:153" *) + PFUMX _255_ ( + .ALUT(_077_), + .BLUT(_076_), + .C0(_117_), + .Z(_081_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:154" *) + L6MUX21 _256_ ( + .D0(_078_), + .D1(_079_), + .SD(_113_), + .Z(_082_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:155" *) + L6MUX21 _257_ ( + .D0(_080_), + .D1(_081_), + .SD(_113_), + .Z(_083_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:156" *) + L6MUX21 _258_ ( + .D0(_082_), + .D1(_083_), + .SD(_125_), + .Z(q_a[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:130" *) + LUT4 #( + .INIT(16'hf000) + ) _259_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_122_), + .Z(_084_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:132" *) + LUT4 #( + .INIT(16'hfccc) + ) _260_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_122_), + .Z(_085_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:135" *) + LUT4 #( + .INIT(16'hfaaa) + ) _261_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_122_), + .Z(_086_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:137" *) + LUT4 #( + .INIT(16'hfeee) + ) _262_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_122_), + .Z(_087_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:140" *) + LUT4 #( + .INIT(16'hf101) + ) _263_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_122_), + .Z(_088_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:142" *) + LUT4 #( + .INIT(16'hfdcd) + ) _264_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_122_), + .Z(_089_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:145" *) + LUT4 #( + .INIT(16'hfbab) + ) _265_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_122_), + .Z(_090_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:147" *) + LUT4 #( + .INIT(16'hffef) + ) _266_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_122_), + .Z(_091_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:150" *) + PFUMX _267_ ( + .ALUT(_085_), + .BLUT(_084_), + .C0(_118_), + .Z(_092_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:151" *) + PFUMX _268_ ( + .ALUT(_087_), + .BLUT(_086_), + .C0(_118_), + .Z(_093_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:152" *) + PFUMX _269_ ( + .ALUT(_089_), + .BLUT(_088_), + .C0(_118_), + .Z(_094_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:153" *) + PFUMX _270_ ( + .ALUT(_091_), + .BLUT(_090_), + .C0(_118_), + .Z(_095_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:154" *) + L6MUX21 _271_ ( + .D0(_092_), + .D1(_093_), + .SD(_114_), + .Z(_096_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:155" *) + L6MUX21 _272_ ( + .D0(_094_), + .D1(_095_), + .SD(_114_), + .Z(_097_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:156" *) + L6MUX21 _273_ ( + .D0(_096_), + .D1(_097_), + .SD(_126_), + .Z(q_a[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:130" *) + LUT4 #( + .INIT(16'hf000) + ) _274_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_123_), + .Z(_098_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:132" *) + LUT4 #( + .INIT(16'hfccc) + ) _275_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_123_), + .Z(_099_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:135" *) + LUT4 #( + .INIT(16'hfaaa) + ) _276_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_123_), + .Z(_100_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:137" *) + LUT4 #( + .INIT(16'hfeee) + ) _277_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_123_), + .Z(_101_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:140" *) + LUT4 #( + .INIT(16'hf101) + ) _278_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_123_), + .Z(_102_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:142" *) + LUT4 #( + .INIT(16'hfdcd) + ) _279_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_123_), + .Z(_103_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:145" *) + LUT4 #( + .INIT(16'hfbab) + ) _280_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_123_), + .Z(_104_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:147" *) + LUT4 #( + .INIT(16'hffef) + ) _281_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_123_), + .Z(_105_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:150" *) + PFUMX _282_ ( + .ALUT(_099_), + .BLUT(_098_), + .C0(_119_), + .Z(_106_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:151" *) + PFUMX _283_ ( + .ALUT(_101_), + .BLUT(_100_), + .C0(_119_), + .Z(_107_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:152" *) + PFUMX _284_ ( + .ALUT(_103_), + .BLUT(_102_), + .C0(_119_), + .Z(_108_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:153" *) + PFUMX _285_ ( + .ALUT(_105_), + .BLUT(_104_), + .C0(_119_), + .Z(_109_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:154" *) + L6MUX21 _286_ ( + .D0(_106_), + .D1(_107_), + .SD(_115_), + .Z(_110_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:155" *) + L6MUX21 _287_ ( + .D0(_108_), + .D1(_109_), + .SD(_115_), + .Z(_111_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:156" *) + L6MUX21 _288_ ( + .D0(_110_), + .D1(_111_), + .SD(_127_), + .Z(q_a[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _289_ ( + .CLK(clk), + .DI(_147_), + .LSR(1'h0), + .Q(_144_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _290_ ( + .CLK(clk), + .DI(_154_[0]), + .LSR(1'h0), + .Q(_112_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _291_ ( + .CLK(clk), + .DI(_154_[1]), + .LSR(1'h0), + .Q(_113_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _292_ ( + .CLK(clk), + .DI(_154_[2]), + .LSR(1'h0), + .Q(_114_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _293_ ( + .CLK(clk), + .DI(_154_[3]), + .LSR(1'h0), + .Q(_115_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _294_ ( + .CLK(clk), + .DI(_155_[0]), + .LSR(1'h0), + .Q(_116_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _295_ ( + .CLK(clk), + .DI(_155_[1]), + .LSR(1'h0), + .Q(_117_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _296_ ( + .CLK(clk), + .DI(_155_[2]), + .LSR(1'h0), + .Q(_118_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _297_ ( + .CLK(clk), + .DI(_155_[3]), + .LSR(1'h0), + .Q(_119_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _298_ ( + .CLK(clk), + .DI(_156_[0]), + .LSR(1'h0), + .Q(_120_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _299_ ( + .CLK(clk), + .DI(_156_[1]), + .LSR(1'h0), + .Q(_121_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _300_ ( + .CLK(clk), + .DI(_156_[2]), + .LSR(1'h0), + .Q(_122_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _301_ ( + .CLK(clk), + .DI(_156_[3]), + .LSR(1'h0), + .Q(_123_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _302_ ( + .CLK(clk), + .DI(_149_), + .LSR(1'h0), + .Q(_146_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _303_ ( + .CLK(clk), + .DI(_157_[0]), + .LSR(1'h0), + .Q(_124_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _304_ ( + .CLK(clk), + .DI(_157_[1]), + .LSR(1'h0), + .Q(_125_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _305_ ( + .CLK(clk), + .DI(_157_[2]), + .LSR(1'h0), + .Q(_126_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _306_ ( + .CLK(clk), + .DI(_157_[3]), + .LSR(1'h0), + .Q(_127_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _307_ ( + .CLK(clk), + .DI(_158_[0]), + .LSR(1'h0), + .Q(_128_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _308_ ( + .CLK(clk), + .DI(_158_[1]), + .LSR(1'h0), + .Q(_129_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _309_ ( + .CLK(clk), + .DI(_158_[2]), + .LSR(1'h0), + .Q(_130_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _310_ ( + .CLK(clk), + .DI(_158_[3]), + .LSR(1'h0), + .Q(_131_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _311_ ( + .CLK(clk), + .DI(_159_[0]), + .LSR(1'h0), + .Q(_132_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _312_ ( + .CLK(clk), + .DI(_159_[1]), + .LSR(1'h0), + .Q(_133_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _313_ ( + .CLK(clk), + .DI(_159_[2]), + .LSR(1'h0), + .Q(_134_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _314_ ( + .CLK(clk), + .DI(_159_[3]), + .LSR(1'h0), + .Q(_135_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _315_ ( + .CLK(clk), + .DI(_148_), + .LSR(1'h0), + .Q(_145_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _316_ ( + .CLK(clk), + .DI(_160_[0]), + .LSR(1'h0), + .Q(_136_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _317_ ( + .CLK(clk), + .DI(_160_[1]), + .LSR(1'h0), + .Q(_137_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _318_ ( + .CLK(clk), + .DI(_160_[2]), + .LSR(1'h0), + .Q(_138_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _319_ ( + .CLK(clk), + .DI(_160_[3]), + .LSR(1'h0), + .Q(_139_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _320_ ( + .CLK(clk), + .DI(_161_[0]), + .LSR(1'h0), + .Q(_140_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _321_ ( + .CLK(clk), + .DI(_161_[1]), + .LSR(1'h0), + .Q(_141_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _322_ ( + .CLK(clk), + .DI(_161_[2]), + .LSR(1'h0), + .Q(_142_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _323_ ( + .CLK(clk), + .DI(_161_[3]), + .LSR(1'h0), + .Q(_143_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/lutrams_map.v:15" *) + TRELLIS_DPR16X4 #( + .INITVAL(64'hxxxxxxxxxxxxxxxx), + .WCKMUX("WCK"), + .WREMUX("WRE") + ) \ram.0.0.0 ( + .DI(data_a[3:0]), + .DO(_154_), + .RAD(addr_a[4:1]), + .WAD(addr_a[4:1]), + .WCK(clk), + .WRE(_150_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/lutrams_map.v:15" *) + TRELLIS_DPR16X4 #( + .INITVAL(64'hxxxxxxxxxxxxxxxx), + .WCKMUX("WCK"), + .WREMUX("WRE") + ) \ram.0.1.0 ( + .DI(data_a[3:0]), + .DO(_155_), + .RAD(addr_a[4:1]), + .WAD(addr_a[4:1]), + .WCK(clk), + .WRE(_151_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/lutrams_map.v:15" *) + TRELLIS_DPR16X4 #( + .INITVAL(64'hxxxxxxxxxxxxxxxx), + .WCKMUX("WCK"), + .WREMUX("WRE") + ) \ram.0.2.0 ( + .DI(data_a[3:0]), + .DO(_156_), + .RAD(addr_a[4:1]), + .WAD(addr_a[4:1]), + .WCK(clk), + .WRE(_152_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/lutrams_map.v:15" *) + TRELLIS_DPR16X4 #( + .INITVAL(64'hxxxxxxxxxxxxxxxx), + .WCKMUX("WCK"), + .WREMUX("WRE") + ) \ram.0.3.0 ( + .DI(data_a[3:0]), + .DO(_157_), + .RAD(addr_a[4:1]), + .WAD(addr_a[4:1]), + .WCK(clk), + .WRE(_153_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/lutrams_map.v:15" *) + TRELLIS_DPR16X4 #( + .INITVAL(64'hxxxxxxxxxxxxxxxx), + .WCKMUX("WCK"), + .WREMUX("WRE") + ) \ram.1.0.0 ( + .DI(data_a[7:4]), + .DO(_158_), + .RAD(addr_a[4:1]), + .WAD(addr_a[4:1]), + .WCK(clk), + .WRE(_150_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/lutrams_map.v:15" *) + TRELLIS_DPR16X4 #( + .INITVAL(64'hxxxxxxxxxxxxxxxx), + .WCKMUX("WCK"), + .WREMUX("WRE") + ) \ram.1.1.0 ( + .DI(data_a[7:4]), + .DO(_159_), + .RAD(addr_a[4:1]), + .WAD(addr_a[4:1]), + .WCK(clk), + .WRE(_151_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/lutrams_map.v:15" *) + TRELLIS_DPR16X4 #( + .INITVAL(64'hxxxxxxxxxxxxxxxx), + .WCKMUX("WCK"), + .WREMUX("WRE") + ) \ram.1.2.0 ( + .DI(data_a[7:4]), + .DO(_160_), + .RAD(addr_a[4:1]), + .WAD(addr_a[4:1]), + .WCK(clk), + .WRE(_152_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/lutrams_map.v:15" *) + TRELLIS_DPR16X4 #( + .INITVAL(64'hxxxxxxxxxxxxxxxx), + .WCKMUX("WCK"), + .WREMUX("WRE") + ) \ram.1.3.0 ( + .DI(data_a[7:4]), + .DO(_161_), + .RAD(addr_a[4:1]), + .WAD(addr_a[4:1]), + .WCK(clk), + .WRE(_153_) + ); +endmodule -- cgit v1.2.3