From 11f330ed223f524cbbdbe2433599990a69b8f380 Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Tue, 3 Sep 2019 11:53:37 +0300 Subject: Add tests for ECP5 architecture --- tests/ecp5/memory.ys | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 tests/ecp5/memory.ys (limited to 'tests/ecp5/memory.ys') diff --git a/tests/ecp5/memory.ys b/tests/ecp5/memory.ys new file mode 100644 index 000000000..c90f1991e --- /dev/null +++ b/tests/ecp5/memory.ys @@ -0,0 +1,21 @@ +read_verilog memory.v +hierarchy -top top +proc +memory -nomap +equiv_opt -run :prove -map +/ecp5/cells_sim.v synth_ecp5 +memory +opt -full + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +#ERROR: Called with -verify and proof did fail! +#sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter + +design -load postopt +cd top +select -assert-count 24 t:L6MUX21 +select -assert-count 71 t:LUT4 +select -assert-count 32 t:PFUMX +select -assert-count 8 t:TRELLIS_DPR16X4 +select -assert-count 35 t:TRELLIS_FF +select -assert-none t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_DPR16X4 t:TRELLIS_FF %% t:* %D +write_verilog memory_synth.v -- cgit v1.2.3 From 55fbc1a355a6139872a176318356ecdb71a35f5d Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Tue, 3 Sep 2019 12:11:12 +0300 Subject: Uncomment sat command in memory.ys test. --- tests/ecp5/memory.ys | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'tests/ecp5/memory.ys') diff --git a/tests/ecp5/memory.ys b/tests/ecp5/memory.ys index c90f1991e..9cc6bb5be 100644 --- a/tests/ecp5/memory.ys +++ b/tests/ecp5/memory.ys @@ -7,8 +7,7 @@ memory opt -full miter -equiv -flatten -make_assert -make_outputs gold gate miter -#ERROR: Called with -verify and proof did fail! -#sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter +sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter design -load postopt cd top -- cgit v1.2.3 From a203c8569cb6fc7093a5d09e4c64d8e545f81e39 Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Wed, 4 Sep 2019 12:15:52 +0300 Subject: Fix ecp5 tests - remove *_synth.v files and generation in scripts; - change synth_ice40 to synth_ecp5; --- tests/ecp5/memory.ys | 1 - 1 file changed, 1 deletion(-) (limited to 'tests/ecp5/memory.ys') diff --git a/tests/ecp5/memory.ys b/tests/ecp5/memory.ys index 9cc6bb5be..9b475f122 100644 --- a/tests/ecp5/memory.ys +++ b/tests/ecp5/memory.ys @@ -17,4 +17,3 @@ select -assert-count 32 t:PFUMX select -assert-count 8 t:TRELLIS_DPR16X4 select -assert-count 35 t:TRELLIS_FF select -assert-none t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_DPR16X4 t:TRELLIS_FF %% t:* %D -write_verilog memory_synth.v -- cgit v1.2.3