From 4d9d90079c6e069fcba7ce04e8005285f4f237fe Mon Sep 17 00:00:00 2001 From: Dan Ravensloft Date: Tue, 21 Jul 2020 13:58:38 +0100 Subject: intel_alm: add additional ABC9 timings --- tests/arch/intel_alm/mux.ys | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) (limited to 'tests/arch') diff --git a/tests/arch/intel_alm/mux.ys b/tests/arch/intel_alm/mux.ys index d109257bd..8277e925f 100644 --- a/tests/arch/intel_alm/mux.ys +++ b/tests/arch/intel_alm/mux.ys @@ -47,10 +47,9 @@ proc equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux8 # Constrain all select calls below inside the top module -select -assert-count 1 t:MISTRAL_ALUT3 -select -assert-count 1 t:MISTRAL_ALUT5 -select -assert-count 2 t:MISTRAL_ALUT6 -select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D +select -assert-count 3 t:MISTRAL_ALUT5 +select -assert-count 1 t:MISTRAL_ALUT6 +select -assert-none t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D design -load read @@ -70,10 +69,9 @@ proc equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module -select -assert-count 1 t:MISTRAL_ALUT3 select -assert-count 2 t:MISTRAL_ALUT5 select -assert-count 4 t:MISTRAL_ALUT6 -select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D +select -assert-none t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D design -load read -- cgit v1.2.3