From 3d149aff733692b368919191dc31e731cbba9cfa Mon Sep 17 00:00:00 2001
From: Dan Ravensloft <dan.ravensloft@gmail.com>
Date: Thu, 23 Apr 2020 00:56:49 +0100
Subject: intel_alm: work around a Quartus ICE

---
 tests/arch/intel_alm/quartus_ice.ys | 12 ++++++++++++
 1 file changed, 12 insertions(+)
 create mode 100644 tests/arch/intel_alm/quartus_ice.ys

(limited to 'tests/arch/intel_alm')

diff --git a/tests/arch/intel_alm/quartus_ice.ys b/tests/arch/intel_alm/quartus_ice.ys
new file mode 100644
index 000000000..4b9b54d10
--- /dev/null
+++ b/tests/arch/intel_alm/quartus_ice.ys
@@ -0,0 +1,12 @@
+read_verilog <<EOT
+// Verilog has syntax for raw identifiers, where you start it with \ and end it with a space.
+// This test crashes Quartus due to it parsing \a[10] as a wire slice and not a raw identifier.
+module top();
+  (* keep *) wire [31:0] \a[10] ;
+  (* keep *) wire b;
+  assign b = \a[10] [31];
+endmodule
+EOT
+
+synth_intel_alm -family cyclonev -quartus
+select -assert-none w:*[* w:*]*
-- 
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