From 8de17877d4073a6e593ea650b8eca0488f653d24 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 3 Dec 2019 14:48:00 -0800
Subject: Add testcase

---
 tests/arch/ice40/ice40_opt.ys | 60 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 60 insertions(+)

(limited to 'tests/arch/ice40')

diff --git a/tests/arch/ice40/ice40_opt.ys b/tests/arch/ice40/ice40_opt.ys
index b17c69c91..58c33acaa 100644
--- a/tests/arch/ice40/ice40_opt.ys
+++ b/tests/arch/ice40/ice40_opt.ys
@@ -24,3 +24,63 @@ equiv_opt -assert -map +/ice40/cells_map.v -map +/ice40/cells_sim.v ice40_opt
 design -load postopt
 select -assert-count 1 t:*
 select -assert-count 1 t:$lut
+
+# https://github.com/YosysHQ/yosys/issues/1543
+design -reset
+read_verilog <<EOT
+module delay_element (input wire clk, input wire reset, input wire enable,
+                      input wire chainin,  output wire chainout, output reg latch);
+
+
+   reg                           const_zero = 0;
+   reg                           const_one = 1;
+
+    wire                         delay_tap;
+
+
+   //carry logic
+   (* keep *) SB_CARRY carry ( .CO(chainout), .I0(const_zero),
+                    .I1(const_one), .CI(chainin));
+
+
+   //flip flop latch
+   (* keep *) SB_DFFER flipflop( .Q(latch), .C(clk), .E(enable),
+                      .D(delay_tap), .R(reset));
+
+
+   //LUT table
+   // the LUT should just echo the carry in (I3)
+   // carry I0 = LUT I1
+   // carry I1 = LUT I2
+   // carry in = LUT I3
+   // LUT_INIT[0] = 0
+   // LUT_INIT[1] = 0
+   // LUT_INIT[2] = 0
+   // LUT_INIT[3] = 0
+   // LUT_INIT[4] = 0
+   // LUT_INIT[5] = 0
+   // LUT_INIT[6] = 0
+   // LUT_INIT[7] = 0
+   // LUT_INIT[8] = 1
+   // LUT_INIT[9] = 1
+   // LUT_INIT[10] = 1
+   // LUT_INIT[11] = 1
+   // LUT_INIT[12] = 1
+   // LUT_INIT[13] = 1
+   // LUT_INIT[14] = 1
+   // LUT_INIT[15] = 1
+
+   (* keep *) SB_LUT4 lut( .O(delay_tap), .I0(const_zero), .I1(const_zero),
+                .I2(const_one), .I3(chainin));
+
+   //TODO: is this the right way round??
+   defparam lut.LUT_INIT=16'hFF00;
+
+
+endmodule // delay_element
+EOT
+
+synth_ice40
+select -assert-count 1 t:SB_LUT4
+select -assert-count 1 t:SB_CARRY
+select -assert-count 1 t:SB_CARRY a:keep %i
-- 
cgit v1.2.3


From 67f1ce2d4340c359137ac00e4ca085e6711986f3 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 3 Dec 2019 14:51:39 -0800
Subject: Check SB_CARRY name also preserved

---
 tests/arch/ice40/ice40_opt.ys | 1 +
 1 file changed, 1 insertion(+)

(limited to 'tests/arch/ice40')

diff --git a/tests/arch/ice40/ice40_opt.ys b/tests/arch/ice40/ice40_opt.ys
index 58c33acaa..860e2e211 100644
--- a/tests/arch/ice40/ice40_opt.ys
+++ b/tests/arch/ice40/ice40_opt.ys
@@ -84,3 +84,4 @@ synth_ice40
 select -assert-count 1 t:SB_LUT4
 select -assert-count 1 t:SB_CARRY
 select -assert-count 1 t:SB_CARRY a:keep %i
+select -assert-count 1 t:SB_CARRY c:carry %i
-- 
cgit v1.2.3


From d8fbf88980d6ccd22e2aa3f34c4ff2a39aeed9df Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 5 Dec 2019 07:01:02 -0800
Subject: Add WIP test for unwrapping $__ICE40_CARRY_WRAPPER

---
 tests/arch/ice40/wrapcarry.ys | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

(limited to 'tests/arch/ice40')

diff --git a/tests/arch/ice40/wrapcarry.ys b/tests/arch/ice40/wrapcarry.ys
index 10c029e68..a4b0d357a 100644
--- a/tests/arch/ice40/wrapcarry.ys
+++ b/tests/arch/ice40/wrapcarry.ys
@@ -20,3 +20,33 @@ EOT
 
 ice40_wrapcarry
 select -assert-count 1 t:$__ICE40_CARRY_WRAPPER
+
+design -reset
+read_verilog <<EOT
+module top(input A, B, CI, output O, CO);
+    (* foo = "bar", answer = 42 *)
+	SB_CARRY carry (
+		.I0(A),
+		.I1(B),
+		.CI(CI),
+		.CO(CO)
+	);
+    (* keep, blah="blah", answer = 43 *)
+	SB_LUT4 #(
+		.LUT_INIT(16'b 0110_1001_1001_0110)
+	) adder (
+		.I0(1'b0),
+		.I1(A),
+		.I2(B),
+		.I3(1'b0),
+		.O(O)
+	);
+endmodule
+EOT
+
+ice40_wrapcarry
+select -assert-count 1 t:$__ICE40_CARRY_WRAPPER
+select -assert-count 0 t:* t:$__ICE40_CARRY_WRAPPER %d
+select -assert-count 1 a:foo=bar a:answer=42 %i a:keep %i a:blah=blah %i
+techmap -map +/ice40/cells_map.v
+#TODO: Check unwrapped attributes
-- 
cgit v1.2.3


From 946d5854c0b2e63a3757a0fbdf41276255967bc8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 6 Dec 2019 17:27:47 -0800
Subject: Drop keep=0 attributes on SB_CARRY

---
 tests/arch/ice40/wrapcarry.ys | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'tests/arch/ice40')

diff --git a/tests/arch/ice40/wrapcarry.ys b/tests/arch/ice40/wrapcarry.ys
index a4b0d357a..579335b27 100644
--- a/tests/arch/ice40/wrapcarry.ys
+++ b/tests/arch/ice40/wrapcarry.ys
@@ -24,7 +24,7 @@ select -assert-count 1 t:$__ICE40_CARRY_WRAPPER
 design -reset
 read_verilog <<EOT
 module top(input A, B, CI, output O, CO);
-    (* foo = "bar", answer = 42 *)
+    (* foo = "bar", answer = 42, keep=0 *)
 	SB_CARRY carry (
 		.I0(A),
 		.I1(B),
@@ -47,6 +47,6 @@ EOT
 ice40_wrapcarry
 select -assert-count 1 t:$__ICE40_CARRY_WRAPPER
 select -assert-count 0 t:* t:$__ICE40_CARRY_WRAPPER %d
-select -assert-count 1 a:foo=bar a:answer=42 %i a:keep %i a:blah=blah %i
+select -assert-count 1 a:foo=bar a:answer=42 %i a:keep=1 %i a:blah=blah %i
 techmap -map +/ice40/cells_map.v
 #TODO: Check unwrapped attributes
-- 
cgit v1.2.3


From e05372778a26e5cbc5166f208eddc6a1b42ed198 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 9 Dec 2019 11:48:28 -0800
Subject: ice40_wrapcarry to really preserve attributes via -unwrap option

---
 tests/arch/ice40/ice40_wrapcarry.ys | 54 +++++++++++++++++++++++++++++++++++++
 tests/arch/ice40/wrapcarry.ys       | 52 -----------------------------------
 2 files changed, 54 insertions(+), 52 deletions(-)
 create mode 100644 tests/arch/ice40/ice40_wrapcarry.ys
 delete mode 100644 tests/arch/ice40/wrapcarry.ys

(limited to 'tests/arch/ice40')

diff --git a/tests/arch/ice40/ice40_wrapcarry.ys b/tests/arch/ice40/ice40_wrapcarry.ys
new file mode 100644
index 000000000..fb9fccc3a
--- /dev/null
+++ b/tests/arch/ice40/ice40_wrapcarry.ys
@@ -0,0 +1,54 @@
+read_verilog <<EOT
+module top(input A, B, CI, output O, CO);
+	SB_CARRY carry (
+		.I0(A),
+		.I1(B),
+		.CI(CI),
+		.CO(CO)
+	);
+	SB_LUT4 #(
+		.LUT_INIT(16'b 0110_1001_1001_0110)
+	) adder (
+		.I0(1'b0),
+		.I1(A),
+		.I2(B),
+		.I3(1'b0),
+		.O(O)
+	);
+endmodule
+EOT
+
+ice40_wrapcarry
+select -assert-count 1 t:$__ICE40_CARRY_WRAPPER
+
+design -reset
+read_verilog <<EOT
+module top(input A, B, CI, output O, CO);
+    (* foo = "bar", answer = 42, keep=0 *)
+	SB_CARRY carry (
+		.I0(A),
+		.I1(B),
+		.CI(CI),
+		.CO(CO)
+	);
+    (* keep, blah="blah", answer = 43 *)
+	SB_LUT4 #(
+		.LUT_INIT(16'b 0110_1001_1001_0110)
+	) adder (
+		.I0(1'b0),
+		.I1(A),
+		.I2(B),
+		.I3(1'b0),
+		.O(O)
+	);
+endmodule
+EOT
+
+ice40_wrapcarry
+select -assert-count 1 t:$__ICE40_CARRY_WRAPPER
+select -assert-count 0 t:* t:$__ICE40_CARRY_WRAPPER %d
+select -assert-count 1 a:keep=1 a:SB_CARRY.\foo=bar %i a:SB_CARRY.\answer=42 %i a:SB_LUT4.\blah=blah %i a:SB_LUT4.\answer=43 %i
+
+ice40_wrapcarry -unwrap
+select -assert-count 1 c:carry a:src=<<EOT:3 %i a:keep=0 %i a:foo=bar %i a:answer=42 %i
+select -assert-count 1 c:adder a:src=<<EOT:10 %i a:keep=1 %i a:blah=blah %i a:answer=43 %i
diff --git a/tests/arch/ice40/wrapcarry.ys b/tests/arch/ice40/wrapcarry.ys
deleted file mode 100644
index 579335b27..000000000
--- a/tests/arch/ice40/wrapcarry.ys
+++ /dev/null
@@ -1,52 +0,0 @@
-read_verilog <<EOT
-module top(input A, B, CI, output O, CO);
-	SB_CARRY carry (
-		.I0(A),
-		.I1(B),
-		.CI(CI),
-		.CO(CO)
-	);
-	SB_LUT4 #(
-		.LUT_INIT(16'b 0110_1001_1001_0110)
-	) adder (
-		.I0(1'b0),
-		.I1(A),
-		.I2(B),
-		.I3(1'b0),
-		.O(O)
-	);
-endmodule
-EOT
-
-ice40_wrapcarry
-select -assert-count 1 t:$__ICE40_CARRY_WRAPPER
-
-design -reset
-read_verilog <<EOT
-module top(input A, B, CI, output O, CO);
-    (* foo = "bar", answer = 42, keep=0 *)
-	SB_CARRY carry (
-		.I0(A),
-		.I1(B),
-		.CI(CI),
-		.CO(CO)
-	);
-    (* keep, blah="blah", answer = 43 *)
-	SB_LUT4 #(
-		.LUT_INIT(16'b 0110_1001_1001_0110)
-	) adder (
-		.I0(1'b0),
-		.I1(A),
-		.I2(B),
-		.I3(1'b0),
-		.O(O)
-	);
-endmodule
-EOT
-
-ice40_wrapcarry
-select -assert-count 1 t:$__ICE40_CARRY_WRAPPER
-select -assert-count 0 t:* t:$__ICE40_CARRY_WRAPPER %d
-select -assert-count 1 a:foo=bar a:answer=42 %i a:keep=1 %i a:blah=blah %i
-techmap -map +/ice40/cells_map.v
-#TODO: Check unwrapped attributes
-- 
cgit v1.2.3


From eff858cd33403a13736ac74cce6964648306e594 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 9 Dec 2019 14:20:35 -0800
Subject: unmap $__ICE40_CARRY_WRAPPER in test

---
 tests/arch/ice40/ice40_opt.ys | 22 +++++++++++++++++++++-
 1 file changed, 21 insertions(+), 1 deletion(-)

(limited to 'tests/arch/ice40')

diff --git a/tests/arch/ice40/ice40_opt.ys b/tests/arch/ice40/ice40_opt.ys
index 860e2e211..5186d4800 100644
--- a/tests/arch/ice40/ice40_opt.ys
+++ b/tests/arch/ice40/ice40_opt.ys
@@ -1,3 +1,23 @@
+read_verilog -icells -formal <<EOT
+module \$__ICE40_CARRY_WRAPPER (output CO, O, input A, B, CI, I0, I3);
+  parameter LUT = 0;
+  SB_CARRY carry (
+    .I0(A),
+    .I1(B),
+    .CI(CI),
+    .CO(CO)
+  );
+  \$lut #(
+    .WIDTH(4),
+    .LUT(LUT)
+  ) lut (
+    .A({I0,A,B,I3}),
+    .Y(O)
+  );
+endmodule
+EOT
+design -stash unmap
+
 read_verilog -icells -formal <<EOT
 module top(input CI, I0, output [1:0] CO, output O);
     wire A = 1'b0, B = 1'b0;
@@ -20,7 +40,7 @@ module top(input CI, I0, output [1:0] CO, output O);
 endmodule
 EOT
 
-equiv_opt -assert -map +/ice40/cells_map.v -map +/ice40/cells_sim.v ice40_opt
+equiv_opt -assert -map %unmap -map +/ice40/cells_sim.v ice40_opt
 design -load postopt
 select -assert-count 1 t:*
 select -assert-count 1 t:$lut
-- 
cgit v1.2.3


From caab66111e2b5052bd26c8fd64b1324e7e4a4106 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 12 Dec 2019 17:44:37 -0800
Subject: Rename memory tests to lutram, add more xilinx tests

---
 tests/arch/ice40/lutram.ys | 15 +++++++++++++++
 tests/arch/ice40/memory.ys | 15 ---------------
 2 files changed, 15 insertions(+), 15 deletions(-)
 create mode 100644 tests/arch/ice40/lutram.ys
 delete mode 100644 tests/arch/ice40/memory.ys

(limited to 'tests/arch/ice40')

diff --git a/tests/arch/ice40/lutram.ys b/tests/arch/ice40/lutram.ys
new file mode 100644
index 000000000..1ba40f8ec
--- /dev/null
+++ b/tests/arch/ice40/lutram.ys
@@ -0,0 +1,15 @@
+read_verilog ../common/lutram.v
+hierarchy -top lutram_1w1r
+proc
+memory -nomap
+equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40
+memory
+opt -full
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
+
+design -load postopt
+cd lutram_1w1r
+select -assert-count 1 t:SB_RAM40_4K
+select -assert-none t:SB_RAM40_4K %% t:* %D
diff --git a/tests/arch/ice40/memory.ys b/tests/arch/ice40/memory.ys
deleted file mode 100644
index c356e67fb..000000000
--- a/tests/arch/ice40/memory.ys
+++ /dev/null
@@ -1,15 +0,0 @@
-read_verilog ../common/memory.v
-hierarchy -top top
-proc
-memory -nomap
-equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40
-memory
-opt -full
-
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
-
-design -load postopt
-cd top
-select -assert-count 1 t:SB_RAM40_4K
-select -assert-none t:SB_RAM40_4K %% t:* %D
-- 
cgit v1.2.3


From d45869855c6fc86dc6a0225018a8e383866dacb4 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 27 Dec 2019 16:44:57 -0800
Subject: Add #1598 testcase

---
 tests/arch/ice40/bug1598.ys | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)
 create mode 100644 tests/arch/ice40/bug1598.ys

(limited to 'tests/arch/ice40')

diff --git a/tests/arch/ice40/bug1598.ys b/tests/arch/ice40/bug1598.ys
new file mode 100644
index 000000000..8438cb979
--- /dev/null
+++ b/tests/arch/ice40/bug1598.ys
@@ -0,0 +1,16 @@
+read_verilog <<EOT
+module led_blink (
+        input clk,
+        output ledc
+    );
+ 
+    reg [6:0] led_counter = 0;
+    always @( posedge clk ) begin
+            led_counter <= led_counter + 1;
+    end
+    assign ledc = !led_counter[ 6:3 ];
+ 
+endmodule
+EOT
+proc
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -abc9
-- 
cgit v1.2.3


From c082329af33cd428f53f5afbcb51fab8de545090 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 31 Dec 2019 18:39:32 -0800
Subject: Call equiv_opt with -multiclock and -assert

---
 tests/arch/ice40/counter.ys | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'tests/arch/ice40')

diff --git a/tests/arch/ice40/counter.ys b/tests/arch/ice40/counter.ys
index f112eb97d..7bbc4f2c3 100644
--- a/tests/arch/ice40/counter.ys
+++ b/tests/arch/ice40/counter.ys
@@ -2,7 +2,7 @@ read_verilog ../common/counter.v
 hierarchy -top top
 proc
 flatten
-equiv_opt -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+equiv_opt -assert -multiclock -map +/ice40/cells_sim.v synth_ice40 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 6 t:SB_CARRY
-- 
cgit v1.2.3


From a59016b146e91311324bc87f9a9437d7ff31d9f2 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 31 Dec 2019 18:40:11 -0800
Subject: Fix warnings

---
 tests/arch/ice40/mul.ys | 2 +-
 tests/arch/ice40/rom.v  | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

(limited to 'tests/arch/ice40')

diff --git a/tests/arch/ice40/mul.ys b/tests/arch/ice40/mul.ys
index 9891b77d6..b8c3eb941 100644
--- a/tests/arch/ice40/mul.ys
+++ b/tests/arch/ice40/mul.ys
@@ -1,6 +1,6 @@
 read_verilog ../common/mul.v
 hierarchy -top top
-equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check
+equiv_opt -assert -multiclock -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 1 t:SB_MAC16
diff --git a/tests/arch/ice40/rom.v b/tests/arch/ice40/rom.v
index 0a0f41f37..c4c677c1e 100644
--- a/tests/arch/ice40/rom.v
+++ b/tests/arch/ice40/rom.v
@@ -2,7 +2,7 @@
 Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 74].
 */
 module top(data, addr);
-output [3:0] data;
+output reg [3:0] data;
 input [4:0] addr;
 always @(addr) begin
 case (addr)
-- 
cgit v1.2.3


From 52fe1e0c44d572b8e1f8881dc0a1e91f7fa93c9c Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 1 Jan 2020 09:05:46 -0800
Subject: Revert insertion of 'reg', leave note behind

---
 tests/arch/ice40/rom.v | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'tests/arch/ice40')

diff --git a/tests/arch/ice40/rom.v b/tests/arch/ice40/rom.v
index c4c677c1e..71459fe38 100644
--- a/tests/arch/ice40/rom.v
+++ b/tests/arch/ice40/rom.v
@@ -2,7 +2,8 @@
 Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 74].
 */
 module top(data, addr);
-output reg [3:0] data;
+output [3:0] data; // Note: this prompts a Yosys warning, but
+                   //       vendor doc does not contain 'reg'
 input [4:0] addr;
 always @(addr) begin
 case (addr)
-- 
cgit v1.2.3


From ae619ba87a58ee530549206eee7f5ea1ad8e1072 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Sun, 12 Jan 2020 15:21:26 -0800
Subject: Add #1626 testcase

---
 tests/arch/ice40/bug1626.ys | 217 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 217 insertions(+)
 create mode 100644 tests/arch/ice40/bug1626.ys

(limited to 'tests/arch/ice40')

diff --git a/tests/arch/ice40/bug1626.ys b/tests/arch/ice40/bug1626.ys
new file mode 100644
index 000000000..27b6fb5e8
--- /dev/null
+++ b/tests/arch/ice40/bug1626.ys
@@ -0,0 +1,217 @@
+read_ilang <<EOT
+# Generated by Yosys 0.9+1706 (git sha1 58ab9f60, clang 6.0.0-1ubuntu2 -fPIC -Os)
+autoidx 2815
+attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:9"
+attribute \cells_not_processed 1
+attribute \dynports 1
+module \ahb_async_sram_halfwidth
+  parameter \DEPTH
+  parameter \W_ADDR
+  parameter \W_BYTEADDR
+  parameter \W_DATA
+  parameter \W_SRAM_ADDR
+  parameter \W_SRAM_DATA
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:71"
+  wire $0\addr_lsb[0:0]
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:71"
+  wire $0\hready_r[0:0]
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:71"
+  wire $0\long_dphase[0:0]
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:71"
+  wire width 16 $0\rdata_buf[15:0]
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:71"
+  wire $0\read_dph[0:0]
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:71"
+  wire $0\write_dph[0:0]
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:63"
+  wire width 32 $add$../hdl/mem/ahb_async_sram_halfwidth.v:63$2433_Y
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:62"
+  wire width 16 $and$../hdl/mem/ahb_async_sram_halfwidth.v:62$2431_Y
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:56"
+  wire $eq$../hdl/mem/ahb_async_sram_halfwidth.v:56$2424_Y
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112"
+  wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2450_Y
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112"
+  wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2451_Y
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112"
+  wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2452_Y
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112"
+  wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2453_Y
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112"
+  wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2454_Y
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112"
+  wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2455_Y
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112"
+  wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2456_Y
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112"
+  wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2457_Y
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112"
+  wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2458_Y
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112"
+  wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2459_Y
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:118"
+  wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:118$2444_Y
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:133"
+  wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:133$2449_Y
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:140"
+  wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:140$2461_Y
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:140"
+  wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:140$2463_Y
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:58"
+  wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:58$2425_Y
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:59"
+  wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:59$2426_Y
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:59"
+  wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:59$2427_Y
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:59"
+  wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:59$2429_Y
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:91"
+  wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:91$2441_Y
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:104"
+  wire $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:104$2442_Y
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:118"
+  wire $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:118$2443_Y
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:125"
+  wire $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:125$2446_Y
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:132"
+  wire $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:132$2447_Y
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:59"
+  wire $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:59$2428_Y
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:72"
+  wire $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:72$2437_Y
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:81"
+  wire $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:81$2438_Y
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:83"
+  wire $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:83$2439_Y
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:91"
+  wire $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:91$2440_Y
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:118"
+  wire $logic_or$../hdl/mem/ahb_async_sram_halfwidth.v:118$2445_Y
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:132"
+  wire $logic_or$../hdl/mem/ahb_async_sram_halfwidth.v:132$2448_Y
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:59"
+  wire $logic_or$../hdl/mem/ahb_async_sram_halfwidth.v:59$2430_Y
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:139"
+  wire width 2 $not$../hdl/mem/ahb_async_sram_halfwidth.v:139$2460_Y
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:139"
+  wire width 2 $not$../hdl/mem/ahb_async_sram_halfwidth.v:139$2462_Y
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:54"
+  wire width 2 $not$../hdl/mem/ahb_async_sram_halfwidth.v:54$2421_Y
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:63"
+  wire width 16 $shiftx$../hdl/mem/ahb_async_sram_halfwidth.v:63$2434_Y
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:54"
+  wire width 8 $shl$../hdl/mem/ahb_async_sram_halfwidth.v:54$2419_Y
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:54"
+  wire width 2 $shl$../hdl/mem/ahb_async_sram_halfwidth.v:54$2420_Y
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:55"
+  wire width 2 $shl$../hdl/mem/ahb_async_sram_halfwidth.v:55$2422_Y
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:56"
+  wire width 32 $shl$../hdl/mem/ahb_async_sram_halfwidth.v:56$2423_Y
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:63"
+  wire width 32 $ternary$../hdl/mem/ahb_async_sram_halfwidth.v:63$2432_Y
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:65"
+  wire width 16 $ternary$../hdl/mem/ahb_async_sram_halfwidth.v:65$2435_Y
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:50"
+  wire \addr_lsb
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:24"
+  wire width 32 \ahbls_haddr
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:28"
+  wire width 3 \ahbls_hburst
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:30"
+  wire \ahbls_hmastlock
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:29"
+  wire width 4 \ahbls_hprot
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:32"
+  wire width 32 \ahbls_hrdata
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:22"
+  wire \ahbls_hready
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:21"
+  wire \ahbls_hready_resp
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:23"
+  wire \ahbls_hresp
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:27"
+  wire width 3 \ahbls_hsize
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:26"
+  wire width 2 \ahbls_htrans
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:31"
+  wire width 32 \ahbls_hwdata
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:25"
+  wire \ahbls_hwrite
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:56"
+  wire \aphase_full_width
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:55"
+  wire width 2 \bytemask
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:54"
+  wire width 2 \bytemask_noshift
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:17"
+  wire \clk
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:46"
+  wire \hready_r
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:47"
+  wire \long_dphase
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:64"
+  wire width 16 \rdata_buf
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:49"
+  wire \read_dph
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:18"
+  wire \rst_n
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:34"
+  wire width 11 \sram_addr
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:39"
+  wire width 2 \sram_byte_n
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:36"
+  wire \sram_ce_n
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:35"
+  wire width 16 \sram_dq
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:38"
+  wire \sram_oe_n
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:61"
+  wire width 16 \sram_q
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:62"
+  wire width 16 \sram_rdata
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:63"
+  wire width 16 \sram_wdata
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:37"
+  wire \sram_we_n
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:58"
+  wire \we_next
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:48"
+  wire \write_dph
+  attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:71"
+  process $proc$../hdl/mem/ahb_async_sram_halfwidth.v:71$2436
+    attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:72"
+    switch $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:72$2437_Y
+      case 1'1
+      case 
+        attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:78"
+        switch \ahbls_hready
+          case 1'1
+            attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:79"
+            switch \ahbls_htrans [1]
+              case 1'1
+              case 
+            end
+          case 
+            attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:91"
+            switch $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:91$2441_Y
+              case 1'1
+              case 
+            end
+        end
+    end
+    sync posedge \clk
+    sync negedge \rst_n
+  end
+  connect \ahbls_hresp 1'0
+  connect \bytemask_noshift $not$../hdl/mem/ahb_async_sram_halfwidth.v:54$2421_Y
+  connect \bytemask $shl$../hdl/mem/ahb_async_sram_halfwidth.v:55$2422_Y
+  connect \aphase_full_width $eq$../hdl/mem/ahb_async_sram_halfwidth.v:56$2424_Y
+  connect \we_next $logic_or$../hdl/mem/ahb_async_sram_halfwidth.v:59$2430_Y
+  connect \sram_rdata $and$../hdl/mem/ahb_async_sram_halfwidth.v:62$2431_Y
+  connect \sram_wdata $shiftx$../hdl/mem/ahb_async_sram_halfwidth.v:63$2434_Y
+  connect \ahbls_hrdata { \sram_rdata $ternary$../hdl/mem/ahb_async_sram_halfwidth.v:65$2435_Y }
+  connect \ahbls_hready_resp \hready_r
+end
+EOT
+
+synth_ice40 -abc2 -abc9
-- 
cgit v1.2.3


From ad6c49fff12e27d99c1fc15850857e5129dd76ee Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 17 Jan 2020 15:38:26 -0800
Subject: ice40_dsp: add test

---
 tests/arch/ice40/ice40_dsp.ys | 11 +++++++++++
 1 file changed, 11 insertions(+)
 create mode 100644 tests/arch/ice40/ice40_dsp.ys

(limited to 'tests/arch/ice40')

diff --git a/tests/arch/ice40/ice40_dsp.ys b/tests/arch/ice40/ice40_dsp.ys
new file mode 100644
index 000000000..250273859
--- /dev/null
+++ b/tests/arch/ice40/ice40_dsp.ys
@@ -0,0 +1,11 @@
+read_verilog <<EOT
+module top(input [15:0] a, b, output [31:0] o1, o2, o5);
+SB_MAC16 m1 (.A(a), .B(16'd1234), .O(o1));
+assign o2 = a * 16'd0;
+wire [31:0] o3, o4;
+SB_MAC16 m2 (.A(a), .B(b), .O(o3));
+assign o4 = a * b;
+SB_MAC16 m3 (.A(a), .B(b), .O(o5));
+endmodule
+EOT
+ice40_dsp
-- 
cgit v1.2.3


From 5507c328fff7b534abcba4186b2e5b1e26c4ad5e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 17 Jan 2020 15:57:52 -0800
Subject: Add #1644 testcase

---
 tests/arch/ice40/bug1644.il.gz | Bin 0 -> 25669 bytes
 tests/arch/ice40/bug1644.ys    |   2 ++
 2 files changed, 2 insertions(+)
 create mode 100644 tests/arch/ice40/bug1644.il.gz
 create mode 100644 tests/arch/ice40/bug1644.ys

(limited to 'tests/arch/ice40')

diff --git a/tests/arch/ice40/bug1644.il.gz b/tests/arch/ice40/bug1644.il.gz
new file mode 100644
index 000000000..363c510ef
Binary files /dev/null and b/tests/arch/ice40/bug1644.il.gz differ
diff --git a/tests/arch/ice40/bug1644.ys b/tests/arch/ice40/bug1644.ys
new file mode 100644
index 000000000..5950f0e3c
--- /dev/null
+++ b/tests/arch/ice40/bug1644.ys
@@ -0,0 +1,2 @@
+read_ilang bug1644.il.gz
+synth_ice40 -top top -dsp -json adc_dac_pass_through.json -run :map_bram
-- 
cgit v1.2.3


From b1787615514f84c83c27d08011427e90c9bd0f4a Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 24 Jan 2020 11:59:48 -0800
Subject: ice40: reduce ABC9 internal fanout warnings with a param for CI->I3

---
 tests/arch/ice40/ice40_opt.ys | 27 ++++-----------------------
 1 file changed, 4 insertions(+), 23 deletions(-)

(limited to 'tests/arch/ice40')

diff --git a/tests/arch/ice40/ice40_opt.ys b/tests/arch/ice40/ice40_opt.ys
index 5186d4800..011d98fef 100644
--- a/tests/arch/ice40/ice40_opt.ys
+++ b/tests/arch/ice40/ice40_opt.ys
@@ -1,23 +1,3 @@
-read_verilog -icells -formal <<EOT
-module \$__ICE40_CARRY_WRAPPER (output CO, O, input A, B, CI, I0, I3);
-  parameter LUT = 0;
-  SB_CARRY carry (
-    .I0(A),
-    .I1(B),
-    .CI(CI),
-    .CO(CO)
-  );
-  \$lut #(
-    .WIDTH(4),
-    .LUT(LUT)
-  ) lut (
-    .A({I0,A,B,I3}),
-    .Y(O)
-  );
-endmodule
-EOT
-design -stash unmap
-
 read_verilog -icells -formal <<EOT
 module top(input CI, I0, output [1:0] CO, output O);
     wire A = 1'b0, B = 1'b0;
@@ -26,13 +6,14 @@ module top(input CI, I0, output [1:0] CO, output O);
 		//    A[1]: 1100 1100 1100 1100
 		//    A[2]: 1111 0000 1111 0000
 		//    A[3]: 1111 1111 0000 0000
-		.LUT(~16'b 0110_1001_1001_0110)
+		.LUT(~16'b 0110_1001_1001_0110),
+		.I3_IS_CI(1'b1)
 	) u0 (
 		.A(A),
 		.B(B),
 		.CI(CI),
 		.I0(I0),
-		.I3(CI),
+		.I3(1'bx),
 		.CO(CO[0]),
 		.O(O)
 	);
@@ -40,7 +21,7 @@ module top(input CI, I0, output [1:0] CO, output O);
 endmodule
 EOT
 
-equiv_opt -assert -map %unmap -map +/ice40/cells_sim.v ice40_opt
+equiv_opt -assert -map +/ice40/abc9_model.v -map +/ice40/cells_sim.v ice40_opt
 design -load postopt
 select -assert-count 1 t:*
 select -assert-count 1 t:$lut
-- 
cgit v1.2.3


From cfb0366a18b0f3cab254636fdf534a3de76af8d5 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 27 Jan 2020 13:56:16 -0800
Subject: Import tests from #1628

---
 tests/arch/ice40/bug1597.ys   | 72 +++++++++++++++++++++++++++++++++++++++++++
 tests/arch/ice40/ice40_opt.ys | 30 ++++++++++++++++++
 2 files changed, 102 insertions(+)
 create mode 100644 tests/arch/ice40/bug1597.ys

(limited to 'tests/arch/ice40')

diff --git a/tests/arch/ice40/bug1597.ys b/tests/arch/ice40/bug1597.ys
new file mode 100644
index 000000000..b7983cfa4
--- /dev/null
+++ b/tests/arch/ice40/bug1597.ys
@@ -0,0 +1,72 @@
+read_verilog <<EOT
+module top (
+    input CLK, PIN_1, PIN_2, PIN_3, PIN_4, PIN_5,
+        PIN_6, PIN_7, PIN_8, PIN_9, PIN_10, PIN_11, PIN_12, PIN_13, PIN_25,
+    output USBPU, PIN_14, PIN_15, PIN_16, PIN_17, PIN_18,
+        PIN_19, PIN_20, PIN_21, PIN_22, PIN_23, PIN_24,
+);
+    assign USBPU = 0;
+
+    wire[5:0] parOut;
+    wire[5:0] chrg;
+
+    assign PIN_14 = parOut[0];
+    assign PIN_15 = parOut[1];
+    assign PIN_16 = parOut[2];
+    assign PIN_17 = parOut[3];
+    assign PIN_18 = parOut[4];
+    assign PIN_19 = parOut[5];
+    assign chrg[0] = PIN_3;
+    assign chrg[1] = PIN_4;
+    assign chrg[2] = PIN_5;
+    assign chrg[3] = PIN_6;
+    assign chrg[4] = PIN_7;
+    assign chrg[5] = PIN_8;
+
+    SSCounter6o sc6(PIN_1, CLK, PIN_2, PIN_9, chrg, parOut);
+
+endmodule
+
+module SSCounter6 (input wire rst, clk, adv, jmp, input wire [5:0] in, output reg[5:0] out);
+    always @(posedge clk, posedge rst)
+        if (rst) out <= 0;
+        else if (adv || jmp) out <= jmp ? in : out + 1;
+endmodule
+
+// Optimized 6 bit counter, it should takes 7 cells.
+/* b[5:1]                       /* b[0]
+1010101010101010 in             1010101010101010 in
+1100110011001100 jmp            1100110011001100 jmp
+1111000011110000 loop           1111000011110000 loop
+1111111100000000 carry          1111111100000000 -
+----------------------          ----------------------
+1000101110111000 out            1000101110001011 out
+   8   B   B   8                   8   B   8   B
+*/
+module SSCounter6o (input wire rst, clk, adv, jmp, input wire [5:0] in, output wire[5:0] out);
+    wire[4:0] co;
+    wire[5:0] lo;
+    wire ien;
+    SB_LUT4 #(.LUT_INIT(16'hFFF0)) lien (ien, 0, 0, adv, jmp);
+    SB_CARRY c0 (co[0], jmp, out[0], 1),
+             c1 (co[1], jmp, out[1], co[0]),
+             c2 (co[2], jmp, out[2], co[1]),
+             c3 (co[3], jmp, out[3], co[2]),
+             c4 (co[4], jmp, out[4], co[3]);
+    SB_DFFER d0 (out[0], clk, ien, rst, lo[0]),
+             d1 (out[1], clk, ien, rst, lo[1]),
+             d2 (out[2], clk, ien, rst, lo[2]),
+             d3 (out[3], clk, ien, rst, lo[3]),
+             d4 (out[4], clk, ien, rst, lo[4]),
+             d5 (out[5], clk, ien, rst, lo[5]);
+    SB_LUT4 #(.LUT_INIT(16'h8B8B)) l0 (lo[0], in[0], jmp, out[0], 0);
+    SB_LUT4 #(.LUT_INIT(16'h8BB8)) l1 (lo[1], in[1], jmp, out[1], co[0]);
+    SB_LUT4 #(.LUT_INIT(16'h8BB8)) l2 (lo[2], in[2], jmp, out[2], co[1]);
+    SB_LUT4 #(.LUT_INIT(16'h8BB8)) l3 (lo[3], in[3], jmp, out[3], co[2]);
+    SB_LUT4 #(.LUT_INIT(16'h8BB8)) l4 (lo[4], in[4], jmp, out[4], co[3]);
+    SB_LUT4 #(.LUT_INIT(16'h8BB8)) l5 (lo[5], in[5], jmp, out[5], co[4]);
+endmodule
+EOT
+hierarchy -top top
+flatten
+equiv_opt -multiclock -map +/ice40/cells_sim.v synth_ice40
diff --git a/tests/arch/ice40/ice40_opt.ys b/tests/arch/ice40/ice40_opt.ys
index 011d98fef..71b68431e 100644
--- a/tests/arch/ice40/ice40_opt.ys
+++ b/tests/arch/ice40/ice40_opt.ys
@@ -86,3 +86,33 @@ select -assert-count 1 t:SB_LUT4
 select -assert-count 1 t:SB_CARRY
 select -assert-count 1 t:SB_CARRY a:keep %i
 select -assert-count 1 t:SB_CARRY c:carry %i
+
+
+design -reset
+read_verilog -icells <<EOT
+module top(input I3, I2, I1, I0, output O, O2);
+	SB_LUT4 #(
+		.LUT_INIT(8'b 1001_0110)
+	) u0 (
+		.I0(I0),
+		.I1(I1),
+		.I2(I2),
+		.I3(),
+		.O(O)
+	);
+	wire CO;
+	\$__ICE40_CARRY_WRAPPER #(
+		.LUT(~8'b 1001_0110),
+		.I3_IS_CI(1'b0)
+	) u1 (
+		.A(1'b0),
+		.B(1'b0),
+		.CI(1'b0),
+		.I0(),
+		.I3(),
+		.CO(CO),
+		.O(O2)
+	);
+endmodule
+EOT
+ice40_opt
-- 
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