From fc28bf55aa65ce86b3e340333751b466935f8b5f Mon Sep 17 00:00:00 2001 From: whitequark Date: Wed, 1 Jan 2020 06:18:53 +0000 Subject: ice40: add support for both 1364.1 and LSE RAM/ROM attributes. This commit tries to carefully follow the documented behavior of LSE and Synplify. It will use `syn_ramstyle` attribute if there are any write ports, and `syn_romstyle` attribute otherwise. * LSE supports both `syn_ramstyle` and `syn_romstyle`. * Synplify only supports `syn_ramstyle`, with same values as LSE. * Synplify also supports `syn_rw_conflict_logic`, which is not documented as supported for LSE. Limitations of the Yosys implementation: * LSE/Synplify appear to interpret attribute values insensitive to case. There is currently no way to do this in Yosys (attrmap can only change case of attribute names). * LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"` syntax to turn off insertion of transparency logic. There is currently no way to support multiple valued attributes in memory_bram. It is also not clear if that is a good idea, since it can cause sim/synth mismatches. * LSE/Synplify/1364.1 support block ROM inference from full case statements. Yosys does not currently perform this transformation. * LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes from the module to the inner memories. There is currently no way to do this in Yosys (attrmvcp only works on cells and wires). --- tests/arch/ice40/memories.ys | 126 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 126 insertions(+) create mode 100644 tests/arch/ice40/memories.ys (limited to 'tests/arch/ice40/memories.ys') diff --git a/tests/arch/ice40/memories.ys b/tests/arch/ice40/memories.ys new file mode 100644 index 000000000..83386f0ec --- /dev/null +++ b/tests/arch/ice40/memories.ys @@ -0,0 +1,126 @@ +# RAM bits <= 4K; Data width <= 16; Address width <= 11: -> SB_RAM40_4K + +design -reset; read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 11 -set DATA_WIDTH 2 sync_ram_sdp +synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp +select -assert-count 1 t:SB_RAM40_4K + +design -reset; read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 4 sync_ram_sdp +synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp +select -assert-count 1 t:SB_RAM40_4K + +design -reset; read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 8 sync_ram_sdp +synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp +select -assert-count 1 t:SB_RAM40_4K + +design -reset; read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 16 sync_ram_sdp +synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp +select -assert-count 1 t:SB_RAM40_4K + +## With parameters + +design -reset; read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp +synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp +select -assert-count 0 t:SB_RAM40_4K # too inefficient +select -assert-min 1 t:SB_DFFE + +design -reset; read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp +setattr -set syn_ramstyle "block_ram" m:memory +synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp +select -assert-count 1 t:SB_RAM40_4K + +design -reset; read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp +setattr -set ram_block 1 m:memory +synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp +select -assert-count 1 t:SB_RAM40_4K + +design -reset; read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp +setattr -set logic_block 1 m:memory +synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp +select -assert-count 0 t:SB_RAM40_4K # requested FFRAM explicitly +select -assert-min 1 t:SB_DFFE + +design -reset; read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp +setattr -set syn_romstyle "ebr" m:memory +synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp +select -assert-count 0 t:SB_RAM40_4K # requested BROM but this is a RAM +select -assert-min 1 t:SB_DFFE + +design -reset; read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp +setattr -set rom_block 1 m:memory +synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp +select -assert-count 0 t:SB_RAM40_4K # requested BROM but this is a RAM +select -assert-min 1 t:SB_DFFE + +# ROM bits <= 4K; Data width <= 16; Address width <= 11: -> SB_RAM40_4K + +design -reset; read_verilog ../common/blockrom.v +chparam -set ADDRESS_WIDTH 11 -set DATA_WIDTH 2 sync_rom +synth_ice40 -top sync_rom; cd sync_rom +select -assert-count 1 t:SB_RAM40_4K + +design -reset; read_verilog ../common/blockrom.v +chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 4 sync_rom +synth_ice40 -top sync_rom; cd sync_rom +select -assert-count 1 t:SB_RAM40_4K + +design -reset; read_verilog ../common/blockrom.v +chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 8 sync_rom +synth_ice40 -top sync_rom; cd sync_rom +select -assert-count 1 t:SB_RAM40_4K + +design -reset; read_verilog ../common/blockrom.v +chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 16 sync_rom +synth_ice40 -top sync_rom; cd sync_rom +select -assert-count 1 t:SB_RAM40_4K + +## With parameters + +design -reset; read_verilog ../common/blockrom.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom +write_ilang +synth_ice40 -top sync_rom; cd sync_rom +select -assert-count 0 t:SB_RAM40_4K # too inefficient +select -assert-min 1 t:SB_LUT4 + +design -reset; read_verilog ../common/blockrom.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom +setattr -set syn_romstyle "ebr" m:memory +synth_ice40 -top sync_rom; cd sync_rom +select -assert-count 1 t:SB_RAM40_4K + +design -reset; read_verilog ../common/blockrom.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom +setattr -set rom_block 1 m:memory +synth_ice40 -top sync_rom; cd sync_rom +select -assert-count 1 t:SB_RAM40_4K + +design -reset; read_verilog ../common/blockrom.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom +setattr -set logic_block 1 m:memory +synth_ice40 -top sync_rom; cd sync_rom +select -assert-count 0 t:SB_RAM40_4K # requested LUTROM explicitly +select -assert-min 1 t:SB_LUT4 + +design -reset; read_verilog ../common/blockrom.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom +setattr -set syn_ramstyle "block_ram" m:memory +synth_ice40 -top sync_rom; cd sync_rom +select -assert-count 0 t:SB_RAM40_4K # requested BRAM but this is a ROM +select -assert-min 1 t:SB_LUT4 + +design -reset; read_verilog ../common/blockrom.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom +setattr -set ram_block 1 m:memory +synth_ice40 -top sync_rom; cd sync_rom +select -assert-count 0 t:SB_RAM40_4K # requested BRAM but this is a ROM +select -assert-min 1 t:SB_LUT4 -- cgit v1.2.3 From 3f4460a1869ccfd6225379d18ade195f165841a4 Mon Sep 17 00:00:00 2001 From: whitequark Date: Wed, 1 Jan 2020 07:20:06 +0000 Subject: ice40: match memory inference attribute values case insensitive. LSE/Synplify use case insensitive matching. --- tests/arch/ice40/memories.ys | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'tests/arch/ice40/memories.ys') diff --git a/tests/arch/ice40/memories.ys b/tests/arch/ice40/memories.ys index 83386f0ec..43bcf2452 100644 --- a/tests/arch/ice40/memories.ys +++ b/tests/arch/ice40/memories.ys @@ -34,6 +34,12 @@ setattr -set syn_ramstyle "block_ram" m:memory synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp select -assert-count 1 t:SB_RAM40_4K +design -reset; read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp +setattr -set syn_ramstyle "Block_RAM" m:memory +synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp +select -assert-count 1 t:SB_RAM40_4K # any case works + design -reset; read_verilog ../common/blockram.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp setattr -set ram_block 1 m:memory -- cgit v1.2.3 From 081d9318bcf1ee13549ddcb0983cba5f00b4272c Mon Sep 17 00:00:00 2001 From: whitequark Date: Wed, 1 Jan 2020 08:27:47 +0000 Subject: ecp5: add support for both 1364.1 and LSE RAM/ROM attributes. This commit tries to carefully follow the documented behavior of LSE and Synplify. It will use `syn_ramstyle` attribute if there are any write ports, and `syn_romstyle` attribute otherwise. * LSE supports both `syn_ramstyle` and `syn_romstyle`. * Synplify only supports `syn_ramstyle`, with same values as LSE. * Synplify also supports `syn_rw_conflict_logic`, which is not documented as supported for LSE. Limitations of the Yosys implementation: * LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"` syntax to turn off insertion of transparency logic. There is currently no way to support multiple valued attributes in memory_bram. It is also not clear if that is a good idea, since it can cause sim/synth mismatches. * LSE/Synplify/1364.1 support block ROM inference from full case statements. Yosys does not currently perform this transformation. * LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes from the module to the inner memories. There is currently no way to do this in Yosys (attrmvcp only works on cells and wires). --- tests/arch/ice40/memories.ys | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'tests/arch/ice40/memories.ys') diff --git a/tests/arch/ice40/memories.ys b/tests/arch/ice40/memories.ys index 43bcf2452..86a60b258 100644 --- a/tests/arch/ice40/memories.ys +++ b/tests/arch/ice40/memories.ys @@ -1,3 +1,4 @@ +# ================================ RAM ================================ # RAM bits <= 4K; Data width <= 16; Address width <= 11: -> SB_RAM40_4K design -reset; read_verilog ../common/blockram.v @@ -46,6 +47,13 @@ setattr -set ram_block 1 m:memory synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp select -assert-count 1 t:SB_RAM40_4K +design -reset; read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp +setattr -set syn_ramstyle "registers" m:memory +synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp +select -assert-count 0 t:SB_RAM40_4K # requested FFRAM explicitly +select -assert-min 1 t:SB_DFFE + design -reset; read_verilog ../common/blockram.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp setattr -set logic_block 1 m:memory @@ -67,6 +75,7 @@ synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp select -assert-count 0 t:SB_RAM40_4K # requested BROM but this is a RAM select -assert-min 1 t:SB_DFFE +# ================================ ROM ================================ # ROM bits <= 4K; Data width <= 16; Address width <= 11: -> SB_RAM40_4K design -reset; read_verilog ../common/blockrom.v @@ -110,6 +119,13 @@ setattr -set rom_block 1 m:memory synth_ice40 -top sync_rom; cd sync_rom select -assert-count 1 t:SB_RAM40_4K +design -reset; read_verilog ../common/blockrom.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom +setattr -set syn_romstyle "logic" m:memory +synth_ice40 -top sync_rom; cd sync_rom +select -assert-count 0 t:SB_RAM40_4K # requested LUTROM explicitly +select -assert-min 1 t:SB_LUT4 + design -reset; read_verilog ../common/blockrom.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom setattr -set logic_block 1 m:memory -- cgit v1.2.3 From ebee746ad21b9f1fe37f50908bdc5d219880e6bb Mon Sep 17 00:00:00 2001 From: whitequark Date: Wed, 1 Jan 2020 09:48:39 +0000 Subject: ice40: do not map FFRAM if explicitly requested otherwise. --- tests/arch/ice40/memories.ys | 36 ++++++++++++++++++++++++++++-------- 1 file changed, 28 insertions(+), 8 deletions(-) (limited to 'tests/arch/ice40/memories.ys') diff --git a/tests/arch/ice40/memories.ys b/tests/arch/ice40/memories.ys index 86a60b258..571edec1d 100644 --- a/tests/arch/ice40/memories.ys +++ b/tests/arch/ice40/memories.ys @@ -65,15 +65,25 @@ design -reset; read_verilog ../common/blockram.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp setattr -set syn_romstyle "ebr" m:memory synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp -select -assert-count 0 t:SB_RAM40_4K # requested BROM but this is a RAM -select -assert-min 1 t:SB_DFFE +select -assert-count 1 t:$mem # requested BROM but this is a RAM design -reset; read_verilog ../common/blockram.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp setattr -set rom_block 1 m:memory synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp -select -assert-count 0 t:SB_RAM40_4K # requested BROM but this is a RAM -select -assert-min 1 t:SB_DFFE +select -assert-count 1 t:$mem # requested BROM but this is a RAM + +design -reset; read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp +setattr -set syn_ramstyle "block_ram" m:memory +synth_ice40 -top sync_ram_sdp -nobram; cd sync_ram_sdp +select -assert-count 1 t:$mem # requested BRAM but BRAM is disabled + +design -reset; read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp +setattr -set ram_block 1 m:memory +synth_ice40 -top sync_ram_sdp -nobram; cd sync_ram_sdp +select -assert-count 1 t:$mem # requested BRAM but BRAM is disabled # ================================ ROM ================================ # ROM bits <= 4K; Data width <= 16; Address width <= 11: -> SB_RAM40_4K @@ -137,12 +147,22 @@ design -reset; read_verilog ../common/blockrom.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom setattr -set syn_ramstyle "block_ram" m:memory synth_ice40 -top sync_rom; cd sync_rom -select -assert-count 0 t:SB_RAM40_4K # requested BRAM but this is a ROM -select -assert-min 1 t:SB_LUT4 +select -assert-count 1 t:$mem # requested BRAM but this is a ROM design -reset; read_verilog ../common/blockrom.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom setattr -set ram_block 1 m:memory synth_ice40 -top sync_rom; cd sync_rom -select -assert-count 0 t:SB_RAM40_4K # requested BRAM but this is a ROM -select -assert-min 1 t:SB_LUT4 +select -assert-count 1 t:$mem # requested BRAM but this is a ROM + +design -reset; read_verilog ../common/blockrom.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom +setattr -set syn_romstyle "ebr" m:memory +synth_ice40 -top sync_rom -nobram; cd sync_rom +select -assert-count 1 t:$mem # requested BROM but BRAM is disabled + +design -reset; read_verilog ../common/blockrom.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom +setattr -set rom_block 1 m:memory +synth_ice40 -top sync_rom -nobram; cd sync_rom +select -assert-count 1 t:$mem # requested BROM but BRAM is disabled -- cgit v1.2.3