From 92e705cb51d8c8f6d9f1550ed103b677a2447c93 Mon Sep 17 00:00:00 2001 From: Claire Xenia Wolf Date: Wed, 9 Jun 2021 12:16:33 +0200 Subject: Fix files with CRLF line endings --- tests/arch/common/counter.v | 22 +++++----- tests/arch/common/fsm.v | 102 ++++++++++++++++++++++---------------------- tests/arch/common/shifter.v | 22 +++++----- 3 files changed, 73 insertions(+), 73 deletions(-) (limited to 'tests/arch/common') diff --git a/tests/arch/common/counter.v b/tests/arch/common/counter.v index 9746fd701..1e0a13dc9 100644 --- a/tests/arch/common/counter.v +++ b/tests/arch/common/counter.v @@ -1,11 +1,11 @@ -module top ( out, clk, reset ); - output [7:0] out; - input clk, reset; - reg [7:0] out; - - always @(posedge clk, posedge reset) - if (reset) - out <= 8'b0; - else - out <= out + 1; -endmodule +module top ( out, clk, reset ); + output [7:0] out; + input clk, reset; + reg [7:0] out; + + always @(posedge clk, posedge reset) + if (reset) + out <= 8'b0; + else + out <= out + 1; +endmodule diff --git a/tests/arch/common/fsm.v b/tests/arch/common/fsm.v index 9d3fbb64a..cf1c21a58 100644 --- a/tests/arch/common/fsm.v +++ b/tests/arch/common/fsm.v @@ -1,51 +1,51 @@ - module fsm ( clock, reset, req_0, req_1, gnt_0, gnt_1 ); - input clock,reset,req_0,req_1; - output gnt_0,gnt_1; - wire clock,reset,req_0,req_1; - reg gnt_0,gnt_1; - - parameter SIZE = 3; - parameter IDLE = 3'b001; - parameter GNT0 = 3'b010; - parameter GNT1 = 3'b100; - parameter GNT2 = 3'b101; - - reg [SIZE-1:0] state; - reg [SIZE-1:0] next_state; - - always @ (posedge clock) - begin : FSM - if (reset == 1'b1) begin - state <= #1 IDLE; - gnt_0 <= 0; - gnt_1 <= 0; - end - else - case(state) - IDLE : if (req_0 == 1'b1) begin - state <= #1 GNT0; - gnt_0 <= 1; - end else if (req_1 == 1'b1) begin - gnt_1 <= 1; - state <= #1 GNT0; - end else begin - state <= #1 IDLE; - end - GNT0 : if (req_0 == 1'b1) begin - state <= #1 GNT0; - end else begin - gnt_0 <= 0; - state <= #1 IDLE; - end - GNT1 : if (req_1 == 1'b1) begin - state <= #1 GNT2; - gnt_1 <= req_0; - end - GNT2 : if (req_0 == 1'b1) begin - state <= #1 GNT1; - gnt_1 <= req_1; - end - default : state <= #1 IDLE; - endcase - end -endmodule + module fsm ( clock, reset, req_0, req_1, gnt_0, gnt_1 ); + input clock,reset,req_0,req_1; + output gnt_0,gnt_1; + wire clock,reset,req_0,req_1; + reg gnt_0,gnt_1; + + parameter SIZE = 3; + parameter IDLE = 3'b001; + parameter GNT0 = 3'b010; + parameter GNT1 = 3'b100; + parameter GNT2 = 3'b101; + + reg [SIZE-1:0] state; + reg [SIZE-1:0] next_state; + + always @ (posedge clock) + begin : FSM + if (reset == 1'b1) begin + state <= #1 IDLE; + gnt_0 <= 0; + gnt_1 <= 0; + end + else + case(state) + IDLE : if (req_0 == 1'b1) begin + state <= #1 GNT0; + gnt_0 <= 1; + end else if (req_1 == 1'b1) begin + gnt_1 <= 1; + state <= #1 GNT0; + end else begin + state <= #1 IDLE; + end + GNT0 : if (req_0 == 1'b1) begin + state <= #1 GNT0; + end else begin + gnt_0 <= 0; + state <= #1 IDLE; + end + GNT1 : if (req_1 == 1'b1) begin + state <= #1 GNT2; + gnt_1 <= req_0; + end + GNT2 : if (req_0 == 1'b1) begin + state <= #1 GNT1; + gnt_1 <= req_1; + end + default : state <= #1 IDLE; + endcase + end +endmodule diff --git a/tests/arch/common/shifter.v b/tests/arch/common/shifter.v index cace3b588..3030608ab 100644 --- a/tests/arch/common/shifter.v +++ b/tests/arch/common/shifter.v @@ -1,11 +1,11 @@ -module top(out, clk, in); - output [7:0] out; - input signed clk, in; - reg signed [7:0] out = 0; - - always @(posedge clk) - begin - out <= out >> 1; - out[7] <= in; - end -endmodule +module top(out, clk, in); + output [7:0] out; + input signed clk, in; + reg signed [7:0] out = 0; + + always @(posedge clk) + begin + out <= out >> 1; + out[7] <= in; + end +endmodule -- cgit v1.2.3