From cf606998847a286a52f01d748372df396b59dd2b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= Date: Wed, 22 Jul 2020 13:34:11 +0200 Subject: synth_ice40: Use opt_dff. The main part is converting ice40_dsp to recognize the new FF types created in opt_dff instead of trying to recognize the mux patterns on its own. The fsm call has been moved upwards because the passes cannot deal with $dffe/$sdff*, and other optimizations don't help it much anyway. --- techlibs/ice40/Makefile.inc | 1 - techlibs/ice40/ice40_ffssr.cc | 131 ------------------------------------------ techlibs/ice40/ice40_opt.cc | 4 +- techlibs/ice40/synth_ice40.cc | 12 ++-- 4 files changed, 6 insertions(+), 142 deletions(-) delete mode 100644 techlibs/ice40/ice40_ffssr.cc (limited to 'techlibs') diff --git a/techlibs/ice40/Makefile.inc b/techlibs/ice40/Makefile.inc index 4f4faf6d5..8ce3cb024 100644 --- a/techlibs/ice40/Makefile.inc +++ b/techlibs/ice40/Makefile.inc @@ -1,7 +1,6 @@ OBJS += techlibs/ice40/synth_ice40.o OBJS += techlibs/ice40/ice40_braminit.o -OBJS += techlibs/ice40/ice40_ffssr.o OBJS += techlibs/ice40/ice40_opt.o GENFILES += techlibs/ice40/brams_init1.vh diff --git a/techlibs/ice40/ice40_ffssr.cc b/techlibs/ice40/ice40_ffssr.cc deleted file mode 100644 index 492029b77..000000000 --- a/techlibs/ice40/ice40_ffssr.cc +++ /dev/null @@ -1,131 +0,0 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2012 Clifford Wolf - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -#include "kernel/yosys.h" -#include "kernel/sigtools.h" - -USING_YOSYS_NAMESPACE -PRIVATE_NAMESPACE_BEGIN - -struct Ice40FfssrPass : public Pass { - Ice40FfssrPass() : Pass("ice40_ffssr", "iCE40: merge synchronous set/reset into FF cells") { } - void help() override - { - log("\n"); - log(" ice40_ffssr [options] [selection]\n"); - log("\n"); - log("Merge synchronous set/reset $_MUX_ cells into iCE40 FFs.\n"); - log("\n"); - } - void execute(std::vector args, RTLIL::Design *design) override - { - log_header(design, "Executing ICE40_FFSSR pass (merge synchronous set/reset into FF cells).\n"); - - size_t argidx; - for (argidx = 1; argidx < args.size(); argidx++) - { - // if (args[argidx] == "-singleton") { - // singleton_mode = true; - // continue; - // } - break; - } - extra_args(args, argidx, design); - - pool sb_dff_types; - sb_dff_types.insert(ID(SB_DFF)); - sb_dff_types.insert(ID(SB_DFFE)); - sb_dff_types.insert(ID(SB_DFFN)); - sb_dff_types.insert(ID(SB_DFFNE)); - - for (auto module : design->selected_modules()) - { - log("Merging set/reset $_MUX_ cells into SB_FFs in %s.\n", log_id(module)); - - SigMap sigmap(module); - dict sr_muxes; - vector ff_cells; - - for (auto cell : module->selected_cells()) - { - if (sb_dff_types.count(cell->type)) { - ff_cells.push_back(cell); - continue; - } - - if (cell->type != ID($_MUX_)) - continue; - - SigBit bit_a = sigmap(cell->getPort(ID::A)); - SigBit bit_b = sigmap(cell->getPort(ID::B)); - - if (bit_a.wire == nullptr || bit_b.wire == nullptr) - sr_muxes[sigmap(cell->getPort(ID::Y))] = cell; - } - - for (auto cell : ff_cells) - { - if (cell->get_bool_attribute(ID(dont_touch))) - continue; - - SigSpec sig_d = cell->getPort(ID::D); - - if (GetSize(sig_d) < 1) - continue; - - SigBit bit_d = sigmap(sig_d[0]); - - if (sr_muxes.count(bit_d) == 0) - continue; - - Cell *mux_cell = sr_muxes.at(bit_d); - SigBit bit_a = sigmap(mux_cell->getPort(ID::A)); - SigBit bit_b = sigmap(mux_cell->getPort(ID::B)); - SigBit bit_s = sigmap(mux_cell->getPort(ID::S)); - - log(" Merging %s (A=%s, B=%s, S=%s) into %s (%s).\n", log_id(mux_cell), - log_signal(bit_a), log_signal(bit_b), log_signal(bit_s), log_id(cell), log_id(cell->type)); - - SigBit sr_val, sr_sig; - if (bit_a.wire == nullptr) { - bit_d = bit_b; - sr_val = bit_a; - sr_sig = module->NotGate(NEW_ID, bit_s); - } else { - log_assert(bit_b.wire == nullptr); - bit_d = bit_a; - sr_val = bit_b; - sr_sig = bit_s; - } - - if (sr_val == State::S1) { - cell->type = cell->type.str() + "SS"; - cell->setPort(ID::S, sr_sig); - cell->setPort(ID::D, bit_d); - } else { - cell->type = cell->type.str() + "SR"; - cell->setPort(ID::R, sr_sig); - cell->setPort(ID::D, bit_d); - } - } - } - } -} Ice40FfssrPass; - -PRIVATE_NAMESPACE_END diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc index 1a70fa8c0..d28607904 100644 --- a/techlibs/ice40/ice40_opt.cc +++ b/techlibs/ice40/ice40_opt.cc @@ -215,7 +215,7 @@ struct Ice40OptPass : public Pass { log(" \n"); log(" opt_expr -mux_undef -undriven [-full]\n"); log(" opt_merge\n"); - log(" opt_rmdff\n"); + log(" opt_dff\n"); log(" opt_clean\n"); log(" while \n"); log("\n"); @@ -247,7 +247,7 @@ struct Ice40OptPass : public Pass { Pass::call(design, "opt_expr " + opt_expr_args); Pass::call(design, "opt_merge"); - Pass::call(design, "opt_rmdff"); + Pass::call(design, "opt_dff"); Pass::call(design, "opt_clean"); if (design->scratchpad_get_bool("opt.did_something") == false) diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 4ddb6ca70..ae6d3539c 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -293,6 +293,10 @@ struct SynthIce40Pass : public ScriptPass run("opt_clean"); run("check"); run("opt"); + run("fsm"); + run("opt"); + run("opt_dff"); + run("opt"); run("wreduce"); run("peepopt"); run("opt_clean"); @@ -316,8 +320,6 @@ struct SynthIce40Pass : public ScriptPass } run("alumacc"); run("opt"); - run("fsm"); - run("opt -fast"); run("memory -nomap"); run("opt_clean"); } @@ -354,11 +356,6 @@ struct SynthIce40Pass : public ScriptPass if (check_label("map_ffs")) { - if (!nodffe) - run("dff2dffe -direct-match $_DFF_*"); - if (min_ce_use >= 0) { - run("opt_merge"); - } if (nodffe) run(stringf("dfflegalize -cell $_DFF_?_ 0 -cell $_DFF_?P?_ 0 -cell $_SDFF_?P?_ 0 -cell $_DLATCH_?_ x")); else @@ -366,7 +363,6 @@ struct SynthIce40Pass : public ScriptPass run("techmap -map +/ice40/ff_map.v"); run("opt_expr -mux_undef"); run("simplemap"); - run("ice40_ffssr"); run("ice40_opt -full"); } -- cgit v1.2.3