From 295bb23ae06d36acc8ced4825ece6003470cd357 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 15 Jun 2019 09:08:56 -0700
Subject: Wrap FDRE with $__ABC_FDRE containing comb

---
 techlibs/xilinx/Makefile.inc    |  1 +
 techlibs/xilinx/abc_xc7.box     |  8 ++++----
 techlibs/xilinx/ff_map.v        | 10 +++++++++-
 techlibs/xilinx/synth_xilinx.cc | 22 +++++++++++++++-------
 4 files changed, 29 insertions(+), 12 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc
index 1a652eb27..12ec20053 100644
--- a/techlibs/xilinx/Makefile.inc
+++ b/techlibs/xilinx/Makefile.inc
@@ -30,6 +30,7 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_ff.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.box))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.lut))
 
diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
index 8a48bad4e..653f6bcb3 100644
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@ -41,10 +41,10 @@ RAM128X1D 5 0 17 2
 -   -   -   -   -   -   -   - 314 314 314 314 314 314 292 - -
 347 347 347 347 347 347 296 - -   -   -   -   -   -   -   - -
 
-# Inputs: C CE D R
-# Outputs: Q
-FDRE 6 0 4 1
-- - - -
+# Inputs: C CE D R Q_past
+# Outputs: Q_next
+FDRE 6 1 5 1
+- - - - -
 
 # Inputs: C CE D S
 # Outputs: Q
diff --git a/techlibs/xilinx/ff_map.v b/techlibs/xilinx/ff_map.v
index 13beaa6ae..ba34425d6 100644
--- a/techlibs/xilinx/ff_map.v
+++ b/techlibs/xilinx/ff_map.v
@@ -23,7 +23,15 @@
 `ifndef _NO_FFS
 
 module  \$_DFF_N_   (input D, C, output Q);    FDRE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0)); endmodule
-module  \$_DFF_P_   (input D, C, output Q);    FDRE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0)); endmodule
+module  \$_DFF_P_   (input D, C, output Q);
+`ifndef _ABC
+	FDRE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0));
+`else
+    wire Q_next;
+	\$__ABC_FDRE #(/*.INIT(|0)*/) _TECHMAP_REPLACE_ (.D(D), .Q(Q_next), .Q_past(Q), .C(C), .CE(1'b1), .R(1'b0));
+	\$_DFF_P_ abc_dff (.D(Q_next), .Q(Q), .C(C));
+`endif
+endmodule
 
 module  \$_DFFE_NP_ (input D, C, E, output Q); FDRE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E),    .R(1'b0)); endmodule
 module  \$_DFFE_PP_ (input D, C, E, output Q); FDRE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E),    .R(1'b0)); endmodule
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index a11648873..b9da4e6a6 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -276,25 +276,33 @@ struct SynthXilinxPass : public ScriptPass
 
 		if (check_label("map_cells")) {
 			run("techmap -map +/techmap.v -map +/xilinx/cells_map.v");
+			if (abc == "abc9")
+				run("techmap -max_iter 1 -D _ABC -map +/xilinx/ff_map.v");
 			run("clean");
 		}
 
 		if (check_label("map_luts")) {
-			if (abc == "abc9")
-				run(abc + " -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W " + XC7_WIRE_DELAY + string(retime ? " -dff" : ""));
-			else if (help_mode)
+			if (abc == "abc9") {
+				run("read_verilog -icells -lib +/xilinx/abc_ff.v");
+				run(abc + " -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W " + XC7_WIRE_DELAY + string(retime ? " -retime" : ""));
+			}
+			else if (help_mode) {
 				run(abc + " -luts 2:2,3,6:5,10,20 [-dff]");
-			else
+				run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
+						"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
+			}
+			else {
 				run(abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
+				run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
+						"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
+			}
 			run("clean");
 
 			// This shregmap call infers fixed length shift registers after abc
 			//   has performed any necessary retiming
 			if (!nosrl || help_mode)
 				run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')");
-			run("techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v");
-			run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
-					"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
+			run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v");
 			run("clean");
 		}
 
-- 
cgit v1.2.3


From ac18a76bebad001fc3e617a7cefebe13610abcb8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 15 Jun 2019 09:34:48 -0700
Subject: Map to $_FF_ instead of $_DFF_P_ to prevent recursion issues

---
 techlibs/xilinx/ff_map.v        | 2 +-
 techlibs/xilinx/synth_xilinx.cc | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/ff_map.v b/techlibs/xilinx/ff_map.v
index ba34425d6..8688c1c3b 100644
--- a/techlibs/xilinx/ff_map.v
+++ b/techlibs/xilinx/ff_map.v
@@ -29,7 +29,7 @@ module  \$_DFF_P_   (input D, C, output Q);
 `else
     wire Q_next;
 	\$__ABC_FDRE #(/*.INIT(|0)*/) _TECHMAP_REPLACE_ (.D(D), .Q(Q_next), .Q_past(Q), .C(C), .CE(1'b1), .R(1'b0));
-	\$_DFF_P_ abc_dff (.D(Q_next), .Q(Q), .C(C));
+	\$_FF_ abc_dff (.D(Q_next), .Q(Q));
 `endif
 endmodule
 
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index b9da4e6a6..375ab7af1 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -277,7 +277,7 @@ struct SynthXilinxPass : public ScriptPass
 		if (check_label("map_cells")) {
 			run("techmap -map +/techmap.v -map +/xilinx/cells_map.v");
 			if (abc == "abc9")
-				run("techmap -max_iter 1 -D _ABC -map +/xilinx/ff_map.v");
+				run("techmap -D _ABC -map +/xilinx/ff_map.v t:$_DFF*");
 			run("clean");
 		}
 
-- 
cgit v1.2.3


From a76c8a7ffdfb879971c8c3d1b1f7e8392ddf2c91 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 15 Jun 2019 09:46:35 -0700
Subject: Fix initialisation of flops

---
 techlibs/xilinx/ff_map.v        |  2 +-
 techlibs/xilinx/synth_xilinx.cc | 22 +++++++++++-----------
 2 files changed, 12 insertions(+), 12 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/ff_map.v b/techlibs/xilinx/ff_map.v
index 8688c1c3b..1f0635614 100644
--- a/techlibs/xilinx/ff_map.v
+++ b/techlibs/xilinx/ff_map.v
@@ -28,7 +28,7 @@ module  \$_DFF_P_   (input D, C, output Q);
 	FDRE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0));
 `else
     wire Q_next;
-	\$__ABC_FDRE #(/*.INIT(|0)*/) _TECHMAP_REPLACE_ (.D(D), .Q(Q_next), .Q_past(Q), .C(C), .CE(1'b1), .R(1'b0));
+	\$__ABC_FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q_next), .Q_past(Q), .C(C), .CE(1'b1), .R(1'b0));
 	\$_FF_ abc_dff (.D(Q_next), .Q(Q));
 `endif
 endmodule
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 375ab7af1..db43e13c1 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -275,9 +275,10 @@ struct SynthXilinxPass : public ScriptPass
 		}
 
 		if (check_label("map_cells")) {
-			run("techmap -map +/techmap.v -map +/xilinx/cells_map.v");
 			if (abc == "abc9")
-				run("techmap -D _ABC -map +/xilinx/ff_map.v t:$_DFF*");
+				run("techmap -map +/techmap.v -map +/xilinx/cells_map.v -D _ABC -map +/xilinx/ff_map.v");
+			else
+				run("techmap -map +/techmap.v -map +/xilinx/cells_map.v");
 			run("clean");
 		}
 
@@ -286,23 +287,22 @@ struct SynthXilinxPass : public ScriptPass
 				run("read_verilog -icells -lib +/xilinx/abc_ff.v");
 				run(abc + " -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W " + XC7_WIRE_DELAY + string(retime ? " -retime" : ""));
 			}
-			else if (help_mode) {
+			else if (help_mode)
 				run(abc + " -luts 2:2,3,6:5,10,20 [-dff]");
-				run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
-						"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
-			}
-			else {
+			else
 				run(abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
-				run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
-						"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
-			}
 			run("clean");
 
 			// This shregmap call infers fixed length shift registers after abc
 			//   has performed any necessary retiming
 			if (!nosrl || help_mode)
 				run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')");
-			run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v");
+			if (abc == "abc9")
+				run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v");
+			else
+				run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v -map +/xilinx/ff_map.v");
+			run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
+					"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
 			run("clean");
 		}
 
-- 
cgit v1.2.3


From 65c7bafc64682276d6c1f3cc53b97aa04d8c9039 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 15 Jun 2019 10:19:05 -0700
Subject: Re-order alphabetically

---
 techlibs/xilinx/abc_xc7.box | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
index 653f6bcb3..42f563898 100644
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@ -41,7 +41,7 @@ RAM128X1D 5 0 17 2
 -   -   -   -   -   -   -   - 314 314 314 314 314 314 292 - -
 347 347 347 347 347 347 296 - -   -   -   -   -   -   -   - -
 
-# Inputs: C CE D R Q_past
+# Inputs: C CE D Q_past R
 # Outputs: Q_next
 FDRE 6 1 5 1
 - - - - -
-- 
cgit v1.2.3


From c2f3f116d041b97b0d8b6ed28c87810bf6c2630e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 15 Jun 2019 18:16:14 -0700
Subject: Use $__ABC_FF_ instead of $_FF_

---
 techlibs/xilinx/ff_map.v | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/ff_map.v b/techlibs/xilinx/ff_map.v
index 1f0635614..bfd4c6998 100644
--- a/techlibs/xilinx/ff_map.v
+++ b/techlibs/xilinx/ff_map.v
@@ -29,12 +29,20 @@ module  \$_DFF_P_   (input D, C, output Q);
 `else
     wire Q_next;
 	\$__ABC_FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q_next), .Q_past(Q), .C(C), .CE(1'b1), .R(1'b0));
-	\$_FF_ abc_dff (.D(Q_next), .Q(Q));
+	\$__ABC_FF_ abc_dff (.D(Q_next), .Q(Q));
 `endif
 endmodule
 
 module  \$_DFFE_NP_ (input D, C, E, output Q); FDRE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E),    .R(1'b0)); endmodule
-module  \$_DFFE_PP_ (input D, C, E, output Q); FDRE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E),    .R(1'b0)); endmodule
+module  \$_DFFE_PP_ (input D, C, E, output Q);
+`ifndef _ABC
+	FDRE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E),    .R(1'b0));
+`else
+	wire Q_next;
+	\$__ABC_FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q_next), .Q_past(Q), .C(C), .CE(E), .R(1'b0));
+	\$__ABC_FF_ abc_dff (.D(Q_next), .Q(Q));
+`endif
+endmodule
 
 module  \$_DFF_NN0_ (input D, C, R, output Q); FDCE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R)); endmodule
 module  \$_DFF_NP0_ (input D, C, R, output Q); FDCE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R)); endmodule
-- 
cgit v1.2.3


From 9ec57b46c2f37ca9eafca8e0e919d676c74f99d8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 15 Jun 2019 19:36:37 -0700
Subject: Fix spacing

---
 techlibs/xilinx/ff_map.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/ff_map.v b/techlibs/xilinx/ff_map.v
index bfd4c6998..bd36c78fc 100644
--- a/techlibs/xilinx/ff_map.v
+++ b/techlibs/xilinx/ff_map.v
@@ -27,7 +27,7 @@ module  \$_DFF_P_   (input D, C, output Q);
 `ifndef _ABC
 	FDRE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0));
 `else
-    wire Q_next;
+	wire Q_next;
 	\$__ABC_FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q_next), .Q_past(Q), .C(C), .CE(1'b1), .R(1'b0));
 	\$__ABC_FF_ abc_dff (.D(Q_next), .Q(Q));
 `endif
-- 
cgit v1.2.3


From d969a9060eb337007e9246301fff906db5a8283e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 15 Jun 2019 22:41:29 -0700
Subject: Add +/xilinx/abc_ff

---
 techlibs/xilinx/abc_ff.v | 33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)
 create mode 100644 techlibs/xilinx/abc_ff.v

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc_ff.v b/techlibs/xilinx/abc_ff.v
new file mode 100644
index 000000000..abf4ac093
--- /dev/null
+++ b/techlibs/xilinx/abc_ff.v
@@ -0,0 +1,33 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *                2019  Eddie Hung    <eddie@fpgeh.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+// ============================================================================
+
+module \$__ABC_FF_ (input C, D, output Q);
+endmodule
+
+(* abc_box_id = 6, lib_whitebox, abc_flop *)
+module \$__ABC_FDRE ((* abc_flop_q *) output Q, input C, CE, (* abc_flop_d *) input D, (* abc_flop_q_past, abc_discard *) input Q_past, input R);
+  parameter [0:0] INIT = 1'b0;
+  //parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  parameter [0:0] IS_R_INVERTED = 1'b0;
+  assign Q = (R ^ IS_R_INVERTED) ? 1'b0 : (CE ? (D ^ IS_D_INVERTED) : Q_past);
+endmodule
-- 
cgit v1.2.3


From 0c59bc0b75ba2985e6ae0806d410fe2fa1c94e37 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Sun, 16 Jun 2019 10:42:00 -0700
Subject: Cleanup

---
 techlibs/xilinx/abc_ff.v    |  6 +++---
 techlibs/xilinx/abc_xc7.box |  4 ++--
 techlibs/xilinx/ff_map.v    | 12 ++++++------
 3 files changed, 11 insertions(+), 11 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc_ff.v b/techlibs/xilinx/abc_ff.v
index abf4ac093..e95602ab2 100644
--- a/techlibs/xilinx/abc_ff.v
+++ b/techlibs/xilinx/abc_ff.v
@@ -23,11 +23,11 @@
 module \$__ABC_FF_ (input C, D, output Q);
 endmodule
 
-(* abc_box_id = 6, lib_whitebox, abc_flop *)
-module \$__ABC_FDRE ((* abc_flop_q *) output Q, input C, CE, (* abc_flop_d *) input D, (* abc_flop_q_past, abc_discard *) input Q_past, input R);
+(* abc_box_id = 6, lib_whitebox, abc_flop = "FDRE", abc_flop_q = "Q", abc_flop_d = "D", abc_flop_past_q = "\\$pastQ" *)
+module \$__ABC_FDRE (output Q, input C, CE, D, R, \$pastQ );
   parameter [0:0] INIT = 1'b0;
   //parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_R_INVERTED = 1'b0;
-  assign Q = (R ^ IS_R_INVERTED) ? 1'b0 : (CE ? (D ^ IS_D_INVERTED) : Q_past);
+  assign Q = (R ^ IS_R_INVERTED) ? 1'b0 : (CE ? (D ^ IS_D_INVERTED) : \$pastQ );
 endmodule
diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
index 42f563898..9aef37545 100644
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@ -41,8 +41,8 @@ RAM128X1D 5 0 17 2
 -   -   -   -   -   -   -   - 314 314 314 314 314 314 292 - -
 347 347 347 347 347 347 296 - -   -   -   -   -   -   -   - -
 
-# Inputs: C CE D Q_past R
-# Outputs: Q_next
+# Inputs: C CE D R \$pastQ
+# Outputs: Q
 FDRE 6 1 5 1
 - - - - -
 
diff --git a/techlibs/xilinx/ff_map.v b/techlibs/xilinx/ff_map.v
index bd36c78fc..5ad73aa63 100644
--- a/techlibs/xilinx/ff_map.v
+++ b/techlibs/xilinx/ff_map.v
@@ -27,9 +27,9 @@ module  \$_DFF_P_   (input D, C, output Q);
 `ifndef _ABC
 	FDRE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0));
 `else
-	wire Q_next;
-	\$__ABC_FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q_next), .Q_past(Q), .C(C), .CE(1'b1), .R(1'b0));
-	\$__ABC_FF_ abc_dff (.D(Q_next), .Q(Q));
+	wire \$nextQ ;
+	\$__ABC_FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(1'b1), .R(1'b0));
+	\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
 `endif
 endmodule
 
@@ -38,9 +38,9 @@ module  \$_DFFE_PP_ (input D, C, E, output Q);
 `ifndef _ABC
 	FDRE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E),    .R(1'b0));
 `else
-	wire Q_next;
-	\$__ABC_FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q_next), .Q_past(Q), .C(C), .CE(E), .R(1'b0));
-	\$__ABC_FF_ abc_dff (.D(Q_next), .Q(Q));
+	wire \$nextQ ;
+	\$__ABC_FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(E), .R(1'b0));
+	\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
 `endif
 endmodule
 
-- 
cgit v1.2.3


From 8a86f9bb6259d335a250868c6f060936a482be8a Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 17 Jun 2019 15:13:05 -0700
Subject: Add box delays for FD*

---
 techlibs/xilinx/abc_xc7.box | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
index 9aef37545..4caf69320 100644
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@ -44,19 +44,19 @@ RAM128X1D 5 0 17 2
 # Inputs: C CE D R \$pastQ
 # Outputs: Q
 FDRE 6 1 5 1
-- - - - -
+- 109 -46 358 0
 
-# Inputs: C CE D S
+# Inputs: C CE D S \$pastQ
 # Outputs: Q
-FDSE 7 0 4 1
-- - - -
+FDSE 7 0 5 1
+- 109 -46 358 0
 
-# Inputs: C CE CLR D
+# Inputs: C CE CLR D \$pastQ
 # Outputs: Q
-FDCE 8 0 4 1
-- - - -
+FDCE 8 0 5 1
+- 109 - -46 0
 
-# Inputs: C CE D PRE
+# Inputs: C CE D PRE \$pastQ
 # Outputs: Q
-FDPE 9 0 4 1
-- - - -
+FDPE 9 0 5 1
+- 109 -46 - 0
-- 
cgit v1.2.3


From 659c04a68d15b20a9421ea5d154b259265f39494 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 1 Jul 2019 10:47:14 -0700
Subject: Update abc_box_id numbering

---
 techlibs/xilinx/abc_ff.v    | 2 +-
 techlibs/xilinx/abc_xc7.box | 8 ++++----
 2 files changed, 5 insertions(+), 5 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc_ff.v b/techlibs/xilinx/abc_ff.v
index e95602ab2..9f6f9c47e 100644
--- a/techlibs/xilinx/abc_ff.v
+++ b/techlibs/xilinx/abc_ff.v
@@ -23,7 +23,7 @@
 module \$__ABC_FF_ (input C, D, output Q);
 endmodule
 
-(* abc_box_id = 6, lib_whitebox, abc_flop = "FDRE", abc_flop_q = "Q", abc_flop_d = "D", abc_flop_past_q = "\\$pastQ" *)
+(* abc_box_id = 7, lib_whitebox, abc_flop = "FDRE", abc_flop_q = "Q", abc_flop_d = "D", abc_flop_past_q = "\\$pastQ" *)
 module \$__ABC_FDRE (output Q, input C, CE, D, R, \$pastQ );
   parameter [0:0] INIT = 1'b0;
   //parameter [0:0] IS_C_INVERTED = 1'b0;
diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
index bb9258e78..633e2d484 100644
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@ -54,20 +54,20 @@ RAM128X1D 6 0 17 2
 
 # Inputs: C CE D R \$pastQ
 # Outputs: Q
-FDRE 6 1 5 1
+FDRE 7 1 5 1
 - 109 -46 358 0
 
 # Inputs: C CE D S \$pastQ
 # Outputs: Q
-FDSE 7 0 5 1
+FDSE 8 0 5 1
 - 109 -46 358 0
 
 # Inputs: C CE CLR D \$pastQ
 # Outputs: Q
-FDCE 8 0 5 1
+FDCE 9 0 5 1
 - 109 - -46 0
 
 # Inputs: C CE D PRE \$pastQ
 # Outputs: Q
-FDPE 9 0 5 1
+FDPE 10 0 5 1
 - 109 -46 - 0
-- 
cgit v1.2.3


From 5466121ffb055c81946f8a729724febb8f93d4ef Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 1 Jul 2019 11:50:14 -0700
Subject: Capture all data in one "abc_flop" attribute

---
 techlibs/xilinx/abc_ff.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc_ff.v b/techlibs/xilinx/abc_ff.v
index 9f6f9c47e..a91720260 100644
--- a/techlibs/xilinx/abc_ff.v
+++ b/techlibs/xilinx/abc_ff.v
@@ -23,7 +23,7 @@
 module \$__ABC_FF_ (input C, D, output Q);
 endmodule
 
-(* abc_box_id = 7, lib_whitebox, abc_flop = "FDRE", abc_flop_q = "Q", abc_flop_d = "D", abc_flop_past_q = "\\$pastQ" *)
+(* abc_box_id = 7, lib_whitebox, abc_flop = "FDRE,D,Q,\\$pastQ" *)
 module \$__ABC_FDRE (output Q, input C, CE, D, R, \$pastQ );
   parameter [0:0] INIT = 1'b0;
   //parameter [0:0] IS_C_INVERTED = 1'b0;
-- 
cgit v1.2.3


From 73c8f1a59e69c5c2f06827d365afc6504fdfad82 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 10 Jul 2019 16:12:33 -0700
Subject: Fix box numbering

---
 techlibs/xilinx/abc_ff.v    | 2 +-
 techlibs/xilinx/abc_xc7.box | 8 ++++----
 2 files changed, 5 insertions(+), 5 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc_ff.v b/techlibs/xilinx/abc_ff.v
index a91720260..8bbdff6f4 100644
--- a/techlibs/xilinx/abc_ff.v
+++ b/techlibs/xilinx/abc_ff.v
@@ -23,7 +23,7 @@
 module \$__ABC_FF_ (input C, D, output Q);
 endmodule
 
-(* abc_box_id = 7, lib_whitebox, abc_flop = "FDRE,D,Q,\\$pastQ" *)
+(* abc_box_id = 8, lib_whitebox, abc_flop = "FDRE,D,Q,\\$pastQ" *)
 module \$__ABC_FDRE (output Q, input C, CE, D, R, \$pastQ );
   parameter [0:0] INIT = 1'b0;
   //parameter [0:0] IS_C_INVERTED = 1'b0;
diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
index 69ff9aeab..1e1afbc1d 100644
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@ -59,20 +59,20 @@ RAM128X1D 7 0 17 2
 
 # Inputs: C CE D R \$pastQ
 # Outputs: Q
-FDRE 7 1 5 1
+FDRE 8 1 5 1
 - 109 -46 358 0
 
 # Inputs: C CE D S \$pastQ
 # Outputs: Q
-FDSE 8 0 5 1
+FDSE 9 0 5 1
 - 109 -46 358 0
 
 # Inputs: C CE CLR D \$pastQ
 # Outputs: Q
-FDCE 9 0 5 1
+FDCE 10 0 5 1
 - 109 - -46 0
 
 # Inputs: C CE D PRE \$pastQ
 # Outputs: Q
-FDPE 10 0 5 1
+FDPE 11 0 5 1
 - 109 -46 - 0
-- 
cgit v1.2.3


From 838ae1a14cddf25919bb2a68e74220a07db4a06e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 10 Jul 2019 16:15:57 -0700
Subject: synth_xilinx's map_cells stage to techmap ff_map.v

---
 techlibs/xilinx/synth_xilinx.cc | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 2455c2885..45be9a318 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -361,6 +361,8 @@ struct SynthXilinxPass : public ScriptPass
 			std::string techmap_args = "-map +/techmap.v -D _ABC -map +/xilinx/cells_map.v";
 			if (widemux > 0)
 				techmap_args += stringf(" -D MIN_MUX_INPUTS=%d", widemux);
+			if (abc9)
+				techmap_args += " -map +/xilinx/ff_map.v";
 			run("techmap " + techmap_args);
 			run("clean");
 		}
-- 
cgit v1.2.3


From 0ab8f28bc7b6fefc1b4acd4e5c1cb437af878806 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 10 Jul 2019 16:23:15 -0700
Subject: Uncomment IS_C_INVERTED parameter

---
 techlibs/xilinx/abc_ff.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc_ff.v b/techlibs/xilinx/abc_ff.v
index 8bbdff6f4..d81f828e9 100644
--- a/techlibs/xilinx/abc_ff.v
+++ b/techlibs/xilinx/abc_ff.v
@@ -26,7 +26,7 @@ endmodule
 (* abc_box_id = 8, lib_whitebox, abc_flop = "FDRE,D,Q,\\$pastQ" *)
 module \$__ABC_FDRE (output Q, input C, CE, D, R, \$pastQ );
   parameter [0:0] INIT = 1'b0;
-  //parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_R_INVERTED = 1'b0;
   assign Q = (R ^ IS_R_INVERTED) ? 1'b0 : (CE ? (D ^ IS_D_INVERTED) : \$pastQ );
-- 
cgit v1.2.3


From 7b2599cb94a718d3c3d6fa4b5eb3ad4824ed13c4 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 10 Jul 2019 17:06:05 -0700
Subject: Move ABC FF stuff to abc_ff.v; add support for other FD* types

---
 techlibs/xilinx/abc_ff.v        | 114 +++++++++++++++++++++++++++++++++++++++-
 techlibs/xilinx/abc_xc7.box     |  25 +++++++--
 techlibs/xilinx/ff_map.v        |  21 +-------
 techlibs/xilinx/synth_xilinx.cc |   2 +-
 4 files changed, 135 insertions(+), 27 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc_ff.v b/techlibs/xilinx/abc_ff.v
index d81f828e9..f823bd731 100644
--- a/techlibs/xilinx/abc_ff.v
+++ b/techlibs/xilinx/abc_ff.v
@@ -20,14 +20,124 @@
 
 // ============================================================================
 
+module FDRE (output reg Q, input C, CE, D, R);
+  parameter [0:0] INIT = 1'b0;
+  parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  parameter [0:0] IS_CLR_INVERTED = 1'b0;
+  wire \$nextQ ;
+  \$__ABC_FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .R(R));
+  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
+endmodule
+module FDRE_1 (output reg Q, input C, CE, D, R);
+  parameter [0:0] INIT = 1'b0;
+  wire \$nextQ ;
+  \$__ABC_FDRE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .R(R));
+  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
+endmodule
+
+module FDCE (output reg Q, input C, CE, D, CLR);
+  parameter [0:0] INIT = 1'b0;
+  parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  parameter [0:0] IS_CLR_INVERTED = 1'b0;
+  wire \$nextQ , \$currQ ;
+  \$__ABC_FDCE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR));
+  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
+  \$__ABC_MUX_ abc_async_mux (.A(\$currQ ), .B(1'b0), .S(CLR), .Y(Q));
+endmodule
+module FDCE_1 (output reg Q, input C, CE, D, CLR);
+  parameter [0:0] INIT = 1'b0;
+  wire \$nextQ , \$currQ ;
+  \$__ABC_FDCE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR));
+  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
+  \$__ABC_MUX_ abc_async_mux (.A(\$currQ ), .B(1'b0), .S(CLR), .Y(Q));
+endmodule
+
+module FDPE (output reg Q, input C, CE, D, PRE);
+  parameter [0:0] INIT = 1'b0;
+  parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  parameter [0:0] IS_PRE_INVERTED = 1'b0;
+  wire \$nextQ , \$currQ ;
+  \$__ABC_FDCE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE));
+  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
+  generate
+    if (IS_PRE_INVERTED)
+      \$__ABC_MUX_ abc_async_mux (.A(\$currQ ), .B(1'b1), .S(PRE), .Y(Q));
+    else
+      \$__ABC_MUX_ abc_async_mux (.A(1'b1), .B(\$currQ ), .S(PRE), .Y(Q));
+  endgenerate
+endmodule
+module FDPE_1 (output reg Q, input C, CE, D, CLR);
+  parameter [0:0] INIT = 1'b0;
+  wire \$nextQ , \$currQ ;
+  \$__ABC_FDCE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE));
+  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
+  \$__ABC_MUX_ abc_async_mux (.A(\$currQ ), .B(1'b1), .S(PRE), .Y(Q));
+endmodule
+
+`ifndef _ABC
 module \$__ABC_FF_ (input C, D, output Q);
 endmodule
 
-(* abc_box_id = 8, lib_whitebox, abc_flop = "FDRE,D,Q,\\$pastQ" *)
+(* abc_box_id = 1000 *)
+module \$__ABC_FD_ASYNC_MUX_ (input A, B, S, output Q);
+//  assign Q = S ? B : A;
+endmodule
+
+(* abc_box_id = 1001, lib_whitebox, abc_flop = "FDRE,D,Q,\\$pastQ" *)
 module \$__ABC_FDRE (output Q, input C, CE, D, R, \$pastQ );
   parameter [0:0] INIT = 1'b0;
-  parameter [0:0] IS_C_INVERTED = 1'b0;
+  //parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_R_INVERTED = 1'b0;
   assign Q = (R ^ IS_R_INVERTED) ? 1'b0 : (CE ? (D ^ IS_D_INVERTED) : \$pastQ );
 endmodule
+
+(* abc_box_id = 1002, lib_whitebox, abc_flop = "FDRE_1,D,Q,\\$pastQ" *)
+module \$__ABC_FDRE_1 (output Q, input C, CE, D, R, \$pastQ );
+  parameter [0:0] INIT = 1'b0;
+  //parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  parameter [0:0] IS_R_INVERTED = 1'b0;
+  assign Q = (R ^ IS_R_INVERTED) ? 1'b0 : (CE ? (D ^ IS_D_INVERTED) : \$pastQ );
+endmodule
+
+(* abc_box_id = 1003, lib_whitebox, abc_flop = "FDCE,D,Q,\\$pastQ" *)
+module \$__ABC_FDCE (output Q, input C, CE, D, CLR, \$pastQ );
+  parameter [0:0] INIT = 1'b0;
+  //parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  //parameter [0:0] IS_CLR_INVERTED = 1'b0;
+  assign Q = CE ? (D ^ IS_D_INVERTED) : \$pastQ ;
+endmodule
+
+(* abc_box_id = 1004, lib_whitebox, abc_flop = "FDCE_1,D,Q,\\$pastQ" *)
+module \$__ABC_FDCE_1 (output Q, input C, CE, D, CLR, \$pastQ );
+  parameter [0:0] INIT = 1'b0;
+  //parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  //parameter [0:0] IS_CLR_INVERTED = 1'b0;
+  assign Q = CE ? (D ^ IS_D_INVERTED) : \$pastQ ;
+endmodule
+
+(* abc_box_id = 1005, lib_whitebox, abc_flop = "FDPE,D,Q,\\$pastQ" *)
+module \$__ABC_FDPE (output Q, input C, CE, D, PRE, \$pastQ );
+  parameter [0:0] INIT = 1'b0;
+  //parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  //parameter [0:0] IS_PRE_INVERTED = 1'b0;
+  assign Q = CE ? (D ^ IS_D_INVERTED) : \$pastQ ;
+endmodule
+
+(* abc_box_id = 1006, lib_whitebox, abc_flop = "FDPE_1,D,Q,\\$pastQ" *)
+module \$__ABC_FDPE_1 (output Q, input C, CE, D, PRE, \$pastQ );
+  parameter [0:0] INIT = 1'b0;
+  //parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  //parameter [0:0] IS_PRE_INVERTED = 1'b0;
+  assign Q = CE ? (D ^ IS_D_INVERTED) : \$pastQ ;
+endmodule
+
+`endif
diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
index 1e1afbc1d..ed283deac 100644
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@ -57,22 +57,37 @@ RAM128X1D 7 0 17 2
 -    -    -   -   -   -   -   - 1009 998 839 774 605 494 450 - -
 1047 1036 877 812 643 532 478 - -    -   -   -   -   -   -   - -
 
+# Inputs: A B S
+# Outputs: Y
+$__ABC_FD_ASYNC_MUX_ 1000 0 3 1
+0 0 764
+
 # Inputs: C CE D R \$pastQ
 # Outputs: Q
-FDRE 8 1 5 1
+FDRE 1001 1 5 1
 - 109 -46 358 0
 
-# Inputs: C CE D S \$pastQ
+# Inputs: C CE D R \$pastQ
 # Outputs: Q
-FDSE 9 0 5 1
+FDRE_1 1002 1 5 1
 - 109 -46 358 0
 
 # Inputs: C CE CLR D \$pastQ
 # Outputs: Q
-FDCE 10 0 5 1
+FDCE 1003 1 5 1
+- 109 - -46 0
+
+# Inputs: C CE CLR D \$pastQ
+# Outputs: Q
+FDCE_1004 11 1 5 1
 - 109 - -46 0
 
 # Inputs: C CE D PRE \$pastQ
 # Outputs: Q
-FDPE 11 0 5 1
+FDPE 1005 1 5 1
+- 109 -46 - 0
+
+# Inputs: C CE D PRE \$pastQ
+# Outputs: Q
+FDPE_1 1006 1 5 1
 - 109 -46 - 0
diff --git a/techlibs/xilinx/ff_map.v b/techlibs/xilinx/ff_map.v
index 5ad73aa63..b12b0ed7d 100644
--- a/techlibs/xilinx/ff_map.v
+++ b/techlibs/xilinx/ff_map.v
@@ -23,26 +23,9 @@
 `ifndef _NO_FFS
 
 module  \$_DFF_N_   (input D, C, output Q);    FDRE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0)); endmodule
-module  \$_DFF_P_   (input D, C, output Q);
-`ifndef _ABC
-	FDRE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0));
-`else
-	wire \$nextQ ;
-	\$__ABC_FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(1'b1), .R(1'b0));
-	\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
-`endif
-endmodule
-
+module  \$_DFF_P_   (input D, C, output Q);    FDRE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0)); endmodule
 module  \$_DFFE_NP_ (input D, C, E, output Q); FDRE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E),    .R(1'b0)); endmodule
-module  \$_DFFE_PP_ (input D, C, E, output Q);
-`ifndef _ABC
-	FDRE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E),    .R(1'b0));
-`else
-	wire \$nextQ ;
-	\$__ABC_FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(E), .R(1'b0));
-	\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
-`endif
-endmodule
+module  \$_DFFE_PP_ (input D, C, E, output Q); FDRE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E),    .R(1'b0)); endmodule
 
 module  \$_DFF_NN0_ (input D, C, R, output Q); FDCE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R)); endmodule
 module  \$_DFF_NP0_ (input D, C, R, output Q); FDCE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R)); endmodule
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 45be9a318..d5ae124e0 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -362,7 +362,7 @@ struct SynthXilinxPass : public ScriptPass
 			if (widemux > 0)
 				techmap_args += stringf(" -D MIN_MUX_INPUTS=%d", widemux);
 			if (abc9)
-				techmap_args += " -map +/xilinx/ff_map.v";
+				techmap_args += " -map +/xilinx/ff_map.v -D _ABC -map +/xilinx/abc_ff.v";
 			run("techmap " + techmap_args);
 			run("clean");
 		}
-- 
cgit v1.2.3


From 0372c900e8dbf6c3d46cdb9438b46d5ddf970e18 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 10 Jul 2019 17:15:49 -0700
Subject: Fix typo, and have !{PRE,CLR} behave as CE

---
 techlibs/xilinx/abc_ff.v | 28 ++++++++++++++--------------
 1 file changed, 14 insertions(+), 14 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc_ff.v b/techlibs/xilinx/abc_ff.v
index f823bd731..015211988 100644
--- a/techlibs/xilinx/abc_ff.v
+++ b/techlibs/xilinx/abc_ff.v
@@ -44,14 +44,14 @@ module FDCE (output reg Q, input C, CE, D, CLR);
   wire \$nextQ , \$currQ ;
   \$__ABC_FDCE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR));
   \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
-  \$__ABC_MUX_ abc_async_mux (.A(\$currQ ), .B(1'b0), .S(CLR), .Y(Q));
+  \$__ABC_FD_ASYNC_MUX abc_async_mux (.A(\$currQ ), .B(1'b0), .S(CLR), .Y(Q));
 endmodule
 module FDCE_1 (output reg Q, input C, CE, D, CLR);
   parameter [0:0] INIT = 1'b0;
   wire \$nextQ , \$currQ ;
   \$__ABC_FDCE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR));
   \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
-  \$__ABC_MUX_ abc_async_mux (.A(\$currQ ), .B(1'b0), .S(CLR), .Y(Q));
+  \$__ABC_FD_ASYNC_MUX abc_async_mux (.A(\$currQ ), .B(1'b0), .S(CLR), .Y(Q));
 endmodule
 
 module FDPE (output reg Q, input C, CE, D, PRE);
@@ -64,9 +64,9 @@ module FDPE (output reg Q, input C, CE, D, PRE);
   \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
   generate
     if (IS_PRE_INVERTED)
-      \$__ABC_MUX_ abc_async_mux (.A(\$currQ ), .B(1'b1), .S(PRE), .Y(Q));
+      \$__ABC_FD_ASYNC_MUX abc_async_mux (.A(\$currQ ), .B(1'b1), .S(PRE), .Y(Q));
     else
-      \$__ABC_MUX_ abc_async_mux (.A(1'b1), .B(\$currQ ), .S(PRE), .Y(Q));
+      \$__ABC_FD_ASYNC_MUX abc_async_mux (.A(1'b1), .B(\$currQ ), .S(PRE), .Y(Q));
   endgenerate
 endmodule
 module FDPE_1 (output reg Q, input C, CE, D, CLR);
@@ -74,7 +74,7 @@ module FDPE_1 (output reg Q, input C, CE, D, CLR);
   wire \$nextQ , \$currQ ;
   \$__ABC_FDCE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE));
   \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
-  \$__ABC_MUX_ abc_async_mux (.A(\$currQ ), .B(1'b1), .S(PRE), .Y(Q));
+  \$__ABC_FD_ASYNC_MUX abc_async_mux (.A(\$currQ ), .B(1'b1), .S(PRE), .Y(Q));
 endmodule
 
 `ifndef _ABC
@@ -82,7 +82,7 @@ module \$__ABC_FF_ (input C, D, output Q);
 endmodule
 
 (* abc_box_id = 1000 *)
-module \$__ABC_FD_ASYNC_MUX_ (input A, B, S, output Q);
+module \$__ABC_FD_ASYNC_MUX (input A, B, S, output Q);
 //  assign Q = S ? B : A;
 endmodule
 
@@ -109,8 +109,8 @@ module \$__ABC_FDCE (output Q, input C, CE, D, CLR, \$pastQ );
   parameter [0:0] INIT = 1'b0;
   //parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
-  //parameter [0:0] IS_CLR_INVERTED = 1'b0;
-  assign Q = CE ? (D ^ IS_D_INVERTED) : \$pastQ ;
+  parameter [0:0] IS_CLR_INVERTED = 1'b0;
+  assign Q = (CE && !(CLR ^ IS_CLR_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
 endmodule
 
 (* abc_box_id = 1004, lib_whitebox, abc_flop = "FDCE_1,D,Q,\\$pastQ" *)
@@ -118,8 +118,8 @@ module \$__ABC_FDCE_1 (output Q, input C, CE, D, CLR, \$pastQ );
   parameter [0:0] INIT = 1'b0;
   //parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
-  //parameter [0:0] IS_CLR_INVERTED = 1'b0;
-  assign Q = CE ? (D ^ IS_D_INVERTED) : \$pastQ ;
+  parameter [0:0] IS_CLR_INVERTED = 1'b0;
+  assign Q = (CE && !(CLR ^ IS_CLR_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
 endmodule
 
 (* abc_box_id = 1005, lib_whitebox, abc_flop = "FDPE,D,Q,\\$pastQ" *)
@@ -127,8 +127,8 @@ module \$__ABC_FDPE (output Q, input C, CE, D, PRE, \$pastQ );
   parameter [0:0] INIT = 1'b0;
   //parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
-  //parameter [0:0] IS_PRE_INVERTED = 1'b0;
-  assign Q = CE ? (D ^ IS_D_INVERTED) : \$pastQ ;
+  parameter [0:0] IS_PRE_INVERTED = 1'b0;
+  assign Q = (CE && !(PRE ^ IS_PRE_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
 endmodule
 
 (* abc_box_id = 1006, lib_whitebox, abc_flop = "FDPE_1,D,Q,\\$pastQ" *)
@@ -136,8 +136,8 @@ module \$__ABC_FDPE_1 (output Q, input C, CE, D, PRE, \$pastQ );
   parameter [0:0] INIT = 1'b0;
   //parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
-  //parameter [0:0] IS_PRE_INVERTED = 1'b0;
-  assign Q = CE ? (D ^ IS_D_INVERTED) : \$pastQ ;
+  parameter [0:0] IS_PRE_INVERTED = 1'b0;
+  assign Q = (CE && !(PRE ^ IS_PRE_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
 endmodule
 
 `endif
-- 
cgit v1.2.3


From 3bb48facb21032eb49ca40150827358e2d35a9c8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 10 Jul 2019 17:17:54 -0700
Subject: Remove params from FD*_1 variants

---
 techlibs/xilinx/abc_ff.v | 15 +++------------
 1 file changed, 3 insertions(+), 12 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc_ff.v b/techlibs/xilinx/abc_ff.v
index 015211988..1d9a25ba7 100644
--- a/techlibs/xilinx/abc_ff.v
+++ b/techlibs/xilinx/abc_ff.v
@@ -98,10 +98,7 @@ endmodule
 (* abc_box_id = 1002, lib_whitebox, abc_flop = "FDRE_1,D,Q,\\$pastQ" *)
 module \$__ABC_FDRE_1 (output Q, input C, CE, D, R, \$pastQ );
   parameter [0:0] INIT = 1'b0;
-  //parameter [0:0] IS_C_INVERTED = 1'b0;
-  parameter [0:0] IS_D_INVERTED = 1'b0;
-  parameter [0:0] IS_R_INVERTED = 1'b0;
-  assign Q = (R ^ IS_R_INVERTED) ? 1'b0 : (CE ? (D ^ IS_D_INVERTED) : \$pastQ );
+  assign Q = R ? 1'b0 : (CE ? D : \$pastQ );
 endmodule
 
 (* abc_box_id = 1003, lib_whitebox, abc_flop = "FDCE,D,Q,\\$pastQ" *)
@@ -116,10 +113,7 @@ endmodule
 (* abc_box_id = 1004, lib_whitebox, abc_flop = "FDCE_1,D,Q,\\$pastQ" *)
 module \$__ABC_FDCE_1 (output Q, input C, CE, D, CLR, \$pastQ );
   parameter [0:0] INIT = 1'b0;
-  //parameter [0:0] IS_C_INVERTED = 1'b0;
-  parameter [0:0] IS_D_INVERTED = 1'b0;
-  parameter [0:0] IS_CLR_INVERTED = 1'b0;
-  assign Q = (CE && !(CLR ^ IS_CLR_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
+  assign Q = (CE && !CLR) ? D : \$pastQ ;
 endmodule
 
 (* abc_box_id = 1005, lib_whitebox, abc_flop = "FDPE,D,Q,\\$pastQ" *)
@@ -134,10 +128,7 @@ endmodule
 (* abc_box_id = 1006, lib_whitebox, abc_flop = "FDPE_1,D,Q,\\$pastQ" *)
 module \$__ABC_FDPE_1 (output Q, input C, CE, D, PRE, \$pastQ );
   parameter [0:0] INIT = 1'b0;
-  //parameter [0:0] IS_C_INVERTED = 1'b0;
-  parameter [0:0] IS_D_INVERTED = 1'b0;
-  parameter [0:0] IS_PRE_INVERTED = 1'b0;
-  assign Q = (CE && !(PRE ^ IS_PRE_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
+  assign Q = (CE && !PRE) ? D : \$pastQ ;
 endmodule
 
 `endif
-- 
cgit v1.2.3


From 4a995c5d80735baf1431a088c2faf81eb75fdaf6 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 10 Jul 2019 17:54:56 -0700
Subject: Change how to specify flops to ABC again

---
 techlibs/xilinx/abc_ff.v | 50 +++++++++++++++++++++++++++++++++++-------------
 1 file changed, 37 insertions(+), 13 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc_ff.v b/techlibs/xilinx/abc_ff.v
index 1d9a25ba7..db63232b7 100644
--- a/techlibs/xilinx/abc_ff.v
+++ b/techlibs/xilinx/abc_ff.v
@@ -86,23 +86,35 @@ module \$__ABC_FD_ASYNC_MUX (input A, B, S, output Q);
 //  assign Q = S ? B : A;
 endmodule
 
-(* abc_box_id = 1001, lib_whitebox, abc_flop = "FDRE,D,Q,\\$pastQ" *)
-module \$__ABC_FDRE (output Q, input C, CE, D, R, \$pastQ );
+(* abc_box_id = 1001, lib_whitebox, abc_flop = "FDRE" *)
+module \$__ABC_FDRE ((* abc_flop_q *)   output Q,
+                     (* abc_flop_clk *) input C,
+                     (* abc_flop_en *)  input CE,
+                     (* abc_flop_d *)   input D,
+                     input R, \$pastQ );
   parameter [0:0] INIT = 1'b0;
-  //parameter [0:0] IS_C_INVERTED = 1'b0;
+  (* abc_flop_clk_inv *) parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_R_INVERTED = 1'b0;
   assign Q = (R ^ IS_R_INVERTED) ? 1'b0 : (CE ? (D ^ IS_D_INVERTED) : \$pastQ );
 endmodule
 
-(* abc_box_id = 1002, lib_whitebox, abc_flop = "FDRE_1,D,Q,\\$pastQ" *)
-module \$__ABC_FDRE_1 (output Q, input C, CE, D, R, \$pastQ );
+(* abc_box_id = 1002, lib_whitebox, abc_flop = "FDRE_1" *)
+module \$__ABC_FDRE_1 ((* abc_flop_q *)   output Q,
+                       (* abc_flop_clk *) input C,
+                       (* abc_flop_en *)  input CE,
+                       (* abc_flop_d *)   input D,
+                       input R, \$pastQ );
   parameter [0:0] INIT = 1'b0;
   assign Q = R ? 1'b0 : (CE ? D : \$pastQ );
 endmodule
 
-(* abc_box_id = 1003, lib_whitebox, abc_flop = "FDCE,D,Q,\\$pastQ" *)
-module \$__ABC_FDCE (output Q, input C, CE, D, CLR, \$pastQ );
+(* abc_box_id = 1003, lib_whitebox, abc_flop = "FDCE" *)
+module \$__ABC_FDCE ((* abc_flop_q *)   output Q,
+                     (* abc_flop_clk *) input C,
+                     (* abc_flop_en *)  input CE,
+                     (* abc_flop_d *)   input D,
+                     input CLR, \$pastQ );
   parameter [0:0] INIT = 1'b0;
   //parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -110,14 +122,22 @@ module \$__ABC_FDCE (output Q, input C, CE, D, CLR, \$pastQ );
   assign Q = (CE && !(CLR ^ IS_CLR_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
 endmodule
 
-(* abc_box_id = 1004, lib_whitebox, abc_flop = "FDCE_1,D,Q,\\$pastQ" *)
-module \$__ABC_FDCE_1 (output Q, input C, CE, D, CLR, \$pastQ );
+(* abc_box_id = 1004, lib_whitebox, abc_flop = "FDCE_1" *)
+module \$__ABC_FDCE_1 ((* abc_flop_q *)   output Q,
+                       (* abc_flop_clk *) input C,
+                       (* abc_flop_en *)  input CE,
+                       (* abc_flop_d *)   input D,
+                       input CLR, \$pastQ );
   parameter [0:0] INIT = 1'b0;
   assign Q = (CE && !CLR) ? D : \$pastQ ;
 endmodule
 
-(* abc_box_id = 1005, lib_whitebox, abc_flop = "FDPE,D,Q,\\$pastQ" *)
-module \$__ABC_FDPE (output Q, input C, CE, D, PRE, \$pastQ );
+(* abc_box_id = 1005, lib_whitebox, abc_flop = "FDPE" *)
+module \$__ABC_FDPE ((* abc_flop_q *)   output Q,
+                     (* abc_flop_clk *) input C,
+                     (* abc_flop_en *)  input CE,
+                     (* abc_flop_d *)   input D,
+                     input PRE, \$pastQ );
   parameter [0:0] INIT = 1'b0;
   //parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -125,8 +145,12 @@ module \$__ABC_FDPE (output Q, input C, CE, D, PRE, \$pastQ );
   assign Q = (CE && !(PRE ^ IS_PRE_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
 endmodule
 
-(* abc_box_id = 1006, lib_whitebox, abc_flop = "FDPE_1,D,Q,\\$pastQ" *)
-module \$__ABC_FDPE_1 (output Q, input C, CE, D, PRE, \$pastQ );
+(* abc_box_id = 1006, lib_whitebox, abc_flop = "FDPE_1" *)
+module \$__ABC_FDPE_1 ((* abc_flop_q *)   output Q,
+                       (* abc_flop_clk *) input C,
+                       (* abc_flop_en *)  input CE,
+                       (* abc_flop_d *)   input D,
+                       input PRE, \$pastQ );
   parameter [0:0] INIT = 1'b0;
   assign Q = (CE && !PRE) ? D : \$pastQ ;
 endmodule
-- 
cgit v1.2.3


From f030be3f1c384f457b5700aef99d21c34258f64e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 10 Jul 2019 18:57:11 -0700
Subject: Preserve all parameters, plus some extra ones for clk/en polarity

---
 techlibs/xilinx/abc_ff.v | 76 +++++++++++++++++++++++++++++++++++++++++-------
 1 file changed, 66 insertions(+), 10 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc_ff.v b/techlibs/xilinx/abc_ff.v
index db63232b7..d0087501d 100644
--- a/techlibs/xilinx/abc_ff.v
+++ b/techlibs/xilinx/abc_ff.v
@@ -24,15 +24,29 @@ module FDRE (output reg Q, input C, CE, D, R);
   parameter [0:0] INIT = 1'b0;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
-  parameter [0:0] IS_CLR_INVERTED = 1'b0;
+  parameter [0:0] IS_R_INVERTED = 1'b0;
   wire \$nextQ ;
-  \$__ABC_FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .R(R));
+  \$__ABC_FDRE #(
+    .INIT(|0),
+    .IS_C_INVERTED(IS_C_INVERTED),
+    .IS_D_INVERTED(IS_D_INVERTED),
+    .IS_R_INVERTED(IS_R_INVERTED),
+    .\$abc_flop_clk_pol (!IS_C_INVERTED),
+    .\$abc_flop_en_pol (1'b1)
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .R(R)
+  );
   \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
 endmodule
 module FDRE_1 (output reg Q, input C, CE, D, R);
   parameter [0:0] INIT = 1'b0;
   wire \$nextQ ;
-  \$__ABC_FDRE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .R(R));
+  \$__ABC_FDRE_1 #(.INIT(|0),
+    .\$abc_flop_clk_pol (1'b1),
+    .\$abc_flop_en_pol (1'b1)
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .R(R)
+  );
   \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
 endmodule
 
@@ -42,14 +56,29 @@ module FDCE (output reg Q, input C, CE, D, CLR);
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_CLR_INVERTED = 1'b0;
   wire \$nextQ , \$currQ ;
-  \$__ABC_FDCE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR));
+  \$__ABC_FDCE #(
+    .INIT(|0),
+    .IS_C_INVERTED(IS_C_INVERTED),
+    .IS_D_INVERTED(IS_D_INVERTED),
+    .IS_CLR_INVERTED(IS_CLR_INVERTED),
+    .\$abc_flop_clk_pol (!IS_C_INVERTED),
+    .\$abc_flop_en_pol (1'b1)
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR)
+  );
   \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
   \$__ABC_FD_ASYNC_MUX abc_async_mux (.A(\$currQ ), .B(1'b0), .S(CLR), .Y(Q));
 endmodule
 module FDCE_1 (output reg Q, input C, CE, D, CLR);
   parameter [0:0] INIT = 1'b0;
   wire \$nextQ , \$currQ ;
-  \$__ABC_FDCE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR));
+  \$__ABC_FDCE_1 #(
+    .INIT(|0),
+    .\$abc_flop_clk_pol (1'b1),
+    .\$abc_flop_en_pol (1'b1)
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR)
+  );
   \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
   \$__ABC_FD_ASYNC_MUX abc_async_mux (.A(\$currQ ), .B(1'b0), .S(CLR), .Y(Q));
 endmodule
@@ -60,7 +89,16 @@ module FDPE (output reg Q, input C, CE, D, PRE);
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_PRE_INVERTED = 1'b0;
   wire \$nextQ , \$currQ ;
-  \$__ABC_FDCE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE));
+  \$__ABC_FDCE #(
+    .INIT(|0),
+    .IS_C_INVERTED(IS_C_INVERTED),
+    .IS_D_INVERTED(IS_D_INVERTED),
+    .IS_PRE_INVERTED(IS_PRE_INVERTED),
+    .\$abc_flop_clk_pol (!IS_C_INVERTED),
+    .\$abc_flop_en_pol (1'b1)
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE)
+  );
   \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
   generate
     if (IS_PRE_INVERTED)
@@ -72,7 +110,13 @@ endmodule
 module FDPE_1 (output reg Q, input C, CE, D, CLR);
   parameter [0:0] INIT = 1'b0;
   wire \$nextQ , \$currQ ;
-  \$__ABC_FDCE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE));
+  \$__ABC_FDPE_1 #(
+    .INIT(|0),
+    .\$abc_flop_clk_pol (1'b1),
+    .\$abc_flop_en_pol (1'b1)
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE)
+  );
   \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
   \$__ABC_FD_ASYNC_MUX abc_async_mux (.A(\$currQ ), .B(1'b1), .S(PRE), .Y(Q));
 endmodule
@@ -93,9 +137,11 @@ module \$__ABC_FDRE ((* abc_flop_q *)   output Q,
                      (* abc_flop_d *)   input D,
                      input R, \$pastQ );
   parameter [0:0] INIT = 1'b0;
-  (* abc_flop_clk_inv *) parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_R_INVERTED = 1'b0;
+  parameter \$abc_flop_clk_pol = ~IS_C_INVERTED;
+  parameter \$abc_flop_en_pol = 1'b1;
   assign Q = (R ^ IS_R_INVERTED) ? 1'b0 : (CE ? (D ^ IS_D_INVERTED) : \$pastQ );
 endmodule
 
@@ -106,6 +152,8 @@ module \$__ABC_FDRE_1 ((* abc_flop_q *)   output Q,
                        (* abc_flop_d *)   input D,
                        input R, \$pastQ );
   parameter [0:0] INIT = 1'b0;
+  parameter \$abc_flop_clk_pol = 1'b1;
+  parameter \$abc_flop_en_pol = 1'b1;
   assign Q = R ? 1'b0 : (CE ? D : \$pastQ );
 endmodule
 
@@ -116,9 +164,11 @@ module \$__ABC_FDCE ((* abc_flop_q *)   output Q,
                      (* abc_flop_d *)   input D,
                      input CLR, \$pastQ );
   parameter [0:0] INIT = 1'b0;
-  //parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_CLR_INVERTED = 1'b0;
+  parameter \$abc_flop_clk_pol = ~IS_C_INVERTED;
+  parameter \$abc_flop_en_pol = 1'b1;
   assign Q = (CE && !(CLR ^ IS_CLR_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
 endmodule
 
@@ -129,6 +179,8 @@ module \$__ABC_FDCE_1 ((* abc_flop_q *)   output Q,
                        (* abc_flop_d *)   input D,
                        input CLR, \$pastQ );
   parameter [0:0] INIT = 1'b0;
+  parameter \$abc_flop_clk_pol = 1'b1;
+  parameter \$abc_flop_en_inv = 1'b1;
   assign Q = (CE && !CLR) ? D : \$pastQ ;
 endmodule
 
@@ -139,9 +191,11 @@ module \$__ABC_FDPE ((* abc_flop_q *)   output Q,
                      (* abc_flop_d *)   input D,
                      input PRE, \$pastQ );
   parameter [0:0] INIT = 1'b0;
-  //parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_PRE_INVERTED = 1'b0;
+  parameter \$abc_flop_clk_pol = ~IS_C_INVERTED;
+  parameter \$abc_flop_en_pol = 1'b1;
   assign Q = (CE && !(PRE ^ IS_PRE_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
 endmodule
 
@@ -152,6 +206,8 @@ module \$__ABC_FDPE_1 ((* abc_flop_q *)   output Q,
                        (* abc_flop_d *)   input D,
                        input PRE, \$pastQ );
   parameter [0:0] INIT = 1'b0;
+  parameter \$abc_flop_clk_pol = ~IS_C_INVERTED;
+  parameter \$abc_flop_en_pol = 1'b1;
   assign Q = (CE && !PRE) ? D : \$pastQ ;
 endmodule
 
-- 
cgit v1.2.3


From f3511e4f9358b0eb053893877ab615b66325da39 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 10 Jul 2019 19:01:13 -0700
Subject: Use \$currQ

---
 techlibs/xilinx/abc_ff.v | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc_ff.v b/techlibs/xilinx/abc_ff.v
index d0087501d..96cbb1e04 100644
--- a/techlibs/xilinx/abc_ff.v
+++ b/techlibs/xilinx/abc_ff.v
@@ -66,8 +66,13 @@ module FDCE (output reg Q, input C, CE, D, CLR);
   ) _TECHMAP_REPLACE_ (
     .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR)
   );
-  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
-  \$__ABC_FD_ASYNC_MUX abc_async_mux (.A(\$currQ ), .B(1'b0), .S(CLR), .Y(Q));
+  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
+  generate
+    if (IS_PRE_INVERTED)
+      \$__ABC_FD_ASYNC_MUX abc_async_mux (.A(\$currQ ), .B(1'b0), .S(CLR), .Y(Q));
+    else
+      \$__ABC_FD_ASYNC_MUX abc_async_mux (.A(1'b0), .B(\$currQ ), .S(CLR), .Y(Q));
+  endgenerate
 endmodule
 module FDCE_1 (output reg Q, input C, CE, D, CLR);
   parameter [0:0] INIT = 1'b0;
@@ -99,7 +104,7 @@ module FDPE (output reg Q, input C, CE, D, PRE);
   ) _TECHMAP_REPLACE_ (
     .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE)
   );
-  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
+  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
   generate
     if (IS_PRE_INVERTED)
       \$__ABC_FD_ASYNC_MUX abc_async_mux (.A(\$currQ ), .B(1'b1), .S(PRE), .Y(Q));
@@ -117,7 +122,7 @@ module FDPE_1 (output reg Q, input C, CE, D, CLR);
   ) _TECHMAP_REPLACE_ (
     .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE)
   );
-  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
+  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
   \$__ABC_FD_ASYNC_MUX abc_async_mux (.A(\$currQ ), .B(1'b1), .S(PRE), .Y(Q));
 endmodule
 
-- 
cgit v1.2.3


From ad35b509de55df1ab5c6a360adec1e3777ba2410 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 10 Jul 2019 19:05:53 -0700
Subject: Another typo

---
 techlibs/xilinx/abc_ff.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc_ff.v b/techlibs/xilinx/abc_ff.v
index 96cbb1e04..91cfbc4c4 100644
--- a/techlibs/xilinx/abc_ff.v
+++ b/techlibs/xilinx/abc_ff.v
@@ -68,7 +68,7 @@ module FDCE (output reg Q, input C, CE, D, CLR);
   );
   \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
   generate
-    if (IS_PRE_INVERTED)
+    if (IS_CLR_INVERTED)
       \$__ABC_FD_ASYNC_MUX abc_async_mux (.A(\$currQ ), .B(1'b0), .S(CLR), .Y(Q));
     else
       \$__ABC_FD_ASYNC_MUX abc_async_mux (.A(1'b0), .B(\$currQ ), .S(CLR), .Y(Q));
-- 
cgit v1.2.3


From 7899a06ed64c55e8d804ef2970ad983e3d112013 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 10 Jul 2019 19:59:24 -0700
Subject: Another typo

---
 techlibs/xilinx/abc_ff.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc_ff.v b/techlibs/xilinx/abc_ff.v
index 91cfbc4c4..6f9011ef1 100644
--- a/techlibs/xilinx/abc_ff.v
+++ b/techlibs/xilinx/abc_ff.v
@@ -94,7 +94,7 @@ module FDPE (output reg Q, input C, CE, D, PRE);
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_PRE_INVERTED = 1'b0;
   wire \$nextQ , \$currQ ;
-  \$__ABC_FDCE #(
+  \$__ABC_FDPE #(
     .INIT(|0),
     .IS_C_INVERTED(IS_C_INVERTED),
     .IS_D_INVERTED(IS_D_INVERTED),
-- 
cgit v1.2.3


From ea6ffea2cd580542cbb5cc349f5268af0700e292 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 10 Jul 2019 20:10:20 -0700
Subject: Fix clk_pol for FD*_1

---
 techlibs/xilinx/abc_ff.v | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc_ff.v b/techlibs/xilinx/abc_ff.v
index 6f9011ef1..8e0b578ab 100644
--- a/techlibs/xilinx/abc_ff.v
+++ b/techlibs/xilinx/abc_ff.v
@@ -157,7 +157,7 @@ module \$__ABC_FDRE_1 ((* abc_flop_q *)   output Q,
                        (* abc_flop_d *)   input D,
                        input R, \$pastQ );
   parameter [0:0] INIT = 1'b0;
-  parameter \$abc_flop_clk_pol = 1'b1;
+  parameter \$abc_flop_clk_pol = 1'b0;
   parameter \$abc_flop_en_pol = 1'b1;
   assign Q = R ? 1'b0 : (CE ? D : \$pastQ );
 endmodule
@@ -184,7 +184,7 @@ module \$__ABC_FDCE_1 ((* abc_flop_q *)   output Q,
                        (* abc_flop_d *)   input D,
                        input CLR, \$pastQ );
   parameter [0:0] INIT = 1'b0;
-  parameter \$abc_flop_clk_pol = 1'b1;
+  parameter \$abc_flop_clk_pol = 1'b0;
   parameter \$abc_flop_en_inv = 1'b1;
   assign Q = (CE && !CLR) ? D : \$pastQ ;
 endmodule
@@ -211,7 +211,7 @@ module \$__ABC_FDPE_1 ((* abc_flop_q *)   output Q,
                        (* abc_flop_d *)   input D,
                        input PRE, \$pastQ );
   parameter [0:0] INIT = 1'b0;
-  parameter \$abc_flop_clk_pol = ~IS_C_INVERTED;
+  parameter \$abc_flop_clk_pol = 1'b0;
   parameter \$abc_flop_en_pol = 1'b1;
   assign Q = (CE && !PRE) ? D : \$pastQ ;
 endmodule
-- 
cgit v1.2.3


From f984e0cb345c7cec85eb9b90a13faacffa2e3fa2 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 10 Jul 2019 22:33:35 -0700
Subject: Another typo

---
 techlibs/xilinx/abc_ff.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc_ff.v b/techlibs/xilinx/abc_ff.v
index 8e0b578ab..e4937f646 100644
--- a/techlibs/xilinx/abc_ff.v
+++ b/techlibs/xilinx/abc_ff.v
@@ -112,7 +112,7 @@ module FDPE (output reg Q, input C, CE, D, PRE);
       \$__ABC_FD_ASYNC_MUX abc_async_mux (.A(1'b1), .B(\$currQ ), .S(PRE), .Y(Q));
   endgenerate
 endmodule
-module FDPE_1 (output reg Q, input C, CE, D, CLR);
+module FDPE_1 (output reg Q, input C, CE, D, PRE);
   parameter [0:0] INIT = 1'b0;
   wire \$nextQ , \$currQ ;
   \$__ABC_FDPE_1 #(
-- 
cgit v1.2.3


From d357431df175719ed7653d2e3724473aece36b78 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 10 Jul 2019 22:54:39 -0700
Subject: Restore from master

---
 techlibs/xilinx/ff_map.v | 1 +
 1 file changed, 1 insertion(+)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/ff_map.v b/techlibs/xilinx/ff_map.v
index b12b0ed7d..13beaa6ae 100644
--- a/techlibs/xilinx/ff_map.v
+++ b/techlibs/xilinx/ff_map.v
@@ -24,6 +24,7 @@
 
 module  \$_DFF_N_   (input D, C, output Q);    FDRE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0)); endmodule
 module  \$_DFF_P_   (input D, C, output Q);    FDRE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0)); endmodule
+
 module  \$_DFFE_NP_ (input D, C, E, output Q); FDRE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E),    .R(1'b0)); endmodule
 module  \$_DFFE_PP_ (input D, C, E, output Q); FDRE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E),    .R(1'b0)); endmodule
 
-- 
cgit v1.2.3


From 93fbd56db1c72403881281aa2c3e61bf6e622344 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 11 Jul 2019 10:25:59 -0700
Subject: $__ABC_FD_ASYNC_MUX.Q -> Y

---
 techlibs/xilinx/abc_ff.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc_ff.v b/techlibs/xilinx/abc_ff.v
index e4937f646..81696ddb5 100644
--- a/techlibs/xilinx/abc_ff.v
+++ b/techlibs/xilinx/abc_ff.v
@@ -131,7 +131,7 @@ module \$__ABC_FF_ (input C, D, output Q);
 endmodule
 
 (* abc_box_id = 1000 *)
-module \$__ABC_FD_ASYNC_MUX (input A, B, S, output Q);
+module \$__ABC_FD_ASYNC_MUX (input A, B, S, output Y);
 //  assign Q = S ? B : A;
 endmodule
 
-- 
cgit v1.2.3


From 8fef4c359419998eb4b068b019cbeb7faae331b7 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 11 Jul 2019 10:52:33 -0700
Subject: Simplify to $__ABC_ASYNC box

---
 techlibs/xilinx/abc_ff.v    | 21 +++++----------------
 techlibs/xilinx/abc_xc7.box |  6 +++---
 2 files changed, 8 insertions(+), 19 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc_ff.v b/techlibs/xilinx/abc_ff.v
index 81696ddb5..69013f475 100644
--- a/techlibs/xilinx/abc_ff.v
+++ b/techlibs/xilinx/abc_ff.v
@@ -67,12 +67,7 @@ module FDCE (output reg Q, input C, CE, D, CLR);
     .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR)
   );
   \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
-  generate
-    if (IS_CLR_INVERTED)
-      \$__ABC_FD_ASYNC_MUX abc_async_mux (.A(\$currQ ), .B(1'b0), .S(CLR), .Y(Q));
-    else
-      \$__ABC_FD_ASYNC_MUX abc_async_mux (.A(1'b0), .B(\$currQ ), .S(CLR), .Y(Q));
-  endgenerate
+  \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(CLR), .Y(Q));
 endmodule
 module FDCE_1 (output reg Q, input C, CE, D, CLR);
   parameter [0:0] INIT = 1'b0;
@@ -85,7 +80,7 @@ module FDCE_1 (output reg Q, input C, CE, D, CLR);
     .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR)
   );
   \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
-  \$__ABC_FD_ASYNC_MUX abc_async_mux (.A(\$currQ ), .B(1'b0), .S(CLR), .Y(Q));
+  \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(CLR), .Y(Q));
 endmodule
 
 module FDPE (output reg Q, input C, CE, D, PRE);
@@ -105,12 +100,7 @@ module FDPE (output reg Q, input C, CE, D, PRE);
     .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE)
   );
   \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
-  generate
-    if (IS_PRE_INVERTED)
-      \$__ABC_FD_ASYNC_MUX abc_async_mux (.A(\$currQ ), .B(1'b1), .S(PRE), .Y(Q));
-    else
-      \$__ABC_FD_ASYNC_MUX abc_async_mux (.A(1'b1), .B(\$currQ ), .S(PRE), .Y(Q));
-  endgenerate
+  \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(PRE), .Y(Q));
 endmodule
 module FDPE_1 (output reg Q, input C, CE, D, PRE);
   parameter [0:0] INIT = 1'b0;
@@ -123,7 +113,7 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE);
     .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE)
   );
   \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
-  \$__ABC_FD_ASYNC_MUX abc_async_mux (.A(\$currQ ), .B(1'b1), .S(PRE), .Y(Q));
+  \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(PRE), .Y(Q));
 endmodule
 
 `ifndef _ABC
@@ -131,8 +121,7 @@ module \$__ABC_FF_ (input C, D, output Q);
 endmodule
 
 (* abc_box_id = 1000 *)
-module \$__ABC_FD_ASYNC_MUX (input A, B, S, output Y);
-//  assign Q = S ? B : A;
+module \$__ABC_ASYNC (input A, S, output Y);
 endmodule
 
 (* abc_box_id = 1001, lib_whitebox, abc_flop = "FDRE" *)
diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
index ed283deac..df16c3af1 100644
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@ -57,10 +57,10 @@ RAM128X1D 7 0 17 2
 -    -    -   -   -   -   -   - 1009 998 839 774 605 494 450 - -
 1047 1036 877 812 643 532 478 - -    -   -   -   -   -   -   - -
 
-# Inputs: A B S
+# Inputs: A S
 # Outputs: Y
-$__ABC_FD_ASYNC_MUX_ 1000 0 3 1
-0 0 764
+$__ABC_ASYNC 1000 0 2 1
+0 764
 
 # Inputs: C CE D R \$pastQ
 # Outputs: Q
-- 
cgit v1.2.3


From 021f8e549266fb500d19f7a3b7747cad6eda22c2 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 11 Jul 2019 13:23:07 -0700
Subject: Fix typo

---
 techlibs/xilinx/abc_xc7.box | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
index df16c3af1..24512ecf7 100644
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@ -79,7 +79,7 @@ FDCE 1003 1 5 1
 
 # Inputs: C CE CLR D \$pastQ
 # Outputs: Q
-FDCE_1004 11 1 5 1
+FDCE_1004 1 1 5 1
 - 109 - -46 0
 
 # Inputs: C CE D PRE \$pastQ
-- 
cgit v1.2.3


From 8f9d529929f43e6ba98f06159ae9533984c6264f Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 11 Jul 2019 13:54:40 -0700
Subject: $pastQ should be first input

---
 techlibs/xilinx/abc_xc7.box | 26 +++++++++++++-------------
 1 file changed, 13 insertions(+), 13 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
index 24512ecf7..5dc93e508 100644
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@ -62,32 +62,32 @@ RAM128X1D 7 0 17 2
 $__ABC_ASYNC 1000 0 2 1
 0 764
 
-# Inputs: C CE D R \$pastQ
+# Inputs: $pastQ C CE D R
 # Outputs: Q
 FDRE 1001 1 5 1
-- 109 -46 358 0
+0 - 0 0 0
 
-# Inputs: C CE D R \$pastQ
+# Inputs: $pastQ C CE D R
 # Outputs: Q
 FDRE_1 1002 1 5 1
-- 109 -46 358 0
+0 - 109 -46 358
 
-# Inputs: C CE CLR D \$pastQ
+# Inputs: $pastQ C CE CLR D
 # Outputs: Q
 FDCE 1003 1 5 1
-- 109 - -46 0
+0 - 109 - -46
 
-# Inputs: C CE CLR D \$pastQ
+# Inputs: $pastQ C CE CLR D
 # Outputs: Q
-FDCE_1004 1 1 5 1
-- 109 - -46 0
+FDCE_1 1004 1 5 1
+0 - 109 - -46
 
-# Inputs: C CE D PRE \$pastQ
+# Inputs: $pastQ C CE D PRE
 # Outputs: Q
 FDPE 1005 1 5 1
-- 109 -46 - 0
+0 - 109 -46 -
 
-# Inputs: C CE D PRE \$pastQ
+# Inputs: $pastQ C CE D PRE
 # Outputs: Q
 FDPE_1 1006 1 5 1
-- 109 -46 - 0
+0 - 109 -46 -
-- 
cgit v1.2.3


From 854333f2af53626e09de693f5d5c7fa107d81c74 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 11 Jul 2019 13:55:47 -0700
Subject: Propagate INIT attr

---
 techlibs/xilinx/abc_ff.v | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc_ff.v b/techlibs/xilinx/abc_ff.v
index 69013f475..19f86365a 100644
--- a/techlibs/xilinx/abc_ff.v
+++ b/techlibs/xilinx/abc_ff.v
@@ -27,7 +27,7 @@ module FDRE (output reg Q, input C, CE, D, R);
   parameter [0:0] IS_R_INVERTED = 1'b0;
   wire \$nextQ ;
   \$__ABC_FDRE #(
-    .INIT(|0),
+    .INIT(INIT),
     .IS_C_INVERTED(IS_C_INVERTED),
     .IS_D_INVERTED(IS_D_INVERTED),
     .IS_R_INVERTED(IS_R_INVERTED),
@@ -57,7 +57,7 @@ module FDCE (output reg Q, input C, CE, D, CLR);
   parameter [0:0] IS_CLR_INVERTED = 1'b0;
   wire \$nextQ , \$currQ ;
   \$__ABC_FDCE #(
-    .INIT(|0),
+    .INIT(INIT),
     .IS_C_INVERTED(IS_C_INVERTED),
     .IS_D_INVERTED(IS_D_INVERTED),
     .IS_CLR_INVERTED(IS_CLR_INVERTED),
@@ -73,7 +73,7 @@ module FDCE_1 (output reg Q, input C, CE, D, CLR);
   parameter [0:0] INIT = 1'b0;
   wire \$nextQ , \$currQ ;
   \$__ABC_FDCE_1 #(
-    .INIT(|0),
+    .INIT(INIT),
     .\$abc_flop_clk_pol (1'b1),
     .\$abc_flop_en_pol (1'b1)
   ) _TECHMAP_REPLACE_ (
@@ -90,7 +90,7 @@ module FDPE (output reg Q, input C, CE, D, PRE);
   parameter [0:0] IS_PRE_INVERTED = 1'b0;
   wire \$nextQ , \$currQ ;
   \$__ABC_FDPE #(
-    .INIT(|0),
+    .INIT(INIT),
     .IS_C_INVERTED(IS_C_INVERTED),
     .IS_D_INVERTED(IS_D_INVERTED),
     .IS_PRE_INVERTED(IS_PRE_INVERTED),
@@ -106,7 +106,7 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE);
   parameter [0:0] INIT = 1'b0;
   wire \$nextQ , \$currQ ;
   \$__ABC_FDPE_1 #(
-    .INIT(|0),
+    .INIT(INIT),
     .\$abc_flop_clk_pol (1'b1),
     .\$abc_flop_en_pol (1'b1)
   ) _TECHMAP_REPLACE_ (
-- 
cgit v1.2.3


From 1ada5681340aca5132e4a7bf8fa2d4a6e80adc59 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 11 Jul 2019 14:23:45 -0700
Subject: Revert "$pastQ should be first input"

This reverts commit 8f9d529929f43e6ba98f06159ae9533984c6264f.
---
 techlibs/xilinx/abc_xc7.box | 26 +++++++++++++-------------
 1 file changed, 13 insertions(+), 13 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
index 5dc93e508..24512ecf7 100644
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@ -62,32 +62,32 @@ RAM128X1D 7 0 17 2
 $__ABC_ASYNC 1000 0 2 1
 0 764
 
-# Inputs: $pastQ C CE D R
+# Inputs: C CE D R \$pastQ
 # Outputs: Q
 FDRE 1001 1 5 1
-0 - 0 0 0
+- 109 -46 358 0
 
-# Inputs: $pastQ C CE D R
+# Inputs: C CE D R \$pastQ
 # Outputs: Q
 FDRE_1 1002 1 5 1
-0 - 109 -46 358
+- 109 -46 358 0
 
-# Inputs: $pastQ C CE CLR D
+# Inputs: C CE CLR D \$pastQ
 # Outputs: Q
 FDCE 1003 1 5 1
-0 - 109 - -46
+- 109 - -46 0
 
-# Inputs: $pastQ C CE CLR D
+# Inputs: C CE CLR D \$pastQ
 # Outputs: Q
-FDCE_1 1004 1 5 1
-0 - 109 - -46
+FDCE_1004 1 1 5 1
+- 109 - -46 0
 
-# Inputs: $pastQ C CE D PRE
+# Inputs: C CE D PRE \$pastQ
 # Outputs: Q
 FDPE 1005 1 5 1
-0 - 109 -46 -
+- 109 -46 - 0
 
-# Inputs: $pastQ C CE D PRE
+# Inputs: C CE D PRE \$pastQ
 # Outputs: Q
 FDPE_1 1006 1 5 1
-0 - 109 -46 -
+- 109 -46 - 0
-- 
cgit v1.2.3


From 3ef927647c04bccce1d72751f6fb95ac4ac7e98b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 11 Jul 2019 14:25:47 -0700
Subject: Fix FDCE_1 box

---
 techlibs/xilinx/abc_xc7.box | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
index 24512ecf7..73f532711 100644
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@ -79,7 +79,7 @@ FDCE 1003 1 5 1
 
 # Inputs: C CE CLR D \$pastQ
 # Outputs: Q
-FDCE_1004 1 1 5 1
+FDCE_1 1004 1 5 1
 - 109 - -46 0
 
 # Inputs: C CE D PRE \$pastQ
-- 
cgit v1.2.3


From d386177e6d99ea2b3ef4b798653c0b1d7786e6b8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 11 Jul 2019 17:09:17 -0700
Subject: ABC doesn't like negative delays in flop boxes...

---
 techlibs/xilinx/abc_xc7.box | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
index 73f532711..f59cdcde8 100644
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@ -65,29 +65,29 @@ $__ABC_ASYNC 1000 0 2 1
 # Inputs: C CE D R \$pastQ
 # Outputs: Q
 FDRE 1001 1 5 1
-- 109 -46 358 0
+0 109 0 358 0
 
 # Inputs: C CE D R \$pastQ
 # Outputs: Q
 FDRE_1 1002 1 5 1
-- 109 -46 358 0
+0 109 0 358 0
 
 # Inputs: C CE CLR D \$pastQ
 # Outputs: Q
 FDCE 1003 1 5 1
-- 109 - -46 0
+0 109 764 0 0
 
 # Inputs: C CE CLR D \$pastQ
 # Outputs: Q
 FDCE_1 1004 1 5 1
-- 109 - -46 0
+0 109 764 0 0
 
 # Inputs: C CE D PRE \$pastQ
 # Outputs: Q
 FDPE 1005 1 5 1
-- 109 -46 - 0
+0 109 0 764 0
 
 # Inputs: C CE D PRE \$pastQ
 # Outputs: Q
 FDPE_1 1006 1 5 1
-- 109 -46 - 0
+0 109 0 764 0
-- 
cgit v1.2.3


From 1c9f3fadb9f60653fc9d1d7d72ba22033e077468 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 11 Jul 2019 17:17:26 -0700
Subject: Add Tsu offset to boxes, and comments

---
 techlibs/xilinx/abc_xc7.box | 17 +++++++++++------
 1 file changed, 11 insertions(+), 6 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
index f59cdcde8..044ed1bff 100644
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@ -14,6 +14,7 @@ F7MUX 1 1 3 1
 MUXF8 2 1 3 1
 104 94 273
 
+# Box containing MUXF7.[AB] + MUXF8
 # Inputs: I0 I1 I2 I3 S0 S1
 # Outputs: O
 $__MUXF78 3 1 6 1
@@ -57,37 +58,41 @@ RAM128X1D 7 0 17 2
 -    -    -   -   -   -   -   - 1009 998 839 774 605 494 450 - -
 1047 1036 877 812 643 532 478 - -    -   -   -   -   -   -   - -
 
+# Box to emulate async behaviour of FD[CP]*
 # Inputs: A S
 # Outputs: Y
 $__ABC_ASYNC 1000 0 2 1
 0 764
 
+# The following FD*.{CE,R,CLR,PRE) are offset by 46ps to
+# reflect the -46ps Tsu
+
 # Inputs: C CE D R \$pastQ
 # Outputs: Q
 FDRE 1001 1 5 1
-0 109 0 358 0
+0 155 0 404 0
 
 # Inputs: C CE D R \$pastQ
 # Outputs: Q
 FDRE_1 1002 1 5 1
-0 109 0 358 0
+0 155 0 404 0
 
 # Inputs: C CE CLR D \$pastQ
 # Outputs: Q
 FDCE 1003 1 5 1
-0 109 764 0 0
+0 155 810 0 0
 
 # Inputs: C CE CLR D \$pastQ
 # Outputs: Q
 FDCE_1 1004 1 5 1
-0 109 764 0 0
+0 155 810 0 0
 
 # Inputs: C CE D PRE \$pastQ
 # Outputs: Q
 FDPE 1005 1 5 1
-0 109 0 764 0
+0 155 0 810 0
 
 # Inputs: C CE D PRE \$pastQ
 # Outputs: Q
 FDPE_1 1006 1 5 1
-0 109 0 764 0
+0 155 0 810 0
-- 
cgit v1.2.3


From e301440a0bae76dcff159c77274c91aad40021c0 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 19 Aug 2019 09:51:49 -0700
Subject: Use attributes instead of params

---
 techlibs/xilinx/abc_ff.v | 42 ++++++++++++------------------------------
 1 file changed, 12 insertions(+), 30 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc_ff.v b/techlibs/xilinx/abc_ff.v
index 19f86365a..1d308fa96 100644
--- a/techlibs/xilinx/abc_ff.v
+++ b/techlibs/xilinx/abc_ff.v
@@ -26,13 +26,12 @@ module FDRE (output reg Q, input C, CE, D, R);
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_R_INVERTED = 1'b0;
   wire \$nextQ ;
+  (* abc_flop_clk_pol="!IS_C_INVERTED", abc_flop_en_pol=1 *)
   \$__ABC_FDRE #(
     .INIT(INIT),
     .IS_C_INVERTED(IS_C_INVERTED),
     .IS_D_INVERTED(IS_D_INVERTED),
-    .IS_R_INVERTED(IS_R_INVERTED),
-    .\$abc_flop_clk_pol (!IS_C_INVERTED),
-    .\$abc_flop_en_pol (1'b1)
+    .IS_R_INVERTED(IS_R_INVERTED)
   ) _TECHMAP_REPLACE_ (
     .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .R(R)
   );
@@ -41,9 +40,8 @@ endmodule
 module FDRE_1 (output reg Q, input C, CE, D, R);
   parameter [0:0] INIT = 1'b0;
   wire \$nextQ ;
-  \$__ABC_FDRE_1 #(.INIT(|0),
-    .\$abc_flop_clk_pol (1'b1),
-    .\$abc_flop_en_pol (1'b1)
+  (* abc_flop_clk_pol=1, abc_flop_en_pol=1 *)
+  \$__ABC_FDRE_1 #(.INIT(|0)
   ) _TECHMAP_REPLACE_ (
     .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .R(R)
   );
@@ -56,13 +54,12 @@ module FDCE (output reg Q, input C, CE, D, CLR);
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_CLR_INVERTED = 1'b0;
   wire \$nextQ , \$currQ ;
+  (* abc_flop_clk_pol="!IS_C_INVERTED", abc_flop_en_pol=1 *)
   \$__ABC_FDCE #(
     .INIT(INIT),
     .IS_C_INVERTED(IS_C_INVERTED),
     .IS_D_INVERTED(IS_D_INVERTED),
-    .IS_CLR_INVERTED(IS_CLR_INVERTED),
-    .\$abc_flop_clk_pol (!IS_C_INVERTED),
-    .\$abc_flop_en_pol (1'b1)
+    .IS_CLR_INVERTED(IS_CLR_INVERTED)
   ) _TECHMAP_REPLACE_ (
     .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR)
   );
@@ -72,10 +69,9 @@ endmodule
 module FDCE_1 (output reg Q, input C, CE, D, CLR);
   parameter [0:0] INIT = 1'b0;
   wire \$nextQ , \$currQ ;
+  (* abc_flop_clk_pol=1, abc_flop_en_pol=1 *)
   \$__ABC_FDCE_1 #(
-    .INIT(INIT),
-    .\$abc_flop_clk_pol (1'b1),
-    .\$abc_flop_en_pol (1'b1)
+    .INIT(INIT)
   ) _TECHMAP_REPLACE_ (
     .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR)
   );
@@ -89,13 +85,12 @@ module FDPE (output reg Q, input C, CE, D, PRE);
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_PRE_INVERTED = 1'b0;
   wire \$nextQ , \$currQ ;
+  (* abc_flop_clk_pol="!IS_C_INVERTED", abc_flop_en_pol=1 *)
   \$__ABC_FDPE #(
     .INIT(INIT),
     .IS_C_INVERTED(IS_C_INVERTED),
     .IS_D_INVERTED(IS_D_INVERTED),
-    .IS_PRE_INVERTED(IS_PRE_INVERTED),
-    .\$abc_flop_clk_pol (!IS_C_INVERTED),
-    .\$abc_flop_en_pol (1'b1)
+    .IS_PRE_INVERTED(IS_PRE_INVERTED)
   ) _TECHMAP_REPLACE_ (
     .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE)
   );
@@ -105,10 +100,9 @@ endmodule
 module FDPE_1 (output reg Q, input C, CE, D, PRE);
   parameter [0:0] INIT = 1'b0;
   wire \$nextQ , \$currQ ;
+  (* abc_flop_clk_pol=1, abc_flop_en_pol=1 *)
   \$__ABC_FDPE_1 #(
-    .INIT(INIT),
-    .\$abc_flop_clk_pol (1'b1),
-    .\$abc_flop_en_pol (1'b1)
+    .INIT(INIT)
   ) _TECHMAP_REPLACE_ (
     .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE)
   );
@@ -134,8 +128,6 @@ module \$__ABC_FDRE ((* abc_flop_q *)   output Q,
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_R_INVERTED = 1'b0;
-  parameter \$abc_flop_clk_pol = ~IS_C_INVERTED;
-  parameter \$abc_flop_en_pol = 1'b1;
   assign Q = (R ^ IS_R_INVERTED) ? 1'b0 : (CE ? (D ^ IS_D_INVERTED) : \$pastQ );
 endmodule
 
@@ -146,8 +138,6 @@ module \$__ABC_FDRE_1 ((* abc_flop_q *)   output Q,
                        (* abc_flop_d *)   input D,
                        input R, \$pastQ );
   parameter [0:0] INIT = 1'b0;
-  parameter \$abc_flop_clk_pol = 1'b0;
-  parameter \$abc_flop_en_pol = 1'b1;
   assign Q = R ? 1'b0 : (CE ? D : \$pastQ );
 endmodule
 
@@ -161,8 +151,6 @@ module \$__ABC_FDCE ((* abc_flop_q *)   output Q,
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_CLR_INVERTED = 1'b0;
-  parameter \$abc_flop_clk_pol = ~IS_C_INVERTED;
-  parameter \$abc_flop_en_pol = 1'b1;
   assign Q = (CE && !(CLR ^ IS_CLR_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
 endmodule
 
@@ -173,8 +161,6 @@ module \$__ABC_FDCE_1 ((* abc_flop_q *)   output Q,
                        (* abc_flop_d *)   input D,
                        input CLR, \$pastQ );
   parameter [0:0] INIT = 1'b0;
-  parameter \$abc_flop_clk_pol = 1'b0;
-  parameter \$abc_flop_en_inv = 1'b1;
   assign Q = (CE && !CLR) ? D : \$pastQ ;
 endmodule
 
@@ -188,8 +174,6 @@ module \$__ABC_FDPE ((* abc_flop_q *)   output Q,
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_PRE_INVERTED = 1'b0;
-  parameter \$abc_flop_clk_pol = ~IS_C_INVERTED;
-  parameter \$abc_flop_en_pol = 1'b1;
   assign Q = (CE && !(PRE ^ IS_PRE_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
 endmodule
 
@@ -200,8 +184,6 @@ module \$__ABC_FDPE_1 ((* abc_flop_q *)   output Q,
                        (* abc_flop_d *)   input D,
                        input PRE, \$pastQ );
   parameter [0:0] INIT = 1'b0;
-  parameter \$abc_flop_clk_pol = 1'b0;
-  parameter \$abc_flop_en_pol = 1'b1;
   assign Q = (CE && !PRE) ? D : \$pastQ ;
 endmodule
 
-- 
cgit v1.2.3


From ba2261e21a18b969473f228b5f55bd5612558ed8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 19 Aug 2019 11:18:33 -0700
Subject: Move from cell attr to module attr

---
 techlibs/xilinx/abc_ff.v | 18 ++++++------------
 1 file changed, 6 insertions(+), 12 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc_ff.v b/techlibs/xilinx/abc_ff.v
index 1d308fa96..117820f0d 100644
--- a/techlibs/xilinx/abc_ff.v
+++ b/techlibs/xilinx/abc_ff.v
@@ -26,7 +26,6 @@ module FDRE (output reg Q, input C, CE, D, R);
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_R_INVERTED = 1'b0;
   wire \$nextQ ;
-  (* abc_flop_clk_pol="!IS_C_INVERTED", abc_flop_en_pol=1 *)
   \$__ABC_FDRE #(
     .INIT(INIT),
     .IS_C_INVERTED(IS_C_INVERTED),
@@ -40,7 +39,6 @@ endmodule
 module FDRE_1 (output reg Q, input C, CE, D, R);
   parameter [0:0] INIT = 1'b0;
   wire \$nextQ ;
-  (* abc_flop_clk_pol=1, abc_flop_en_pol=1 *)
   \$__ABC_FDRE_1 #(.INIT(|0)
   ) _TECHMAP_REPLACE_ (
     .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .R(R)
@@ -54,7 +52,6 @@ module FDCE (output reg Q, input C, CE, D, CLR);
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_CLR_INVERTED = 1'b0;
   wire \$nextQ , \$currQ ;
-  (* abc_flop_clk_pol="!IS_C_INVERTED", abc_flop_en_pol=1 *)
   \$__ABC_FDCE #(
     .INIT(INIT),
     .IS_C_INVERTED(IS_C_INVERTED),
@@ -69,7 +66,6 @@ endmodule
 module FDCE_1 (output reg Q, input C, CE, D, CLR);
   parameter [0:0] INIT = 1'b0;
   wire \$nextQ , \$currQ ;
-  (* abc_flop_clk_pol=1, abc_flop_en_pol=1 *)
   \$__ABC_FDCE_1 #(
     .INIT(INIT)
   ) _TECHMAP_REPLACE_ (
@@ -85,7 +81,6 @@ module FDPE (output reg Q, input C, CE, D, PRE);
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_PRE_INVERTED = 1'b0;
   wire \$nextQ , \$currQ ;
-  (* abc_flop_clk_pol="!IS_C_INVERTED", abc_flop_en_pol=1 *)
   \$__ABC_FDPE #(
     .INIT(INIT),
     .IS_C_INVERTED(IS_C_INVERTED),
@@ -100,7 +95,6 @@ endmodule
 module FDPE_1 (output reg Q, input C, CE, D, PRE);
   parameter [0:0] INIT = 1'b0;
   wire \$nextQ , \$currQ ;
-  (* abc_flop_clk_pol=1, abc_flop_en_pol=1 *)
   \$__ABC_FDPE_1 #(
     .INIT(INIT)
   ) _TECHMAP_REPLACE_ (
@@ -118,7 +112,7 @@ endmodule
 module \$__ABC_ASYNC (input A, S, output Y);
 endmodule
 
-(* abc_box_id = 1001, lib_whitebox, abc_flop = "FDRE" *)
+(* abc_box_id=1001, lib_whitebox, abc_flop="FDRE", abc_flop_clk_pol="!IS_C_INVERTED", abc_flop_en_pol=1 *)
 module \$__ABC_FDRE ((* abc_flop_q *)   output Q,
                      (* abc_flop_clk *) input C,
                      (* abc_flop_en *)  input CE,
@@ -131,7 +125,7 @@ module \$__ABC_FDRE ((* abc_flop_q *)   output Q,
   assign Q = (R ^ IS_R_INVERTED) ? 1'b0 : (CE ? (D ^ IS_D_INVERTED) : \$pastQ );
 endmodule
 
-(* abc_box_id = 1002, lib_whitebox, abc_flop = "FDRE_1" *)
+(* abc_box_id = 1002, lib_whitebox, abc_flop = "FDRE_1", abc_flop_clk_pol=1, abc_flop_en_pol=1 *)
 module \$__ABC_FDRE_1 ((* abc_flop_q *)   output Q,
                        (* abc_flop_clk *) input C,
                        (* abc_flop_en *)  input CE,
@@ -141,7 +135,7 @@ module \$__ABC_FDRE_1 ((* abc_flop_q *)   output Q,
   assign Q = R ? 1'b0 : (CE ? D : \$pastQ );
 endmodule
 
-(* abc_box_id = 1003, lib_whitebox, abc_flop = "FDCE" *)
+(* abc_box_id = 1003, lib_whitebox, abc_flop = "FDCE", abc_flop_clk_pol="!IS_C_INVERTED", abc_flop_en_pol=1 *)
 module \$__ABC_FDCE ((* abc_flop_q *)   output Q,
                      (* abc_flop_clk *) input C,
                      (* abc_flop_en *)  input CE,
@@ -154,7 +148,7 @@ module \$__ABC_FDCE ((* abc_flop_q *)   output Q,
   assign Q = (CE && !(CLR ^ IS_CLR_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
 endmodule
 
-(* abc_box_id = 1004, lib_whitebox, abc_flop = "FDCE_1" *)
+(* abc_box_id = 1004, lib_whitebox, abc_flop = "FDCE_1", abc_flop_clk_pol=1, abc_flop_en_pol=1 *)
 module \$__ABC_FDCE_1 ((* abc_flop_q *)   output Q,
                        (* abc_flop_clk *) input C,
                        (* abc_flop_en *)  input CE,
@@ -164,7 +158,7 @@ module \$__ABC_FDCE_1 ((* abc_flop_q *)   output Q,
   assign Q = (CE && !CLR) ? D : \$pastQ ;
 endmodule
 
-(* abc_box_id = 1005, lib_whitebox, abc_flop = "FDPE" *)
+(* abc_box_id=1005, lib_whitebox, abc_flop="FDPE", abc_flop_clk_pol="!IS_C_INVERTED", abc_flop_en_pol=1 *)
 module \$__ABC_FDPE ((* abc_flop_q *)   output Q,
                      (* abc_flop_clk *) input C,
                      (* abc_flop_en *)  input CE,
@@ -177,7 +171,7 @@ module \$__ABC_FDPE ((* abc_flop_q *)   output Q,
   assign Q = (CE && !(PRE ^ IS_PRE_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
 endmodule
 
-(* abc_box_id = 1006, lib_whitebox, abc_flop = "FDPE_1" *)
+(* abc_box_id=1006, lib_whitebox, abc_flop="FDPE_1", abc_flop_clk_pol=1, abc_flop_en_pol=1 *)
 module \$__ABC_FDPE_1 ((* abc_flop_q *)   output Q,
                        (* abc_flop_clk *) input C,
                        (* abc_flop_en *)  input CE,
-- 
cgit v1.2.3


From f25837f8e8482036a761fc631f7f79e5a2c777c5 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 19 Aug 2019 11:31:40 -0700
Subject: Update box timings

---
 techlibs/xilinx/abc_xc7.box | 15 +++++++++------
 1 file changed, 9 insertions(+), 6 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
index 044ed1bff..16040662c 100644
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@ -1,4 +1,5 @@
 # Max delays from https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf
+#                 https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf
 
 # NB: Inputs/Outputs must be ordered alphabetically
 #     (with exceptions for carry in/out)
@@ -66,33 +67,35 @@ $__ABC_ASYNC 1000 0 2 1
 
 # The following FD*.{CE,R,CLR,PRE) are offset by 46ps to
 # reflect the -46ps Tsu
+# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L237-L251
+# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L265-L277
 
 # Inputs: C CE D R \$pastQ
 # Outputs: Q
 FDRE 1001 1 5 1
-0 155 0 404 0
+0 151 0 446 0
 
 # Inputs: C CE D R \$pastQ
 # Outputs: Q
 FDRE_1 1002 1 5 1
-0 155 0 404 0
+0 151 0 446 0
 
 # Inputs: C CE CLR D \$pastQ
 # Outputs: Q
 FDCE 1003 1 5 1
-0 155 810 0 0
+0 151 806 0 0
 
 # Inputs: C CE CLR D \$pastQ
 # Outputs: Q
 FDCE_1 1004 1 5 1
-0 155 810 0 0
+0 151 806 0 0
 
 # Inputs: C CE D PRE \$pastQ
 # Outputs: Q
 FDPE 1005 1 5 1
-0 155 0 810 0
+0 151 0 806 0
 
 # Inputs: C CE D PRE \$pastQ
 # Outputs: Q
 FDPE_1 1006 1 5 1
-0 155 0 810 0
+0 151 0 806 0
-- 
cgit v1.2.3


From d02ef8c73f90b345b56f2e1f5f8a3f96a92bdf74 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 19 Aug 2019 11:32:18 -0700
Subject:  Add 'abc_arrival' attribute for flop outputs

---
 techlibs/xilinx/abc_ff.v | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc_ff.v b/techlibs/xilinx/abc_ff.v
index 117820f0d..66d9573d3 100644
--- a/techlibs/xilinx/abc_ff.v
+++ b/techlibs/xilinx/abc_ff.v
@@ -113,7 +113,7 @@ module \$__ABC_ASYNC (input A, S, output Y);
 endmodule
 
 (* abc_box_id=1001, lib_whitebox, abc_flop="FDRE", abc_flop_clk_pol="!IS_C_INVERTED", abc_flop_en_pol=1 *)
-module \$__ABC_FDRE ((* abc_flop_q *)   output Q,
+module \$__ABC_FDRE ((* abc_flop_q, abc_arrival=303 *) output Q,
                      (* abc_flop_clk *) input C,
                      (* abc_flop_en *)  input CE,
                      (* abc_flop_d *)   input D,
@@ -126,7 +126,7 @@ module \$__ABC_FDRE ((* abc_flop_q *)   output Q,
 endmodule
 
 (* abc_box_id = 1002, lib_whitebox, abc_flop = "FDRE_1", abc_flop_clk_pol=1, abc_flop_en_pol=1 *)
-module \$__ABC_FDRE_1 ((* abc_flop_q *)   output Q,
+module \$__ABC_FDRE_1 ((* abc_flop_q, abc_arrival=303 *) output Q,
                        (* abc_flop_clk *) input C,
                        (* abc_flop_en *)  input CE,
                        (* abc_flop_d *)   input D,
@@ -136,7 +136,7 @@ module \$__ABC_FDRE_1 ((* abc_flop_q *)   output Q,
 endmodule
 
 (* abc_box_id = 1003, lib_whitebox, abc_flop = "FDCE", abc_flop_clk_pol="!IS_C_INVERTED", abc_flop_en_pol=1 *)
-module \$__ABC_FDCE ((* abc_flop_q *)   output Q,
+module \$__ABC_FDCE ((* abc_flop_q, abc_arrival=303 *) output Q,
                      (* abc_flop_clk *) input C,
                      (* abc_flop_en *)  input CE,
                      (* abc_flop_d *)   input D,
@@ -149,7 +149,7 @@ module \$__ABC_FDCE ((* abc_flop_q *)   output Q,
 endmodule
 
 (* abc_box_id = 1004, lib_whitebox, abc_flop = "FDCE_1", abc_flop_clk_pol=1, abc_flop_en_pol=1 *)
-module \$__ABC_FDCE_1 ((* abc_flop_q *)   output Q,
+module \$__ABC_FDCE_1 ((* abc_flop_q, abc_arrival=303 *) output Q,
                        (* abc_flop_clk *) input C,
                        (* abc_flop_en *)  input CE,
                        (* abc_flop_d *)   input D,
@@ -159,7 +159,7 @@ module \$__ABC_FDCE_1 ((* abc_flop_q *)   output Q,
 endmodule
 
 (* abc_box_id=1005, lib_whitebox, abc_flop="FDPE", abc_flop_clk_pol="!IS_C_INVERTED", abc_flop_en_pol=1 *)
-module \$__ABC_FDPE ((* abc_flop_q *)   output Q,
+module \$__ABC_FDPE ((* abc_flop_q, abc_arrival=303 *) output Q,
                      (* abc_flop_clk *) input C,
                      (* abc_flop_en *)  input CE,
                      (* abc_flop_d *)   input D,
@@ -172,7 +172,7 @@ module \$__ABC_FDPE ((* abc_flop_q *)   output Q,
 endmodule
 
 (* abc_box_id=1006, lib_whitebox, abc_flop="FDPE_1", abc_flop_clk_pol=1, abc_flop_en_pol=1 *)
-module \$__ABC_FDPE_1 ((* abc_flop_q *)   output Q,
+module \$__ABC_FDPE_1 ((* abc_flop_q, abc_arrival=303 *) output Q,
                        (* abc_flop_clk *) input C,
                        (* abc_flop_en *)  input CE,
                        (* abc_flop_d *)   input D,
-- 
cgit v1.2.3


From 2f863660870e9ef66c5fcccbf711cf9eb46849c0 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 19 Aug 2019 12:39:22 -0700
Subject: Add reference to source of Tclktoq timing

---
 techlibs/xilinx/abc_ff.v | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc_ff.v b/techlibs/xilinx/abc_ff.v
index 66d9573d3..36e1a08e4 100644
--- a/techlibs/xilinx/abc_ff.v
+++ b/techlibs/xilinx/abc_ff.v
@@ -20,6 +20,8 @@
 
 // ============================================================================
 
+// Max delays from https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L237-L251
+
 module FDRE (output reg Q, input C, CE, D, R);
   parameter [0:0] INIT = 1'b0;
   parameter [0:0] IS_C_INVERTED = 1'b0;
-- 
cgit v1.2.3


From b71212ddeaf099fbbf78d65cf64b3f6f75f80aea Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 19 Aug 2019 12:46:35 -0700
Subject: Add BRAM arrival times

---
 techlibs/xilinx/xc7_brams_bb.v | 18 ++++++++++--------
 1 file changed, 10 insertions(+), 8 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/xc7_brams_bb.v b/techlibs/xilinx/xc7_brams_bb.v
index a682ba4a7..0e8cb406c 100644
--- a/techlibs/xilinx/xc7_brams_bb.v
+++ b/techlibs/xilinx/xc7_brams_bb.v
@@ -1,3 +1,5 @@
+// Max delays from https://github.com/SymbiFlow/prjxray-db/blob/f8e0364116b2983ac72a3dc8c509ea1cc79e2e3d/artix7/timings/BRAM_L.sdf#L138-L147
+
 module RAMB18E1 (
 	input CLKARDCLK,
 	input CLKBWRCLK,
@@ -19,10 +21,10 @@ module RAMB18E1 (
 	input [1:0] WEA,
 	input [3:0] WEBWE,
 
-	output [15:0] DOADO,
-	output [15:0] DOBDO,
-	output [1:0] DOPADOP,
-	output [1:0] DOPBDOP
+	(* abc_arrival=2454 *) output [15:0] DOADO,
+	(* abc_arrival=2454 *) output [15:0] DOBDO,
+	(* abc_arrival=2454 *) output [1:0] DOPADOP,
+	(* abc_arrival=2454 *) output [1:0] DOPBDOP
 );
 	parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 	parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
@@ -143,10 +145,10 @@ module RAMB36E1 (
 	input [3:0] WEA,
 	input [7:0] WEBWE,
 
-	output [31:0] DOADO,
-	output [31:0] DOBDO,
-	output [3:0] DOPADOP,
-	output [3:0] DOPBDOP
+	(* abc_arrival=2454 *) output [31:0] DOADO,
+	(* abc_arrival=2454 *) output [31:0] DOBDO,
+	(* abc_arrival=2454 *) output [3:0] DOPADOP,
+	(* abc_arrival=2454 *) output [3:0] DOPBDOP
 );
 	parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 	parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-- 
cgit v1.2.3


From 526e0813427aae24b9df2eacbbb8c067bdfd5eec Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 19 Aug 2019 15:15:43 -0700
Subject: Add arrival times for SRL outputs

---
 techlibs/xilinx/cells_sim.v | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 910d0e246..e5d9f480b 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -353,7 +353,8 @@ module RAM128X1D (
 endmodule
 
 module SRL16E (
-  output Q,
+  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
+  (* abc_arrival=1472 *) output Q,
   input A0, A1, A2, A3, CE, CLK, D
 );
   parameter [15:0] INIT = 16'h0000;
@@ -371,8 +372,9 @@ module SRL16E (
 endmodule
 
 module SRLC32E (
-  output Q,
-  output Q31,
+  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
+  (* abc_arrival=1472 *) output Q,
+  (* abc_arrival=1114 *) output Q31,
   input [4:0] A,
   input CE, CLK, D
 );
-- 
cgit v1.2.3


From be9e4f1b674ef4fb3f02e99efcfda04ea27b2a68 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 20 Aug 2019 12:39:11 -0700
Subject: Use abc_{map,unmap,model}.v

---
 techlibs/xilinx/Makefile.inc    |   4 +-
 techlibs/xilinx/abc_ff.v        | 186 ----------------------------------------
 techlibs/xilinx/abc_map.v       | 120 ++++++++++++++++++++++++++
 techlibs/xilinx/abc_model.v     | 148 ++++++++++++++++++++++++++++++++
 techlibs/xilinx/abc_unmap.v     | 140 ++++++++++++++++++++++++++++++
 techlibs/xilinx/cells_map.v     |   2 -
 techlibs/xilinx/cells_sim.v     |   8 --
 techlibs/xilinx/synth_xilinx.cc |  12 +--
 8 files changed, 417 insertions(+), 203 deletions(-)
 delete mode 100644 techlibs/xilinx/abc_ff.v
 create mode 100644 techlibs/xilinx/abc_map.v
 create mode 100644 techlibs/xilinx/abc_model.v
 create mode 100644 techlibs/xilinx/abc_unmap.v

(limited to 'techlibs')

diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc
index a9e0c5c7b..a11880c4d 100644
--- a/techlibs/xilinx/Makefile.inc
+++ b/techlibs/xilinx/Makefile.inc
@@ -39,7 +39,9 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/mux_map.v))
 
-$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_ff.v))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_map.v))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_unmap.v))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_model.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.box))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.lut))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7_nowide.lut))
diff --git a/techlibs/xilinx/abc_ff.v b/techlibs/xilinx/abc_ff.v
deleted file mode 100644
index 36e1a08e4..000000000
--- a/techlibs/xilinx/abc_ff.v
+++ /dev/null
@@ -1,186 +0,0 @@
-/*
- *  yosys -- Yosys Open SYnthesis Suite
- *
- *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *                2019  Eddie Hung    <eddie@fpgeh.com>
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-// ============================================================================
-
-// Max delays from https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L237-L251
-
-module FDRE (output reg Q, input C, CE, D, R);
-  parameter [0:0] INIT = 1'b0;
-  parameter [0:0] IS_C_INVERTED = 1'b0;
-  parameter [0:0] IS_D_INVERTED = 1'b0;
-  parameter [0:0] IS_R_INVERTED = 1'b0;
-  wire \$nextQ ;
-  \$__ABC_FDRE #(
-    .INIT(INIT),
-    .IS_C_INVERTED(IS_C_INVERTED),
-    .IS_D_INVERTED(IS_D_INVERTED),
-    .IS_R_INVERTED(IS_R_INVERTED)
-  ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .R(R)
-  );
-  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
-endmodule
-module FDRE_1 (output reg Q, input C, CE, D, R);
-  parameter [0:0] INIT = 1'b0;
-  wire \$nextQ ;
-  \$__ABC_FDRE_1 #(.INIT(|0)
-  ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .R(R)
-  );
-  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
-endmodule
-
-module FDCE (output reg Q, input C, CE, D, CLR);
-  parameter [0:0] INIT = 1'b0;
-  parameter [0:0] IS_C_INVERTED = 1'b0;
-  parameter [0:0] IS_D_INVERTED = 1'b0;
-  parameter [0:0] IS_CLR_INVERTED = 1'b0;
-  wire \$nextQ , \$currQ ;
-  \$__ABC_FDCE #(
-    .INIT(INIT),
-    .IS_C_INVERTED(IS_C_INVERTED),
-    .IS_D_INVERTED(IS_D_INVERTED),
-    .IS_CLR_INVERTED(IS_CLR_INVERTED)
-  ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR)
-  );
-  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
-  \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(CLR), .Y(Q));
-endmodule
-module FDCE_1 (output reg Q, input C, CE, D, CLR);
-  parameter [0:0] INIT = 1'b0;
-  wire \$nextQ , \$currQ ;
-  \$__ABC_FDCE_1 #(
-    .INIT(INIT)
-  ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR)
-  );
-  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
-  \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(CLR), .Y(Q));
-endmodule
-
-module FDPE (output reg Q, input C, CE, D, PRE);
-  parameter [0:0] INIT = 1'b0;
-  parameter [0:0] IS_C_INVERTED = 1'b0;
-  parameter [0:0] IS_D_INVERTED = 1'b0;
-  parameter [0:0] IS_PRE_INVERTED = 1'b0;
-  wire \$nextQ , \$currQ ;
-  \$__ABC_FDPE #(
-    .INIT(INIT),
-    .IS_C_INVERTED(IS_C_INVERTED),
-    .IS_D_INVERTED(IS_D_INVERTED),
-    .IS_PRE_INVERTED(IS_PRE_INVERTED)
-  ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE)
-  );
-  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
-  \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(PRE), .Y(Q));
-endmodule
-module FDPE_1 (output reg Q, input C, CE, D, PRE);
-  parameter [0:0] INIT = 1'b0;
-  wire \$nextQ , \$currQ ;
-  \$__ABC_FDPE_1 #(
-    .INIT(INIT)
-  ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE)
-  );
-  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
-  \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(PRE), .Y(Q));
-endmodule
-
-`ifndef _ABC
-module \$__ABC_FF_ (input C, D, output Q);
-endmodule
-
-(* abc_box_id = 1000 *)
-module \$__ABC_ASYNC (input A, S, output Y);
-endmodule
-
-(* abc_box_id=1001, lib_whitebox, abc_flop="FDRE", abc_flop_clk_pol="!IS_C_INVERTED", abc_flop_en_pol=1 *)
-module \$__ABC_FDRE ((* abc_flop_q, abc_arrival=303 *) output Q,
-                     (* abc_flop_clk *) input C,
-                     (* abc_flop_en *)  input CE,
-                     (* abc_flop_d *)   input D,
-                     input R, \$pastQ );
-  parameter [0:0] INIT = 1'b0;
-  parameter [0:0] IS_C_INVERTED = 1'b0;
-  parameter [0:0] IS_D_INVERTED = 1'b0;
-  parameter [0:0] IS_R_INVERTED = 1'b0;
-  assign Q = (R ^ IS_R_INVERTED) ? 1'b0 : (CE ? (D ^ IS_D_INVERTED) : \$pastQ );
-endmodule
-
-(* abc_box_id = 1002, lib_whitebox, abc_flop = "FDRE_1", abc_flop_clk_pol=1, abc_flop_en_pol=1 *)
-module \$__ABC_FDRE_1 ((* abc_flop_q, abc_arrival=303 *) output Q,
-                       (* abc_flop_clk *) input C,
-                       (* abc_flop_en *)  input CE,
-                       (* abc_flop_d *)   input D,
-                       input R, \$pastQ );
-  parameter [0:0] INIT = 1'b0;
-  assign Q = R ? 1'b0 : (CE ? D : \$pastQ );
-endmodule
-
-(* abc_box_id = 1003, lib_whitebox, abc_flop = "FDCE", abc_flop_clk_pol="!IS_C_INVERTED", abc_flop_en_pol=1 *)
-module \$__ABC_FDCE ((* abc_flop_q, abc_arrival=303 *) output Q,
-                     (* abc_flop_clk *) input C,
-                     (* abc_flop_en *)  input CE,
-                     (* abc_flop_d *)   input D,
-                     input CLR, \$pastQ );
-  parameter [0:0] INIT = 1'b0;
-  parameter [0:0] IS_C_INVERTED = 1'b0;
-  parameter [0:0] IS_D_INVERTED = 1'b0;
-  parameter [0:0] IS_CLR_INVERTED = 1'b0;
-  assign Q = (CE && !(CLR ^ IS_CLR_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
-endmodule
-
-(* abc_box_id = 1004, lib_whitebox, abc_flop = "FDCE_1", abc_flop_clk_pol=1, abc_flop_en_pol=1 *)
-module \$__ABC_FDCE_1 ((* abc_flop_q, abc_arrival=303 *) output Q,
-                       (* abc_flop_clk *) input C,
-                       (* abc_flop_en *)  input CE,
-                       (* abc_flop_d *)   input D,
-                       input CLR, \$pastQ );
-  parameter [0:0] INIT = 1'b0;
-  assign Q = (CE && !CLR) ? D : \$pastQ ;
-endmodule
-
-(* abc_box_id=1005, lib_whitebox, abc_flop="FDPE", abc_flop_clk_pol="!IS_C_INVERTED", abc_flop_en_pol=1 *)
-module \$__ABC_FDPE ((* abc_flop_q, abc_arrival=303 *) output Q,
-                     (* abc_flop_clk *) input C,
-                     (* abc_flop_en *)  input CE,
-                     (* abc_flop_d *)   input D,
-                     input PRE, \$pastQ );
-  parameter [0:0] INIT = 1'b0;
-  parameter [0:0] IS_C_INVERTED = 1'b0;
-  parameter [0:0] IS_D_INVERTED = 1'b0;
-  parameter [0:0] IS_PRE_INVERTED = 1'b0;
-  assign Q = (CE && !(PRE ^ IS_PRE_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
-endmodule
-
-(* abc_box_id=1006, lib_whitebox, abc_flop="FDPE_1", abc_flop_clk_pol=1, abc_flop_en_pol=1 *)
-module \$__ABC_FDPE_1 ((* abc_flop_q, abc_arrival=303 *) output Q,
-                       (* abc_flop_clk *) input C,
-                       (* abc_flop_en *)  input CE,
-                       (* abc_flop_d *)   input D,
-                       input PRE, \$pastQ );
-  parameter [0:0] INIT = 1'b0;
-  assign Q = (CE && !PRE) ? D : \$pastQ ;
-endmodule
-
-`endif
diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v
new file mode 100644
index 000000000..99e1fe127
--- /dev/null
+++ b/techlibs/xilinx/abc_map.v
@@ -0,0 +1,120 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *                2019  Eddie Hung    <eddie@fpgeh.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+// ============================================================================
+
+// Max delays from https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L237-L251
+
+module FDRE (output reg Q, input C, CE, D, R);
+  parameter [0:0] INIT = 1'b0;
+  parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  parameter [0:0] IS_R_INVERTED = 1'b0;
+  wire \$nextQ ;
+  \$__ABC_FDRE #(
+    .INIT(INIT),
+    .IS_C_INVERTED(IS_C_INVERTED),
+    .IS_D_INVERTED(IS_D_INVERTED),
+    .IS_R_INVERTED(IS_R_INVERTED),
+    .CLK_POLARITY(!IS_C_INVERTED),
+    .EN_POLARITY(1'b1)
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .R(R)
+  );
+  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
+endmodule
+module FDRE_1 (output reg Q, input C, CE, D, R);
+  parameter [0:0] INIT = 1'b0;
+  wire \$nextQ ;
+  \$__ABC_FDRE_1 #(
+      .INIT(|0),
+    .CLK_POLARITY(1'b0),
+    .EN_POLARITY(1'b1)
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .R(R)
+  );
+  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
+endmodule
+
+module FDCE (output reg Q, input C, CE, D, CLR);
+  parameter [0:0] INIT = 1'b0;
+  parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  parameter [0:0] IS_CLR_INVERTED = 1'b0;
+  wire \$nextQ , \$currQ ;
+  \$__ABC_FDCE #(
+    .INIT(INIT),
+    .IS_C_INVERTED(IS_C_INVERTED),
+    .IS_D_INVERTED(IS_D_INVERTED),
+    .IS_CLR_INVERTED(IS_CLR_INVERTED),
+    .CLK_POLARITY(!IS_C_INVERTED),
+    .EN_POLARITY(1'b1)
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR)
+  );
+  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
+  \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(CLR), .Y(Q));
+endmodule
+module FDCE_1 (output reg Q, input C, CE, D, CLR);
+  parameter [0:0] INIT = 1'b0;
+  wire \$nextQ , \$currQ ;
+  \$__ABC_FDCE_1 #(
+    .INIT(INIT),
+    .CLK_POLARITY(1'b0),
+    .EN_POLARITY(1'b1)
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR)
+  );
+  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
+  \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(CLR), .Y(Q));
+endmodule
+
+module FDPE (output reg Q, input C, CE, D, PRE);
+  parameter [0:0] INIT = 1'b0;
+  parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  parameter [0:0] IS_PRE_INVERTED = 1'b0;
+  wire \$nextQ , \$currQ ;
+  \$__ABC_FDPE #(
+    .INIT(INIT),
+    .IS_C_INVERTED(IS_C_INVERTED),
+    .IS_D_INVERTED(IS_D_INVERTED),
+    .IS_PRE_INVERTED(IS_PRE_INVERTED),
+    .CLK_POLARITY(!IS_C_INVERTED),
+    .EN_POLARITY(1'b1)
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE)
+  );
+  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
+  \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(PRE), .Y(Q));
+endmodule
+module FDPE_1 (output reg Q, input C, CE, D, PRE);
+  parameter [0:0] INIT = 1'b0;
+  wire \$nextQ , \$currQ ;
+  \$__ABC_FDPE_1 #(
+    .INIT(INIT),
+    .CLK_POLARITY(1'b0),
+    .EN_POLARITY(1'b1)
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE)
+  );
+  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
+  \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(PRE), .Y(Q));
+endmodule
diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc_model.v
new file mode 100644
index 000000000..41c232650
--- /dev/null
+++ b/techlibs/xilinx/abc_model.v
@@ -0,0 +1,148 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *                2019  Eddie Hung    <eddie@fpgeh.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+// ============================================================================
+
+(* abc_box_id = 3, lib_whitebox *)
+module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
+  assign O = S1 ? (S0 ? I3 : I2)
+                : (S0 ? I1 : I0);
+endmodule
+
+module \$__ABC_FF_ (input C, D, output Q);
+endmodule
+
+(* abc_box_id = 1000 *)
+module \$__ABC_ASYNC (input A, S, output Y);
+endmodule
+
+(* abc_box_id=1001, lib_whitebox, abc_flop *)
+module \$__ABC_FDRE ((* abc_flop_q, abc_arrival=303 *) output Q,
+                     (* abc_flop_clk *) input C,
+                     (* abc_flop_en *)  input CE,
+                     (* abc_flop_d *)   input D,
+                     input R, \$pastQ );
+  parameter [0:0] INIT = 1'b0;
+  parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  parameter [0:0] IS_R_INVERTED = 1'b0;
+  parameter CLK_POLARITY = !IS_C_INVERTED;
+  parameter EN_POLARITY = 1'b1;
+  assign Q = (R ^ IS_R_INVERTED) ? 1'b0 : (CE ? (D ^ IS_D_INVERTED) : \$pastQ );
+endmodule
+
+(* abc_box_id=1002, lib_whitebox, abc_flop *)
+module \$__ABC_FDRE_1 ((* abc_flop_q, abc_arrival=303 *) output Q,
+                       (* abc_flop_clk *) input C,
+                       (* abc_flop_en *)  input CE,
+                       (* abc_flop_d *)   input D,
+                       input R, \$pastQ );
+  parameter [0:0] INIT = 1'b0;
+  parameter CLK_POLARITY = 1'b0;
+  parameter EN_POLARITY = 1'b1;
+  assign Q = R ? 1'b0 : (CE ? D : \$pastQ );
+endmodule
+
+(* abc_box_id=1003, lib_whitebox, abc_flop *)
+module \$__ABC_FDCE ((* abc_flop_q, abc_arrival=303 *) output Q,
+                     (* abc_flop_clk *) input C,
+                     (* abc_flop_en *)  input CE,
+                     (* abc_flop_d *)   input D,
+                     input CLR, \$pastQ );
+  parameter [0:0] INIT = 1'b0;
+  parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  parameter [0:0] IS_CLR_INVERTED = 1'b0;
+  parameter CLK_POLARITY = !IS_C_INVERTED;
+  parameter EN_POLARITY = 1'b1;
+  assign Q = (CE && !(CLR ^ IS_CLR_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
+endmodule
+
+(* abc_box_id=1004, lib_whitebox, abc_flop *)
+module \$__ABC_FDCE_1 ((* abc_flop_q, abc_arrival=303 *) output Q,
+                       (* abc_flop_clk *) input C,
+                       (* abc_flop_en *)  input CE,
+                       (* abc_flop_d *)   input D,
+                       input CLR, \$pastQ );
+  parameter [0:0] INIT = 1'b0;
+  parameter CLK_POLARITY = 1'b0;
+  parameter EN_POLARITY = 1'b1;
+  assign Q = (CE && !CLR) ? D : \$pastQ ;
+endmodule
+
+(* abc_box_id=1005, lib_whitebox, abc_flop *)
+module \$__ABC_FDPE ((* abc_flop_q, abc_arrival=303 *) output Q,
+                     (* abc_flop_clk *) input C,
+                     (* abc_flop_en *)  input CE,
+                     (* abc_flop_d *)   input D,
+                     input PRE, \$pastQ );
+  parameter [0:0] INIT = 1'b0;
+  parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  parameter [0:0] IS_PRE_INVERTED = 1'b0;
+  parameter CLK_POLARITY = !IS_C_INVERTED;
+  parameter EN_POLARITY = 1'b1;
+  assign Q = (CE && !(PRE ^ IS_PRE_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
+endmodule
+
+(* abc_box_id=1006, lib_whitebox, abc_flop *)
+module \$__ABC_FDPE_1 ((* abc_flop_q, abc_arrival=303 *) output Q,
+                       (* abc_flop_clk *) input C,
+                       (* abc_flop_en *)  input CE,
+                       (* abc_flop_d *)   input D,
+                       input PRE, \$pastQ );
+  parameter [0:0] INIT = 1'b0; 
+  parameter CLK_POLARITY = 1'b0;
+  parameter EN_POLARITY = 1'b1;
+  assign Q = (CE && !PRE) ? D : \$pastQ ;
+endmodule
+
+module \$__XILINX_MUXF78 (O, I0, I1, I2, I3, S0, S1);
+  output O;
+  input I0, I1, I2, I3, S0, S1;
+  wire T0, T1;
+  parameter _TECHMAP_BITS_CONNMAP_ = 0;
+  parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I0_ = 0;
+  parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I1_ = 0;
+  parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I2_ = 0;
+  parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I3_ = 0;
+  parameter _TECHMAP_CONSTMSK_S0_ = 0;
+  parameter _TECHMAP_CONSTVAL_S0_ = 0;
+  parameter _TECHMAP_CONSTMSK_S1_ = 0;
+  parameter _TECHMAP_CONSTVAL_S1_ = 0;
+  if (_TECHMAP_CONSTMSK_S0_ && _TECHMAP_CONSTVAL_S0_ === 1'b1)
+    assign T0 = I1;
+  else if (_TECHMAP_CONSTMSK_S0_ || _TECHMAP_CONNMAP_I0_ === _TECHMAP_CONNMAP_I1_)
+    assign T0 = I0;
+  else
+    MUXF7 mux7a (.I0(I0), .I1(I1), .S(S0), .O(T0));
+  if (_TECHMAP_CONSTMSK_S0_ && _TECHMAP_CONSTVAL_S0_ === 1'b1)
+    assign T1 = I3;
+  else if (_TECHMAP_CONSTMSK_S0_ || _TECHMAP_CONNMAP_I2_ === _TECHMAP_CONNMAP_I3_)
+    assign T1 = I2;
+  else
+    MUXF7 mux7b (.I0(I2), .I1(I3), .S(S0), .O(T1));
+  if (_TECHMAP_CONSTMSK_S1_ && _TECHMAP_CONSTVAL_S1_ === 1'b1)
+    assign O = T1;
+  else if (_TECHMAP_CONSTMSK_S1_ || (_TECHMAP_CONNMAP_I0_ === _TECHMAP_CONNMAP_I1_ && _TECHMAP_CONNMAP_I1_ === _TECHMAP_CONNMAP_I2_ && _TECHMAP_CONNMAP_I2_ === _TECHMAP_CONNMAP_I3_))
+    assign O = T0;
+  else
+    MUXF8 mux8 (.I0(T0), .I1(T1), .S(S1), .O(O));
+endmodule
diff --git a/techlibs/xilinx/abc_unmap.v b/techlibs/xilinx/abc_unmap.v
new file mode 100644
index 000000000..6de766e76
--- /dev/null
+++ b/techlibs/xilinx/abc_unmap.v
@@ -0,0 +1,140 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *                2019  Eddie Hung    <eddie@fpgeh.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+// ============================================================================
+
+module \$__ABC_ASYNC (input A, S, output Y);
+  assign Y = A;
+endmodule
+
+module \$__ABC_FDRE (output Q,
+                     input C,
+                     input CE,
+                     input D,
+                     input R, \$pastQ );
+  parameter [0:0] INIT = 1'b0;
+  parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  parameter [0:0] IS_R_INVERTED = 1'b0;
+  parameter CLK_POLARITY = !IS_C_INVERTED;
+  parameter EN_POLARITY = 1'b1;
+
+  FDRE #(
+    .INIT(INIT),
+    .IS_C_INVERTED(IS_C_INVERTED),
+    .IS_D_INVERTED(IS_D_INVERTED),
+    .IS_R_INVERTED(IS_R_INVERTED),
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(Q), .C(C), .CE(CE), .R(R)
+  );
+endmodule
+
+module \$__ABC_FDRE_1 (output Q,
+                       input C,
+                       input CE,
+                       input D,
+                       input R, \$pastQ );
+  parameter [0:0] INIT = 1'b0;
+  parameter CLK_POLARITY = 1'b0;
+  parameter EN_POLARITY = 1'b1;
+  assign Q = R ? 1'b0 : (CE ? D : \$pastQ );
+
+  FDRE_1 #(
+    .INIT(INIT),
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(Q), .C(C), .CE(CE), .R(R)
+  );
+endmodule
+
+module \$__ABC_FDCE (output Q,
+                     input C,
+                     input CE,
+                     input D,
+                     input CLR, \$pastQ );
+  parameter [0:0] INIT = 1'b0;
+  parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  parameter [0:0] IS_CLR_INVERTED = 1'b0;
+  parameter CLK_POLARITY = !IS_C_INVERTED;
+  parameter EN_POLARITY = 1'b1;
+
+  FDCE #(
+    .INIT(INIT),
+    .IS_C_INVERTED(IS_C_INVERTED),
+    .IS_D_INVERTED(IS_D_INVERTED),
+    .IS_CLR_INVERTED(IS_CLR_INVERTED),
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(Q), .C(C), .CE(CE), .CLR(CLR)
+  );
+endmodule
+
+module \$__ABC_FDCE_1 (output Q,
+                       input C,
+                       input CE,
+                       input D,
+                       input CLR, \$pastQ );
+  parameter [0:0] INIT = 1'b0;
+  parameter CLK_POLARITY = 1'b0;
+  parameter EN_POLARITY = 1'b1;
+
+  FDCE_1 #(
+    .INIT(INIT),
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(Q), .C(C), .CE(CE), .CLR(CLR)
+  );
+endmodule
+
+module \$__ABC_FDPE (output Q,
+                     input C,
+                     input CE,
+                     input D,
+                     input PRE, \$pastQ );
+  parameter [0:0] INIT = 1'b0;
+  parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  parameter [0:0] IS_PRE_INVERTED = 1'b0;
+  parameter CLK_POLARITY = !IS_C_INVERTED;
+  parameter EN_POLARITY = 1'b1;
+
+  FDPE #(
+    .INIT(INIT),
+    .IS_C_INVERTED(IS_C_INVERTED),
+    .IS_D_INVERTED(IS_D_INVERTED),
+    .IS_PRE_INVERTED(IS_PRE_INVERTED),
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(Q), .C(C), .CE(CE), .PRE(PRE)
+  );
+endmodule
+
+module \$__ABC_FDPE_1 (output Q,
+                       input C,
+                       input CE,
+                       input D,
+                       input PRE, \$pastQ );
+  parameter [0:0] INIT = 1'b0;
+  parameter CLK_POLARITY = 1'b0;
+  parameter EN_POLARITY = 1'b1;
+
+  FDPE_1 #(
+    .INIT(INIT),
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(Q), .C(C), .CE(CE), .PRE(PRE)
+  );
+endmodule
diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index b8e5bafc7..a15884ec4 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -331,7 +331,6 @@ module \$_MUX16_ (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V, Y)
 endmodule
 `endif
 
-`ifndef _ABC
 module \$__XILINX_MUXF78 (O, I0, I1, I2, I3, S0, S1);
   output O;
   input I0, I1, I2, I3, S0, S1;
@@ -364,4 +363,3 @@ module \$__XILINX_MUXF78 (O, I0, I1, I2, I3, S0, S1);
   else
     MUXF8 mux8 (.I0(T0), .I1(T1), .S(S1), .O(O));
 endmodule
-`endif
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index dd5a76752..614fd8eef 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -169,14 +169,6 @@ module MUXF8(output O, input I0, I1, S);
   assign O = S ? I1 : I0;
 endmodule
 
-`ifdef _ABC
-(* abc_box_id = 3, lib_whitebox *)
-module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
-  assign O = S1 ? (S0 ? I3 : I2)
-                : (S0 ? I1 : I0);
-endmodule
-`endif
-
 module XORCY(output O, input CI, LI);
   assign O = CI ^ LI;
 endmodule
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 6456dbdf4..3525e4de9 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -230,9 +230,9 @@ struct SynthXilinxPass : public ScriptPass
 	{
 		if (check_label("begin")) {
 			if (vpr)
-				run("read_verilog -lib -icells -D _ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
+				run("read_verilog -lib -icells -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
 			else
-				run("read_verilog -lib -icells -D _ABC +/xilinx/cells_sim.v");
+				run("read_verilog -lib -icells +/xilinx/cells_sim.v");
 
 			run("read_verilog -lib +/xilinx/cells_xtra.v");
 
@@ -373,11 +373,11 @@ struct SynthXilinxPass : public ScriptPass
 		}
 
 		if (check_label("map_cells")) {
-			std::string techmap_args = "-map +/techmap.v -D _ABC -map +/xilinx/cells_map.v";
+			std::string techmap_args = "-map +/techmap.v -map +/xilinx/cells_map.v";
 			if (widemux > 0)
 				techmap_args += stringf(" -D MIN_MUX_INPUTS=%d", widemux);
 			if (abc9)
-				techmap_args += " -map +/xilinx/ff_map.v -D _ABC -map +/xilinx/abc_ff.v";
+				techmap_args += " -map +/xilinx/ff_map.v -map +/xilinx/abc_map.v";
 			run("techmap " + techmap_args);
 			run("clean");
 		}
@@ -389,7 +389,7 @@ struct SynthXilinxPass : public ScriptPass
 			else if (abc9) {
 				if (family != "xc7")
 					log_warning("'synth_xilinx -abc9' currently supports '-family xc7' only.\n");
-				run("read_verilog -icells -lib +/xilinx/abc_ff.v");
+				run("read_verilog -icells -lib +/xilinx/abc_model.v");
 				if (nowidelut)
 					run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY));
 				else
@@ -408,7 +408,7 @@ struct SynthXilinxPass : public ScriptPass
 			if (!nosrl || help_mode)
 				run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')");
 			if (abc9)
-				run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v");
+				run("techmap -map +/xilinx/lut_map.v -map +/xilinx/abc_unmap.v");
 			else
 				run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v -map +/xilinx/ff_map.v");
 			run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
-- 
cgit v1.2.3


From 5eda5fc7eb889b738739270f67349b1027951443 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 20 Aug 2019 12:41:11 -0700
Subject: Remove -icells

---
 techlibs/xilinx/synth_xilinx.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 3525e4de9..d4874af45 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -230,9 +230,9 @@ struct SynthXilinxPass : public ScriptPass
 	{
 		if (check_label("begin")) {
 			if (vpr)
-				run("read_verilog -lib -icells -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
+				run("read_verilog -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
 			else
-				run("read_verilog -lib -icells +/xilinx/cells_sim.v");
+				run("read_verilog -lib +/xilinx/cells_sim.v");
 
 			run("read_verilog -lib +/xilinx/cells_xtra.v");
 
-- 
cgit v1.2.3


From 8d0cffaf20c55c733bb5d286b5de1ed85cde77f6 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 20 Aug 2019 13:11:39 -0700
Subject: Remove mapping rules

---
 techlibs/xilinx/abc_model.v | 33 ---------------------------------
 1 file changed, 33 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc_model.v
index 41c232650..243a93403 100644
--- a/techlibs/xilinx/abc_model.v
+++ b/techlibs/xilinx/abc_model.v
@@ -113,36 +113,3 @@ module \$__ABC_FDPE_1 ((* abc_flop_q, abc_arrival=303 *) output Q,
   parameter EN_POLARITY = 1'b1;
   assign Q = (CE && !PRE) ? D : \$pastQ ;
 endmodule
-
-module \$__XILINX_MUXF78 (O, I0, I1, I2, I3, S0, S1);
-  output O;
-  input I0, I1, I2, I3, S0, S1;
-  wire T0, T1;
-  parameter _TECHMAP_BITS_CONNMAP_ = 0;
-  parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I0_ = 0;
-  parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I1_ = 0;
-  parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I2_ = 0;
-  parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I3_ = 0;
-  parameter _TECHMAP_CONSTMSK_S0_ = 0;
-  parameter _TECHMAP_CONSTVAL_S0_ = 0;
-  parameter _TECHMAP_CONSTMSK_S1_ = 0;
-  parameter _TECHMAP_CONSTVAL_S1_ = 0;
-  if (_TECHMAP_CONSTMSK_S0_ && _TECHMAP_CONSTVAL_S0_ === 1'b1)
-    assign T0 = I1;
-  else if (_TECHMAP_CONSTMSK_S0_ || _TECHMAP_CONNMAP_I0_ === _TECHMAP_CONNMAP_I1_)
-    assign T0 = I0;
-  else
-    MUXF7 mux7a (.I0(I0), .I1(I1), .S(S0), .O(T0));
-  if (_TECHMAP_CONSTMSK_S0_ && _TECHMAP_CONSTVAL_S0_ === 1'b1)
-    assign T1 = I3;
-  else if (_TECHMAP_CONSTMSK_S0_ || _TECHMAP_CONNMAP_I2_ === _TECHMAP_CONNMAP_I3_)
-    assign T1 = I2;
-  else
-    MUXF7 mux7b (.I0(I2), .I1(I3), .S(S0), .O(T1));
-  if (_TECHMAP_CONSTMSK_S1_ && _TECHMAP_CONSTVAL_S1_ === 1'b1)
-    assign O = T1;
-  else if (_TECHMAP_CONSTMSK_S1_ || (_TECHMAP_CONNMAP_I0_ === _TECHMAP_CONNMAP_I1_ && _TECHMAP_CONNMAP_I1_ === _TECHMAP_CONNMAP_I2_ && _TECHMAP_CONNMAP_I2_ === _TECHMAP_CONNMAP_I3_))
-    assign O = T0;
-  else
-    MUXF8 mux8 (.I0(T0), .I1(T1), .S(S1), .O(O));
-endmodule
-- 
cgit v1.2.3


From 0079e9b4a677de66372e5c5c9cb011ce74184258 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 20 Aug 2019 13:53:38 -0700
Subject: Add LUTRAM delays

---
 techlibs/xilinx/cells_sim.v | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 614fd8eef..fa0a8fea0 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -289,7 +289,8 @@ endmodule
 
 (* abc_box_id = 5 *)
 module RAM32X1D (
-  output DPO, SPO,
+  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
+  (* abc_arrival=1472 *) output DPO, SPO,
   (* abc_scc_break *) input D,
   input  WCLK,
   (* abc_scc_break *) input WE,
@@ -309,7 +310,8 @@ endmodule
 
 (* abc_box_id = 6 *)
 module RAM64X1D (
-  output DPO, SPO,
+  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
+  (* abc_arrival=1472 *) output DPO, SPO,
   (* abc_scc_break *) input D,
   input  WCLK,
   (* abc_scc_break *) input WE,
@@ -329,7 +331,8 @@ endmodule
 
 (* abc_box_id = 7 *)
 module RAM128X1D (
-  output       DPO, SPO,
+  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
+  (* abc_arrival=1472 *) output DPO, SPO,
   (* abc_scc_break *) input D,
   input        WCLK,
   (* abc_scc_break *) input WE,
-- 
cgit v1.2.3


From 808f07630fc79bf5f6e44986985dd07f83bb9d46 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 20 Aug 2019 14:49:11 -0700
Subject: Wrap LUTRAMs in order to capture comb/seq behaviour

---
 techlibs/xilinx/abc_map.v   | 69 +++++++++++++++++++++++++++++++++++++++++++++
 techlibs/xilinx/abc_model.v | 44 +++++++++++++++++++++++++++++
 techlibs/xilinx/abc_unmap.v | 64 +++++++++++++++++++++++++++++++++++++++++
 techlibs/xilinx/abc_xc7.box | 35 +++++++++--------------
 techlibs/xilinx/cells_sim.v | 24 ++++++----------
 5 files changed, 200 insertions(+), 36 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v
index 99e1fe127..0d69e8c08 100644
--- a/techlibs/xilinx/abc_map.v
+++ b/techlibs/xilinx/abc_map.v
@@ -118,3 +118,72 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE);
   \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
   \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(PRE), .Y(Q));
 endmodule
+
+module RAM32X1D (
+  output DPO, SPO,
+  input  D,
+  input  WCLK,
+  input  WE,
+  input  A0, A1, A2, A3, A4,
+  input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
+);
+  parameter INIT = 32'h0;
+  parameter IS_WCLK_INVERTED = 1'b0;
+  wire \$DPO , \$SPO ;
+  \$__ABC_RAM32X1D #(
+    .INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
+  ) _TECHMAP_REPLACE_ (
+    .DPO(\$DPO ), .SPO(\$SPO ),
+    .D(D), .WCLK(WCLK), .WE(WE),
+    .A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4),
+    .DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4)
+  );
+  \$__ABC_LUTMUX dpo (.A(\$DPO ), .S({1'b0, A0, A1, A2, A3, A4}), .Y(DPO));
+  \$__ABC_LUTMUX spo (.A(\$SPO ), .S({1'b0, A0, A1, A2, A3, A4}), .Y(SPO));
+endmodule
+
+module RAM64X1D (
+  output DPO, SPO,
+  input  D,
+  input  WCLK,
+  input  WE,
+  input  A0, A1, A2, A3, A4, A5,
+  input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
+);
+  parameter INIT = 64'h0;
+  parameter IS_WCLK_INVERTED = 1'b0;
+  wire \$DPO , \$SPO ;
+  \$__ABC_RAM64X1D #(
+    .INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
+  ) _TECHMAP_REPLACE_ (
+    .DPO(\$DPO ), .SPO(\$SPO ),
+    .D(D), .WCLK(WCLK), .WE(WE),
+    .A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4), .A5(A5),
+    .DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4), .DPRA5(DPRA5)
+  );
+  \$__ABC_LUTMUX6 dpo (.A(\$DPO ), .S({A0, A1, A2, A3, A4, A5}), .Y(DPO));
+  \$__ABC_LUTMUX6 spo (.A(\$SPO ), .S({A0, A1, A2, A3, A4, A5}), .Y(SPO));
+endmodule
+
+module \$__ABC_RAM128X1D (
+  output       DPO, SPO,
+  input        D,
+  input        WCLK,
+  input        WE,
+  input  [6:0] A, DPRA
+);
+  parameter INIT = 128'h0;
+  parameter IS_WCLK_INVERTED = 1'b0;
+  wire \$DPO , \$SPO ;
+  \$__ABC_RAM128X1D #(
+    .INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
+  ) _TECHMAP_REPLACE_ (
+    .DPO(\$DPO ), .SPO(\$SPO ),
+    .D(D), .WCLK(WCLK), .WE(WE),
+    .A(A),
+    .DPRA(DPRA)
+  );
+  \$__ABC_LUTMUX7 dpo (.A(\$DPO ), .S(A), .Y(DPO));
+  \$__ABC_LUTMUX7 spo (.A(\$SPO ), .S(A), .Y(SPO));
+
+endmodule
diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc_model.v
index 243a93403..76ef41a91 100644
--- a/techlibs/xilinx/abc_model.v
+++ b/techlibs/xilinx/abc_model.v
@@ -113,3 +113,47 @@ module \$__ABC_FDPE_1 ((* abc_flop_q, abc_arrival=303 *) output Q,
   parameter EN_POLARITY = 1'b1;
   assign Q = (CE && !PRE) ? D : \$pastQ ;
 endmodule
+
+(* abc_box_id=2000 *)
+module \$__ABC_LUTMUX6 (input A, input [5:0] S, output Y);
+endmodule
+(* abc_box_id=2001 *)
+module \$__ABC_LUTMUX7 (input A, input [6:0] S, output Y);
+endmodule
+
+
+module \$__ABC_RAM32X1D (
+  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
+  (* abc_arrival=1472 *) output DPO, SPO,
+  input  D,
+  input  WCLK,
+  input  WE,
+  input  A0, A1, A2, A3, A4,
+  input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
+);
+endmodule
+
+module \$__ABC_RAM64X1D (
+  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
+  (* abc_arrival=1472 *) output DPO, SPO,
+  input  D,
+  input  WCLK,
+  input  WE,
+  input  A0, A1, A2, A3, A4, A5,
+  input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
+);
+  parameter INIT = 64'h0;
+  parameter IS_WCLK_INVERTED = 1'b0;
+endmodule
+
+module \$__ABC_RAM128X1D (
+  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
+  (* abc_arrival=1472 *) output DPO, SPO,
+  input        D,
+  input        WCLK,
+  input        WE,
+  input  [6:0] A, DPRA
+);
+  parameter INIT = 128'h0;
+  parameter IS_WCLK_INVERTED = 1'b0;
+endmodule
diff --git a/techlibs/xilinx/abc_unmap.v b/techlibs/xilinx/abc_unmap.v
index 6de766e76..f2708b477 100644
--- a/techlibs/xilinx/abc_unmap.v
+++ b/techlibs/xilinx/abc_unmap.v
@@ -138,3 +138,67 @@ module \$__ABC_FDPE_1 (output Q,
     .D(D), .Q(Q), .C(C), .CE(CE), .PRE(PRE)
   );
 endmodule
+
+module \$__ABC_LUTMUX (input A, input [5:0] S, output Y);
+  assign Y = A;
+endmodule
+
+module \$__ABC_RAM32X1D (
+  output DPO, SPO,
+  input  D,
+  input  WCLK,
+  input  WE,
+  input  A0, A1, A2, A3, A4,
+  input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
+);
+  parameter INIT = 32'h0;
+  parameter IS_WCLK_INVERTED = 1'b0;
+  RAM32X1D #(
+    .INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
+  ) _TECHMAP_REPLACE_ (
+    .DPO(DPO), .SPO(SPO),
+    .D(D), .WCLK(WCLK), .WE(WE),
+    .A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4),
+    .DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4)
+  );
+endmodule
+
+module \$__ABC_RAM64X1D (
+  output DPO, SPO,
+  input  D,
+  input  WCLK,
+  input  WE,
+  input  A0, A1, A2, A3, A4, A5,
+  input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
+);
+  parameter INIT = 64'h0;
+  parameter IS_WCLK_INVERTED = 1'b0;
+  RAM64X1D #(
+    .INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
+  ) _TECHMAP_REPLACE_ (
+    .DPO(DPO), .SPO(SPO),
+    .D(D), .WCLK(WCLK), .WE(WE),
+    .A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4), .A5(A5),
+    .DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4), .DPRA5(DPRA5)
+  );
+endmodule
+
+module \$__ABC_RAM128X1D (
+  output DPO, SPO,
+  input  D,
+  input  WCLK,
+  input  WE,
+  input  A,
+  input  DPRA,
+);
+  parameter INIT = 128'h0;
+  parameter IS_WCLK_INVERTED = 1'b0;
+  RAM128X1D #(
+    .INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
+  ) _TECHMAP_REPLACE_ (
+    .DPO(DPO), .SPO(SPO),
+    .D(D), .WCLK(WCLK), .WE(WE),
+    .A(A),
+    .DPRA(DPRA)
+  );
+endmodule
diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
index 16040662c..c08af6320 100644
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@ -38,27 +38,6 @@ CARRY4 4 1 10 8
 592 540 520 356 -   512 548 292 -   228
 580 526 507 398 385 508 528 378 380 114
 
-# SLICEM/A6LUT
-# Inputs: A0 A1 A2 A3 A4 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 WCLK WE
-# Outputs: DPO SPO
-RAM32X1D 5 0 13 2
--   -   -   -   -   - 631 472 407 238 127 - -
-631 472 407 238 127 - -   -   -   -   -   - -
-
-# SLICEM/A6LUT
-# Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE
-# Outputs: DPO SPO
-RAM64X1D 6 0 15 2
--   -   -   -   -   -   - 642 631 472 407 238 127 - -
-642 631 472 407 238 127 - -   -   -   -   -   -   - -
-
-# SLICEM/A6LUT + F7[AB]MUX
-# Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE
-# Outputs: DPO SPO
-RAM128X1D 7 0 17 2
--    -    -   -   -   -   -   - 1009 998 839 774 605 494 450 - -
-1047 1036 877 812 643 532 478 - -    -   -   -   -   -   -   - -
-
 # Box to emulate async behaviour of FD[CP]*
 # Inputs: A S
 # Outputs: Y
@@ -99,3 +78,17 @@ FDPE 1005 1 5 1
 # Outputs: Q
 FDPE_1 1006 1 5 1
 0 151 0 806 0
+
+# SLICEM/A6LUT
+# Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32}
+# Inputs: A S0 S1 S2 S3 S4 S5
+# Outputs: Y
+$__ABC_LUTRAM6 2000 0 7 1
+0 642 631 472 407 238 127
+
+# SLICEM/A6LUT + F7BMUX
+# Box to emulate comb/seq behaviour of RAMD128
+# Inputs: A S0 S1 S2 S3 S4 S5 S6
+# Outputs: DPO SPO
+$__ABC_LUTRAM7 2001 0 8 1
+0 1047 1036 877 812 643 532 478
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index fa0a8fea0..e5261de1c 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -287,13 +287,11 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE);
   always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
 endmodule
 
-(* abc_box_id = 5 *)
 module RAM32X1D (
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
-  (* abc_arrival=1472 *) output DPO, SPO,
-  (* abc_scc_break *) input D,
+  output DPO, SPO,
+  input  D,
   input  WCLK,
-  (* abc_scc_break *) input WE,
+  input  WE,
   input  A0, A1, A2, A3, A4,
   input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
 );
@@ -308,13 +306,11 @@ module RAM32X1D (
   always @(posedge clk) if (WE) mem[a] <= D;
 endmodule
 
-(* abc_box_id = 6 *)
 module RAM64X1D (
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
-  (* abc_arrival=1472 *) output DPO, SPO,
-  (* abc_scc_break *) input D,
+  output DPO, SPO,
+  input  D,
   input  WCLK,
-  (* abc_scc_break *) input WE,
+  input  WE,
   input  A0, A1, A2, A3, A4, A5,
   input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
 );
@@ -329,13 +325,11 @@ module RAM64X1D (
   always @(posedge clk) if (WE) mem[a] <= D;
 endmodule
 
-(* abc_box_id = 7 *)
 module RAM128X1D (
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
-  (* abc_arrival=1472 *) output DPO, SPO,
-  (* abc_scc_break *) input D,
+  output       DPO, SPO,
+  input        D,
   input        WCLK,
-  (* abc_scc_break *) input WE,
+  input        WE,
   input  [6:0] A, DPRA
 );
   parameter INIT = 128'h0;
-- 
cgit v1.2.3


From e273ed52758599cb156cf3c309905da70826fe2d Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 20 Aug 2019 15:09:38 -0700
Subject: Wrap SRL{16,32} too

---
 techlibs/xilinx/abc_map.v   | 36 ++++++++++++++++++++++++++++++++++++
 techlibs/xilinx/abc_model.v | 32 ++++++++++++++++++++++++++------
 techlibs/xilinx/abc_unmap.v | 37 ++++++++++++++++++++++++++++++++++++-
 3 files changed, 98 insertions(+), 7 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v
index 0d69e8c08..56b4fe7f9 100644
--- a/techlibs/xilinx/abc_map.v
+++ b/techlibs/xilinx/abc_map.v
@@ -185,5 +185,41 @@ module \$__ABC_RAM128X1D (
   );
   \$__ABC_LUTMUX7 dpo (.A(\$DPO ), .S(A), .Y(DPO));
   \$__ABC_LUTMUX7 spo (.A(\$SPO ), .S(A), .Y(SPO));
+endmodule
 
+module SRL16E (
+  output Q,
+  input A0, A1, A2, A3, CE, CLK, D
+);
+  parameter [15:0] INIT = 16'h0000;
+  parameter [0:0] IS_CLK_INVERTED = 1'b0;
+  wire \$Q ;
+  \$__ABC_SRL16E #(
+    .INIT(INIT), .IS_CLK_INVERTED(IS_CLK_INVERTED)
+  ) _TECHMAP_REPLACE_ (
+    .Q(\$Q ),
+    .A0(A0), .A1(A1), .A2(A2), .A3(A3), .CE(CE), .CLK(CLK), .D(D)
+  );
+  // TODO: Check if SRL uses fast inputs or slow inputs
+  \$__ABC_LUTMUX6 q (.A(\$Q ), .S({A0, A1, A2, A3, 1'b0, 1'b0}), .Y(Q));
+endmodule
+
+module SRLC32E (
+  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
+  (* abc_arrival=1472 *) output Q,
+  (* abc_arrival=1114 *) output Q31,
+  input [4:0] A,
+  input CE, CLK, D
+);
+  parameter [31:0] INIT = 32'h00000000;
+  parameter [0:0] IS_CLK_INVERTED = 1'b0;
+  wire \$Q ;
+  \$__ABC_SRLC32E #(
+    .INIT(INIT), .IS_CLK_INVERTED(IS_CLK_INVERTED)
+  ) _TECHMAP_REPLACE_ (
+    .Q(\$Q ), .Q31(Q31),
+    .A(A), .CE(CE), .CLK(CLK), .D(D)
+  );
+  // TODO: Check if SRL uses fast inputs or slow inputs
+  \$__ABC_LUTMUX6 q (.A(\$Q ), .S({A, 1'b0}), .Y(Q));
 endmodule
diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc_model.v
index 76ef41a91..7162bd213 100644
--- a/techlibs/xilinx/abc_model.v
+++ b/techlibs/xilinx/abc_model.v
@@ -123,8 +123,8 @@ endmodule
 
 
 module \$__ABC_RAM32X1D (
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
-  (* abc_arrival=1472 *) output DPO, SPO,
+  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
+  (* abc_arrival=1153 *) output DPO, SPO,
   input  D,
   input  WCLK,
   input  WE,
@@ -134,8 +134,8 @@ module \$__ABC_RAM32X1D (
 endmodule
 
 module \$__ABC_RAM64X1D (
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
-  (* abc_arrival=1472 *) output DPO, SPO,
+  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
+  (* abc_arrival=1153 *) output DPO, SPO,
   input  D,
   input  WCLK,
   input  WE,
@@ -147,8 +147,8 @@ module \$__ABC_RAM64X1D (
 endmodule
 
 module \$__ABC_RAM128X1D (
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
-  (* abc_arrival=1472 *) output DPO, SPO,
+  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
+  (* abc_arrival=1153 *) output DPO, SPO,
   input        D,
   input        WCLK,
   input        WE,
@@ -157,3 +157,23 @@ module \$__ABC_RAM128X1D (
   parameter INIT = 128'h0;
   parameter IS_WCLK_INVERTED = 1'b0;
 endmodule
+
+module SRL16E (
+  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
+  (* abc_arrival=1472 *) output Q,
+  input A0, A1, A2, A3, CE, CLK, D
+);
+  parameter [15:0] INIT = 16'h0000;
+  parameter [0:0] IS_CLK_INVERTED = 1'b0;
+endmodule
+
+module SRLC32E (
+  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
+  (* abc_arrival=1472 *) output Q,
+  (* abc_arrival=1114 *) output Q31,
+  input [4:0] A,
+  input CE, CLK, D
+);
+  parameter [31:0] INIT = 32'h00000000;
+  parameter [0:0] IS_CLK_INVERTED = 1'b0;
+endmodule
diff --git a/techlibs/xilinx/abc_unmap.v b/techlibs/xilinx/abc_unmap.v
index f2708b477..d00d27e2e 100644
--- a/techlibs/xilinx/abc_unmap.v
+++ b/techlibs/xilinx/abc_unmap.v
@@ -139,7 +139,10 @@ module \$__ABC_FDPE_1 (output Q,
   );
 endmodule
 
-module \$__ABC_LUTMUX (input A, input [5:0] S, output Y);
+module \$__ABC_LUTMUX6 (input A, input [5:0] S, output Y);
+  assign Y = A;
+endmodule
+module \$__ABC_LUTMUX7 (input A, input [6:0] S, output Y);
   assign Y = A;
 endmodule
 
@@ -202,3 +205,35 @@ module \$__ABC_RAM128X1D (
     .DPRA(DPRA)
   );
 endmodule
+
+module \$__ABC_SRL16E (
+  output Q,
+  input A0, A1, A2, A3, CE, CLK, D
+);
+  parameter [15:0] INIT = 16'h0000;
+  parameter [0:0] IS_CLK_INVERTED = 1'b0;
+
+  SRL16E #(
+    .INIT(INIT), .IS_CLK_INVERTED(IS_CLK_INVERTED)
+  ) _TECHMAP_REPLACE_ (
+    .Q(Q),
+    .A0(A0), .A1(A1), .A2(A2), .A3(A3), .CE(CE), .CLK(CLK), .D(D)
+  );
+endmodule
+
+module \$__ABC_SRLC32E (
+  output Q,
+  output Q31,
+  input [4:0] A,
+  input CE, CLK, D
+);
+  parameter [31:0] INIT = 32'h00000000;
+  parameter [0:0] IS_CLK_INVERTED = 1'b0;
+
+  SRLC32E #(
+    .INIT(INIT), .IS_CLK_INVERTED(IS_CLK_INVERTED)
+  ) _TECHMAP_REPLACE_ (
+    .Q(Q), .Q31(Q31),
+    .A(A), .CE(CE), .CLK(CLK), .D(D)
+  );
+endmodule
-- 
cgit v1.2.3


From 96f00e9147967b587ee3b0118b944464b06da0b6 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 20 Aug 2019 17:51:50 -0700
Subject: Typo

---
 techlibs/xilinx/abc_map.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v
index 56b4fe7f9..dc5032d23 100644
--- a/techlibs/xilinx/abc_map.v
+++ b/techlibs/xilinx/abc_map.v
@@ -165,7 +165,7 @@ module RAM64X1D (
   \$__ABC_LUTMUX6 spo (.A(\$SPO ), .S({A0, A1, A2, A3, A4, A5}), .Y(SPO));
 endmodule
 
-module \$__ABC_RAM128X1D (
+module RAM128X1D (
   output       DPO, SPO,
   input        D,
   input        WCLK,
-- 
cgit v1.2.3


From 54284aaa986800b8623d401fd93cf92d25d13713 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 20 Aug 2019 17:52:27 -0700
Subject: Remove delays from abc_map.v

---
 techlibs/xilinx/abc_map.v | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v
index dc5032d23..1d8604ddb 100644
--- a/techlibs/xilinx/abc_map.v
+++ b/techlibs/xilinx/abc_map.v
@@ -20,8 +20,6 @@
 
 // ============================================================================
 
-// Max delays from https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L237-L251
-
 module FDRE (output reg Q, input C, CE, D, R);
   parameter [0:0] INIT = 1'b0;
   parameter [0:0] IS_C_INVERTED = 1'b0;
@@ -205,9 +203,8 @@ module SRL16E (
 endmodule
 
 module SRLC32E (
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
-  (* abc_arrival=1472 *) output Q,
-  (* abc_arrival=1114 *) output Q31,
+  output Q,
+  output Q31,
   input [4:0] A,
   input CE, CLK, D
 );
-- 
cgit v1.2.3


From 3b52d6e29ccc95fd4d102d9a59bb34125521c648 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 20 Aug 2019 17:55:12 -0700
Subject: Move `techmap abc_map.v` into map_luts

---
 techlibs/xilinx/synth_xilinx.cc | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index d6ff91e13..a2ec6a9c9 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -380,7 +380,7 @@ struct SynthXilinxPass : public ScriptPass
 			if (widemux > 0)
 				techmap_args += stringf(" -D MIN_MUX_INPUTS=%d", widemux);
 			if (abc9)
-				techmap_args += " -map +/xilinx/ff_map.v -map +/xilinx/abc_map.v";
+				techmap_args += " -map +/xilinx/ff_map.v";
 			run("techmap " + techmap_args);
 			run("clean");
 		}
@@ -393,6 +393,7 @@ struct SynthXilinxPass : public ScriptPass
 				if (family != "xc7")
 					log_warning("'synth_xilinx -abc9' currently supports '-family xc7' only.\n");
 				run("read_verilog -icells -lib +/xilinx/abc_model.v");
+				run("techmap -map +/xilinx/abc_map.v";
 				if (nowidelut)
 					run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY));
 				else
-- 
cgit v1.2.3


From 30a379b5b6600f0e0e99f0c99ad7bc1d4d08cd90 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 20 Aug 2019 17:59:31 -0700
Subject: Cleanup techmap in map_luts

---
 techlibs/xilinx/synth_xilinx.cc | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index a2ec6a9c9..d28cd2428 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -393,7 +393,7 @@ struct SynthXilinxPass : public ScriptPass
 				if (family != "xc7")
 					log_warning("'synth_xilinx -abc9' currently supports '-family xc7' only.\n");
 				run("read_verilog -icells -lib +/xilinx/abc_model.v");
-				run("techmap -map +/xilinx/abc_map.v";
+				run("techmap -map +/xilinx/abc_map.v");
 				if (nowidelut)
 					run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY));
 				else
@@ -411,10 +411,12 @@ struct SynthXilinxPass : public ScriptPass
 			//   has performed any necessary retiming
 			if (!nosrl || help_mode)
 				run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')");
+			std::string techmap_args = "-map +/xilinx/lut_map.v";
 			if (abc9)
-				run("techmap -map +/xilinx/lut_map.v -map +/xilinx/abc_unmap.v");
+				techmap_args += " -map +/xilinx/abc_unmap.v";
 			else
-				run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v -map +/xilinx/ff_map.v");
+				techmap_args += " -map +/xilinx/ff_map.v";
+			run("techmap " + techmap_args);
 			run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
 					"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
 			run("clean");
-- 
cgit v1.2.3


From aa2d3af6319d475e589acd1efc83d07c11257229 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 20 Aug 2019 18:08:07 -0700
Subject: LUTMUX -> LUTMUX6

---
 techlibs/xilinx/abc_map.v | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v
index 1d8604ddb..a760b3d6d 100644
--- a/techlibs/xilinx/abc_map.v
+++ b/techlibs/xilinx/abc_map.v
@@ -136,8 +136,8 @@ module RAM32X1D (
     .A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4),
     .DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4)
   );
-  \$__ABC_LUTMUX dpo (.A(\$DPO ), .S({1'b0, A0, A1, A2, A3, A4}), .Y(DPO));
-  \$__ABC_LUTMUX spo (.A(\$SPO ), .S({1'b0, A0, A1, A2, A3, A4}), .Y(SPO));
+  \$__ABC_LUTMUX6 dpo (.A(\$DPO ), .S({1'b0, A0, A1, A2, A3, A4}), .Y(DPO));
+  \$__ABC_LUTMUX6 spo (.A(\$SPO ), .S({1'b0, A0, A1, A2, A3, A4}), .Y(SPO));
 endmodule
 
 module RAM64X1D (
-- 
cgit v1.2.3


From bbab6086918f8af3a8a09c2be56208fc29ef7068 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 20 Aug 2019 18:14:40 -0700
Subject: Remove SRL* delays from cells_sim.v

---
 techlibs/xilinx/cells_sim.v | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index e5261de1c..1ab718ccc 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -342,8 +342,7 @@ module RAM128X1D (
 endmodule
 
 module SRL16E (
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
-  (* abc_arrival=1472 *) output Q,
+  output Q,
   input A0, A1, A2, A3, CE, CLK, D
 );
   parameter [15:0] INIT = 16'h0000;
@@ -361,9 +360,8 @@ module SRL16E (
 endmodule
 
 module SRLC32E (
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
-  (* abc_arrival=1472 *) output Q,
-  (* abc_arrival=1114 *) output Q31,
+  output Q,
+  output Q31,
   input [4:0] A,
   input CE, CLK, D
 );
-- 
cgit v1.2.3


From 091bf4a18b2f4bf84fe62b61577c88d961468b3c Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 20 Aug 2019 18:16:37 -0700
Subject: Remove sequential extension

---
 techlibs/xilinx/abc_map.v       |  97 --------------------------------
 techlibs/xilinx/abc_model.v     |  89 ------------------------------
 techlibs/xilinx/abc_unmap.v     | 119 ----------------------------------------
 techlibs/xilinx/abc_xc7.box     |  41 --------------
 techlibs/xilinx/cells_sim.v     |  24 +++++---
 techlibs/xilinx/synth_xilinx.cc |   6 +-
 6 files changed, 17 insertions(+), 359 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v
index a760b3d6d..121862692 100644
--- a/techlibs/xilinx/abc_map.v
+++ b/techlibs/xilinx/abc_map.v
@@ -20,103 +20,6 @@
 
 // ============================================================================
 
-module FDRE (output reg Q, input C, CE, D, R);
-  parameter [0:0] INIT = 1'b0;
-  parameter [0:0] IS_C_INVERTED = 1'b0;
-  parameter [0:0] IS_D_INVERTED = 1'b0;
-  parameter [0:0] IS_R_INVERTED = 1'b0;
-  wire \$nextQ ;
-  \$__ABC_FDRE #(
-    .INIT(INIT),
-    .IS_C_INVERTED(IS_C_INVERTED),
-    .IS_D_INVERTED(IS_D_INVERTED),
-    .IS_R_INVERTED(IS_R_INVERTED),
-    .CLK_POLARITY(!IS_C_INVERTED),
-    .EN_POLARITY(1'b1)
-  ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .R(R)
-  );
-  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
-endmodule
-module FDRE_1 (output reg Q, input C, CE, D, R);
-  parameter [0:0] INIT = 1'b0;
-  wire \$nextQ ;
-  \$__ABC_FDRE_1 #(
-      .INIT(|0),
-    .CLK_POLARITY(1'b0),
-    .EN_POLARITY(1'b1)
-  ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .R(R)
-  );
-  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
-endmodule
-
-module FDCE (output reg Q, input C, CE, D, CLR);
-  parameter [0:0] INIT = 1'b0;
-  parameter [0:0] IS_C_INVERTED = 1'b0;
-  parameter [0:0] IS_D_INVERTED = 1'b0;
-  parameter [0:0] IS_CLR_INVERTED = 1'b0;
-  wire \$nextQ , \$currQ ;
-  \$__ABC_FDCE #(
-    .INIT(INIT),
-    .IS_C_INVERTED(IS_C_INVERTED),
-    .IS_D_INVERTED(IS_D_INVERTED),
-    .IS_CLR_INVERTED(IS_CLR_INVERTED),
-    .CLK_POLARITY(!IS_C_INVERTED),
-    .EN_POLARITY(1'b1)
-  ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR)
-  );
-  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
-  \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(CLR), .Y(Q));
-endmodule
-module FDCE_1 (output reg Q, input C, CE, D, CLR);
-  parameter [0:0] INIT = 1'b0;
-  wire \$nextQ , \$currQ ;
-  \$__ABC_FDCE_1 #(
-    .INIT(INIT),
-    .CLK_POLARITY(1'b0),
-    .EN_POLARITY(1'b1)
-  ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR)
-  );
-  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
-  \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(CLR), .Y(Q));
-endmodule
-
-module FDPE (output reg Q, input C, CE, D, PRE);
-  parameter [0:0] INIT = 1'b0;
-  parameter [0:0] IS_C_INVERTED = 1'b0;
-  parameter [0:0] IS_D_INVERTED = 1'b0;
-  parameter [0:0] IS_PRE_INVERTED = 1'b0;
-  wire \$nextQ , \$currQ ;
-  \$__ABC_FDPE #(
-    .INIT(INIT),
-    .IS_C_INVERTED(IS_C_INVERTED),
-    .IS_D_INVERTED(IS_D_INVERTED),
-    .IS_PRE_INVERTED(IS_PRE_INVERTED),
-    .CLK_POLARITY(!IS_C_INVERTED),
-    .EN_POLARITY(1'b1)
-  ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE)
-  );
-  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
-  \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(PRE), .Y(Q));
-endmodule
-module FDPE_1 (output reg Q, input C, CE, D, PRE);
-  parameter [0:0] INIT = 1'b0;
-  wire \$nextQ , \$currQ ;
-  \$__ABC_FDPE_1 #(
-    .INIT(INIT),
-    .CLK_POLARITY(1'b0),
-    .EN_POLARITY(1'b1)
-  ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE)
-  );
-  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
-  \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(PRE), .Y(Q));
-endmodule
-
 module RAM32X1D (
   output DPO, SPO,
   input  D,
diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc_model.v
index 7162bd213..e3e9686b5 100644
--- a/techlibs/xilinx/abc_model.v
+++ b/techlibs/xilinx/abc_model.v
@@ -26,94 +26,6 @@ module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
                 : (S0 ? I1 : I0);
 endmodule
 
-module \$__ABC_FF_ (input C, D, output Q);
-endmodule
-
-(* abc_box_id = 1000 *)
-module \$__ABC_ASYNC (input A, S, output Y);
-endmodule
-
-(* abc_box_id=1001, lib_whitebox, abc_flop *)
-module \$__ABC_FDRE ((* abc_flop_q, abc_arrival=303 *) output Q,
-                     (* abc_flop_clk *) input C,
-                     (* abc_flop_en *)  input CE,
-                     (* abc_flop_d *)   input D,
-                     input R, \$pastQ );
-  parameter [0:0] INIT = 1'b0;
-  parameter [0:0] IS_C_INVERTED = 1'b0;
-  parameter [0:0] IS_D_INVERTED = 1'b0;
-  parameter [0:0] IS_R_INVERTED = 1'b0;
-  parameter CLK_POLARITY = !IS_C_INVERTED;
-  parameter EN_POLARITY = 1'b1;
-  assign Q = (R ^ IS_R_INVERTED) ? 1'b0 : (CE ? (D ^ IS_D_INVERTED) : \$pastQ );
-endmodule
-
-(* abc_box_id=1002, lib_whitebox, abc_flop *)
-module \$__ABC_FDRE_1 ((* abc_flop_q, abc_arrival=303 *) output Q,
-                       (* abc_flop_clk *) input C,
-                       (* abc_flop_en *)  input CE,
-                       (* abc_flop_d *)   input D,
-                       input R, \$pastQ );
-  parameter [0:0] INIT = 1'b0;
-  parameter CLK_POLARITY = 1'b0;
-  parameter EN_POLARITY = 1'b1;
-  assign Q = R ? 1'b0 : (CE ? D : \$pastQ );
-endmodule
-
-(* abc_box_id=1003, lib_whitebox, abc_flop *)
-module \$__ABC_FDCE ((* abc_flop_q, abc_arrival=303 *) output Q,
-                     (* abc_flop_clk *) input C,
-                     (* abc_flop_en *)  input CE,
-                     (* abc_flop_d *)   input D,
-                     input CLR, \$pastQ );
-  parameter [0:0] INIT = 1'b0;
-  parameter [0:0] IS_C_INVERTED = 1'b0;
-  parameter [0:0] IS_D_INVERTED = 1'b0;
-  parameter [0:0] IS_CLR_INVERTED = 1'b0;
-  parameter CLK_POLARITY = !IS_C_INVERTED;
-  parameter EN_POLARITY = 1'b1;
-  assign Q = (CE && !(CLR ^ IS_CLR_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
-endmodule
-
-(* abc_box_id=1004, lib_whitebox, abc_flop *)
-module \$__ABC_FDCE_1 ((* abc_flop_q, abc_arrival=303 *) output Q,
-                       (* abc_flop_clk *) input C,
-                       (* abc_flop_en *)  input CE,
-                       (* abc_flop_d *)   input D,
-                       input CLR, \$pastQ );
-  parameter [0:0] INIT = 1'b0;
-  parameter CLK_POLARITY = 1'b0;
-  parameter EN_POLARITY = 1'b1;
-  assign Q = (CE && !CLR) ? D : \$pastQ ;
-endmodule
-
-(* abc_box_id=1005, lib_whitebox, abc_flop *)
-module \$__ABC_FDPE ((* abc_flop_q, abc_arrival=303 *) output Q,
-                     (* abc_flop_clk *) input C,
-                     (* abc_flop_en *)  input CE,
-                     (* abc_flop_d *)   input D,
-                     input PRE, \$pastQ );
-  parameter [0:0] INIT = 1'b0;
-  parameter [0:0] IS_C_INVERTED = 1'b0;
-  parameter [0:0] IS_D_INVERTED = 1'b0;
-  parameter [0:0] IS_PRE_INVERTED = 1'b0;
-  parameter CLK_POLARITY = !IS_C_INVERTED;
-  parameter EN_POLARITY = 1'b1;
-  assign Q = (CE && !(PRE ^ IS_PRE_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
-endmodule
-
-(* abc_box_id=1006, lib_whitebox, abc_flop *)
-module \$__ABC_FDPE_1 ((* abc_flop_q, abc_arrival=303 *) output Q,
-                       (* abc_flop_clk *) input C,
-                       (* abc_flop_en *)  input CE,
-                       (* abc_flop_d *)   input D,
-                       input PRE, \$pastQ );
-  parameter [0:0] INIT = 1'b0; 
-  parameter CLK_POLARITY = 1'b0;
-  parameter EN_POLARITY = 1'b1;
-  assign Q = (CE && !PRE) ? D : \$pastQ ;
-endmodule
-
 (* abc_box_id=2000 *)
 module \$__ABC_LUTMUX6 (input A, input [5:0] S, output Y);
 endmodule
@@ -121,7 +33,6 @@ endmodule
 module \$__ABC_LUTMUX7 (input A, input [6:0] S, output Y);
 endmodule
 
-
 module \$__ABC_RAM32X1D (
   // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
   (* abc_arrival=1153 *) output DPO, SPO,
diff --git a/techlibs/xilinx/abc_unmap.v b/techlibs/xilinx/abc_unmap.v
index d00d27e2e..779fc5aac 100644
--- a/techlibs/xilinx/abc_unmap.v
+++ b/techlibs/xilinx/abc_unmap.v
@@ -20,125 +20,6 @@
 
 // ============================================================================
 
-module \$__ABC_ASYNC (input A, S, output Y);
-  assign Y = A;
-endmodule
-
-module \$__ABC_FDRE (output Q,
-                     input C,
-                     input CE,
-                     input D,
-                     input R, \$pastQ );
-  parameter [0:0] INIT = 1'b0;
-  parameter [0:0] IS_C_INVERTED = 1'b0;
-  parameter [0:0] IS_D_INVERTED = 1'b0;
-  parameter [0:0] IS_R_INVERTED = 1'b0;
-  parameter CLK_POLARITY = !IS_C_INVERTED;
-  parameter EN_POLARITY = 1'b1;
-
-  FDRE #(
-    .INIT(INIT),
-    .IS_C_INVERTED(IS_C_INVERTED),
-    .IS_D_INVERTED(IS_D_INVERTED),
-    .IS_R_INVERTED(IS_R_INVERTED),
-  ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(Q), .C(C), .CE(CE), .R(R)
-  );
-endmodule
-
-module \$__ABC_FDRE_1 (output Q,
-                       input C,
-                       input CE,
-                       input D,
-                       input R, \$pastQ );
-  parameter [0:0] INIT = 1'b0;
-  parameter CLK_POLARITY = 1'b0;
-  parameter EN_POLARITY = 1'b1;
-  assign Q = R ? 1'b0 : (CE ? D : \$pastQ );
-
-  FDRE_1 #(
-    .INIT(INIT),
-  ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(Q), .C(C), .CE(CE), .R(R)
-  );
-endmodule
-
-module \$__ABC_FDCE (output Q,
-                     input C,
-                     input CE,
-                     input D,
-                     input CLR, \$pastQ );
-  parameter [0:0] INIT = 1'b0;
-  parameter [0:0] IS_C_INVERTED = 1'b0;
-  parameter [0:0] IS_D_INVERTED = 1'b0;
-  parameter [0:0] IS_CLR_INVERTED = 1'b0;
-  parameter CLK_POLARITY = !IS_C_INVERTED;
-  parameter EN_POLARITY = 1'b1;
-
-  FDCE #(
-    .INIT(INIT),
-    .IS_C_INVERTED(IS_C_INVERTED),
-    .IS_D_INVERTED(IS_D_INVERTED),
-    .IS_CLR_INVERTED(IS_CLR_INVERTED),
-  ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(Q), .C(C), .CE(CE), .CLR(CLR)
-  );
-endmodule
-
-module \$__ABC_FDCE_1 (output Q,
-                       input C,
-                       input CE,
-                       input D,
-                       input CLR, \$pastQ );
-  parameter [0:0] INIT = 1'b0;
-  parameter CLK_POLARITY = 1'b0;
-  parameter EN_POLARITY = 1'b1;
-
-  FDCE_1 #(
-    .INIT(INIT),
-  ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(Q), .C(C), .CE(CE), .CLR(CLR)
-  );
-endmodule
-
-module \$__ABC_FDPE (output Q,
-                     input C,
-                     input CE,
-                     input D,
-                     input PRE, \$pastQ );
-  parameter [0:0] INIT = 1'b0;
-  parameter [0:0] IS_C_INVERTED = 1'b0;
-  parameter [0:0] IS_D_INVERTED = 1'b0;
-  parameter [0:0] IS_PRE_INVERTED = 1'b0;
-  parameter CLK_POLARITY = !IS_C_INVERTED;
-  parameter EN_POLARITY = 1'b1;
-
-  FDPE #(
-    .INIT(INIT),
-    .IS_C_INVERTED(IS_C_INVERTED),
-    .IS_D_INVERTED(IS_D_INVERTED),
-    .IS_PRE_INVERTED(IS_PRE_INVERTED),
-  ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(Q), .C(C), .CE(CE), .PRE(PRE)
-  );
-endmodule
-
-module \$__ABC_FDPE_1 (output Q,
-                       input C,
-                       input CE,
-                       input D,
-                       input PRE, \$pastQ );
-  parameter [0:0] INIT = 1'b0;
-  parameter CLK_POLARITY = 1'b0;
-  parameter EN_POLARITY = 1'b1;
-
-  FDPE_1 #(
-    .INIT(INIT),
-  ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(Q), .C(C), .CE(CE), .PRE(PRE)
-  );
-endmodule
-
 module \$__ABC_LUTMUX6 (input A, input [5:0] S, output Y);
   assign Y = A;
 endmodule
diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
index c08af6320..61b89b8af 100644
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@ -38,47 +38,6 @@ CARRY4 4 1 10 8
 592 540 520 356 -   512 548 292 -   228
 580 526 507 398 385 508 528 378 380 114
 
-# Box to emulate async behaviour of FD[CP]*
-# Inputs: A S
-# Outputs: Y
-$__ABC_ASYNC 1000 0 2 1
-0 764
-
-# The following FD*.{CE,R,CLR,PRE) are offset by 46ps to
-# reflect the -46ps Tsu
-# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L237-L251
-# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L265-L277
-
-# Inputs: C CE D R \$pastQ
-# Outputs: Q
-FDRE 1001 1 5 1
-0 151 0 446 0
-
-# Inputs: C CE D R \$pastQ
-# Outputs: Q
-FDRE_1 1002 1 5 1
-0 151 0 446 0
-
-# Inputs: C CE CLR D \$pastQ
-# Outputs: Q
-FDCE 1003 1 5 1
-0 151 806 0 0
-
-# Inputs: C CE CLR D \$pastQ
-# Outputs: Q
-FDCE_1 1004 1 5 1
-0 151 806 0 0
-
-# Inputs: C CE D PRE \$pastQ
-# Outputs: Q
-FDPE 1005 1 5 1
-0 151 0 806 0
-
-# Inputs: C CE D PRE \$pastQ
-# Outputs: Q
-FDPE_1 1006 1 5 1
-0 151 0 806 0
-
 # SLICEM/A6LUT
 # Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32}
 # Inputs: A S0 S1 S2 S3 S4 S5
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 1ab718ccc..d879a56ee 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -211,7 +211,8 @@ endmodule
 
 `endif
 
-module FDRE (output reg Q, input C, CE, D, R);
+module FDRE ((* abc_arrival=303 *) output reg Q,
+             input C, CE, D, R);
   parameter [0:0] INIT = 1'b0;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -223,7 +224,8 @@ module FDRE (output reg Q, input C, CE, D, R);
   endcase endgenerate
 endmodule
 
-module FDSE (output reg Q, input C, CE, D, S);
+module FDSE ((* abc_arrival=303 *) output reg Q,
+             input C, CE, D, S);
   parameter [0:0] INIT = 1'b1;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -235,7 +237,8 @@ module FDSE (output reg Q, input C, CE, D, S);
   endcase endgenerate
 endmodule
 
-module FDCE (output reg Q, input C, CE, D, CLR);
+module FDCE ((* abc_arrival=303 *) output reg Q,
+             input C, CE, D, CLR);
   parameter [0:0] INIT = 1'b0;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -249,7 +252,8 @@ module FDCE (output reg Q, input C, CE, D, CLR);
   endcase endgenerate
 endmodule
 
-module FDPE (output reg Q, input C, CE, D, PRE);
+module FDPE ((* abc_arrival=303 *) output reg Q,
+             input C, CE, D, PRE);
   parameter [0:0] INIT = 1'b1;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -263,25 +267,29 @@ module FDPE (output reg Q, input C, CE, D, PRE);
   endcase endgenerate
 endmodule
 
-module FDRE_1 (output reg Q, input C, CE, D, R);
+module FDRE_1 ((* abc_arrival=303 *) output reg Q,
+               input C, CE, D, R);
   parameter [0:0] INIT = 1'b0;
   initial Q <= INIT;
   always @(negedge C) if (R) Q <= 1'b0; else if(CE) Q <= D;
 endmodule
 
-module FDSE_1 (output reg Q, input C, CE, D, S);
+module FDSE_1 ((* abc_arrival=303 *) output reg Q,
+               input C, CE, D, S);
   parameter [0:0] INIT = 1'b1;
   initial Q <= INIT;
   always @(negedge C) if (S) Q <= 1'b1; else if(CE) Q <= D;
 endmodule
 
-module FDCE_1 (output reg Q, input C, CE, D, CLR);
+module FDCE_1 ((* abc_arrival=303 *) output reg Q,
+               input C, CE, D, CLR);
   parameter [0:0] INIT = 1'b0;
   initial Q <= INIT;
   always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
 endmodule
 
-module FDPE_1 (output reg Q, input C, CE, D, PRE);
+module FDPE_1 ((* abc_arrival=303 *) output reg Q,
+               input C, CE, D, PRE);
   parameter [0:0] INIT = 1'b1;
   initial Q <= INIT;
   always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index d28cd2428..b9c4df82f 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -379,8 +379,6 @@ struct SynthXilinxPass : public ScriptPass
 			std::string techmap_args = "-map +/techmap.v -map +/xilinx/cells_map.v";
 			if (widemux > 0)
 				techmap_args += stringf(" -D MIN_MUX_INPUTS=%d", widemux);
-			if (abc9)
-				techmap_args += " -map +/xilinx/ff_map.v";
 			run("techmap " + techmap_args);
 			run("clean");
 		}
@@ -411,11 +409,9 @@ struct SynthXilinxPass : public ScriptPass
 			//   has performed any necessary retiming
 			if (!nosrl || help_mode)
 				run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')");
-			std::string techmap_args = "-map +/xilinx/lut_map.v";
+			std::string techmap_args = "-map +/xilinx/lut_map.v -map +/xilinx/ff_map.v";
 			if (abc9)
 				techmap_args += " -map +/xilinx/abc_unmap.v";
-			else
-				techmap_args += " -map +/xilinx/ff_map.v";
 			run("techmap " + techmap_args);
 			run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
 					"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
-- 
cgit v1.2.3


From 343039496baf434beca8c2fb3c275a60365f9496 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 20 Aug 2019 18:22:58 -0700
Subject: Add reference to FD* timing

---
 techlibs/xilinx/cells_sim.v | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index d879a56ee..6aba5a4b2 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -211,6 +211,8 @@ endmodule
 
 `endif
 
+// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L238-L250
+
 module FDRE ((* abc_arrival=303 *) output reg Q,
              input C, CE, D, R);
   parameter [0:0] INIT = 1'b0;
-- 
cgit v1.2.3


From 55acf3120fa47bb95be8a6551738f4f9b1c70a21 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 20 Aug 2019 18:59:03 -0700
Subject: ecp5 to use abc_map.v and _unmap.v

---
 techlibs/ecp5/Makefile.inc  |  3 +++
 techlibs/ecp5/abc_5g.box    | 18 +++++++++---------
 techlibs/ecp5/abc_map.v     | 24 ++++++++++++++++++++++++
 techlibs/ecp5/abc_model.v   | 18 ++++++++++++++++++
 techlibs/ecp5/abc_unmap.v   | 25 +++++++++++++++++++++++++
 techlibs/ecp5/cells_sim.v   |  7 +++----
 techlibs/ecp5/synth_ecp5.cc |  8 +++++++-
 7 files changed, 89 insertions(+), 14 deletions(-)
 create mode 100644 techlibs/ecp5/abc_map.v
 create mode 100644 techlibs/ecp5/abc_model.v
 create mode 100644 techlibs/ecp5/abc_unmap.v

(limited to 'techlibs')

diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc
index 73e18112f..cffd5c3a4 100644
--- a/techlibs/ecp5/Makefile.inc
+++ b/techlibs/ecp5/Makefile.inc
@@ -11,6 +11,9 @@ $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram.txt))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/arith_map.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/latches_map.v))
 
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_map.v))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_unmap.v))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_model.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g.box))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g.lut))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g_nowide.lut))
diff --git a/techlibs/ecp5/abc_5g.box b/techlibs/ecp5/abc_5g.box
index c757d137d..66ebe196a 100644
--- a/techlibs/ecp5/abc_5g.box
+++ b/techlibs/ecp5/abc_5g.box
@@ -15,16 +15,16 @@ CCU2C   1      1   9      3
 630  379  630  379  526   275  392  141  273
 516  516  516  516  412   412  278  278  43
 
-# Box 2 : TRELLIS_DPR16X4 (16x4 dist ram)
+# Box 2 : TRELLIS_DPR16X4_COMB (16x4 dist ram)
 # Outputs: DO0, DO1, DO2, DO3
-# name            ID  w/b   ins   outs
-TRELLIS_DPR16X4   2     0   14    4
-
-#DI0   DI1   DI2   DI3   RAD0   RAD1   RAD2   RAD3   WAD0    WAD1   WAD2   WAD3  WCK   WRE
--      -     -     -     141    379    275    379    -       -      -      -     -     -
--      -     -     -     141    379    275    379    -       -      -      -     -     -
--      -     -     -     141    379    275    379    -       -      -      -     -     -
--      -     -     -     141    379    275    379    -       -      -      -     -     -
+# name               ID  w/b   ins   outs
+$__ABC_RAM16X2_COMB  2     0   8    4
+
+#A0   A1   A2   A3   RAD0   RAD1   RAD2   RAD3
+0     0    0    0    141    379    275    379
+0     0    0    0    141    379    275    379
+0     0    0    0    141    379    275    379
+0     0    0    0    141    379    275    379
 
 # Box 3 : PFUMX (MUX2)
 # Outputs: Z
diff --git a/techlibs/ecp5/abc_map.v b/techlibs/ecp5/abc_map.v
new file mode 100644
index 000000000..e8187ed18
--- /dev/null
+++ b/techlibs/ecp5/abc_map.v
@@ -0,0 +1,24 @@
+// ---------------------------------------
+
+module TRELLIS_DPR16X4 (
+	input  [3:0] DI,
+	input  [3:0] WAD,
+	input        WRE,
+	input        WCK,
+	input  [3:0] RAD,
+	output [3:0] DO
+);
+	parameter WCKMUX = "WCK";
+	parameter WREMUX = "WRE";
+	parameter [63:0] INITVAL = 64'h0000000000000000;
+    wire [3:0] \$DO ;
+
+    \$__ABC_DPR16X4_SEQ #(
+      .WCKMUX(WCKMUX), .WREMUX(WREMUX), .INITVAL(INITVAL)
+    ) _TECHMAP_REPLACE_ (
+      .DI(DI), .WAD(WAD), .WRE(WRE), .WCK(WCK),
+      .RAD(RAD), .DO(\$DO )
+    );
+
+    \$__ABC_DPR16X4_COMB do (.A(\$DO ), .S(RAD), .Y(DO));
+endmodule
diff --git a/techlibs/ecp5/abc_model.v b/techlibs/ecp5/abc_model.v
new file mode 100644
index 000000000..4eb923cb1
--- /dev/null
+++ b/techlibs/ecp5/abc_model.v
@@ -0,0 +1,18 @@
+// ---------------------------------------
+
+(* abc_box_id=2 *)
+module \$__ABC_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y);
+endmodule
+
+module \$__ABC_DPR16X4_SEQ (
+	input  [3:0] DI,
+	input  [3:0] WAD,
+	input        WRE,
+	input        WCK,
+	input  [3:0] RAD,
+	output [3:0] DO
+);
+	parameter WCKMUX = "WCK";
+	parameter WREMUX = "WRE";
+	parameter [63:0] INITVAL = 64'h0000000000000000;
+endmodule
diff --git a/techlibs/ecp5/abc_unmap.v b/techlibs/ecp5/abc_unmap.v
new file mode 100644
index 000000000..0f918c202
--- /dev/null
+++ b/techlibs/ecp5/abc_unmap.v
@@ -0,0 +1,25 @@
+// ---------------------------------------
+
+module \$__ABC_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y);
+    assign Y = A;
+endmodule
+
+module \$__ABC_DPR16X4_SEQ (
+	input  [3:0] DI,
+	input  [3:0] WAD,
+	input        WRE,
+	input        WCK,
+	input  [3:0] RAD,
+	output [3:0] DO
+);
+	parameter WCKMUX = "WCK";
+	parameter WREMUX = "WRE";
+	parameter [63:0] INITVAL = 64'h0000000000000000;
+
+    TRELLIS_DPR16X4 #(
+      .WCKMUX(WCKMUX), .WREMUX(WREMUX), .INITVAL(INITVAL)
+    ) _TECHMAP_REPLACE_ (
+      .DI(DI), .WAD(WAD), .WRE(WRE), .WCK(WCK),
+      .RAD(RAD), .DO(DO)
+    );
+endmodule
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 2fcb0369e..f79a27312 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -107,11 +107,10 @@ module PFUMX (input ALUT, BLUT, C0, output Z);
 endmodule
 
 // ---------------------------------------
-//(* abc_box_id=2 *)
 module TRELLIS_DPR16X4 (
-	(* abc_scc_break *) input [3:0] DI,
-	(* abc_scc_break *) input [3:0] WAD,
-	(* abc_scc_break *) input       WRE,
+	input  [3:0] DI,
+	input  [3:0] WAD,
+	input        WRE,
 	input        WCK,
 	input  [3:0] RAD,
 	output [3:0] DO
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 143d1f95c..93e1cd5b5 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -278,12 +278,18 @@ struct SynthEcp5Pass : public ScriptPass
 			if (abc2 || help_mode) {
 				run("abc", "      (only if -abc2)");
 			}
-			run("techmap -map +/ecp5/latches_map.v");
+			std::string techmap_args = "-map +/ecp5/latches_map.v";
+			if (abc9)
+				techmap_args += " -map +/ecp5/abc_map.v";
+			run("techmap " + techmap_args);
+
 			if (abc9) {
+				run("read_verilog -icells -lib +/ecp5/abc_model.v");
 				if (nowidelut)
 					run("abc9 -lut +/ecp5/abc_5g_nowide.lut -box +/ecp5/abc_5g.box -W 200");
 				else
 					run("abc9 -lut +/ecp5/abc_5g.lut -box +/ecp5/abc_5g.box -W 200");
+				run("techmap -map +/ecp5/abc_unmap.v");
 			} else {
 				if (nowidelut)
 					run("abc -lut 4 -dress");
-- 
cgit v1.2.3


From d46dc9c5b4362c1e333979cbbac4f3567904fee5 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 20 Aug 2019 19:18:36 -0700
Subject: ecp5 to use -max_iter 1

---
 techlibs/ecp5/abc_map.v     | 2 +-
 techlibs/ecp5/cells_sim.v   | 2 +-
 techlibs/ecp5/synth_ecp5.cc | 3 +--
 3 files changed, 3 insertions(+), 4 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/ecp5/abc_map.v b/techlibs/ecp5/abc_map.v
index e8187ed18..ffd25f06d 100644
--- a/techlibs/ecp5/abc_map.v
+++ b/techlibs/ecp5/abc_map.v
@@ -13,7 +13,7 @@ module TRELLIS_DPR16X4 (
 	parameter [63:0] INITVAL = 64'h0000000000000000;
     wire [3:0] \$DO ;
 
-    \$__ABC_DPR16X4_SEQ #(
+    TRELLIS_DPR16X4 #(
       .WCKMUX(WCKMUX), .WREMUX(WREMUX), .INITVAL(INITVAL)
     ) _TECHMAP_REPLACE_ (
       .DI(DI), .WAD(WAD), .WRE(WRE), .WCK(WCK),
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index f79a27312..24de0c3c2 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -113,7 +113,7 @@ module TRELLIS_DPR16X4 (
 	input        WRE,
 	input        WCK,
 	input  [3:0] RAD,
-	output [3:0] DO
+	/* (* abc_arrival=<TODO> *) */ output [3:0] DO
 );
 	parameter WCKMUX = "WCK";
 	parameter WREMUX = "WRE";
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 93e1cd5b5..b1d3160ba 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -280,11 +280,10 @@ struct SynthEcp5Pass : public ScriptPass
 			}
 			std::string techmap_args = "-map +/ecp5/latches_map.v";
 			if (abc9)
-				techmap_args += " -map +/ecp5/abc_map.v";
+				techmap_args += " -map +/ecp5/abc_map.v -max_iter 1";
 			run("techmap " + techmap_args);
 
 			if (abc9) {
-				run("read_verilog -icells -lib +/ecp5/abc_model.v");
 				if (nowidelut)
 					run("abc9 -lut +/ecp5/abc_5g_nowide.lut -box +/ecp5/abc_5g.box -W 200");
 				else
-- 
cgit v1.2.3


From 6b1b03d9f771addbd54358299faad181b589c9f8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 20 Aug 2019 19:20:17 -0700
Subject: ecp5: remove DPR16X4 from abc_unmap.v

---
 techlibs/ecp5/abc_unmap.v | 20 --------------------
 1 file changed, 20 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/ecp5/abc_unmap.v b/techlibs/ecp5/abc_unmap.v
index 0f918c202..d43cdd93f 100644
--- a/techlibs/ecp5/abc_unmap.v
+++ b/techlibs/ecp5/abc_unmap.v
@@ -3,23 +3,3 @@
 module \$__ABC_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y);
     assign Y = A;
 endmodule
-
-module \$__ABC_DPR16X4_SEQ (
-	input  [3:0] DI,
-	input  [3:0] WAD,
-	input        WRE,
-	input        WCK,
-	input  [3:0] RAD,
-	output [3:0] DO
-);
-	parameter WCKMUX = "WCK";
-	parameter WREMUX = "WRE";
-	parameter [63:0] INITVAL = 64'h0000000000000000;
-
-    TRELLIS_DPR16X4 #(
-      .WCKMUX(WCKMUX), .WREMUX(WREMUX), .INITVAL(INITVAL)
-    ) _TECHMAP_REPLACE_ (
-      .DI(DI), .WAD(WAD), .WRE(WRE), .WCK(WCK),
-      .RAD(RAD), .DO(DO)
-    );
-endmodule
-- 
cgit v1.2.3


From c26c5563845d81048dea35c4aef5f4678e177b23 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 20 Aug 2019 19:47:11 -0700
Subject: xilinx to use abc_map.v with -max_iter 1

---
 techlibs/xilinx/abc_map.v       | 26 +++++------
 techlibs/xilinx/abc_model.v     | 60 +-------------------------
 techlibs/xilinx/abc_unmap.v     | 96 +----------------------------------------
 techlibs/xilinx/abc_xc7.box     |  4 +-
 techlibs/xilinx/cells_sim.v     |  9 ++--
 techlibs/xilinx/synth_xilinx.cc |  2 +-
 6 files changed, 26 insertions(+), 171 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v
index 121862692..c3701b1a8 100644
--- a/techlibs/xilinx/abc_map.v
+++ b/techlibs/xilinx/abc_map.v
@@ -31,7 +31,7 @@ module RAM32X1D (
   parameter INIT = 32'h0;
   parameter IS_WCLK_INVERTED = 1'b0;
   wire \$DPO , \$SPO ;
-  \$__ABC_RAM32X1D #(
+  RAM32X1D #(
     .INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
   ) _TECHMAP_REPLACE_ (
     .DPO(\$DPO ), .SPO(\$SPO ),
@@ -39,8 +39,8 @@ module RAM32X1D (
     .A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4),
     .DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4)
   );
-  \$__ABC_LUTMUX6 dpo (.A(\$DPO ), .S({1'b0, A0, A1, A2, A3, A4}), .Y(DPO));
-  \$__ABC_LUTMUX6 spo (.A(\$SPO ), .S({1'b0, A0, A1, A2, A3, A4}), .Y(SPO));
+  \$__ABC_LUT6 dpo (.A(\$DPO ), .S({1'b0, A0, A1, A2, A3, A4}), .Y(DPO));
+  \$__ABC_LUT6 spo (.A(\$SPO ), .S({1'b0, A0, A1, A2, A3, A4}), .Y(SPO));
 endmodule
 
 module RAM64X1D (
@@ -54,7 +54,7 @@ module RAM64X1D (
   parameter INIT = 64'h0;
   parameter IS_WCLK_INVERTED = 1'b0;
   wire \$DPO , \$SPO ;
-  \$__ABC_RAM64X1D #(
+  RAM64X1D #(
     .INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
   ) _TECHMAP_REPLACE_ (
     .DPO(\$DPO ), .SPO(\$SPO ),
@@ -62,8 +62,8 @@ module RAM64X1D (
     .A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4), .A5(A5),
     .DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4), .DPRA5(DPRA5)
   );
-  \$__ABC_LUTMUX6 dpo (.A(\$DPO ), .S({A0, A1, A2, A3, A4, A5}), .Y(DPO));
-  \$__ABC_LUTMUX6 spo (.A(\$SPO ), .S({A0, A1, A2, A3, A4, A5}), .Y(SPO));
+  \$__ABC_LUT6 dpo (.A(\$DPO ), .S({A0, A1, A2, A3, A4, A5}), .Y(DPO));
+  \$__ABC_LUT6 spo (.A(\$SPO ), .S({A0, A1, A2, A3, A4, A5}), .Y(SPO));
 endmodule
 
 module RAM128X1D (
@@ -76,7 +76,7 @@ module RAM128X1D (
   parameter INIT = 128'h0;
   parameter IS_WCLK_INVERTED = 1'b0;
   wire \$DPO , \$SPO ;
-  \$__ABC_RAM128X1D #(
+  RAM128X1D #(
     .INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
   ) _TECHMAP_REPLACE_ (
     .DPO(\$DPO ), .SPO(\$SPO ),
@@ -84,8 +84,8 @@ module RAM128X1D (
     .A(A),
     .DPRA(DPRA)
   );
-  \$__ABC_LUTMUX7 dpo (.A(\$DPO ), .S(A), .Y(DPO));
-  \$__ABC_LUTMUX7 spo (.A(\$SPO ), .S(A), .Y(SPO));
+  \$__ABC_LUT7 dpo (.A(\$DPO ), .S(A), .Y(DPO));
+  \$__ABC_LUT7 spo (.A(\$SPO ), .S(A), .Y(SPO));
 endmodule
 
 module SRL16E (
@@ -95,14 +95,14 @@ module SRL16E (
   parameter [15:0] INIT = 16'h0000;
   parameter [0:0] IS_CLK_INVERTED = 1'b0;
   wire \$Q ;
-  \$__ABC_SRL16E #(
+  SRL16E #(
     .INIT(INIT), .IS_CLK_INVERTED(IS_CLK_INVERTED)
   ) _TECHMAP_REPLACE_ (
     .Q(\$Q ),
     .A0(A0), .A1(A1), .A2(A2), .A3(A3), .CE(CE), .CLK(CLK), .D(D)
   );
   // TODO: Check if SRL uses fast inputs or slow inputs
-  \$__ABC_LUTMUX6 q (.A(\$Q ), .S({A0, A1, A2, A3, 1'b0, 1'b0}), .Y(Q));
+  \$__ABC_LUT6 q (.A(\$Q ), .S({A0, A1, A2, A3, 1'b0, 1'b0}), .Y(Q));
 endmodule
 
 module SRLC32E (
@@ -114,12 +114,12 @@ module SRLC32E (
   parameter [31:0] INIT = 32'h00000000;
   parameter [0:0] IS_CLK_INVERTED = 1'b0;
   wire \$Q ;
-  \$__ABC_SRLC32E #(
+  SRLC32E #(
     .INIT(INIT), .IS_CLK_INVERTED(IS_CLK_INVERTED)
   ) _TECHMAP_REPLACE_ (
     .Q(\$Q ), .Q31(Q31),
     .A(A), .CE(CE), .CLK(CLK), .D(D)
   );
   // TODO: Check if SRL uses fast inputs or slow inputs
-  \$__ABC_LUTMUX6 q (.A(\$Q ), .S({A, 1'b0}), .Y(Q));
+  \$__ABC_LUT6 q (.A(\$Q ), .S({A, 1'b0}), .Y(Q));
 endmodule
diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc_model.v
index e3e9686b5..655b993f6 100644
--- a/techlibs/xilinx/abc_model.v
+++ b/techlibs/xilinx/abc_model.v
@@ -27,64 +27,8 @@ module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
 endmodule
 
 (* abc_box_id=2000 *)
-module \$__ABC_LUTMUX6 (input A, input [5:0] S, output Y);
+module \$__ABC_LUT6 (input A, input [5:0] S, output Y);
 endmodule
 (* abc_box_id=2001 *)
-module \$__ABC_LUTMUX7 (input A, input [6:0] S, output Y);
-endmodule
-
-module \$__ABC_RAM32X1D (
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
-  (* abc_arrival=1153 *) output DPO, SPO,
-  input  D,
-  input  WCLK,
-  input  WE,
-  input  A0, A1, A2, A3, A4,
-  input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
-);
-endmodule
-
-module \$__ABC_RAM64X1D (
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
-  (* abc_arrival=1153 *) output DPO, SPO,
-  input  D,
-  input  WCLK,
-  input  WE,
-  input  A0, A1, A2, A3, A4, A5,
-  input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
-);
-  parameter INIT = 64'h0;
-  parameter IS_WCLK_INVERTED = 1'b0;
-endmodule
-
-module \$__ABC_RAM128X1D (
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
-  (* abc_arrival=1153 *) output DPO, SPO,
-  input        D,
-  input        WCLK,
-  input        WE,
-  input  [6:0] A, DPRA
-);
-  parameter INIT = 128'h0;
-  parameter IS_WCLK_INVERTED = 1'b0;
-endmodule
-
-module SRL16E (
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
-  (* abc_arrival=1472 *) output Q,
-  input A0, A1, A2, A3, CE, CLK, D
-);
-  parameter [15:0] INIT = 16'h0000;
-  parameter [0:0] IS_CLK_INVERTED = 1'b0;
-endmodule
-
-module SRLC32E (
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
-  (* abc_arrival=1472 *) output Q,
-  (* abc_arrival=1114 *) output Q31,
-  input [4:0] A,
-  input CE, CLK, D
-);
-  parameter [31:0] INIT = 32'h00000000;
-  parameter [0:0] IS_CLK_INVERTED = 1'b0;
+module \$__ABC_LUT7 (input A, input [6:0] S, output Y);
 endmodule
diff --git a/techlibs/xilinx/abc_unmap.v b/techlibs/xilinx/abc_unmap.v
index 779fc5aac..f101a22d0 100644
--- a/techlibs/xilinx/abc_unmap.v
+++ b/techlibs/xilinx/abc_unmap.v
@@ -20,101 +20,9 @@
 
 // ============================================================================
 
-module \$__ABC_LUTMUX6 (input A, input [5:0] S, output Y);
+module \$__ABC_LUT6 (input A, input [5:0] S, output Y);
   assign Y = A;
 endmodule
-module \$__ABC_LUTMUX7 (input A, input [6:0] S, output Y);
+module \$__ABC_LUT7 (input A, input [6:0] S, output Y);
   assign Y = A;
 endmodule
-
-module \$__ABC_RAM32X1D (
-  output DPO, SPO,
-  input  D,
-  input  WCLK,
-  input  WE,
-  input  A0, A1, A2, A3, A4,
-  input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
-);
-  parameter INIT = 32'h0;
-  parameter IS_WCLK_INVERTED = 1'b0;
-  RAM32X1D #(
-    .INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
-  ) _TECHMAP_REPLACE_ (
-    .DPO(DPO), .SPO(SPO),
-    .D(D), .WCLK(WCLK), .WE(WE),
-    .A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4),
-    .DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4)
-  );
-endmodule
-
-module \$__ABC_RAM64X1D (
-  output DPO, SPO,
-  input  D,
-  input  WCLK,
-  input  WE,
-  input  A0, A1, A2, A3, A4, A5,
-  input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
-);
-  parameter INIT = 64'h0;
-  parameter IS_WCLK_INVERTED = 1'b0;
-  RAM64X1D #(
-    .INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
-  ) _TECHMAP_REPLACE_ (
-    .DPO(DPO), .SPO(SPO),
-    .D(D), .WCLK(WCLK), .WE(WE),
-    .A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4), .A5(A5),
-    .DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4), .DPRA5(DPRA5)
-  );
-endmodule
-
-module \$__ABC_RAM128X1D (
-  output DPO, SPO,
-  input  D,
-  input  WCLK,
-  input  WE,
-  input  A,
-  input  DPRA,
-);
-  parameter INIT = 128'h0;
-  parameter IS_WCLK_INVERTED = 1'b0;
-  RAM128X1D #(
-    .INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
-  ) _TECHMAP_REPLACE_ (
-    .DPO(DPO), .SPO(SPO),
-    .D(D), .WCLK(WCLK), .WE(WE),
-    .A(A),
-    .DPRA(DPRA)
-  );
-endmodule
-
-module \$__ABC_SRL16E (
-  output Q,
-  input A0, A1, A2, A3, CE, CLK, D
-);
-  parameter [15:0] INIT = 16'h0000;
-  parameter [0:0] IS_CLK_INVERTED = 1'b0;
-
-  SRL16E #(
-    .INIT(INIT), .IS_CLK_INVERTED(IS_CLK_INVERTED)
-  ) _TECHMAP_REPLACE_ (
-    .Q(Q),
-    .A0(A0), .A1(A1), .A2(A2), .A3(A3), .CE(CE), .CLK(CLK), .D(D)
-  );
-endmodule
-
-module \$__ABC_SRLC32E (
-  output Q,
-  output Q31,
-  input [4:0] A,
-  input CE, CLK, D
-);
-  parameter [31:0] INIT = 32'h00000000;
-  parameter [0:0] IS_CLK_INVERTED = 1'b0;
-
-  SRLC32E #(
-    .INIT(INIT), .IS_CLK_INVERTED(IS_CLK_INVERTED)
-  ) _TECHMAP_REPLACE_ (
-    .Q(Q), .Q31(Q31),
-    .A(A), .CE(CE), .CLK(CLK), .D(D)
-  );
-endmodule
diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
index 61b89b8af..554cc0cf0 100644
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@ -42,12 +42,12 @@ CARRY4 4 1 10 8
 # Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32}
 # Inputs: A S0 S1 S2 S3 S4 S5
 # Outputs: Y
-$__ABC_LUTRAM6 2000 0 7 1
+$__ABC_LUT6 2000 0 7 1
 0 642 631 472 407 238 127
 
 # SLICEM/A6LUT + F7BMUX
 # Box to emulate comb/seq behaviour of RAMD128
 # Inputs: A S0 S1 S2 S3 S4 S5 S6
 # Outputs: DPO SPO
-$__ABC_LUTRAM7 2001 0 8 1
+$__ABC_LUT7 2001 0 8 1
 0 1047 1036 877 812 643 532 478
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 6aba5a4b2..3a58f32fa 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -298,7 +298,8 @@ module FDPE_1 ((* abc_arrival=303 *) output reg Q,
 endmodule
 
 module RAM32X1D (
-  output DPO, SPO,
+  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
+  (* abc_arrival=11530 *) output DPO, SPO,
   input  D,
   input  WCLK,
   input  WE,
@@ -317,7 +318,8 @@ module RAM32X1D (
 endmodule
 
 module RAM64X1D (
-  output DPO, SPO,
+  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
+  (* abc_arrival=1153 *) output DPO, SPO,
   input  D,
   input  WCLK,
   input  WE,
@@ -336,7 +338,8 @@ module RAM64X1D (
 endmodule
 
 module RAM128X1D (
-  output       DPO, SPO,
+  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
+  (* abc_arrival=1153 *) output DPO, SPO,
   input        D,
   input        WCLK,
   input        WE,
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index b9c4df82f..263788fec 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -391,7 +391,7 @@ struct SynthXilinxPass : public ScriptPass
 				if (family != "xc7")
 					log_warning("'synth_xilinx -abc9' currently supports '-family xc7' only.\n");
 				run("read_verilog -icells -lib +/xilinx/abc_model.v");
-				run("techmap -map +/xilinx/abc_map.v");
+				run("techmap -map +/xilinx/abc_map.v -max_iter 1");
 				if (nowidelut)
 					run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY));
 				else
-- 
cgit v1.2.3


From 64d62710de4f1db0d59d7fa04b3fb4d51c8dff2e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 20 Aug 2019 20:07:38 -0700
Subject: Oops

---
 techlibs/xilinx/cells_sim.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 3a58f32fa..80211619b 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -299,7 +299,7 @@ endmodule
 
 module RAM32X1D (
   // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
-  (* abc_arrival=11530 *) output DPO, SPO,
+  (* abc_arrival=1153 *) output DPO, SPO,
   input  D,
   input  WCLK,
   input  WE,
-- 
cgit v1.2.3


From 584c68069194f7c776755c108801a56898e19fff Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 21 Aug 2019 11:27:42 -0700
Subject: Add abc_arrival to SRL*

---
 techlibs/xilinx/cells_sim.v | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 80211619b..65c59759a 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -355,7 +355,8 @@ module RAM128X1D (
 endmodule
 
 module SRL16E (
-  output Q,
+  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
+  (* abc_arrival=1472 *) output Q,
   input A0, A1, A2, A3, CE, CLK, D
 );
   parameter [15:0] INIT = 16'h0000;
@@ -373,8 +374,9 @@ module SRL16E (
 endmodule
 
 module SRLC32E (
-  output Q,
-  output Q31,
+  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
+  (* abc_arrival=1472 *) output Q,
+  (* abc_arrival=1114 *) output Q31,
   input [4:0] A,
   input CE, CLK, D
 );
-- 
cgit v1.2.3


From 5d0f6cbd540e1be4525563329dabd2f2aaf7069e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 21 Aug 2019 11:47:06 -0700
Subject: techmap before read

---
 techlibs/xilinx/synth_xilinx.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 263788fec..218192315 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -390,8 +390,8 @@ struct SynthXilinxPass : public ScriptPass
 			else if (abc9) {
 				if (family != "xc7")
 					log_warning("'synth_xilinx -abc9' currently supports '-family xc7' only.\n");
-				run("read_verilog -icells -lib +/xilinx/abc_model.v");
 				run("techmap -map +/xilinx/abc_map.v -max_iter 1");
+				run("read_verilog -icells -lib +/xilinx/abc_model.v");
 				if (nowidelut)
 					run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY));
 				else
-- 
cgit v1.2.3


From c7af71ecde65ad310e487a296b957678412fca74 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 21 Aug 2019 11:47:17 -0700
Subject: Use semicolon

---
 techlibs/xilinx/synth_xilinx.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 218192315..8d0cf84f3 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -386,7 +386,7 @@ struct SynthXilinxPass : public ScriptPass
 		if (check_label("map_luts")) {
 			run("opt_expr -mux_undef");
 			if (help_mode)
-				run("abc -luts 2:2,3,6:5[,10,20] [-dff]", "(option for 'nowidelut', option for '-retime')");
+				run("abc -luts 2:2,3,6:5[,10,20] [-dff]", "(option for 'nowidelut'; option for '-retime')");
 			else if (abc9) {
 				if (family != "xc7")
 					log_warning("'synth_xilinx -abc9' currently supports '-family xc7' only.\n");
-- 
cgit v1.2.3


From e658d472c89d0fef820f2a9ddc6184b566cc0d9b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 23 Aug 2019 11:31:20 -0700
Subject: Put attributes above port

---
 techlibs/xilinx/cells_sim.v    | 65 ++++++++++++++++++++++++++++++------------
 techlibs/xilinx/xc7_brams_bb.v | 24 ++++++++++------
 2 files changed, 62 insertions(+), 27 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 21ac19300..e2ec4e525 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -215,8 +215,11 @@ endmodule
 
 // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L238-L250
 
-module FDRE ((* abc_arrival=303 *) output reg Q,
-             input C, CE, D, R);
+module FDRE (
+  (* abc_arrival=303 *)
+  output reg Q,
+  input C, CE, D, R
+);
   parameter [0:0] INIT = 1'b0;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -228,8 +231,11 @@ module FDRE ((* abc_arrival=303 *) output reg Q,
   endcase endgenerate
 endmodule
 
-module FDSE ((* abc_arrival=303 *) output reg Q,
-             input C, CE, D, S);
+module FDSE (
+  (* abc_arrival=303 *)
+  output reg Q,
+  input C, CE, D, S
+);
   parameter [0:0] INIT = 1'b1;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -241,8 +247,11 @@ module FDSE ((* abc_arrival=303 *) output reg Q,
   endcase endgenerate
 endmodule
 
-module FDCE ((* abc_arrival=303 *) output reg Q,
-             input C, CE, D, CLR);
+module FDCE (
+  (* abc_arrival=303 *)
+  output reg Q,
+  input C, CE, D, CLR
+);
   parameter [0:0] INIT = 1'b0;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -256,8 +265,11 @@ module FDCE ((* abc_arrival=303 *) output reg Q,
   endcase endgenerate
 endmodule
 
-module FDPE ((* abc_arrival=303 *) output reg Q,
-             input C, CE, D, PRE);
+module FDPE (
+  (* abc_arrival=303 *)
+  output reg Q,
+  input C, CE, D, PRE
+);
   parameter [0:0] INIT = 1'b1;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -271,29 +283,41 @@ module FDPE ((* abc_arrival=303 *) output reg Q,
   endcase endgenerate
 endmodule
 
-module FDRE_1 ((* abc_arrival=303 *) output reg Q,
-               input C, CE, D, R);
+module FDRE_1 (
+  (* abc_arrival=303 *)
+  output reg Q,
+  input C, CE, D, R
+);
   parameter [0:0] INIT = 1'b0;
   initial Q <= INIT;
   always @(negedge C) if (R) Q <= 1'b0; else if(CE) Q <= D;
 endmodule
 
-module FDSE_1 ((* abc_arrival=303 *) output reg Q,
-               input C, CE, D, S);
+module FDSE_1 (
+  (* abc_arrival=303 *)
+  output reg Q,
+  input C, CE, D, S
+);
   parameter [0:0] INIT = 1'b1;
   initial Q <= INIT;
   always @(negedge C) if (S) Q <= 1'b1; else if(CE) Q <= D;
 endmodule
 
-module FDCE_1 ((* abc_arrival=303 *) output reg Q,
-               input C, CE, D, CLR);
+module FDCE_1 (
+  (* abc_arrival=303 *)
+  output reg Q,
+  input C, CE, D, CLR
+);
   parameter [0:0] INIT = 1'b0;
   initial Q <= INIT;
   always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
 endmodule
 
-module FDPE_1 ((* abc_arrival=303 *) output reg Q,
-               input C, CE, D, PRE);
+module FDPE_1 (
+  (* abc_arrival=303 *)
+  output reg Q,
+  input C, CE, D, PRE
+);
   parameter [0:0] INIT = 1'b1;
   initial Q <= INIT;
   always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
@@ -361,7 +385,8 @@ endmodule
 
 module SRL16E (
   // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
-  (* abc_arrival=1472 *) output Q,
+  (* abc_arrival=1472 *)
+  output Q,
   input A0, A1, A2, A3, CE, CLK, D
 );
   parameter [15:0] INIT = 16'h0000;
@@ -380,8 +405,10 @@ endmodule
 
 module SRLC32E (
   // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
-  (* abc_arrival=1472 *) output Q,
-  (* abc_arrival=1114 *) output Q31,
+  (* abc_arrival=1472 *)
+  output Q,
+  (* abc_arrival=1114 *)
+  output Q31,
   input [4:0] A,
   input CE, CLK, D
 );
diff --git a/techlibs/xilinx/xc7_brams_bb.v b/techlibs/xilinx/xc7_brams_bb.v
index 0e8cb406c..56939089c 100644
--- a/techlibs/xilinx/xc7_brams_bb.v
+++ b/techlibs/xilinx/xc7_brams_bb.v
@@ -21,10 +21,14 @@ module RAMB18E1 (
 	input [1:0] WEA,
 	input [3:0] WEBWE,
 
-	(* abc_arrival=2454 *) output [15:0] DOADO,
-	(* abc_arrival=2454 *) output [15:0] DOBDO,
-	(* abc_arrival=2454 *) output [1:0] DOPADOP,
-	(* abc_arrival=2454 *) output [1:0] DOPBDOP
+	(* abc_arrival=2454 *)
+	output [15:0] DOADO,
+	(* abc_arrival=2454 *)
+	output [15:0] DOBDO,
+	(* abc_arrival=2454 *)
+	output [1:0] DOPADOP,
+	(* abc_arrival=2454 *)
+	output [1:0] DOPBDOP
 );
 	parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 	parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
@@ -145,10 +149,14 @@ module RAMB36E1 (
 	input [3:0] WEA,
 	input [7:0] WEBWE,
 
-	(* abc_arrival=2454 *) output [31:0] DOADO,
-	(* abc_arrival=2454 *) output [31:0] DOBDO,
-	(* abc_arrival=2454 *) output [3:0] DOPADOP,
-	(* abc_arrival=2454 *) output [3:0] DOPBDOP
+	(* abc_arrival=2454 *)
+	output [31:0] DOADO,
+	(* abc_arrival=2454 *)
+	output [31:0] DOBDO,
+	(* abc_arrival=2454 *)
+	output [3:0] DOPADOP,
+	(* abc_arrival=2454 *)
+	output [3:0] DOPBDOP
 );
 	parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 	parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-- 
cgit v1.2.3


From 85d39653ac62fa4f1f809fb71b0df82a8bd01dfc Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 23 Aug 2019 13:20:29 -0700
Subject: Remove unused model

---
 techlibs/ecp5/abc_model.v | 13 -------------
 1 file changed, 13 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/ecp5/abc_model.v b/techlibs/ecp5/abc_model.v
index 4eb923cb1..56a733b75 100644
--- a/techlibs/ecp5/abc_model.v
+++ b/techlibs/ecp5/abc_model.v
@@ -3,16 +3,3 @@
 (* abc_box_id=2 *)
 module \$__ABC_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y);
 endmodule
-
-module \$__ABC_DPR16X4_SEQ (
-	input  [3:0] DI,
-	input  [3:0] WAD,
-	input        WRE,
-	input        WCK,
-	input  [3:0] RAD,
-	output [3:0] DO
-);
-	parameter WCKMUX = "WCK";
-	parameter WREMUX = "WRE";
-	parameter [63:0] INITVAL = 64'h0000000000000000;
-endmodule
-- 
cgit v1.2.3


From 455da572723e4f19ddc1d636b700a5fe1e975fbb Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 23 Aug 2019 13:21:21 -0700
Subject: Fix spacing

---
 techlibs/ecp5/cells_sim.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index e2bf3c854..01b10f392 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -116,7 +116,7 @@ module TRELLIS_DPR16X4 (
 	input        WCK,
 	input  [3:0] RAD,
 	/* (* abc_arrival=<TODO> *) */
-    output [3:0] DO
+	output [3:0] DO
 );
 	parameter WCKMUX = "WCK";
 	parameter WREMUX = "WRE";
-- 
cgit v1.2.3


From e4f89e01b5710eb9e2e6675a1df13a5a2637b206 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 17:21:12 -0700
Subject: Specify ice40 family to cells_sim.v using define

---
 techlibs/ice40/synth_ice40.cc | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index c6de81bd9..2f77c03db 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -238,7 +238,14 @@ struct SynthIce40Pass : public ScriptPass
 	{
 		if (check_label("begin"))
 		{
-			run("read_verilog -icells -lib +/ice40/cells_sim.v");
+			std::string define;
+			if (device_opt == "lp")
+				define = "-D ICE40_LX";
+			else if (device_opt == "u")
+				define = "-D ICE40_U";
+			else
+				define = "-D ICE40_HX";
+			run("read_verilog -icells " + define + " -lib +/ice40/cells_sim.v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 			run("proc");
 		}
-- 
cgit v1.2.3


From 2421cb3fed1a990219227ed3cf0632eb221e9698 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 17:21:37 -0700
Subject: Add arrival times for HX devices

---
 techlibs/ice40/cells_sim.v | 135 ++++++++++++++++++++++++++++++++++++++-------
 1 file changed, 114 insertions(+), 21 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 02726605f..261d99c9b 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -2,6 +2,10 @@
 `define SB_DFF_REG reg Q = 0
 // `define SB_DFF_REG reg Q
 
+`define ABC_ARRIVAL_HX(TIME) `ifdef ICE40_HX (* abc_arrival=TIME *) `endif
+`define ABC_ARRIVAL_LX(TIME) `ifdef ICE40_LX (* abc_arrival=TIME *) `endif
+`define ABC_ARRIVAL_U(TIME)  `ifdef ICE40_U (* abc_arrival=TIME *) `endif
+
 // SiliconBlue IO Cells
 
 module SB_IO (
@@ -169,20 +173,34 @@ module \$__ICE40_CARRY_WRAPPER (
 	);
 endmodule
 
+// Max delay from: https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
+
 // Positive Edge SiliconBlue FF Cells
 
-module SB_DFF (output `SB_DFF_REG, input C, D);
+module SB_DFF (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, D
+);
 	always @(posedge C)
 		Q <= D;
 endmodule
 
-module SB_DFFE (output `SB_DFF_REG, input C, E, D);
+module SB_DFFE (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, E, D
+);
 	always @(posedge C)
 		if (E)
 			Q <= D;
 endmodule
 
-module SB_DFFSR (output `SB_DFF_REG, input C, R, D);
+module SB_DFFSR (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, R, D
+);
 	always @(posedge C)
 		if (R)
 			Q <= 0;
@@ -190,7 +208,11 @@ module SB_DFFSR (output `SB_DFF_REG, input C, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFR (output `SB_DFF_REG, input C, R, D);
+module SB_DFFR (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, R, D
+);
 	always @(posedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -198,7 +220,11 @@ module SB_DFFR (output `SB_DFF_REG, input C, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFSS (output `SB_DFF_REG, input C, S, D);
+module SB_DFFSS (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, S, D
+);
 	always @(posedge C)
 		if (S)
 			Q <= 1;
@@ -206,7 +232,11 @@ module SB_DFFSS (output `SB_DFF_REG, input C, S, D);
 			Q <= D;
 endmodule
 
-module SB_DFFS (output `SB_DFF_REG, input C, S, D);
+module SB_DFFS (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, S, D
+);
 	always @(posedge C, posedge S)
 		if (S)
 			Q <= 1;
@@ -214,7 +244,11 @@ module SB_DFFS (output `SB_DFF_REG, input C, S, D);
 			Q <= D;
 endmodule
 
-module SB_DFFESR (output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFESR (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, E, R, D
+);
 	always @(posedge C)
 		if (E) begin
 			if (R)
@@ -224,7 +258,11 @@ module SB_DFFESR (output `SB_DFF_REG, input C, E, R, D);
 		end
 endmodule
 
-module SB_DFFER (output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFER (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, E, R, D
+);
 	always @(posedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -232,7 +270,11 @@ module SB_DFFER (output `SB_DFF_REG, input C, E, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFESS (output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFESS (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, E, S, D
+);
 	always @(posedge C)
 		if (E) begin
 			if (S)
@@ -242,7 +284,11 @@ module SB_DFFESS (output `SB_DFF_REG, input C, E, S, D);
 		end
 endmodule
 
-module SB_DFFES (output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFES (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, E, S, D
+);
 	always @(posedge C, posedge S)
 		if (S)
 			Q <= 1;
@@ -252,18 +298,30 @@ endmodule
 
 // Negative Edge SiliconBlue FF Cells
 
-module SB_DFFN (output `SB_DFF_REG, input C, D);
+module SB_DFFN (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, D
+);
 	always @(negedge C)
 		Q <= D;
 endmodule
 
-module SB_DFFNE (output `SB_DFF_REG, input C, E, D);
+module SB_DFFNE (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, E, D
+);
 	always @(negedge C)
 		if (E)
 			Q <= D;
 endmodule
 
-module SB_DFFNSR (output `SB_DFF_REG, input C, R, D);
+module SB_DFFNSR (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, R, D
+);
 	always @(negedge C)
 		if (R)
 			Q <= 0;
@@ -271,7 +329,11 @@ module SB_DFFNSR (output `SB_DFF_REG, input C, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNR (output `SB_DFF_REG, input C, R, D);
+module SB_DFFNR (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, R, D
+);
 	always @(negedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -279,7 +341,11 @@ module SB_DFFNR (output `SB_DFF_REG, input C, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNSS (output `SB_DFF_REG, input C, S, D);
+module SB_DFFNSS (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, S, D
+);
 	always @(negedge C)
 		if (S)
 			Q <= 1;
@@ -287,7 +353,11 @@ module SB_DFFNSS (output `SB_DFF_REG, input C, S, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNS (output `SB_DFF_REG, input C, S, D);
+module SB_DFFNS (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, S, D
+);
 	always @(negedge C, posedge S)
 		if (S)
 			Q <= 1;
@@ -295,7 +365,11 @@ module SB_DFFNS (output `SB_DFF_REG, input C, S, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNESR (output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFNESR (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, E, R, D
+);
 	always @(negedge C)
 		if (E) begin
 			if (R)
@@ -305,7 +379,11 @@ module SB_DFFNESR (output `SB_DFF_REG, input C, E, R, D);
 		end
 endmodule
 
-module SB_DFFNER (output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFNER (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, E, R, D
+);
 	always @(negedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -313,7 +391,11 @@ module SB_DFFNER (output `SB_DFF_REG, input C, E, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNESS (output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFNESS (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, E, S, D
+);
 	always @(negedge C)
 		if (E) begin
 			if (S)
@@ -323,7 +405,11 @@ module SB_DFFNESS (output `SB_DFF_REG, input C, E, S, D);
 		end
 endmodule
 
-module SB_DFFNES (output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFNES (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, E, S, D
+);
 	always @(negedge C, posedge S)
 		if (S)
 			Q <= 1;
@@ -334,6 +420,7 @@ endmodule
 // SiliconBlue RAM Cells
 
 module SB_RAM40_4K (
+	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
 	output [15:0] RDATA,
 	input         RCLK, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -502,6 +589,7 @@ module SB_RAM40_4K (
 endmodule
 
 module SB_RAM40_4KNR (
+	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
 	output [15:0] RDATA,
 	input         RCLKN, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -567,6 +655,7 @@ module SB_RAM40_4KNR (
 endmodule
 
 module SB_RAM40_4KNW (
+	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
 	output [15:0] RDATA,
 	input         RCLK, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -632,6 +721,7 @@ module SB_RAM40_4KNW (
 endmodule
 
 module SB_RAM40_4KNRNW (
+	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
 	output [15:0] RDATA,
 	input         RCLKN, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -700,7 +790,10 @@ endmodule
 
 module ICESTORM_LC (
 	input I0, I1, I2, I3, CIN, CLK, CEN, SR,
-	output LO, O, COUT
+	output LO,
+	`ABC_ARRIVAL_HX(540)
+	output O,
+	output COUT
 );
 	parameter [15:0] LUT_INIT = 0;
 
-- 
cgit v1.2.3


From c0b99ed0e8c8c6adf76d70fa71c9753957162e04 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 18:45:09 -0700
Subject: Do not overwrite LUT param

---
 techlibs/ice40/ice40_opt.cc | 1 -
 1 file changed, 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index 58f106f7c..ea56d3f4d 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -125,7 +125,6 @@ static void run_ice40_opts(Module *module)
 				cell->unsetPort("\\I3");
 				cell->unsetPort("\\CO");
 				cell->unsetPort("\\O");
-				cell->setParam("\\LUT", RTLIL::Const::from_string("0110100110010110"));
 				cell->setParam("\\WIDTH", 4);
 			}
 			continue;
-- 
cgit v1.2.3


From e3709e5ee6b28c1156b4768373e244c32c7c5aba Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 18:51:14 -0700
Subject: LX -> LP

---
 techlibs/ice40/cells_sim.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 34134d02a..fe80c998d 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -3,7 +3,7 @@
 // `define SB_DFF_REG reg Q
 
 `define ABC_ARRIVAL_HX(TIME) `ifdef ICE40_HX (* abc_arrival=TIME *) `endif
-`define ABC_ARRIVAL_LX(TIME) `ifdef ICE40_LX (* abc_arrival=TIME *) `endif
+`define ABC_ARRIVAL_LP(TIME) `ifdef ICE40_LP (* abc_arrival=TIME *) `endif
 `define ABC_ARRIVAL_U(TIME)  `ifdef ICE40_U (* abc_arrival=TIME *) `endif
 
 // SiliconBlue IO Cells
-- 
cgit v1.2.3


From 927f1e3754987ab794566a521c7a1149d4fbf6a7 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 18:56:25 -0700
Subject: Add LP timings

---
 techlibs/ice40/cells_sim.v | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

(limited to 'techlibs')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index fe80c998d..b86ec3ea5 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -174,11 +174,13 @@ module \$__ICE40_CARRY_WRAPPER (
 endmodule
 
 // Max delay from: https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
+//                 https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
 
 // Positive Edge SiliconBlue FF Cells
 
 module SB_DFF (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, D
 );
@@ -188,6 +190,7 @@ endmodule
 
 module SB_DFFE (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, E, D
 );
@@ -198,6 +201,7 @@ endmodule
 
 module SB_DFFSR (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -210,6 +214,7 @@ endmodule
 
 module SB_DFFR (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -222,6 +227,7 @@ endmodule
 
 module SB_DFFSS (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -234,6 +240,7 @@ endmodule
 
 module SB_DFFS (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -246,6 +253,7 @@ endmodule
 
 module SB_DFFESR (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -260,6 +268,7 @@ endmodule
 
 module SB_DFFER (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -272,6 +281,7 @@ endmodule
 
 module SB_DFFESS (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -286,6 +296,7 @@ endmodule
 
 module SB_DFFES (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -300,6 +311,7 @@ endmodule
 
 module SB_DFFN (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, D
 );
@@ -309,6 +321,7 @@ endmodule
 
 module SB_DFFNE (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, E, D
 );
@@ -319,6 +332,7 @@ endmodule
 
 module SB_DFFNSR (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -331,6 +345,7 @@ endmodule
 
 module SB_DFFNR (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -343,6 +358,7 @@ endmodule
 
 module SB_DFFNSS (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -355,6 +371,7 @@ endmodule
 
 module SB_DFFNS (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -367,6 +384,7 @@ endmodule
 
 module SB_DFFNESR (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -381,6 +399,7 @@ endmodule
 
 module SB_DFFNER (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -393,6 +412,7 @@ endmodule
 
 module SB_DFFNESS (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -407,6 +427,7 @@ endmodule
 
 module SB_DFFNES (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -421,6 +442,7 @@ endmodule
 
 module SB_RAM40_4K (
 	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
+	`ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
 	output [15:0] RDATA,
 	input         RCLK, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -590,6 +612,7 @@ endmodule
 
 module SB_RAM40_4KNR (
 	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
+	`ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
 	output [15:0] RDATA,
 	input         RCLKN, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -656,6 +679,7 @@ endmodule
 
 module SB_RAM40_4KNW (
 	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
+	`ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
 	output [15:0] RDATA,
 	input         RCLK, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -722,6 +746,7 @@ endmodule
 
 module SB_RAM40_4KNRNW (
 	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
+	`ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
 	output [15:0] RDATA,
 	input         RCLKN, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -792,6 +817,7 @@ module ICESTORM_LC (
 	input I0, I1, I2, I3, CIN, CLK, CEN, SR,
 	output LO,
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output O,
 	output COUT
 );
-- 
cgit v1.2.3


From 0f4e9f6bc5a5a564b2ddccb0fbebdfa5735aeefd Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 18:57:34 -0700
Subject: Round not floor

---
 techlibs/ice40/cells_sim.v | 42 +++++++++++++++++++++---------------------
 1 file changed, 21 insertions(+), 21 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index b86ec3ea5..f5fe800f7 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -180,7 +180,7 @@ endmodule
 
 module SB_DFF (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, D
 );
@@ -190,7 +190,7 @@ endmodule
 
 module SB_DFFE (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, E, D
 );
@@ -201,7 +201,7 @@ endmodule
 
 module SB_DFFSR (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -214,7 +214,7 @@ endmodule
 
 module SB_DFFR (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -227,7 +227,7 @@ endmodule
 
 module SB_DFFSS (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -240,7 +240,7 @@ endmodule
 
 module SB_DFFS (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -253,7 +253,7 @@ endmodule
 
 module SB_DFFESR (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -268,7 +268,7 @@ endmodule
 
 module SB_DFFER (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -281,7 +281,7 @@ endmodule
 
 module SB_DFFESS (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -296,7 +296,7 @@ endmodule
 
 module SB_DFFES (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -311,7 +311,7 @@ endmodule
 
 module SB_DFFN (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, D
 );
@@ -321,7 +321,7 @@ endmodule
 
 module SB_DFFNE (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, E, D
 );
@@ -332,7 +332,7 @@ endmodule
 
 module SB_DFFNSR (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -345,7 +345,7 @@ endmodule
 
 module SB_DFFNR (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -358,7 +358,7 @@ endmodule
 
 module SB_DFFNSS (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -371,7 +371,7 @@ endmodule
 
 module SB_DFFNS (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -384,7 +384,7 @@ endmodule
 
 module SB_DFFNESR (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -399,7 +399,7 @@ endmodule
 
 module SB_DFFNER (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -412,7 +412,7 @@ endmodule
 
 module SB_DFFNESS (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -427,7 +427,7 @@ endmodule
 
 module SB_DFFNES (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -817,7 +817,7 @@ module ICESTORM_LC (
 	input I0, I1, I2, I3, CIN, CLK, CEN, SR,
 	output LO,
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output O,
 	output COUT
 );
-- 
cgit v1.2.3


From 4bda902f1b9dccb5603c2beebd71392cbfe34eb9 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 19:02:54 -0700
Subject: LX -> LP

---
 techlibs/ice40/synth_ice40.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 2f77c03db..a3890268a 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -240,7 +240,7 @@ struct SynthIce40Pass : public ScriptPass
 		{
 			std::string define;
 			if (device_opt == "lp")
-				define = "-D ICE40_LX";
+				define = "-D ICE40_LP";
 			else if (device_opt == "u")
 				define = "-D ICE40_U";
 			else
-- 
cgit v1.2.3


From efa4ee5c0e6201f357d7c02a7deeb1ba1c23c368 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 19:03:29 -0700
Subject: Add arrival times for U

---
 techlibs/ice40/cells_sim.v | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

(limited to 'techlibs')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index f5fe800f7..116188acb 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -175,12 +175,14 @@ endmodule
 
 // Max delay from: https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
 //                 https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
+//                 https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
 
 // Positive Edge SiliconBlue FF Cells
 
 module SB_DFF (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, D
 );
@@ -191,6 +193,7 @@ endmodule
 module SB_DFFE (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, D
 );
@@ -202,6 +205,7 @@ endmodule
 module SB_DFFSR (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -215,6 +219,7 @@ endmodule
 module SB_DFFR (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -228,6 +233,7 @@ endmodule
 module SB_DFFSS (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -241,6 +247,7 @@ endmodule
 module SB_DFFS (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -254,6 +261,7 @@ endmodule
 module SB_DFFESR (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -269,6 +277,7 @@ endmodule
 module SB_DFFER (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -282,6 +291,7 @@ endmodule
 module SB_DFFESS (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -297,6 +307,7 @@ endmodule
 module SB_DFFES (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -312,6 +323,7 @@ endmodule
 module SB_DFFN (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, D
 );
@@ -322,6 +334,7 @@ endmodule
 module SB_DFFNE (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, D
 );
@@ -333,6 +346,7 @@ endmodule
 module SB_DFFNSR (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -346,6 +360,7 @@ endmodule
 module SB_DFFNR (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -359,6 +374,7 @@ endmodule
 module SB_DFFNSS (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -372,6 +388,7 @@ endmodule
 module SB_DFFNS (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -385,6 +402,7 @@ endmodule
 module SB_DFFNESR (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -400,6 +418,7 @@ endmodule
 module SB_DFFNER (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -413,6 +432,7 @@ endmodule
 module SB_DFFNESS (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -428,6 +448,7 @@ endmodule
 module SB_DFFNES (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -443,6 +464,7 @@ endmodule
 module SB_RAM40_4K (
 	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
 	`ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
+	`ABC_ARRIVAL_U(1179)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
 	output [15:0] RDATA,
 	input         RCLK, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -613,6 +635,7 @@ endmodule
 module SB_RAM40_4KNR (
 	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
 	`ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
+	`ABC_ARRIVAL_U(1179)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
 	output [15:0] RDATA,
 	input         RCLKN, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -680,6 +703,7 @@ endmodule
 module SB_RAM40_4KNW (
 	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
 	`ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
+	`ABC_ARRIVAL_U(1179)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
 	output [15:0] RDATA,
 	input         RCLK, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -747,6 +771,7 @@ endmodule
 module SB_RAM40_4KNRNW (
 	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
 	`ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
+	`ABC_ARRIVAL_U(1179)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
 	output [15:0] RDATA,
 	input         RCLKN, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -818,6 +843,7 @@ module ICESTORM_LC (
 	output LO,
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output O,
 	output COUT
 );
-- 
cgit v1.2.3


From 309684af16c763f7874beb605d0834c64975d004 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 19:07:28 -0700
Subject: Add arrival for SB_MAC16.O

---
 techlibs/ice40/cells_sim.v | 1 +
 1 file changed, 1 insertion(+)

(limited to 'techlibs')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 116188acb..f4cc342eb 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -1445,6 +1445,7 @@ module SB_MAC16 (
 	input ADDSUBTOP, ADDSUBBOT,
 	input OHOLDTOP, OHOLDBOT,
 	input CI, ACCUMCI, SIGNEXTIN,
+	`ABC_ARRIVAL_U(1984)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L587
 	output [31:0] O,
 	output CO, ACCUMCO, SIGNEXTOUT
 );
-- 
cgit v1.2.3


From e8e38308689a760b69bd2910a36701b19f64656d Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 19:09:29 -0700
Subject: Comment out SB_MAC16 arrival time for now, need to handle all its
 modes

---
 techlibs/ice40/cells_sim.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index f4cc342eb..8e5e0358e 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -1445,7 +1445,7 @@ module SB_MAC16 (
 	input ADDSUBTOP, ADDSUBBOT,
 	input OHOLDTOP, OHOLDBOT,
 	input CI, ACCUMCI, SIGNEXTIN,
-	`ABC_ARRIVAL_U(1984)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L587
+	//`ABC_ARRIVAL_U(1984)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
 	output [31:0] O,
 	output CO, ACCUMCO, SIGNEXTOUT
 );
-- 
cgit v1.2.3


From c4e53108230c246ecf1b014b11c240b71ed39a8a Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 20:58:55 -0700
Subject: Use a dummy box file if none specified

---
 techlibs/common/Makefile.inc | 1 +
 techlibs/common/dummy.box    | 1 +
 2 files changed, 2 insertions(+)
 create mode 100644 techlibs/common/dummy.box

(limited to 'techlibs')

diff --git a/techlibs/common/Makefile.inc b/techlibs/common/Makefile.inc
index 0e05620bc..de94798af 100644
--- a/techlibs/common/Makefile.inc
+++ b/techlibs/common/Makefile.inc
@@ -28,3 +28,4 @@ $(eval $(call add_share_file,share,techlibs/common/dff2ff.v))
 $(eval $(call add_share_file,share,techlibs/common/gate2lut.v))
 $(eval $(call add_share_file,share,techlibs/common/cmp2lut.v))
 $(eval $(call add_share_file,share,techlibs/common/cells.lib))
+$(eval $(call add_share_file,share,techlibs/common/dummy.box))
diff --git a/techlibs/common/dummy.box b/techlibs/common/dummy.box
new file mode 100644
index 000000000..0c18070a0
--- /dev/null
+++ b/techlibs/common/dummy.box
@@ -0,0 +1 @@
+(dummy) 1 0 0 0
-- 
cgit v1.2.3


From f33abd4eab08c0557a561b0fd4f16fc3d86433ab Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 30 Aug 2019 16:44:11 -0700
Subject: Remove trailing space

---
 techlibs/xilinx/cells_sim.v | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index b4657daca..6e8729256 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -269,7 +269,7 @@ endmodule
 module FDCE (
   (* abc_arrival=303 *)
   output reg Q,
-  (* clkbuf_sink *) 
+  (* clkbuf_sink *)
   input C,
   input CE, D, CLR
 );
@@ -289,7 +289,7 @@ endmodule
 module FDPE (
   (* abc_arrival=303 *)
   output reg Q,
-  (* clkbuf_sink *) 
+  (* clkbuf_sink *)
   input C,
   input CE, D, PRE
 );
-- 
cgit v1.2.3


From 696f854801619644e42f437894847ace96594a6b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 2 Sep 2019 12:15:11 -0700
Subject: Rename box

---
 techlibs/ecp5/abc_5g.box | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/ecp5/abc_5g.box b/techlibs/ecp5/abc_5g.box
index 66ebe196a..a336b4a85 100644
--- a/techlibs/ecp5/abc_5g.box
+++ b/techlibs/ecp5/abc_5g.box
@@ -18,7 +18,7 @@ CCU2C   1      1   9      3
 # Box 2 : TRELLIS_DPR16X4_COMB (16x4 dist ram)
 # Outputs: DO0, DO1, DO2, DO3
 # name               ID  w/b   ins   outs
-$__ABC_RAM16X2_COMB  2     0   8    4
+$__ABC_DPR16X4_COMB  2     0   8    4
 
 #A0   A1   A2   A3   RAD0   RAD1   RAD2   RAD3
 0     0    0    0    141    379    275    379
-- 
cgit v1.2.3


From 3459d283492769263e73a0e35d0e5d253c0bbec7 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 2 Sep 2019 12:22:15 -0700
Subject: Add comments

---
 techlibs/xilinx/abc_xc7.box | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
index 554cc0cf0..20da3b8a0 100644
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@ -15,7 +15,10 @@ F7MUX 1 1 3 1
 MUXF8 2 1 3 1
 104 94 273
 
-# Box containing MUXF7.[AB] + MUXF8
+# Box containing MUXF7.[AB] + MUXF8,
+#   Necessary to make these an atomic unit so that
+#   ABC cannot optimise just one of the MUXF7 away
+#   and expect to save on its delay
 # Inputs: I0 I1 I2 I3 S0 S1
 # Outputs: O
 $__MUXF78 3 1 6 1
@@ -40,6 +43,11 @@ CARRY4 4 1 10 8
 
 # SLICEM/A6LUT
 # Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32}
+#   Necessary since RAMD* and SRL* have both combinatorial (i.e.
+#   same-cycle read operation) and sequential (write operation
+#   is only committed on the next clock edge).
+#   To model the combinatorial path, such cells have to be split
+#   into comb and seq parts, with this box modelling only the former.
 # Inputs: A S0 S1 S2 S3 S4 S5
 # Outputs: Y
 $__ABC_LUT6 2000 0 7 1
-- 
cgit v1.2.3


From aa1491add3722e4cfae35755cc4cecfd3e5a6c82 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 4 Sep 2019 15:47:36 -0700
Subject: Resolve TODO with pin assignments for SRL*

---
 techlibs/xilinx/abc_map.v | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v
index c3701b1a8..0c85d6656 100644
--- a/techlibs/xilinx/abc_map.v
+++ b/techlibs/xilinx/abc_map.v
@@ -101,8 +101,7 @@ module SRL16E (
     .Q(\$Q ),
     .A0(A0), .A1(A1), .A2(A2), .A3(A3), .CE(CE), .CLK(CLK), .D(D)
   );
-  // TODO: Check if SRL uses fast inputs or slow inputs
-  \$__ABC_LUT6 q (.A(\$Q ), .S({A0, A1, A2, A3, 1'b0, 1'b0}), .Y(Q));
+  \$__ABC_LUT6 q (.A(\$Q ), .S({1'b1, A0, A1, A2, A3, 1'b1}), .Y(Q));
 endmodule
 
 module SRLC32E (
@@ -120,6 +119,5 @@ module SRLC32E (
     .Q(\$Q ), .Q31(Q31),
     .A(A), .CE(CE), .CLK(CLK), .D(D)
   );
-  // TODO: Check if SRL uses fast inputs or slow inputs
-  \$__ABC_LUT6 q (.A(\$Q ), .S({A, 1'b0}), .Y(Q));
+  \$__ABC_LUT6 q (.A(\$Q ), .S({1'b1, A}), .Y(Q));
 endmodule
-- 
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