From 269ff450f55f4354c82db1b98f8eb722317d9250 Mon Sep 17 00:00:00 2001 From: David Shah Date: Mon, 8 Jul 2019 15:40:12 +0100 Subject: Add mul2dsp multiplier splitting rule and ECP5 mapping Signed-off-by: David Shah --- techlibs/common/Makefile.inc | 1 + techlibs/common/mul2dsp.v | 237 +++++++++++++++++++++++++++++++++++++++++++ techlibs/ecp5/Makefile.inc | 1 + techlibs/ecp5/dsp_map.v | 10 ++ techlibs/ecp5/synth_ecp5.cc | 33 +++++- 5 files changed, 280 insertions(+), 2 deletions(-) create mode 100644 techlibs/common/mul2dsp.v create mode 100644 techlibs/ecp5/dsp_map.v (limited to 'techlibs') diff --git a/techlibs/common/Makefile.inc b/techlibs/common/Makefile.inc index 0e05620bc..e6d1c2f29 100644 --- a/techlibs/common/Makefile.inc +++ b/techlibs/common/Makefile.inc @@ -28,3 +28,4 @@ $(eval $(call add_share_file,share,techlibs/common/dff2ff.v)) $(eval $(call add_share_file,share,techlibs/common/gate2lut.v)) $(eval $(call add_share_file,share,techlibs/common/cmp2lut.v)) $(eval $(call add_share_file,share,techlibs/common/cells.lib)) +$(eval $(call add_share_file,share,techlibs/common/mul2dsp.v)) diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v new file mode 100644 index 000000000..37ce2e485 --- /dev/null +++ b/techlibs/common/mul2dsp.v @@ -0,0 +1,237 @@ +// From Eddie Hung +// extracted from: https://github.com/eddiehung/vtr-with-yosys/blob/vtr7-with-yosys/vtr_flow/misc/yosys_models.v#L220 +// revised by Andre DeHon +// further revised by David Shah +`ifndef DSP_A_MAXWIDTH +`define DSP_A_MAXWIDTH 18 +`endif +`ifndef DSP_A_MAXWIDTH +`define DSP_B_MAXWIDTH 25 +`endif + +`ifndef ADDER_MINWIDTH +`define ADDER_MINWIDTH AAA +`endif + +`ifndef DSP_NAME +`define DSP_NAME M18x25 +`endif + +`define MAX(a,b) (a > b ? a : b) +`define MIN(a,b) (a < b ? a : b) + +(* techmap_celltype = "$mul" *) +module \$mul (A, B, Y); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 1; + parameter B_WIDTH = 1; + parameter Y_WIDTH = 1; + + input [A_WIDTH-1:0] A; + input [B_WIDTH-1:0] B; + output [Y_WIDTH-1:0] Y; + + wire [1023:0] _TECHMAP_DO_ = "proc; clean"; + + generate + if (A_WIDTH `DSP_A_MAXWIDTH) begin + localparam n_floored = A_WIDTH/`DSP_A_MAXWIDTH; + localparam n = n_floored + (n_floored*`DSP_A_MAXWIDTH < A_WIDTH ? 1 : 0); + wire [`DSP_A_MAXWIDTH+B_WIDTH-1:0] partial [n-1:1]; + wire [Y_WIDTH-1:0] partial_sum [n-2:0]; + + \$__mul_gen #( + .A_SIGNED(A_SIGNED), + .B_SIGNED(B_SIGNED), + .A_WIDTH(`DSP_A_MAXWIDTH), + .B_WIDTH(B_WIDTH), + .Y_WIDTH(B_WIDTH+`DSP_A_MAXWIDTH) + ) mul_slice_first ( + .A(A[`DSP_A_MAXWIDTH-1:0]), + .B(B), + .Y(partial_sum[0][B_WIDTH+`DSP_A_MAXWIDTH-1:0]) + ); + assign partial_sum[0][Y_WIDTH-1:B_WIDTH+`DSP_A_MAXWIDTH]=0; + + genvar i; + generate + for (i = 1; i < n-1; i=i+1) begin:slice + \$__mul_gen #( + .A_SIGNED(A_SIGNED), + .B_SIGNED(B_SIGNED), + .A_WIDTH(`DSP_A_MAXWIDTH), + .B_WIDTH(B_WIDTH), + .Y_WIDTH(B_WIDTH+`DSP_A_MAXWIDTH) + ) mul_slice ( + .A(A[(i+1)*`DSP_A_MAXWIDTH-1:i*`DSP_A_MAXWIDTH]), + .B(B), + .Y(partial[i][B_WIDTH+`DSP_A_MAXWIDTH-1:0]) + ); + //assign partial_sum[i] = (partial[i] << i*`DSP_A_MAXWIDTH) + partial_sum[i-1]; + assign partial_sum[i] = { + partial[i][B_WIDTH+`DSP_A_MAXWIDTH-1:0] + + partial_sum[i-1][Y_WIDTH-1:(i*`DSP_A_MAXWIDTH)], + partial_sum[i-1][(i*`DSP_A_MAXWIDTH)-1:0] + }; + end + endgenerate + + \$__mul_gen #( + .A_SIGNED(A_SIGNED), + .B_SIGNED(B_SIGNED), + .A_WIDTH(A_WIDTH-(n-1)*`DSP_A_MAXWIDTH), + .B_WIDTH(B_WIDTH), + .Y_WIDTH(A_WIDTH-(n-1)*`DSP_A_MAXWIDTH+B_WIDTH), + ) mul_slice_last ( + .A(A[A_WIDTH-1:(n-1)*`DSP_A_MAXWIDTH]), + .B(B), + .Y(partial[n-1][A_WIDTH-(n-1)*`DSP_A_MAXWIDTH+B_WIDTH-1:0]) + ); + //assign Y = (partial[n-1] << (n-1)*`DSP_A_MAXWIDTH) + partial_sum[n-2]; + assign Y = { + partial[n-1][A_WIDTH-(n-1)*`DSP_A_MAXWIDTH+B_WIDTH:0] + + partial_sum[n-2][Y_WIDTH-1:((n-1)*`DSP_A_MAXWIDTH)], + partial_sum[n-2][((n-1)*`DSP_A_MAXWIDTH)-1:0] + }; + end + else if (B_WIDTH > `DSP_B_MAXWIDTH) begin + localparam n_floored = B_WIDTH/`DSP_B_MAXWIDTH; + localparam n = n_floored + (n_floored*`DSP_B_MAXWIDTH < B_WIDTH ? 1 : 0); + wire [A_WIDTH+`DSP_B_MAXWIDTH-1:0] partial [n-1:1]; + wire [Y_WIDTH-1:0] partial_sum [n-2:0]; + + \$__mul_gen #( + .A_SIGNED(A_SIGNED), + .B_SIGNED(B_SIGNED), + .A_WIDTH(A_WIDTH), + .B_WIDTH(`DSP_B_MAXWIDTH), + .Y_WIDTH(A_WIDTH+`DSP_B_MAXWIDTH) + ) mul_first ( + .A(A), + .B(B[`DSP_B_MAXWIDTH-1:0]), + .Y(partial_sum[0][A_WIDTH+`DSP_B_MAXWIDTH-1:0]) + ); + assign partial_sum[0][Y_WIDTH-1:A_WIDTH+`DSP_B_MAXWIDTH]=0; + + genvar i; + generate + for (i = 1; i < n-1; i=i+1) begin:slice + \$__mul_gen #( + .A_SIGNED(A_SIGNED), + .B_SIGNED(B_SIGNED), + .A_WIDTH(A_WIDTH), + .B_WIDTH(`DSP_B_MAXWIDTH), + .Y_WIDTH(A_WIDTH+`DSP_B_MAXWIDTH) + ) mul ( + .A(A), + .B(B[(i+1)*`DSP_B_MAXWIDTH-1:i*`DSP_B_MAXWIDTH]), + .Y(partial[i][A_WIDTH+`DSP_B_MAXWIDTH-1:0]) + ); + //assign partial_sum[i] = (partial[i] << i*`DSP_B_MAXWIDTH) + partial_sum[i-1]; + // was: + //assign partial_sum[i] = { + // partial[i][A_WIDTH+`DSP_B_MAXWIDTH-1:`DSP_B_MAXWIDTH], + // partial[i][`DSP_B_MAXWIDTH-1:0] + partial_sum[i-1][A_WIDTH+(i*`DSP_B_MAXWIDTH)-1:A_WIDTH+((i-1)*`DSP_B_MAXWIDTH)], + // partial_sum[i-1][A_WIDTH+((i-1)*`DSP_B_MAXWIDTH):0] + assign partial_sum[i] = { + partial[i][A_WIDTH+`DSP_B_MAXWIDTH-1:0] + + partial_sum[i-1][Y_WIDTH-1:(i*`DSP_B_MAXWIDTH)], + partial_sum[i-1][(i*`DSP_B_MAXWIDTH)-1:0] + }; + end + endgenerate + + \$__mul_gen #( + .A_SIGNED(A_SIGNED), + .B_SIGNED(B_SIGNED), + .A_WIDTH(A_WIDTH), + .B_WIDTH(B_WIDTH-(n-1)*`DSP_B_MAXWIDTH), + .Y_WIDTH(A_WIDTH+B_WIDTH-(n-1)*`DSP_B_MAXWIDTH) + ) mul_last ( + .A(A), + .B(B[B_WIDTH-1:(n-1)*`DSP_B_MAXWIDTH]), + .Y(partial[n-1][A_WIDTH+B_WIDTH-(n-1)*`DSP_B_MAXWIDTH-1:0]) + ); + // AMD: this came comment out -- looks closer to right answer + //assign Y = (partial[n-1] << (n-1)*`DSP_B_MAXWIDTH) + partial_sum[n-2]; + // was (looks broken) + //assign Y = { + // partial[n-1][A_WIDTH+`DSP_B_MAXWIDTH-1:`DSP_B_MAXWIDTH], + // partial[n-1][`DSP_B_MAXWIDTH-1:0] + partial_sum[n-2][A_WIDTH+((n-1)*`DSP_B_MAXWIDTH)-1:A_WIDTH+((n-2)*`DSP_B_MAXWIDTH)], + // partial_sum[n-2][A_WIDTH+((n-2)*`DSP_B_MAXWIDTH):0] + assign Y = { + partial[n-1][A_WIDTH+B_WIDTH-(n-1)*`DSP_B_MAXWIDTH-1:0] + + partial_sum[n-2][Y_WIDTH-1:((n-1)*`DSP_B_MAXWIDTH)], + partial_sum[n-2][((n-1)*`DSP_B_MAXWIDTH)-1:0] + }; + end + else begin + wire [A_WIDTH+B_WIDTH-1:0] out; + wire [(`DSP_A_MAXWIDTH+`DSP_B_MAXWIDTH)-(A_WIDTH+B_WIDTH)-1:0] dummy; + wire Asign, Bsign; + assign Asign = (A_SIGNED ? A[A_WIDTH-1] : 1'b0); + assign Bsign = (B_SIGNED ? B[B_WIDTH-1] : 1'b0); + `DSP_NAME _TECHMAP_REPLACE_ ( + .A({ {{`DSP_A_MAXWIDTH-A_WIDTH}{Asign}}, A }), + .B({ {{`DSP_B_MAXWIDTH-B_WIDTH}{Bsign}}, B }), + .OUT({dummy, out}) + ); + if (Y_WIDTH < A_WIDTH+B_WIDTH) + assign Y = out[Y_WIDTH-1:0]; + else begin + wire Ysign = (A_SIGNED || B_SIGNED ? out[A_WIDTH+BWIDTH-1] : 1'b0); + assign Y = { {{Y_WIDTH-(A_WIDTH+B_WIDTH)}{Ysign}}, out[A_WIDTH+B_WIDTH-1:0] }; + end + end + endgenerate +endmodule + + diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc index ff39ba4fe..a2f5cadee 100644 --- a/techlibs/ecp5/Makefile.inc +++ b/techlibs/ecp5/Makefile.inc @@ -10,6 +10,7 @@ $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/brams_map.v)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram.txt)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/arith_map.v)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/latches_map.v)) +$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/dsp_map.v)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g.box)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g.lut)) diff --git a/techlibs/ecp5/dsp_map.v b/techlibs/ecp5/dsp_map.v new file mode 100644 index 000000000..22e30574c --- /dev/null +++ b/techlibs/ecp5/dsp_map.v @@ -0,0 +1,10 @@ +module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] OUT); + MULT18X18D mult_i( + .A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .A4(A[4]), .A5(A[5]), .A6(A[6]), .A7(A[7]), .A8(A[8]), .A9(A[9]), .A10(A[10]), .A11(A[11]), .A12(A[12]), .A13(A[13]), .A14(A[14]), .A15(A[15]), .A16(A[16]), .A17(A[17]), + .B0(B[0]), .B1(B[1]), .B2(B[2]), .B3(B[3]), .B4(B[4]), .B5(B[5]), .B6(B[6]), .B7(B[7]), .B8(B[8]), .B9(B[9]), .B10(B[10]), .B11(B[11]), .B12(B[12]), .B13(B[13]), .B14(B[14]), .B15(B[15]), .B16(B[16]), .B17(B[17]), + .C17(1'b0), .C16(1'b0), .C15(1'b0), .C14(1'b0), .C13(1'b0), .C12(1'b0), .C11(1'b0), .C10(1'b0), .C9(1'b0), .C8(1'b0), .C7(1'b0), .C6(1'b0), .C5(1'b0), .C4(1'b0), .C3(1'b0), .C2(1'b0), .C1(1'b0), .C0(1'b0), + .SIGNEDA(1'b0), .SIGNEDB(1'b0), .SOURCEA(1'b0), .SOURCEB(1'b0), + + .P0(OUT[0]), .P1(OUT[1]), .P2(OUT[2]), .P3(OUT[3]), .P4(OUT[4]), .P5(OUT[5]), .P6(OUT[6]), .P7(OUT[7]), .P8(OUT[8]), .P9(OUT[9]), .P10(OUT[10]), .P11(OUT[11]), .P12(OUT[12]), .P13(OUT[13]), .P14(OUT[14]), .P15(OUT[15]), .P16(OUT[16]), .P17(OUT[17]), .P18(OUT[18]), .P19(OUT[19]), .P20(OUT[20]), .P21(OUT[21]), .P22(OUT[22]), .P23(OUT[23]), .P24(OUT[24]), .P25(OUT[25]), .P26(OUT[26]), .P27(OUT[27]), .P28(OUT[28]), .P29(OUT[29]), .P30(OUT[30]), .P31(OUT[31]), .P32(OUT[32]), .P33(OUT[33]), .P34(OUT[34]), .P35(OUT[35]) + ); +endmodule \ No newline at end of file diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index f16a47f01..3b4185930 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -89,6 +89,9 @@ struct SynthEcp5Pass : public ScriptPass log(" generate an output netlist (and BLIF file) suitable for VPR\n"); log(" (this feature is experimental and incomplete)\n"); log("\n"); + log(" -dsp\n"); + log(" map multipliers to MULT18X18D (EXPERIMENTAL)\n"); + log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); help_script(); @@ -96,7 +99,7 @@ struct SynthEcp5Pass : public ScriptPass } string top_opt, blif_file, edif_file, json_file; - bool noccu2, nodffe, nobram, nodram, nowidelut, flatten, retime, abc2, abc9, vpr; + bool noccu2, nodffe, nobram, nodram, nowidelut, flatten, retime, abc2, abc9, dsp, vpr; void clear_flags() YS_OVERRIDE { @@ -114,6 +117,7 @@ struct SynthEcp5Pass : public ScriptPass abc2 = false; vpr = false; abc9 = false; + dsp = false; } void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE @@ -192,6 +196,10 @@ struct SynthEcp5Pass : public ScriptPass abc9 = true; continue; } + if (args[argidx] == "-dsp") { + dsp = true; + continue; + } break; } extra_args(args, argidx, design); @@ -225,7 +233,28 @@ struct SynthEcp5Pass : public ScriptPass if (check_label("coarse")) { - run("synth -run coarse"); + run("opt_expr"); + run("opt_clean"); + run("check"); + run("opt"); + run("wreduce"); + run("peepopt"); + run("opt_clean"); + run("share"); + run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4"); + run("opt_expr"); + run("opt_clean"); + if (dsp) { + run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 -D DSP_NAME=$__MUL18X18"); + run("clean"); + run("techmap -map +/ecp5/dsp_map.v"); + } + run("alumacc"); + run("opt"); + run("fsm"); + run("opt -fast"); + run("memory -nomap"); + run("opt_clean"); } if (!nobram && check_label("bram", "(skip if -nobram)")) -- cgit v1.2.3 From e78864993adab41492670c089f6365088426726f Mon Sep 17 00:00:00 2001 From: David Shah Date: Mon, 8 Jul 2019 15:43:48 +0100 Subject: mul2dsp: Fix typo Signed-off-by: David Shah --- techlibs/common/mul2dsp.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 37ce2e485..ece45db79 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -227,7 +227,7 @@ module \$__mul_gen (A, B, Y); if (Y_WIDTH < A_WIDTH+B_WIDTH) assign Y = out[Y_WIDTH-1:0]; else begin - wire Ysign = (A_SIGNED || B_SIGNED ? out[A_WIDTH+BWIDTH-1] : 1'b0); + wire Ysign = (A_SIGNED || B_SIGNED ? out[A_WIDTH+B_WIDTH-1] : 1'b0); assign Y = { {{Y_WIDTH-(A_WIDTH+B_WIDTH)}{Ysign}}, out[A_WIDTH+B_WIDTH-1:0] }; end end -- cgit v1.2.3 From c865559f9540c29cb9c6302edc8b4a2620c0b49d Mon Sep 17 00:00:00 2001 From: David Shah Date: Mon, 8 Jul 2019 19:15:25 +0100 Subject: xc7: Map combinational DSP48E1s Signed-off-by: David Shah --- techlibs/ecp5/dsp_map.v | 4 ++-- techlibs/xilinx/Makefile.inc | 1 + techlibs/xilinx/dsp_map.v | 40 ++++++++++++++++++++++++++++++++++++++++ techlibs/xilinx/synth_xilinx.cc | 39 ++++++++++++++++++++++++++++++++++----- 4 files changed, 77 insertions(+), 7 deletions(-) create mode 100644 techlibs/xilinx/dsp_map.v (limited to 'techlibs') diff --git a/techlibs/ecp5/dsp_map.v b/techlibs/ecp5/dsp_map.v index 22e30574c..5f7755afb 100644 --- a/techlibs/ecp5/dsp_map.v +++ b/techlibs/ecp5/dsp_map.v @@ -1,5 +1,5 @@ module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] OUT); - MULT18X18D mult_i( + MULT18X18D _TECHMAP_REPLACE_ ( .A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .A4(A[4]), .A5(A[5]), .A6(A[6]), .A7(A[7]), .A8(A[8]), .A9(A[9]), .A10(A[10]), .A11(A[11]), .A12(A[12]), .A13(A[13]), .A14(A[14]), .A15(A[15]), .A16(A[16]), .A17(A[17]), .B0(B[0]), .B1(B[1]), .B2(B[2]), .B3(B[3]), .B4(B[4]), .B5(B[5]), .B6(B[6]), .B7(B[7]), .B8(B[8]), .B9(B[9]), .B10(B[10]), .B11(B[11]), .B12(B[12]), .B13(B[13]), .B14(B[14]), .B15(B[15]), .B16(B[16]), .B17(B[17]), .C17(1'b0), .C16(1'b0), .C15(1'b0), .C14(1'b0), .C13(1'b0), .C12(1'b0), .C11(1'b0), .C10(1'b0), .C9(1'b0), .C8(1'b0), .C7(1'b0), .C6(1'b0), .C5(1'b0), .C4(1'b0), .C3(1'b0), .C2(1'b0), .C1(1'b0), .C0(1'b0), @@ -7,4 +7,4 @@ module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] OUT); .P0(OUT[0]), .P1(OUT[1]), .P2(OUT[2]), .P3(OUT[3]), .P4(OUT[4]), .P5(OUT[5]), .P6(OUT[6]), .P7(OUT[7]), .P8(OUT[8]), .P9(OUT[9]), .P10(OUT[10]), .P11(OUT[11]), .P12(OUT[12]), .P13(OUT[13]), .P14(OUT[14]), .P15(OUT[15]), .P16(OUT[16]), .P17(OUT[17]), .P18(OUT[18]), .P19(OUT[19]), .P20(OUT[20]), .P21(OUT[21]), .P22(OUT[22]), .P23(OUT[23]), .P24(OUT[24]), .P25(OUT[25]), .P26(OUT[26]), .P27(OUT[27]), .P28(OUT[28]), .P29(OUT[29]), .P30(OUT[30]), .P31(OUT[31]), .P32(OUT[32]), .P33(OUT[33]), .P34(OUT[34]), .P35(OUT[35]) ); -endmodule \ No newline at end of file +endmodule diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc index 17c5df37d..c41015e94 100644 --- a/techlibs/xilinx/Makefile.inc +++ b/techlibs/xilinx/Makefile.inc @@ -31,6 +31,7 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/mux_map.v)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/dsp_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.box)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.lut)) diff --git a/techlibs/xilinx/dsp_map.v b/techlibs/xilinx/dsp_map.v new file mode 100644 index 000000000..4faa204aa --- /dev/null +++ b/techlibs/xilinx/dsp_map.v @@ -0,0 +1,40 @@ +module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] OUT); + wire [47:0] P_48; + DSP48E1 #( + // Disable all registers + .ACASCREG(0), + .ADREG(0), + .A_INPUT("DIRECT"), + .ALUMODEREG(0), + .AREG(0), + .BCASCREG(0), + .B_INPUT("DIRECT"), + .BREG(0), + .CARRYINREG(0), + .CARRYINSELREG(0), + .CREG(0), + .DREG(0), + .INMODEREG(0), + .MREG(0), + .OPMODEREG(0), + .PREG(0) + ) _TECHMAP_REPLACE_ ( + //Data path + .A({5'b0, A}), + .B(B), + .C(48'b0), + .D(24'b0), + .P(P_48), + + .INMODE(4'b0000), + .ALUMODE(4'b0000), + .OPMODE(7'b000101), + .CARRYINSEL(3'b000), + + .ACIN(30'b0), + .BCIN(18'b0), + .PCIN(48'b0), + .CARRYIN(1'b0) + ); + assign OUT = P_48; +endmodule diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 0a30848aa..db0cbb644 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -77,6 +77,9 @@ struct SynthXilinxPass : public ScriptPass log(" -nowidelut\n"); log(" do not use MUXF[78] resources to implement LUTs larger than LUT6s\n"); log("\n"); + log(" -nodsp\n"); + log(" do not use DSP48E1s to implement multipliers and associated logic\n"); + log("\n"); log(" -widemux \n"); log(" enable inference of hard multiplexer resources (MuxFx) for muxes at or\n"); log(" above this number of inputs (minimum value 5).\n"); @@ -103,7 +106,7 @@ struct SynthXilinxPass : public ScriptPass } std::string top_opt, edif_file, blif_file, family; - bool flatten, retime, vpr, nobram, nodram, nosrl, nocarry, nowidelut, abc9; + bool flatten, retime, vpr, nobram, nodram, nosrl, nocarry, nowidelut, nodsp, abc9; int widemux; void clear_flags() YS_OVERRIDE @@ -121,6 +124,7 @@ struct SynthXilinxPass : public ScriptPass nosrl = false; nocarry = false; nowidelut = false; + nodsp = false; abc9 = false; widemux = 0; } @@ -201,6 +205,10 @@ struct SynthXilinxPass : public ScriptPass abc9 = true; continue; } + if (args[argidx] == "-nodsp") { + nodsp = true; + continue; + } break; } extra_args(args, argidx, design); @@ -239,10 +247,31 @@ struct SynthXilinxPass : public ScriptPass } if (check_label("coarse")) { - if (help_mode) - run("synth -run coarse [-flatten]", "(with '-flatten')"); - else - run("synth -run coarse" + std::string(flatten ? "" : " -flatten"), "(with '-flatten')"); + run("proc"); + if (flatten || help_mode) + run("flatten", "(with '-flatten')"); + run("opt_expr"); + run("opt_clean"); + run("check"); + run("opt"); + run("wreduce"); + run("peepopt"); + run("opt_clean"); + run("share"); + run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4"); + run("opt_expr"); + run("opt_clean"); + if (!nodsp || help_mode) { + run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=25 -D DSP_B_MAXWIDTH=18 -D DSP_NAME=$__MUL25X18"); + run("clean"); + run("techmap -map +/xilinx/dsp_map.v"); + } + run("alumacc"); + run("opt"); + run("fsm"); + run("opt -fast"); + run("memory -nomap"); + run("opt_clean"); if (widemux > 0 || help_mode) run("muxpack", " ('-widemux' only)"); -- cgit v1.2.3 From b33ecd2a746b734fda33d8535afecf76bd35f59c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 10 Jul 2019 16:00:03 -0700 Subject: Move dsp_map.v into cells_map.v; cleanup synth_xilinx a little --- techlibs/xilinx/Makefile.inc | 1 - techlibs/xilinx/cells_map.v | 41 +++++++++++++++++++++++++++++++++++++++++ techlibs/xilinx/dsp_map.v | 40 ---------------------------------------- techlibs/xilinx/synth_xilinx.cc | 5 +---- 4 files changed, 42 insertions(+), 45 deletions(-) delete mode 100644 techlibs/xilinx/dsp_map.v (limited to 'techlibs') diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc index c41015e94..17c5df37d 100644 --- a/techlibs/xilinx/Makefile.inc +++ b/techlibs/xilinx/Makefile.inc @@ -31,7 +31,6 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/mux_map.v)) -$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/dsp_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.box)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.lut)) diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index 2eb9fa2c1..6ebca0d54 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -365,3 +365,44 @@ module \$__XILINX_MUXF78 (O, I0, I1, I2, I3, S0, S1); MUXF8 mux8 (.I0(T0), .I1(T1), .S(S1), .O(O)); endmodule `endif + +module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] OUT); + wire [47:0] P_48; + DSP48E1 #( + // Disable all registers + .ACASCREG(0), + .ADREG(0), + .A_INPUT("DIRECT"), + .ALUMODEREG(0), + .AREG(0), + .BCASCREG(0), + .B_INPUT("DIRECT"), + .BREG(0), + .CARRYINREG(0), + .CARRYINSELREG(0), + .CREG(0), + .DREG(0), + .INMODEREG(0), + .MREG(0), + .OPMODEREG(0), + .PREG(0) + ) _TECHMAP_REPLACE_ ( + //Data path + .A({5'b0, A}), + .B(B), + .C(48'b0), + .D(24'b0), + .P(P_48), + + .INMODE(4'b0000), + .ALUMODE(4'b0000), + .OPMODE(7'b000101), + .CARRYINSEL(3'b000), + + .ACIN(30'b0), + .BCIN(18'b0), + .PCIN(48'b0), + .CARRYIN(1'b0) + ); + assign OUT = P_48; +endmodule diff --git a/techlibs/xilinx/dsp_map.v b/techlibs/xilinx/dsp_map.v deleted file mode 100644 index 4faa204aa..000000000 --- a/techlibs/xilinx/dsp_map.v +++ /dev/null @@ -1,40 +0,0 @@ -module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] OUT); - wire [47:0] P_48; - DSP48E1 #( - // Disable all registers - .ACASCREG(0), - .ADREG(0), - .A_INPUT("DIRECT"), - .ALUMODEREG(0), - .AREG(0), - .BCASCREG(0), - .B_INPUT("DIRECT"), - .BREG(0), - .CARRYINREG(0), - .CARRYINSELREG(0), - .CREG(0), - .DREG(0), - .INMODEREG(0), - .MREG(0), - .OPMODEREG(0), - .PREG(0) - ) _TECHMAP_REPLACE_ ( - //Data path - .A({5'b0, A}), - .B(B), - .C(48'b0), - .D(24'b0), - .P(P_48), - - .INMODE(4'b0000), - .ALUMODE(4'b0000), - .OPMODE(7'b000101), - .CARRYINSEL(3'b000), - - .ACIN(30'b0), - .BCIN(18'b0), - .PCIN(48'b0), - .CARRYIN(1'b0) - ); - assign OUT = P_48; -endmodule diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 3da35db75..9199fbb53 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -279,11 +279,8 @@ struct SynthXilinxPass : public ScriptPass run("techmap -map +/cmp2lut.v -D LUT_WIDTH=6"); - if (!nodsp || help_mode) { + if (!nodsp || help_mode) run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=25 -D DSP_B_MAXWIDTH=18 -D DSP_NAME=$__MUL25X18"); - run("clean"); - run("techmap -map +/xilinx/dsp_map.v"); - } run("alumacc"); run("share"); -- cgit v1.2.3 From 20e3d2d9b0857dae9b03a7fc50b2cce4bced27f0 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 15 Jul 2019 11:13:22 -0700 Subject: Move DSP48E1 model out of cells_xtra, initial multiply one in cells_sim --- techlibs/xilinx/cells_sim.v | 131 +++++++++++++++++++++++++++++++++++++++++++ techlibs/xilinx/cells_xtra.v | 82 --------------------------- 2 files changed, 131 insertions(+), 82 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 05e46b4e7..99120452c 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -378,3 +378,134 @@ module SRLC32E ( always @(posedge CLK) if (CE) r <= { r[30:0], D }; endgenerate endmodule + +module DSP48E1 ( + output [29:0] ACOUT, + output [17:0] BCOUT, + output CARRYCASCOUT, + output [3:0] CARRYOUT, + output MULTSIGNOUT, + output OVERFLOW, + output reg [47:0] P, + output PATTERNBDETECT, + output PATTERNDETECT, + output [47:0] PCOUT, + output UNDERFLOW, + input [29:0] A, + input [29:0] ACIN, + input [3:0] ALUMODE, + input [17:0] B, + input [17:0] BCIN, + input [47:0] C, + input CARRYCASCIN, + input CARRYIN, + input [2:0] CARRYINSEL, + input CEA1, + input CEA2, + input CEAD, + input CEALUMODE, + input CEB1, + input CEB2, + input CEC, + input CECARRYIN, + input CECTRL, + input CED, + input CEINMODE, + input CEM, + input CEP, + input CLK, + input [24:0] D, + input [4:0] INMODE, + input MULTSIGNIN, + input [6:0] OPMODE, + input [47:0] PCIN, + input RSTA, + input RSTALLCARRYIN, + input RSTALUMODE, + input RSTB, + input RSTC, + input RSTCTRL, + input RSTD, + input RSTINMODE, + input RSTM, + input RSTP +); + parameter integer ACASCREG = 1; + parameter integer ADREG = 1; + parameter integer ALUMODEREG = 1; + parameter integer AREG = 1; + parameter AUTORESET_PATDET = "NO_RESET"; + parameter A_INPUT = "DIRECT"; + parameter integer BCASCREG = 1; + parameter integer BREG = 1; + parameter B_INPUT = "DIRECT"; + parameter integer CARRYINREG = 1; + parameter integer CARRYINSELREG = 1; + parameter integer CREG = 1; + parameter integer DREG = 1; + parameter integer INMODEREG = 1; + parameter integer MREG = 1; + parameter integer OPMODEREG = 1; + parameter integer PREG = 1; + parameter SEL_MASK = "MASK"; + parameter SEL_PATTERN = "PATTERN"; + parameter USE_DPORT = "FALSE"; + parameter USE_MULT = "MULTIPLY"; + parameter USE_PATTERN_DETECT = "NO_PATDET"; + parameter USE_SIMD = "ONE48"; + parameter [47:0] MASK = 48'h3FFFFFFFFFFF; + parameter [47:0] PATTERN = 48'h000000000000; + parameter [3:0] IS_ALUMODE_INVERTED = 4'b0; + parameter [0:0] IS_CARRYIN_INVERTED = 1'b0; + parameter [0:0] IS_CLK_INVERTED = 1'b0; + parameter [4:0] IS_INMODE_INVERTED = 5'b0; + parameter [6:0] IS_OPMODE_INVERTED = 7'b0; + + initial begin +`ifdef __ICARUS__ + if (ACASCREG != 0) $fatal(1, "Unsupported ACASCREG value"); + if (ADREG != 0) $fatal(1, "Unsupported ADREG value"); + if (ALUMODEREG != 0) $fatal(1, "Unsupported ALUMODEREG value"); + if (AREG != 0) $fatal(1, "Unsupported AREG value"); + if (AUTORESET_PATDET != "NO_RESET") $fatal(1, "Unsupported AUTORESET_PATDET value"); + if (A_INPUT != "DIRECT") $fatal(1, "Unsupported A_INPUT value"); + if (BCASCREG != 0) $fatal(1, "Unsupported BCASCREG value"); + if (BREG != 0) $fatal(1, "Unsupported BREG value"); + if (B_INPUT != "DIRECT") $fatal(1, "Unsupported B_INPUT value"); + if (CARRYINREG != 0) $fatal(1, "Unsupported CARRYINREG value"); + if (CARRYINSELREG != 0) $fatal(1, "Unsupported CARRYINSELREG value"); + if (CREG != 0) $fatal(1, "Unsupported CREG value"); + if (DREG != 0) $fatal(1, "Unsupported DREG value"); + if (INMODEREG != 0) $fatal(1, "Unsupported INMODEREG value"); + if (MREG != 0) $fatal(1, "Unsupported MREG value"); + if (OPMODEREG != 0) $fatal(1, "Unsupported OPMODEREG value"); + if (PREG != 0) $fatal(1, "Unsupported PREG value"); + if (SEL_MASK != "MASK") $fatal(1, "Unsupported SEL_MASK value"); + if (SEL_PATTERN != "PATTERN") $fatal(1, "Unsupported SEL_PATTERN value"); + if (USE_DPORT != "FALSE") $fatal(1, "Unsupported USE_DPORT value"); + if (USE_MULT != "MULTIPLY") $fatal(1, "Unsupported USE_MULT value"); + if (USE_PATTERN_DETECT != "NO_PATDET") $fatal(1, "Unsupported USE_PATTERN_DETECT value"); + if (USE_SIMD != "ONE48") $fatal(1, "Unsupported USE_SIMD value"); + if (IS_ALUMODE_INVERTED != 4'b0) $fatal(1, "Unsupported IS_ALUMODE_INVERTED value"); + if (IS_CARRYIN_INVERTED != 1'b0) $fatal(1, "Unsupported IS_CARRYIN_INVERTED value"); + if (IS_CLK_INVERTED != 1'b0) $fatal(1, "Unsupported IS_CLK_INVERTED value"); + if (IS_INMODE_INVERTED != 5'b0) $fatal(1, "Unsupported IS_INMODE_INVERTED value"); + if (IS_OPMODE_INVERTED != 7'b0) $fatal(1, "Unsupported IS_OPMODE_INVERTED value"); +`endif + end + + always @* begin + P <= {48{1'bx}}; +`ifdef __ICARUS__ + if (INMODE != 4'b0000) $fatal(1, "Unsupported INMODE value"); + if (ALUMODE != 4'b0000) $fatal(1, "Unsupported ALUMODE value"); + if (OPMODE != 7'b000101) $fatal(1, "Unsupported OPMODE value"); + if (CARRYINSEL != 3'b000) $fatal(1, "Unsupported CARRYINSEL value"); + if (ACIN != 30'b0) $fatal(1, "Unsupported ACIN value"); + if (BCIN != 18'b0) $fatal(1, "Unsupported BCIN value"); + if (PCIN != 48'b0) $fatal(1, "Unsupported PCIN value"); + if (CARRYIN != 1'b0) $fatal(1, "Unsupported CARRYIN value"); +`endif + P[42:0] <= A[24:0] * B; + end +endmodule diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v index 15fa1b63a..d79349225 100644 --- a/techlibs/xilinx/cells_xtra.v +++ b/techlibs/xilinx/cells_xtra.v @@ -111,88 +111,6 @@ module DNA_PORT (...); input CLK, DIN, READ, SHIFT; endmodule -module DSP48E1 (...); - parameter integer ACASCREG = 1; - parameter integer ADREG = 1; - parameter integer ALUMODEREG = 1; - parameter integer AREG = 1; - parameter AUTORESET_PATDET = "NO_RESET"; - parameter A_INPUT = "DIRECT"; - parameter integer BCASCREG = 1; - parameter integer BREG = 1; - parameter B_INPUT = "DIRECT"; - parameter integer CARRYINREG = 1; - parameter integer CARRYINSELREG = 1; - parameter integer CREG = 1; - parameter integer DREG = 1; - parameter integer INMODEREG = 1; - parameter integer MREG = 1; - parameter integer OPMODEREG = 1; - parameter integer PREG = 1; - parameter SEL_MASK = "MASK"; - parameter SEL_PATTERN = "PATTERN"; - parameter USE_DPORT = "FALSE"; - parameter USE_MULT = "MULTIPLY"; - parameter USE_PATTERN_DETECT = "NO_PATDET"; - parameter USE_SIMD = "ONE48"; - parameter [47:0] MASK = 48'h3FFFFFFFFFFF; - parameter [47:0] PATTERN = 48'h000000000000; - parameter [3:0] IS_ALUMODE_INVERTED = 4'b0; - parameter [0:0] IS_CARRYIN_INVERTED = 1'b0; - parameter [0:0] IS_CLK_INVERTED = 1'b0; - parameter [4:0] IS_INMODE_INVERTED = 5'b0; - parameter [6:0] IS_OPMODE_INVERTED = 7'b0; - output [29:0] ACOUT; - output [17:0] BCOUT; - output CARRYCASCOUT; - output [3:0] CARRYOUT; - output MULTSIGNOUT; - output OVERFLOW; - output [47:0] P; - output PATTERNBDETECT; - output PATTERNDETECT; - output [47:0] PCOUT; - output UNDERFLOW; - input [29:0] A; - input [29:0] ACIN; - input [3:0] ALUMODE; - input [17:0] B; - input [17:0] BCIN; - input [47:0] C; - input CARRYCASCIN; - input CARRYIN; - input [2:0] CARRYINSEL; - input CEA1; - input CEA2; - input CEAD; - input CEALUMODE; - input CEB1; - input CEB2; - input CEC; - input CECARRYIN; - input CECTRL; - input CED; - input CEINMODE; - input CEM; - input CEP; - input CLK; - input [24:0] D; - input [4:0] INMODE; - input MULTSIGNIN; - input [6:0] OPMODE; - input [47:0] PCIN; - input RSTA; - input RSTALLCARRYIN; - input RSTALUMODE; - input RSTB; - input RSTC; - input RSTCTRL; - input RSTD; - input RSTINMODE; - input RSTM; - input RSTP; -endmodule - module EFUSE_USR (...); parameter [31:0] SIM_EFUSE_VALUE = 32'h00000000; output [31:0] EFUSEUSR; -- cgit v1.2.3 From 1793e6018a37af674a356769779674e095fae261 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 15 Jul 2019 11:19:54 -0700 Subject: Tidy up --- techlibs/common/mul2dsp.v | 65 +++++++++++++++++++---------------------------- 1 file changed, 26 insertions(+), 39 deletions(-) (limited to 'techlibs') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index ece45db79..d2e68987b 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -32,40 +32,32 @@ module \$mul (A, B, Y); input [B_WIDTH-1:0] B; output [Y_WIDTH-1:0] Y; - wire [1023:0] _TECHMAP_DO_ = "proc; clean"; - - generate - if (A_WIDTH `DSP_A_MAXWIDTH) begin + if (A_WIDTH > `DSP_A_MAXWIDTH) begin localparam n_floored = A_WIDTH/`DSP_A_MAXWIDTH; localparam n = n_floored + (n_floored*`DSP_A_MAXWIDTH < A_WIDTH ? 1 : 0); wire [`DSP_A_MAXWIDTH+B_WIDTH-1:0] partial [n-1:1]; @@ -101,8 +94,6 @@ module \$__mul_gen (A, B, Y); ); assign partial_sum[0][Y_WIDTH-1:B_WIDTH+`DSP_A_MAXWIDTH]=0; - genvar i; - generate for (i = 1; i < n-1; i=i+1) begin:slice \$__mul_gen #( .A_SIGNED(A_SIGNED), @@ -122,7 +113,6 @@ module \$__mul_gen (A, B, Y); partial_sum[i-1][(i*`DSP_A_MAXWIDTH)-1:0] }; end - endgenerate \$__mul_gen #( .A_SIGNED(A_SIGNED), @@ -161,8 +151,6 @@ module \$__mul_gen (A, B, Y); ); assign partial_sum[0][Y_WIDTH-1:A_WIDTH+`DSP_B_MAXWIDTH]=0; - genvar i; - generate for (i = 1; i < n-1; i=i+1) begin:slice \$__mul_gen #( .A_SIGNED(A_SIGNED), @@ -187,7 +175,6 @@ module \$__mul_gen (A, B, Y); partial_sum[i-1][(i*`DSP_B_MAXWIDTH)-1:0] }; end - endgenerate \$__mul_gen #( .A_SIGNED(A_SIGNED), -- cgit v1.2.3 From 91fcf034bceecd50f1aaf96c3cdc270250ab9597 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 15 Jul 2019 11:24:11 -0700 Subject: Only swap if B_WIDTH > A_WIDTH --- techlibs/common/mul2dsp.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index d2e68987b..0eec4cc82 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -33,7 +33,7 @@ module \$mul (A, B, Y); output [Y_WIDTH-1:0] Y; generate - if (A_WIDTH < B_WIDTH) + if (B_WIDTH < A_WIDTH) \$__mul_gen #( .A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), -- cgit v1.2.3 From 0c7ee6d0fa14b634ffbde5ad79983cb89372a697 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 15 Jul 2019 14:18:44 -0700 Subject: Move DSP mapping back out to dsp_map.v --- techlibs/xilinx/cells_map.v | 41 ----------------------------------------- techlibs/xilinx/dsp_map.v | 40 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 40 insertions(+), 41 deletions(-) create mode 100644 techlibs/xilinx/dsp_map.v (limited to 'techlibs') diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index 6ebca0d54..2eb9fa2c1 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -365,44 +365,3 @@ module \$__XILINX_MUXF78 (O, I0, I1, I2, I3, S0, S1); MUXF8 mux8 (.I0(T0), .I1(T1), .S(S1), .O(O)); endmodule `endif - -module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] OUT); - wire [47:0] P_48; - DSP48E1 #( - // Disable all registers - .ACASCREG(0), - .ADREG(0), - .A_INPUT("DIRECT"), - .ALUMODEREG(0), - .AREG(0), - .BCASCREG(0), - .B_INPUT("DIRECT"), - .BREG(0), - .CARRYINREG(0), - .CARRYINSELREG(0), - .CREG(0), - .DREG(0), - .INMODEREG(0), - .MREG(0), - .OPMODEREG(0), - .PREG(0) - ) _TECHMAP_REPLACE_ ( - //Data path - .A({5'b0, A}), - .B(B), - .C(48'b0), - .D(24'b0), - .P(P_48), - - .INMODE(4'b0000), - .ALUMODE(4'b0000), - .OPMODE(7'b000101), - .CARRYINSEL(3'b000), - - .ACIN(30'b0), - .BCIN(18'b0), - .PCIN(48'b0), - .CARRYIN(1'b0) - ); - assign OUT = P_48; -endmodule diff --git a/techlibs/xilinx/dsp_map.v b/techlibs/xilinx/dsp_map.v new file mode 100644 index 000000000..da1d6f3a9 --- /dev/null +++ b/techlibs/xilinx/dsp_map.v @@ -0,0 +1,40 @@ +module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y); + wire [47:0] P_48; + DSP48E1 #( + // Disable all registers + .ACASCREG(0), + .ADREG(0), + .A_INPUT("DIRECT"), + .ALUMODEREG(0), + .AREG(0), + .BCASCREG(0), + .B_INPUT("DIRECT"), + .BREG(0), + .CARRYINREG(0), + .CARRYINSELREG(0), + .CREG(0), + .DREG(0), + .INMODEREG(0), + .MREG(0), + .OPMODEREG(0), + .PREG(0) + ) _TECHMAP_REPLACE_ ( + //Data path + .A({5'b0, A}), + .B(B), + .C(48'b0), + .D(24'b0), + .P(P_48), + + .INMODE(4'b0000), + .ALUMODE(4'b0000), + .OPMODE(7'b000101), + .CARRYINSEL(3'b000), + + .ACIN(30'b0), + .BCIN(18'b0), + .PCIN(48'b0), + .CARRYIN(1'b0) + ); + assign Y = P_48; +endmodule -- cgit v1.2.3 From 42f8e68e76a3717cf4ad29c36f0a9a801cde52c1 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 15 Jul 2019 14:45:47 -0700 Subject: OUT port to Y in generic DSP --- techlibs/common/mul2dsp.v | 2 +- techlibs/ecp5/dsp_map.v | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'techlibs') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 0eec4cc82..0a87716d9 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -209,7 +209,7 @@ module \$__mul_gen (A, B, Y); `DSP_NAME _TECHMAP_REPLACE_ ( .A({ {{`DSP_A_MAXWIDTH-A_WIDTH}{Asign}}, A }), .B({ {{`DSP_B_MAXWIDTH-B_WIDTH}{Bsign}}, B }), - .OUT({dummy, out}) + .Y({dummy, out}) ); if (Y_WIDTH < A_WIDTH+B_WIDTH) assign Y = out[Y_WIDTH-1:0]; diff --git a/techlibs/ecp5/dsp_map.v b/techlibs/ecp5/dsp_map.v index 5f7755afb..24e28869e 100644 --- a/techlibs/ecp5/dsp_map.v +++ b/techlibs/ecp5/dsp_map.v @@ -1,10 +1,10 @@ -module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] OUT); +module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y); MULT18X18D _TECHMAP_REPLACE_ ( .A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .A4(A[4]), .A5(A[5]), .A6(A[6]), .A7(A[7]), .A8(A[8]), .A9(A[9]), .A10(A[10]), .A11(A[11]), .A12(A[12]), .A13(A[13]), .A14(A[14]), .A15(A[15]), .A16(A[16]), .A17(A[17]), .B0(B[0]), .B1(B[1]), .B2(B[2]), .B3(B[3]), .B4(B[4]), .B5(B[5]), .B6(B[6]), .B7(B[7]), .B8(B[8]), .B9(B[9]), .B10(B[10]), .B11(B[11]), .B12(B[12]), .B13(B[13]), .B14(B[14]), .B15(B[15]), .B16(B[16]), .B17(B[17]), .C17(1'b0), .C16(1'b0), .C15(1'b0), .C14(1'b0), .C13(1'b0), .C12(1'b0), .C11(1'b0), .C10(1'b0), .C9(1'b0), .C8(1'b0), .C7(1'b0), .C6(1'b0), .C5(1'b0), .C4(1'b0), .C3(1'b0), .C2(1'b0), .C1(1'b0), .C0(1'b0), .SIGNEDA(1'b0), .SIGNEDB(1'b0), .SOURCEA(1'b0), .SOURCEB(1'b0), - .P0(OUT[0]), .P1(OUT[1]), .P2(OUT[2]), .P3(OUT[3]), .P4(OUT[4]), .P5(OUT[5]), .P6(OUT[6]), .P7(OUT[7]), .P8(OUT[8]), .P9(OUT[9]), .P10(OUT[10]), .P11(OUT[11]), .P12(OUT[12]), .P13(OUT[13]), .P14(OUT[14]), .P15(OUT[15]), .P16(OUT[16]), .P17(OUT[17]), .P18(OUT[18]), .P19(OUT[19]), .P20(OUT[20]), .P21(OUT[21]), .P22(OUT[22]), .P23(OUT[23]), .P24(OUT[24]), .P25(OUT[25]), .P26(OUT[26]), .P27(OUT[27]), .P28(OUT[28]), .P29(OUT[29]), .P30(OUT[30]), .P31(OUT[31]), .P32(OUT[32]), .P33(OUT[33]), .P34(OUT[34]), .P35(OUT[35]) + .P0(Y[0]), .P1(Y[1]), .P2(Y[2]), .P3(Y[3]), .P4(Y[4]), .P5(Y[5]), .P6(Y[6]), .P7(Y[7]), .P8(Y[8]), .P9(Y[9]), .P10(Y[10]), .P11(Y[11]), .P12(Y[12]), .P13(Y[13]), .P14(Y[14]), .P15(Y[15]), .P16(Y[16]), .P17(Y[17]), .P18(Y[18]), .P19(Y[19]), .P20(Y[20]), .P21(Y[21]), .P22(Y[22]), .P23(Y[23]), .P24(Y[24]), .P25(Y[25]), .P26(Y[26]), .P27(Y[27]), .P28(Y[28]), .P29(Y[29]), .P30(Y[30]), .P31(Y[31]), .P32(Y[32]), .P33(Y[33]), .P34(Y[34]), .P35(Y[35]) ); endmodule -- cgit v1.2.3 From 5f00d335d4861fc03dd7b6cee68fd79505bd3d41 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 15 Jul 2019 15:03:15 -0700 Subject: Oops forgot these files --- techlibs/xilinx/Makefile.inc | 1 + techlibs/xilinx/synth_xilinx.cc | 4 ++++ 2 files changed, 5 insertions(+) (limited to 'techlibs') diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc index 2c6e7432e..b0251d621 100644 --- a/techlibs/xilinx/Makefile.inc +++ b/techlibs/xilinx/Makefile.inc @@ -38,6 +38,7 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/mux_map.v)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/dsp_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.box)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.lut)) diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 01e75b50e..796615211 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -329,6 +329,10 @@ struct SynthXilinxPass : public ScriptPass run("memory_map"); run("dffsr2dff"); run("dff2dffe"); + if (help_mode || !nodsp) { + run("techmap -map +/xilinx/dsp_map.v", "(skip if '-nodsp')"); + run("xilinx_dsp", " (skip if '-nodsp')"); + } if (help_mode) { run("simplemap t:$mux", " ('-widemux' only)"); run("muxcover , ('-widemux' only)"); -- cgit v1.2.3 From fd5b3593d8496578c0879fc024bf81737be3702f Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 15 Jul 2019 16:52:37 -0700 Subject: Do not swap if equals --- techlibs/common/mul2dsp.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 0a87716d9..046f84320 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -33,7 +33,7 @@ module \$mul (A, B, Y); output [Y_WIDTH-1:0] Y; generate - if (B_WIDTH < A_WIDTH) + if (A_WIDTH >= B_WIDTH) \$__mul_gen #( .A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), -- cgit v1.2.3 From 7a75f5f3ac82aa764f41e8fbb93475ab729750dc Mon Sep 17 00:00:00 2001 From: David Shah Date: Tue, 16 Jul 2019 16:19:32 +0100 Subject: mul2dsp: Fix indentation Signed-off-by: David Shah --- techlibs/common/mul2dsp.v | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'techlibs') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 0eec4cc82..69de74cad 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -92,7 +92,7 @@ module \$__mul_gen (A, B, Y); .B(B), .Y(partial_sum[0][B_WIDTH+`DSP_A_MAXWIDTH-1:0]) ); - assign partial_sum[0][Y_WIDTH-1:B_WIDTH+`DSP_A_MAXWIDTH]=0; + assign partial_sum[0][Y_WIDTH-1:B_WIDTH+`DSP_A_MAXWIDTH]=0; for (i = 1; i < n-1; i=i+1) begin:slice \$__mul_gen #( @@ -149,7 +149,7 @@ module \$__mul_gen (A, B, Y); .B(B[`DSP_B_MAXWIDTH-1:0]), .Y(partial_sum[0][A_WIDTH+`DSP_B_MAXWIDTH-1:0]) ); - assign partial_sum[0][Y_WIDTH-1:A_WIDTH+`DSP_B_MAXWIDTH]=0; + assign partial_sum[0][Y_WIDTH-1:A_WIDTH+`DSP_B_MAXWIDTH]=0; for (i = 1; i < n-1; i=i+1) begin:slice \$__mul_gen #( @@ -157,14 +157,14 @@ module \$__mul_gen (A, B, Y); .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(`DSP_B_MAXWIDTH), - .Y_WIDTH(A_WIDTH+`DSP_B_MAXWIDTH) + .Y_WIDTH(A_WIDTH+`DSP_B_MAXWIDTH) ) mul ( .A(A), .B(B[(i+1)*`DSP_B_MAXWIDTH-1:i*`DSP_B_MAXWIDTH]), .Y(partial[i][A_WIDTH+`DSP_B_MAXWIDTH-1:0]) ); //assign partial_sum[i] = (partial[i] << i*`DSP_B_MAXWIDTH) + partial_sum[i-1]; - // was: + // was: //assign partial_sum[i] = { // partial[i][A_WIDTH+`DSP_B_MAXWIDTH-1:`DSP_B_MAXWIDTH], // partial[i][`DSP_B_MAXWIDTH-1:0] + partial_sum[i-1][A_WIDTH+(i*`DSP_B_MAXWIDTH)-1:A_WIDTH+((i-1)*`DSP_B_MAXWIDTH)], @@ -187,14 +187,14 @@ module \$__mul_gen (A, B, Y); .B(B[B_WIDTH-1:(n-1)*`DSP_B_MAXWIDTH]), .Y(partial[n-1][A_WIDTH+B_WIDTH-(n-1)*`DSP_B_MAXWIDTH-1:0]) ); - // AMD: this came comment out -- looks closer to right answer + // AMD: this came comment out -- looks closer to right answer //assign Y = (partial[n-1] << (n-1)*`DSP_B_MAXWIDTH) + partial_sum[n-2]; - // was (looks broken) + // was (looks broken) //assign Y = { // partial[n-1][A_WIDTH+`DSP_B_MAXWIDTH-1:`DSP_B_MAXWIDTH], // partial[n-1][`DSP_B_MAXWIDTH-1:0] + partial_sum[n-2][A_WIDTH+((n-1)*`DSP_B_MAXWIDTH)-1:A_WIDTH+((n-2)*`DSP_B_MAXWIDTH)], // partial_sum[n-2][A_WIDTH+((n-2)*`DSP_B_MAXWIDTH):0] - assign Y = { + assign Y = { partial[n-1][A_WIDTH+B_WIDTH-(n-1)*`DSP_B_MAXWIDTH-1:0] + partial_sum[n-2][Y_WIDTH-1:((n-1)*`DSP_B_MAXWIDTH)], partial_sum[n-2][((n-1)*`DSP_B_MAXWIDTH)-1:0] -- cgit v1.2.3 From 8da4c1ad8262216c5204c735f5297da33fed01fa Mon Sep 17 00:00:00 2001 From: David Shah Date: Tue, 16 Jul 2019 16:44:40 +0100 Subject: mul2dsp: Fix edge case where Y_WIDTH is less than B_WIDTH+`DSP_A_MAXWIDTH Signed-off-by: David Shah --- techlibs/common/mul2dsp.v | 40 ++++++++++++++++++++++------------------ 1 file changed, 22 insertions(+), 18 deletions(-) (limited to 'techlibs') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 69de74cad..262e29986 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -80,19 +80,21 @@ module \$__mul_gen (A, B, Y); localparam n = n_floored + (n_floored*`DSP_A_MAXWIDTH < A_WIDTH ? 1 : 0); wire [`DSP_A_MAXWIDTH+B_WIDTH-1:0] partial [n-1:1]; wire [Y_WIDTH-1:0] partial_sum [n-2:0]; + localparam int_yw = `MIN(Y_WIDTH, B_WIDTH+`DSP_A_MAXWIDTH); \$__mul_gen #( .A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(`DSP_A_MAXWIDTH), .B_WIDTH(B_WIDTH), - .Y_WIDTH(B_WIDTH+`DSP_A_MAXWIDTH) + .Y_WIDTH(int_yw) ) mul_slice_first ( .A(A[`DSP_A_MAXWIDTH-1:0]), .B(B), - .Y(partial_sum[0][B_WIDTH+`DSP_A_MAXWIDTH-1:0]) + .Y(partial_sum[0][int_yw-1:0]) ); - assign partial_sum[0][Y_WIDTH-1:B_WIDTH+`DSP_A_MAXWIDTH]=0; + if (Y_WIDTH > int_yw) + assign partial_sum[0][Y_WIDTH-1:int_yw]=0; for (i = 1; i < n-1; i=i+1) begin:slice \$__mul_gen #( @@ -100,15 +102,15 @@ module \$__mul_gen (A, B, Y); .B_SIGNED(B_SIGNED), .A_WIDTH(`DSP_A_MAXWIDTH), .B_WIDTH(B_WIDTH), - .Y_WIDTH(B_WIDTH+`DSP_A_MAXWIDTH) + .Y_WIDTH(int_yw) ) mul_slice ( .A(A[(i+1)*`DSP_A_MAXWIDTH-1:i*`DSP_A_MAXWIDTH]), .B(B), - .Y(partial[i][B_WIDTH+`DSP_A_MAXWIDTH-1:0]) + .Y(partial[i][int_yw-1:0]) ); //assign partial_sum[i] = (partial[i] << i*`DSP_A_MAXWIDTH) + partial_sum[i-1]; assign partial_sum[i] = { - partial[i][B_WIDTH+`DSP_A_MAXWIDTH-1:0] + partial[i][int_yw-1:0] + partial_sum[i-1][Y_WIDTH-1:(i*`DSP_A_MAXWIDTH)], partial_sum[i-1][(i*`DSP_A_MAXWIDTH)-1:0] }; @@ -119,15 +121,15 @@ module \$__mul_gen (A, B, Y); .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH-(n-1)*`DSP_A_MAXWIDTH), .B_WIDTH(B_WIDTH), - .Y_WIDTH(A_WIDTH-(n-1)*`DSP_A_MAXWIDTH+B_WIDTH), + .Y_WIDTH(`MIN(Y_WIDTH, A_WIDTH-(n-1)*`DSP_A_MAXWIDTH+B_WIDTH)), ) mul_slice_last ( .A(A[A_WIDTH-1:(n-1)*`DSP_A_MAXWIDTH]), .B(B), - .Y(partial[n-1][A_WIDTH-(n-1)*`DSP_A_MAXWIDTH+B_WIDTH-1:0]) + .Y(partial[n-1][`MIN(Y_WIDTH, A_WIDTH-(n-1)*`DSP_A_MAXWIDTH+B_WIDTH)-1:0]) ); //assign Y = (partial[n-1] << (n-1)*`DSP_A_MAXWIDTH) + partial_sum[n-2]; assign Y = { - partial[n-1][A_WIDTH-(n-1)*`DSP_A_MAXWIDTH+B_WIDTH:0] + partial[n-1][`MIN(Y_WIDTH, A_WIDTH-(n-1)*`DSP_A_MAXWIDTH+B_WIDTH):0] + partial_sum[n-2][Y_WIDTH-1:((n-1)*`DSP_A_MAXWIDTH)], partial_sum[n-2][((n-1)*`DSP_A_MAXWIDTH)-1:0] }; @@ -137,19 +139,21 @@ module \$__mul_gen (A, B, Y); localparam n = n_floored + (n_floored*`DSP_B_MAXWIDTH < B_WIDTH ? 1 : 0); wire [A_WIDTH+`DSP_B_MAXWIDTH-1:0] partial [n-1:1]; wire [Y_WIDTH-1:0] partial_sum [n-2:0]; + localparam int_yw = `MIN(Y_WIDTH, A_WIDTH+`DSP_B_MAXWIDTH); \$__mul_gen #( .A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(`DSP_B_MAXWIDTH), - .Y_WIDTH(A_WIDTH+`DSP_B_MAXWIDTH) + .Y_WIDTH(int_yw) ) mul_first ( .A(A), .B(B[`DSP_B_MAXWIDTH-1:0]), - .Y(partial_sum[0][A_WIDTH+`DSP_B_MAXWIDTH-1:0]) + .Y(partial_sum[0][int_yw-1:0]) ); - assign partial_sum[0][Y_WIDTH-1:A_WIDTH+`DSP_B_MAXWIDTH]=0; + if (Y_WIDTH > int_yw) + assign partial_sum[0][Y_WIDTH-1:A_WIDTH+`DSP_B_MAXWIDTH]=0; for (i = 1; i < n-1; i=i+1) begin:slice \$__mul_gen #( @@ -157,11 +161,11 @@ module \$__mul_gen (A, B, Y); .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(`DSP_B_MAXWIDTH), - .Y_WIDTH(A_WIDTH+`DSP_B_MAXWIDTH) + .Y_WIDTH(int_yw) ) mul ( .A(A), .B(B[(i+1)*`DSP_B_MAXWIDTH-1:i*`DSP_B_MAXWIDTH]), - .Y(partial[i][A_WIDTH+`DSP_B_MAXWIDTH-1:0]) + .Y(partial[i][int_yw-1:0]) ); //assign partial_sum[i] = (partial[i] << i*`DSP_B_MAXWIDTH) + partial_sum[i-1]; // was: @@ -170,7 +174,7 @@ module \$__mul_gen (A, B, Y); // partial[i][`DSP_B_MAXWIDTH-1:0] + partial_sum[i-1][A_WIDTH+(i*`DSP_B_MAXWIDTH)-1:A_WIDTH+((i-1)*`DSP_B_MAXWIDTH)], // partial_sum[i-1][A_WIDTH+((i-1)*`DSP_B_MAXWIDTH):0] assign partial_sum[i] = { - partial[i][A_WIDTH+`DSP_B_MAXWIDTH-1:0] + partial[i][int_yw-1:0] + partial_sum[i-1][Y_WIDTH-1:(i*`DSP_B_MAXWIDTH)], partial_sum[i-1][(i*`DSP_B_MAXWIDTH)-1:0] }; @@ -181,11 +185,11 @@ module \$__mul_gen (A, B, Y); .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH-(n-1)*`DSP_B_MAXWIDTH), - .Y_WIDTH(A_WIDTH+B_WIDTH-(n-1)*`DSP_B_MAXWIDTH) + .Y_WIDTH(`MIN(Y_WIDTH, A_WIDTH+B_WIDTH-(n-1)*`DSP_B_MAXWIDTH)) ) mul_last ( .A(A), .B(B[B_WIDTH-1:(n-1)*`DSP_B_MAXWIDTH]), - .Y(partial[n-1][A_WIDTH+B_WIDTH-(n-1)*`DSP_B_MAXWIDTH-1:0]) + .Y(partial[n-1][`MIN(Y_WIDTH, A_WIDTH+B_WIDTH-(n-1)*`DSP_B_MAXWIDTH)-1:0]) ); // AMD: this came comment out -- looks closer to right answer //assign Y = (partial[n-1] << (n-1)*`DSP_B_MAXWIDTH) + partial_sum[n-2]; @@ -195,7 +199,7 @@ module \$__mul_gen (A, B, Y); // partial[n-1][`DSP_B_MAXWIDTH-1:0] + partial_sum[n-2][A_WIDTH+((n-1)*`DSP_B_MAXWIDTH)-1:A_WIDTH+((n-2)*`DSP_B_MAXWIDTH)], // partial_sum[n-2][A_WIDTH+((n-2)*`DSP_B_MAXWIDTH):0] assign Y = { - partial[n-1][A_WIDTH+B_WIDTH-(n-1)*`DSP_B_MAXWIDTH-1:0] + partial[n-1][`MIN(Y_WIDTH, A_WIDTH+B_WIDTH-(n-1)*`DSP_B_MAXWIDTH)-1:0] + partial_sum[n-2][Y_WIDTH-1:((n-1)*`DSP_B_MAXWIDTH)], partial_sum[n-2][((n-1)*`DSP_B_MAXWIDTH)-1:0] }; -- cgit v1.2.3 From 95c8d27b0bfdea330a62a18825dea3691b4affe2 Mon Sep 17 00:00:00 2001 From: David Shah Date: Tue, 16 Jul 2019 16:46:41 +0100 Subject: xilinx: Treat DSP48E1 as 24x17 unsigned for now (actual behaviour is 25x18 signed) Signed-off-by: David Shah --- techlibs/xilinx/cells_map.v | 6 +++--- techlibs/xilinx/synth_xilinx.cc | 6 +++++- 2 files changed, 8 insertions(+), 4 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index 6ebca0d54..8302e0b3a 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -366,7 +366,7 @@ module \$__XILINX_MUXF78 (O, I0, I1, I2, I3, S0, S1); endmodule `endif -module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] OUT); +module \$__MUL25X18 (input [23:0] A, input [16:0] B, output [40:0] OUT); wire [47:0] P_48; DSP48E1 #( // Disable all registers @@ -388,8 +388,8 @@ module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] OUT); .PREG(0) ) _TECHMAP_REPLACE_ ( //Data path - .A({5'b0, A}), - .B(B), + .A({6'b0, A}), + .B({1'b0, B}), .C(48'b0), .D(24'b0), .P(P_48), diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 01e75b50e..5bfbd1583 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -284,8 +284,12 @@ struct SynthXilinxPass : public ScriptPass run("techmap -map +/cmp2lut.v -D LUT_WIDTH=6"); + // The actual behaviour of the Xilinx DSP is a signed 25x18 multiply + // Due to current limitations of mul2dsp, we are actually mapping as a 24x17 + // unsigned multiply with MSBs set to 1'b0 + if (!nodsp || help_mode) - run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=25 -D DSP_B_MAXWIDTH=18 -D DSP_NAME=$__MUL25X18"); + run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=24 -D DSP_B_MAXWIDTH=17 -D DSP_NAME=$__MUL25X18"); run("alumacc"); run("share"); -- cgit v1.2.3 From d38df68d26f1644539e5116e6b6c360e1c389cc9 Mon Sep 17 00:00:00 2001 From: David Shah Date: Tue, 16 Jul 2019 17:53:08 +0100 Subject: xilinx: Add correct signed behaviour to DSP48E1 model Signed-off-by: David Shah --- techlibs/xilinx/cells_sim.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 99120452c..ea5a3b788 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -506,6 +506,6 @@ module DSP48E1 ( if (PCIN != 48'b0) $fatal(1, "Unsupported PCIN value"); if (CARRYIN != 1'b0) $fatal(1, "Unsupported CARRYIN value"); `endif - P[42:0] <= A[24:0] * B; + P[42:0] <= $signed(A[24:0]) * $signed(B); end endmodule -- cgit v1.2.3 From 5d1ce043812b9b86ee3c3588c430ea1cd57fee1e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 16 Jul 2019 14:05:50 -0700 Subject: Add support for {A,B,P}REG in DSP48E1 --- techlibs/xilinx/cells_sim.v | 26 +++++++++++++++++++++----- 1 file changed, 21 insertions(+), 5 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 99120452c..5410983ae 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -466,11 +466,11 @@ module DSP48E1 ( if (ACASCREG != 0) $fatal(1, "Unsupported ACASCREG value"); if (ADREG != 0) $fatal(1, "Unsupported ADREG value"); if (ALUMODEREG != 0) $fatal(1, "Unsupported ALUMODEREG value"); - if (AREG != 0) $fatal(1, "Unsupported AREG value"); + if (AREG == 2) $fatal(1, "Unsupported AREG value"); if (AUTORESET_PATDET != "NO_RESET") $fatal(1, "Unsupported AUTORESET_PATDET value"); if (A_INPUT != "DIRECT") $fatal(1, "Unsupported A_INPUT value"); if (BCASCREG != 0) $fatal(1, "Unsupported BCASCREG value"); - if (BREG != 0) $fatal(1, "Unsupported BREG value"); + if (BREG == 2) $fatal(1, "Unsupported BREG value"); if (B_INPUT != "DIRECT") $fatal(1, "Unsupported B_INPUT value"); if (CARRYINREG != 0) $fatal(1, "Unsupported CARRYINREG value"); if (CARRYINSELREG != 0) $fatal(1, "Unsupported CARRYINSELREG value"); @@ -479,7 +479,7 @@ module DSP48E1 ( if (INMODEREG != 0) $fatal(1, "Unsupported INMODEREG value"); if (MREG != 0) $fatal(1, "Unsupported MREG value"); if (OPMODEREG != 0) $fatal(1, "Unsupported OPMODEREG value"); - if (PREG != 0) $fatal(1, "Unsupported PREG value"); + //if (PREG != 0) $fatal(1, "Unsupported PREG value"); if (SEL_MASK != "MASK") $fatal(1, "Unsupported SEL_MASK value"); if (SEL_PATTERN != "PATTERN") $fatal(1, "Unsupported SEL_PATTERN value"); if (USE_DPORT != "FALSE") $fatal(1, "Unsupported USE_DPORT value"); @@ -494,8 +494,18 @@ module DSP48E1 ( `endif end + reg [29:0] Ar; + reg [17:0] Br; + reg [47:0] Pr; + generate + if (AREG == 1) begin always @(posedge CLK) if (CEA2) Ar <= A; end + else always @* Ar <= A; + if (BREG == 1) begin always @(posedge CLK) if (CEB2) Br <= B; end + else always @* Br <= B; + endgenerate + always @* begin - P <= {48{1'bx}}; + Pr <= {48{1'bx}}; `ifdef __ICARUS__ if (INMODE != 4'b0000) $fatal(1, "Unsupported INMODE value"); if (ALUMODE != 4'b0000) $fatal(1, "Unsupported ALUMODE value"); @@ -506,6 +516,12 @@ module DSP48E1 ( if (PCIN != 48'b0) $fatal(1, "Unsupported PCIN value"); if (CARRYIN != 1'b0) $fatal(1, "Unsupported CARRYIN value"); `endif - P[42:0] <= A[24:0] * B; + Pr[42:0] <= Ar[24:0] * Br; end + + generate + if (PREG == 1) begin always @(posedge CLK) if (CEP) P <= Pr; end + else always @* P <= Pr; + endgenerate + endmodule -- cgit v1.2.3 From 6390c535ba70c0a4fe0cb08156fefa80fb621e47 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 16 Jul 2019 14:30:25 -0700 Subject: Revert drop down to 24x16 multipliers for all --- techlibs/xilinx/dsp_map.v | 6 +++--- techlibs/xilinx/synth_xilinx.cc | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/dsp_map.v b/techlibs/xilinx/dsp_map.v index 2063c45e2..da1d6f3a9 100644 --- a/techlibs/xilinx/dsp_map.v +++ b/techlibs/xilinx/dsp_map.v @@ -1,4 +1,4 @@ -module \$__MUL25X18 (input [23:0] A, input [16:0] B, output [40:0] Y); +module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y); wire [47:0] P_48; DSP48E1 #( // Disable all registers @@ -20,8 +20,8 @@ module \$__MUL25X18 (input [23:0] A, input [16:0] B, output [40:0] Y); .PREG(0) ) _TECHMAP_REPLACE_ ( //Data path - .A({6'b0, A}), - .B({1'b0, B}), + .A({5'b0, A}), + .B(B), .C(48'b0), .D(24'b0), .P(P_48), diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 815bf0848..bfce922db 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -289,7 +289,7 @@ struct SynthXilinxPass : public ScriptPass // unsigned multiply with MSBs set to 1'b0 if (!nodsp || help_mode) - run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=24 -D DSP_B_MAXWIDTH=17 -D DSP_NAME=$__MUL25X18"); + run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=25 -D DSP_A_SIGNEDONLY=1 -D DSP_B_MAXWIDTH=18 -D DSP_B_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18"); run("alumacc"); run("share"); -- cgit v1.2.3 From c501aa5ee84c14f5b6aebe3052dabb1c314eb9e0 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 16 Jul 2019 15:54:27 -0700 Subject: Signedness --- techlibs/xilinx/cells_sim.v | 14 +++++++------- techlibs/xilinx/dsp_map.v | 2 +- 2 files changed, 8 insertions(+), 8 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 1262fc8c1..33b2a8f62 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -386,15 +386,15 @@ module DSP48E1 ( output [3:0] CARRYOUT, output MULTSIGNOUT, output OVERFLOW, - output reg [47:0] P, + output reg signed [47:0] P, output PATTERNBDETECT, output PATTERNDETECT, output [47:0] PCOUT, output UNDERFLOW, - input [29:0] A, + input signed [29:0] A, input [29:0] ACIN, input [3:0] ALUMODE, - input [17:0] B, + input signed [17:0] B, input [17:0] BCIN, input [47:0] C, input CARRYCASCIN, @@ -494,9 +494,9 @@ module DSP48E1 ( `endif end - reg [29:0] Ar; - reg [17:0] Br; - reg [47:0] Pr; + reg signed [29:0] Ar; + reg signed [17:0] Br; + reg signed [47:0] Pr; generate if (AREG == 1) begin always @(posedge CLK) if (CEA2) Ar <= A; end else always @* Ar <= A; @@ -516,7 +516,7 @@ module DSP48E1 ( if (PCIN != 48'b0) $fatal(1, "Unsupported PCIN value"); if (CARRYIN != 1'b0) $fatal(1, "Unsupported CARRYIN value"); `endif - Pr[42:0] <= $signed(Ar[24:0]) * $signed(Br); + Pr[42:0] <= $signed(Ar[24:0]) * Br; end generate diff --git a/techlibs/xilinx/dsp_map.v b/techlibs/xilinx/dsp_map.v index da1d6f3a9..28e456898 100644 --- a/techlibs/xilinx/dsp_map.v +++ b/techlibs/xilinx/dsp_map.v @@ -20,7 +20,7 @@ module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y); .PREG(0) ) _TECHMAP_REPLACE_ ( //Data path - .A({5'b0, A}), + .A({{5{A[24]}}, A}), .B(B), .C(48'b0), .D(24'b0), -- cgit v1.2.3 From 0b6d47f8bfe3117817398a7a84a2d93dd339335b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 16 Jul 2019 15:55:13 -0700 Subject: Add DSP_{A,B}_SIGNEDONLY macro --- techlibs/common/mul2dsp.v | 51 +++++++++++++++++++++++++++++++++++++---------- 1 file changed, 40 insertions(+), 11 deletions(-) (limited to 'techlibs') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 6f2281c0a..258ddf021 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -3,24 +3,25 @@ // revised by Andre DeHon // further revised by David Shah `ifndef DSP_A_MAXWIDTH -`define DSP_A_MAXWIDTH 18 +$error("Macro DSP_A_MAXWIDTH must be defined"); `endif -`ifndef DSP_A_MAXWIDTH -`define DSP_B_MAXWIDTH 25 +`ifndef DSP_A_SIGNEDONLY +`define DSP_A_SIGNEDONLY 0 `endif - -`ifndef ADDER_MINWIDTH -`define ADDER_MINWIDTH AAA +`ifndef DSP_B_MAXWIDTH +$error("Macro DSP_B_MAXWIDTH must be defined"); +`endif +`ifndef DSP_B_SIGNEDONLY +`define DSP_B_SIGNEDONLY 0 `endif `ifndef DSP_NAME -`define DSP_NAME M18x25 +$error("Macro DSP_NAME must be defined"); `endif `define MAX(a,b) (a > b ? a : b) `define MIN(a,b) (a < b ? a : b) -(* techmap_celltype = "$mul" *) module \$mul (A, B, Y); parameter A_SIGNED = 0; parameter B_SIGNED = 0; @@ -33,14 +34,42 @@ module \$mul (A, B, Y); output [Y_WIDTH-1:0] Y; generate - if (A_WIDTH >= B_WIDTH) + if (`DSP_A_SIGNEDONLY && !A_SIGNED) begin + wire dummy; + \$mul #( + .A_SIGNED(1), + .B_SIGNED(B_SIGNED), + .A_WIDTH(A_WIDTH+1), + .B_WIDTH(B_WIDTH), + .Y_WIDTH(Y_WIDTH+1) + ) _TECHMAP_REPLACE_ ( + .A({1'b0, A}), + .B(B), + .Y({dummy, Y}) + ); + end + else if (`DSP_B_SIGNEDONLY && !B_SIGNED) begin + wire dummy; + \$mul #( + .A_SIGNED(A_SIGNED), + .B_SIGNED(1), + .A_WIDTH(A_WIDTH), + .B_WIDTH(B_WIDTH+1), + .Y_WIDTH(Y_WIDTH+1) + ) _TECHMAP_REPLACE_ ( + .A(A), + .B({1'b0, B}), + .Y({dummy, Y}) + ); + end + else if (A_WIDTH >= B_WIDTH) \$__mul_gen #( .A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH) - ) mul_slice ( + ) _TECHMAP_REPLACE_ ( .A(A), .B(B), .Y(Y) @@ -52,7 +81,7 @@ module \$mul (A, B, Y); .A_WIDTH(B_WIDTH), .B_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH) - ) mul_slice ( + ) _TECHMAP_REPLACE_ ( .A(B), .B(A), .Y(Y) -- cgit v1.2.3 From 1b62b82e05ef5405d8ddff211f623d90d848a9ca Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 17 Jul 2019 11:34:18 -0700 Subject: A_SIGNED == B_SIGNED so flip both --- techlibs/common/mul2dsp.v | 33 ++++++++++++--------------------- 1 file changed, 12 insertions(+), 21 deletions(-) (limited to 'techlibs') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 258ddf021..d19599620 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -34,31 +34,22 @@ module \$mul (A, B, Y); output [Y_WIDTH-1:0] Y; generate - if (`DSP_A_SIGNEDONLY && !A_SIGNED) begin - wire dummy; + localparam add_sign_A = `DSP_A_SIGNEDONLY && !A_SIGNED; + localparam add_sign_B = `DSP_B_SIGNEDONLY && !B_SIGNED; + if (add_sign_A || add_sign_B) begin + if (add_sign_A && add_sign_B) + wire [1:0] dummy; + else + wire dummy; \$mul #( .A_SIGNED(1), - .B_SIGNED(B_SIGNED), - .A_WIDTH(A_WIDTH+1), - .B_WIDTH(B_WIDTH), - .Y_WIDTH(Y_WIDTH+1) - ) _TECHMAP_REPLACE_ ( - .A({1'b0, A}), - .B(B), - .Y({dummy, Y}) - ); - end - else if (`DSP_B_SIGNEDONLY && !B_SIGNED) begin - wire dummy; - \$mul #( - .A_SIGNED(A_SIGNED), .B_SIGNED(1), - .A_WIDTH(A_WIDTH), - .B_WIDTH(B_WIDTH+1), - .Y_WIDTH(Y_WIDTH+1) + .A_WIDTH(A_WIDTH + (add_sign_A ? 1 : 0)), + .B_WIDTH(B_WIDTH + (add_sign_B ? 1 : 0)), + .Y_WIDTH(Y_WIDTH + (add_sign_A ? 1 : 0) + (add_sign_B ? 1 : 0)) ) _TECHMAP_REPLACE_ ( - .A(A), - .B({1'b0, B}), + .A(add_sign_A ? {1'b0, A} : A), + .B(add_sign_B ? {1'b0, B} : B), .Y({dummy, Y}) ); end -- cgit v1.2.3 From 8dca8d486e945eb5883e6757f711011ed23aa5ba Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 17 Jul 2019 12:44:52 -0700 Subject: Fix mul2dsp signedness --- techlibs/common/mul2dsp.v | 80 ++++++++++++++++++++++------------------------- 1 file changed, 38 insertions(+), 42 deletions(-) (limited to 'techlibs') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index d19599620..7344bc5fe 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -34,49 +34,45 @@ module \$mul (A, B, Y); output [Y_WIDTH-1:0] Y; generate - localparam add_sign_A = `DSP_A_SIGNEDONLY && !A_SIGNED; - localparam add_sign_B = `DSP_B_SIGNEDONLY && !B_SIGNED; - if (add_sign_A || add_sign_B) begin - if (add_sign_A && add_sign_B) - wire [1:0] dummy; - else - wire dummy; - \$mul #( - .A_SIGNED(1), - .B_SIGNED(1), - .A_WIDTH(A_WIDTH + (add_sign_A ? 1 : 0)), - .B_WIDTH(B_WIDTH + (add_sign_B ? 1 : 0)), - .Y_WIDTH(Y_WIDTH + (add_sign_A ? 1 : 0) + (add_sign_B ? 1 : 0)) - ) _TECHMAP_REPLACE_ ( - .A(add_sign_A ? {1'b0, A} : A), - .B(add_sign_B ? {1'b0, B} : B), - .Y({dummy, Y}) - ); + if (`DSP_A_SIGNEDONLY && `DSP_B_SIGNEDONLY && !A_SIGNED) begin + wire [1:0] dummy; + \$mul #( + .A_SIGNED(1), + .B_SIGNED(1), + .A_WIDTH(A_WIDTH + 1), + .B_WIDTH(B_WIDTH + 1), + .Y_WIDTH(Y_WIDTH + 2) + ) _TECHMAP_REPLACE_ ( + .A({1'b0, A}), + .B({1'b0, B}), + .Y({dummy, Y}) + ); end - else if (A_WIDTH >= B_WIDTH) - \$__mul_gen #( - .A_SIGNED(A_SIGNED), - .B_SIGNED(B_SIGNED), - .A_WIDTH(A_WIDTH), - .B_WIDTH(B_WIDTH), - .Y_WIDTH(Y_WIDTH) - ) _TECHMAP_REPLACE_ ( - .A(A), - .B(B), - .Y(Y) - ); - else - \$__mul_gen #( - .A_SIGNED(B_SIGNED), - .B_SIGNED(A_SIGNED), - .A_WIDTH(B_WIDTH), - .B_WIDTH(A_WIDTH), - .Y_WIDTH(Y_WIDTH) - ) _TECHMAP_REPLACE_ ( - .A(B), - .B(A), - .Y(Y) - ); + // NB: A_SIGNED == B_SIGNED == 0 from here + else if (A_WIDTH >= B_WIDTH) + \$__mul_gen #( + .A_SIGNED(A_SIGNED), + .B_SIGNED(B_SIGNED), + .A_WIDTH(A_WIDTH), + .B_WIDTH(B_WIDTH), + .Y_WIDTH(Y_WIDTH) + ) _TECHMAP_REPLACE_ ( + .A(A), + .B(B), + .Y(Y) + ); + else + \$__mul_gen #( + .A_SIGNED(B_SIGNED), + .B_SIGNED(A_SIGNED), + .A_WIDTH(B_WIDTH), + .B_WIDTH(A_WIDTH), + .Y_WIDTH(Y_WIDTH) + ) _TECHMAP_REPLACE_ ( + .A(B), + .B(A), + .Y(Y) + ); endgenerate endmodule -- cgit v1.2.3 From 58e63feae1e950fff839c4261a787d5daf07612e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 17 Jul 2019 13:26:17 -0700 Subject: Update comment --- techlibs/xilinx/synth_xilinx.cc | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index bfce922db..2e2fbbd9d 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -284,12 +284,10 @@ struct SynthXilinxPass : public ScriptPass run("techmap -map +/cmp2lut.v -D LUT_WIDTH=6"); - // The actual behaviour of the Xilinx DSP is a signed 25x18 multiply - // Due to current limitations of mul2dsp, we are actually mapping as a 24x17 - // unsigned multiply with MSBs set to 1'b0 - - if (!nodsp || help_mode) + if (!nodsp || help_mode) { + // NB: Xilinx multipliers are signed only run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=25 -D DSP_A_SIGNEDONLY=1 -D DSP_B_MAXWIDTH=18 -D DSP_B_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18"); + } run("alumacc"); run("share"); -- cgit v1.2.3 From e3f8e59f182129aa2ff9ba7a1ed7fbbaab657ce5 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 17 Jul 2019 14:25:40 -0700 Subject: Make all operands signed --- techlibs/xilinx/dsp_map.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/dsp_map.v b/techlibs/xilinx/dsp_map.v index 28e456898..32f570935 100644 --- a/techlibs/xilinx/dsp_map.v +++ b/techlibs/xilinx/dsp_map.v @@ -1,4 +1,4 @@ -module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y); +module \$__MUL25X18 (input signed [24:0] A, input signed [17:0] B, output signed [42:0] Y); wire [47:0] P_48; DSP48E1 #( // Disable all registers -- cgit v1.2.3 From 16b0ccf04ca83d76f9bd182e125dd75fa838753a Mon Sep 17 00:00:00 2001 From: David Shah Date: Thu, 18 Jul 2019 11:33:37 +0100 Subject: mul2dsp: Lower partial products always have unsigned inputs Signed-off-by: David Shah --- techlibs/common/mul2dsp.v | 72 +++++++++++++++++++++++++++-------------------- 1 file changed, 41 insertions(+), 31 deletions(-) (limited to 'techlibs') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 7344bc5fe..31469ddeb 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -92,20 +92,25 @@ module \$__mul_gen (A, B, Y); genvar i; generate if (A_WIDTH > `DSP_A_MAXWIDTH) begin - localparam n_floored = A_WIDTH/`DSP_A_MAXWIDTH; - localparam n = n_floored + (n_floored*`DSP_A_MAXWIDTH < A_WIDTH ? 1 : 0); +`ifdef DSP_A_SIGNEDONLY + localparam sign_headroom = 1; +`else + localparam sign_headroom = 0; +`endif + localparam n_floored = A_WIDTH/(`DSP_A_MAXWIDTH - sign_headroom); + localparam n = n_floored + (n_floored*(`DSP_A_MAXWIDTH - sign_headroom) < A_WIDTH ? 1 : 0); wire [`DSP_A_MAXWIDTH+B_WIDTH-1:0] partial [n-1:1]; wire [Y_WIDTH-1:0] partial_sum [n-2:0]; localparam int_yw = `MIN(Y_WIDTH, B_WIDTH+`DSP_A_MAXWIDTH); \$__mul_gen #( - .A_SIGNED(A_SIGNED), + .A_SIGNED(0), .B_SIGNED(B_SIGNED), .A_WIDTH(`DSP_A_MAXWIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(int_yw) ) mul_slice_first ( - .A(A[`DSP_A_MAXWIDTH-1:0]), + .A({{sign_headroom{1'b0}}, A[`DSP_A_MAXWIDTH-sign_headroom-1:0]}), .B(B), .Y(partial_sum[0][int_yw-1:0]) ); @@ -114,73 +119,78 @@ module \$__mul_gen (A, B, Y); for (i = 1; i < n-1; i=i+1) begin:slice \$__mul_gen #( - .A_SIGNED(A_SIGNED), + .A_SIGNED(0), .B_SIGNED(B_SIGNED), .A_WIDTH(`DSP_A_MAXWIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(int_yw) ) mul_slice ( - .A(A[(i+1)*`DSP_A_MAXWIDTH-1:i*`DSP_A_MAXWIDTH]), + .A({{sign_headroom{1'b0}}, A[(i+1)*(`DSP_A_MAXWIDTH-sign_headroom)-1:i*(`DSP_A_MAXWIDTH-sign_headroom)]}), .B(B), .Y(partial[i][int_yw-1:0]) ); //assign partial_sum[i] = (partial[i] << i*`DSP_A_MAXWIDTH) + partial_sum[i-1]; assign partial_sum[i] = { partial[i][int_yw-1:0] - + partial_sum[i-1][Y_WIDTH-1:(i*`DSP_A_MAXWIDTH)], - partial_sum[i-1][(i*`DSP_A_MAXWIDTH)-1:0] + + partial_sum[i-1][Y_WIDTH-1:(i*(`DSP_A_MAXWIDTH-sign_headroom))], + partial_sum[i-1][(i*(`DSP_A_MAXWIDTH-sign_headroom))-1:0] }; end \$__mul_gen #( .A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), - .A_WIDTH(A_WIDTH-(n-1)*`DSP_A_MAXWIDTH), + .A_WIDTH(A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom)), .B_WIDTH(B_WIDTH), - .Y_WIDTH(`MIN(Y_WIDTH, A_WIDTH-(n-1)*`DSP_A_MAXWIDTH+B_WIDTH)), + .Y_WIDTH(`MIN(Y_WIDTH, A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom)+B_WIDTH)), ) mul_slice_last ( - .A(A[A_WIDTH-1:(n-1)*`DSP_A_MAXWIDTH]), + .A(A[A_WIDTH-1:(n-1)*(`DSP_A_MAXWIDTH-sign_headroom)]), .B(B), - .Y(partial[n-1][`MIN(Y_WIDTH, A_WIDTH-(n-1)*`DSP_A_MAXWIDTH+B_WIDTH)-1:0]) + .Y(partial[n-1][`MIN(Y_WIDTH, A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom)+B_WIDTH)-1:0]) ); //assign Y = (partial[n-1] << (n-1)*`DSP_A_MAXWIDTH) + partial_sum[n-2]; assign Y = { - partial[n-1][`MIN(Y_WIDTH, A_WIDTH-(n-1)*`DSP_A_MAXWIDTH+B_WIDTH):0] - + partial_sum[n-2][Y_WIDTH-1:((n-1)*`DSP_A_MAXWIDTH)], - partial_sum[n-2][((n-1)*`DSP_A_MAXWIDTH)-1:0] + partial[n-1][`MIN(Y_WIDTH, A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom)+B_WIDTH):0] + + partial_sum[n-2][Y_WIDTH-1:((n-1)*(`DSP_A_MAXWIDTH-sign_headroom))], + partial_sum[n-2][((n-1)*(`DSP_A_MAXWIDTH-sign_headroom))-1:0] }; end else if (B_WIDTH > `DSP_B_MAXWIDTH) begin - localparam n_floored = B_WIDTH/`DSP_B_MAXWIDTH; - localparam n = n_floored + (n_floored*`DSP_B_MAXWIDTH < B_WIDTH ? 1 : 0); +`ifdef DSP_B_SIGNEDONLY + localparam sign_headroom = 1; +`else + localparam sign_headroom = 0; +`endif + localparam n_floored = B_WIDTH/(`DSP_B_MAXWIDTH - sign_headroom); + localparam n = n_floored + (n_floored*(`DSP_B_MAXWIDTH - sign_headroom) < B_WIDTH ? 1 : 0); wire [A_WIDTH+`DSP_B_MAXWIDTH-1:0] partial [n-1:1]; wire [Y_WIDTH-1:0] partial_sum [n-2:0]; localparam int_yw = `MIN(Y_WIDTH, A_WIDTH+`DSP_B_MAXWIDTH); \$__mul_gen #( .A_SIGNED(A_SIGNED), - .B_SIGNED(B_SIGNED), + .B_SIGNED(0), .A_WIDTH(A_WIDTH), .B_WIDTH(`DSP_B_MAXWIDTH), .Y_WIDTH(int_yw) ) mul_first ( .A(A), - .B(B[`DSP_B_MAXWIDTH-1:0]), + .B({{sign_headroom{1'b0}}, B[(`DSP_B_MAXWIDTH - sign_headroom)-1:0]}), .Y(partial_sum[0][int_yw-1:0]) ); if (Y_WIDTH > int_yw) - assign partial_sum[0][Y_WIDTH-1:A_WIDTH+`DSP_B_MAXWIDTH]=0; + assign partial_sum[0][Y_WIDTH-1:int_yw]=0; for (i = 1; i < n-1; i=i+1) begin:slice \$__mul_gen #( .A_SIGNED(A_SIGNED), - .B_SIGNED(B_SIGNED), + .B_SIGNED(0), .A_WIDTH(A_WIDTH), .B_WIDTH(`DSP_B_MAXWIDTH), .Y_WIDTH(int_yw) ) mul ( .A(A), - .B(B[(i+1)*`DSP_B_MAXWIDTH-1:i*`DSP_B_MAXWIDTH]), + .B({{sign_headroom{1'b0}}, B[(i+1)*(`DSP_B_MAXWIDTH - sign_headroom)-1:i*(`DSP_B_MAXWIDTH - sign_headroom)]}), .Y(partial[i][int_yw-1:0]) ); //assign partial_sum[i] = (partial[i] << i*`DSP_B_MAXWIDTH) + partial_sum[i-1]; @@ -191,8 +201,8 @@ module \$__mul_gen (A, B, Y); // partial_sum[i-1][A_WIDTH+((i-1)*`DSP_B_MAXWIDTH):0] assign partial_sum[i] = { partial[i][int_yw-1:0] - + partial_sum[i-1][Y_WIDTH-1:(i*`DSP_B_MAXWIDTH)], - partial_sum[i-1][(i*`DSP_B_MAXWIDTH)-1:0] + + partial_sum[i-1][Y_WIDTH-1:(i*(`DSP_B_MAXWIDTH - sign_headroom))], + partial_sum[i-1][(i*(`DSP_B_MAXWIDTH - sign_headroom))-1:0] }; end @@ -200,12 +210,12 @@ module \$__mul_gen (A, B, Y); .A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), - .B_WIDTH(B_WIDTH-(n-1)*`DSP_B_MAXWIDTH), - .Y_WIDTH(`MIN(Y_WIDTH, A_WIDTH+B_WIDTH-(n-1)*`DSP_B_MAXWIDTH)) + .B_WIDTH(B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH - sign_headroom)), + .Y_WIDTH(`MIN(Y_WIDTH, A_WIDTH+B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH - sign_headroom))) ) mul_last ( .A(A), - .B(B[B_WIDTH-1:(n-1)*`DSP_B_MAXWIDTH]), - .Y(partial[n-1][`MIN(Y_WIDTH, A_WIDTH+B_WIDTH-(n-1)*`DSP_B_MAXWIDTH)-1:0]) + .B(B[B_WIDTH-1:(n-1)*(`DSP_B_MAXWIDTH - sign_headroom)]), + .Y(partial[n-1][`MIN(Y_WIDTH, A_WIDTH+B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH - sign_headroom))-1:0]) ); // AMD: this came comment out -- looks closer to right answer //assign Y = (partial[n-1] << (n-1)*`DSP_B_MAXWIDTH) + partial_sum[n-2]; @@ -215,9 +225,9 @@ module \$__mul_gen (A, B, Y); // partial[n-1][`DSP_B_MAXWIDTH-1:0] + partial_sum[n-2][A_WIDTH+((n-1)*`DSP_B_MAXWIDTH)-1:A_WIDTH+((n-2)*`DSP_B_MAXWIDTH)], // partial_sum[n-2][A_WIDTH+((n-2)*`DSP_B_MAXWIDTH):0] assign Y = { - partial[n-1][`MIN(Y_WIDTH, A_WIDTH+B_WIDTH-(n-1)*`DSP_B_MAXWIDTH)-1:0] - + partial_sum[n-2][Y_WIDTH-1:((n-1)*`DSP_B_MAXWIDTH)], - partial_sum[n-2][((n-1)*`DSP_B_MAXWIDTH)-1:0] + partial[n-1][`MIN(Y_WIDTH, A_WIDTH+B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH - sign_headroom))-1:0] + + partial_sum[n-2][Y_WIDTH-1:((n-1)*(`DSP_B_MAXWIDTH - sign_headroom))], + partial_sum[n-2][((n-1)*(`DSP_B_MAXWIDTH - sign_headroom))-1:0] }; end else begin -- cgit v1.2.3 From d5cd2c80be95857cfd30d50081d6c87415e9169a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 18 Jul 2019 09:20:48 -0700 Subject: Cleanup --- techlibs/common/mul2dsp.v | 128 +++++++++++++++++++++------------------------- 1 file changed, 58 insertions(+), 70 deletions(-) (limited to 'techlibs') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 31469ddeb..9da778ace 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -97,25 +97,23 @@ module \$__mul_gen (A, B, Y); `else localparam sign_headroom = 0; `endif - localparam n_floored = A_WIDTH/(`DSP_A_MAXWIDTH - sign_headroom); - localparam n = n_floored + (n_floored*(`DSP_A_MAXWIDTH - sign_headroom) < A_WIDTH ? 1 : 0); - wire [`DSP_A_MAXWIDTH+B_WIDTH-1:0] partial [n-1:1]; + localparam n = (A_WIDTH + `DSP_A_MAXWIDTH - sign_headroom - 1)/(`DSP_A_MAXWIDTH - sign_headroom); + localparam partial_Y_WIDTH = `MIN(Y_WIDTH, B_WIDTH+`DSP_A_MAXWIDTH); + wire [partial_Y_WIDTH-1:0] partial [n-1:1]; wire [Y_WIDTH-1:0] partial_sum [n-2:0]; - localparam int_yw = `MIN(Y_WIDTH, B_WIDTH+`DSP_A_MAXWIDTH); \$__mul_gen #( .A_SIGNED(0), .B_SIGNED(B_SIGNED), .A_WIDTH(`DSP_A_MAXWIDTH), .B_WIDTH(B_WIDTH), - .Y_WIDTH(int_yw) + .Y_WIDTH(partial_Y_WIDTH) ) mul_slice_first ( .A({{sign_headroom{1'b0}}, A[`DSP_A_MAXWIDTH-sign_headroom-1:0]}), .B(B), - .Y(partial_sum[0][int_yw-1:0]) + .Y(partial[0]) ); - if (Y_WIDTH > int_yw) - assign partial_sum[0][Y_WIDTH-1:int_yw]=0; + assign partial_sum[0] = partial[0]; for (i = 1; i < n-1; i=i+1) begin:slice \$__mul_gen #( @@ -123,18 +121,18 @@ module \$__mul_gen (A, B, Y); .B_SIGNED(B_SIGNED), .A_WIDTH(`DSP_A_MAXWIDTH), .B_WIDTH(B_WIDTH), - .Y_WIDTH(int_yw) + .Y_WIDTH(partial_Y_WIDTH) ) mul_slice ( - .A({{sign_headroom{1'b0}}, A[(i+1)*(`DSP_A_MAXWIDTH-sign_headroom)-1:i*(`DSP_A_MAXWIDTH-sign_headroom)]}), + .A({{sign_headroom{1'b0}}, A[i*(`DSP_A_MAXWIDTH-sign_headroom) +: `DSP_A_MAXWIDTH-sign_headroom]}), .B(B), - .Y(partial[i][int_yw-1:0]) + .Y(partial[i]) ); - //assign partial_sum[i] = (partial[i] << i*`DSP_A_MAXWIDTH) + partial_sum[i-1]; - assign partial_sum[i] = { - partial[i][int_yw-1:0] - + partial_sum[i-1][Y_WIDTH-1:(i*(`DSP_A_MAXWIDTH-sign_headroom))], - partial_sum[i-1][(i*(`DSP_A_MAXWIDTH-sign_headroom))-1:0] - }; + assign partial_sum[i] = (partial[i] << i*(`DSP_A_MAXWIDTH-sign_headroom)) + partial_sum[i-1]; + //assign partial_sum[i] = { + // partial[i][partial_Y_WIDTH-1:0] + // + partial_sum[i-1][Y_WIDTH-1:(i*(`DSP_A_MAXWIDTH-sign_headroom))], + // partial_sum[i-1][(i*(`DSP_A_MAXWIDTH-sign_headroom))-1:0] + //}; end \$__mul_gen #( @@ -148,12 +146,12 @@ module \$__mul_gen (A, B, Y); .B(B), .Y(partial[n-1][`MIN(Y_WIDTH, A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom)+B_WIDTH)-1:0]) ); - //assign Y = (partial[n-1] << (n-1)*`DSP_A_MAXWIDTH) + partial_sum[n-2]; - assign Y = { - partial[n-1][`MIN(Y_WIDTH, A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom)+B_WIDTH):0] - + partial_sum[n-2][Y_WIDTH-1:((n-1)*(`DSP_A_MAXWIDTH-sign_headroom))], - partial_sum[n-2][((n-1)*(`DSP_A_MAXWIDTH-sign_headroom))-1:0] - }; + assign Y = (partial[n-1] << (n-1)*(`DSP_A_MAXWIDTH-sign_headroom)) + partial_sum[n-2]; + //assign Y = { + // partial[n-1][`MIN(Y_WIDTH, A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom)+B_WIDTH):0] + // + partial_sum[n-2][Y_WIDTH-1:((n-1)*(`DSP_A_MAXWIDTH-sign_headroom))], + // partial_sum[n-2][((n-1)*(`DSP_A_MAXWIDTH-sign_headroom))-1:0] + //}; end else if (B_WIDTH > `DSP_B_MAXWIDTH) begin `ifdef DSP_B_SIGNEDONLY @@ -161,25 +159,23 @@ module \$__mul_gen (A, B, Y); `else localparam sign_headroom = 0; `endif - localparam n_floored = B_WIDTH/(`DSP_B_MAXWIDTH - sign_headroom); - localparam n = n_floored + (n_floored*(`DSP_B_MAXWIDTH - sign_headroom) < B_WIDTH ? 1 : 0); - wire [A_WIDTH+`DSP_B_MAXWIDTH-1:0] partial [n-1:1]; + localparam n = (B_WIDTH + `DSP_B_MAXWIDTH - sign_headroom - 1)/(`DSP_B_MAXWIDTH - sign_headroom); + localparam partial_Y_WIDTH = `MIN(Y_WIDTH, A_WIDTH+`DSP_B_MAXWIDTH); + wire [partial_Y_WIDTH-1:0] partial [n-1:1]; wire [Y_WIDTH-1:0] partial_sum [n-2:0]; - localparam int_yw = `MIN(Y_WIDTH, A_WIDTH+`DSP_B_MAXWIDTH); \$__mul_gen #( .A_SIGNED(A_SIGNED), .B_SIGNED(0), .A_WIDTH(A_WIDTH), .B_WIDTH(`DSP_B_MAXWIDTH), - .Y_WIDTH(int_yw) + .Y_WIDTH(partial_Y_WIDTH) ) mul_first ( .A(A), - .B({{sign_headroom{1'b0}}, B[(`DSP_B_MAXWIDTH - sign_headroom)-1:0]}), - .Y(partial_sum[0][int_yw-1:0]) + .B({{sign_headroom{1'b0}}, B[`DSP_B_MAXWIDTH-sign_headroom-1:0]}), + .Y(partial[0]) ); - if (Y_WIDTH > int_yw) - assign partial_sum[0][Y_WIDTH-1:int_yw]=0; + assign partial_sum[0] = partial[0]; for (i = 1; i < n-1; i=i+1) begin:slice \$__mul_gen #( @@ -187,23 +183,23 @@ module \$__mul_gen (A, B, Y); .B_SIGNED(0), .A_WIDTH(A_WIDTH), .B_WIDTH(`DSP_B_MAXWIDTH), - .Y_WIDTH(int_yw) + .Y_WIDTH(partial_Y_WIDTH) ) mul ( .A(A), - .B({{sign_headroom{1'b0}}, B[(i+1)*(`DSP_B_MAXWIDTH - sign_headroom)-1:i*(`DSP_B_MAXWIDTH - sign_headroom)]}), - .Y(partial[i][int_yw-1:0]) + .B({{sign_headroom{1'b0}}, B[i*(`DSP_B_MAXWIDTH-sign_headroom) +: `DSP_B_MAXWIDTH-sign_headroom]}), + .Y(partial[i]) ); - //assign partial_sum[i] = (partial[i] << i*`DSP_B_MAXWIDTH) + partial_sum[i-1]; - // was: + assign partial_sum[i] = (partial[i] <<< i*(`DSP_B_MAXWIDTH - sign_headroom)) + partial_sum[i-1]; + //// was: + ////assign partial_sum[i] = { + //// partial[i][A_WIDTH+`DSP_B_MAXWIDTH-1:`DSP_B_MAXWIDTH], + //// partial[i][`DSP_B_MAXWIDTH-1:0] + partial_sum[i-1][A_WIDTH+(i*`DSP_B_MAXWIDTH)-1:A_WIDTH+((i-1)*`DSP_B_MAXWIDTH)], + //// partial_sum[i-1][A_WIDTH+((i-1)*`DSP_B_MAXWIDTH):0] //assign partial_sum[i] = { - // partial[i][A_WIDTH+`DSP_B_MAXWIDTH-1:`DSP_B_MAXWIDTH], - // partial[i][`DSP_B_MAXWIDTH-1:0] + partial_sum[i-1][A_WIDTH+(i*`DSP_B_MAXWIDTH)-1:A_WIDTH+((i-1)*`DSP_B_MAXWIDTH)], - // partial_sum[i-1][A_WIDTH+((i-1)*`DSP_B_MAXWIDTH):0] - assign partial_sum[i] = { - partial[i][int_yw-1:0] - + partial_sum[i-1][Y_WIDTH-1:(i*(`DSP_B_MAXWIDTH - sign_headroom))], - partial_sum[i-1][(i*(`DSP_B_MAXWIDTH - sign_headroom))-1:0] - }; + // partial[i][partial_Y_WIDTH-1:0] + // + partial_sum[i-1][Y_WIDTH-1:(i*(`DSP_B_MAXWIDTH - sign_headroom))], + // partial_sum[i-1][(i*(`DSP_B_MAXWIDTH - sign_headroom))-1:0] + //}; end \$__mul_gen #( @@ -217,36 +213,28 @@ module \$__mul_gen (A, B, Y); .B(B[B_WIDTH-1:(n-1)*(`DSP_B_MAXWIDTH - sign_headroom)]), .Y(partial[n-1][`MIN(Y_WIDTH, A_WIDTH+B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH - sign_headroom))-1:0]) ); - // AMD: this came comment out -- looks closer to right answer - //assign Y = (partial[n-1] << (n-1)*`DSP_B_MAXWIDTH) + partial_sum[n-2]; - // was (looks broken) + assign Y = (partial[n-1] << (n-1)*(`DSP_B_MAXWIDTH - sign_headroom)) + partial_sum[n-2]; + //// was (looks broken) + ////assign Y = { + //// partial[n-1][A_WIDTH+`DSP_B_MAXWIDTH-1:`DSP_B_MAXWIDTH], + //// partial[n-1][`DSP_B_MAXWIDTH-1:0] + partial_sum[n-2][A_WIDTH+((n-1)*`DSP_B_MAXWIDTH)-1:A_WIDTH+((n-2)*`DSP_B_MAXWIDTH)], + //// partial_sum[n-2][A_WIDTH+((n-2)*`DSP_B_MAXWIDTH):0] //assign Y = { - // partial[n-1][A_WIDTH+`DSP_B_MAXWIDTH-1:`DSP_B_MAXWIDTH], - // partial[n-1][`DSP_B_MAXWIDTH-1:0] + partial_sum[n-2][A_WIDTH+((n-1)*`DSP_B_MAXWIDTH)-1:A_WIDTH+((n-2)*`DSP_B_MAXWIDTH)], - // partial_sum[n-2][A_WIDTH+((n-2)*`DSP_B_MAXWIDTH):0] - assign Y = { - partial[n-1][`MIN(Y_WIDTH, A_WIDTH+B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH - sign_headroom))-1:0] - + partial_sum[n-2][Y_WIDTH-1:((n-1)*(`DSP_B_MAXWIDTH - sign_headroom))], - partial_sum[n-2][((n-1)*(`DSP_B_MAXWIDTH - sign_headroom))-1:0] - }; + // partial[n-1][`MIN(Y_WIDTH, A_WIDTH+B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH - sign_headroom))-1:0] + // + partial_sum[n-2][Y_WIDTH-1:((n-1)*(`DSP_B_MAXWIDTH - sign_headroom))], + // partial_sum[n-2][((n-1)*(`DSP_B_MAXWIDTH - sign_headroom))-1:0] + //}; end else begin - wire [A_WIDTH+B_WIDTH-1:0] out; - wire [(`DSP_A_MAXWIDTH+`DSP_B_MAXWIDTH)-(A_WIDTH+B_WIDTH)-1:0] dummy; - wire Asign, Bsign; - assign Asign = (A_SIGNED ? A[A_WIDTH-1] : 1'b0); - assign Bsign = (B_SIGNED ? B[B_WIDTH-1] : 1'b0); + (* keep *) wire [Y_WIDTH-1:0] Yunsigned; + wire signed [`DSP_A_MAXWIDTH-1:0] Asigned = $signed(A); + wire signed [`DSP_A_MAXWIDTH-1:0] Bsigned = $signed(B); `DSP_NAME _TECHMAP_REPLACE_ ( - .A({ {{`DSP_A_MAXWIDTH-A_WIDTH}{Asign}}, A }), - .B({ {{`DSP_B_MAXWIDTH-B_WIDTH}{Bsign}}, B }), - .Y({dummy, out}) + .A(Asigned), + .B(Bsigned), + .Y(Yunsigned) ); - if (Y_WIDTH < A_WIDTH+B_WIDTH) - assign Y = out[Y_WIDTH-1:0]; - else begin - wire Ysign = (A_SIGNED || B_SIGNED ? out[A_WIDTH+B_WIDTH-1] : 1'b0); - assign Y = { {{Y_WIDTH-(A_WIDTH+B_WIDTH)}{Ysign}}, out[A_WIDTH+B_WIDTH-1:0] }; - end + assign Y = $signed(Yunsigned[A_WIDTH+B_WIDTH-1:0]); end endgenerate endmodule -- cgit v1.2.3 From 2024357f32b3a5ee562501f66b16c30d9554aa4b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 18 Jul 2019 10:53:18 -0700 Subject: Working for unsigned --- techlibs/common/mul2dsp.v | 80 +++++++++++++++++------------------------------ 1 file changed, 28 insertions(+), 52 deletions(-) (limited to 'techlibs') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 9da778ace..4af3b871b 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -34,7 +34,7 @@ module \$mul (A, B, Y); output [Y_WIDTH-1:0] Y; generate - if (`DSP_A_SIGNEDONLY && `DSP_B_SIGNEDONLY && !A_SIGNED) begin + if (`DSP_SIGNEDONLY && !A_SIGNED) begin wire [1:0] dummy; \$mul #( .A_SIGNED(1), @@ -89,22 +89,23 @@ module \$__mul_gen (A, B, Y); wire [1023:0] _TECHMAP_DO_ = "proc; clean"; +`ifdef DSP_SIGNEDONLY + localparam sign_headroom = 1; +`else + localparam sign_headroom = 0; +`endif + genvar i; generate if (A_WIDTH > `DSP_A_MAXWIDTH) begin -`ifdef DSP_A_SIGNEDONLY - localparam sign_headroom = 1; -`else - localparam sign_headroom = 0; -`endif localparam n = (A_WIDTH + `DSP_A_MAXWIDTH - sign_headroom - 1)/(`DSP_A_MAXWIDTH - sign_headroom); localparam partial_Y_WIDTH = `MIN(Y_WIDTH, B_WIDTH+`DSP_A_MAXWIDTH); wire [partial_Y_WIDTH-1:0] partial [n-1:1]; - wire [Y_WIDTH-1:0] partial_sum [n-2:0]; + wire [Y_WIDTH-1:0] partial_sum [n-1:0]; \$__mul_gen #( .A_SIGNED(0), - .B_SIGNED(B_SIGNED), + .B_SIGNED(0), .A_WIDTH(`DSP_A_MAXWIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(partial_Y_WIDTH) @@ -118,7 +119,7 @@ module \$__mul_gen (A, B, Y); for (i = 1; i < n-1; i=i+1) begin:slice \$__mul_gen #( .A_SIGNED(0), - .B_SIGNED(B_SIGNED), + .B_SIGNED(0), .A_WIDTH(`DSP_A_MAXWIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(partial_Y_WIDTH) @@ -128,11 +129,6 @@ module \$__mul_gen (A, B, Y); .Y(partial[i]) ); assign partial_sum[i] = (partial[i] << i*(`DSP_A_MAXWIDTH-sign_headroom)) + partial_sum[i-1]; - //assign partial_sum[i] = { - // partial[i][partial_Y_WIDTH-1:0] - // + partial_sum[i-1][Y_WIDTH-1:(i*(`DSP_A_MAXWIDTH-sign_headroom))], - // partial_sum[i-1][(i*(`DSP_A_MAXWIDTH-sign_headroom))-1:0] - //}; end \$__mul_gen #( @@ -140,18 +136,13 @@ module \$__mul_gen (A, B, Y); .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom)), .B_WIDTH(B_WIDTH), - .Y_WIDTH(`MIN(Y_WIDTH, A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom)+B_WIDTH)), + .Y_WIDTH(A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom) + B_WIDTH), ) mul_slice_last ( .A(A[A_WIDTH-1:(n-1)*(`DSP_A_MAXWIDTH-sign_headroom)]), .B(B), - .Y(partial[n-1][`MIN(Y_WIDTH, A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom)+B_WIDTH)-1:0]) + .Y(partial[n-1]) ); assign Y = (partial[n-1] << (n-1)*(`DSP_A_MAXWIDTH-sign_headroom)) + partial_sum[n-2]; - //assign Y = { - // partial[n-1][`MIN(Y_WIDTH, A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom)+B_WIDTH):0] - // + partial_sum[n-2][Y_WIDTH-1:((n-1)*(`DSP_A_MAXWIDTH-sign_headroom))], - // partial_sum[n-2][((n-1)*(`DSP_A_MAXWIDTH-sign_headroom))-1:0] - //}; end else if (B_WIDTH > `DSP_B_MAXWIDTH) begin `ifdef DSP_B_SIGNEDONLY @@ -162,7 +153,7 @@ module \$__mul_gen (A, B, Y); localparam n = (B_WIDTH + `DSP_B_MAXWIDTH - sign_headroom - 1)/(`DSP_B_MAXWIDTH - sign_headroom); localparam partial_Y_WIDTH = `MIN(Y_WIDTH, A_WIDTH+`DSP_B_MAXWIDTH); wire [partial_Y_WIDTH-1:0] partial [n-1:1]; - wire [Y_WIDTH-1:0] partial_sum [n-2:0]; + wire [Y_WIDTH-1:0] partial_sum [n-1:0]; \$__mul_gen #( .A_SIGNED(A_SIGNED), @@ -189,17 +180,7 @@ module \$__mul_gen (A, B, Y); .B({{sign_headroom{1'b0}}, B[i*(`DSP_B_MAXWIDTH-sign_headroom) +: `DSP_B_MAXWIDTH-sign_headroom]}), .Y(partial[i]) ); - assign partial_sum[i] = (partial[i] <<< i*(`DSP_B_MAXWIDTH - sign_headroom)) + partial_sum[i-1]; - //// was: - ////assign partial_sum[i] = { - //// partial[i][A_WIDTH+`DSP_B_MAXWIDTH-1:`DSP_B_MAXWIDTH], - //// partial[i][`DSP_B_MAXWIDTH-1:0] + partial_sum[i-1][A_WIDTH+(i*`DSP_B_MAXWIDTH)-1:A_WIDTH+((i-1)*`DSP_B_MAXWIDTH)], - //// partial_sum[i-1][A_WIDTH+((i-1)*`DSP_B_MAXWIDTH):0] - //assign partial_sum[i] = { - // partial[i][partial_Y_WIDTH-1:0] - // + partial_sum[i-1][Y_WIDTH-1:(i*(`DSP_B_MAXWIDTH - sign_headroom))], - // partial_sum[i-1][(i*(`DSP_B_MAXWIDTH - sign_headroom))-1:0] - //}; + assign partial_sum[i] = (partial[i] << i*(`DSP_B_MAXWIDTH - sign_headroom)) + partial_sum[i-1]; end \$__mul_gen #( @@ -207,34 +188,29 @@ module \$__mul_gen (A, B, Y); .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH - sign_headroom)), - .Y_WIDTH(`MIN(Y_WIDTH, A_WIDTH+B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH - sign_headroom))) + .Y_WIDTH(A_WIDTH + B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH - sign_headroom)) ) mul_last ( .A(A), .B(B[B_WIDTH-1:(n-1)*(`DSP_B_MAXWIDTH - sign_headroom)]), - .Y(partial[n-1][`MIN(Y_WIDTH, A_WIDTH+B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH - sign_headroom))-1:0]) + .Y(partial[n-1]) ); assign Y = (partial[n-1] << (n-1)*(`DSP_B_MAXWIDTH - sign_headroom)) + partial_sum[n-2]; - //// was (looks broken) - ////assign Y = { - //// partial[n-1][A_WIDTH+`DSP_B_MAXWIDTH-1:`DSP_B_MAXWIDTH], - //// partial[n-1][`DSP_B_MAXWIDTH-1:0] + partial_sum[n-2][A_WIDTH+((n-1)*`DSP_B_MAXWIDTH)-1:A_WIDTH+((n-2)*`DSP_B_MAXWIDTH)], - //// partial_sum[n-2][A_WIDTH+((n-2)*`DSP_B_MAXWIDTH):0] - //assign Y = { - // partial[n-1][`MIN(Y_WIDTH, A_WIDTH+B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH - sign_headroom))-1:0] - // + partial_sum[n-2][Y_WIDTH-1:((n-1)*(`DSP_B_MAXWIDTH - sign_headroom))], - // partial_sum[n-2][((n-1)*(`DSP_B_MAXWIDTH - sign_headroom))-1:0] - //}; end else begin - (* keep *) wire [Y_WIDTH-1:0] Yunsigned; - wire signed [`DSP_A_MAXWIDTH-1:0] Asigned = $signed(A); - wire signed [`DSP_A_MAXWIDTH-1:0] Bsigned = $signed(B); + if (A_SIGNED) + wire signed [`DSP_A_MAXWIDTH-1:0] Aext = $signed(A); + else + wire [`DSP_A_MAXWIDTH-1:0] Aext = A; + if (B_SIGNED) + wire signed [`DSP_B_MAXWIDTH-1:0] Bext = $signed(B); + else + wire [`DSP_B_MAXWIDTH-1:0] Bext = B; + `DSP_NAME _TECHMAP_REPLACE_ ( - .A(Asigned), - .B(Bsigned), - .Y(Yunsigned) + .A(Aext), + .B(Bext), + .Y(Y) ); - assign Y = $signed(Yunsigned[A_WIDTH+B_WIDTH-1:0]); end endgenerate endmodule -- cgit v1.2.3 From 5562cb08a47881bee30bf79f8ca720b997166b2f Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 18 Jul 2019 13:09:55 -0700 Subject: Use single DSP_SIGNEDONLY macro --- techlibs/xilinx/synth_xilinx.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 2e2fbbd9d..e5a27015a 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -286,7 +286,7 @@ struct SynthXilinxPass : public ScriptPass if (!nodsp || help_mode) { // NB: Xilinx multipliers are signed only - run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=25 -D DSP_A_SIGNEDONLY=1 -D DSP_B_MAXWIDTH=18 -D DSP_B_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18"); + run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=25 -D DSP_B_MAXWIDTH=18 -D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18"); } run("alumacc"); -- cgit v1.2.3 From 8326af5418205e51452e0cced8d2253afe730e76 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 18 Jul 2019 13:11:26 -0700 Subject: Fix signed multiplier decomposition --- techlibs/common/mul2dsp.v | 65 ++++++++++++++++++++++++++--------------------- 1 file changed, 36 insertions(+), 29 deletions(-) (limited to 'techlibs') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 4af3b871b..2819c939e 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -5,14 +5,11 @@ `ifndef DSP_A_MAXWIDTH $error("Macro DSP_A_MAXWIDTH must be defined"); `endif -`ifndef DSP_A_SIGNEDONLY -`define DSP_A_SIGNEDONLY 0 -`endif `ifndef DSP_B_MAXWIDTH $error("Macro DSP_B_MAXWIDTH must be defined"); `endif -`ifndef DSP_B_SIGNEDONLY -`define DSP_B_SIGNEDONLY 0 +`ifndef DSP_SIGNEDONLY +`define DSP_SIGNEDONLY 0 `endif `ifndef DSP_NAME @@ -34,7 +31,9 @@ module \$mul (A, B, Y); output [Y_WIDTH-1:0] Y; generate - if (`DSP_SIGNEDONLY && !A_SIGNED) begin + if (A_SIGNED != B_SIGNED) + wire _TECHMAP_FAIL_ = 1; + else if (`DSP_SIGNEDONLY && !A_SIGNED) begin wire [1:0] dummy; \$mul #( .A_SIGNED(1), @@ -98,19 +97,25 @@ module \$__mul_gen (A, B, Y); genvar i; generate if (A_WIDTH > `DSP_A_MAXWIDTH) begin - localparam n = (A_WIDTH + `DSP_A_MAXWIDTH - sign_headroom - 1)/(`DSP_A_MAXWIDTH - sign_headroom); + localparam n = (A_WIDTH+`DSP_A_MAXWIDTH-sign_headroom-1) / (`DSP_A_MAXWIDTH-sign_headroom); localparam partial_Y_WIDTH = `MIN(Y_WIDTH, B_WIDTH+`DSP_A_MAXWIDTH); - wire [partial_Y_WIDTH-1:0] partial [n-1:1]; - wire [Y_WIDTH-1:0] partial_sum [n-1:0]; + if (A_SIGNED && B_SIGNED) begin + wire signed [partial_Y_WIDTH-1:0] partial [n-1:0]; + wire signed [Y_WIDTH-1:0] partial_sum [n-1:0]; + end + else begin + wire [partial_Y_WIDTH-1:0] partial [n-1:0]; + wire [Y_WIDTH-1:0] partial_sum [n-1:0]; + end \$__mul_gen #( .A_SIGNED(0), - .B_SIGNED(0), + .B_SIGNED(B_SIGNED), .A_WIDTH(`DSP_A_MAXWIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(partial_Y_WIDTH) ) mul_slice_first ( - .A({{sign_headroom{1'b0}}, A[`DSP_A_MAXWIDTH-sign_headroom-1:0]}), + .A({{sign_headroom{1'b0}}, A[`DSP_A_MAXWIDTH-sign_headroom-1 : 0]}), .B(B), .Y(partial[0]) ); @@ -119,7 +124,7 @@ module \$__mul_gen (A, B, Y); for (i = 1; i < n-1; i=i+1) begin:slice \$__mul_gen #( .A_SIGNED(0), - .B_SIGNED(0), + .B_SIGNED(B_SIGNED), .A_WIDTH(`DSP_A_MAXWIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(partial_Y_WIDTH) @@ -136,24 +141,26 @@ module \$__mul_gen (A, B, Y); .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom)), .B_WIDTH(B_WIDTH), - .Y_WIDTH(A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom) + B_WIDTH), + .Y_WIDTH(partial_Y_WIDTH) ) mul_slice_last ( - .A(A[A_WIDTH-1:(n-1)*(`DSP_A_MAXWIDTH-sign_headroom)]), + .A(A[A_WIDTH-1 : (n-1)*(`DSP_A_MAXWIDTH-sign_headroom)]), .B(B), .Y(partial[n-1]) ); - assign Y = (partial[n-1] << (n-1)*(`DSP_A_MAXWIDTH-sign_headroom)) + partial_sum[n-2]; + assign partial_sum[n-1] = (partial[n-1] << (n-1)*(`DSP_A_MAXWIDTH-sign_headroom)) + partial_sum[n-2]; + assign Y = partial_sum[n-1]; end else if (B_WIDTH > `DSP_B_MAXWIDTH) begin -`ifdef DSP_B_SIGNEDONLY - localparam sign_headroom = 1; -`else - localparam sign_headroom = 0; -`endif - localparam n = (B_WIDTH + `DSP_B_MAXWIDTH - sign_headroom - 1)/(`DSP_B_MAXWIDTH - sign_headroom); + localparam n = (B_WIDTH+`DSP_B_MAXWIDTH-sign_headroom-1) / (`DSP_B_MAXWIDTH-sign_headroom); localparam partial_Y_WIDTH = `MIN(Y_WIDTH, A_WIDTH+`DSP_B_MAXWIDTH); - wire [partial_Y_WIDTH-1:0] partial [n-1:1]; - wire [Y_WIDTH-1:0] partial_sum [n-1:0]; + if (A_SIGNED && B_SIGNED) begin + wire signed [partial_Y_WIDTH-1:0] partial [n-1:0]; + wire signed [Y_WIDTH-1:0] partial_sum [n-1:0]; + end + else begin + wire [partial_Y_WIDTH-1:0] partial [n-1:0]; + wire [Y_WIDTH-1:0] partial_sum [n-1:0]; + end \$__mul_gen #( .A_SIGNED(A_SIGNED), @@ -163,7 +170,7 @@ module \$__mul_gen (A, B, Y); .Y_WIDTH(partial_Y_WIDTH) ) mul_first ( .A(A), - .B({{sign_headroom{1'b0}}, B[`DSP_B_MAXWIDTH-sign_headroom-1:0]}), + .B({{sign_headroom{1'b0}}, B[`DSP_B_MAXWIDTH-sign_headroom-1 : 0]}), .Y(partial[0]) ); assign partial_sum[0] = partial[0]; @@ -180,21 +187,21 @@ module \$__mul_gen (A, B, Y); .B({{sign_headroom{1'b0}}, B[i*(`DSP_B_MAXWIDTH-sign_headroom) +: `DSP_B_MAXWIDTH-sign_headroom]}), .Y(partial[i]) ); - assign partial_sum[i] = (partial[i] << i*(`DSP_B_MAXWIDTH - sign_headroom)) + partial_sum[i-1]; + assign partial_sum[i] = (partial[i] << i*(`DSP_B_MAXWIDTH-sign_headroom)) + partial_sum[i-1]; end \$__mul_gen #( .A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), - .B_WIDTH(B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH - sign_headroom)), - .Y_WIDTH(A_WIDTH + B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH - sign_headroom)) + .B_WIDTH(B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH-sign_headroom)), + .Y_WIDTH(partial_Y_WIDTH) ) mul_last ( .A(A), - .B(B[B_WIDTH-1:(n-1)*(`DSP_B_MAXWIDTH - sign_headroom)]), + .B(B[B_WIDTH-1 : (n-1)*(`DSP_B_MAXWIDTH-sign_headroom)]), .Y(partial[n-1]) ); - assign Y = (partial[n-1] << (n-1)*(`DSP_B_MAXWIDTH - sign_headroom)) + partial_sum[n-2]; + assign Y = (partial[n-1] << (n-1)*(`DSP_B_MAXWIDTH-sign_headroom)) + partial_sum[n-2]; end else begin if (A_SIGNED) -- cgit v1.2.3 From e22a7522422ec5f2f6db52d4e9c98d09868ea3e3 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 18 Jul 2019 15:21:23 -0700 Subject: Make consistent --- techlibs/common/mul2dsp.v | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 2819c939e..ee53701ee 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -201,7 +201,8 @@ module \$__mul_gen (A, B, Y); .B(B[B_WIDTH-1 : (n-1)*(`DSP_B_MAXWIDTH-sign_headroom)]), .Y(partial[n-1]) ); - assign Y = (partial[n-1] << (n-1)*(`DSP_B_MAXWIDTH-sign_headroom)) + partial_sum[n-2]; + assign partial_sum[n-1] = (partial[n-1] << (n-1)*(`DSP_A_MAXWIDTH-sign_headroom)) + partial_sum[n-2]; + assign Y = partial_sum[n-1]; end else begin if (A_SIGNED) -- cgit v1.2.3 From 2339b7fc3732996a217f635d95f1f7400cf43d48 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 18 Jul 2019 15:37:35 -0700 Subject: mul2dsp to create cells that can be interchanged with $mul --- techlibs/common/mul2dsp.v | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index ee53701ee..391b395ff 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -214,7 +214,13 @@ module \$__mul_gen (A, B, Y); else wire [`DSP_B_MAXWIDTH-1:0] Bext = B; - `DSP_NAME _TECHMAP_REPLACE_ ( + `DSP_NAME #( + .A_SIGNED(A_SIGNED), + .B_SIGNED(B_SIGNED), + .A_WIDTH(`DSP_A_MAXWIDTH), + .B_WIDTH(`DSP_B_MAXWIDTH), + .Y_WIDTH(`DSP_A_MAXWIDTH+`DSP_B_MAXWIDTH), + ) _TECHMAP_REPLACE_ ( .A(Aext), .B(Bext), .Y(Y) -- cgit v1.2.3 From 266c1ae1226656d90ee6416c214ef64fe8b5906f Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 18 Jul 2019 15:38:09 -0700 Subject: synth_ice40 to decompose into 16x16 --- techlibs/ice40/synth_ice40.cc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 0474e76e9..66446deb7 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -265,8 +265,10 @@ struct SynthIce40Pass : public ScriptPass run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4"); run("opt_expr"); run("opt_clean"); - if (help_mode || dsp) + if (help_mode || dsp) { + run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 -D DSP_NAME=$__MUL16X16"); run("ice40_dsp", "(if -dsp)"); + } run("alumacc"); run("opt"); run("fsm"); -- cgit v1.2.3 From 15c2a79ab96e280ecd6311cb0b726b348a2b1eb5 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 18 Jul 2019 16:04:58 -0700 Subject: Do not define `DSP_SIGNEDONLY macro if no exists --- techlibs/common/mul2dsp.v | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'techlibs') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 391b395ff..1f4759929 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -8,9 +8,6 @@ $error("Macro DSP_A_MAXWIDTH must be defined"); `ifndef DSP_B_MAXWIDTH $error("Macro DSP_B_MAXWIDTH must be defined"); `endif -`ifndef DSP_SIGNEDONLY -`define DSP_SIGNEDONLY 0 -`endif `ifndef DSP_NAME $error("Macro DSP_NAME must be defined"); @@ -33,7 +30,8 @@ module \$mul (A, B, Y); generate if (A_SIGNED != B_SIGNED) wire _TECHMAP_FAIL_ = 1; - else if (`DSP_SIGNEDONLY && !A_SIGNED) begin +`ifdef DSP_SIGNEDONLY + else if (!A_SIGNED) begin wire [1:0] dummy; \$mul #( .A_SIGNED(1), @@ -47,6 +45,7 @@ module \$mul (A, B, Y); .Y({dummy, Y}) ); end +`endif // NB: A_SIGNED == B_SIGNED == 0 from here else if (A_WIDTH >= B_WIDTH) \$__mul_gen #( -- cgit v1.2.3 From 601fac97e4c48d524d5c7f9b4688b536c2e1c891 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 18 Jul 2019 21:02:49 -0700 Subject: Add params --- techlibs/xilinx/dsp_map.v | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'techlibs') diff --git a/techlibs/xilinx/dsp_map.v b/techlibs/xilinx/dsp_map.v index 32f570935..3d7b09d69 100644 --- a/techlibs/xilinx/dsp_map.v +++ b/techlibs/xilinx/dsp_map.v @@ -1,4 +1,10 @@ module \$__MUL25X18 (input signed [24:0] A, input signed [17:0] B, output signed [42:0] Y); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 0; + parameter B_WIDTH = 0; + parameter Y_WIDTH = 0; + wire [47:0] P_48; DSP48E1 #( // Disable all registers -- cgit v1.2.3 From bddd641290d3c01d86144362cd0e16c82e0bcfd8 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 18 Jul 2019 21:03:54 -0700 Subject: Fix SB_MAC sim model -- do not sign extend internal products? --- techlibs/ice40/cells_sim.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'techlibs') diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index 609facc93..4402f8d36 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -1363,9 +1363,9 @@ module SB_MAC16 ( wire [15:0] p_Ah_Bh, p_Al_Bh, p_Ah_Bl, p_Al_Bl; wire [15:0] Ah, Al, Bh, Bl; assign Ah = {A_SIGNED ? {8{iA[15]}} : 8'b0, iA[15: 8]}; - assign Al = {A_SIGNED ? {8{iA[ 7]}} : 8'b0, iA[ 7: 0]}; + assign Al = {A_SIGNED && MODE_8x8 ? {8{iA[ 7]}} : 8'b0, iA[ 7: 0]}; assign Bh = {B_SIGNED ? {8{iB[15]}} : 8'b0, iB[15: 8]}; - assign Bl = {B_SIGNED ? {8{iB[ 7]}} : 8'b0, iB[ 7: 0]}; + assign Bl = {B_SIGNED && MODE_8x8 ? {8{iB[ 7]}} : 8'b0, iB[ 7: 0]}; assign p_Ah_Bh = Ah * Bh; assign p_Al_Bh = Al * Bh; assign p_Ah_Bl = Ah * Bl; -- cgit v1.2.3 From 2168568f43984af2d194c0eab74ad73443f7e84c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 19 Jul 2019 09:16:13 -0700 Subject: Use sign_headroom instead --- techlibs/common/mul2dsp.v | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'techlibs') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 1f4759929..da887d426 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -108,7 +108,7 @@ module \$__mul_gen (A, B, Y); end \$__mul_gen #( - .A_SIGNED(0), + .A_SIGNED(sign_headroom), .B_SIGNED(B_SIGNED), .A_WIDTH(`DSP_A_MAXWIDTH), .B_WIDTH(B_WIDTH), @@ -122,7 +122,7 @@ module \$__mul_gen (A, B, Y); for (i = 1; i < n-1; i=i+1) begin:slice \$__mul_gen #( - .A_SIGNED(0), + .A_SIGNED(sign_headroom), .B_SIGNED(B_SIGNED), .A_WIDTH(`DSP_A_MAXWIDTH), .B_WIDTH(B_WIDTH), @@ -163,7 +163,7 @@ module \$__mul_gen (A, B, Y); \$__mul_gen #( .A_SIGNED(A_SIGNED), - .B_SIGNED(0), + .B_SIGNED(sign_headroom), .A_WIDTH(A_WIDTH), .B_WIDTH(`DSP_B_MAXWIDTH), .Y_WIDTH(partial_Y_WIDTH) @@ -177,7 +177,7 @@ module \$__mul_gen (A, B, Y); for (i = 1; i < n-1; i=i+1) begin:slice \$__mul_gen #( .A_SIGNED(A_SIGNED), - .B_SIGNED(0), + .B_SIGNED(sign_headroom), .A_WIDTH(A_WIDTH), .B_WIDTH(`DSP_B_MAXWIDTH), .Y_WIDTH(partial_Y_WIDTH) -- cgit v1.2.3 From ca94c2d3c4785c45a2fefdb659e9ff94f2f8c7b3 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 19 Jul 2019 10:27:44 -0700 Subject: Fix typo in B --- techlibs/common/mul2dsp.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index ee53701ee..da1c7c0c7 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -201,7 +201,7 @@ module \$__mul_gen (A, B, Y); .B(B[B_WIDTH-1 : (n-1)*(`DSP_B_MAXWIDTH-sign_headroom)]), .Y(partial[n-1]) ); - assign partial_sum[n-1] = (partial[n-1] << (n-1)*(`DSP_A_MAXWIDTH-sign_headroom)) + partial_sum[n-2]; + assign partial_sum[n-1] = (partial[n-1] << (n-1)*(`DSP_B_MAXWIDTH-sign_headroom)) + partial_sum[n-2]; assign Y = partial_sum[n-1]; end else begin -- cgit v1.2.3 From 1d14cec7fd41710aba0bb910a82fa5ca81c4adb0 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 19 Jul 2019 11:39:24 -0700 Subject: Add a DSP_MINWIDTH macro, and soft-logic for {A_WIDTH,B_WIDTH} <= 1 too --- techlibs/common/mul2dsp.v | 96 +++++++++++++++++++++++++++++++++-------------- 1 file changed, 68 insertions(+), 28 deletions(-) (limited to 'techlibs') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index b6aa02834..aab568c9f 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -28,27 +28,11 @@ module \$mul (A, B, Y); output [Y_WIDTH-1:0] Y; generate - if (A_SIGNED != B_SIGNED) + if (A_SIGNED != B_SIGNED || A_WIDTH <= 1 || B_WIDTH <= 1) wire _TECHMAP_FAIL_ = 1; -`ifdef DSP_SIGNEDONLY - else if (!A_SIGNED) begin - wire [1:0] dummy; - \$mul #( - .A_SIGNED(1), - .B_SIGNED(1), - .A_WIDTH(A_WIDTH + 1), - .B_WIDTH(B_WIDTH + 1), - .Y_WIDTH(Y_WIDTH + 2) - ) _TECHMAP_REPLACE_ ( - .A({1'b0, A}), - .B({1'b0, B}), - .Y({dummy, Y}) - ); - end -`endif // NB: A_SIGNED == B_SIGNED == 0 from here else if (A_WIDTH >= B_WIDTH) - \$__mul_gen #( + \$__mul #( .A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), @@ -60,7 +44,7 @@ module \$mul (A, B, Y); .Y(Y) ); else - \$__mul_gen #( + \$__mul #( .A_SIGNED(B_SIGNED), .B_SIGNED(A_SIGNED), .A_WIDTH(B_WIDTH), @@ -74,7 +58,7 @@ module \$mul (A, B, Y); endgenerate endmodule -module \$__mul_gen (A, B, Y); +module \$__mul (A, B, Y); parameter A_SIGNED = 0; parameter B_SIGNED = 0; parameter A_WIDTH = 1; @@ -95,7 +79,13 @@ module \$__mul_gen (A, B, Y); genvar i; generate - if (A_WIDTH > `DSP_A_MAXWIDTH) begin + if (A_WIDTH <= 1 || B_WIDTH <= 1) + wire _TECHMAP_FAIL_ = 1; +`ifdef DSP_MINWIDTH + else if (A_WIDTH+B_WIDTH < `DSP_MINWIDTH || Y_WIDTH < `DSP_MINWIDTH) + wire _TECHMAP_FAIL_ = 1; +`endif + else if (A_WIDTH > `DSP_A_MAXWIDTH) begin localparam n = (A_WIDTH+`DSP_A_MAXWIDTH-sign_headroom-1) / (`DSP_A_MAXWIDTH-sign_headroom); localparam partial_Y_WIDTH = `MIN(Y_WIDTH, B_WIDTH+`DSP_A_MAXWIDTH); if (A_SIGNED && B_SIGNED) begin @@ -107,7 +97,7 @@ module \$__mul_gen (A, B, Y); wire [Y_WIDTH-1:0] partial_sum [n-1:0]; end - \$__mul_gen #( + \$__mul #( .A_SIGNED(sign_headroom), .B_SIGNED(B_SIGNED), .A_WIDTH(`DSP_A_MAXWIDTH), @@ -121,7 +111,7 @@ module \$__mul_gen (A, B, Y); assign partial_sum[0] = partial[0]; for (i = 1; i < n-1; i=i+1) begin:slice - \$__mul_gen #( + \$__mul #( .A_SIGNED(sign_headroom), .B_SIGNED(B_SIGNED), .A_WIDTH(`DSP_A_MAXWIDTH), @@ -135,7 +125,7 @@ module \$__mul_gen (A, B, Y); assign partial_sum[i] = (partial[i] << i*(`DSP_A_MAXWIDTH-sign_headroom)) + partial_sum[i-1]; end - \$__mul_gen #( + \$__mul #( .A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom)), @@ -161,7 +151,7 @@ module \$__mul_gen (A, B, Y); wire [Y_WIDTH-1:0] partial_sum [n-1:0]; end - \$__mul_gen #( + \$__mul #( .A_SIGNED(A_SIGNED), .B_SIGNED(sign_headroom), .A_WIDTH(A_WIDTH), @@ -175,7 +165,7 @@ module \$__mul_gen (A, B, Y); assign partial_sum[0] = partial[0]; for (i = 1; i < n-1; i=i+1) begin:slice - \$__mul_gen #( + \$__mul #( .A_SIGNED(A_SIGNED), .B_SIGNED(sign_headroom), .A_WIDTH(A_WIDTH), @@ -189,7 +179,7 @@ module \$__mul_gen (A, B, Y); assign partial_sum[i] = (partial[i] << i*(`DSP_B_MAXWIDTH-sign_headroom)) + partial_sum[i-1]; end - \$__mul_gen #( + \$__mul #( .A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), @@ -218,7 +208,7 @@ module \$__mul_gen (A, B, Y); .B_SIGNED(B_SIGNED), .A_WIDTH(`DSP_A_MAXWIDTH), .B_WIDTH(`DSP_B_MAXWIDTH), - .Y_WIDTH(`DSP_A_MAXWIDTH+`DSP_B_MAXWIDTH), + .Y_WIDTH(`MIN(Y_WIDTH,`DSP_A_MAXWIDTH+`DSP_B_MAXWIDTH)), ) _TECHMAP_REPLACE_ ( .A(Aext), .B(Bext), @@ -228,4 +218,54 @@ module \$__mul_gen (A, B, Y); endgenerate endmodule +(* techmap_celltype = "$__mul" *) +module _90_internal_mul_to_external (A, B, Y); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 1; + parameter B_WIDTH = 1; + parameter Y_WIDTH = 1; + input [A_WIDTH-1:0] A; + input [B_WIDTH-1:0] B; + output [Y_WIDTH-1:0] Y; + + generate + if (A_SIGNED && !B_SIGNED) + \$mul #( + .A_SIGNED(A_SIGNED), + .B_SIGNED(1), + .A_WIDTH(A_WIDTH), + .B_WIDTH(B_WIDTH+1), + .Y_WIDTH(Y_WIDTH) + ) _TECHMAP_REPLACE_ ( + .A(A), + .B({1'b0, B}), + .Y(Y) + ); + else if (!A_SIGNED && B_SIGNED) + \$mul #( + .A_SIGNED(1), + .B_SIGNED(B_SIGNED), + .A_WIDTH(A_WIDTH+1), + .B_WIDTH(B_WIDTH), + .Y_WIDTH(Y_WIDTH) + ) _TECHMAP_REPLACE_ ( + .A({1'b0, A}), + .B(B), + .Y(Y) + ); + else + \$mul #( + .A_SIGNED(A_SIGNED), + .B_SIGNED(B_SIGNED), + .A_WIDTH(A_WIDTH), + .B_WIDTH(B_WIDTH), + .Y_WIDTH(Y_WIDTH) + ) _TECHMAP_REPLACE_ ( + .A(A), + .B(B), + .Y(Y) + ); + endgenerate +endmodule -- cgit v1.2.3 From 3dc3c749d5c7c10e1aa504f48794ef0a87513a82 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 19 Jul 2019 11:41:00 -0700 Subject: Add DSP_MINWIDTH=11 for ice40 since ice40_dsp uses this threshold --- techlibs/ice40/synth_ice40.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 5053e445d..77bd0ac81 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -266,7 +266,7 @@ struct SynthIce40Pass : public ScriptPass run("opt_expr"); run("opt_clean"); if (help_mode || dsp) { - run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 -D DSP_NAME=$__MUL16X16"); + run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 -D DSP_MINWIDTH=11 -D DSP_NAME=$__MUL16X16", "(if -dsp)"); run("ice40_dsp", "(if -dsp)"); } run("alumacc"); -- cgit v1.2.3 From bba72f03ddd6db370e8fd5afbf14f4f89d0c7e3e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 19 Jul 2019 11:54:26 -0700 Subject: Do not $mul -> $__mul if A and B are less than maxwidth --- techlibs/common/mul2dsp.v | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index aab568c9f..5444d842a 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -28,7 +28,9 @@ module \$mul (A, B, Y); output [Y_WIDTH-1:0] Y; generate - if (A_SIGNED != B_SIGNED || A_WIDTH <= 1 || B_WIDTH <= 1) + if (A_SIGNED != B_SIGNED) + wire _TECHMAP_FAIL_ = 1; + else if (A_WIDTH <= `DSP_A_MAXWIDTH && B_WIDTH <= `DSP_B_MAXWIDTH) wire _TECHMAP_FAIL_ = 1; // NB: A_SIGNED == B_SIGNED == 0 from here else if (A_WIDTH >= B_WIDTH) -- cgit v1.2.3 From 595a8f032f1e9db385959f92a4a414a40de291fd Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 19 Jul 2019 15:50:13 -0700 Subject: Do not do sign extension in techmap; let packer do it --- techlibs/common/mul2dsp.v | 19 +++++-------------- 1 file changed, 5 insertions(+), 14 deletions(-) (limited to 'techlibs') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 5444d842a..70c2c42c6 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -196,24 +196,15 @@ module \$__mul (A, B, Y); assign Y = partial_sum[n-1]; end else begin - if (A_SIGNED) - wire signed [`DSP_A_MAXWIDTH-1:0] Aext = $signed(A); - else - wire [`DSP_A_MAXWIDTH-1:0] Aext = A; - if (B_SIGNED) - wire signed [`DSP_B_MAXWIDTH-1:0] Bext = $signed(B); - else - wire [`DSP_B_MAXWIDTH-1:0] Bext = B; - `DSP_NAME #( .A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), - .A_WIDTH(`DSP_A_MAXWIDTH), - .B_WIDTH(`DSP_B_MAXWIDTH), - .Y_WIDTH(`MIN(Y_WIDTH,`DSP_A_MAXWIDTH+`DSP_B_MAXWIDTH)), + .A_WIDTH(A_WIDTH), + .B_WIDTH(B_WIDTH), + .Y_WIDTH(`MIN(Y_WIDTH,A_WIDTH+B_WIDTH)), ) _TECHMAP_REPLACE_ ( - .A(Aext), - .B(Bext), + .A(A), + .B(B), .Y(Y) ); end -- cgit v1.2.3 From 47fd042b9f8a92df1e1d59042068e7846c4ce808 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 19 Jul 2019 20:20:33 -0700 Subject: Indirection via $__soft_mul --- techlibs/common/mul2dsp.v | 18 +++++++++--------- techlibs/ice40/synth_ice40.cc | 1 + 2 files changed, 10 insertions(+), 9 deletions(-) (limited to 'techlibs') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 70c2c42c6..8b1ddefbf 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -28,9 +28,7 @@ module \$mul (A, B, Y); output [Y_WIDTH-1:0] Y; generate - if (A_SIGNED != B_SIGNED) - wire _TECHMAP_FAIL_ = 1; - else if (A_WIDTH <= `DSP_A_MAXWIDTH && B_WIDTH <= `DSP_B_MAXWIDTH) + if (A_SIGNED != B_SIGNED || A_WIDTH <= 1 || B_WIDTH <= 1) wire _TECHMAP_FAIL_ = 1; // NB: A_SIGNED == B_SIGNED == 0 from here else if (A_WIDTH >= B_WIDTH) @@ -212,7 +210,7 @@ module \$__mul (A, B, Y); endmodule (* techmap_celltype = "$__mul" *) -module _90_internal_mul_to_external (A, B, Y); +module $__soft_mul (A, B, Y); parameter A_SIGNED = 0; parameter B_SIGNED = 0; parameter A_WIDTH = 1; @@ -223,9 +221,11 @@ module _90_internal_mul_to_external (A, B, Y); input [B_WIDTH-1:0] B; output [Y_WIDTH-1:0] Y; + // Indirection necessary since mapping + // back to $mul will cause recursion generate if (A_SIGNED && !B_SIGNED) - \$mul #( + \$__soft__mul #( .A_SIGNED(A_SIGNED), .B_SIGNED(1), .A_WIDTH(A_WIDTH), @@ -233,23 +233,23 @@ module _90_internal_mul_to_external (A, B, Y); .Y_WIDTH(Y_WIDTH) ) _TECHMAP_REPLACE_ ( .A(A), - .B({1'b0, B}), + .B({1'b0,B}), .Y(Y) ); else if (!A_SIGNED && B_SIGNED) - \$mul #( + \$__soft_mul #( .A_SIGNED(1), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH+1), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH) ) _TECHMAP_REPLACE_ ( - .A({1'b0, A}), + .A({1'b0,A}), .B(B), .Y(Y) ); else - \$mul #( + \$__soft_mul #( .A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 77bd0ac81..fcb177491 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -268,6 +268,7 @@ struct SynthIce40Pass : public ScriptPass if (help_mode || dsp) { run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 -D DSP_MINWIDTH=11 -D DSP_NAME=$__MUL16X16", "(if -dsp)"); run("ice40_dsp", "(if -dsp)"); + run("chtype -set $mul t:$__soft_mul"); } run("alumacc"); run("opt"); -- cgit v1.2.3 From 3a7aeb028d7680a73c18ec700939cca76aab0433 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 22 Jul 2019 13:01:26 -0700 Subject: Use minimum sized width wires --- techlibs/common/mul2dsp.v | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) (limited to 'techlibs') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 8b1ddefbf..cf9eeff6f 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -88,12 +88,15 @@ module \$__mul (A, B, Y); else if (A_WIDTH > `DSP_A_MAXWIDTH) begin localparam n = (A_WIDTH+`DSP_A_MAXWIDTH-sign_headroom-1) / (`DSP_A_MAXWIDTH-sign_headroom); localparam partial_Y_WIDTH = `MIN(Y_WIDTH, B_WIDTH+`DSP_A_MAXWIDTH); + localparam last_Y_WIDTH = `MIN(partial_Y_WIDTH, B_WIDTH+A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom)); if (A_SIGNED && B_SIGNED) begin - wire signed [partial_Y_WIDTH-1:0] partial [n-1:0]; + wire signed [partial_Y_WIDTH-1:0] partial [n-2:0]; + wire signed [last_Y_WIDTH-1:0] last_partial; wire signed [Y_WIDTH-1:0] partial_sum [n-1:0]; end else begin wire [partial_Y_WIDTH-1:0] partial [n-1:0]; + wire [last_Y_WIDTH-1:0] last_partial; wire [Y_WIDTH-1:0] partial_sum [n-1:0]; end @@ -130,24 +133,27 @@ module \$__mul (A, B, Y); .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom)), .B_WIDTH(B_WIDTH), - .Y_WIDTH(partial_Y_WIDTH) + .Y_WIDTH(last_Y_WIDTH) ) mul_slice_last ( .A(A[A_WIDTH-1 : (n-1)*(`DSP_A_MAXWIDTH-sign_headroom)]), .B(B), - .Y(partial[n-1]) + .Y(last_partial) ); - assign partial_sum[n-1] = (partial[n-1] << (n-1)*(`DSP_A_MAXWIDTH-sign_headroom)) + partial_sum[n-2]; + assign partial_sum[n-1] = (last_partial << (n-1)*(`DSP_A_MAXWIDTH-sign_headroom)) + partial_sum[n-2]; assign Y = partial_sum[n-1]; end else if (B_WIDTH > `DSP_B_MAXWIDTH) begin localparam n = (B_WIDTH+`DSP_B_MAXWIDTH-sign_headroom-1) / (`DSP_B_MAXWIDTH-sign_headroom); localparam partial_Y_WIDTH = `MIN(Y_WIDTH, A_WIDTH+`DSP_B_MAXWIDTH); + localparam last_Y_WIDTH = `MIN(partial_Y_WIDTH, A_WIDTH+B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH-sign_headroom)); if (A_SIGNED && B_SIGNED) begin - wire signed [partial_Y_WIDTH-1:0] partial [n-1:0]; + wire signed [partial_Y_WIDTH-1:0] partial [n-2:0]; + wire signed [last_Y_WIDTH-1:0] last_partial; wire signed [Y_WIDTH-1:0] partial_sum [n-1:0]; end else begin wire [partial_Y_WIDTH-1:0] partial [n-1:0]; + wire [last_Y_WIDTH-1:0] last_partial; wire [Y_WIDTH-1:0] partial_sum [n-1:0]; end @@ -188,9 +194,9 @@ module \$__mul (A, B, Y); ) mul_last ( .A(A), .B(B[B_WIDTH-1 : (n-1)*(`DSP_B_MAXWIDTH-sign_headroom)]), - .Y(partial[n-1]) + .Y(last_partial) ); - assign partial_sum[n-1] = (partial[n-1] << (n-1)*(`DSP_B_MAXWIDTH-sign_headroom)) + partial_sum[n-2]; + assign partial_sum[n-1] = (last_partial << (n-1)*(`DSP_B_MAXWIDTH-sign_headroom)) + partial_sum[n-2]; assign Y = partial_sum[n-1]; end else begin -- cgit v1.2.3 From 5e70b8a22bf38e622943b0546255befd539fa884 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 22 Jul 2019 13:48:33 -0700 Subject: opt and wreduce necessary for -dsp --- techlibs/ice40/synth_ice40.cc | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'techlibs') diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index fcb177491..ce88a0542 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -267,8 +267,10 @@ struct SynthIce40Pass : public ScriptPass run("opt_clean"); if (help_mode || dsp) { run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 -D DSP_MINWIDTH=11 -D DSP_NAME=$__MUL16X16", "(if -dsp)"); - run("ice40_dsp", "(if -dsp)"); - run("chtype -set $mul t:$__soft_mul"); + run("opt_expr", " (if -dsp)"); + run("wreduce", " (if -dsp)"); + run("ice40_dsp", " (if -dsp)"); + run("chtype -set $mul t:$__soft_mul","(if -dsp)"); } run("alumacc"); run("opt"); -- cgit v1.2.3 From 4d71ab384d640f53435d2e4773b2277f385cda27 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 22 Jul 2019 15:08:26 -0700 Subject: Rename according to vendor doc TN1295 --- techlibs/ice40/synth_ice40.cc | 1 + 1 file changed, 1 insertion(+) (limited to 'techlibs') diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index ce88a0542..50e071a1a 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -271,6 +271,7 @@ struct SynthIce40Pass : public ScriptPass run("wreduce", " (if -dsp)"); run("ice40_dsp", " (if -dsp)"); run("chtype -set $mul t:$__soft_mul","(if -dsp)"); + run("dump A:top"); } run("alumacc"); run("opt"); -- cgit v1.2.3 From cb505c50d3572a0622110b31b950b43cffc995db Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 22 Jul 2019 16:14:15 -0700 Subject: Remove debug --- techlibs/ice40/synth_ice40.cc | 1 - 1 file changed, 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 50e071a1a..ce88a0542 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -271,7 +271,6 @@ struct SynthIce40Pass : public ScriptPass run("wreduce", " (if -dsp)"); run("ice40_dsp", " (if -dsp)"); run("chtype -set $mul t:$__soft_mul","(if -dsp)"); - run("dump A:top"); } run("alumacc"); run("opt"); -- cgit v1.2.3 From 151c5c96c0a85a1b69fc7824949ed89d70667059 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 23 Jul 2019 15:05:20 -0700 Subject: Typo for Y_WIDTH --- techlibs/common/mul2dsp.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index cf9eeff6f..06ae3fc04 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -190,7 +190,7 @@ module \$__mul (A, B, Y); .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH-sign_headroom)), - .Y_WIDTH(partial_Y_WIDTH) + .Y_WIDTH(last_Y_WIDTH) ) mul_last ( .A(A), .B(B[B_WIDTH-1 : (n-1)*(`DSP_B_MAXWIDTH-sign_headroom)]), -- cgit v1.2.3 From c39ccc65e9ba79aafa6ebd5c3abe9faf7d465a8f Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 24 Jul 2019 10:49:09 -0700 Subject: Add copyright header, comment on cascade --- techlibs/common/mul2dsp.v | 38 ++++++++++++++++++++++++++++++++++---- 1 file changed, 34 insertions(+), 4 deletions(-) (limited to 'techlibs') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 06ae3fc04..a8c2dcccc 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -1,7 +1,31 @@ -// From Eddie Hung -// extracted from: https://github.com/eddiehung/vtr-with-yosys/blob/vtr7-with-yosys/vtr_flow/misc/yosys_models.v#L220 -// revised by Andre DeHon -// further revised by David Shah +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * 2019 Eddie Hung + * 2019 David Shah + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * --- + * + * Tech-mapping rules for decomposing arbitrarily-sized $mul cells + * into an equivalent collection of smaller `DSP_NAME cells (with the + * same interface as $mul) no larger than `DSP_[AB]_MAXWIDTH, attached + * to $shl and $add cells. + * + */ + `ifndef DSP_A_MAXWIDTH $error("Macro DSP_A_MAXWIDTH must be defined"); `endif @@ -125,6 +149,9 @@ module \$__mul (A, B, Y); .B(B), .Y(partial[i]) ); + // TODO: Currently a 'cascade' approach to summing the partial + // products is taken here, but a more efficient 'binary + // reduction' approach also exists... assign partial_sum[i] = (partial[i] << i*(`DSP_A_MAXWIDTH-sign_headroom)) + partial_sum[i-1]; end @@ -182,6 +209,9 @@ module \$__mul (A, B, Y); .B({{sign_headroom{1'b0}}, B[i*(`DSP_B_MAXWIDTH-sign_headroom) +: `DSP_B_MAXWIDTH-sign_headroom]}), .Y(partial[i]) ); + // TODO: Currently a 'cascade' approach to summing the partial + // products is taken here, but a more efficient 'binary + // reduction' approach also exists... assign partial_sum[i] = (partial[i] << i*(`DSP_B_MAXWIDTH-sign_headroom)) + partial_sum[i-1]; end -- cgit v1.2.3 From 2f71c2c2198b05e216524feb94b66d14c9c433c0 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 26 Jul 2019 15:30:51 -0700 Subject: Fix spacing --- techlibs/common/mul2dsp.v | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'techlibs') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index a8c2dcccc..678de3796 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -149,9 +149,9 @@ module \$__mul (A, B, Y); .B(B), .Y(partial[i]) ); - // TODO: Currently a 'cascade' approach to summing the partial - // products is taken here, but a more efficient 'binary - // reduction' approach also exists... + // TODO: Currently a 'cascade' approach to summing the partial + // products is taken here, but a more efficient 'binary + // reduction' approach also exists... assign partial_sum[i] = (partial[i] << i*(`DSP_A_MAXWIDTH-sign_headroom)) + partial_sum[i-1]; end -- cgit v1.2.3 From 60c4887d15f89499d351fe9bd9ed36a5a4c1fe37 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 31 Jul 2019 15:45:41 -0700 Subject: For signed multipliers, compute sign bit separately... --- techlibs/common/mul2dsp.v | 65 ++++++++++++++++++++++++++++++----------------- 1 file changed, 42 insertions(+), 23 deletions(-) (limited to 'techlibs') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 678de3796..b745547a8 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -54,8 +54,22 @@ module \$mul (A, B, Y); generate if (A_SIGNED != B_SIGNED || A_WIDTH <= 1 || B_WIDTH <= 1) wire _TECHMAP_FAIL_ = 1; - // NB: A_SIGNED == B_SIGNED == 0 from here - else if (A_WIDTH >= B_WIDTH) + // NB: A_SIGNED == B_SIGNED from here + else if (A_WIDTH < B_WIDTH) + \$mul #( + .A_SIGNED(B_SIGNED), + .B_SIGNED(A_SIGNED), + .A_WIDTH(B_WIDTH), + .B_WIDTH(A_WIDTH), + .Y_WIDTH(Y_WIDTH) + ) _TECHMAP_REPLACE_ ( + .A(B), + .B(A), + .Y(Y) + ); + else if (A_SIGNED && (A_WIDTH > `DSP_A_MAXWIDTH || B_WIDTH > `DSP_B_MAXWIDTH)) begin + wire _; + assign Y[Y_WIDTH-1] = A[A_WIDTH-1] ^ B[B_WIDTH-1]; \$__mul #( .A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), @@ -65,18 +79,19 @@ module \$mul (A, B, Y); ) _TECHMAP_REPLACE_ ( .A(A), .B(B), - .Y(Y) + .Y({_,Y[Y_WIDTH-2:0]}) ); + end else \$__mul #( - .A_SIGNED(B_SIGNED), - .B_SIGNED(A_SIGNED), - .A_WIDTH(B_WIDTH), - .B_WIDTH(A_WIDTH), + .A_SIGNED(A_SIGNED), + .B_SIGNED(B_SIGNED), + .A_WIDTH(A_WIDTH), + .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH) ) _TECHMAP_REPLACE_ ( - .A(B), - .B(A), + .A(A), + .B(B), .Y(Y) ); endgenerate @@ -209,23 +224,27 @@ module \$__mul (A, B, Y); .B({{sign_headroom{1'b0}}, B[i*(`DSP_B_MAXWIDTH-sign_headroom) +: `DSP_B_MAXWIDTH-sign_headroom]}), .Y(partial[i]) ); - // TODO: Currently a 'cascade' approach to summing the partial - // products is taken here, but a more efficient 'binary - // reduction' approach also exists... + // TODO: Currently a 'cascade' approach to summing the partial + // products is taken here, but a more efficient 'binary + // reduction' approach also exists... assign partial_sum[i] = (partial[i] << i*(`DSP_B_MAXWIDTH-sign_headroom)) + partial_sum[i-1]; end - \$__mul #( - .A_SIGNED(A_SIGNED), - .B_SIGNED(B_SIGNED), - .A_WIDTH(A_WIDTH), - .B_WIDTH(B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH-sign_headroom)), - .Y_WIDTH(last_Y_WIDTH) - ) mul_last ( - .A(A), - .B(B[B_WIDTH-1 : (n-1)*(`DSP_B_MAXWIDTH-sign_headroom)]), - .Y(last_partial) - ); + localparam last_B_WIDTH = B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH-sign_headroom); + if (A_SIGNED && B_SIGNED && last_B_WIDTH == 1) + assign last_partial = 0; + else + \$__mul #( + .A_SIGNED(A_SIGNED), + .B_SIGNED(B_SIGNED), + .A_WIDTH(A_WIDTH), + .B_WIDTH(last_B_WIDTH), + .Y_WIDTH(last_Y_WIDTH) + ) mul_last ( + .A(A), + .B(B[B_WIDTH-1 -: last_B_WIDTH]), + .Y(last_partial) + ); assign partial_sum[n-1] = (last_partial << (n-1)*(`DSP_B_MAXWIDTH-sign_headroom)) + partial_sum[n-2]; assign Y = partial_sum[n-1]; end -- cgit v1.2.3 From d2c33863d08bbc506888b723a304aa11f8650296 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 31 Jul 2019 16:04:19 -0700 Subject: Do not compute sign bit if result is zero --- techlibs/common/mul2dsp.v | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index b745547a8..bfd216fbf 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -69,7 +69,6 @@ module \$mul (A, B, Y); ); else if (A_SIGNED && (A_WIDTH > `DSP_A_MAXWIDTH || B_WIDTH > `DSP_B_MAXWIDTH)) begin wire _; - assign Y[Y_WIDTH-1] = A[A_WIDTH-1] ^ B[B_WIDTH-1]; \$__mul #( .A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), @@ -81,6 +80,8 @@ module \$mul (A, B, Y); .B(B), .Y({_,Y[Y_WIDTH-2:0]}) ); + // For non-zero results, recompute sign bit + assign Y[Y_WIDTH-1] = (|Y[Y_WIDTH-2:0]) & (A[A_WIDTH-1] ^ B[B_WIDTH-1]); end else \$__mul #( -- cgit v1.2.3 From 7e86c8bcfb10f6a819273ad8bd10fa461987f2f1 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 1 Aug 2019 10:01:43 -0700 Subject: Fix B_WIDTH > DSP_B_MAXWIDTH case --- techlibs/common/mul2dsp.v | 46 ++++++++++++++-------------------------------- 1 file changed, 14 insertions(+), 32 deletions(-) (limited to 'techlibs') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index bfd216fbf..b28a4247e 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -67,22 +67,6 @@ module \$mul (A, B, Y); .B(A), .Y(Y) ); - else if (A_SIGNED && (A_WIDTH > `DSP_A_MAXWIDTH || B_WIDTH > `DSP_B_MAXWIDTH)) begin - wire _; - \$__mul #( - .A_SIGNED(A_SIGNED), - .B_SIGNED(B_SIGNED), - .A_WIDTH(A_WIDTH), - .B_WIDTH(B_WIDTH), - .Y_WIDTH(Y_WIDTH) - ) _TECHMAP_REPLACE_ ( - .A(A), - .B(B), - .Y({_,Y[Y_WIDTH-2:0]}) - ); - // For non-zero results, recompute sign bit - assign Y[Y_WIDTH-1] = (|Y[Y_WIDTH-2:0]) & (A[A_WIDTH-1] ^ B[B_WIDTH-1]); - end else \$__mul #( .A_SIGNED(A_SIGNED), @@ -171,14 +155,15 @@ module \$__mul (A, B, Y); assign partial_sum[i] = (partial[i] << i*(`DSP_A_MAXWIDTH-sign_headroom)) + partial_sum[i-1]; end + localparam last_A_WIDTH = A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom); \$__mul #( .A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), - .A_WIDTH(A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom)), + .A_WIDTH(last_A_WIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(last_Y_WIDTH) ) mul_slice_last ( - .A(A[A_WIDTH-1 : (n-1)*(`DSP_A_MAXWIDTH-sign_headroom)]), + .A(A[A_WIDTH-1 -: last_A_WIDTH]), .B(B), .Y(last_partial) ); @@ -232,20 +217,17 @@ module \$__mul (A, B, Y); end localparam last_B_WIDTH = B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH-sign_headroom); - if (A_SIGNED && B_SIGNED && last_B_WIDTH == 1) - assign last_partial = 0; - else - \$__mul #( - .A_SIGNED(A_SIGNED), - .B_SIGNED(B_SIGNED), - .A_WIDTH(A_WIDTH), - .B_WIDTH(last_B_WIDTH), - .Y_WIDTH(last_Y_WIDTH) - ) mul_last ( - .A(A), - .B(B[B_WIDTH-1 -: last_B_WIDTH]), - .Y(last_partial) - ); + \$__mul #( + .A_SIGNED(A_SIGNED), + .B_SIGNED(B_SIGNED), + .A_WIDTH(A_WIDTH), + .B_WIDTH(last_B_WIDTH), + .Y_WIDTH(last_Y_WIDTH) + ) mul_last ( + .A(A), + .B(B[B_WIDTH-1 -: last_B_WIDTH]), + .Y(last_partial) + ); assign partial_sum[n-1] = (last_partial << (n-1)*(`DSP_B_MAXWIDTH-sign_headroom)) + partial_sum[n-2]; assign Y = partial_sum[n-1]; end -- cgit v1.2.3 From 332b86491de4d033f2fe259ab7ad7d02761cc515 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 1 Aug 2019 12:17:14 -0700 Subject: Revert "Do not do sign extension in techmap; let packer do it" This reverts commit 595a8f032f1e9db385959f92a4a414a40de291fd. --- techlibs/common/mul2dsp.v | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) (limited to 'techlibs') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index b28a4247e..99afce18c 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -232,15 +232,24 @@ module \$__mul (A, B, Y); assign Y = partial_sum[n-1]; end else begin + if (A_SIGNED) + wire signed [`DSP_A_MAXWIDTH-1:0] Aext = $signed(A); + else + wire [`DSP_A_MAXWIDTH-1:0] Aext = A; + if (B_SIGNED) + wire signed [`DSP_B_MAXWIDTH-1:0] Bext = $signed(B); + else + wire [`DSP_B_MAXWIDTH-1:0] Bext = B; + `DSP_NAME #( .A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), - .A_WIDTH(A_WIDTH), - .B_WIDTH(B_WIDTH), - .Y_WIDTH(`MIN(Y_WIDTH,A_WIDTH+B_WIDTH)), + .A_WIDTH(`DSP_A_MAXWIDTH), + .B_WIDTH(`DSP_B_MAXWIDTH), + .Y_WIDTH(`MIN(Y_WIDTH,`DSP_A_MAXWIDTH+`DSP_B_MAXWIDTH)), ) _TECHMAP_REPLACE_ ( - .A(A), - .B(B), + .A(Aext), + .B(Bext), .Y(Y) ); end -- cgit v1.2.3 From fc0b5d5ab6bcbb6cc5fcacab479504c08ab80d23 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 1 Aug 2019 12:45:14 -0700 Subject: Change $__softmul back to $mul --- techlibs/xilinx/synth_xilinx.cc | 1 + 1 file changed, 1 insertion(+) (limited to 'techlibs') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index e5a27015a..a787c7c4c 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -334,6 +334,7 @@ struct SynthXilinxPass : public ScriptPass if (help_mode || !nodsp) { run("techmap -map +/xilinx/dsp_map.v", "(skip if '-nodsp')"); run("xilinx_dsp", " (skip if '-nodsp')"); + run("chtype -set $mul t:$__soft_mul"," (skip if '-nodsp')"); } if (help_mode) { run("simplemap t:$mux", " ('-widemux' only)"); -- cgit v1.2.3 From 915f4e34bfdf1fd2b9f97d1c15a55e2c4c49f428 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 1 Aug 2019 13:20:34 -0700 Subject: DSP_MINWIDTH -> DSP_{A,B,Y}_MINWIDTH --- techlibs/common/mul2dsp.v | 15 +++++++++++---- techlibs/ice40/synth_ice40.cc | 2 +- 2 files changed, 12 insertions(+), 5 deletions(-) (limited to 'techlibs') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 99afce18c..5ff0e03aa 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -52,7 +52,7 @@ module \$mul (A, B, Y); output [Y_WIDTH-1:0] Y; generate - if (A_SIGNED != B_SIGNED || A_WIDTH <= 1 || B_WIDTH <= 1) + if (A_SIGNED != B_SIGNED) wire _TECHMAP_FAIL_ = 1; // NB: A_SIGNED == B_SIGNED from here else if (A_WIDTH < B_WIDTH) @@ -103,10 +103,17 @@ module \$__mul (A, B, Y); genvar i; generate - if (A_WIDTH <= 1 || B_WIDTH <= 1) + if (0) begin end +`ifdef DSP_A_MINWIDTH + else if (A_WIDTH < `DSP_A_MINWIDTH) wire _TECHMAP_FAIL_ = 1; -`ifdef DSP_MINWIDTH - else if (A_WIDTH+B_WIDTH < `DSP_MINWIDTH || Y_WIDTH < `DSP_MINWIDTH) +`endif +`ifdef DSP_B_MINWIDTH + else if (B_WIDTH < `DSP_B_MINWIDTH) + wire _TECHMAP_FAIL_ = 1; +`endif +`ifdef DSP_Y_MINWIDTH + else if (Y_WIDTH < `DSP_Y_MINWIDTH) wire _TECHMAP_FAIL_ = 1; `endif else if (A_WIDTH > `DSP_A_MAXWIDTH) begin diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index ce88a0542..2cc5fd5fd 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -266,7 +266,7 @@ struct SynthIce40Pass : public ScriptPass run("opt_expr"); run("opt_clean"); if (help_mode || dsp) { - run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 -D DSP_MINWIDTH=11 -D DSP_NAME=$__MUL16X16", "(if -dsp)"); + run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 -D DSP_NAME=$__MUL16X16", "(if -dsp)"); run("opt_expr", " (if -dsp)"); run("wreduce", " (if -dsp)"); run("ice40_dsp", " (if -dsp)"); -- cgit v1.2.3 From 65de9aaaa9d744686e235ff8701cd997cd2dc891 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 1 Aug 2019 14:29:00 -0700 Subject: Add DSP_SIGNEDONLY back --- techlibs/common/mul2dsp.v | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'techlibs') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 5ff0e03aa..6cd5128a6 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -55,6 +55,22 @@ module \$mul (A, B, Y); if (A_SIGNED != B_SIGNED) wire _TECHMAP_FAIL_ = 1; // NB: A_SIGNED == B_SIGNED from here +`ifdef DSP_SIGNEDONLY + else if (!A_SIGNED) begin + wire [1:0] _; + \$mul #( + .A_SIGNED(1), + .B_SIGNED(1), + .A_WIDTH(A_WIDTH + 1), + .B_WIDTH(B_WIDTH + 1), + .Y_WIDTH(Y_WIDTH + 2) + ) _TECHMAP_REPLACE_ ( + .A({1'b0, A}), + .B({1'b0, B}), + .Y({_, Y}) + ); + end +`endif else if (A_WIDTH < B_WIDTH) \$mul #( .A_SIGNED(B_SIGNED), -- cgit v1.2.3 From 105aaeaf598a04020fa5030c947f623f0daa38da Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 1 Aug 2019 14:33:16 -0700 Subject: Trim Y_WIDTH --- techlibs/common/mul2dsp.v | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) (limited to 'techlibs') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 6cd5128a6..8e37201e2 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -56,20 +56,18 @@ module \$mul (A, B, Y); wire _TECHMAP_FAIL_ = 1; // NB: A_SIGNED == B_SIGNED from here `ifdef DSP_SIGNEDONLY - else if (!A_SIGNED) begin - wire [1:0] _; + else if (!A_SIGNED) \$mul #( .A_SIGNED(1), .B_SIGNED(1), .A_WIDTH(A_WIDTH + 1), .B_WIDTH(B_WIDTH + 1), - .Y_WIDTH(Y_WIDTH + 2) + .Y_WIDTH(Y_WIDTH) ) _TECHMAP_REPLACE_ ( .A({1'b0, A}), .B({1'b0, B}), - .Y({_, Y}) + .Y(Y) ); - end `endif else if (A_WIDTH < B_WIDTH) \$mul #( -- cgit v1.2.3 From 7a563d0b92b3b5c837fca9647a43a01e258072a5 Mon Sep 17 00:00:00 2001 From: David Shah Date: Tue, 6 Aug 2019 13:23:42 +0100 Subject: [wip] DSP48E1 sim model improvements Signed-off-by: David Shah --- techlibs/xilinx/cells_sim.v | 83 ++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 75 insertions(+), 8 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 33b2a8f62..9437a057b 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -494,14 +494,81 @@ module DSP48E1 ( `endif end - reg signed [29:0] Ar; - reg signed [17:0] Br; + reg signed [29:0] Ar1, Ar2; + reg signed [24:0] Dr; + reg signed [17:0] Br1, Br2; reg signed [47:0] Pr; + reg [4:0] INMODEr; generate - if (AREG == 1) begin always @(posedge CLK) if (CEA2) Ar <= A; end - else always @* Ar <= A; - if (BREG == 1) begin always @(posedge CLK) if (CEB2) Br <= B; end - else always @* Br <= B; + if (AREG == 2) begin + always @(posedge CLK) + if (RSTA) begin + Ar1 <= 30'b0; + Ar2 <= 30'b0; + end else begin + if (CEA1) Ar1 <= A; + if (CEA2) Ar2 <= Ar1; + end + end else if (AREG == 1) begin + always @(posedge CLK) + if (RSTA) begin + Ar1 <= 30'b0; + Ar2 <= 30'b0; + end else begin + if (CEA1) Ar1 <= A; + if (CEA2) Ar2 <= A; + end + end else begin + always @* Ar1 <= A; + always @* Ar2 <= A; + end + + if (BREG == 2) begin + always @(posedge CLK) + if (RSTB) begin + Br1 <= 18'b0; + Br2 <= 18'b0; + end else begin + if (CEB1) Br1 <= B; + if (CEB2) Br2 <= Br1; + end + end else if (AREG == 1) begin + always @(posedge CLK) + if (RSTB) begin + Br1 <= 18'b0; + Br2 <= 18'b0; + end else begin + if (CEB1) Br1 <= B; + if (CEB2) Br2 <= B; + end + end else begin + always @* Br1 <= B; + always @* Br2 <= B; + end + + if (DREG == 1) begin always @(posedge CLK) if (RSTD) Dr <= 25'b0; else if (CED) Dr <= D; end + else always @* Dr <= D; + + if (INMODEREG == 1) begin always @(posedge CLK) if (RSTINMODE) INMODEr <= 5'b0; else if (CEINMODE) INMODEr <= INMODE; end + else always @* INMODEr <= INMODE; + endgenerate + + wire signed [29:0] Ar12_muxed = INMODEr[0] ? Ar1 : Ar2; + wire signed [24:0] Ar12_gated = INMODEr[1] ? 25'b0 : Ar12_muxed; + wire signed [24:0] Dr_gated = INMODEr[2] ? Dr : 25'b0; + wire signed [24:0] AD_result = INMODEr[3] ? (Dr_gated - Ar12_gated) : (Dr_gated + Ar12_gated); + reg signed [24:0] ADr; + + generate + if (ADREG == 1) begin always @(posedge CLK) if (RSTD) ADr <= 25'b0; else if (CEAD) ADr <= AD_result; end + else always @* ADr <= AD_result; + endgenerate + + wire signed [24:0] A_MULT; + wire signed [24:0] B_MULT = INMODEr[4] ? Br1 : Br2; + generate + if (USE_DPORT == "TRUE") assign A_MULT = ADr; + else assign A_MULT = Ar12_gated; endgenerate always @* begin @@ -516,11 +583,11 @@ module DSP48E1 ( if (PCIN != 48'b0) $fatal(1, "Unsupported PCIN value"); if (CARRYIN != 1'b0) $fatal(1, "Unsupported CARRYIN value"); `endif - Pr[42:0] <= $signed(Ar[24:0]) * Br; + Pr[42:0] <= A_MULT * B_MULT; end generate - if (PREG == 1) begin always @(posedge CLK) if (CEP) P <= Pr; end + if (PREG == 1) begin always @(posedge CLK) if (RSTP) P <= 48'b0; else if (CEP) P <= Pr; end else always @* P <= Pr; endgenerate -- cgit v1.2.3 From c43b0c4b49235da5aee658413a2a6f880aff09b0 Mon Sep 17 00:00:00 2001 From: David Shah Date: Tue, 6 Aug 2019 18:47:18 +0100 Subject: [wip] DSP48E1 sim model improvements Signed-off-by: David Shah --- techlibs/xilinx/cells_sim.v | 143 +++++++++++++++++++++++++++++++++++++------- 1 file changed, 120 insertions(+), 23 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 9437a057b..bc8a2d8f0 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -494,19 +494,35 @@ module DSP48E1 ( `endif end + wire signed [29:0] A_muxed; + wire signed [17:0] B_muxed; + + generate + if (A_INPUT == "CASCADE") assign A_muxed = ACIN; + else assign A_muxed = A; + + if (B_INPUT == "CASCADE") assign B_muxed = BCIN; + else assign B_muxed = B; + endgenerate + reg signed [29:0] Ar1, Ar2; reg signed [24:0] Dr; reg signed [17:0] Br1, Br2; - reg signed [47:0] Pr; + reg signed [47:0] Cr; reg [4:0] INMODEr; + reg [6:0] OPMODEr; + reg [3:0] ALUMODEr; + reg [2:0] CARRYINSELr; + generate + // Configurable A register if (AREG == 2) begin always @(posedge CLK) if (RSTA) begin Ar1 <= 30'b0; Ar2 <= 30'b0; end else begin - if (CEA1) Ar1 <= A; + if (CEA1) Ar1 <= A_muxed; if (CEA2) Ar2 <= Ar1; end end else if (AREG == 1) begin @@ -515,21 +531,22 @@ module DSP48E1 ( Ar1 <= 30'b0; Ar2 <= 30'b0; end else begin - if (CEA1) Ar1 <= A; - if (CEA2) Ar2 <= A; + if (CEA1) Ar1 <= A_muxed; + if (CEA2) Ar2 <= A_muxed; end end else begin - always @* Ar1 <= A; - always @* Ar2 <= A; + always @* Ar1 <= A_muxed; + always @* Ar2 <= A_muxed; end + // Configurable A register if (BREG == 2) begin always @(posedge CLK) if (RSTB) begin Br1 <= 18'b0; Br2 <= 18'b0; end else begin - if (CEB1) Br1 <= B; + if (CEB1) Br1 <= B_muxed; if (CEB2) Br2 <= Br1; end end else if (AREG == 1) begin @@ -538,21 +555,41 @@ module DSP48E1 ( Br1 <= 18'b0; Br2 <= 18'b0; end else begin - if (CEB1) Br1 <= B; - if (CEB2) Br2 <= B; + if (CEB1) Br1 <= B_muxed; + if (CEB2) Br2 <= B_muxed; end end else begin - always @* Br1 <= B; - always @* Br2 <= B; + always @* Br1 <= B_muxed; + always @* Br2 <= B_muxed; end + // C and D registers + if (CREG == 1) begin always @(posedge CLK) if (RSTC) Cr <= 48'b0; else if (CEC) Cr <= D; end + else always @* Cr <= C; + if (DREG == 1) begin always @(posedge CLK) if (RSTD) Dr <= 25'b0; else if (CED) Dr <= D; end else always @* Dr <= D; + // Control registers if (INMODEREG == 1) begin always @(posedge CLK) if (RSTINMODE) INMODEr <= 5'b0; else if (CEINMODE) INMODEr <= INMODE; end else always @* INMODEr <= INMODE; + if (OPMODEREG == 1) begin always @(posedge CLK) if (RSTCTRL) OPMODEr <= 7'b0; else if (CECTRL) OPMODEr <= OPMODE; end + else always @* OPMODEr <= OPMODE; + if (ALUMODEREG == 1) begin always @(posedge CLK) if (RSTALUMODE) ALUMODEr <= 4'b0; else if (CEALUMODE) ALUMODEr <= ALUMODE; end + else always @* ALUMODEr <= ALUMODE; + if (CARRYINSELREG == 1) begin always @(posedge CLK) if (RSTCTRL) CARRYINSELr <= 3'b0; else if (CECTRL) CARRYINSELr <= CARRYINSEL; end + else always @* CARRYINSELr <= CARRYINSEL; + endgenerate + + // A and B cascsde + generate + if (ACASCREG == 1 && AREG == 2) assign ACOUT = Ar1; + else assign ACOUT = Ar2; + if (BCASCREG == 1 && BREG == 2) assign BCOUT = Br1; + else assign BCOUT = Br2; endgenerate + // A/D input selection and pre-adder wire signed [29:0] Ar12_muxed = INMODEr[0] ? Ar1 : Ar2; wire signed [24:0] Ar12_gated = INMODEr[1] ? 25'b0 : Ar12_muxed; wire signed [24:0] Dr_gated = INMODEr[2] ? Dr : 25'b0; @@ -564,31 +601,91 @@ module DSP48E1 ( else always @* ADr <= AD_result; endgenerate + // 25x18 multiplier wire signed [24:0] A_MULT; - wire signed [24:0] B_MULT = INMODEr[4] ? Br1 : Br2; + wire signed [17:0] B_MULT = INMODEr[4] ? Br1 : Br2; generate if (USE_DPORT == "TRUE") assign A_MULT = ADr; else assign A_MULT = Ar12_gated; endgenerate + wire signed [42:0] M = A_MULT * B_MULT; + reg signed [42:0] Mr; + + // Multiplier result register + generate + if (MREG == 1) begin always @(posedge CLK) if (RSTM) Mr <= 43'b0; else if (CEM) Mr <= M; end + else always @* Mr <= M; + endgenerate + + // X, Y and Z ALU inputs + reg signed [47:0] X, Y, Z; + + always @* begin + // X multiplexer + case (OPMODEr[1:0]) + 2'b00: X = 48'b0; + 2'b01: X = $signed(M); +`ifdef __ICARUS__ + if (OPMODEr[3:2] != 2'b01) $fatal(1, "OPMODEr[3:2] must be 2'b01 when OPMODEr[1:0] is 2'b01"); +`endif + 2'b10: X = P; +`ifdef __ICARUS__ + if (PREG != 1) $fatal(1, "PREG must be 1 when OPMODEr[1:0] is 2'b10"); +`endif + 2'b11: X = $signed({Ar2, Br2}); + default: X = 48'bx; + endcase + + // Y multiplexer + case (OPMODEr[3:2]) + 2'b00: Y = 48'b0; + 2'b01: Y = 48'b0; // FIXME: more accurate partial product modelling? +`ifdef __ICARUS__ + if (OPMODEr[1:0] != 2'b01) $fatal(1, "OPMODEr[1:0] must be 2'b01 when OPMODEr[3:2] is 2'b01"); +`endif + 2'b10: Y = {48{1'b1}}; + 2'b11: Y = C; + default: Y = 48'bx; + endcase + + // Z multiplexer + case (OPMODEr[6:4]) + 3'b000: Z = 48'b0; + 3'b001: Z = PCIN; + 3'b010: Z = P; +`ifdef __ICARUS__ + if (PREG != 1) $fatal(1, "PREG must be 1 when OPMODEr[6:4] i0s 3'b010"); +`endif + 3'b011: Z = C; + 3'b100: Z = P; +`ifdef __ICARUS__ + if (PREG != 1) $fatal(1, "PREG must be 1 when OPMODEr[6:4] is 3'b100"); + if (OPMODEr[3:0] != 4'b1000) $fatal(1, "OPMODEr[3:0] must be 4'b1000 when OPMODEr[6:4] i0s 3'b100"); +`endif + 3'b101: Z = $signed(PCIN[47:17]); + 3'b110: Z = $signed(P[47:17]); + default: Z = 48'bx; + endcase + end + + wire alu_cin = 1'b0; // FIXME* + + wire [47:0] Z_muxinv = ALUMODEr[0] ? ~Z : Z; + wire [47:0] xor_xyz = X ^ Y ^ Z_muxinv; + wire [47:0] maj_xyz = (X & Y) | (X & Z) | (X & Y); + + + always @* begin - Pr <= {48{1'bx}}; `ifdef __ICARUS__ - if (INMODE != 4'b0000) $fatal(1, "Unsupported INMODE value"); - if (ALUMODE != 4'b0000) $fatal(1, "Unsupported ALUMODE value"); - if (OPMODE != 7'b000101) $fatal(1, "Unsupported OPMODE value"); if (CARRYINSEL != 3'b000) $fatal(1, "Unsupported CARRYINSEL value"); - if (ACIN != 30'b0) $fatal(1, "Unsupported ACIN value"); - if (BCIN != 18'b0) $fatal(1, "Unsupported BCIN value"); - if (PCIN != 48'b0) $fatal(1, "Unsupported PCIN value"); - if (CARRYIN != 1'b0) $fatal(1, "Unsupported CARRYIN value"); `endif - Pr[42:0] <= A_MULT * B_MULT; end generate - if (PREG == 1) begin always @(posedge CLK) if (RSTP) P <= 48'b0; else if (CEP) P <= Pr; end - else always @* P <= Pr; + if (PREG == 1) begin always @(posedge CLK) if (RSTP) P <= 48'b0; else if (CEP) P <= Mr; end + else always @* P <= Mr; endgenerate endmodule -- cgit v1.2.3 From fe95807f162704d1f9c09ba8d665092c92574cce Mon Sep 17 00:00:00 2001 From: David Shah Date: Wed, 7 Aug 2019 13:09:12 +0100 Subject: [wip] DSP48E1 sim model improvements Signed-off-by: David Shah --- techlibs/xilinx/cells_sim.v | 88 +++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 82 insertions(+), 6 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index bc8a2d8f0..7e7199f0b 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -382,9 +382,9 @@ endmodule module DSP48E1 ( output [29:0] ACOUT, output [17:0] BCOUT, - output CARRYCASCOUT, - output [3:0] CARRYOUT, - output MULTSIGNOUT, + output reg CARRYCASCOUT, + output reg [3:0] CARRYOUT, + output reg MULTSIGNOUT, output OVERFLOW, output reg signed [47:0] P, output PATTERNBDETECT, @@ -669,13 +669,70 @@ module DSP48E1 ( endcase end + // ALU core + wire alu_cin = 1'b0; // FIXME* wire [47:0] Z_muxinv = ALUMODEr[0] ? ~Z : Z; wire [47:0] xor_xyz = X ^ Y ^ Z_muxinv; wire [47:0] maj_xyz = (X & Y) | (X & Z) | (X & Y); - + wire [47:0] xor_xyz_muxed = ALUMODEr[3] ? maj_xyz : xor_xyz; + wire [47:0] maj_xyz_gated = ALUMODEr[2] ? 48'b0 : maj_xyz; + + wire [48:0] maj_xyz_simd_gated; + wire [3:0] int_carry_in, int_carry_out, ext_carry_out; + wire [47:0] alu_sum; + assign int_carry_in[0] = 1'b0; + + generate + if (USE_SIMD == "FOUR12") begin + assign maj_xyz_simd_gated = { + maj_xyz_gated[47:36], + 1'b0, maj_xyz_gated[34:24], + 1'b0, maj_xyz_gated[22:12], + 1'b0, maj_xyz_gated[10:0], + alu_cin + }; + assign int_carry_in[3:1] = 3'b000; + assign ext_carry_out = { + int_carry_out[3], + maj_xyz_gated[35] ^ int_carry_out[2], + maj_xyz_gated[23] ^ int_carry_out[1], + maj_xyz_gated[11] ^ int_carry_out[0] + }; + end else if (USE_SIMD == "TWO24") begin + assign maj_xyz_simd_gated = { + maj_xyz_gated[47:24], + 1'b0, maj_xyz_gated[22:0], + alu_cin + }; + assign int_carry_in[3:1] = {int_carry_out[2], 1'b0, int_carry_out[0]}; + assign ext_carry_out = { + int_carry_out[3], + 1'bx, + maj_xyz_gated[23] ^ int_carry_out[1], + 1'bx + }; + end else if (USE_SIMD == "FOUR48") begin + assign maj_xyz_simd_gated = {maj_xyz_gated, alu_cin}; + assign int_carry_in[3:1] = int_carry_out[2:0]; + assign ext_carry_out = { + int_carry_out[3], + 3'bxxx + }; + end + + genvar i; + for (i = 0; i < 4; i++) + assign {int_carry_out[i], alu_sum[i*12 +: 12]} = {1'b0, maj_xyz_simd_gated[i*12 +: ((i == 3) ? 13 : 12)]} + + xor_xyz_muxed[i*12 +: 12] + int_carry_in[i]; + endgenerate + + wire signed [47:0] Pd = ALUMODEr[1] ? ~alu_sum : alu_sum; + wire [3:0] CARRYOUTd = (ALUMODEr[0] & ALUMODEr[1]) ? ~ext_carry_out : ext_carry_out; + wire CARRYCASCOUTd = ext_carry_out[3]; + wire MULTSIGNOUTd = Mr[42]; always @* begin `ifdef __ICARUS__ @@ -684,8 +741,27 @@ module DSP48E1 ( end generate - if (PREG == 1) begin always @(posedge CLK) if (RSTP) P <= 48'b0; else if (CEP) P <= Mr; end - else always @* P <= Mr; + if (PREG == 1) begin + always @(posedge CLK) + if (RSTP) begin + P <= 48'b0; + CARRYOUT <= 4'b0; + CARRYCASCOUT <= 1'b0; + MULTSIGNOUT <= 1'b0; + end else if (CEP) begin + P <= Pd; + CARRYOUT <= CARRYOUTd; + CARRYCASCOUT <= CARRYCASCOUTd; + MULTSIGNOUT <= MULTSIGNOUTd; + end + end else begin + always @* begin + P = Pd; + CARRYOUT = CARRYOUTd; + CARRYCASCOUT = CARRYCASCOUTd; + MULTSIGNOUT = MULTSIGNOUTd; + end + end endgenerate endmodule -- cgit v1.2.3 From a206aed977e92a63aa52137690e20897f27df458 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 7 Aug 2019 13:59:07 -0700 Subject: Run "opt_expr -fine" instead of "wreduce" due to #1213 --- techlibs/ice40/synth_ice40.cc | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'techlibs') diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 2cc5fd5fd..09759f359 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -267,8 +267,7 @@ struct SynthIce40Pass : public ScriptPass run("opt_clean"); if (help_mode || dsp) { run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 -D DSP_NAME=$__MUL16X16", "(if -dsp)"); - run("opt_expr", " (if -dsp)"); - run("wreduce", " (if -dsp)"); + run("opt_expr -fine", " (if -dsp)"); run("ice40_dsp", " (if -dsp)"); run("chtype -set $mul t:$__soft_mul","(if -dsp)"); } -- cgit v1.2.3 From ccfb4ff2a9d1cdf8205481042b0c22c39fc20e88 Mon Sep 17 00:00:00 2001 From: David Shah Date: Thu, 8 Aug 2019 09:31:34 +0100 Subject: [wip] sim model testing Signed-off-by: David Shah --- techlibs/xilinx/cells_sim.v | 89 +++++----- techlibs/xilinx/tests/.gitignore | 1 + techlibs/xilinx/tests/test_dsp_model.v | 310 +++++++++++++++++++++++++++++++++ 3 files changed, 360 insertions(+), 40 deletions(-) create mode 100644 techlibs/xilinx/tests/test_dsp_model.v (limited to 'techlibs') diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 7e7199f0b..a6ab98926 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -463,27 +463,10 @@ module DSP48E1 ( initial begin `ifdef __ICARUS__ - if (ACASCREG != 0) $fatal(1, "Unsupported ACASCREG value"); - if (ADREG != 0) $fatal(1, "Unsupported ADREG value"); - if (ALUMODEREG != 0) $fatal(1, "Unsupported ALUMODEREG value"); - if (AREG == 2) $fatal(1, "Unsupported AREG value"); if (AUTORESET_PATDET != "NO_RESET") $fatal(1, "Unsupported AUTORESET_PATDET value"); - if (A_INPUT != "DIRECT") $fatal(1, "Unsupported A_INPUT value"); - if (BCASCREG != 0) $fatal(1, "Unsupported BCASCREG value"); - if (BREG == 2) $fatal(1, "Unsupported BREG value"); - if (B_INPUT != "DIRECT") $fatal(1, "Unsupported B_INPUT value"); - if (CARRYINREG != 0) $fatal(1, "Unsupported CARRYINREG value"); - if (CARRYINSELREG != 0) $fatal(1, "Unsupported CARRYINSELREG value"); - if (CREG != 0) $fatal(1, "Unsupported CREG value"); - if (DREG != 0) $fatal(1, "Unsupported DREG value"); - if (INMODEREG != 0) $fatal(1, "Unsupported INMODEREG value"); - if (MREG != 0) $fatal(1, "Unsupported MREG value"); - if (OPMODEREG != 0) $fatal(1, "Unsupported OPMODEREG value"); //if (PREG != 0) $fatal(1, "Unsupported PREG value"); if (SEL_MASK != "MASK") $fatal(1, "Unsupported SEL_MASK value"); if (SEL_PATTERN != "PATTERN") $fatal(1, "Unsupported SEL_PATTERN value"); - if (USE_DPORT != "FALSE") $fatal(1, "Unsupported USE_DPORT value"); - if (USE_MULT != "MULTIPLY") $fatal(1, "Unsupported USE_MULT value"); if (USE_PATTERN_DETECT != "NO_PATDET") $fatal(1, "Unsupported USE_PATTERN_DETECT value"); if (USE_SIMD != "ONE48") $fatal(1, "Unsupported USE_SIMD value"); if (IS_ALUMODE_INVERTED != 4'b0) $fatal(1, "Unsupported IS_ALUMODE_INVERTED value"); @@ -505,14 +488,14 @@ module DSP48E1 ( else assign B_muxed = B; endgenerate - reg signed [29:0] Ar1, Ar2; - reg signed [24:0] Dr; - reg signed [17:0] Br1, Br2; - reg signed [47:0] Cr; - reg [4:0] INMODEr; - reg [6:0] OPMODEr; - reg [3:0] ALUMODEr; - reg [2:0] CARRYINSELr; + reg signed [29:0] Ar1 = 30'b0, Ar2 = 30'b0; + reg signed [24:0] Dr = 25'b0; + reg signed [17:0] Br1 = 18'b0, Br2 = 18'b0; + reg signed [47:0] Cr = 48'b0; + reg [4:0] INMODEr = 5'b0; + reg [6:0] OPMODEr = 7'b0; + reg [3:0] ALUMODEr = 4'b0; + reg [2:0] CARRYINSELr = 3'b0; generate // Configurable A register @@ -594,7 +577,7 @@ module DSP48E1 ( wire signed [24:0] Ar12_gated = INMODEr[1] ? 25'b0 : Ar12_muxed; wire signed [24:0] Dr_gated = INMODEr[2] ? Dr : 25'b0; wire signed [24:0] AD_result = INMODEr[3] ? (Dr_gated - Ar12_gated) : (Dr_gated + Ar12_gated); - reg signed [24:0] ADr; + reg signed [24:0] ADr = 25'b0; generate if (ADREG == 1) begin always @(posedge CLK) if (RSTD) ADr <= 25'b0; else if (CEAD) ADr <= AD_result; end @@ -610,7 +593,7 @@ module DSP48E1 ( endgenerate wire signed [42:0] M = A_MULT * B_MULT; - reg signed [42:0] Mr; + reg signed [42:0] Mr = 43'b0; // Multiplier result register generate @@ -625,14 +608,16 @@ module DSP48E1 ( // X multiplexer case (OPMODEr[1:0]) 2'b00: X = 48'b0; - 2'b01: X = $signed(M); + 2'b01: begin X = $signed(M); `ifdef __ICARUS__ if (OPMODEr[3:2] != 2'b01) $fatal(1, "OPMODEr[3:2] must be 2'b01 when OPMODEr[1:0] is 2'b01"); `endif - 2'b10: X = P; + end + 2'b10: begin X = P; `ifdef __ICARUS__ if (PREG != 1) $fatal(1, "PREG must be 1 when OPMODEr[1:0] is 2'b10"); `endif + end 2'b11: X = $signed({Ar2, Br2}); default: X = 48'bx; endcase @@ -640,10 +625,11 @@ module DSP48E1 ( // Y multiplexer case (OPMODEr[3:2]) 2'b00: Y = 48'b0; - 2'b01: Y = 48'b0; // FIXME: more accurate partial product modelling? + 2'b01: begin Y = 48'b0; // FIXME: more accurate partial product modelling? `ifdef __ICARUS__ if (OPMODEr[1:0] != 2'b01) $fatal(1, "OPMODEr[1:0] must be 2'b01 when OPMODEr[3:2] is 2'b01"); `endif + end 2'b10: Y = {48{1'b1}}; 2'b11: Y = C; default: Y = 48'bx; @@ -653,26 +639,54 @@ module DSP48E1 ( case (OPMODEr[6:4]) 3'b000: Z = 48'b0; 3'b001: Z = PCIN; - 3'b010: Z = P; + 3'b010: begin Z = P; `ifdef __ICARUS__ if (PREG != 1) $fatal(1, "PREG must be 1 when OPMODEr[6:4] i0s 3'b010"); `endif + end 3'b011: Z = C; - 3'b100: Z = P; + 3'b100: begin Z = P; `ifdef __ICARUS__ if (PREG != 1) $fatal(1, "PREG must be 1 when OPMODEr[6:4] is 3'b100"); if (OPMODEr[3:0] != 4'b1000) $fatal(1, "OPMODEr[3:0] must be 4'b1000 when OPMODEr[6:4] i0s 3'b100"); `endif + end 3'b101: Z = $signed(PCIN[47:17]); 3'b110: Z = $signed(P[47:17]); default: Z = 48'bx; endcase end - // ALU core + // Carry in + wire A24_xnor_B17d = A_MULT[24] ~^ B_MULT[17]; + reg CARRYINr, A24_xnor_B17; + generate + if (CARRYINREG == 1) begin always @(posedge CLK) if (RSTALLCARRYIN) CARRYINr <= 1'b0; else if (CECARRYIN) CARRYINr <= CARRYIN; end + else always @* CARRYINr = CARRYIN; + + if (MREG == 1) begin always @(posedge CLK) if (RSTALLCARRYIN) A24_xnor_B17 <= 1'b0; else if (CECARRYIN) A24_xnor_B17 <= A24_xnor_B17d; end + else always @* A24_xnor_B17 = A24_xnor_B17d; + endgenerate - wire alu_cin = 1'b0; // FIXME* + reg cin_muxed; + + always @(*) begin + case (CARRYINSELr) + 3'b000: cin_muxed = CARRYINr; + 3'b001: cin_muxed = ~PCIN[47]; + 3'b010: cin_muxed = CARRYCASCIN; + 3'b011: cin_muxed = PCIN[47]; + 3'b100: cin_muxed = CARRYCASCOUT; + 3'b101: cin_muxed = ~P[47]; + 3'b110: cin_muxed = A24_xnor_B17; + 3'b111: cin_muxed = P[47]; + default: cin_muxed = 1'bx; + endcase + end + + wire alu_cin = (ALUMODEr[3] || ALUMODEr[2]) ? 1'b0 : cin_muxed; + // ALU core wire [47:0] Z_muxinv = ALUMODEr[0] ? ~Z : Z; wire [47:0] xor_xyz = X ^ Y ^ Z_muxinv; wire [47:0] maj_xyz = (X & Y) | (X & Z) | (X & Y); @@ -730,16 +744,11 @@ module DSP48E1 ( endgenerate wire signed [47:0] Pd = ALUMODEr[1] ? ~alu_sum : alu_sum; + initial P = 48'b0; wire [3:0] CARRYOUTd = (ALUMODEr[0] & ALUMODEr[1]) ? ~ext_carry_out : ext_carry_out; wire CARRYCASCOUTd = ext_carry_out[3]; wire MULTSIGNOUTd = Mr[42]; - always @* begin -`ifdef __ICARUS__ - if (CARRYINSEL != 3'b000) $fatal(1, "Unsupported CARRYINSEL value"); -`endif - end - generate if (PREG == 1) begin always @(posedge CLK) diff --git a/techlibs/xilinx/tests/.gitignore b/techlibs/xilinx/tests/.gitignore index 496b87461..40d61ccce 100644 --- a/techlibs/xilinx/tests/.gitignore +++ b/techlibs/xilinx/tests/.gitignore @@ -4,3 +4,4 @@ bram1_[0-9]*/ bram2.log bram2_syn.v bram2_tb +dsp_work*/ \ No newline at end of file diff --git a/techlibs/xilinx/tests/test_dsp_model.v b/techlibs/xilinx/tests/test_dsp_model.v new file mode 100644 index 000000000..2ecaabfe7 --- /dev/null +++ b/techlibs/xilinx/tests/test_dsp_model.v @@ -0,0 +1,310 @@ +`timescale 1ns / 1ps + +module testbench; + parameter integer ACASCREG = 1; + parameter integer ADREG = 1; + parameter integer ALUMODEREG = 1; + parameter integer AREG = 1; + parameter AUTORESET_PATDET = "NO_RESET"; + parameter A_INPUT = "DIRECT"; + parameter integer BCASCREG = 1; + parameter integer BREG = 1; + parameter B_INPUT = "DIRECT"; + parameter integer CARRYINREG = 1; + parameter integer CARRYINSELREG = 1; + parameter integer CREG = 1; + parameter integer DREG = 1; + parameter integer INMODEREG = 1; + parameter integer MREG = 1; + parameter integer OPMODEREG = 1; + parameter integer PREG = 1; + parameter SEL_MASK = "MASK"; + parameter SEL_PATTERN = "PATTERN"; + parameter USE_DPORT = "FALSE"; + parameter USE_MULT = "MULTIPLY"; + parameter USE_PATTERN_DETECT = "NO_PATDET"; + parameter USE_SIMD = "ONE48"; + parameter [47:0] MASK = 48'h3FFFFFFFFFFF; + parameter [47:0] PATTERN = 48'h000000000000; + parameter [3:0] IS_ALUMODE_INVERTED = 4'b0; + parameter [0:0] IS_CARRYIN_INVERTED = 1'b0; + parameter [0:0] IS_CLK_INVERTED = 1'b0; + parameter [4:0] IS_INMODE_INVERTED = 5'b0; + parameter [6:0] IS_OPMODE_INVERTED = 7'b0; + + reg CLK; + reg CEA1, CEA2, CEAD, CEALUMODE, CEB1, CEB2, CEC, CECARRYIN, CECTRL; + reg CED, CEINMODE, CEM, CEP; + reg RSTA, RSTALLCARRYIN, RSTALUMODE, RSTB, RSTC, RSTD, RSTINMODE, RSTM, RSTP; + reg [29:0] A, ACIN; + reg [17:0] B, BCIN; + reg [47:0] C; + reg [24:0] D; + reg [47:0] PCIN; + reg [3:0] ALUMODE; + reg [2:0] CARRYINSEL; + reg [4:0] INMODE; + reg [6:0] OPMODE; + reg CARRYCASCIN, CARRYIN, MULTSIGNIN; + + output [29:0] ACOUT, REF_ACOUT; + output [17:0] BCOUT, REF_BCOUT; + output CARRYCASCOUT, REF_CARRYCASCOUT; + output [3:0] CARRYOUT, REF_CARRYOUT; + output MULTSIGNOUT, REF_MULTSIGNOUT; + output OVERFLOW, REF_OVERFLOW; + output [47:0] P, REF_P; + output PATTERNBDETECT, REF_PATTERNBDETECT; + output PATTERNDETECT, REF_PATTERNDETECT; + output [47:0] PCOUT, REF_PCOUT; + output UNDERFLOW, REF_UNDERFLOW; + + integer errcount = 0; + + task clkcycle; + begin + #5; + CLK = ~CLK; + #10; + CLK = ~CLK; + #2; + + if (REF_P !== P) begin + $display("ERROR at %1t: REF_P=%b UUT_P=%b DIFF=%b", $time, REF_P, P, REF_P ^ P); + errcount = errcount + 1; + end + if (REF_CARRYOUT !== CARRYOUT) begin + $display("ERROR at %1t: REF_CARRYOUT=%b UUT_CARRYOUT=%b", $time, REF_CARRYOUT, CARRYOUT); + errcount = errcount + 1; + end + #3; + end + endtask + + reg config_valid = 0; + task drc; + config_valid = 1; + if (AREG != 2 && INMODE[0]) config_valid = 0; + if (BREG != 2 && INMODE[4]) config_valid = 0; + if ((OPMODE[3:2] == 2'b01) ^ (OPMODE[1:0] == 2'b01) == 1'b1) config_valid = 0; + if ((OPMODE[6:4] == 3'b010) && PREG != 1) config_valid = 0; + if ((OPMODE[6:4] == 3'b010) && (PREG != 1 || OPMODE[3:0] != 4'b1000)) config_valid = 0; + endtask + + initial begin + $dumpfile("test_dsp_model.vcd"); + $dumpvars(0, testbench); + + #2; + CLK = 1'b0; + {CEA1, CEA2, CEAD, CEALUMODE, CEB1, CEB2, CEC, CECARRYIN, CECTRL} = 9'b111111111; + {CED, CEINMODE, CEM, CEP} = 4'b1111; + + {A, B, C, D} = 0; + {ACIN, BCIN, PCIN} = 0; + {ALUMODE, CARRYINSEL, INMODE} = 0; + {OPMODE, CARRYCASCIN, CARRYIN, MULTSIGNIN} = 0; + + {RSTA, RSTALLCARRYIN, RSTALUMODE, RSTB, RSTC, RSTD, RSTINMODE, RSTM, RSTP} = ~0; + #5; + CLK = 1'b1; + #10; + CLK = 1'b0 + #5; + CLK = 1'b1; + #10; + CLK = 1'b0; + {RSTA, RSTALLCARRYIN, RSTALUMODE, RSTB, RSTC, RSTD, RSTINMODE, RSTM, RSTP} = 0; + + repeat (300) begin + clkcycle; + do begin + A = $urandom; + ACIN = $urandom; + B = $urandom; + BCIN = $urandom; + C = {$urandom, $urandom}; + D = $urandom; + PCIN = {$urandom, $urandom}; + + {RSTA, RSTALLCARRYIN, RSTALUMODE, RSTB, RSTC, RSTD, RSTINMODE, RSTM, RSTP} = $urandom & $urandom & $urandom; + {ALUMODE, CARRYINSEL, INMODE} = $urandom & $urandom & $urandom; + OPMODE = $urandom; + {CARRYCASCIN, CARRYIN, MULTSIGNIN} = $urandom; + drc; + end while (!config_valid); + end + + if (errcount == 0) begin + $display("All tests passed."); + $finish; + end else begin + $display("Caught %1d errors.", errcount); + $stop; + end + end + + DSP48E1 #( + .ACASCREG (ACASCREG), + .ADREG (ADREG), + .ALUMODEREG (ALUMODEREG), + .AREG (AREG), + .AUTORESET_PATDET (AUTORESET_PATDET), + .A_INPUT (A_INPUT), + .BCASCREG (BCASCREG), + .BREG (BREG), + .B_INPUT (B_INPUT), + .CARRYINREG (CARRYINREG), + .CARRYINSELREG (CARRYINSELREG), + .CREG (CREG), + .DREG (DREG), + .INMODEREG (INMODEREG), + .MREG (MREG), + .OPMODEREG (OPMODEREG), + .PREG (PREG), + .SEL_MASK (SEL_MASK), + .SEL_PATTERN (SEL_PATTERN), + .USE_DPORT (USE_DPORT), + .USE_MULT (USE_MULT), + .USE_PATTERN_DETECT (USE_PATTERN_DETECT), + .USE_SIMD (USE_SIMD), + .MASK (MASK), + .PATTERN (PATTERN), + .IS_ALUMODE_INVERTED(IS_ALUMODE_INVERTED), + .IS_CARRYIN_INVERTED(IS_CARRYIN_INVERTED), + .IS_CLK_INVERTED (IS_CLK_INVERTED), + .IS_INMODE_INVERTED (IS_INMODE_INVERTED), + .IS_OPMODE_INVERTED (IS_OPMODE_INVERTED) + ) ref ( + .ACOUT (REF_ACOUT), + .BCOUT (REF_BCOUT), + .CARRYCASCOUT (REF_CARRYCASCOUT), + .CARRYOUT (REF_CARRYOUT), + .MULTSIGNOUT (REF_MULTSIGNOUT), + .OVERFLOW (REF_OVERFLOW), + .P (REF_P), + .PATTERNBDETECT(REF_PATTERNBDETECT), + .PATTERNDETECT (REF_PATTERNDETECT), + .PCOUT (REF_PCOUT), + .UNDERFLOW (REF_UNDERFLOW), + .A (A), + .ACIN (ACIN), + .ALUMODE (ALUMODE), + .B (B), + .BCIN (BCIN), + .C (C), + .CARRYCASCIN (CARRYCASCIN), + .CEA1 (CEA1), + .CEA2 (CEA2), + .CEAD (CEAD), + .CEALUMODE (CEALUMODE), + .CEB1 (CEB1), + .CEB2 (CEB2), + .CEC (CEC), + .CECARRYIN (CECARRYIN), + .CECTRL (CECTRL), + .CED (CED), + .CEINMODE (CEINMODE), + .CEM (CEM), + .CEP (CEP), + .CLK (CLK), + .D (D), + .INMODE (INMODE), + .MULTSIGNIN (MULTSIGNIN), + .OPMODE (OPMODE), + .PCIN (PCIN), + .RSTA (RSTA), + .RSTALLCARRYIN (RSTALLCARRYIN), + .RSTALUMODE (RSTALUMODE), + .RSTB (RSTB), + .RSTC (RSTC), + .RSTCTRL (RSTCTRL), + .RSTD (RSTD), + .RSTINMODE (RSTINMODE), + .RSTM (RSTM), + .RSTP (RSTP) + ); + + DSP48E1_UUT #( + .ACASCREG (ACASCREG), + .ADREG (ADREG), + .ALUMODEREG (ALUMODEREG), + .AREG (AREG), + .AUTORESET_PATDET (AUTORESET_PATDET), + .A_INPUT (A_INPUT), + .BCASCREG (BCASCREG), + .BREG (BREG), + .B_INPUT (B_INPUT), + .CARRYINREG (CARRYINREG), + .CARRYINSELREG (CARRYINSELREG), + .CREG (CREG), + .DREG (DREG), + .INMODEREG (INMODEREG), + .MREG (MREG), + .OPMODEREG (OPMODEREG), + .PREG (PREG), + .SEL_MASK (SEL_MASK), + .SEL_PATTERN (SEL_PATTERN), + .USE_DPORT (USE_DPORT), + .USE_MULT (USE_MULT), + .USE_PATTERN_DETECT (USE_PATTERN_DETECT), + .USE_SIMD (USE_SIMD), + .MASK (MASK), + .PATTERN (PATTERN), + .IS_ALUMODE_INVERTED(IS_ALUMODE_INVERTED), + .IS_CARRYIN_INVERTED(IS_CARRYIN_INVERTED), + .IS_CLK_INVERTED (IS_CLK_INVERTED), + .IS_INMODE_INVERTED (IS_INMODE_INVERTED), + .IS_OPMODE_INVERTED (IS_OPMODE_INVERTED) + ) uut ( + .ACOUT (ACOUT), + .BCOUT (BCOUT), + .CARRYCASCOUT (CARRYCASCOUT), + .CARRYOUT (CARRYOUT), + .MULTSIGNOUT (MULTSIGNOUT), + .OVERFLOW (OVERFLOW), + .P (P), + .PATTERNBDETECT(PATTERNBDETECT), + .PATTERNDETECT (PATTERNDETECT), + .PCOUT (PCOUT), + .UNDERFLOW (UNDERFLOW), + .A (A), + .ACIN (ACIN), + .ALUMODE (ALUMODE), + .B (B), + .BCIN (BCIN), + .C (C), + .CARRYCASCIN (CARRYCASCIN), + .CEA1 (CEA1), + .CEA2 (CEA2), + .CEAD (CEAD), + .CEALUMODE (CEALUMODE), + .CEB1 (CEB1), + .CEB2 (CEB2), + .CEC (CEC), + .CECARRYIN (CECARRYIN), + .CECTRL (CECTRL), + .CED (CED), + .CEINMODE (CEINMODE), + .CEM (CEM), + .CEP (CEP), + .CLK (CLK), + .D (D), + .INMODE (INMODE), + .MULTSIGNIN (MULTSIGNIN), + .OPMODE (OPMODE), + .PCIN (PCIN), + .RSTA (RSTA), + .RSTALLCARRYIN (RSTALLCARRYIN), + .RSTALUMODE (RSTALUMODE), + .RSTB (RSTB), + .RSTC (RSTC), + .RSTCTRL (RSTCTRL), + .RSTD (RSTD), + .RSTINMODE (RSTINMODE), + .RSTM (RSTM), + .RSTP (RSTP) + ); + + +endmodule -- cgit v1.2.3 From f0f352e97164692572ce41801abd62cf5641c44f Mon Sep 17 00:00:00 2001 From: David Shah Date: Thu, 8 Aug 2019 10:05:11 +0100 Subject: [wip] sim model testing Signed-off-by: David Shah --- techlibs/xilinx/cells_sim.v | 4 +- techlibs/xilinx/tests/.gitignore | 6 ++- techlibs/xilinx/tests/test_dsp_model.sh | 11 +++++ techlibs/xilinx/tests/test_dsp_model.v | 71 +++++++++++++++++++++++++++------ 4 files changed, 77 insertions(+), 15 deletions(-) create mode 100644 techlibs/xilinx/tests/test_dsp_model.sh (limited to 'techlibs') diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index a6ab98926..4e26ea5c9 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -728,7 +728,7 @@ module DSP48E1 ( maj_xyz_gated[23] ^ int_carry_out[1], 1'bx }; - end else if (USE_SIMD == "FOUR48") begin + end else begin assign maj_xyz_simd_gated = {maj_xyz_gated, alu_cin}; assign int_carry_in[3:1] = int_carry_out[2:0]; assign ext_carry_out = { @@ -738,7 +738,7 @@ module DSP48E1 ( end genvar i; - for (i = 0; i < 4; i++) + for (i = 0; i < 4; i = i + 1) assign {int_carry_out[i], alu_sum[i*12 +: 12]} = {1'b0, maj_xyz_simd_gated[i*12 +: ((i == 3) ? 13 : 12)]} + xor_xyz_muxed[i*12 +: 12] + int_carry_in[i]; endgenerate diff --git a/techlibs/xilinx/tests/.gitignore b/techlibs/xilinx/tests/.gitignore index 40d61ccce..ef3699bd2 100644 --- a/techlibs/xilinx/tests/.gitignore +++ b/techlibs/xilinx/tests/.gitignore @@ -4,4 +4,8 @@ bram1_[0-9]*/ bram2.log bram2_syn.v bram2_tb -dsp_work*/ \ No newline at end of file +dsp_work*/ +test_dsp_model_ref.v +test_dsp_model_uut.v +test_dsp_model +*.vcd diff --git a/techlibs/xilinx/tests/test_dsp_model.sh b/techlibs/xilinx/tests/test_dsp_model.sh new file mode 100644 index 000000000..5455294da --- /dev/null +++ b/techlibs/xilinx/tests/test_dsp_model.sh @@ -0,0 +1,11 @@ +#!/bin/bash +set -ex +sed 's/DSP48E1/DSP48E1_UUT/; /DSP48E1_UUT/,/endmodule/ p; d;' < ../cells_sim.v > test_dsp_model_uut.v +if [ ! -f "test_dsp_model_ref.v" ]; then + cat /opt/Xilinx/Vivado/2019.1/data/verilog/src/unisims/DSP48E1.v > test_dsp_model_ref.v +fi +for tb in mult_noreg_nopreadd_nocasc +do + iverilog -s $tb -s glbl -o test_dsp_model test_dsp_model.v test_dsp_model_uut.v test_dsp_model_ref.v /opt/Xilinx/Vivado/2019.1/data/verilog/src/glbl.v + vvp -N ./test_dsp_model +done diff --git a/techlibs/xilinx/tests/test_dsp_model.v b/techlibs/xilinx/tests/test_dsp_model.v index 2ecaabfe7..f8039aa15 100644 --- a/techlibs/xilinx/tests/test_dsp_model.v +++ b/techlibs/xilinx/tests/test_dsp_model.v @@ -83,12 +83,21 @@ module testbench; reg config_valid = 0; task drc; - config_valid = 1; - if (AREG != 2 && INMODE[0]) config_valid = 0; - if (BREG != 2 && INMODE[4]) config_valid = 0; - if ((OPMODE[3:2] == 2'b01) ^ (OPMODE[1:0] == 2'b01) == 1'b1) config_valid = 0; - if ((OPMODE[6:4] == 3'b010) && PREG != 1) config_valid = 0; - if ((OPMODE[6:4] == 3'b010) && (PREG != 1 || OPMODE[3:0] != 4'b1000)) config_valid = 0; + begin + config_valid = 1; + if (AREG != 2 && INMODE[0]) config_valid = 0; + if (BREG != 2 && INMODE[4]) config_valid = 0; + if (OPMODE[1:0] == 2'b10 && PREG != 1) config_valid = 0; + if ((OPMODE[3:2] == 2'b01) ^ (OPMODE[1:0] == 2'b01) == 1'b1) config_valid = 0; + if ((OPMODE[6:4] == 3'b010 || OPMODE[6:4] == 3'b110) && PREG != 1) config_valid = 0; + if ((OPMODE[6:4] == 3'b100) && (PREG != 1 || OPMODE[3:0] != 4'b1000)) config_valid = 0; + if ((CARRYINSEL == 3'b100 || CARRYINSEL == 3'b101 || CARRYINSEL == 3'b111) && (PREG != 1)) config_valid = 0; + if (OPMODE[6:4] == 3'b111) config_valid = 0; + if ((ALUMODE[3:2] == 2'b01 || ALUMODE[3:2] == 2'b11) && OPMODE[3:2] != 2'b00 && OPMODE[3:2] != 2'b10) config_valid = 0; + if ((OPMODE[3:0] == 4'b0101) && CARRYINSEL == 3'b010) config_valid = 0; + if (CARRYINSEL == 3'b010 && OPMODE != 7'b0001010) config_valid = 0; + if (CARRYINSEL == 3'b001 && OPMODE != 7'b1010101) config_valid = 0; + end endtask initial begin @@ -109,7 +118,7 @@ module testbench; #5; CLK = 1'b1; #10; - CLK = 1'b0 + CLK = 1'b0; #5; CLK = 1'b1; #10; @@ -118,7 +127,8 @@ module testbench; repeat (300) begin clkcycle; - do begin + config_valid = 0; + while (!config_valid) begin A = $urandom; ACIN = $urandom; B = $urandom; @@ -129,10 +139,12 @@ module testbench; {RSTA, RSTALLCARRYIN, RSTALUMODE, RSTB, RSTC, RSTD, RSTINMODE, RSTM, RSTP} = $urandom & $urandom & $urandom; {ALUMODE, CARRYINSEL, INMODE} = $urandom & $urandom & $urandom; - OPMODE = $urandom; + OPMODE = $urandom; + if ($urandom & 1'b1) + OPMODE[3:0] = 4'b0101; // test multiply more than other modes {CARRYCASCIN, CARRYIN, MULTSIGNIN} = $urandom; drc; - end while (!config_valid); + end end if (errcount == 0) begin @@ -194,6 +206,7 @@ module testbench; .BCIN (BCIN), .C (C), .CARRYCASCIN (CARRYCASCIN), + .CARRYINSEL (CARRYINSEL), .CEA1 (CEA1), .CEA2 (CEA2), .CEAD (CEAD), @@ -275,6 +288,7 @@ module testbench; .BCIN (BCIN), .C (C), .CARRYCASCIN (CARRYCASCIN), + .CARRYINSEL (CARRYINSEL), .CEA1 (CEA1), .CEA2 (CEA2), .CEAD (CEAD), @@ -305,6 +319,39 @@ module testbench; .RSTM (RSTM), .RSTP (RSTP) ); - - endmodule + +module mult_noreg_nopreadd_nocasc; + testbench #( + .ACASCREG (0), + .ADREG (0), + .ALUMODEREG (0), + .AREG (0), + .AUTORESET_PATDET ("NO_RESET"), + .A_INPUT ("DIRECT"), + .BCASCREG (0), + .BREG (0), + .B_INPUT ("DIRECT"), + .CARRYINREG (0), + .CARRYINSELREG (0), + .CREG (0), + .DREG (0), + .INMODEREG (0), + .MREG (0), + .OPMODEREG (0), + .PREG (0), + .SEL_MASK ("MASK"), + .SEL_PATTERN ("PATTERN"), + .USE_DPORT ("FALSE"), + .USE_MULT ("DYNAMIC"), + .USE_PATTERN_DETECT ("NO_PATDET"), + .USE_SIMD ("ONE48"), + .MASK (48'h3FFFFFFFFFFF), + .PATTERN (48'h000000000000), + .IS_ALUMODE_INVERTED(4'b0), + .IS_CARRYIN_INVERTED(1'b0), + .IS_CLK_INVERTED (1'b0), + .IS_INMODE_INVERTED (5'b0), + .IS_OPMODE_INVERTED (7'b0) + ) testbench (); +endmodule \ No newline at end of file -- cgit v1.2.3 From f6605c7dc0b1bcbc091b8283a741e24be25478b1 Mon Sep 17 00:00:00 2001 From: David Shah Date: Thu, 8 Aug 2019 10:26:40 +0100 Subject: DSP48E1 sim model: Comb, no pre-adder, mode working Signed-off-by: David Shah --- techlibs/xilinx/cells_sim.v | 5 +++-- techlibs/xilinx/tests/test_dsp_model.v | 16 ++++++++++------ 2 files changed, 13 insertions(+), 8 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 4e26ea5c9..3817c6a1d 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -689,7 +689,7 @@ module DSP48E1 ( // ALU core wire [47:0] Z_muxinv = ALUMODEr[0] ? ~Z : Z; wire [47:0] xor_xyz = X ^ Y ^ Z_muxinv; - wire [47:0] maj_xyz = (X & Y) | (X & Z) | (X & Y); + wire [47:0] maj_xyz = (X & Y) | (X & Z_muxinv) | (Y & Z_muxinv); wire [47:0] xor_xyz_muxed = ALUMODEr[3] ? maj_xyz : xor_xyz; wire [47:0] maj_xyz_gated = ALUMODEr[2] ? 48'b0 : maj_xyz; @@ -745,7 +745,8 @@ module DSP48E1 ( wire signed [47:0] Pd = ALUMODEr[1] ? ~alu_sum : alu_sum; initial P = 48'b0; - wire [3:0] CARRYOUTd = (ALUMODEr[0] & ALUMODEr[1]) ? ~ext_carry_out : ext_carry_out; + wire [3:0] CARRYOUTd = (OPMODEr[3:0] == 4'b0101 || ALUMODEr[3:2] != 2'b00) ? 4'bxxxx : + ((ALUMODEr[0] & ALUMODEr[1]) ? ~ext_carry_out : ext_carry_out); wire CARRYCASCOUTd = ext_carry_out[3]; wire MULTSIGNOUTd = Mr[42]; diff --git a/techlibs/xilinx/tests/test_dsp_model.v b/techlibs/xilinx/tests/test_dsp_model.v index f8039aa15..86ff7ab40 100644 --- a/techlibs/xilinx/tests/test_dsp_model.v +++ b/techlibs/xilinx/tests/test_dsp_model.v @@ -35,7 +35,7 @@ module testbench; reg CLK; reg CEA1, CEA2, CEAD, CEALUMODE, CEB1, CEB2, CEC, CECARRYIN, CECTRL; reg CED, CEINMODE, CEM, CEP; - reg RSTA, RSTALLCARRYIN, RSTALUMODE, RSTB, RSTC, RSTD, RSTINMODE, RSTM, RSTP; + reg RSTA, RSTALLCARRYIN, RSTALUMODE, RSTB, RSTC, RSTCTRL, RSTD, RSTINMODE, RSTM, RSTP; reg [29:0] A, ACIN; reg [17:0] B, BCIN; reg [47:0] C; @@ -61,6 +61,8 @@ module testbench; integer errcount = 0; + reg ERROR_FLAG = 0; + task clkcycle; begin #5; @@ -68,14 +70,16 @@ module testbench; #10; CLK = ~CLK; #2; - + ERROR_FLAG = 0; if (REF_P !== P) begin $display("ERROR at %1t: REF_P=%b UUT_P=%b DIFF=%b", $time, REF_P, P, REF_P ^ P); errcount = errcount + 1; + ERROR_FLAG = 1; end if (REF_CARRYOUT !== CARRYOUT) begin $display("ERROR at %1t: REF_CARRYOUT=%b UUT_CARRYOUT=%b", $time, REF_CARRYOUT, CARRYOUT); errcount = errcount + 1; + ERROR_FLAG = 1; end #3; end @@ -114,7 +118,7 @@ module testbench; {ALUMODE, CARRYINSEL, INMODE} = 0; {OPMODE, CARRYCASCIN, CARRYIN, MULTSIGNIN} = 0; - {RSTA, RSTALLCARRYIN, RSTALUMODE, RSTB, RSTC, RSTD, RSTINMODE, RSTM, RSTP} = ~0; + {RSTA, RSTALLCARRYIN, RSTALUMODE, RSTB, RSTC, RSTCTRL, RSTD, RSTINMODE, RSTM, RSTP} = ~0; #5; CLK = 1'b1; #10; @@ -123,7 +127,7 @@ module testbench; CLK = 1'b1; #10; CLK = 1'b0; - {RSTA, RSTALLCARRYIN, RSTALUMODE, RSTB, RSTC, RSTD, RSTINMODE, RSTM, RSTP} = 0; + {RSTA, RSTALLCARRYIN, RSTALUMODE, RSTB, RSTC, RSTCTRL, RSTD, RSTINMODE, RSTM, RSTP} = 0; repeat (300) begin clkcycle; @@ -137,8 +141,8 @@ module testbench; D = $urandom; PCIN = {$urandom, $urandom}; - {RSTA, RSTALLCARRYIN, RSTALUMODE, RSTB, RSTC, RSTD, RSTINMODE, RSTM, RSTP} = $urandom & $urandom & $urandom; - {ALUMODE, CARRYINSEL, INMODE} = $urandom & $urandom & $urandom; + {RSTA, RSTALLCARRYIN, RSTALUMODE, RSTB, RSTC, RSTCTRL, RSTD, RSTINMODE, RSTM, RSTP} = $urandom & $urandom & $urandom & $urandom & $urandom & $urandom; + {ALUMODE, CARRYINSEL, INMODE} = $urandom; OPMODE = $urandom; if ($urandom & 1'b1) OPMODE[3:0] = 4'b0101; // test multiply more than other modes -- cgit v1.2.3 From e7dbe7bb3de256f0ea89eb07647799b1e8d65bbe Mon Sep 17 00:00:00 2001 From: David Shah Date: Thu, 8 Aug 2019 10:52:04 +0100 Subject: DSP48E1 sim model: seq test working Signed-off-by: David Shah --- techlibs/xilinx/cells_sim.v | 19 ++++++++---- techlibs/xilinx/tests/test_dsp_model.sh | 2 +- techlibs/xilinx/tests/test_dsp_model.v | 55 +++++++++++++++++++++++++++------ 3 files changed, 60 insertions(+), 16 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 3817c6a1d..53061808b 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -547,7 +547,7 @@ module DSP48E1 ( end // C and D registers - if (CREG == 1) begin always @(posedge CLK) if (RSTC) Cr <= 48'b0; else if (CEC) Cr <= D; end + if (CREG == 1) begin always @(posedge CLK) if (RSTC) Cr <= 48'b0; else if (CEC) Cr <= C; end else always @* Cr <= C; if (DREG == 1) begin always @(posedge CLK) if (RSTD) Dr <= 25'b0; else if (CED) Dr <= D; end @@ -608,7 +608,7 @@ module DSP48E1 ( // X multiplexer case (OPMODEr[1:0]) 2'b00: X = 48'b0; - 2'b01: begin X = $signed(M); + 2'b01: begin X = $signed(Mr); `ifdef __ICARUS__ if (OPMODEr[3:2] != 2'b01) $fatal(1, "OPMODEr[3:2] must be 2'b01 when OPMODEr[1:0] is 2'b01"); `endif @@ -631,7 +631,7 @@ module DSP48E1 ( `endif end 2'b10: Y = {48{1'b1}}; - 2'b11: Y = C; + 2'b11: Y = Cr; default: Y = 48'bx; endcase @@ -644,7 +644,7 @@ module DSP48E1 ( if (PREG != 1) $fatal(1, "PREG must be 1 when OPMODEr[6:4] i0s 3'b010"); `endif end - 3'b011: Z = C; + 3'b011: Z = Cr; 3'b100: begin Z = P; `ifdef __ICARUS__ if (PREG != 1) $fatal(1, "PREG must be 1 when OPMODEr[6:4] is 3'b100"); @@ -659,7 +659,7 @@ module DSP48E1 ( // Carry in wire A24_xnor_B17d = A_MULT[24] ~^ B_MULT[17]; - reg CARRYINr, A24_xnor_B17; + reg CARRYINr = 1'b0, A24_xnor_B17 = 1'b0; generate if (CARRYINREG == 1) begin always @(posedge CLK) if (RSTALLCARRYIN) CARRYINr <= 1'b0; else if (CECARRYIN) CARRYINr <= CARRYIN; end else always @* CARRYINr = CARRYIN; @@ -698,6 +698,7 @@ module DSP48E1 ( wire [3:0] int_carry_in, int_carry_out, ext_carry_out; wire [47:0] alu_sum; assign int_carry_in[0] = 1'b0; + wire [3:0] carryout_reset; generate if (USE_SIMD == "FOUR12") begin @@ -715,6 +716,7 @@ module DSP48E1 ( maj_xyz_gated[23] ^ int_carry_out[1], maj_xyz_gated[11] ^ int_carry_out[0] }; + assign carryout_reset = 4'b0000; end else if (USE_SIMD == "TWO24") begin assign maj_xyz_simd_gated = { maj_xyz_gated[47:24], @@ -728,6 +730,7 @@ module DSP48E1 ( maj_xyz_gated[23] ^ int_carry_out[1], 1'bx }; + assign carryout_reset = 4'b0x0x; end else begin assign maj_xyz_simd_gated = {maj_xyz_gated, alu_cin}; assign int_carry_in[3:1] = int_carry_out[2:0]; @@ -735,6 +738,7 @@ module DSP48E1 ( int_carry_out[3], 3'bxxx }; + assign carryout_reset = 4'b0xxx; end genvar i; @@ -745,6 +749,9 @@ module DSP48E1 ( wire signed [47:0] Pd = ALUMODEr[1] ? ~alu_sum : alu_sum; initial P = 48'b0; + initial CARRYOUT = carryout_reset; + initial CARRYCASCOUT = 1'b0; + initial MULTSIGNOUT = 1'b0; wire [3:0] CARRYOUTd = (OPMODEr[3:0] == 4'b0101 || ALUMODEr[3:2] != 2'b00) ? 4'bxxxx : ((ALUMODEr[0] & ALUMODEr[1]) ? ~ext_carry_out : ext_carry_out); wire CARRYCASCOUTd = ext_carry_out[3]; @@ -755,7 +762,7 @@ module DSP48E1 ( always @(posedge CLK) if (RSTP) begin P <= 48'b0; - CARRYOUT <= 4'b0; + CARRYOUT <= carryout_reset; CARRYCASCOUT <= 1'b0; MULTSIGNOUT <= 1'b0; end else if (CEP) begin diff --git a/techlibs/xilinx/tests/test_dsp_model.sh b/techlibs/xilinx/tests/test_dsp_model.sh index 5455294da..3c7cfac30 100644 --- a/techlibs/xilinx/tests/test_dsp_model.sh +++ b/techlibs/xilinx/tests/test_dsp_model.sh @@ -4,7 +4,7 @@ sed 's/DSP48E1/DSP48E1_UUT/; /DSP48E1_UUT/,/endmodule/ p; d;' < ../cells_sim.v > if [ ! -f "test_dsp_model_ref.v" ]; then cat /opt/Xilinx/Vivado/2019.1/data/verilog/src/unisims/DSP48E1.v > test_dsp_model_ref.v fi -for tb in mult_noreg_nopreadd_nocasc +for tb in mult_allreg_nopreadd_nocasc mult_noreg_nopreadd_nocasc do iverilog -s $tb -s glbl -o test_dsp_model test_dsp_model.v test_dsp_model_uut.v test_dsp_model_ref.v /opt/Xilinx/Vivado/2019.1/data/verilog/src/glbl.v vvp -N ./test_dsp_model diff --git a/techlibs/xilinx/tests/test_dsp_model.v b/techlibs/xilinx/tests/test_dsp_model.v index 86ff7ab40..b5574911b 100644 --- a/techlibs/xilinx/tests/test_dsp_model.v +++ b/techlibs/xilinx/tests/test_dsp_model.v @@ -94,7 +94,7 @@ module testbench; if (OPMODE[1:0] == 2'b10 && PREG != 1) config_valid = 0; if ((OPMODE[3:2] == 2'b01) ^ (OPMODE[1:0] == 2'b01) == 1'b1) config_valid = 0; if ((OPMODE[6:4] == 3'b010 || OPMODE[6:4] == 3'b110) && PREG != 1) config_valid = 0; - if ((OPMODE[6:4] == 3'b100) && (PREG != 1 || OPMODE[3:0] != 4'b1000)) config_valid = 0; + if ((OPMODE[6:4] == 3'b100) && (PREG != 1 || OPMODE[3:0] != 4'b1000 || ALUMODE[3:2] == 2'b01 || ALUMODE[3:2] == 2'b11)) config_valid = 0; if ((CARRYINSEL == 3'b100 || CARRYINSEL == 3'b101 || CARRYINSEL == 3'b111) && (PREG != 1)) config_valid = 0; if (OPMODE[6:4] == 3'b111) config_valid = 0; if ((ALUMODE[3:2] == 2'b01 || ALUMODE[3:2] == 2'b11) && OPMODE[3:2] != 2'b00 && OPMODE[3:2] != 2'b10) config_valid = 0; @@ -119,14 +119,16 @@ module testbench; {OPMODE, CARRYCASCIN, CARRYIN, MULTSIGNIN} = 0; {RSTA, RSTALLCARRYIN, RSTALUMODE, RSTB, RSTC, RSTCTRL, RSTD, RSTINMODE, RSTM, RSTP} = ~0; - #5; - CLK = 1'b1; - #10; - CLK = 1'b0; - #5; - CLK = 1'b1; - #10; - CLK = 1'b0; + repeat (10) begin + #10; + CLK = 1'b1; + #10; + CLK = 1'b0; + #10; + CLK = 1'b1; + #10; + CLK = 1'b0; + end {RSTA, RSTALLCARRYIN, RSTALUMODE, RSTB, RSTC, RSTCTRL, RSTD, RSTINMODE, RSTM, RSTP} = 0; repeat (300) begin @@ -358,4 +360,39 @@ module mult_noreg_nopreadd_nocasc; .IS_INMODE_INVERTED (5'b0), .IS_OPMODE_INVERTED (7'b0) ) testbench (); +endmodule + +module mult_allreg_nopreadd_nocasc; + testbench #( + .ACASCREG (1), + .ADREG (1), + .ALUMODEREG (1), + .AREG (2), + .AUTORESET_PATDET ("NO_RESET"), + .A_INPUT ("DIRECT"), + .BCASCREG (1), + .BREG (2), + .B_INPUT ("DIRECT"), + .CARRYINREG (1), + .CARRYINSELREG (1), + .CREG (1), + .DREG (1), + .INMODEREG (1), + .MREG (1), + .OPMODEREG (1), + .PREG (1), + .SEL_MASK ("MASK"), + .SEL_PATTERN ("PATTERN"), + .USE_DPORT ("FALSE"), + .USE_MULT ("DYNAMIC"), + .USE_PATTERN_DETECT ("NO_PATDET"), + .USE_SIMD ("ONE48"), + .MASK (48'h3FFFFFFFFFFF), + .PATTERN (48'h000000000000), + .IS_ALUMODE_INVERTED(4'b0), + .IS_CARRYIN_INVERTED(1'b0), + .IS_CLK_INVERTED (1'b0), + .IS_INMODE_INVERTED (5'b0), + .IS_OPMODE_INVERTED (7'b0) + ) testbench (); endmodule \ No newline at end of file -- cgit v1.2.3 From d60b3c0dc8ca9ce1b14c4acf2b602acc1fac00c5 Mon Sep 17 00:00:00 2001 From: David Shah Date: Thu, 8 Aug 2019 11:18:37 +0100 Subject: DSP48E1 sim model: fix seq tests and add preadder tests Signed-off-by: David Shah --- techlibs/xilinx/tests/test_dsp_model.sh | 3 +- techlibs/xilinx/tests/test_dsp_model.v | 94 +++++++++++++++++++++++++++++++-- 2 files changed, 91 insertions(+), 6 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/tests/test_dsp_model.sh b/techlibs/xilinx/tests/test_dsp_model.sh index 3c7cfac30..337530e87 100644 --- a/techlibs/xilinx/tests/test_dsp_model.sh +++ b/techlibs/xilinx/tests/test_dsp_model.sh @@ -4,7 +4,8 @@ sed 's/DSP48E1/DSP48E1_UUT/; /DSP48E1_UUT/,/endmodule/ p; d;' < ../cells_sim.v > if [ ! -f "test_dsp_model_ref.v" ]; then cat /opt/Xilinx/Vivado/2019.1/data/verilog/src/unisims/DSP48E1.v > test_dsp_model_ref.v fi -for tb in mult_allreg_nopreadd_nocasc mult_noreg_nopreadd_nocasc +for tb in mult_allreg_nopreadd_nocasc mult_noreg_nopreadd_nocasc \ + mult_allreg_preadd_nocasc mult_noreg_preadd_nocasc do iverilog -s $tb -s glbl -o test_dsp_model test_dsp_model.v test_dsp_model_uut.v test_dsp_model_ref.v /opt/Xilinx/Vivado/2019.1/data/verilog/src/glbl.v vvp -N ./test_dsp_model diff --git a/techlibs/xilinx/tests/test_dsp_model.v b/techlibs/xilinx/tests/test_dsp_model.v index b5574911b..6f1ca045a 100644 --- a/techlibs/xilinx/tests/test_dsp_model.v +++ b/techlibs/xilinx/tests/test_dsp_model.v @@ -91,16 +91,19 @@ module testbench; config_valid = 1; if (AREG != 2 && INMODE[0]) config_valid = 0; if (BREG != 2 && INMODE[4]) config_valid = 0; + if (OPMODE[1:0] == 2'b10 && PREG != 1) config_valid = 0; if ((OPMODE[3:2] == 2'b01) ^ (OPMODE[1:0] == 2'b01) == 1'b1) config_valid = 0; if ((OPMODE[6:4] == 3'b010 || OPMODE[6:4] == 3'b110) && PREG != 1) config_valid = 0; if ((OPMODE[6:4] == 3'b100) && (PREG != 1 || OPMODE[3:0] != 4'b1000 || ALUMODE[3:2] == 2'b01 || ALUMODE[3:2] == 2'b11)) config_valid = 0; if ((CARRYINSEL == 3'b100 || CARRYINSEL == 3'b101 || CARRYINSEL == 3'b111) && (PREG != 1)) config_valid = 0; if (OPMODE[6:4] == 3'b111) config_valid = 0; - if ((ALUMODE[3:2] == 2'b01 || ALUMODE[3:2] == 2'b11) && OPMODE[3:2] != 2'b00 && OPMODE[3:2] != 2'b10) config_valid = 0; if ((OPMODE[3:0] == 4'b0101) && CARRYINSEL == 3'b010) config_valid = 0; - if (CARRYINSEL == 3'b010 && OPMODE != 7'b0001010) config_valid = 0; - if (CARRYINSEL == 3'b001 && OPMODE != 7'b1010101) config_valid = 0; + if (CARRYINSEL == 3'b000 && OPMODE == 7'b1001000) config_valid = 0; + + if ((ALUMODE[3:2] == 2'b01 || ALUMODE[3:2] == 2'b11) && OPMODE[3:2] != 2'b00 && OPMODE[3:2] != 2'b10) config_valid = 0; + + end endtask @@ -131,7 +134,7 @@ module testbench; end {RSTA, RSTALLCARRYIN, RSTALUMODE, RSTB, RSTC, RSTCTRL, RSTD, RSTINMODE, RSTM, RSTP} = 0; - repeat (300) begin + repeat (5000) begin clkcycle; config_valid = 0; while (!config_valid) begin @@ -144,11 +147,22 @@ module testbench; PCIN = {$urandom, $urandom}; {RSTA, RSTALLCARRYIN, RSTALUMODE, RSTB, RSTC, RSTCTRL, RSTD, RSTINMODE, RSTM, RSTP} = $urandom & $urandom & $urandom & $urandom & $urandom & $urandom; - {ALUMODE, CARRYINSEL, INMODE} = $urandom; + {ALUMODE, INMODE} = $urandom; + CARRYINSEL = $urandom & $urandom & $urandom; OPMODE = $urandom; if ($urandom & 1'b1) OPMODE[3:0] = 4'b0101; // test multiply more than other modes {CARRYCASCIN, CARRYIN, MULTSIGNIN} = $urandom; + + // So few valid options in these modes, just force one valid option + if (CARRYINSEL == 3'b001) OPMODE = 7'b1010101; + if (CARRYINSEL == 3'b010) OPMODE = 7'b0001010; + if (CARRYINSEL == 3'b011) OPMODE = 7'b0011011; + if (CARRYINSEL == 3'b100) OPMODE = 7'b0110011; + if (CARRYINSEL == 3'b101) OPMODE = 7'b0011010; + if (CARRYINSEL == 3'b110) OPMODE = 7'b0010101; + if (CARRYINSEL == 3'b111) OPMODE = 7'b0100011; + drc; end end @@ -395,4 +409,74 @@ module mult_allreg_nopreadd_nocasc; .IS_INMODE_INVERTED (5'b0), .IS_OPMODE_INVERTED (7'b0) ) testbench (); +endmodule + +module mult_noreg_preadd_nocasc; + testbench #( + .ACASCREG (0), + .ADREG (0), + .ALUMODEREG (0), + .AREG (0), + .AUTORESET_PATDET ("NO_RESET"), + .A_INPUT ("DIRECT"), + .BCASCREG (0), + .BREG (0), + .B_INPUT ("DIRECT"), + .CARRYINREG (0), + .CARRYINSELREG (0), + .CREG (0), + .DREG (0), + .INMODEREG (0), + .MREG (0), + .OPMODEREG (0), + .PREG (0), + .SEL_MASK ("MASK"), + .SEL_PATTERN ("PATTERN"), + .USE_DPORT ("TRUE"), + .USE_MULT ("DYNAMIC"), + .USE_PATTERN_DETECT ("NO_PATDET"), + .USE_SIMD ("ONE48"), + .MASK (48'h3FFFFFFFFFFF), + .PATTERN (48'h000000000000), + .IS_ALUMODE_INVERTED(4'b0), + .IS_CARRYIN_INVERTED(1'b0), + .IS_CLK_INVERTED (1'b0), + .IS_INMODE_INVERTED (5'b0), + .IS_OPMODE_INVERTED (7'b0) + ) testbench (); +endmodule + +module mult_allreg_preadd_nocasc; + testbench #( + .ACASCREG (1), + .ADREG (1), + .ALUMODEREG (1), + .AREG (2), + .AUTORESET_PATDET ("NO_RESET"), + .A_INPUT ("DIRECT"), + .BCASCREG (1), + .BREG (2), + .B_INPUT ("DIRECT"), + .CARRYINREG (1), + .CARRYINSELREG (1), + .CREG (1), + .DREG (1), + .INMODEREG (1), + .MREG (1), + .OPMODEREG (1), + .PREG (1), + .SEL_MASK ("MASK"), + .SEL_PATTERN ("PATTERN"), + .USE_DPORT ("TRUE"), + .USE_MULT ("DYNAMIC"), + .USE_PATTERN_DETECT ("NO_PATDET"), + .USE_SIMD ("ONE48"), + .MASK (48'h3FFFFFFFFFFF), + .PATTERN (48'h000000000000), + .IS_ALUMODE_INVERTED(4'b0), + .IS_CARRYIN_INVERTED(1'b0), + .IS_CLK_INVERTED (1'b0), + .IS_INMODE_INVERTED (5'b0), + .IS_OPMODE_INVERTED (7'b0) + ) testbench (); endmodule \ No newline at end of file -- cgit v1.2.3 From 57aeb4cc01058c0167e5a4eda9def97b0bb1741b Mon Sep 17 00:00:00 2001 From: David Shah Date: Thu, 8 Aug 2019 11:32:43 +0100 Subject: DSP48E1 model: test CE inputs Signed-off-by: David Shah --- techlibs/xilinx/cells_sim.v | 13 ++++++++----- techlibs/xilinx/tests/test_dsp_model.v | 11 +++++++++-- 2 files changed, 17 insertions(+), 7 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 53061808b..b738d9712 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -593,14 +593,17 @@ module DSP48E1 ( endgenerate wire signed [42:0] M = A_MULT * B_MULT; + wire signed [42:0] Mx = (CARRYINSEL == 3'b010) ? 43'bx : M; reg signed [42:0] Mr = 43'b0; // Multiplier result register generate - if (MREG == 1) begin always @(posedge CLK) if (RSTM) Mr <= 43'b0; else if (CEM) Mr <= M; end - else always @* Mr <= M; + if (MREG == 1) begin always @(posedge CLK) if (RSTM) Mr <= 43'b0; else if (CEM) Mr <= Mx; end + else always @* Mr <= Mx; endgenerate + wire signed [42:0] Mrx = (CARRYINSELr == 3'b010) ? 43'bx : Mr; + // X, Y and Z ALU inputs reg signed [47:0] X, Y, Z; @@ -608,7 +611,7 @@ module DSP48E1 ( // X multiplexer case (OPMODEr[1:0]) 2'b00: X = 48'b0; - 2'b01: begin X = $signed(Mr); + 2'b01: begin X = $signed(Mrx); `ifdef __ICARUS__ if (OPMODEr[3:2] != 2'b01) $fatal(1, "OPMODEr[3:2] must be 2'b01 when OPMODEr[1:0] is 2'b01"); `endif @@ -664,7 +667,7 @@ module DSP48E1 ( if (CARRYINREG == 1) begin always @(posedge CLK) if (RSTALLCARRYIN) CARRYINr <= 1'b0; else if (CECARRYIN) CARRYINr <= CARRYIN; end else always @* CARRYINr = CARRYIN; - if (MREG == 1) begin always @(posedge CLK) if (RSTALLCARRYIN) A24_xnor_B17 <= 1'b0; else if (CECARRYIN) A24_xnor_B17 <= A24_xnor_B17d; end + if (MREG == 1) begin always @(posedge CLK) if (RSTALLCARRYIN) A24_xnor_B17 <= 1'b0; else if (CEM) A24_xnor_B17 <= A24_xnor_B17d; end else always @* A24_xnor_B17 = A24_xnor_B17d; endgenerate @@ -755,7 +758,7 @@ module DSP48E1 ( wire [3:0] CARRYOUTd = (OPMODEr[3:0] == 4'b0101 || ALUMODEr[3:2] != 2'b00) ? 4'bxxxx : ((ALUMODEr[0] & ALUMODEr[1]) ? ~ext_carry_out : ext_carry_out); wire CARRYCASCOUTd = ext_carry_out[3]; - wire MULTSIGNOUTd = Mr[42]; + wire MULTSIGNOUTd = Mrx[42]; generate if (PREG == 1) begin diff --git a/techlibs/xilinx/tests/test_dsp_model.v b/techlibs/xilinx/tests/test_dsp_model.v index 6f1ca045a..7086634d2 100644 --- a/techlibs/xilinx/tests/test_dsp_model.v +++ b/techlibs/xilinx/tests/test_dsp_model.v @@ -134,7 +134,7 @@ module testbench; end {RSTA, RSTALLCARRYIN, RSTALUMODE, RSTB, RSTC, RSTCTRL, RSTD, RSTINMODE, RSTM, RSTP} = 0; - repeat (5000) begin + repeat (10000) begin clkcycle; config_valid = 0; while (!config_valid) begin @@ -146,6 +146,13 @@ module testbench; D = $urandom; PCIN = {$urandom, $urandom}; + {CEA1, CEA2, CEAD, CEALUMODE, CEB1, CEB2, CEC, CECARRYIN, CECTRL} = $urandom | $urandom | $urandom; + {CED, CEINMODE, CEM, CEP} = $urandom | $urandom | $urandom | $urandom; + + // Otherwise we can accidentally create illegal configs + CEINMODE = CECTRL; + CEALUMODE = CECTRL; + {RSTA, RSTALLCARRYIN, RSTALUMODE, RSTB, RSTC, RSTCTRL, RSTD, RSTINMODE, RSTM, RSTP} = $urandom & $urandom & $urandom & $urandom & $urandom & $urandom; {ALUMODE, INMODE} = $urandom; CARRYINSEL = $urandom & $urandom & $urandom; @@ -162,7 +169,7 @@ module testbench; if (CARRYINSEL == 3'b101) OPMODE = 7'b0011010; if (CARRYINSEL == 3'b110) OPMODE = 7'b0010101; if (CARRYINSEL == 3'b111) OPMODE = 7'b0100011; - + drc; end end -- cgit v1.2.3 From b8cd4ad64ae9a45faecffc1a6b92a8219755bc60 Mon Sep 17 00:00:00 2001 From: David Shah Date: Thu, 8 Aug 2019 11:39:35 +0100 Subject: DSP48E1 sim model: add SIMD tests Signed-off-by: David Shah --- techlibs/xilinx/cells_sim.v | 2 +- techlibs/xilinx/tests/test_dsp_model.sh | 6 +- techlibs/xilinx/tests/test_dsp_model.v | 108 ++++++++++++++++++++++++++++++++ 3 files changed, 113 insertions(+), 3 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index b738d9712..8b6eaae5d 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -468,7 +468,7 @@ module DSP48E1 ( if (SEL_MASK != "MASK") $fatal(1, "Unsupported SEL_MASK value"); if (SEL_PATTERN != "PATTERN") $fatal(1, "Unsupported SEL_PATTERN value"); if (USE_PATTERN_DETECT != "NO_PATDET") $fatal(1, "Unsupported USE_PATTERN_DETECT value"); - if (USE_SIMD != "ONE48") $fatal(1, "Unsupported USE_SIMD value"); + if (USE_SIMD != "ONE48" && USE_SIMD != "TWO24" && USE_SIMD != "FOUR12") $fatal(1, "Unsupported USE_SIMD value"); if (IS_ALUMODE_INVERTED != 4'b0) $fatal(1, "Unsupported IS_ALUMODE_INVERTED value"); if (IS_CARRYIN_INVERTED != 1'b0) $fatal(1, "Unsupported IS_CARRYIN_INVERTED value"); if (IS_CLK_INVERTED != 1'b0) $fatal(1, "Unsupported IS_CLK_INVERTED value"); diff --git a/techlibs/xilinx/tests/test_dsp_model.sh b/techlibs/xilinx/tests/test_dsp_model.sh index 337530e87..2acd97eb4 100644 --- a/techlibs/xilinx/tests/test_dsp_model.sh +++ b/techlibs/xilinx/tests/test_dsp_model.sh @@ -4,8 +4,10 @@ sed 's/DSP48E1/DSP48E1_UUT/; /DSP48E1_UUT/,/endmodule/ p; d;' < ../cells_sim.v > if [ ! -f "test_dsp_model_ref.v" ]; then cat /opt/Xilinx/Vivado/2019.1/data/verilog/src/unisims/DSP48E1.v > test_dsp_model_ref.v fi -for tb in mult_allreg_nopreadd_nocasc mult_noreg_nopreadd_nocasc \ - mult_allreg_preadd_nocasc mult_noreg_preadd_nocasc +for tb in simd24_preadd_noreg_nocasc simd12_preadd_noreg_nocasc \ + mult_allreg_nopreadd_nocasc mult_noreg_nopreadd_nocasc \ + mult_allreg_preadd_nocasc mult_noreg_preadd_nocasc mult_inreg_preadd_nocasc \ + do iverilog -s $tb -s glbl -o test_dsp_model test_dsp_model.v test_dsp_model_uut.v test_dsp_model_ref.v /opt/Xilinx/Vivado/2019.1/data/verilog/src/glbl.v vvp -N ./test_dsp_model diff --git a/techlibs/xilinx/tests/test_dsp_model.v b/techlibs/xilinx/tests/test_dsp_model.v index 7086634d2..04d5b26ab 100644 --- a/techlibs/xilinx/tests/test_dsp_model.v +++ b/techlibs/xilinx/tests/test_dsp_model.v @@ -92,6 +92,8 @@ module testbench; if (AREG != 2 && INMODE[0]) config_valid = 0; if (BREG != 2 && INMODE[4]) config_valid = 0; + if (USE_SIMD != "ONE48" && OPMODE[3:0] == 4'b0101) config_valid = 0; + if (OPMODE[1:0] == 2'b10 && PREG != 1) config_valid = 0; if ((OPMODE[3:2] == 2'b01) ^ (OPMODE[1:0] == 2'b01) == 1'b1) config_valid = 0; if ((OPMODE[6:4] == 3'b010 || OPMODE[6:4] == 3'b110) && PREG != 1) config_valid = 0; @@ -486,4 +488,110 @@ module mult_allreg_preadd_nocasc; .IS_INMODE_INVERTED (5'b0), .IS_OPMODE_INVERTED (7'b0) ) testbench (); +endmodule + +module mult_inreg_preadd_nocasc; + testbench #( + .ACASCREG (1), + .ADREG (0), + .ALUMODEREG (0), + .AREG (1), + .AUTORESET_PATDET ("NO_RESET"), + .A_INPUT ("DIRECT"), + .BCASCREG (1), + .BREG (1), + .B_INPUT ("DIRECT"), + .CARRYINREG (0), + .CARRYINSELREG (0), + .CREG (1), + .DREG (1), + .INMODEREG (0), + .MREG (0), + .OPMODEREG (0), + .PREG (0), + .SEL_MASK ("MASK"), + .SEL_PATTERN ("PATTERN"), + .USE_DPORT ("TRUE"), + .USE_MULT ("DYNAMIC"), + .USE_PATTERN_DETECT ("NO_PATDET"), + .USE_SIMD ("ONE48"), + .MASK (48'h3FFFFFFFFFFF), + .PATTERN (48'h000000000000), + .IS_ALUMODE_INVERTED(4'b0), + .IS_CARRYIN_INVERTED(1'b0), + .IS_CLK_INVERTED (1'b0), + .IS_INMODE_INVERTED (5'b0), + .IS_OPMODE_INVERTED (7'b0) + ) testbench (); +endmodule + +module simd12_preadd_noreg_nocasc; + testbench #( + .ACASCREG (0), + .ADREG (0), + .ALUMODEREG (0), + .AREG (0), + .AUTORESET_PATDET ("NO_RESET"), + .A_INPUT ("DIRECT"), + .BCASCREG (0), + .BREG (0), + .B_INPUT ("DIRECT"), + .CARRYINREG (0), + .CARRYINSELREG (0), + .CREG (0), + .DREG (0), + .INMODEREG (0), + .MREG (0), + .OPMODEREG (0), + .PREG (0), + .SEL_MASK ("MASK"), + .SEL_PATTERN ("PATTERN"), + .USE_DPORT ("TRUE"), + .USE_MULT ("DYNAMIC"), + .USE_PATTERN_DETECT ("NO_PATDET"), + .USE_SIMD ("FOUR12"), + .MASK (48'h3FFFFFFFFFFF), + .PATTERN (48'h000000000000), + .IS_ALUMODE_INVERTED(4'b0), + .IS_CARRYIN_INVERTED(1'b0), + .IS_CLK_INVERTED (1'b0), + .IS_INMODE_INVERTED (5'b0), + .IS_OPMODE_INVERTED (7'b0) + ) testbench (); +endmodule + + +module simd24_preadd_noreg_nocasc; + testbench #( + .ACASCREG (0), + .ADREG (0), + .ALUMODEREG (0), + .AREG (0), + .AUTORESET_PATDET ("NO_RESET"), + .A_INPUT ("DIRECT"), + .BCASCREG (0), + .BREG (0), + .B_INPUT ("DIRECT"), + .CARRYINREG (0), + .CARRYINSELREG (0), + .CREG (0), + .DREG (0), + .INMODEREG (0), + .MREG (0), + .OPMODEREG (0), + .PREG (0), + .SEL_MASK ("MASK"), + .SEL_PATTERN ("PATTERN"), + .USE_DPORT ("TRUE"), + .USE_MULT ("DYNAMIC"), + .USE_PATTERN_DETECT ("NO_PATDET"), + .USE_SIMD ("TWO24"), + .MASK (48'h3FFFFFFFFFFF), + .PATTERN (48'h000000000000), + .IS_ALUMODE_INVERTED(4'b0), + .IS_CARRYIN_INVERTED(1'b0), + .IS_CLK_INVERTED (1'b0), + .IS_INMODE_INVERTED (5'b0), + .IS_OPMODE_INVERTED (7'b0) + ) testbench (); endmodule \ No newline at end of file -- cgit v1.2.3 From cb84ed23263f8cad8f878a327061ac2c990af812 Mon Sep 17 00:00:00 2001 From: David Shah Date: Thu, 8 Aug 2019 15:14:09 +0100 Subject: ecp5: Bring up to date with mul2dsp changes Signed-off-by: David Shah --- techlibs/ecp5/dsp_map.v | 9 ++++++++- techlibs/ecp5/synth_ecp5.cc | 3 ++- 2 files changed, 10 insertions(+), 2 deletions(-) (limited to 'techlibs') diff --git a/techlibs/ecp5/dsp_map.v b/techlibs/ecp5/dsp_map.v index 24e28869e..cb95ddb1c 100644 --- a/techlibs/ecp5/dsp_map.v +++ b/techlibs/ecp5/dsp_map.v @@ -1,9 +1,16 @@ module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y); + + parameter A_WIDTH = 18; + parameter B_WIDTH = 18; + parameter Y_WIDTH = 36; + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + MULT18X18D _TECHMAP_REPLACE_ ( .A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .A4(A[4]), .A5(A[5]), .A6(A[6]), .A7(A[7]), .A8(A[8]), .A9(A[9]), .A10(A[10]), .A11(A[11]), .A12(A[12]), .A13(A[13]), .A14(A[14]), .A15(A[15]), .A16(A[16]), .A17(A[17]), .B0(B[0]), .B1(B[1]), .B2(B[2]), .B3(B[3]), .B4(B[4]), .B5(B[5]), .B6(B[6]), .B7(B[7]), .B8(B[8]), .B9(B[9]), .B10(B[10]), .B11(B[11]), .B12(B[12]), .B13(B[13]), .B14(B[14]), .B15(B[15]), .B16(B[16]), .B17(B[17]), .C17(1'b0), .C16(1'b0), .C15(1'b0), .C14(1'b0), .C13(1'b0), .C12(1'b0), .C11(1'b0), .C10(1'b0), .C9(1'b0), .C8(1'b0), .C7(1'b0), .C6(1'b0), .C5(1'b0), .C4(1'b0), .C3(1'b0), .C2(1'b0), .C1(1'b0), .C0(1'b0), - .SIGNEDA(1'b0), .SIGNEDB(1'b0), .SOURCEA(1'b0), .SOURCEB(1'b0), + .SIGNEDA(A_SIGNED), .SIGNEDB(B_SIGNED), .SOURCEA(1'b0), .SOURCEB(1'b0), .P0(Y[0]), .P1(Y[1]), .P2(Y[2]), .P3(Y[3]), .P4(Y[4]), .P5(Y[5]), .P6(Y[6]), .P7(Y[7]), .P8(Y[8]), .P9(Y[9]), .P10(Y[10]), .P11(Y[11]), .P12(Y[12]), .P13(Y[13]), .P14(Y[14]), .P15(Y[15]), .P16(Y[16]), .P17(Y[17]), .P18(Y[18]), .P19(Y[19]), .P20(Y[20]), .P21(Y[21]), .P22(Y[22]), .P23(Y[23]), .P24(Y[24]), .P25(Y[25]), .P26(Y[26]), .P27(Y[27]), .P28(Y[28]), .P29(Y[29]), .P30(Y[30]), .P31(Y[31]), .P32(Y[32]), .P33(Y[33]), .P34(Y[34]), .P35(Y[35]) ); diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index 3129ba929..7be377280 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -248,9 +248,10 @@ struct SynthEcp5Pass : public ScriptPass run("opt_expr"); run("opt_clean"); if (dsp) { - run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 -D DSP_NAME=$__MUL18X18"); + run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=$__MUL18X18"); run("clean"); run("techmap -map +/ecp5/dsp_map.v"); + run("chtype -set $mul t:$__soft_mul","(if -dsp)"); } run("alumacc"); run("opt"); -- cgit v1.2.3 From 0492b8b5412683392bc19ad7f15ba6c14e6668f8 Mon Sep 17 00:00:00 2001 From: David Shah Date: Thu, 8 Aug 2019 15:18:59 +0100 Subject: ecp5: Replace '-dsp' with inverse logic '-nodsp' to match synth_xilinx Signed-off-by: David Shah --- techlibs/ecp5/synth_ecp5.cc | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) (limited to 'techlibs') diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index 7be377280..1a5359e85 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -89,8 +89,8 @@ struct SynthEcp5Pass : public ScriptPass log(" generate an output netlist (and BLIF file) suitable for VPR\n"); log(" (this feature is experimental and incomplete)\n"); log("\n"); - log(" -dsp\n"); - log(" map multipliers to MULT18X18D (EXPERIMENTAL)\n"); + log(" -nodsp\n"); + log(" do not map multipliers to MULT18X18D\n"); log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); @@ -99,7 +99,7 @@ struct SynthEcp5Pass : public ScriptPass } string top_opt, blif_file, edif_file, json_file; - bool noccu2, nodffe, nobram, nolutram, nowidelut, flatten, retime, abc2, abc9, dsp, vpr; + bool noccu2, nodffe, nobram, nolutram, nowidelut, flatten, retime, abc2, abc9, nodsp, vpr; void clear_flags() YS_OVERRIDE { @@ -117,7 +117,7 @@ struct SynthEcp5Pass : public ScriptPass abc2 = false; vpr = false; abc9 = false; - dsp = false; + nodsp = false; } void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE @@ -196,8 +196,8 @@ struct SynthEcp5Pass : public ScriptPass abc9 = true; continue; } - if (args[argidx] == "-dsp") { - dsp = true; + if (args[argidx] == "-nodsp") { + nodsp = true; continue; } break; @@ -247,11 +247,11 @@ struct SynthEcp5Pass : public ScriptPass run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4"); run("opt_expr"); run("opt_clean"); - if (dsp) { - run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=$__MUL18X18"); - run("clean"); - run("techmap -map +/ecp5/dsp_map.v"); - run("chtype -set $mul t:$__soft_mul","(if -dsp)"); + if (!nodsp) { + run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=$__MUL18X18", "(unless -nodsp)"); + run("clean", "(unless -nodsp)"); + run("techmap -map +/ecp5/dsp_map.v", "(unless -nodsp)"); + run("chtype -set $mul t:$__soft_mul", "(unless -nodsp)"); } run("alumacc"); run("opt"); -- cgit v1.2.3 From 13cc106cf7409570936f441af2cc133896f4ecb4 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 8 Aug 2019 10:44:26 -0700 Subject: Fix copy-pasta typo --- techlibs/xilinx/cells_sim.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 8b6eaae5d..2731cb454 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -522,7 +522,7 @@ module DSP48E1 ( always @* Ar2 <= A_muxed; end - // Configurable A register + // Configurable B register if (BREG == 2) begin always @(posedge CLK) if (RSTB) begin @@ -532,7 +532,7 @@ module DSP48E1 ( if (CEB1) Br1 <= B_muxed; if (CEB2) Br2 <= Br1; end - end else if (AREG == 1) begin + end else if (BREG == 1) begin always @(posedge CLK) if (RSTB) begin Br1 <= 18'b0; -- cgit v1.2.3 From 57b2e4b9c1dda6d092e261f90a311087c62d0bc4 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 8 Aug 2019 10:44:35 -0700 Subject: INMODE is 5 bits --- techlibs/xilinx/dsp_map.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/dsp_map.v b/techlibs/xilinx/dsp_map.v index 3d7b09d69..423e12fbe 100644 --- a/techlibs/xilinx/dsp_map.v +++ b/techlibs/xilinx/dsp_map.v @@ -32,7 +32,7 @@ module \$__MUL25X18 (input signed [24:0] A, input signed [17:0] B, output signed .D(24'b0), .P(P_48), - .INMODE(4'b0000), + .INMODE(5'b00000), .ALUMODE(4'b0000), .OPMODE(7'b000101), .CARRYINSEL(3'b000), -- cgit v1.2.3 From 716024387468285f0d5ee2719b86fe6ddbfff93e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 8 Aug 2019 10:45:56 -0700 Subject: Move xilinx_dsp to before alumacc --- techlibs/xilinx/synth_xilinx.cc | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index a787c7c4c..49beaa565 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -286,7 +286,10 @@ struct SynthXilinxPass : public ScriptPass if (!nodsp || help_mode) { // NB: Xilinx multipliers are signed only - run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=25 -D DSP_B_MAXWIDTH=18 -D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18"); + run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=25 -D DSP_B_MAXWIDTH=18 -D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18", "(skip if '-nodsp')"); + run("techmap -map +/xilinx/dsp_map.v", "(skip if '-nodsp')"); // TODO: fold into xilinx_dsp + run("xilinx_dsp", " (skip if '-nodsp')"); + run("chtype -set $mul t:$__soft_mul"," (skip if '-nodsp')"); } run("alumacc"); @@ -331,11 +334,6 @@ struct SynthXilinxPass : public ScriptPass run("memory_map"); run("dffsr2dff"); run("dff2dffe"); - if (help_mode || !nodsp) { - run("techmap -map +/xilinx/dsp_map.v", "(skip if '-nodsp')"); - run("xilinx_dsp", " (skip if '-nodsp')"); - run("chtype -set $mul t:$__soft_mul"," (skip if '-nodsp')"); - } if (help_mode) { run("simplemap t:$mux", " ('-widemux' only)"); run("muxcover , ('-widemux' only)"); -- cgit v1.2.3 From 162eab6b7422754c4c88d794f8024cfc1e03a419 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 8 Aug 2019 10:55:48 -0700 Subject: Combine techmap calls --- techlibs/xilinx/synth_xilinx.cc | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 49beaa565..7b1fe5e3b 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -286,8 +286,7 @@ struct SynthXilinxPass : public ScriptPass if (!nodsp || help_mode) { // NB: Xilinx multipliers are signed only - run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=25 -D DSP_B_MAXWIDTH=18 -D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18", "(skip if '-nodsp')"); - run("techmap -map +/xilinx/dsp_map.v", "(skip if '-nodsp')"); // TODO: fold into xilinx_dsp + run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_B_MAXWIDTH=18 -D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18", "(skip if '-nodsp')"); run("xilinx_dsp", " (skip if '-nodsp')"); run("chtype -set $mul t:$__soft_mul"," (skip if '-nodsp')"); } -- cgit v1.2.3 From 2c0be7aa5d7dcdf18678fb7b09ba1b3b5dd00998 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 8 Aug 2019 12:56:05 -0700 Subject: Rework ice40_dsp to map to SB_MAC16 earlier, and check before packing --- techlibs/ice40/Makefile.inc | 1 + techlibs/ice40/dsp_map.v | 34 ++++++++++++++++++++++++++++++++++ techlibs/ice40/synth_ice40.cc | 2 +- 3 files changed, 36 insertions(+), 1 deletion(-) create mode 100644 techlibs/ice40/dsp_map.v (limited to 'techlibs') diff --git a/techlibs/ice40/Makefile.inc b/techlibs/ice40/Makefile.inc index d258d5a5d..b0eadab44 100644 --- a/techlibs/ice40/Makefile.inc +++ b/techlibs/ice40/Makefile.inc @@ -28,6 +28,7 @@ $(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_sim.v)) $(eval $(call add_share_file,share/ice40,techlibs/ice40/latches_map.v)) $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams.txt)) $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams_map.v)) +$(eval $(call add_share_file,share/ice40,techlibs/ice40/dsp_map.v)) $(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_hx.box)) $(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_hx.lut)) $(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_lp.box)) diff --git a/techlibs/ice40/dsp_map.v b/techlibs/ice40/dsp_map.v new file mode 100644 index 000000000..06fa73956 --- /dev/null +++ b/techlibs/ice40/dsp_map.v @@ -0,0 +1,34 @@ +module \$__MUL16X16 (input [15:0] A, input [15:0] B, output [31:0] Y); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 0; + parameter B_WIDTH = 0; + parameter Y_WIDTH = 0; + + SB_MAC16 #( + .NEG_TRIGGER(1'b0), + .C_REG(1'b0), + .A_REG(1'b0), + .B_REG(1'b0), + .D_REG(1'b0), + .TOP_8x8_MULT_REG(1'b0), + .BOT_8x8_MULT_REG(1'b0), + .PIPELINE_16x16_MULT_REG1(1'b0), + .PIPELINE_16x16_MULT_REG2(1'b0), + .TOPOUTPUT_SELECT(2'b11), + .TOPADDSUB_LOWERINPUT(2'b0), + .TOPADDSUB_UPPERINPUT(1'b0), + .TOPADDSUB_CARRYSELECT(2'b0), + .BOTOUTPUT_SELECT(2'b11), + .BOTADDSUB_LOWERINPUT(2'b0), + .BOTADDSUB_UPPERINPUT(1'b0), + .BOTADDSUB_CARRYSELECT(2'b0), + .MODE_8x8(1'b0), + .A_SIGNED(A_SIGNED), + .B_SIGNED(B_SIGNED) + ) _TECHMAP_REPLACE_ ( + .A(A), + .B(B), + .O(Y), + ); +endmodule diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 09759f359..9c3670c7c 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -266,7 +266,7 @@ struct SynthIce40Pass : public ScriptPass run("opt_expr"); run("opt_clean"); if (help_mode || dsp) { - run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 -D DSP_NAME=$__MUL16X16", "(if -dsp)"); + run("techmap -map +/mul2dsp.v -map +/ice40/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 -D DSP_NAME=$__MUL16X16", "(if -dsp)"); run("opt_expr -fine", " (if -dsp)"); run("ice40_dsp", " (if -dsp)"); run("chtype -set $mul t:$__soft_mul","(if -dsp)"); -- cgit v1.2.3 From 1f722b35009275ad9a3f4ce4224fcb6973e3bc80 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 8 Aug 2019 16:33:20 -0700 Subject: Remove signed from ports in +/xilinx/dsp_map.v --- techlibs/xilinx/dsp_map.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/dsp_map.v b/techlibs/xilinx/dsp_map.v index 423e12fbe..fdd55afe3 100644 --- a/techlibs/xilinx/dsp_map.v +++ b/techlibs/xilinx/dsp_map.v @@ -1,4 +1,4 @@ -module \$__MUL25X18 (input signed [24:0] A, input signed [17:0] B, output signed [42:0] Y); +module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y); parameter A_SIGNED = 0; parameter B_SIGNED = 0; parameter A_WIDTH = 0; -- cgit v1.2.3 From 0b5b56c1ecab78d126bbab13598c184f5e28cccc Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 9 Aug 2019 15:19:33 -0700 Subject: Pack partial-product adder DSP48E1 packing --- techlibs/xilinx/synth_xilinx.cc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'techlibs') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 7b1fe5e3b..a54b3ac52 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -287,6 +287,8 @@ struct SynthXilinxPass : public ScriptPass if (!nodsp || help_mode) { // NB: Xilinx multipliers are signed only run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_B_MAXWIDTH=18 -D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18", "(skip if '-nodsp')"); + run("opt_expr -fine", " (skip if '-nodsp')"); + run("wreduce", " (skip if '-nodsp')"); run("xilinx_dsp", " (skip if '-nodsp')"); run("chtype -set $mul t:$__soft_mul"," (skip if '-nodsp')"); } -- cgit v1.2.3 From 6d254f2de802ccd71b6514b0f5e4c0b44c415ae4 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 9 Aug 2019 17:05:56 -0700 Subject: Add wreduce to synth_ice40 -dsp as well --- techlibs/ice40/synth_ice40.cc | 1 + 1 file changed, 1 insertion(+) (limited to 'techlibs') diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 9c3670c7c..02598401c 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -268,6 +268,7 @@ struct SynthIce40Pass : public ScriptPass if (help_mode || dsp) { run("techmap -map +/mul2dsp.v -map +/ice40/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 -D DSP_NAME=$__MUL16X16", "(if -dsp)"); run("opt_expr -fine", " (if -dsp)"); + run("wreduce", " (if -dsp)"); run("ice40_dsp", " (if -dsp)"); run("chtype -set $mul t:$__soft_mul","(if -dsp)"); } -- cgit v1.2.3 From edff79a25a802e5b1816608b48e3ac335ad87147 Mon Sep 17 00:00:00 2001 From: David Shah Date: Tue, 13 Aug 2019 10:29:42 +0100 Subject: xilinx: Rework labels for faster Verilator testing Signed-off-by: David Shah --- techlibs/xilinx/synth_xilinx.cc | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 265cee6d6..546d67337 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -255,7 +255,7 @@ struct SynthXilinxPass : public ScriptPass run(stringf("hierarchy -check %s", top_opt.c_str())); } - if (check_label("coarse")) { + if (check_label("prepare")) { run("proc"); if (flatten || help_mode) run("flatten", "(with '-flatten')"); @@ -283,7 +283,9 @@ struct SynthXilinxPass : public ScriptPass } run("techmap -map +/cmp2lut.v -D LUT_WIDTH=6"); + } + if (check_label("dsp")) { if (!nodsp || help_mode) { // NB: Xilinx multipliers are signed only run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_B_MAXWIDTH=18 -D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18", "(skip if '-nodsp')"); @@ -292,7 +294,9 @@ struct SynthXilinxPass : public ScriptPass run("xilinx_dsp", " (skip if '-nodsp')"); run("chtype -set $mul t:$__soft_mul"," (skip if '-nodsp')"); } + } + if (check_label("coarse")) { run("alumacc"); run("share"); run("opt"); -- cgit v1.2.3 From 2a1b98d478918b0a17c7e509ada6e7a71bbab526 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 13 Aug 2019 10:21:24 -0700 Subject: Add DSP_A_MAXWIDTH_PARTIAL, refactor --- techlibs/common/mul2dsp.v | 254 +++++++++++++++++----------------------- techlibs/xilinx/synth_xilinx.cc | 2 +- 2 files changed, 111 insertions(+), 145 deletions(-) (limited to 'techlibs') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 8e37201e2..71d5a5454 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -27,20 +27,30 @@ */ `ifndef DSP_A_MAXWIDTH -$error("Macro DSP_A_MAXWIDTH must be defined"); +$fatal(1, "Macro DSP_A_MAXWIDTH must be defined"); `endif `ifndef DSP_B_MAXWIDTH -$error("Macro DSP_B_MAXWIDTH must be defined"); +$fatal(1, "Macro DSP_B_MAXWIDTH must be defined"); +`endif +`ifndef DSP_B_MAXWIDTH +$fatal(1, "Macro DSP_B_MAXWIDTH must be defined"); +`endif +`ifndef DSP_A_MAXWIDTH_PARTIAL +`define DSP_A_MAXWIDTH_PARTIAL `DSP_A_MAXWIDTH +`endif +`ifndef DSP_B_MAXWIDTH_PARTIAL +`define DSP_B_MAXWIDTH_PARTIAL `DSP_B_MAXWIDTH `endif `ifndef DSP_NAME -$error("Macro DSP_NAME must be defined"); +$fatal(1, "Macro DSP_NAME must be defined"); `endif `define MAX(a,b) (a > b ? a : b) `define MIN(a,b) (a < b ? a : b) -module \$mul (A, B, Y); +(* techmap_celltype = "$mul $__mul" *) +module _80_mul (A, B, Y); parameter A_SIGNED = 0; parameter B_SIGNED = 0; parameter A_WIDTH = 1; @@ -51,12 +61,26 @@ module \$mul (A, B, Y); input [B_WIDTH-1:0] B; output [Y_WIDTH-1:0] Y; + parameter _TECHMAP_CELLTYPE_ = ""; + generate - if (A_SIGNED != B_SIGNED) + if (0) begin end +`ifdef DSP_A_MINWIDTH + else if (A_WIDTH < `DSP_A_MINWIDTH) + wire _TECHMAP_FAIL_ = 1; +`endif +`ifdef DSP_B_MINWIDTH + else if (B_WIDTH < `DSP_B_MINWIDTH) + wire _TECHMAP_FAIL_ = 1; +`endif +`ifdef DSP_Y_MINWIDTH + else if (Y_WIDTH < `DSP_Y_MINWIDTH) + wire _TECHMAP_FAIL_ = 1; +`endif + else if (_TECHMAP_CELLTYPE_ == "$mul" && A_SIGNED != B_SIGNED) wire _TECHMAP_FAIL_ = 1; - // NB: A_SIGNED == B_SIGNED from here `ifdef DSP_SIGNEDONLY - else if (!A_SIGNED) + else if (_TECHMAP_CELLTYPE_ == "$mul" && !A_SIGNED) \$mul #( .A_SIGNED(1), .B_SIGNED(1), @@ -81,102 +105,53 @@ module \$mul (A, B, Y); .B(A), .Y(Y) ); - else - \$__mul #( - .A_SIGNED(A_SIGNED), - .B_SIGNED(B_SIGNED), - .A_WIDTH(A_WIDTH), - .B_WIDTH(B_WIDTH), - .Y_WIDTH(Y_WIDTH) - ) _TECHMAP_REPLACE_ ( - .A(A), - .B(B), - .Y(Y) - ); - endgenerate -endmodule - -module \$__mul (A, B, Y); - parameter A_SIGNED = 0; - parameter B_SIGNED = 0; - parameter A_WIDTH = 1; - parameter B_WIDTH = 1; - parameter Y_WIDTH = 1; - - input [A_WIDTH-1:0] A; - input [B_WIDTH-1:0] B; - output [Y_WIDTH-1:0] Y; - - wire [1023:0] _TECHMAP_DO_ = "proc; clean"; + else begin + wire [1023:0] _TECHMAP_DO_ = "proc; clean"; `ifdef DSP_SIGNEDONLY - localparam sign_headroom = 1; + localparam sign_headroom = 1; `else - localparam sign_headroom = 0; + localparam sign_headroom = 0; `endif - genvar i; - generate - if (0) begin end -`ifdef DSP_A_MINWIDTH - else if (A_WIDTH < `DSP_A_MINWIDTH) - wire _TECHMAP_FAIL_ = 1; -`endif -`ifdef DSP_B_MINWIDTH - else if (B_WIDTH < `DSP_B_MINWIDTH) - wire _TECHMAP_FAIL_ = 1; -`endif -`ifdef DSP_Y_MINWIDTH - else if (Y_WIDTH < `DSP_Y_MINWIDTH) - wire _TECHMAP_FAIL_ = 1; -`endif - else if (A_WIDTH > `DSP_A_MAXWIDTH) begin - localparam n = (A_WIDTH+`DSP_A_MAXWIDTH-sign_headroom-1) / (`DSP_A_MAXWIDTH-sign_headroom); - localparam partial_Y_WIDTH = `MIN(Y_WIDTH, B_WIDTH+`DSP_A_MAXWIDTH); - localparam last_Y_WIDTH = `MIN(partial_Y_WIDTH, B_WIDTH+A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom)); + genvar i; + if (A_WIDTH > `DSP_A_MAXWIDTH) begin + localparam n = (A_WIDTH-`DSP_A_MAXWIDTH+`DSP_A_MAXWIDTH_PARTIAL-sign_headroom-1) / (`DSP_A_MAXWIDTH_PARTIAL-sign_headroom); + localparam partial_Y_WIDTH = `MIN(Y_WIDTH, B_WIDTH+`DSP_A_MAXWIDTH_PARTIAL); + localparam last_A_WIDTH = A_WIDTH-n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom); + localparam last_Y_WIDTH = B_WIDTH+last_A_WIDTH; if (A_SIGNED && B_SIGNED) begin - wire signed [partial_Y_WIDTH-1:0] partial [n-2:0]; + wire signed [partial_Y_WIDTH-1:0] partial [n-1:0]; wire signed [last_Y_WIDTH-1:0] last_partial; - wire signed [Y_WIDTH-1:0] partial_sum [n-1:0]; + wire signed [Y_WIDTH-1:0] partial_sum [n:0]; end else begin wire [partial_Y_WIDTH-1:0] partial [n-1:0]; wire [last_Y_WIDTH-1:0] last_partial; - wire [Y_WIDTH-1:0] partial_sum [n-1:0]; + wire [Y_WIDTH-1:0] partial_sum [n:0]; end - \$__mul #( - .A_SIGNED(sign_headroom), - .B_SIGNED(B_SIGNED), - .A_WIDTH(`DSP_A_MAXWIDTH), - .B_WIDTH(B_WIDTH), - .Y_WIDTH(partial_Y_WIDTH) - ) mul_slice_first ( - .A({{sign_headroom{1'b0}}, A[`DSP_A_MAXWIDTH-sign_headroom-1 : 0]}), - .B(B), - .Y(partial[0]) - ); - assign partial_sum[0] = partial[0]; - - for (i = 1; i < n-1; i=i+1) begin:slice + for (i = 0; i < n; i=i+1) begin:slice \$__mul #( .A_SIGNED(sign_headroom), .B_SIGNED(B_SIGNED), - .A_WIDTH(`DSP_A_MAXWIDTH), + .A_WIDTH(`DSP_A_MAXWIDTH_PARTIAL), .B_WIDTH(B_WIDTH), .Y_WIDTH(partial_Y_WIDTH) ) mul_slice ( - .A({{sign_headroom{1'b0}}, A[i*(`DSP_A_MAXWIDTH-sign_headroom) +: `DSP_A_MAXWIDTH-sign_headroom]}), + .A({{sign_headroom{1'b0}}, A[i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom) +: `DSP_A_MAXWIDTH_PARTIAL-sign_headroom]}), .B(B), .Y(partial[i]) ); // TODO: Currently a 'cascade' approach to summing the partial // products is taken here, but a more efficient 'binary // reduction' approach also exists... - assign partial_sum[i] = (partial[i] << i*(`DSP_A_MAXWIDTH-sign_headroom)) + partial_sum[i-1]; + if (i == 0) + assign partial_sum[i] = partial[i]; + else + assign partial_sum[i] = (partial[i] << i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[i-1]; end - localparam last_A_WIDTH = A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom); \$__mul #( .A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), @@ -188,56 +163,46 @@ module \$__mul (A, B, Y); .B(B), .Y(last_partial) ); - assign partial_sum[n-1] = (last_partial << (n-1)*(`DSP_A_MAXWIDTH-sign_headroom)) + partial_sum[n-2]; - assign Y = partial_sum[n-1]; + assign partial_sum[n] = (last_partial << n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[n-1]; + assign Y = partial_sum[n]; end else if (B_WIDTH > `DSP_B_MAXWIDTH) begin - localparam n = (B_WIDTH+`DSP_B_MAXWIDTH-sign_headroom-1) / (`DSP_B_MAXWIDTH-sign_headroom); - localparam partial_Y_WIDTH = `MIN(Y_WIDTH, A_WIDTH+`DSP_B_MAXWIDTH); - localparam last_Y_WIDTH = `MIN(partial_Y_WIDTH, A_WIDTH+B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH-sign_headroom)); + localparam n = (B_WIDTH-`DSP_B_MAXWIDTH+`DSP_B_MAXWIDTH_PARTIAL-sign_headroom-1) / (`DSP_B_MAXWIDTH_PARTIAL-sign_headroom); + localparam partial_Y_WIDTH = `MIN(Y_WIDTH, A_WIDTH+`DSP_B_MAXWIDTH_PARTIAL); + localparam last_B_WIDTH = B_WIDTH-n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom); + localparam last_Y_WIDTH = A_WIDTH+last_B_WIDTH; if (A_SIGNED && B_SIGNED) begin - wire signed [partial_Y_WIDTH-1:0] partial [n-2:0]; + wire signed [partial_Y_WIDTH-1:0] partial [n-1:0]; wire signed [last_Y_WIDTH-1:0] last_partial; - wire signed [Y_WIDTH-1:0] partial_sum [n-1:0]; + wire signed [Y_WIDTH-1:0] partial_sum [n:0]; end else begin wire [partial_Y_WIDTH-1:0] partial [n-1:0]; wire [last_Y_WIDTH-1:0] last_partial; - wire [Y_WIDTH-1:0] partial_sum [n-1:0]; + wire [Y_WIDTH-1:0] partial_sum [n:0]; end - \$__mul #( - .A_SIGNED(A_SIGNED), - .B_SIGNED(sign_headroom), - .A_WIDTH(A_WIDTH), - .B_WIDTH(`DSP_B_MAXWIDTH), - .Y_WIDTH(partial_Y_WIDTH) - ) mul_first ( - .A(A), - .B({{sign_headroom{1'b0}}, B[`DSP_B_MAXWIDTH-sign_headroom-1 : 0]}), - .Y(partial[0]) - ); - assign partial_sum[0] = partial[0]; - - for (i = 1; i < n-1; i=i+1) begin:slice + for (i = 0; i < n; i=i+1) begin:slice \$__mul #( .A_SIGNED(A_SIGNED), .B_SIGNED(sign_headroom), .A_WIDTH(A_WIDTH), - .B_WIDTH(`DSP_B_MAXWIDTH), + .B_WIDTH(`DSP_B_MAXWIDTH_PARTIAL), .Y_WIDTH(partial_Y_WIDTH) ) mul ( .A(A), - .B({{sign_headroom{1'b0}}, B[i*(`DSP_B_MAXWIDTH-sign_headroom) +: `DSP_B_MAXWIDTH-sign_headroom]}), + .B({{sign_headroom{1'b0}}, B[i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom) +: `DSP_B_MAXWIDTH_PARTIAL-sign_headroom]}), .Y(partial[i]) ); - // TODO: Currently a 'cascade' approach to summing the partial + // TODO: Currently a 'cascade' approach to summing the partial // products is taken here, but a more efficient 'binary // reduction' approach also exists... - assign partial_sum[i] = (partial[i] << i*(`DSP_B_MAXWIDTH-sign_headroom)) + partial_sum[i-1]; + if (i == 0) + assign partial_sum[i] = partial[i]; + else + assign partial_sum[i] = (partial[i] << i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[i-1]; end - localparam last_B_WIDTH = B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH-sign_headroom); \$__mul #( .A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), @@ -249,10 +214,10 @@ module \$__mul (A, B, Y); .B(B[B_WIDTH-1 -: last_B_WIDTH]), .Y(last_partial) ); - assign partial_sum[n-1] = (last_partial << (n-1)*(`DSP_B_MAXWIDTH-sign_headroom)) + partial_sum[n-2]; - assign Y = partial_sum[n-1]; + assign partial_sum[n] = (last_partial << n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[n-1]; + assign Y = partial_sum[n]; end - else begin + else begin if (A_SIGNED) wire signed [`DSP_A_MAXWIDTH-1:0] Aext = $signed(A); else @@ -274,11 +239,12 @@ module \$__mul (A, B, Y); .Y(Y) ); end + end endgenerate endmodule -(* techmap_celltype = "$__mul" *) -module $__soft_mul (A, B, Y); +(* techmap_celltype = "$mul $__mul" *) +module _90_soft_mul (A, B, Y); parameter A_SIGNED = 0; parameter B_SIGNED = 0; parameter A_WIDTH = 1; @@ -292,41 +258,41 @@ module $__soft_mul (A, B, Y); // Indirection necessary since mapping // back to $mul will cause recursion generate - if (A_SIGNED && !B_SIGNED) - \$__soft__mul #( - .A_SIGNED(A_SIGNED), - .B_SIGNED(1), - .A_WIDTH(A_WIDTH), - .B_WIDTH(B_WIDTH+1), - .Y_WIDTH(Y_WIDTH) - ) _TECHMAP_REPLACE_ ( - .A(A), - .B({1'b0,B}), - .Y(Y) - ); - else if (!A_SIGNED && B_SIGNED) - \$__soft_mul #( - .A_SIGNED(1), - .B_SIGNED(B_SIGNED), - .A_WIDTH(A_WIDTH+1), - .B_WIDTH(B_WIDTH), - .Y_WIDTH(Y_WIDTH) - ) _TECHMAP_REPLACE_ ( - .A({1'b0,A}), - .B(B), - .Y(Y) - ); - else - \$__soft_mul #( - .A_SIGNED(A_SIGNED), - .B_SIGNED(B_SIGNED), - .A_WIDTH(A_WIDTH), - .B_WIDTH(B_WIDTH), - .Y_WIDTH(Y_WIDTH) - ) _TECHMAP_REPLACE_ ( - .A(A), - .B(B), - .Y(Y) - ); + if (A_SIGNED && !B_SIGNED) + \$__soft_mul #( + .A_SIGNED(A_SIGNED), + .B_SIGNED(1), + .A_WIDTH(A_WIDTH), + .B_WIDTH(B_WIDTH+1), + .Y_WIDTH(Y_WIDTH) + ) _TECHMAP_REPLACE_ ( + .A(A), + .B({1'b0,B}), + .Y(Y) + ); + else if (!A_SIGNED && B_SIGNED) + \$__soft_mul #( + .A_SIGNED(1), + .B_SIGNED(B_SIGNED), + .A_WIDTH(A_WIDTH+1), + .B_WIDTH(B_WIDTH), + .Y_WIDTH(Y_WIDTH) + ) _TECHMAP_REPLACE_ ( + .A({1'b0,A}), + .B(B), + .Y(Y) + ); + else + \$__soft_mul #( + .A_SIGNED(A_SIGNED), + .B_SIGNED(B_SIGNED), + .A_WIDTH(A_WIDTH), + .B_WIDTH(B_WIDTH), + .Y_WIDTH(Y_WIDTH) + ) _TECHMAP_REPLACE_ ( + .A(A), + .B(B), + .Y(Y) + ); endgenerate endmodule diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 265cee6d6..477b2f6f7 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -286,7 +286,7 @@ struct SynthXilinxPass : public ScriptPass if (!nodsp || help_mode) { // NB: Xilinx multipliers are signed only - run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_B_MAXWIDTH=18 -D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18", "(skip if '-nodsp')"); + run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_A_MAXWIDTH_PARTIAL=18 -D DSP_B_MAXWIDTH=18 -D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18", "(skip if '-nodsp')"); run("opt_expr -fine", " (skip if '-nodsp')"); run("wreduce", " (skip if '-nodsp')"); run("xilinx_dsp", " (skip if '-nodsp')"); -- cgit v1.2.3 From ed4b2834ef6ed811318c897bd6f8b19b6ec15f38 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 13 Aug 2019 12:19:26 -0700 Subject: Add assign PCOUT = P to DSP48E1 --- techlibs/xilinx/cells_sim.v | 2 ++ 1 file changed, 2 insertions(+) (limited to 'techlibs') diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 2731cb454..02ce0d61b 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -784,4 +784,6 @@ module DSP48E1 ( end endgenerate + assign PCOUT = P; + endmodule -- cgit v1.2.3 From e35dfc5ab591968d86259b90a643f1545e79e661 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 13 Aug 2019 16:52:15 -0700 Subject: Only swap ports if $mul and not $__mul --- techlibs/common/mul2dsp.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 71d5a5454..75b1242a2 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -93,7 +93,7 @@ module _80_mul (A, B, Y); .Y(Y) ); `endif - else if (A_WIDTH < B_WIDTH) + else if (_TECHMAP_CELLTYPE_ == "$mul" && A_WIDTH < B_WIDTH) \$mul #( .A_SIGNED(B_SIGNED), .B_SIGNED(A_SIGNED), -- cgit v1.2.3 From a7e60322878913886278d537365baf939182a1d9 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 9 Sep 2019 20:56:29 -0700 Subject: Set USE_MULT and USE_SIMD --- techlibs/xilinx/dsp_map.v | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/dsp_map.v b/techlibs/xilinx/dsp_map.v index fdd55afe3..cc37f0085 100644 --- a/techlibs/xilinx/dsp_map.v +++ b/techlibs/xilinx/dsp_map.v @@ -23,7 +23,9 @@ module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y); .INMODEREG(0), .MREG(0), .OPMODEREG(0), - .PREG(0) + .PREG(0), + .USE_MULT("MULTIPLY"), + .USE_SIMD("ONE48") ) _TECHMAP_REPLACE_ ( //Data path .A({{5{A[24]}}, A}), -- cgit v1.2.3 From bfda921d0317bfb4cb6fc9de8a556c2258b709bc Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 10 Sep 2019 13:17:47 -0700 Subject: Remove "opt_expr -fine" call --- techlibs/xilinx/synth_xilinx.cc | 1 - 1 file changed, 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 95b2c4040..e13491e2c 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -325,7 +325,6 @@ struct SynthXilinxPass : public ScriptPass if (!nodsp || help_mode) { // NB: Xilinx multipliers are signed only run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_A_MAXWIDTH_PARTIAL=18 -D DSP_B_MAXWIDTH=18 -D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18", "(skip if '-nodsp')"); - run("opt_expr -fine", " (skip if '-nodsp')"); run("wreduce", " (skip if '-nodsp')"); run("xilinx_dsp", " (skip if '-nodsp')"); run("chtype -set $mul t:$__soft_mul"," (skip if '-nodsp')"); -- cgit v1.2.3 From d3fb3081812f0fc34230aabe01b14f06a3240d56 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 10 Sep 2019 13:18:10 -0700 Subject: Rename label to map_dsp --- techlibs/xilinx/synth_xilinx.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index e13491e2c..af8ee2368 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -321,7 +321,7 @@ struct SynthXilinxPass : public ScriptPass run("techmap -map +/cmp2lut.v -D LUT_WIDTH=6"); } - if (check_label("dsp")) { + if (check_label("map_dsp")) { if (!nodsp || help_mode) { // NB: Xilinx multipliers are signed only run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_A_MAXWIDTH_PARTIAL=18 -D DSP_B_MAXWIDTH=18 -D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18", "(skip if '-nodsp')"); -- cgit v1.2.3 From 8514e7c32ebfb2ce35619063b1507416f01bd3b4 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 10 Sep 2019 14:09:21 -0700 Subject: Revert "Remove "opt_expr -fine" call" This reverts commit bfda921d0317bfb4cb6fc9de8a556c2258b709bc. --- techlibs/xilinx/synth_xilinx.cc | 1 + 1 file changed, 1 insertion(+) (limited to 'techlibs') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index af8ee2368..2cf0bd4f9 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -325,6 +325,7 @@ struct SynthXilinxPass : public ScriptPass if (!nodsp || help_mode) { // NB: Xilinx multipliers are signed only run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_A_MAXWIDTH_PARTIAL=18 -D DSP_B_MAXWIDTH=18 -D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18", "(skip if '-nodsp')"); + run("opt_expr -fine", " (skip if '-nodsp')"); run("wreduce", " (skip if '-nodsp')"); run("xilinx_dsp", " (skip if '-nodsp')"); run("chtype -set $mul t:$__soft_mul"," (skip if '-nodsp')"); -- cgit v1.2.3 From f3a55d3f06a21af06a267b3f9da8bd4df3d4aa82 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 10 Sep 2019 14:11:56 -0700 Subject: Add comment for why opt_expr is necessary --- techlibs/xilinx/synth_xilinx.cc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'techlibs') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 2cf0bd4f9..c99b77905 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -325,6 +325,8 @@ struct SynthXilinxPass : public ScriptPass if (!nodsp || help_mode) { // NB: Xilinx multipliers are signed only run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_A_MAXWIDTH_PARTIAL=18 -D DSP_B_MAXWIDTH=18 -D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18", "(skip if '-nodsp')"); + // Necessary for optimising away $shl cells, as well as $add cells + // that have inputs with 1'b0 LSBs run("opt_expr -fine", " (skip if '-nodsp')"); run("wreduce", " (skip if '-nodsp')"); run("xilinx_dsp", " (skip if '-nodsp')"); -- cgit v1.2.3 From c460d10e60648c5126fe4a105ebf608b4f8d5e1a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 10 Sep 2019 14:17:35 -0700 Subject: Remove wreduce call --- techlibs/xilinx/synth_xilinx.cc | 1 - 1 file changed, 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index c99b77905..9ad28a933 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -328,7 +328,6 @@ struct SynthXilinxPass : public ScriptPass // Necessary for optimising away $shl cells, as well as $add cells // that have inputs with 1'b0 LSBs run("opt_expr -fine", " (skip if '-nodsp')"); - run("wreduce", " (skip if '-nodsp')"); run("xilinx_dsp", " (skip if '-nodsp')"); run("chtype -set $mul t:$__soft_mul"," (skip if '-nodsp')"); } -- cgit v1.2.3 From 76eedee08928f035f00f46304d1b49e9502401c1 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 10 Sep 2019 14:26:12 -0700 Subject: Really get rid of 'opt_expr -fine' by being explicit --- techlibs/common/mul2dsp.v | 39 +++++++++++++++++++++++++++++++++------ techlibs/xilinx/synth_xilinx.cc | 3 --- 2 files changed, 33 insertions(+), 9 deletions(-) (limited to 'techlibs') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 75b1242a2..51a6c5fb9 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -148,8 +148,17 @@ module _80_mul (A, B, Y); // reduction' approach also exists... if (i == 0) assign partial_sum[i] = partial[i]; - else - assign partial_sum[i] = (partial[i] << i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[i-1]; + else begin + // Rewrite the following statement explicitly in order + // to save on a call to 'opt_expr -fine' which would + // optimise away the '<<' op and trim size of adder + //assign partial_sum[i] = (partial[i] << i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[i-1]; + wire [Y_WIDTH-1:0] shifted_sum = {partial[i], {i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom){1'b0}}}; + assign partial_sum[i] = { + partial_sum[i-1][i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)-1:0], + shifted_sum[Y_WIDTH-1:i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)] + partial_sum[i-1][Y_WIDTH-1:i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)] + }; + end end \$__mul #( @@ -163,7 +172,12 @@ module _80_mul (A, B, Y); .B(B), .Y(last_partial) ); - assign partial_sum[n] = (last_partial << n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[n-1]; + //assign partial_sum[n] = (last_partial << n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[n-1]; + wire [Y_WIDTH-1:0] shifted_sum = {last_partial, {n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom){1'b0}}}; + assign partial_sum[n] = { + partial_sum[n-1][n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)-1:0], + shifted_sum[Y_WIDTH-1:n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)] + partial_sum[n-1][Y_WIDTH-1:n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)] + }; assign Y = partial_sum[n]; end else if (B_WIDTH > `DSP_B_MAXWIDTH) begin @@ -199,8 +213,16 @@ module _80_mul (A, B, Y); // reduction' approach also exists... if (i == 0) assign partial_sum[i] = partial[i]; - else - assign partial_sum[i] = (partial[i] << i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[i-1]; + else begin + // Rewrite the following statement explicitly in order + // to save on a call to 'opt_expr -fine' which would + // optimise away the '<<' op and trim size of adder + wire [Y_WIDTH-1:0] shifted_sum = {partial[i], {i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom){1'b0}}}; + assign partial_sum[i] = { + partial_sum[i-1][i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)-1:0], + shifted_sum[Y_WIDTH-1:i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)] + partial_sum[i-1][Y_WIDTH-1:i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)] + }; + end end \$__mul #( @@ -214,7 +236,12 @@ module _80_mul (A, B, Y); .B(B[B_WIDTH-1 -: last_B_WIDTH]), .Y(last_partial) ); - assign partial_sum[n] = (last_partial << n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[n-1]; + //assign partial_sum[n] = (last_partial << n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[n-1]; + wire [Y_WIDTH-1:0] shifted_sum = {last_partial, {n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom){1'b0}}}; + assign partial_sum[n] = { + partial_sum[n-1][n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)-1:0], + shifted_sum[Y_WIDTH-1:n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)] + partial_sum[n-1][Y_WIDTH-1:n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)] + }; assign Y = partial_sum[n]; end else begin diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 9ad28a933..4ca8a4667 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -325,9 +325,6 @@ struct SynthXilinxPass : public ScriptPass if (!nodsp || help_mode) { // NB: Xilinx multipliers are signed only run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_A_MAXWIDTH_PARTIAL=18 -D DSP_B_MAXWIDTH=18 -D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18", "(skip if '-nodsp')"); - // Necessary for optimising away $shl cells, as well as $add cells - // that have inputs with 1'b0 LSBs - run("opt_expr -fine", " (skip if '-nodsp')"); run("xilinx_dsp", " (skip if '-nodsp')"); run("chtype -set $mul t:$__soft_mul"," (skip if '-nodsp')"); } -- cgit v1.2.3 From f2d030a70f1754e7ee6bd1fb588c5abadac4dd08 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 10 Sep 2019 15:14:55 -0700 Subject: Be sensitive to signedness --- techlibs/common/mul2dsp.v | 41 +++++++++++++++++++++-------------------- 1 file changed, 21 insertions(+), 20 deletions(-) (limited to 'techlibs') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 51a6c5fb9..f2b44222e 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -153,11 +153,11 @@ module _80_mul (A, B, Y); // to save on a call to 'opt_expr -fine' which would // optimise away the '<<' op and trim size of adder //assign partial_sum[i] = (partial[i] << i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[i-1]; - wire [Y_WIDTH-1:0] shifted_sum = {partial[i], {i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom){1'b0}}}; - assign partial_sum[i] = { - partial_sum[i-1][i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)-1:0], - shifted_sum[Y_WIDTH-1:i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)] + partial_sum[i-1][Y_WIDTH-1:i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)] - }; + if (A_SIGNED && B_SIGNED) + assign partial_sum[i][Y_WIDTH-1:i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)] = partial[i] + $signed(partial_sum[i-1][Y_WIDTH-1:i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)]); + else + assign partial_sum[i][Y_WIDTH-1:i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)] = partial[i] + partial_sum[i-1][Y_WIDTH-1:i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)]; + assign partial_sum[i][i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)-1:0] = partial_sum[i-1][i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)-1:0]; end end @@ -173,11 +173,11 @@ module _80_mul (A, B, Y); .Y(last_partial) ); //assign partial_sum[n] = (last_partial << n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[n-1]; - wire [Y_WIDTH-1:0] shifted_sum = {last_partial, {n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom){1'b0}}}; - assign partial_sum[n] = { - partial_sum[n-1][n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)-1:0], - shifted_sum[Y_WIDTH-1:n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)] + partial_sum[n-1][Y_WIDTH-1:n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)] - }; + if (A_SIGNED && B_SIGNED) + assign partial_sum[n][Y_WIDTH-1:n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)] = last_partial + $signed(partial_sum[n-1][Y_WIDTH-1:n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)]); + else + assign partial_sum[n][Y_WIDTH-1:n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)] = last_partial + partial_sum[n-1][Y_WIDTH-1:n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)]; + assign partial_sum[n][n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)-1:0] = partial_sum[n-1][n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)-1:0]; assign Y = partial_sum[n]; end else if (B_WIDTH > `DSP_B_MAXWIDTH) begin @@ -217,11 +217,12 @@ module _80_mul (A, B, Y); // Rewrite the following statement explicitly in order // to save on a call to 'opt_expr -fine' which would // optimise away the '<<' op and trim size of adder - wire [Y_WIDTH-1:0] shifted_sum = {partial[i], {i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom){1'b0}}}; - assign partial_sum[i] = { - partial_sum[i-1][i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)-1:0], - shifted_sum[Y_WIDTH-1:i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)] + partial_sum[i-1][Y_WIDTH-1:i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)] - }; + //assign partial_sum[i] = (partial[i] << i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[i-1]; + if (A_SIGNED && B_SIGNED) + assign partial_sum[i][Y_WIDTH-1:i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)] = partial[i] + $signed(partial_sum[i-1][Y_WIDTH-1:i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)]); + else + assign partial_sum[i][Y_WIDTH-1:i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)] = partial[i] + partial_sum[i-1][Y_WIDTH-1:i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)]; + assign partial_sum[i][i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)-1:0] = partial_sum[i-1][i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)-1:0]; end end @@ -237,11 +238,11 @@ module _80_mul (A, B, Y); .Y(last_partial) ); //assign partial_sum[n] = (last_partial << n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[n-1]; - wire [Y_WIDTH-1:0] shifted_sum = {last_partial, {n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom){1'b0}}}; - assign partial_sum[n] = { - partial_sum[n-1][n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)-1:0], - shifted_sum[Y_WIDTH-1:n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)] + partial_sum[n-1][Y_WIDTH-1:n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)] - }; + if (A_SIGNED && B_SIGNED) + assign partial_sum[n][Y_WIDTH-1:n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)] = last_partial + partial_sum[n-1][Y_WIDTH-1:n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)]; + else + assign partial_sum[n][Y_WIDTH-1:n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)] = last_partial + $signed(partial_sum[n-1][Y_WIDTH-1:n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)]); + assign partial_sum[n][n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)-1:0] = partial_sum[n-1][n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)-1:0]; assign Y = partial_sum[n]; end else begin -- cgit v1.2.3 From 5c1271c51c41b8a067ecf6165d3e09a73eee5fb7 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 10 Sep 2019 15:26:56 -0700 Subject: Move "(skip if -nodsp)" message to label --- techlibs/xilinx/synth_xilinx.cc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 4ca8a4667..83be66daa 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -321,12 +321,12 @@ struct SynthXilinxPass : public ScriptPass run("techmap -map +/cmp2lut.v -D LUT_WIDTH=6"); } - if (check_label("map_dsp")) { + if (check_label("map_dsp"), "(skip if '-nodsp')") { if (!nodsp || help_mode) { // NB: Xilinx multipliers are signed only - run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_A_MAXWIDTH_PARTIAL=18 -D DSP_B_MAXWIDTH=18 -D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18", "(skip if '-nodsp')"); - run("xilinx_dsp", " (skip if '-nodsp')"); - run("chtype -set $mul t:$__soft_mul"," (skip if '-nodsp')"); + run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_A_MAXWIDTH_PARTIAL=18 -D DSP_B_MAXWIDTH=18 -D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18"); + run("xilinx_dsp"); + run("chtype -set $mul t:$__soft_mul"); } } -- cgit v1.2.3 From 0ebbecf833712165c495fc15fe67b6287cf1fb72 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 11 Sep 2019 13:06:59 -0700 Subject: Missing space --- techlibs/xilinx/synth_xilinx.cc | 1 + 1 file changed, 1 insertion(+) (limited to 'techlibs') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 3d92c3e2c..e822d9b7e 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -83,6 +83,7 @@ struct SynthXilinxPass : public ScriptPass log("\n"); log(" -nodsp\n"); log(" do not use DSP48E1s to implement multipliers and associated logic\n"); + log("\n"); log(" -iopad\n"); log(" enable I/O buffer insertion (selected automatically by -ise)\n"); log("\n"); -- cgit v1.2.3 From 3a390733027584071d0cd3b2d99c738ce6f1a829 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 12 Sep 2019 17:10:43 -0700 Subject: Set more ports explicitly --- techlibs/xilinx/dsp_map.v | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/dsp_map.v b/techlibs/xilinx/dsp_map.v index cc37f0085..8901b215b 100644 --- a/techlibs/xilinx/dsp_map.v +++ b/techlibs/xilinx/dsp_map.v @@ -25,7 +25,8 @@ module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y); .OPMODEREG(0), .PREG(0), .USE_MULT("MULTIPLY"), - .USE_SIMD("ONE48") + .USE_SIMD("ONE48"), + .USE_DPORT("FALSE") ) _TECHMAP_REPLACE_ ( //Data path .A({{5{A[24]}}, A}), -- cgit v1.2.3 From 6bb8e6a7267b4e3d8c1717cde87d41d04fdac82d Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 12 Sep 2019 17:11:01 -0700 Subject: Initial DSP48E1 box support --- techlibs/xilinx/abc_map.v | 216 ++++++++++++++++++++++++++ techlibs/xilinx/abc_model.v | 108 +++++++++++++ techlibs/xilinx/abc_unmap.v | 176 +++++++++++++++++++++ techlibs/xilinx/abc_xc7.box | 367 ++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 867 insertions(+) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v index 0c85d6656..be69ae256 100644 --- a/techlibs/xilinx/abc_map.v +++ b/techlibs/xilinx/abc_map.v @@ -121,3 +121,219 @@ module SRLC32E ( ); \$__ABC_LUT6 q (.A(\$Q ), .S({1'b1, A}), .Y(Q)); endmodule + +module DSP48E1 ( + output [29:0] ACOUT, + output [17:0] BCOUT, + output reg CARRYCASCOUT, + output reg [3:0] CARRYOUT, + output reg MULTSIGNOUT, + output OVERFLOW, + output reg signed [47:0] P, + output PATTERNBDETECT, + output PATTERNDETECT, + output [47:0] PCOUT, + output UNDERFLOW, + input signed [29:0] A, + input [29:0] ACIN, + input [3:0] ALUMODE, + input signed [17:0] B, + input [17:0] BCIN, + input [47:0] C, + input CARRYCASCIN, + input CARRYIN, + input [2:0] CARRYINSEL, + input CEA1, + input CEA2, + input CEAD, + input CEALUMODE, + input CEB1, + input CEB2, + input CEC, + input CECARRYIN, + input CECTRL, + input CED, + input CEINMODE, + input CEM, + input CEP, + input CLK, + input [24:0] D, + input [4:0] INMODE, + input MULTSIGNIN, + input [6:0] OPMODE, + input [47:0] PCIN, + input RSTA, + input RSTALLCARRYIN, + input RSTALUMODE, + input RSTB, + input RSTC, + input RSTCTRL, + input RSTD, + input RSTINMODE, + input RSTM, + input RSTP +); + parameter integer ACASCREG = 1; + parameter integer ADREG = 1; + parameter integer ALUMODEREG = 1; + parameter integer AREG = 1; + parameter AUTORESET_PATDET = "NO_RESET"; + parameter A_INPUT = "DIRECT"; + parameter integer BCASCREG = 1; + parameter integer BREG = 1; + parameter B_INPUT = "DIRECT"; + parameter integer CARRYINREG = 1; + parameter integer CARRYINSELREG = 1; + parameter integer CREG = 1; + parameter integer DREG = 1; + parameter integer INMODEREG = 1; + parameter integer MREG = 1; + parameter integer OPMODEREG = 1; + parameter integer PREG = 1; + parameter SEL_MASK = "MASK"; + parameter SEL_PATTERN = "PATTERN"; + parameter USE_DPORT = "FALSE"; + parameter USE_MULT = "MULTIPLY"; + parameter USE_PATTERN_DETECT = "NO_PATDET"; + parameter USE_SIMD = "ONE48"; + parameter [47:0] MASK = 48'h3FFFFFFFFFFF; + parameter [47:0] PATTERN = 48'h000000000000; + parameter [3:0] IS_ALUMODE_INVERTED = 4'b0; + parameter [0:0] IS_CARRYIN_INVERTED = 1'b0; + parameter [0:0] IS_CLK_INVERTED = 1'b0; + parameter [4:0] IS_INMODE_INVERTED = 5'b0; + parameter [6:0] IS_OPMODE_INVERTED = 7'b0; + + parameter _TECHMAP_CELLTYPE_ = ""; + + generate + if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin + wire [29:0] iA; + wire [17:0] iB; + wire [47:0] iC; + wire [24:0] iD; + + wire pA, pB, pC, pD, pAD, pM, pP; + wire [47:0] oP, oPCOUT; + + // Disconnect the A-input if MREG is enabled, since + // combinatorial path is broken + if (AREG == 0 || MREG == 1 || PREG == 1) + assign iA = A; + else + \$__ABC_DSP48E1_REG rA (.I(A), .O(iA), .Q(pA)); + if (BREG == 0 || MREG == 1 || PREG == 1) + assign iB = B; + else + \$__ABC_DSP48E1_REG rB (.I(B), .O(iB), .Q(pB)); + if (CREG == 0 || PREG == 1) + assign iC = C; + else + \$__ABC_DSP48E1_REG rC (.I(C), .O(iC), .Q(pC)); + if (DREG == 0) + assign iD = D; + else if (_TECHMAP_CELLTYPE_ != "") + $error("Invalid DSP48E1 configuration: DREG enabled but USE_DPORT == \"FALSE\""); + if (ADREG == 1 && _TECHMAP_CELLTYPE_ != "") + $error("Invalid DSP48E1 configuration: ADREG enabled but USE_DPORT == \"FALSE\""); + if (PREG == 0) begin + if (MREG == 1) + \$__ABC_DSP48E1_REG rM (.Q(pM)); + end + else + \$__ABC_DSP48E1_REG rP (.Q(pP)); + + \$__ABC_DSP48E1_MULT_P_MUX muxP ( + .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oP), .Pq(pP), .O(P) + ); + \$__ABC_DSP48E1_MULT_PCOUT_MUX muxPCOUT ( + .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oPCOUT), .Pq(pP), .O(PCOUT) + ); + + \$__ABC_DSP48E1_MULT #( + .ACASCREG(ACASCREG), + .ADREG(ADREG), + .ALUMODEREG(ALUMODEREG), + .AREG(AREG), + .AUTORESET_PATDET(AUTORESET_PATDET), + .A_INPUT(A_INPUT), + .BCASCREG(BCASCREG), + .BREG(BREG), + .B_INPUT(B_INPUT), + .CARRYINREG(CARRYINREG), + .CARRYINSELREG(CARRYINSELREG), + .CREG(CREG), + .DREG(DREG), + .INMODEREG(INMODEREG), + .MREG(MREG), + .OPMODEREG(OPMODEREG), + .PREG(PREG), + .SEL_MASK(SEL_MASK), + .SEL_PATTERN(SEL_PATTERN), + .USE_DPORT(USE_DPORT), + .USE_MULT(USE_MULT), + .USE_PATTERN_DETECT(USE_PATTERN_DETECT), + .USE_SIMD(USE_SIMD), + .MASK(MASK), + .PATTERN(PATTERN), + .IS_ALUMODE_INVERTED(IS_ALUMODE_INVERTED), + .IS_CARRYIN_INVERTED(IS_CARRYIN_INVERTED), + .IS_CLK_INVERTED(IS_CLK_INVERTED), + .IS_INMODE_INVERTED(IS_INMODE_INVERTED), + .IS_OPMODE_INVERTED(IS_OPMODE_INVERTED) + ) _TECHMAP_REPLACE_ ( + .ACOUT(ACOUT), + .BCOUT(BCOUT), + .CARRYCASCOUT(CARRYCASCOUT), + .CARRYOUT(CARRYOUT), + .MULTSIGNOUT(MULTSIGNOUT), + .OVERFLOW(OVERFLOW), + .P(oP), + .PATTERNBDETECT(PATTERNBDETECT), + .PATTERNDETECT(PATTERNDETECT), + .PCOUT(oPCOUT), + .UNDERFLOW(UNDERFLOW), + .A(iA), + .ACIN(ACIN), + .ALUMODE(ALUMODE), + .B(iB), + .BCIN(BCIN), + .C(iC), + .CARRYCASCIN(CARRYCASCIN), + .CARRYIN(CARRYIN), + .CARRYINSEL(CARRYINSEL), + .CEA1(CEA1), + .CEA2(CEA2), + .CEAD(CEAD), + .CEALUMODE(CEALUMODE), + .CEB1(CEB1), + .CEB2(CEB2), + .CEC(CEC), + .CECARRYIN(CECARRYIN), + .CECTRL(CECTRL), + .CED(CED), + .CEINMODE(CEINMODE), + .CEM(CEM), + .CEP(CEP), + .CLK(CLK), + .D(iD), + .INMODE(INMODE), + .MULTSIGNIN(MULTSIGNIN), + .OPMODE(OPMODE), + .PCIN(PCIN), + .RSTA(RSTA), + .RSTALLCARRYIN(RSTALLCARRYIN), + .RSTALUMODE(RSTALUMODE), + .RSTB(RSTB), + .RSTC(RSTC), + .RSTCTRL(RSTCTRL), + .RSTD(RSTD), + .RSTINMODE(RSTINMODE), + .RSTM(RSTM), + .RSTP(RSTP) + ); + end + else + wire _TECHMAP_FAIL_ = 1; + endgenerate +endmodule diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc_model.v index 655b993f6..95a368306 100644 --- a/techlibs/xilinx/abc_model.v +++ b/techlibs/xilinx/abc_model.v @@ -20,15 +20,123 @@ // ============================================================================ +// Box containing MUXF7.[AB] + MUXF8, +// Necessary to make these an atomic unit so that +// ABC cannot optimise just one of the MUXF7 away +// and expect to save on its delay (* abc_box_id = 3, lib_whitebox *) module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1); assign O = S1 ? (S0 ? I3 : I2) : (S0 ? I1 : I0); endmodule +// Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32} +// Necessary since RAMD* and SRL* have both combinatorial (i.e. +// same-cycle read operation) and sequential (write operation +// is only committed on the next clock edge). +// To model the combinatorial path, such cells have to be split +// into comb and seq parts, with this box modelling only the former. (* abc_box_id=2000 *) module \$__ABC_LUT6 (input A, input [5:0] S, output Y); endmodule +// Box to emulate comb/seq behaviour of RAMD128 (* abc_box_id=2001 *) module \$__ABC_LUT7 (input A, input [6:0] S, output Y); endmodule + +(* abc_box_id=2100 *) +module \$__ABC_DSP48E1_MULT_P_MUX (input Aq, ADq, Bq, Cq, Dq, Mq, input [47:0] P, input Pq, output [47:0] O); +endmodule +(* abc_box_id=2101 *) +module \$__ABC_DSP48E1_MULT_PCOUT_MUX (input Aq, ADq, Bq, Cq, Dq, Mq, input [47:0] P, input Pq, output [47:0] O); +endmodule + +// Box used to represent the comb/seq behaviour of DSP48E1 +// abc_map.v is responsible for disconnecting inputs to +// the combinatorial DSP48E1 model by a register (e.g. +// disconnecting A when AREG, MREG or PREG is enabled) +(* abc_box_id=3000 *) +module \$__ABC_DSP48E1_MULT ( + output [29:0] ACOUT, + output [17:0] BCOUT, + output reg CARRYCASCOUT, + output reg [3:0] CARRYOUT, + output reg MULTSIGNOUT, + output OVERFLOW, + output reg signed [47:0] P, + output PATTERNBDETECT, + output PATTERNDETECT, + output [47:0] PCOUT, + output UNDERFLOW, + input signed [29:0] A, + input [29:0] ACIN, + input [3:0] ALUMODE, + input signed [17:0] B, + input [17:0] BCIN, + input [47:0] C, + input CARRYCASCIN, + input CARRYIN, + input [2:0] CARRYINSEL, + input CEA1, + input CEA2, + input CEAD, + input CEALUMODE, + input CEB1, + input CEB2, + input CEC, + input CECARRYIN, + input CECTRL, + input CED, + input CEINMODE, + input CEM, + input CEP, + input CLK, + input [24:0] D, + input [4:0] INMODE, + input MULTSIGNIN, + input [6:0] OPMODE, + input [47:0] PCIN, + input RSTA, + input RSTALLCARRYIN, + input RSTALUMODE, + input RSTB, + input RSTC, + input RSTCTRL, + input RSTD, + input RSTINMODE, + input RSTM, + input RSTP +); + parameter integer ACASCREG = 1; + parameter integer ADREG = 1; + parameter integer ALUMODEREG = 1; + parameter integer AREG = 1; + parameter AUTORESET_PATDET = "NO_RESET"; + parameter A_INPUT = "DIRECT"; + parameter integer BCASCREG = 1; + parameter integer BREG = 1; + parameter B_INPUT = "DIRECT"; + parameter integer CARRYINREG = 1; + parameter integer CARRYINSELREG = 1; + parameter integer CREG = 1; + parameter integer DREG = 1; + parameter integer INMODEREG = 1; + parameter integer MREG = 1; + parameter integer OPMODEREG = 1; + parameter integer PREG = 1; + parameter SEL_MASK = "MASK"; + parameter SEL_PATTERN = "PATTERN"; + parameter USE_DPORT = "FALSE"; + parameter USE_MULT = "MULTIPLY"; + parameter USE_PATTERN_DETECT = "NO_PATDET"; + parameter USE_SIMD = "ONE48"; + parameter [47:0] MASK = 48'h3FFFFFFFFFFF; + parameter [47:0] PATTERN = 48'h000000000000; + parameter [3:0] IS_ALUMODE_INVERTED = 4'b0; + parameter [0:0] IS_CARRYIN_INVERTED = 1'b0; + parameter [0:0] IS_CLK_INVERTED = 1'b0; + parameter [4:0] IS_INMODE_INVERTED = 5'b0; + parameter [6:0] IS_OPMODE_INVERTED = 7'b0; +endmodule + + diff --git a/techlibs/xilinx/abc_unmap.v b/techlibs/xilinx/abc_unmap.v index f101a22d0..bcb1069bc 100644 --- a/techlibs/xilinx/abc_unmap.v +++ b/techlibs/xilinx/abc_unmap.v @@ -26,3 +26,179 @@ endmodule module \$__ABC_LUT7 (input A, input [6:0] S, output Y); assign Y = A; endmodule + +module \$__ABC_DSP48E1_REG (input [47:0] I, output [47:0] O, output Q); + assign O = I; +endmodule +module \$__ABC_DSP48E1_MULT_P_MUX (input Aq, Bq, Cq, Dq, ADq, Mq, input [47:0] P, input Pq, output [47:0] O); + assign O = P; +endmodule +module \$__ABC_DSP48E1_MULT_PCOUT_MUX (input Aq, Bq, Cq, Dq, ADq, Mq, input [47:0] P, input Pq, output [47:0] O); + assign O = P; +endmodule + +module \$__ABC_DSP48E1_MULT ( + output [29:0] ACOUT, + output [17:0] BCOUT, + output reg CARRYCASCOUT, + output reg [3:0] CARRYOUT, + output reg MULTSIGNOUT, + output OVERFLOW, + output reg signed [47:0] P, + output PATTERNBDETECT, + output PATTERNDETECT, + output [47:0] PCOUT, + output UNDERFLOW, + input signed [29:0] A, + input [29:0] ACIN, + input [3:0] ALUMODE, + input signed [17:0] B, + input [17:0] BCIN, + input [47:0] C, + input CARRYCASCIN, + input CARRYIN, + input [2:0] CARRYINSEL, + input CEA1, + input CEA2, + input CEAD, + input CEALUMODE, + input CEB1, + input CEB2, + input CEC, + input CECARRYIN, + input CECTRL, + input CED, + input CEINMODE, + input CEM, + input CEP, + input CLK, + input [24:0] D, + input [4:0] INMODE, + input MULTSIGNIN, + input [6:0] OPMODE, + input [47:0] PCIN, + input RSTA, + input RSTALLCARRYIN, + input RSTALUMODE, + input RSTB, + input RSTC, + input RSTCTRL, + input RSTD, + input RSTINMODE, + input RSTM, + input RSTP +); + parameter integer ACASCREG = 1; + parameter integer ADREG = 1; + parameter integer ALUMODEREG = 1; + parameter integer AREG = 1; + parameter AUTORESET_PATDET = "NO_RESET"; + parameter A_INPUT = "DIRECT"; + parameter integer BCASCREG = 1; + parameter integer BREG = 1; + parameter B_INPUT = "DIRECT"; + parameter integer CARRYINREG = 1; + parameter integer CARRYINSELREG = 1; + parameter integer CREG = 1; + parameter integer DREG = 1; + parameter integer INMODEREG = 1; + parameter integer MREG = 1; + parameter integer OPMODEREG = 1; + parameter integer PREG = 1; + parameter SEL_MASK = "MASK"; + parameter SEL_PATTERN = "PATTERN"; + parameter USE_DPORT = "FALSE"; + parameter USE_MULT = "MULTIPLY"; + parameter USE_PATTERN_DETECT = "NO_PATDET"; + parameter USE_SIMD = "ONE48"; + parameter [47:0] MASK = 48'h3FFFFFFFFFFF; + parameter [47:0] PATTERN = 48'h000000000000; + parameter [3:0] IS_ALUMODE_INVERTED = 4'b0; + parameter [0:0] IS_CARRYIN_INVERTED = 1'b0; + parameter [0:0] IS_CLK_INVERTED = 1'b0; + parameter [4:0] IS_INMODE_INVERTED = 5'b0; + parameter [6:0] IS_OPMODE_INVERTED = 7'b0; + + DSP48E1 #( + .ACASCREG(ACASCREG), + .ADREG(ADREG), + .ALUMODEREG(ALUMODEREG), + .AREG(AREG), + .AUTORESET_PATDET(AUTORESET_PATDET), + .A_INPUT(A_INPUT), + .BCASCREG(BCASCREG), + .BREG(BREG), + .B_INPUT(B_INPUT), + .CARRYINREG(CARRYINREG), + .CARRYINSELREG(CARRYINSELREG), + .CREG(CREG), + .DREG(DREG), + .INMODEREG(INMODEREG), + .MREG(MREG), + .OPMODEREG(OPMODEREG), + .PREG(PREG), + .SEL_MASK(SEL_MASK), + .SEL_PATTERN(SEL_PATTERN), + .USE_DPORT(USE_DPORT), + .USE_MULT(USE_MULT), + .USE_PATTERN_DETECT(USE_PATTERN_DETECT), + .USE_SIMD(USE_SIMD), + .MASK(MASK), + .PATTERN(PATTERN), + .IS_ALUMODE_INVERTED(IS_ALUMODE_INVERTED), + .IS_CARRYIN_INVERTED(IS_CARRYIN_INVERTED), + .IS_CLK_INVERTED(IS_CLK_INVERTED), + .IS_INMODE_INVERTED(IS_INMODE_INVERTED), + .IS_OPMODE_INVERTED(IS_OPMODE_INVERTED) + ) _TECHMAP_REPLACE_ ( + .ACOUT(ACOUT), + .BCOUT(BCOUT), + .CARRYCASCOUT(CARRYCASCOUT), + .CARRYOUT(CARRYOUT), + .MULTSIGNOUT(MULTSIGNOUT), + .OVERFLOW(OVERFLOW), + .P(P), + .PATTERNBDETECT(PATTERNBDETECT), + .PATTERNDETECT(PATTERNDETECT), + .PCOUT(PCOUT), + .UNDERFLOW(UNDERFLOW), + .A(A), + .ACIN(ACIN), + .ALUMODE(ALUMODE), + .B(B), + .BCIN(BCIN), + .C(C), + .CARRYCASCIN(CARRYCASCIN), + .CARRYIN(CARRYIN), + .CARRYINSEL(CARRYINSEL), + .CEA1(CEA1), + .CEA2(CEA2), + .CEAD(CEAD), + .CEALUMODE(CEALUMODE), + .CEB1(CEB1), + .CEB2(CEB2), + .CEC(CEC), + .CECARRYIN(CECARRYIN), + .CECTRL(CECTRL), + .CED(CED), + .CEINMODE(CEINMODE), + .CEM(CEM), + .CEP(CEP), + .CLK(CLK), + .D(D), + .INMODE(INMODE), + .MULTSIGNIN(MULTSIGNIN), + .OPMODE(OPMODE), + .PCIN(PCIN), + .RSTA(RSTA), + .RSTALLCARRYIN(RSTALLCARRYIN), + .RSTALUMODE(RSTALUMODE), + .RSTB(RSTB), + .RSTC(RSTC), + .RSTCTRL(RSTCTRL), + .RSTD(RSTD), + .RSTINMODE(RSTINMODE), + .RSTM(RSTM), + .RSTP(RSTP) + ); +endmodule diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box index 20da3b8a0..bbd38d90c 100644 --- a/techlibs/xilinx/abc_xc7.box +++ b/techlibs/xilinx/abc_xc7.box @@ -59,3 +59,370 @@ $__ABC_LUT6 2000 0 7 1 # Outputs: DPO SPO $__ABC_LUT7 2001 0 8 1 0 1047 1036 877 812 643 532 478 + +$__ABC_DSP48E1_MULT_P_MUX 2100 0 55 48 +# A AD B C D M P Pq +2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 +2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 +2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 +2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 +2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 +2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 +2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 +2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 +2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 +2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 +2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 +2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 +2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 +2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 +2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 +2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 +2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 +2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 +2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 +2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 +2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 +2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 +2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 +2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 +2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 +2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 +2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 +2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 +2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 +2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 +2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 +2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 +2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 +2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 +2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 +2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 +2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 +2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 +2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 +2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 +2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 +2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 +2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 +2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 +2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 +2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 +2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 +2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 + +$__ABC_DSP48E1_MULT_PCOUT_MUX 2101 0 55 48 +# A AD B C D M P Pq +3098 - 2960 1835 - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435 +3098 - 2960 1835 - 1819 0 0 0 0 0 0 0 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- - - - - - - - - - - - - - - - - - - - - - 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 - - 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 - +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 - - 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 - +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 - - 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 - +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 - - 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 - +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 - - 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 - +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 - - 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 - +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 - - 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 - +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 - - 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 - +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 - - 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 - +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 - - 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 - +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 - - 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 - +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- cgit v1.2.3 From aaeaab4ac035aaf79f46873e27b8d464675d1c9c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 12 Sep 2019 17:45:02 -0700 Subject: Rename to techmap_guard --- techlibs/xilinx/abc_map.v | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v index be69ae256..f52397c9f 100644 --- a/techlibs/xilinx/abc_map.v +++ b/techlibs/xilinx/abc_map.v @@ -205,6 +205,7 @@ module DSP48E1 ( parameter [6:0] IS_OPMODE_INVERTED = 7'b0; parameter _TECHMAP_CELLTYPE_ = ""; + localparam techmap_guard = (_TECHMAP_CELLTYPE_ != ""); generate if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin @@ -232,9 +233,9 @@ module DSP48E1 ( \$__ABC_DSP48E1_REG rC (.I(C), .O(iC), .Q(pC)); if (DREG == 0) assign iD = D; - else if (_TECHMAP_CELLTYPE_ != "") + else if (techmap_guard) $error("Invalid DSP48E1 configuration: DREG enabled but USE_DPORT == \"FALSE\""); - if (ADREG == 1 && _TECHMAP_CELLTYPE_ != "") + if (ADREG == 1 && techmap_guard) $error("Invalid DSP48E1 configuration: ADREG enabled but USE_DPORT == \"FALSE\""); if (PREG == 0) begin if (MREG == 1) -- cgit v1.2.3 From c52863f147c45727dc38dd349f3f5d756baf27ce Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 12 Sep 2019 18:01:49 -0700 Subject: Finish explanation --- techlibs/xilinx/abc_model.v | 14 ++++++++++---- techlibs/xilinx/abc_xc7.box | 11 ++++++++++- 2 files changed, 20 insertions(+), 5 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc_model.v index 95a368306..504f8a0d8 100644 --- a/techlibs/xilinx/abc_model.v +++ b/techlibs/xilinx/abc_model.v @@ -44,6 +44,16 @@ endmodule module \$__ABC_LUT7 (input A, input [6:0] S, output Y); endmodule +// Boxes used to represent the comb/seq behaviour of DSP48E1 +// With abc_map.v responsible for disconnecting inputs to +// the combinatorial DSP48E1 model by a register (e.g. +// disconnecting A when AREG, MREG or PREG is enabled) +// this mux captures the existence of a replacement path +// between AREG/BREG/CREG/etc. and P/PCOUT. +// Since the Aq/ADq/Bq/etc. inputs are assumed to arrive at +// the mux at zero time, the combinatorial delay through +// these muxes thus represents the clock-to-q delay at +// P/PCOUT. (* abc_box_id=2100 *) module \$__ABC_DSP48E1_MULT_P_MUX (input Aq, ADq, Bq, Cq, Dq, Mq, input [47:0] P, input Pq, output [47:0] O); endmodule @@ -51,10 +61,6 @@ endmodule module \$__ABC_DSP48E1_MULT_PCOUT_MUX (input Aq, ADq, Bq, Cq, Dq, Mq, input [47:0] P, input Pq, output [47:0] O); endmodule -// Box used to represent the comb/seq behaviour of DSP48E1 -// abc_map.v is responsible for disconnecting inputs to -// the combinatorial DSP48E1 model by a register (e.g. -// disconnecting A when AREG, MREG or PREG is enabled) (* abc_box_id=3000 *) module \$__ABC_DSP48E1_MULT ( output [29:0] ACOUT, diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box index bbd38d90c..e4b1dcd32 100644 --- a/techlibs/xilinx/abc_xc7.box +++ b/techlibs/xilinx/abc_xc7.box @@ -60,6 +60,16 @@ $__ABC_LUT6 2000 0 7 1 $__ABC_LUT7 2001 0 8 1 0 1047 1036 877 812 643 532 478 +# Boxes used to represent the comb/seq behaviour of DSP48E1 +# With abc_map.v responsible for disconnecting inputs to +# the combinatorial DSP48E1 model by a register (e.g. +# disconnecting A when AREG, MREG or PREG is enabled) +# this mux captures the existence of a replacement path +# between AREG/BREG/CREG/etc. and P/PCOUT. +# Since the Aq/ADq/Bq/etc. inputs are assumed to arrive at +# the mux at zero time, the combinatorial delay through +# these muxes thus represents the clock-to-q delay at +# P/PCOUT. $__ABC_DSP48E1_MULT_P_MUX 2100 0 55 48 # A AD B C D M P Pq 2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 @@ -110,7 +120,6 @@ $__ABC_DSP48E1_MULT_P_MUX 2100 0 55 48 2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 - $__ABC_DSP48E1_MULT_PCOUT_MUX 2101 0 55 48 # A AD B C D M P Pq 3098 - 2960 1835 - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435 -- cgit v1.2.3 From 734034a8727023fdb74c9a6acd2cb6d1bfe3e81c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 12 Sep 2019 18:13:46 -0700 Subject: Add an ASCII drawing --- techlibs/xilinx/abc_model.v | 25 ++++++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc_model.v index 504f8a0d8..109804f09 100644 --- a/techlibs/xilinx/abc_model.v +++ b/techlibs/xilinx/abc_model.v @@ -48,12 +48,31 @@ endmodule // With abc_map.v responsible for disconnecting inputs to // the combinatorial DSP48E1 model by a register (e.g. // disconnecting A when AREG, MREG or PREG is enabled) -// this mux captures the existence of a replacement path -// between AREG/BREG/CREG/etc. and P/PCOUT. +// this blackbox captures the existence of a replacement +// path between AREG/BREG/CREG/etc. and P/PCOUT. // Since the Aq/ADq/Bq/etc. inputs are assumed to arrive at -// the mux at zero time, the combinatorial delay through +// the box at zero time, the combinatorial delay through // these muxes thus represents the clock-to-q delay at // P/PCOUT. +// Doing so should means that ABC is able to analyse the +// worst-case delay through to P. +// However, the true value of being as complete as this is +// questionable since if AREG=1 and BREG=0 (as below) +// then the worse-case path would very likely be through B +// and very unlikely to be through AREG.Q...? +// +// In graphical form: +// +// NEW "PI" >>---+ +// for AREG.Q | +// | +// +---------+ | __ +// A --X X-| | +--| \ +// | DSP48E1 |P | |--- P +// | AREG=1 |-------|__/ +// B ------| | +// +---------+ +// (* abc_box_id=2100 *) module \$__ABC_DSP48E1_MULT_P_MUX (input Aq, ADq, Bq, Cq, Dq, Mq, input [47:0] P, input Pq, output [47:0] O); endmodule -- cgit v1.2.3 From e235dd07854ad31617a4609c59dbdeacb9323ad0 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 13 Sep 2019 09:34:40 -0700 Subject: Refine diagram --- techlibs/xilinx/abc_model.v | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc_model.v index 109804f09..5963258e8 100644 --- a/techlibs/xilinx/abc_model.v +++ b/techlibs/xilinx/abc_model.v @@ -52,10 +52,12 @@ endmodule // path between AREG/BREG/CREG/etc. and P/PCOUT. // Since the Aq/ADq/Bq/etc. inputs are assumed to arrive at // the box at zero time, the combinatorial delay through -// these muxes thus represents the clock-to-q delay at -// P/PCOUT. +// these boxes thus represents the clock-to-q delay +// (arrival time) at P/PCOUT. // Doing so should means that ABC is able to analyse the -// worst-case delay through to P. +// worst-case delay through to P, regardless of if it was +// through any combinatorial paths (e.g. B, below) or an +// internal register (A2REG). // However, the true value of being as complete as this is // questionable since if AREG=1 and BREG=0 (as below) // then the worse-case path would very likely be through B @@ -63,15 +65,15 @@ endmodule // // In graphical form: // -// NEW "PI" >>---+ -// for AREG.Q | -// | -// +---------+ | __ -// A --X X-| | +--| \ -// | DSP48E1 |P | |--- P -// | AREG=1 |-------|__/ -// B ------| | -// +---------+ +// NEW "PI" >>---+ +// for AREG.Q | +// | +// +---------+ | __ +// A >>--X X-| | +--| \ +// | DSP48E1 |P | |--->> P +// | AREG=1 |-------|__/ +// B >>------| | +// +---------+ // (* abc_box_id=2100 *) module \$__ABC_DSP48E1_MULT_P_MUX (input Aq, ADq, Bq, Cq, Dq, Mq, input [47:0] P, input Pq, output [47:0] O); -- cgit v1.2.3 From 247a63f55df2e85f0aa15a9a05f436c1225f9ec1 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 13 Sep 2019 11:45:55 -0700 Subject: Add support for MULT and DPORT --- techlibs/xilinx/abc_map.v | 134 +++++++++++++++- techlibs/xilinx/abc_model.v | 90 ++++++++++- techlibs/xilinx/abc_unmap.v | 9 +- techlibs/xilinx/abc_xc7.box | 365 ++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 588 insertions(+), 10 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v index f52397c9f..27133fc1e 100644 --- a/techlibs/xilinx/abc_map.v +++ b/techlibs/xilinx/abc_map.v @@ -219,15 +219,15 @@ module DSP48E1 ( // Disconnect the A-input if MREG is enabled, since // combinatorial path is broken - if (AREG == 0 || MREG == 1 || PREG == 1) + if (AREG == 0 && MREG == 0 && PREG == 0) assign iA = A; else \$__ABC_DSP48E1_REG rA (.I(A), .O(iA), .Q(pA)); - if (BREG == 0 || MREG == 1 || PREG == 1) + if (BREG == 0 && MREG == 0 && PREG == 0) assign iB = B; else \$__ABC_DSP48E1_REG rB (.I(B), .O(iB), .Q(pB)); - if (CREG == 0 || PREG == 1) + if (CREG == 0 && PREG == 0) assign iC = C; else \$__ABC_DSP48E1_REG rC (.I(C), .O(iC), .Q(pC)); @@ -334,7 +334,133 @@ module DSP48E1 ( .RSTP(RSTP) ); end + else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin + wire [29:0] iA; + wire [17:0] iB; + wire [47:0] iC; + wire [24:0] iD; + + wire pA, pB, pC, pD, pAD, pM, pP; + wire [47:0] oP, oPCOUT; + + // Disconnect the A-input if MREG is enabled, since + // combinatorial path is broken + if (AREG == 0 && ADREG == 0 && MREG == 0 && PREG == 1) + assign iA = A; + else + \$__ABC_DSP48E1_REG rA (.I(A), .O(iA), .Q(pA)); + if (BREG == 0 && MREG == 0 && PREG == 0) + assign iB = B; + else + \$__ABC_DSP48E1_REG rB (.I(B), .O(iB), .Q(pB)); + if (CREG == 0 && PREG == 0) + assign iC = C; + else + \$__ABC_DSP48E1_REG rC (.I(C), .O(iC), .Q(pC)); + if (DREG == 0 && ADREG == 0) + assign iD = D; + else + \$__ABC_DSP48E1_REG rD (.I(D), .O(iD), .Q(pD)); + if (PREG == 0) begin + if (MREG == 1) + \$__ABC_DSP48E1_REG rM (.Q(pM)); + else if (ADREG == 1) + \$__ABC_DSP48E1_REG rAD (.Q(pAD)); + end + else + \$__ABC_DSP48E1_REG rP (.Q(pP)); + + \$__ABC_DSP48E1_MULT_DPORT_P_MUX muxP ( + .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oP), .Pq(pP), .O(P) + ); + \$__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX muxPCOUT ( + .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oPCOUT), .Pq(pP), .O(PCOUT) + ); + + \$__ABC_DSP48E1_MULT_DPORT #( + .ACASCREG(ACASCREG), + .ADREG(ADREG), + .ALUMODEREG(ALUMODEREG), + .AREG(AREG), + .AUTORESET_PATDET(AUTORESET_PATDET), + .A_INPUT(A_INPUT), + .BCASCREG(BCASCREG), + .BREG(BREG), + .B_INPUT(B_INPUT), + .CARRYINREG(CARRYINREG), + .CARRYINSELREG(CARRYINSELREG), + .CREG(CREG), + .DREG(DREG), + .INMODEREG(INMODEREG), + .MREG(MREG), + .OPMODEREG(OPMODEREG), + .PREG(PREG), + .SEL_MASK(SEL_MASK), + .SEL_PATTERN(SEL_PATTERN), + .USE_DPORT(USE_DPORT), + .USE_MULT(USE_MULT), + .USE_PATTERN_DETECT(USE_PATTERN_DETECT), + .USE_SIMD(USE_SIMD), + .MASK(MASK), + .PATTERN(PATTERN), + .IS_ALUMODE_INVERTED(IS_ALUMODE_INVERTED), + .IS_CARRYIN_INVERTED(IS_CARRYIN_INVERTED), + .IS_CLK_INVERTED(IS_CLK_INVERTED), + .IS_INMODE_INVERTED(IS_INMODE_INVERTED), + .IS_OPMODE_INVERTED(IS_OPMODE_INVERTED) + ) _TECHMAP_REPLACE_ ( + .ACOUT(ACOUT), + .BCOUT(BCOUT), + .CARRYCASCOUT(CARRYCASCOUT), + .CARRYOUT(CARRYOUT), + .MULTSIGNOUT(MULTSIGNOUT), + .OVERFLOW(OVERFLOW), + .P(oP), + .PATTERNBDETECT(PATTERNBDETECT), + .PATTERNDETECT(PATTERNDETECT), + .PCOUT(oPCOUT), + .UNDERFLOW(UNDERFLOW), + .A(iA), + .ACIN(ACIN), + .ALUMODE(ALUMODE), + .B(iB), + .BCIN(BCIN), + .C(iC), + .CARRYCASCIN(CARRYCASCIN), + .CARRYIN(CARRYIN), + .CARRYINSEL(CARRYINSEL), + .CEA1(CEA1), + .CEA2(CEA2), + .CEAD(CEAD), + .CEALUMODE(CEALUMODE), + .CEB1(CEB1), + .CEB2(CEB2), + .CEC(CEC), + .CECARRYIN(CECARRYIN), + .CECTRL(CECTRL), + .CED(CED), + .CEINMODE(CEINMODE), + .CEM(CEM), + .CEP(CEP), + .CLK(CLK), + .D(iD), + .INMODE(INMODE), + .MULTSIGNIN(MULTSIGNIN), + .OPMODE(OPMODE), + .PCIN(PCIN), + .RSTA(RSTA), + .RSTALLCARRYIN(RSTALLCARRYIN), + .RSTALUMODE(RSTALUMODE), + .RSTB(RSTB), + .RSTC(RSTC), + .RSTCTRL(RSTCTRL), + .RSTD(RSTD), + .RSTINMODE(RSTINMODE), + .RSTM(RSTM), + .RSTP(RSTP) + ); + end else - wire _TECHMAP_FAIL_ = 1; + $error("Invalid DSP48E1 configuration"); endgenerate endmodule diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc_model.v index 5963258e8..4310ad39e 100644 --- a/techlibs/xilinx/abc_model.v +++ b/techlibs/xilinx/abc_model.v @@ -81,6 +81,12 @@ endmodule (* abc_box_id=2101 *) module \$__ABC_DSP48E1_MULT_PCOUT_MUX (input Aq, ADq, Bq, Cq, Dq, Mq, input [47:0] P, input Pq, output [47:0] O); endmodule +(* abc_box_id=2102 *) +module \$__ABC_DSP48E1_MULT_DPORT_P_MUX (input Aq, ADq, Bq, Cq, Dq, Mq, input [47:0] P, input Pq, output [47:0] O); +endmodule +(* abc_box_id=2103 *) +module \$__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX (input Aq, ADq, Bq, Cq, Dq, Mq, input [47:0] P, input Pq, output [47:0] O); +endmodule (* abc_box_id=3000 *) module \$__ABC_DSP48E1_MULT ( @@ -166,4 +172,86 @@ module \$__ABC_DSP48E1_MULT ( parameter [6:0] IS_OPMODE_INVERTED = 7'b0; endmodule - +(* abc_box_id=3001 *) +module \$__ABC_DSP48E1_MULT_DPORT ( + output [29:0] ACOUT, + output [17:0] BCOUT, + output reg CARRYCASCOUT, + output reg [3:0] CARRYOUT, + output reg MULTSIGNOUT, + output OVERFLOW, + output reg signed [47:0] P, + output PATTERNBDETECT, + output PATTERNDETECT, + output [47:0] PCOUT, + output UNDERFLOW, + input signed [29:0] A, + input [29:0] ACIN, + input [3:0] ALUMODE, + input signed [17:0] B, + input [17:0] BCIN, + input [47:0] C, + input CARRYCASCIN, + input CARRYIN, + input [2:0] CARRYINSEL, + input CEA1, + input CEA2, + input CEAD, + input CEALUMODE, + input CEB1, + input CEB2, + input CEC, + input CECARRYIN, + input CECTRL, + input CED, + input CEINMODE, + input CEM, + input CEP, + input CLK, + input [24:0] D, + input [4:0] INMODE, + input MULTSIGNIN, + input [6:0] OPMODE, + input [47:0] PCIN, + input RSTA, + input RSTALLCARRYIN, + input RSTALUMODE, + input RSTB, + input RSTC, + input RSTCTRL, + input RSTD, + input RSTINMODE, + input RSTM, + input RSTP +); + parameter integer ACASCREG = 1; + parameter integer ADREG = 1; + parameter integer ALUMODEREG = 1; + parameter integer AREG = 1; + parameter AUTORESET_PATDET = "NO_RESET"; + parameter A_INPUT = "DIRECT"; + parameter integer BCASCREG = 1; + parameter integer BREG = 1; + parameter B_INPUT = "DIRECT"; + parameter integer CARRYINREG = 1; + parameter integer CARRYINSELREG = 1; + parameter integer CREG = 1; + parameter integer DREG = 1; + parameter integer INMODEREG = 1; + parameter integer MREG = 1; + parameter integer OPMODEREG = 1; + parameter integer PREG = 1; + parameter SEL_MASK = "MASK"; + parameter SEL_PATTERN = "PATTERN"; + parameter USE_DPORT = "FALSE"; + parameter USE_MULT = "MULTIPLY"; + parameter USE_PATTERN_DETECT = "NO_PATDET"; + parameter USE_SIMD = "ONE48"; + parameter [47:0] MASK = 48'h3FFFFFFFFFFF; + parameter [47:0] PATTERN = 48'h000000000000; + parameter [3:0] IS_ALUMODE_INVERTED = 4'b0; + parameter [0:0] IS_CARRYIN_INVERTED = 1'b0; + parameter [0:0] IS_CLK_INVERTED = 1'b0; + parameter [4:0] IS_INMODE_INVERTED = 5'b0; + parameter [6:0] IS_OPMODE_INVERTED = 7'b0; +endmodule diff --git a/techlibs/xilinx/abc_unmap.v b/techlibs/xilinx/abc_unmap.v index bcb1069bc..f9b5bd518 100644 --- a/techlibs/xilinx/abc_unmap.v +++ b/techlibs/xilinx/abc_unmap.v @@ -30,14 +30,13 @@ endmodule module \$__ABC_DSP48E1_REG (input [47:0] I, output [47:0] O, output Q); assign O = I; endmodule -module \$__ABC_DSP48E1_MULT_P_MUX (input Aq, Bq, Cq, Dq, ADq, Mq, input [47:0] P, input Pq, output [47:0] O); - assign O = P; -endmodule -module \$__ABC_DSP48E1_MULT_PCOUT_MUX (input Aq, Bq, Cq, Dq, ADq, Mq, input [47:0] P, input Pq, output [47:0] O); +(* techmap_celltype = "$__ABC_DSP48E1_MULT_P_MUX $__ABC_DSP48E1_MULT_PCOUT_MUX $__ABC_DSP48E1_MULT_DPORT_P_MUX $__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX" *) +module \$__ABC_DSP48E1_MUX (input Aq, Bq, Cq, Dq, ADq, Mq, input [47:0] P, input Pq, output [47:0] O); assign O = P; endmodule -module \$__ABC_DSP48E1_MULT ( +(* techmap_celltype = "$__ABC_DSP48E1_MULT $__ABC_DSP48E1_MULT_DPORT" *) +module \$__ABC_DSP48E1 ( output [29:0] ACOUT, output [17:0] BCOUT, output reg CARRYCASCOUT, diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box index e4b1dcd32..7e56e6121 100644 --- a/techlibs/xilinx/abc_xc7.box +++ b/techlibs/xilinx/abc_xc7.box @@ -170,6 +170,106 @@ $__ABC_DSP48E1_MULT_PCOUT_MUX 2101 0 55 48 3098 - 2960 1835 - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435 3098 - 2960 1835 - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435 3098 - 2960 1835 - 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435 +$__ABC_DSP48E1_MULT_DPORT_P_MUX 2102 0 55 48 +# A AD B C D M P Pq +3935 2958 2813 1687 3908 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 +3935 2958 2813 1687 3908 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 - - 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 - +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 - - 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 - +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 1107 - - 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 1255 - +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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- - - - +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- cgit v1.2.3 From d0b202c58d45145e79243caac55f155328008d39 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 13 Sep 2019 12:05:14 -0700 Subject: Add no MULT no DPORT config --- techlibs/xilinx/abc_map.v | 218 +++++++++++--------------- techlibs/xilinx/abc_model.v | 110 ++----------- techlibs/xilinx/abc_unmap.v | 4 +- techlibs/xilinx/abc_xc7.box | 365 +++++++++++++++++++++++++++++++++++++++++++- 4 files changed, 471 insertions(+), 226 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v index 27133fc1e..6e36417e2 100644 --- a/techlibs/xilinx/abc_map.v +++ b/techlibs/xilinx/abc_map.v @@ -207,51 +207,8 @@ module DSP48E1 ( parameter _TECHMAP_CELLTYPE_ = ""; localparam techmap_guard = (_TECHMAP_CELLTYPE_ != ""); - generate - if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin - wire [29:0] iA; - wire [17:0] iB; - wire [47:0] iC; - wire [24:0] iD; - - wire pA, pB, pC, pD, pAD, pM, pP; - wire [47:0] oP, oPCOUT; - - // Disconnect the A-input if MREG is enabled, since - // combinatorial path is broken - if (AREG == 0 && MREG == 0 && PREG == 0) - assign iA = A; - else - \$__ABC_DSP48E1_REG rA (.I(A), .O(iA), .Q(pA)); - if (BREG == 0 && MREG == 0 && PREG == 0) - assign iB = B; - else - \$__ABC_DSP48E1_REG rB (.I(B), .O(iB), .Q(pB)); - if (CREG == 0 && PREG == 0) - assign iC = C; - else - \$__ABC_DSP48E1_REG rC (.I(C), .O(iC), .Q(pC)); - if (DREG == 0) - assign iD = D; - else if (techmap_guard) - $error("Invalid DSP48E1 configuration: DREG enabled but USE_DPORT == \"FALSE\""); - if (ADREG == 1 && techmap_guard) - $error("Invalid DSP48E1 configuration: ADREG enabled but USE_DPORT == \"FALSE\""); - if (PREG == 0) begin - if (MREG == 1) - \$__ABC_DSP48E1_REG rM (.Q(pM)); - end - else - \$__ABC_DSP48E1_REG rP (.Q(pP)); - - \$__ABC_DSP48E1_MULT_P_MUX muxP ( - .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oP), .Pq(pP), .O(P) - ); - \$__ABC_DSP48E1_MULT_PCOUT_MUX muxPCOUT ( - .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oPCOUT), .Pq(pP), .O(PCOUT) - ); - - \$__ABC_DSP48E1_MULT #( +`define DSP48E1_inst(__CELL__) """ +__CELL__ #( .ACASCREG(ACASCREG), .ADREG(ADREG), .ALUMODEREG(ALUMODEREG), @@ -333,6 +290,53 @@ module DSP48E1 ( .RSTM(RSTM), .RSTP(RSTP) ); +""" + + generate + if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin + wire [29:0] iA; + wire [17:0] iB; + wire [47:0] iC; + wire [24:0] iD; + + wire pA, pB, pC, pD, pAD, pM, pP; + wire [47:0] oP, oPCOUT; + + // Disconnect the A-input if MREG is enabled, since + // combinatorial path is broken + if (AREG == 0 && MREG == 0 && PREG == 0) + assign iA = A; + else + \$__ABC_DSP48E1_REG rA (.I(A), .O(iA), .Q(pA)); + if (BREG == 0 && MREG == 0 && PREG == 0) + assign iB = B; + else + \$__ABC_DSP48E1_REG rB (.I(B), .O(iB), .Q(pB)); + if (CREG == 0 && PREG == 0) + assign iC = C; + else + \$__ABC_DSP48E1_REG rC (.I(C), .O(iC), .Q(pC)); + if (DREG == 0) + assign iD = D; + else if (techmap_guard) + $error("Invalid DSP48E1 configuration: DREG enabled but USE_DPORT == \"FALSE\""); + if (ADREG == 1 && techmap_guard) + $error("Invalid DSP48E1 configuration: ADREG enabled but USE_DPORT == \"FALSE\""); + if (PREG == 0) begin + if (MREG == 1) + \$__ABC_DSP48E1_REG rM (.Q(pM)); + end + else + \$__ABC_DSP48E1_REG rP (.Q(pP)); + + \$__ABC_DSP48E1_MULT_P_MUX muxP ( + .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oP), .Pq(pP), .O(P) + ); + \$__ABC_DSP48E1_MULT_PCOUT_MUX muxPCOUT ( + .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oPCOUT), .Pq(pP), .O(PCOUT) + ); + + `DSP48E1_inst(\$__ABC_DSP48E1_MULT ) end else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin wire [29:0] iA; @@ -345,7 +349,7 @@ module DSP48E1 ( // Disconnect the A-input if MREG is enabled, since // combinatorial path is broken - if (AREG == 0 && ADREG == 0 && MREG == 0 && PREG == 1) + if (AREG == 0 && ADREG == 0 && MREG == 0 && PREG == 0) assign iA = A; else \$__ABC_DSP48E1_REG rA (.I(A), .O(iA), .Q(pA)); @@ -377,88 +381,48 @@ module DSP48E1 ( .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oPCOUT), .Pq(pP), .O(PCOUT) ); - \$__ABC_DSP48E1_MULT_DPORT #( - .ACASCREG(ACASCREG), - .ADREG(ADREG), - .ALUMODEREG(ALUMODEREG), - .AREG(AREG), - .AUTORESET_PATDET(AUTORESET_PATDET), - .A_INPUT(A_INPUT), - .BCASCREG(BCASCREG), - .BREG(BREG), - .B_INPUT(B_INPUT), - .CARRYINREG(CARRYINREG), - .CARRYINSELREG(CARRYINSELREG), - .CREG(CREG), - .DREG(DREG), - .INMODEREG(INMODEREG), - .MREG(MREG), - .OPMODEREG(OPMODEREG), - .PREG(PREG), - .SEL_MASK(SEL_MASK), - .SEL_PATTERN(SEL_PATTERN), - .USE_DPORT(USE_DPORT), - .USE_MULT(USE_MULT), - .USE_PATTERN_DETECT(USE_PATTERN_DETECT), - .USE_SIMD(USE_SIMD), - .MASK(MASK), - .PATTERN(PATTERN), - .IS_ALUMODE_INVERTED(IS_ALUMODE_INVERTED), - .IS_CARRYIN_INVERTED(IS_CARRYIN_INVERTED), - .IS_CLK_INVERTED(IS_CLK_INVERTED), - .IS_INMODE_INVERTED(IS_INMODE_INVERTED), - .IS_OPMODE_INVERTED(IS_OPMODE_INVERTED) - ) _TECHMAP_REPLACE_ ( - .ACOUT(ACOUT), - .BCOUT(BCOUT), - .CARRYCASCOUT(CARRYCASCOUT), - .CARRYOUT(CARRYOUT), - .MULTSIGNOUT(MULTSIGNOUT), - .OVERFLOW(OVERFLOW), - .P(oP), - .PATTERNBDETECT(PATTERNBDETECT), - .PATTERNDETECT(PATTERNDETECT), - .PCOUT(oPCOUT), - .UNDERFLOW(UNDERFLOW), - .A(iA), - .ACIN(ACIN), - .ALUMODE(ALUMODE), - .B(iB), - .BCIN(BCIN), - .C(iC), - .CARRYCASCIN(CARRYCASCIN), - .CARRYIN(CARRYIN), - .CARRYINSEL(CARRYINSEL), - .CEA1(CEA1), - .CEA2(CEA2), - .CEAD(CEAD), - .CEALUMODE(CEALUMODE), - .CEB1(CEB1), - .CEB2(CEB2), - .CEC(CEC), - .CECARRYIN(CECARRYIN), - .CECTRL(CECTRL), - .CED(CED), - .CEINMODE(CEINMODE), - .CEM(CEM), - .CEP(CEP), - .CLK(CLK), - .D(iD), - .INMODE(INMODE), - .MULTSIGNIN(MULTSIGNIN), - .OPMODE(OPMODE), - .PCIN(PCIN), - .RSTA(RSTA), - .RSTALLCARRYIN(RSTALLCARRYIN), - .RSTALUMODE(RSTALUMODE), - .RSTB(RSTB), - .RSTC(RSTC), - .RSTCTRL(RSTCTRL), - .RSTD(RSTD), - .RSTINMODE(RSTINMODE), - .RSTM(RSTM), - .RSTP(RSTP) + `DSP48E1_inst(\$__ABC_DSP48E1_MULTD_PORT ) + end + else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin + wire [29:0] iA; + wire [17:0] iB; + wire [47:0] iC; + wire [24:0] iD; + + wire pA, pB, pC, pD, pAD, pM, pP; + wire [47:0] oP, oPCOUT; + + // Disconnect the A-input if MREG is enabled, since + // combinatorial path is broken + if (AREG == 0 && PREG == 0) + assign iA = A; + else + \$__ABC_DSP48E1_REG rA (.I(A), .O(iA), .Q(pA)); + if (BREG == 0 && PREG == 0) + assign iB = B; + else + \$__ABC_DSP48E1_REG rB (.I(B), .O(iB), .Q(pB)); + if (CREG == 0 && PREG == 0) + assign iC = C; + else + \$__ABC_DSP48E1_REG rC (.I(C), .O(iC), .Q(pC)); + if (MREG == 1 && techmap_guard) + $error("Invalid DSP48E1 configuration: MREG enabled but USE_MULT == \"NONE\""); + if (DREG == 1 && techmap_guard) + $error("Invalid DSP48E1 configuration: DREG enabled but USE_DPORT == \"FALSE\""); + if (ADREG == 1 && techmap_guard) + $error("Invalid DSP48E1 configuration: ADREG enabled but USE_DPORT == \"FALSE\""); + if (PREG == 1) + \$__ABC_DSP48E1_REG rP (.Q(pP)); + + \$__ABC_DSP48E1_P_MUX muxP ( + .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oP), .Pq(pP), .O(P) ); + \$__ABC_DSP48E1_PCOUT_MUX muxPCOUT ( + .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oPCOUT), .Pq(pP), .O(PCOUT) + ); + + `DSP48E1_inst(\$__ABC_DSP48E1_MULTD_PORT ) end else $error("Invalid DSP48E1 configuration"); diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc_model.v index 4310ad39e..a8f6deafc 100644 --- a/techlibs/xilinx/abc_model.v +++ b/techlibs/xilinx/abc_model.v @@ -75,20 +75,18 @@ endmodule // B >>------| | // +---------+ // -(* abc_box_id=2100 *) -module \$__ABC_DSP48E1_MULT_P_MUX (input Aq, ADq, Bq, Cq, Dq, Mq, input [47:0] P, input Pq, output [47:0] O); -endmodule -(* abc_box_id=2101 *) -module \$__ABC_DSP48E1_MULT_PCOUT_MUX (input Aq, ADq, Bq, Cq, Dq, Mq, input [47:0] P, input Pq, output [47:0] O); -endmodule -(* abc_box_id=2102 *) -module \$__ABC_DSP48E1_MULT_DPORT_P_MUX (input Aq, ADq, Bq, Cq, Dq, Mq, input [47:0] P, input Pq, output [47:0] O); -endmodule -(* abc_box_id=2103 *) -module \$__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX (input Aq, ADq, Bq, Cq, Dq, Mq, input [47:0] P, input Pq, output [47:0] O); +`define ABC_DSP48E1_MUX(__NAME__) """ +module __NAME__ (input Aq, ADq, Bq, Cq, Dq, Mq, input [47:0] P, input Pq, output [47:0] O); endmodule +""" +(* abc_box_id=2100 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_P_MUX ) +(* abc_box_id=2101 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_PCOUT_MUX ) +(* abc_box_id=2102 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_DPORT_P_MUX ) +(* abc_box_id=2103 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX ) +(* abc_box_id=2104 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_P_MUX ) +(* abc_box_id=2105 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_PCOUT_MUX ) -(* abc_box_id=3000 *) +`define ABC_DSP48E1(__NAME__) """ module \$__ABC_DSP48E1_MULT ( output [29:0] ACOUT, output [17:0] BCOUT, @@ -171,87 +169,7 @@ module \$__ABC_DSP48E1_MULT ( parameter [4:0] IS_INMODE_INVERTED = 5'b0; parameter [6:0] IS_OPMODE_INVERTED = 7'b0; endmodule - -(* abc_box_id=3001 *) -module \$__ABC_DSP48E1_MULT_DPORT ( - output [29:0] ACOUT, - output [17:0] BCOUT, - output reg CARRYCASCOUT, - output reg [3:0] CARRYOUT, - output reg MULTSIGNOUT, - output OVERFLOW, - output reg signed [47:0] P, - output PATTERNBDETECT, - output PATTERNDETECT, - output [47:0] PCOUT, - output UNDERFLOW, - input signed [29:0] A, - input [29:0] ACIN, - input [3:0] ALUMODE, - input signed [17:0] B, - input [17:0] BCIN, - input [47:0] C, - input CARRYCASCIN, - input CARRYIN, - input [2:0] CARRYINSEL, - input CEA1, - input CEA2, - input CEAD, - input CEALUMODE, - input CEB1, - input CEB2, - input CEC, - input CECARRYIN, - input CECTRL, - input CED, - input CEINMODE, - input CEM, - input CEP, - input CLK, - input [24:0] D, - input [4:0] INMODE, - input MULTSIGNIN, - input [6:0] OPMODE, - input [47:0] PCIN, - input RSTA, - input RSTALLCARRYIN, - input RSTALUMODE, - input RSTB, - input RSTC, - input RSTCTRL, - input RSTD, - input RSTINMODE, - input RSTM, - input RSTP -); - parameter integer ACASCREG = 1; - parameter integer ADREG = 1; - parameter integer ALUMODEREG = 1; - parameter integer AREG = 1; - parameter AUTORESET_PATDET = "NO_RESET"; - parameter A_INPUT = "DIRECT"; - parameter integer BCASCREG = 1; - parameter integer BREG = 1; - parameter B_INPUT = "DIRECT"; - parameter integer CARRYINREG = 1; - parameter integer CARRYINSELREG = 1; - parameter integer CREG = 1; - parameter integer DREG = 1; - parameter integer INMODEREG = 1; - parameter integer MREG = 1; - parameter integer OPMODEREG = 1; - parameter integer PREG = 1; - parameter SEL_MASK = "MASK"; - parameter SEL_PATTERN = "PATTERN"; - parameter USE_DPORT = "FALSE"; - parameter USE_MULT = "MULTIPLY"; - parameter USE_PATTERN_DETECT = "NO_PATDET"; - parameter USE_SIMD = "ONE48"; - parameter [47:0] MASK = 48'h3FFFFFFFFFFF; - parameter [47:0] PATTERN = 48'h000000000000; - parameter [3:0] IS_ALUMODE_INVERTED = 4'b0; - parameter [0:0] IS_CARRYIN_INVERTED = 1'b0; - parameter [0:0] IS_CLK_INVERTED = 1'b0; - parameter [4:0] IS_INMODE_INVERTED = 5'b0; - parameter [6:0] IS_OPMODE_INVERTED = 7'b0; -endmodule +""" +(* abc_box_id=3000 *) `ABC_DSP48E1(\$__ABC_DSP48E1_MULT ) +(* abc_box_id=3001 *) `ABC_DSP48E1(\$__ABC_DSP48E1_MULT_DPORT ) +(* abc_box_id=3002 *) `ABC_DSP48E1(\$__ABC_DSP48E1 ) diff --git a/techlibs/xilinx/abc_unmap.v b/techlibs/xilinx/abc_unmap.v index f9b5bd518..2ef507bf2 100644 --- a/techlibs/xilinx/abc_unmap.v +++ b/techlibs/xilinx/abc_unmap.v @@ -30,12 +30,12 @@ endmodule module \$__ABC_DSP48E1_REG (input [47:0] I, output [47:0] O, output Q); assign O = I; endmodule -(* techmap_celltype = "$__ABC_DSP48E1_MULT_P_MUX $__ABC_DSP48E1_MULT_PCOUT_MUX $__ABC_DSP48E1_MULT_DPORT_P_MUX $__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX" *) +(* techmap_celltype = "$__ABC_DSP48E1_MULT_P_MUX $__ABC_DSP48E1_MULT_PCOUT_MUX $__ABC_DSP48E1_MULT_DPORT_P_MUX $__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX $__ABC_DSP48E1_P_MUX $__ABC_DSP48E1_PCOUT_MUX" *) module \$__ABC_DSP48E1_MUX (input Aq, Bq, Cq, Dq, ADq, Mq, input [47:0] P, input Pq, output [47:0] O); assign O = P; endmodule -(* techmap_celltype = "$__ABC_DSP48E1_MULT $__ABC_DSP48E1_MULT_DPORT" *) +(* techmap_celltype = "$__ABC_DSP48E1_MULT $__ABC_DSP48E1_MULT_DPORT $__ABC_DSP48E1" *) module \$__ABC_DSP48E1 ( output [29:0] ACOUT, output [17:0] BCOUT, diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box index 7e56e6121..9a968fedf 100644 --- a/techlibs/xilinx/abc_xc7.box +++ b/techlibs/xilinx/abc_xc7.box @@ -270,6 +270,106 @@ $__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX 2103 0 55 48 4083 2859 2960 1835 4056 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435 4083 2859 2960 1835 4056 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435 4083 2859 2960 1835 4056 1819 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 435 +$__ABC_DSP48E1_P_MUX 2104 0 55 48 +# A AD B C D M P Pq +1632 - 1616 1687 - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- cgit v1.2.3 From 61877e13704405a93a7ec70d0d7158f24fcafb82 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 13 Sep 2019 13:32:55 -0700 Subject: Fix D -> P{,COUT} delay --- techlibs/xilinx/abc_xc7.box | 86 ++++++++++++++++++++++----------------------- 1 file changed, 43 insertions(+), 43 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box index 9a968fedf..79b400d40 100644 --- a/techlibs/xilinx/abc_xc7.box +++ b/techlibs/xilinx/abc_xc7.box @@ -700,24 +700,24 @@ $__ABC_DSP48E1_MULT_DPORT 3001 0 263 154 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- cgit v1.2.3 From 681be20ca219fc64e2bf0f9d2c24937f98903455 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 13 Sep 2019 17:07:18 -0700 Subject: Add `undef DSP48E1_INST --- techlibs/xilinx/abc_map.v | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v index 6e36417e2..31fd79861 100644 --- a/techlibs/xilinx/abc_map.v +++ b/techlibs/xilinx/abc_map.v @@ -207,7 +207,7 @@ module DSP48E1 ( parameter _TECHMAP_CELLTYPE_ = ""; localparam techmap_guard = (_TECHMAP_CELLTYPE_ != ""); -`define DSP48E1_inst(__CELL__) """ +`define DSP48E1_INST(__CELL__) """ __CELL__ #( .ACASCREG(ACASCREG), .ADREG(ADREG), @@ -336,7 +336,7 @@ __CELL__ #( .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oPCOUT), .Pq(pP), .O(PCOUT) ); - `DSP48E1_inst(\$__ABC_DSP48E1_MULT ) + `DSP48E1_INST(\$__ABC_DSP48E1_MULT ) end else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin wire [29:0] iA; @@ -381,7 +381,7 @@ __CELL__ #( .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oPCOUT), .Pq(pP), .O(PCOUT) ); - `DSP48E1_inst(\$__ABC_DSP48E1_MULTD_PORT ) + `DSP48E1_INST(\$__ABC_DSP48E1_MULTD_PORT ) end else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin wire [29:0] iA; @@ -422,9 +422,10 @@ __CELL__ #( .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oPCOUT), .Pq(pP), .O(PCOUT) ); - `DSP48E1_inst(\$__ABC_DSP48E1_MULTD_PORT ) + `DSP48E1_INST(\$__ABC_DSP48E1_MULTD_PORT ) end else $error("Invalid DSP48E1 configuration"); endgenerate + `undef DSP48E1_INST endmodule -- cgit v1.2.3 From e992dbf2c525fc3d4e4b4ddaf9bf9ceaae7804d4 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 18 Sep 2019 10:45:04 -0700 Subject: Add pattern detection support for DSP48E1 model, check against vendor --- techlibs/xilinx/cells_sim.v | 47 ++++++++++++++++++++++++--- techlibs/xilinx/tests/test_dsp_model.sh | 6 ++-- techlibs/xilinx/tests/test_dsp_model.v | 57 ++++++++++++++++++++++++++++++++- 3 files changed, 102 insertions(+), 8 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index ed421f85e..2f586e798 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -498,8 +498,8 @@ module DSP48E1 ( output reg MULTSIGNOUT, output OVERFLOW, output reg signed [47:0] P, - output PATTERNBDETECT, - output PATTERNDETECT, + output reg PATTERNBDETECT, + output reg PATTERNDETECT, output [47:0] PCOUT, output UNDERFLOW, input signed [29:0] A, @@ -575,10 +575,8 @@ module DSP48E1 ( initial begin `ifdef __ICARUS__ if (AUTORESET_PATDET != "NO_RESET") $fatal(1, "Unsupported AUTORESET_PATDET value"); - //if (PREG != 0) $fatal(1, "Unsupported PREG value"); if (SEL_MASK != "MASK") $fatal(1, "Unsupported SEL_MASK value"); if (SEL_PATTERN != "PATTERN") $fatal(1, "Unsupported SEL_PATTERN value"); - if (USE_PATTERN_DETECT != "NO_PATDET") $fatal(1, "Unsupported USE_PATTERN_DETECT value"); if (USE_SIMD != "ONE48" && USE_SIMD != "TWO24" && USE_SIMD != "FOUR12") $fatal(1, "Unsupported USE_SIMD value"); if (IS_ALUMODE_INVERTED != 4'b0) $fatal(1, "Unsupported IS_ALUMODE_INVERTED value"); if (IS_CARRYIN_INVERTED != 1'b0) $fatal(1, "Unsupported IS_CARRYIN_INVERTED value"); @@ -897,4 +895,45 @@ module DSP48E1 ( assign PCOUT = P; + generate + wire PATTERNDETECTd, PATTERNBDETECTd; + + if (USE_PATTERN_DETECT == "PATDET") begin + // TODO: Support SEL_PATTERN != "PATTERN" and SEL_MASK != "MASK + assign PATTERNDETECTd = &(~(Pd ^ PATTERN) | MASK); + assign PATTERNBDETECTd = &((Pd ^ PATTERN) | MASK); + end else begin + assign PATTERNDETECTd = 1'b1; + assign PATTERNBDETECTd = 1'b1; + end + + if (PREG == 1) begin + reg PATTERNDETECTPAST, PATTERNBDETECTPAST; + initial PATTERNDETECT = 1'b0; + initial PATTERNBDETECT = 1'b0; + initial PATTERNDETECTPAST = 1'b0; + initial PATTERNBDETECTPAST = 1'b0; + always @(posedge CLK) + if (RSTP) begin + PATTERNDETECT <= 1'b0; + PATTERNBDETECT <= 1'b0; + PATTERNDETECTPAST <= 1'b0; + PATTERNBDETECTPAST <= 1'b0; + end else if (CEP) begin + PATTERNDETECT <= PATTERNDETECTd; + PATTERNBDETECT <= PATTERNBDETECTd; + PATTERNDETECTPAST <= PATTERNDETECT; + PATTERNBDETECTPAST <= PATTERNBDETECT; + end + assign OVERFLOW = &{PATTERNDETECTPAST, ~PATTERNBDETECT, ~PATTERNDETECT}; + assign UNDERFLOW = &{PATTERNBDETECTPAST, ~PATTERNBDETECT, ~PATTERNDETECT}; + end else begin + always @* begin + PATTERNDETECT = PATTERNDETECTd; + PATTERNBDETECT = PATTERNBDETECTd; + end + assign OVERFLOW = 1'bx, UNDERFLOW = 1'bx; + end + endgenerate + endmodule diff --git a/techlibs/xilinx/tests/test_dsp_model.sh b/techlibs/xilinx/tests/test_dsp_model.sh index 2acd97eb4..ae925c402 100644 --- a/techlibs/xilinx/tests/test_dsp_model.sh +++ b/techlibs/xilinx/tests/test_dsp_model.sh @@ -4,10 +4,10 @@ sed 's/DSP48E1/DSP48E1_UUT/; /DSP48E1_UUT/,/endmodule/ p; d;' < ../cells_sim.v > if [ ! -f "test_dsp_model_ref.v" ]; then cat /opt/Xilinx/Vivado/2019.1/data/verilog/src/unisims/DSP48E1.v > test_dsp_model_ref.v fi -for tb in simd24_preadd_noreg_nocasc simd12_preadd_noreg_nocasc \ +for tb in macc_overflow_underflow \ + simd24_preadd_noreg_nocasc simd12_preadd_noreg_nocasc \ mult_allreg_nopreadd_nocasc mult_noreg_nopreadd_nocasc \ - mult_allreg_preadd_nocasc mult_noreg_preadd_nocasc mult_inreg_preadd_nocasc \ - + mult_allreg_preadd_nocasc mult_noreg_preadd_nocasc mult_inreg_preadd_nocasc do iverilog -s $tb -s glbl -o test_dsp_model test_dsp_model.v test_dsp_model_uut.v test_dsp_model_ref.v /opt/Xilinx/Vivado/2019.1/data/verilog/src/glbl.v vvp -N ./test_dsp_model diff --git a/techlibs/xilinx/tests/test_dsp_model.v b/techlibs/xilinx/tests/test_dsp_model.v index 04d5b26ab..db012f169 100644 --- a/techlibs/xilinx/tests/test_dsp_model.v +++ b/techlibs/xilinx/tests/test_dsp_model.v @@ -81,6 +81,26 @@ module testbench; errcount = errcount + 1; ERROR_FLAG = 1; end + if (REF_PATTERNDETECT !== PATTERNDETECT) begin + $display("ERROR at %1t: REF_PATTERNDETECT=%b UUT_PATTERNDETECT=%b DIFF=%b REF_P=%b P=%b", $time, REF_PATTERNDETECT, PATTERNDETECT, REF_PATTERNDETECT ^ PATTERNDETECT, REF_P, P); + errcount = errcount + 1; + ERROR_FLAG = 1; + end + if (REF_PATTERNBDETECT !== PATTERNBDETECT) begin + $display("ERROR at %1t: REF_PATTERNBDETECT=%b UUT_PATTERNBDETECT=%b DIFF=%b", $time, REF_PATTERNBDETECT, PATTERNBDETECT, REF_PATTERNBDETECT ^ PATTERNBDETECT); + errcount = errcount + 1; + ERROR_FLAG = 1; + end + if (REF_OVERFLOW !== OVERFLOW) begin + $display("ERROR at %1t: REF_OVERFLOW=%b UUT_OVERFLOW=%b DIFF=%b", $time, REF_OVERFLOW, OVERFLOW, REF_OVERFLOW ^ OVERFLOW); + errcount = errcount + 1; + ERROR_FLAG = 1; + end + if (REF_UNDERFLOW !== UNDERFLOW) begin + $display("ERROR at %1t: REF_UNDERFLOW=%b UUT_UNDERFLOW=%b DIFF=%b", $time, REF_UNDERFLOW, UNDERFLOW, REF_UNDERFLOW ^ UNDERFLOW); + errcount = errcount + 1; + ERROR_FLAG = 1; + end #3; end endtask @@ -594,4 +614,39 @@ module simd24_preadd_noreg_nocasc; .IS_INMODE_INVERTED (5'b0), .IS_OPMODE_INVERTED (7'b0) ) testbench (); -endmodule \ No newline at end of file +endmodule + +module macc_overflow_underflow; + testbench #( + .ACASCREG (0), + .ADREG (0), + .ALUMODEREG (0), + .AREG (0), + .AUTORESET_PATDET ("NO_RESET"), + .A_INPUT ("DIRECT"), + .BCASCREG (0), + .BREG (0), + .B_INPUT ("DIRECT"), + .CARRYINREG (0), + .CARRYINSELREG (0), + .CREG (0), + .DREG (0), + .INMODEREG (0), + .MREG (0), + .OPMODEREG (0), + .PREG (1), + .SEL_MASK ("MASK"), + .SEL_PATTERN ("PATTERN"), + .USE_DPORT ("FALSE"), + .USE_MULT ("DYNAMIC"), + .USE_PATTERN_DETECT ("PATDET"), + .USE_SIMD ("ONE48"), + .MASK (48'h1FFFFFFFFFFF), + .PATTERN (48'h000000000000), + .IS_ALUMODE_INVERTED(4'b0), + .IS_CARRYIN_INVERTED(1'b0), + .IS_CLK_INVERTED (1'b0), + .IS_INMODE_INVERTED (5'b0), + .IS_OPMODE_INVERTED (7'b0) + ) testbench (); +endmodule -- cgit v1.2.3 From b77cf6ba48ec5f6bc7895ad52d4c9aa56b945e71 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 18 Sep 2019 11:12:46 -0700 Subject: Mis-spell --- techlibs/xilinx/cells_sim.v | 35 +++++++++++++++++++++++++---------- 1 file changed, 25 insertions(+), 10 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 2f586e798..1a041aac7 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -597,10 +597,10 @@ module DSP48E1 ( else assign B_muxed = B; endgenerate - reg signed [29:0] Ar1 = 30'b0, Ar2 = 30'b0; - reg signed [24:0] Dr = 25'b0; - reg signed [17:0] Br1 = 18'b0, Br2 = 18'b0; - reg signed [47:0] Cr = 48'b0; + reg signed [29:0] Ar1, Ar2; + reg signed [24:0] Dr; + reg signed [17:0] Br1, Br2; + reg signed [47:0] Cr; reg [4:0] INMODEr = 5'b0; reg [6:0] OPMODEr = 7'b0; reg [3:0] ALUMODEr = 4'b0; @@ -609,6 +609,8 @@ module DSP48E1 ( generate // Configurable A register if (AREG == 2) begin + initial Ar1 = 30'b0; + initial Ar2 = 30'b0; always @(posedge CLK) if (RSTA) begin Ar1 <= 30'b0; @@ -618,6 +620,8 @@ module DSP48E1 ( if (CEA2) Ar2 <= Ar1; end end else if (AREG == 1) begin + //initial Ar1 = 30'b0; + initial Ar2 = 30'b0; always @(posedge CLK) if (RSTA) begin Ar1 <= 30'b0; @@ -633,6 +637,8 @@ module DSP48E1 ( // Configurable B register if (BREG == 2) begin + initial Br1 = 25'b0; + initial Br2 = 25'b0; always @(posedge CLK) if (RSTB) begin Br1 <= 18'b0; @@ -642,6 +648,8 @@ module DSP48E1 ( if (CEB2) Br2 <= Br1; end end else if (BREG == 1) begin + //initial Br1 = 25'b0; + initial Br2 = 25'b0; always @(posedge CLK) if (RSTB) begin Br1 <= 18'b0; @@ -656,24 +664,30 @@ module DSP48E1 ( end // C and D registers + if (CREG == 1) initial Cr = 48'b0; if (CREG == 1) begin always @(posedge CLK) if (RSTC) Cr <= 48'b0; else if (CEC) Cr <= C; end else always @* Cr <= C; + if (CREG == 1) initial Dr = 25'b0; if (DREG == 1) begin always @(posedge CLK) if (RSTD) Dr <= 25'b0; else if (CED) Dr <= D; end else always @* Dr <= D; // Control registers + if (INMODEREG == 1) initial INMODEr = 5'b0; if (INMODEREG == 1) begin always @(posedge CLK) if (RSTINMODE) INMODEr <= 5'b0; else if (CEINMODE) INMODEr <= INMODE; end else always @* INMODEr <= INMODE; + if (OPMODEREG == 1) initial OPMODEr = 7'b0; if (OPMODEREG == 1) begin always @(posedge CLK) if (RSTCTRL) OPMODEr <= 7'b0; else if (CECTRL) OPMODEr <= OPMODE; end else always @* OPMODEr <= OPMODE; + if (ALUMODEREG == 1) initial ALUMODEr = 4'b0; if (ALUMODEREG == 1) begin always @(posedge CLK) if (RSTALUMODE) ALUMODEr <= 4'b0; else if (CEALUMODE) ALUMODEr <= ALUMODE; end else always @* ALUMODEr <= ALUMODE; + if (CARRYINSELREG == 1) initial CARRYINSELr = 3'b0; if (CARRYINSELREG == 1) begin always @(posedge CLK) if (RSTCTRL) CARRYINSELr <= 3'b0; else if (CECTRL) CARRYINSELr <= CARRYINSEL; end else always @* CARRYINSELr <= CARRYINSEL; endgenerate - // A and B cascsde + // A and B cascade generate if (ACASCREG == 1 && AREG == 2) assign ACOUT = Ar1; else assign ACOUT = Ar2; @@ -686,9 +700,10 @@ module DSP48E1 ( wire signed [24:0] Ar12_gated = INMODEr[1] ? 25'b0 : Ar12_muxed; wire signed [24:0] Dr_gated = INMODEr[2] ? Dr : 25'b0; wire signed [24:0] AD_result = INMODEr[3] ? (Dr_gated - Ar12_gated) : (Dr_gated + Ar12_gated); - reg signed [24:0] ADr = 25'b0; + reg signed [24:0] ADr; generate + if (ADREG == 1) initial ADr = 25'b0; if (ADREG == 1) begin always @(posedge CLK) if (RSTD) ADr <= 25'b0; else if (CEAD) ADr <= AD_result; end else always @* ADr <= AD_result; endgenerate @@ -860,10 +875,6 @@ module DSP48E1 ( endgenerate wire signed [47:0] Pd = ALUMODEr[1] ? ~alu_sum : alu_sum; - initial P = 48'b0; - initial CARRYOUT = carryout_reset; - initial CARRYCASCOUT = 1'b0; - initial MULTSIGNOUT = 1'b0; wire [3:0] CARRYOUTd = (OPMODEr[3:0] == 4'b0101 || ALUMODEr[3:2] != 2'b00) ? 4'bxxxx : ((ALUMODEr[0] & ALUMODEr[1]) ? ~ext_carry_out : ext_carry_out); wire CARRYCASCOUTd = ext_carry_out[3]; @@ -871,6 +882,10 @@ module DSP48E1 ( generate if (PREG == 1) begin + initial P = 48'b0; + initial CARRYOUT = carryout_reset; + initial CARRYCASCOUT = 1'b0; + initial MULTSIGNOUT = 1'b0; always @(posedge CLK) if (RSTP) begin P <= 48'b0; -- cgit v1.2.3 From 25e0f0c3765060b7ce25a0c58bc926b90dba304d Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 18 Sep 2019 12:19:16 -0700 Subject: Fix copy-paste --- techlibs/xilinx/abc_map.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v index 31fd79861..1f369fc19 100644 --- a/techlibs/xilinx/abc_map.v +++ b/techlibs/xilinx/abc_map.v @@ -381,7 +381,7 @@ __CELL__ #( .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oPCOUT), .Pq(pP), .O(PCOUT) ); - `DSP48E1_INST(\$__ABC_DSP48E1_MULTD_PORT ) + `DSP48E1_INST(\$__ABC_DSP48E1_MULT_DPORT ) end else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin wire [29:0] iA; @@ -422,7 +422,7 @@ __CELL__ #( .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oPCOUT), .Pq(pP), .O(PCOUT) ); - `DSP48E1_INST(\$__ABC_DSP48E1_MULTD_PORT ) + `DSP48E1_INST(\$__ABC_DSP48E1 ) end else $error("Invalid DSP48E1 configuration"); -- cgit v1.2.3 From 3b9b0fcd0630133092b23a18453eb420534b2369 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 19 Sep 2019 14:57:38 -0700 Subject: Tidy up synth_ice40, only restrict DSP_B_MINWIDTH=2 --- techlibs/ice40/synth_ice40.cc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 55aa72aa7..284bc90d0 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -273,7 +273,9 @@ struct SynthIce40Pass : public ScriptPass run("opt_expr"); run("opt_clean"); if (help_mode || dsp) { - run("techmap -map +/mul2dsp.v -map +/ice40/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 -D DSP_NAME=$__MUL16X16", "(if -dsp)"); + run("techmap -map +/mul2dsp.v -map +/ice40/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 " + "-D DSP_A_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 " + "-D DSP_NAME=$__MUL16X16", "(if -dsp)"); run("opt_expr -fine", " (if -dsp)"); run("wreduce", " (if -dsp)"); run("ice40_dsp", " (if -dsp)"); -- cgit v1.2.3 From 95db2489bdb515a2e9d3a995574adc8c1071d3c0 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 19 Sep 2019 14:58:06 -0700 Subject: synth_xilinx to infer DSPs for Y_WIDTH >= 9 and [AB]_WIDTH >= 2 --- techlibs/xilinx/synth_xilinx.cc | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 2ac254a1f..b55c40764 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -342,7 +342,10 @@ struct SynthXilinxPass : public ScriptPass if (check_label("map_dsp"), "(skip if '-nodsp')") { if (!nodsp || help_mode) { // NB: Xilinx multipliers are signed only - run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_A_MAXWIDTH_PARTIAL=18 -D DSP_B_MAXWIDTH=18 -D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18"); + run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_A_MAXWIDTH_PARTIAL=18 -D DSP_B_MAXWIDTH=18 " + "-D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers + "-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller + "-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18"); run("xilinx_dsp"); run("chtype -set $mul t:$__soft_mul"); } -- cgit v1.2.3 From c15a35db8487a31592046bfe8422740e196407d1 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 19 Sep 2019 15:55:49 -0700 Subject: D is 25 bits not 24 bits wide --- techlibs/xilinx/dsp_map.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/dsp_map.v b/techlibs/xilinx/dsp_map.v index 8901b215b..a4256eb92 100644 --- a/techlibs/xilinx/dsp_map.v +++ b/techlibs/xilinx/dsp_map.v @@ -32,7 +32,7 @@ module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y); .A({{5{A[24]}}, A}), .B(B), .C(48'b0), - .D(24'b0), + .D(25'b0), .P(P_48), .INMODE(5'b00000), -- cgit v1.2.3 From 595fb611a5179f280452b5af356f652648eb3e2d Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 19 Sep 2019 15:58:01 -0700 Subject: Use (* techmap_autopurge *) to suppress techmap warnings --- techlibs/xilinx/abc_map.v | 110 ++++++++++++++++++++++---------------------- techlibs/xilinx/abc_unmap.v | 83 +++++++++++++++++---------------- 2 files changed, 99 insertions(+), 94 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v index 1f369fc19..f23ec6463 100644 --- a/techlibs/xilinx/abc_map.v +++ b/techlibs/xilinx/abc_map.v @@ -22,11 +22,11 @@ module RAM32X1D ( output DPO, SPO, - input D, - input WCLK, - input WE, - input A0, A1, A2, A3, A4, - input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4 + (* techmap_autopurge *) input D, + (* techmap_autopurge *) input WCLK, + (* techmap_autopurge *) input WE, + (* techmap_autopurge *) input A0, A1, A2, A3, A4, + (* techmap_autopurge *) input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4 ); parameter INIT = 32'h0; parameter IS_WCLK_INVERTED = 1'b0; @@ -45,11 +45,11 @@ endmodule module RAM64X1D ( output DPO, SPO, - input D, - input WCLK, - input WE, - input A0, A1, A2, A3, A4, A5, - input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5 + (* techmap_autopurge *) input D, + (* techmap_autopurge *) input WCLK, + (* techmap_autopurge *) input WE, + (* techmap_autopurge *) input A0, A1, A2, A3, A4, A5, + (* techmap_autopurge *) input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5 ); parameter INIT = 64'h0; parameter IS_WCLK_INVERTED = 1'b0; @@ -68,10 +68,10 @@ endmodule module RAM128X1D ( output DPO, SPO, - input D, - input WCLK, - input WE, - input [6:0] A, DPRA + (* techmap_autopurge *) input D, + (* techmap_autopurge *) input WCLK, + (* techmap_autopurge *) input WE, + (* techmap_autopurge *) input [6:0] A, DPRA ); parameter INIT = 128'h0; parameter IS_WCLK_INVERTED = 1'b0; @@ -90,7 +90,7 @@ endmodule module SRL16E ( output Q, - input A0, A1, A2, A3, CE, CLK, D + (* techmap_autopurge *) input A0, A1, A2, A3, CE, CLK, D ); parameter [15:0] INIT = 16'h0000; parameter [0:0] IS_CLK_INVERTED = 1'b0; @@ -107,8 +107,8 @@ endmodule module SRLC32E ( output Q, output Q31, - input [4:0] A, - input CE, CLK, D + (* techmap_autopurge *) input [4:0] A, + (* techmap_autopurge *) input CE, CLK, D ); parameter [31:0] INIT = 32'h00000000; parameter [0:0] IS_CLK_INVERTED = 1'b0; @@ -134,44 +134,44 @@ module DSP48E1 ( output PATTERNDETECT, output [47:0] PCOUT, output UNDERFLOW, - input signed [29:0] A, - input [29:0] ACIN, - input [3:0] ALUMODE, - input signed [17:0] B, - input [17:0] BCIN, - input [47:0] C, - input CARRYCASCIN, - input CARRYIN, - input [2:0] CARRYINSEL, - input CEA1, - input CEA2, - input CEAD, - input CEALUMODE, - input CEB1, - input CEB2, - input CEC, - input CECARRYIN, - input CECTRL, - input CED, - input CEINMODE, - input CEM, - input CEP, - input CLK, - input [24:0] D, - input [4:0] INMODE, - input MULTSIGNIN, - input [6:0] OPMODE, - input [47:0] PCIN, - input RSTA, - input RSTALLCARRYIN, - input RSTALUMODE, - input RSTB, - input RSTC, - input RSTCTRL, - input RSTD, - input RSTINMODE, - input RSTM, - input RSTP + (* techmap_autopurge *) input signed [29:0] A, + (* techmap_autopurge *) input [29:0] ACIN, + (* techmap_autopurge *) input [3:0] ALUMODE, + (* techmap_autopurge *) input signed [17:0] B, + (* techmap_autopurge *) input [17:0] BCIN, + (* techmap_autopurge *) input [47:0] C, + (* techmap_autopurge *) input CARRYCASCIN, + (* techmap_autopurge *) input CARRYIN, + (* techmap_autopurge *) input [2:0] CARRYINSEL, + (* techmap_autopurge *) input CEA1, + (* techmap_autopurge *) input CEA2, + (* techmap_autopurge *) input CEAD, + (* techmap_autopurge *) input CEALUMODE, + (* techmap_autopurge *) input CEB1, + (* techmap_autopurge *) input CEB2, + (* techmap_autopurge *) input CEC, + (* techmap_autopurge *) input CECARRYIN, + (* techmap_autopurge *) input CECTRL, + (* techmap_autopurge *) input CED, + (* techmap_autopurge *) input CEINMODE, + (* techmap_autopurge *) input CEM, + (* techmap_autopurge *) input CEP, + (* techmap_autopurge *) input CLK, + (* techmap_autopurge *) input [24:0] D, + (* techmap_autopurge *) input [4:0] INMODE, + (* techmap_autopurge *) input MULTSIGNIN, + (* techmap_autopurge *) input [6:0] OPMODE, + (* techmap_autopurge *) input [47:0] PCIN, + (* techmap_autopurge *) input RSTA, + (* techmap_autopurge *) input RSTALLCARRYIN, + (* techmap_autopurge *) input RSTALUMODE, + (* techmap_autopurge *) input RSTB, + (* techmap_autopurge *) input RSTC, + (* techmap_autopurge *) input RSTCTRL, + (* techmap_autopurge *) input RSTD, + (* techmap_autopurge *) input RSTINMODE, + (* techmap_autopurge *) input RSTM, + (* techmap_autopurge *) input RSTP ); parameter integer ACASCREG = 1; parameter integer ADREG = 1; diff --git a/techlibs/xilinx/abc_unmap.v b/techlibs/xilinx/abc_unmap.v index 2ef507bf2..010041b73 100644 --- a/techlibs/xilinx/abc_unmap.v +++ b/techlibs/xilinx/abc_unmap.v @@ -31,7 +31,12 @@ module \$__ABC_DSP48E1_REG (input [47:0] I, output [47:0] O, output Q); assign O = I; endmodule (* techmap_celltype = "$__ABC_DSP48E1_MULT_P_MUX $__ABC_DSP48E1_MULT_PCOUT_MUX $__ABC_DSP48E1_MULT_DPORT_P_MUX $__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX $__ABC_DSP48E1_P_MUX $__ABC_DSP48E1_PCOUT_MUX" *) -module \$__ABC_DSP48E1_MUX (input Aq, Bq, Cq, Dq, ADq, Mq, input [47:0] P, input Pq, output [47:0] O); +module \$__ABC_DSP48E1_MUX ( + input Aq, Bq, Cq, Dq, ADq, Mq, + input [47:0] P, + input Pq, + output [47:0] O +); assign O = P; endmodule @@ -48,44 +53,44 @@ module \$__ABC_DSP48E1 ( output PATTERNDETECT, output [47:0] PCOUT, output UNDERFLOW, - input signed [29:0] A, - input [29:0] ACIN, - input [3:0] ALUMODE, - input signed [17:0] B, - input [17:0] BCIN, - input [47:0] C, - input CARRYCASCIN, - input CARRYIN, - input [2:0] CARRYINSEL, - input CEA1, - input CEA2, - input CEAD, - input CEALUMODE, - input CEB1, - input CEB2, - input CEC, - input CECARRYIN, - input CECTRL, - input CED, - input CEINMODE, - input CEM, - input CEP, - input CLK, - input [24:0] D, - input [4:0] INMODE, - input MULTSIGNIN, - input [6:0] OPMODE, - input [47:0] PCIN, - input RSTA, - input RSTALLCARRYIN, - input RSTALUMODE, - input RSTB, - input RSTC, - input RSTCTRL, - input RSTD, - input RSTINMODE, - input RSTM, - input RSTP + (* techmap_autopurge *) input signed [29:0] A, + (* techmap_autopurge *) input [29:0] ACIN, + (* techmap_autopurge *) input [3:0] ALUMODE, + (* techmap_autopurge *) input signed [17:0] B, + (* techmap_autopurge *) input [17:0] BCIN, + (* techmap_autopurge *) input [47:0] C, + (* techmap_autopurge *) input CARRYCASCIN, + (* techmap_autopurge *) input CARRYIN, + (* techmap_autopurge *) input [2:0] CARRYINSEL, + (* techmap_autopurge *) input CEA1, + (* techmap_autopurge *) input CEA2, + (* techmap_autopurge *) input CEAD, + (* techmap_autopurge *) input CEALUMODE, + (* techmap_autopurge *) input CEB1, + (* techmap_autopurge *) input CEB2, + (* techmap_autopurge *) input CEC, + (* techmap_autopurge *) input CECARRYIN, + (* techmap_autopurge *) input CECTRL, + (* techmap_autopurge *) input CED, + (* techmap_autopurge *) input CEINMODE, + (* techmap_autopurge *) input CEM, + (* techmap_autopurge *) input CEP, + (* techmap_autopurge *) input CLK, + (* techmap_autopurge *) input [24:0] D, + (* techmap_autopurge *) input [4:0] INMODE, + (* techmap_autopurge *) input MULTSIGNIN, + (* techmap_autopurge *) input [6:0] OPMODE, + (* techmap_autopurge *) input [47:0] PCIN, + (* techmap_autopurge *) input RSTA, + (* techmap_autopurge *) input RSTALLCARRYIN, + (* techmap_autopurge *) input RSTALUMODE, + (* techmap_autopurge *) input RSTB, + (* techmap_autopurge *) input RSTC, + (* techmap_autopurge *) input RSTCTRL, + (* techmap_autopurge *) input RSTD, + (* techmap_autopurge *) input RSTINMODE, + (* techmap_autopurge *) input RSTM, + (* techmap_autopurge *) input RSTP ); parameter integer ACASCREG = 1; parameter integer ADREG = 1; -- cgit v1.2.3 From 5ca25b0c59d47e26c7bf119c47b4e73054fafbc8 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 19 Sep 2019 16:27:14 -0700 Subject: Suppress $anyseq warnings --- techlibs/xilinx/abc_map.v | 47 ++++++++++++++++++++++++++++++++--------------- 1 file changed, 32 insertions(+), 15 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v index f23ec6463..1b7900af8 100644 --- a/techlibs/xilinx/abc_map.v +++ b/techlibs/xilinx/abc_map.v @@ -305,29 +305,36 @@ __CELL__ #( // Disconnect the A-input if MREG is enabled, since // combinatorial path is broken if (AREG == 0 && MREG == 0 && PREG == 0) - assign iA = A; + assign iA = A, pA = 1'bx; else \$__ABC_DSP48E1_REG rA (.I(A), .O(iA), .Q(pA)); if (BREG == 0 && MREG == 0 && PREG == 0) - assign iB = B; + assign iB = B, pB = 1'bx; else \$__ABC_DSP48E1_REG rB (.I(B), .O(iB), .Q(pB)); if (CREG == 0 && PREG == 0) - assign iC = C; + assign iC = C, pC = 1'bx; else \$__ABC_DSP48E1_REG rC (.I(C), .O(iC), .Q(pC)); if (DREG == 0) assign iD = D; else if (techmap_guard) $error("Invalid DSP48E1 configuration: DREG enabled but USE_DPORT == \"FALSE\""); + assign pD = 1'bx; if (ADREG == 1 && techmap_guard) - $error("Invalid DSP48E1 configuration: ADREG enabled but USE_DPORT == \"FALSE\""); + $error("Invalid DSP48E1 configuration: ADREG enabled but USE_DPORT == \"FALSE\""); + assign pAD = 1'bx; if (PREG == 0) begin + assign pP = 1'bx; if (MREG == 1) \$__ABC_DSP48E1_REG rM (.Q(pM)); + else + assign pM = 1'bx; end - else + else begin \$__ABC_DSP48E1_REG rP (.Q(pP)); + assign pM = 1'bx; + end \$__ABC_DSP48E1_MULT_P_MUX muxP ( .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oP), .Pq(pP), .O(P) @@ -350,26 +357,31 @@ __CELL__ #( // Disconnect the A-input if MREG is enabled, since // combinatorial path is broken if (AREG == 0 && ADREG == 0 && MREG == 0 && PREG == 0) - assign iA = A; + assign iA = A, pA = 1'bx; else \$__ABC_DSP48E1_REG rA (.I(A), .O(iA), .Q(pA)); if (BREG == 0 && MREG == 0 && PREG == 0) - assign iB = B; + assign iB = B, pB = 1'bx; else \$__ABC_DSP48E1_REG rB (.I(B), .O(iB), .Q(pB)); if (CREG == 0 && PREG == 0) - assign iC = C; + assign iC = C, pC = 1'bx; else \$__ABC_DSP48E1_REG rC (.I(C), .O(iC), .Q(pC)); if (DREG == 0 && ADREG == 0) - assign iD = D; + assign iD = D, pD = 1'bx; else \$__ABC_DSP48E1_REG rD (.I(D), .O(iD), .Q(pD)); if (PREG == 0) begin if (MREG == 1) \$__ABC_DSP48E1_REG rM (.Q(pM)); - else if (ADREG == 1) - \$__ABC_DSP48E1_REG rAD (.Q(pAD)); + else begin + assign pM = 1'bx; + if (ADREG == 1) + \$__ABC_DSP48E1_REG rAD (.Q(pAD)); + else + assign pAD = 1'bx; + end end else \$__ABC_DSP48E1_REG rP (.Q(pP)); @@ -395,25 +407,30 @@ __CELL__ #( // Disconnect the A-input if MREG is enabled, since // combinatorial path is broken if (AREG == 0 && PREG == 0) - assign iA = A; + assign iA = A, pA = 1'bx; else \$__ABC_DSP48E1_REG rA (.I(A), .O(iA), .Q(pA)); if (BREG == 0 && PREG == 0) - assign iB = B; + assign iB = B, pB = 1'bx; else \$__ABC_DSP48E1_REG rB (.I(B), .O(iB), .Q(pB)); if (CREG == 0 && PREG == 0) - assign iC = C; + assign iC = C, pC = 1'bx; else \$__ABC_DSP48E1_REG rC (.I(C), .O(iC), .Q(pC)); if (MREG == 1 && techmap_guard) - $error("Invalid DSP48E1 configuration: MREG enabled but USE_MULT == \"NONE\""); + $error("Invalid DSP48E1 configuration: MREG enabled but USE_MULT == \"NONE\""); + assign pM = 1'bx; if (DREG == 1 && techmap_guard) $error("Invalid DSP48E1 configuration: DREG enabled but USE_DPORT == \"FALSE\""); + assign pD = 1'bx; if (ADREG == 1 && techmap_guard) $error("Invalid DSP48E1 configuration: ADREG enabled but USE_DPORT == \"FALSE\""); + assign pAD = 1'bx; if (PREG == 1) \$__ABC_DSP48E1_REG rP (.Q(pP)); + else + assign pP = 1'bx; \$__ABC_DSP48E1_P_MUX muxP ( .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oP), .Pq(pP), .O(P) -- cgit v1.2.3 From 41256f48a5f3231e231cbdf9380a26128f272044 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 19 Sep 2019 18:33:29 -0700 Subject: Different approach to timing --- techlibs/xilinx/abc_map.v | 141 ++++++++++-------- techlibs/xilinx/abc_model.v | 105 +++++++------ techlibs/xilinx/abc_unmap.v | 4 +- techlibs/xilinx/abc_xc7.box | 350 +++++++------------------------------------- 4 files changed, 195 insertions(+), 405 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v index 1b7900af8..124ce6d8f 100644 --- a/techlibs/xilinx/abc_map.v +++ b/techlibs/xilinx/abc_map.v @@ -299,49 +299,60 @@ __CELL__ #( wire [47:0] iC; wire [24:0] iD; - wire pA, pB, pC, pD, pAD, pM, pP; + wire pAP, pBP, pCP, pDP, pADP, pMP, pPP; + wire pAPCOUT, pBPCOUT, pCPCOUT, pDPCOUT, pADPCOUT, pMPCOUT, pPPCOUT; wire [47:0] oP, oPCOUT; - // Disconnect the A-input if MREG is enabled, since - // combinatorial path is broken + // Disconnect the A-input if MREG is enabled, since + // combinatorial path is broken if (AREG == 0 && MREG == 0 && PREG == 0) - assign iA = A, pA = 1'bx; + assign iA = A, pAP = 1'bx, pAPCOUT = 1'bx; else - \$__ABC_DSP48E1_REG rA (.I(A), .O(iA), .Q(pA)); + \$__ABC_DSP48E1_MULT_AREG rA (.I(A), .O(iA), .P(pAP), .PCOUT(pAPCOUT)); if (BREG == 0 && MREG == 0 && PREG == 0) - assign iB = B, pB = 1'bx; + assign iB = B, pBP = 1'bx, pBPCOUT = 1'bx; else - \$__ABC_DSP48E1_REG rB (.I(B), .O(iB), .Q(pB)); + \$__ABC_DSP48E1_MULT_BREG rB (.I(B), .O(iB), .P(pBP), .PCOUT(pBPCOUT)); if (CREG == 0 && PREG == 0) - assign iC = C, pC = 1'bx; + assign iC = C, pCP = 1'bx, pCPCOUT = 1'bx; else - \$__ABC_DSP48E1_REG rC (.I(C), .O(iC), .Q(pC)); + \$__ABC_DSP48E1_MULT_CREG rC (.I(C), .O(iC), .P(pCP), .PCOUT(pCPCOUT)); if (DREG == 0) assign iD = D; else if (techmap_guard) - $error("Invalid DSP48E1 configuration: DREG enabled but USE_DPORT == \"FALSE\""); - assign pD = 1'bx; + $error("Invalid DSP48E1 configuration: DREG enabled but USE_DPORT == \"FALSE\""); + assign pDP = 1'bx, pDPCOUT = 1'bx; if (ADREG == 1 && techmap_guard) $error("Invalid DSP48E1 configuration: ADREG enabled but USE_DPORT == \"FALSE\""); - assign pAD = 1'bx; + assign pADP = 1'bx, pADPCOUT = 1'bx; if (PREG == 0) begin - assign pP = 1'bx; if (MREG == 1) - \$__ABC_DSP48E1_REG rM (.Q(pM)); + \$__ABC_DSP48E1_MULT_MREG rM (.P(pMP), .PCOUT(pMPCOUT)); else - assign pM = 1'bx; + assign pMP = 1'bx, pMPCOUT = 1'bx; + assign pPP = 1'bx, pPPCOUT = 1'bx; end else begin - \$__ABC_DSP48E1_REG rP (.Q(pP)); - assign pM = 1'bx; + assign pMP = 1'bx, pMPCOUT = 1'bx; + \$__ABC_DSP48E1_MULT_PREG rP (.P(pPP), .PCOUT(pPPCOUT)); end - \$__ABC_DSP48E1_MULT_P_MUX muxP ( - .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oP), .Pq(pP), .O(P) - ); - \$__ABC_DSP48E1_MULT_PCOUT_MUX muxPCOUT ( - .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oPCOUT), .Pq(pP), .O(PCOUT) - ); + if (MREG == 0 && PREG == 0) begin + \$__ABC_DSP48E1_MUX muxP ( + .Aq(pAP), .Bq(pBP), .Cq(pCP), .Dq(pDP), .ADq(pADP), .Mq(pMP), .P(oP), .Pq(pPP), .O(P) + ); + \$__ABC_DSP48E1_MUX muxPCOUT ( + .Aq(pAPCOUT), .Bq(pBPCOUT), .Cq(pCPCOUT), .Dq(pDPCOUT), .ADq(pADPCOUT), .Mq(pMPCOUT), .P(oPCOUT), .Pq(pPPCOUT), .O(PCOUT) + ); + end + else begin + \$__ABC_DSP48E1_MUX muxP ( + .Aq(pAP), .Bq(pBP), .Cq(pCP), .Dq(pDP), .ADq(pADP), .Mq(pMP), .P(1'bx), .Pq(pPP), .O(P) + ); + \$__ABC_DSP48E1_MUX muxPCOUT ( + .Aq(pAPCOUT), .Bq(pBPCOUT), .Cq(pCPCOUT), .Dq(pDPCOUT), .ADq(pADPCOUT), .Mq(pMPCOUT), .P(1'bx), .Pq(pPPCOUT), .O(PCOUT) + ); + end `DSP48E1_INST(\$__ABC_DSP48E1_MULT ) end @@ -351,46 +362,53 @@ __CELL__ #( wire [47:0] iC; wire [24:0] iD; - wire pA, pB, pC, pD, pAD, pM, pP; + wire pAP, pBP, pCP, pDP, pADP, pMP, pPP; + wire pAPCOUT, pBPCOUT, pCPCOUT, pDPCOUT, pADPCOUT, pMPCOUT, pPPCOUT; wire [47:0] oP, oPCOUT; // Disconnect the A-input if MREG is enabled, since // combinatorial path is broken if (AREG == 0 && ADREG == 0 && MREG == 0 && PREG == 0) - assign iA = A, pA = 1'bx; + assign iA = A, pAP = 1'bx, pAPCOUT = 1'bx; else - \$__ABC_DSP48E1_REG rA (.I(A), .O(iA), .Q(pA)); + \$__ABC_DSP48E1_MULT_DPORT_AREG rA (.I(A), .O(iA), .P(pAP), .PCOUT(pAPCOUT)); if (BREG == 0 && MREG == 0 && PREG == 0) - assign iB = B, pB = 1'bx; + assign iB = B, pBP = 1'bx, pBPCOUT = 1'bx; else - \$__ABC_DSP48E1_REG rB (.I(B), .O(iB), .Q(pB)); + \$__ABC_DSP48E1_MULT_DPORT_BREG rB (.I(B), .O(iB), .P(pBP), .PCOUT(pBPCOUT)); if (CREG == 0 && PREG == 0) - assign iC = C, pC = 1'bx; + assign iC = C, pCP = 1'bx, pCPCOUT = 1'bx; else - \$__ABC_DSP48E1_REG rC (.I(C), .O(iC), .Q(pC)); + \$__ABC_DSP48E1_MULT_DPORT_CREG rC (.I(C), .O(iC), .P(pCP), .PCOUT(pCPCOUT)); if (DREG == 0 && ADREG == 0) - assign iD = D, pD = 1'bx; + assign iD = D, pDP = 1'bx, pDPCOUT = 1'bx; else - \$__ABC_DSP48E1_REG rD (.I(D), .O(iD), .Q(pD)); + \$__ABC_DSP48E1_MULT_DPORT_DREG rD (.I(D), .O(iD), .P(pDP), .PCOUT(pDPCOUT)); if (PREG == 0) begin - if (MREG == 1) - \$__ABC_DSP48E1_REG rM (.Q(pM)); + if (MREG == 1) begin + assign pADP = 1'bx, pADPCOUT = 1'bx; + \$__ABC_DSP48E1_MULT_DPORT_MREG rM (.P(pMP), .PCOUT(pMPCOUT)); + end else begin - assign pM = 1'bx; if (ADREG == 1) - \$__ABC_DSP48E1_REG rAD (.Q(pAD)); + \$__ABC_DSP48E1_MULT_DPORT_ADPREG rAD (.P(pADP), .PCOUT(pADPCOUT)); else - assign pAD = 1'bx; + assign pADP = 1'bx, pADPCOUT = 1'bx; + assign pMP = 1'bx, pMPCOUT = 1'bx; end + assign pPP = 1'bx, pPPCOUT = 1'bx; end - else - \$__ABC_DSP48E1_REG rP (.Q(pP)); + else begin + assign pADP = 1'bx, pADPCOUT = 1'bx; + assign pMP = 1'bx, pMPCOUT = 1'bx; + \$__ABC_DSP48E1_MULT_DPORT_PREG rP (.P(pPP), .PCOUT(pPPCOUT)); + end - \$__ABC_DSP48E1_MULT_DPORT_P_MUX muxP ( - .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oP), .Pq(pP), .O(P) + \$__ABC_DSP48E1_MUX muxP ( + .Aq(pAP), .Bq(pBP), .Cq(pCP), .Dq(pDP), .ADq(pADP), .Mq(pMP), .P(oP), .Pq(pPP), .O(P) ); - \$__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX muxPCOUT ( - .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oPCOUT), .Pq(pP), .O(PCOUT) + \$__ABC_DSP48E1_MUX muxPCOUT ( + .Aq(pAPCOUT), .Bq(pBPCOUT), .Cq(pCPCOUT), .Dq(pDPCOUT), .ADq(pADPCOUT), .Mq(pMPCOUT), .P(oPCOUT), .Pq(pPPCOUT), .O(PCOUT) ); `DSP48E1_INST(\$__ABC_DSP48E1_MULT_DPORT ) @@ -401,42 +419,43 @@ __CELL__ #( wire [47:0] iC; wire [24:0] iD; - wire pA, pB, pC, pD, pAD, pM, pP; + wire pAP, pBP, pCP, pDP, pADP, pMP, pPP; + wire pAPCOUT, pBPCOUT, pCPCOUT, pDPCOUT, pADPCOUT, pMPCOUT, pPPCOUT; wire [47:0] oP, oPCOUT; // Disconnect the A-input if MREG is enabled, since // combinatorial path is broken if (AREG == 0 && PREG == 0) - assign iA = A, pA = 1'bx; + assign iA = A, pAP = 1'bx, pAPCOUT = 1'bx; else - \$__ABC_DSP48E1_REG rA (.I(A), .O(iA), .Q(pA)); + \$__ABC_DSP48E1_AREG rA (.I(A), .O(iA), .P(pAP), .PCOUT(pAPCOUT)); if (BREG == 0 && PREG == 0) - assign iB = B, pB = 1'bx; + assign iB = B, pBP = 1'bx, pBPCOUT = 1'bx; else - \$__ABC_DSP48E1_REG rB (.I(B), .O(iB), .Q(pB)); + \$__ABC_DSP48E1_BREG rB (.I(B), .O(iB), .P(pB), .PCOUT(pBPCOUT)); if (CREG == 0 && PREG == 0) - assign iC = C, pC = 1'bx; + assign iC = C, pCP = 1'bx, pCPCOUT = 1'bx; else - \$__ABC_DSP48E1_REG rC (.I(C), .O(iC), .Q(pC)); - if (MREG == 1 && techmap_guard) - $error("Invalid DSP48E1 configuration: MREG enabled but USE_MULT == \"NONE\""); - assign pM = 1'bx; + \$__ABC_DSP48E1_CREG rC (.I(C), .O(iC), .P(pC), .PCOUT(pCPCOUT)); if (DREG == 1 && techmap_guard) $error("Invalid DSP48E1 configuration: DREG enabled but USE_DPORT == \"FALSE\""); - assign pD = 1'bx; + assign iD = 25'bx, pDP = 1'bx, pDPCOUT = 1'bx; if (ADREG == 1 && techmap_guard) $error("Invalid DSP48E1 configuration: ADREG enabled but USE_DPORT == \"FALSE\""); - assign pAD = 1'bx; + assign pADP = 1'bx, pADPCOUT = 1'bx; + if (MREG == 1 && techmap_guard) + $error("Invalid DSP48E1 configuration: MREG enabled but USE_MULT == \"NONE\""); + assign pMP = 1'bx, pMPCOUT = 1'bx; if (PREG == 1) - \$__ABC_DSP48E1_REG rP (.Q(pP)); + \$__ABC_DSP48E1_PREG rP (.P(pPP), .P(pPCOUT)); else - assign pP = 1'bx; + assign pPP = 1'bx, pPPCOUT = 1'bx; - \$__ABC_DSP48E1_P_MUX muxP ( - .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oP), .Pq(pP), .O(P) + \$__ABC_DSP48E1_MUX muxP ( + .Aq(pAP), .Bq(pBP), .Cq(pCP), .Dq(pDP), .ADq(pADP), .Mq(pMP), .P(oP), .Pq(pPP), .O(P) ); - \$__ABC_DSP48E1_PCOUT_MUX muxPCOUT ( - .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oPCOUT), .Pq(pP), .O(PCOUT) + \$__ABC_DSP48E1_MUX muxPCOUT ( + .Aq(pAPCOUT), .Bq(pBPCOUT), .Cq(pCPCOUT), .Dq(pDPCOUT), .ADq(pADPCOUT), .Mq(pMPCOUT), .P(oPCOUT), .Pq(pPPCOUT), .O(PCOUT) ); `DSP48E1_INST(\$__ABC_DSP48E1 ) diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc_model.v index a8f6deafc..79cca6b7b 100644 --- a/techlibs/xilinx/abc_model.v +++ b/techlibs/xilinx/abc_model.v @@ -44,48 +44,6 @@ endmodule module \$__ABC_LUT7 (input A, input [6:0] S, output Y); endmodule -// Boxes used to represent the comb/seq behaviour of DSP48E1 -// With abc_map.v responsible for disconnecting inputs to -// the combinatorial DSP48E1 model by a register (e.g. -// disconnecting A when AREG, MREG or PREG is enabled) -// this blackbox captures the existence of a replacement -// path between AREG/BREG/CREG/etc. and P/PCOUT. -// Since the Aq/ADq/Bq/etc. inputs are assumed to arrive at -// the box at zero time, the combinatorial delay through -// these boxes thus represents the clock-to-q delay -// (arrival time) at P/PCOUT. -// Doing so should means that ABC is able to analyse the -// worst-case delay through to P, regardless of if it was -// through any combinatorial paths (e.g. B, below) or an -// internal register (A2REG). -// However, the true value of being as complete as this is -// questionable since if AREG=1 and BREG=0 (as below) -// then the worse-case path would very likely be through B -// and very unlikely to be through AREG.Q...? -// -// In graphical form: -// -// NEW "PI" >>---+ -// for AREG.Q | -// | -// +---------+ | __ -// A >>--X X-| | +--| \ -// | DSP48E1 |P | |--->> P -// | AREG=1 |-------|__/ -// B >>------| | -// +---------+ -// -`define ABC_DSP48E1_MUX(__NAME__) """ -module __NAME__ (input Aq, ADq, Bq, Cq, Dq, Mq, input [47:0] P, input Pq, output [47:0] O); -endmodule -""" -(* abc_box_id=2100 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_P_MUX ) -(* abc_box_id=2101 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_PCOUT_MUX ) -(* abc_box_id=2102 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_DPORT_P_MUX ) -(* abc_box_id=2103 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX ) -(* abc_box_id=2104 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_P_MUX ) -(* abc_box_id=2105 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_PCOUT_MUX ) - `define ABC_DSP48E1(__NAME__) """ module \$__ABC_DSP48E1_MULT ( output [29:0] ACOUT, @@ -173,3 +131,66 @@ endmodule (* abc_box_id=3000 *) `ABC_DSP48E1(\$__ABC_DSP48E1_MULT ) (* abc_box_id=3001 *) `ABC_DSP48E1(\$__ABC_DSP48E1_MULT_DPORT ) (* abc_box_id=3002 *) `ABC_DSP48E1(\$__ABC_DSP48E1 ) + + +// Modules used to model the comb/seq behaviour of DSP48E1 +// With abc_map.v responsible for splicing the below modules +// into between the combinatorial DSP48E1 box (e.g. disconnecting +// A when AREG, MREG or PREG is enabled and splicing in the +// "$__ABC_DSP48E1_MULT_AREG" blackbox as "REG" in the diagram +// below) this acts to first disables the combinatorial path +// (as there is no connectivity through REG), and secondly, +// since this is blackbox a new PI will be introduced, one which +// will have the relevant arrival time (corresponding to delay from +// AREG to P) attached. +// Note: Since these "$__ABC_DSP48E1*_*REG" modules are of a +// sequential nature, they are not passed as a box to ABC./ +// +// On the other hand, the "$__ABC_DSP48E1_MUX" is a combinatorial +// blackbox that is passed to ABC, with zero delay. +// +// Doing so should means that ABC is able to analyse the +// worst-case delay through to P, regardless of if it was +// through any combinatorial paths (e.g. B, below) or an +// internal register (A2REG). +// However, the true value of being as complete as this is +// questionable since if AREG=1 and BREG=0 (as below) +// then the worse-case path would very likely be through B +// and very unlikely to be through AREG.Q...? +// +// In graphical form: +// +// +-----+ +// +-------| REG |-----+ +// | +-----+ | +// | | +// | +---------+ | __ +// A >>-+X X-| | +--| \ +// | DSP48E1 |P | M |--->> P +// | AREG=1 |-------|__/ +// B >>------| | +// +---------+ +// + +(* abc_box_id=2100 *) +module \$__ABC_DSP48E1_MUX (input Aq, ADq, Bq, Cq, Dq, Mq, input [47:0] P, input Pq, output [47:0] O); +endmodule + +module $__ABC_DSP48E1_MULT_AREG (input [29:0] I, output [29:0] O, (* abc_arrival=2952 *) output P, (* abc_arrival=3098 *) output PCOUT); endmodule +module $__ABC_DSP48E1_MULT_BREG (input [17:0] I, output [17:0] O, (* abc_arrival=2813 *) output P, (* abc_arrival=2960 *) output PCOUT); endmodule +module $__ABC_DSP48E1_MULT_CREG (input [47:0] I, output [47:0] O, (* abc_arrival=1687 *) output P, (* abc_arrival=1835 *) output PCOUT); endmodule +module $__ABC_DSP48E1_MULT_MREG (input [47:0] I, output [47:0] O, (* abc_arrival=1671 *) output P, (* abc_arrival=1819 *) output PCOUT); endmodule +module $__ABC_DSP48E1_MULT_PREG (input [47:0] I, output [47:0] O, (* abc_arrival= 329 *) output P, (* abc_arrival= 435 *) output PCOUT); endmodule + +module $__ABC_DSP48E1_MULT_DPORT_AREG (input [29:0] I, output [29:0] O, (* abc_arrival=3935 *) output P, (* abc_arrival=4083 *) output PCOUT); endmodule +module $__ABC_DSP48E1_MULT_DPORT_BREG (input [17:0] I, output [17:0] O, (* abc_arrival=2813 *) output P, (* abc_arrival=2960 *) output PCOUT); endmodule +module $__ABC_DSP48E1_MULT_DPORT_CREG (input [47:0] I, output [47:0] O, (* abc_arrival=1687 *) output P, (* abc_arrival=1835 *) output PCOUT); endmodule +module $__ABC_DSP48E1_MULT_DPORT_DREG (input [47:0] I, output [47:0] O, (* abc_arrival=3908 *) output P, (* abc_arrival=4056 *) output PCOUT); endmodule +module $__ABC_DSP48E1_MULT_DPORT_ADREG (input [47:0] I, output [47:0] O, (* abc_arrival=2958 *) output P, (* abc_arrival=2859 *) output PCOUT); endmodule +module $__ABC_DSP48E1_MULT_DPORT_MREG (input [47:0] I, output [47:0] O, (* abc_arrival=1671 *) output P, (* abc_arrival=1819 *) output PCOUT); endmodule +module $__ABC_DSP48E1_MULT_DPORT_PREG (input [47:0] I, output [47:0] O, (* abc_arrival= 329 *) output P, (* abc_arrival= 435 *) output PCOUT); endmodule + +module $__ABC_DSP48E1_AREG (input [29:0] I, output [29:0] O, (* abc_arrival=1632 *) output P, (* abc_arrival=1780 *) output PCOUT); endmodule +module $__ABC_DSP48E1_BREG (input [17:0] I, output [17:0] O, (* abc_arrival=1616 *) output P, (* abc_arrival=1765 *) output PCOUT); endmodule +module $__ABC_DSP48E1_CREG (input [47:0] I, output [47:0] O, (* abc_arrival=1687 *) output P, (* abc_arrival=1835 *) output PCOUT); endmodule +module $__ABC_DSP48E1_PREG (input [47:0] I, output [47:0] O, (* abc_arrival= 329 *) output P, (* abc_arrival= 435 *) output PCOUT); endmodule diff --git a/techlibs/xilinx/abc_unmap.v b/techlibs/xilinx/abc_unmap.v index 010041b73..8700393ab 100644 --- a/techlibs/xilinx/abc_unmap.v +++ b/techlibs/xilinx/abc_unmap.v @@ -27,10 +27,10 @@ module \$__ABC_LUT7 (input A, input [6:0] S, output Y); assign Y = A; endmodule -module \$__ABC_DSP48E1_REG (input [47:0] I, output [47:0] O, output Q); +(* techmap_celltype = "$__ABC_DSP48E1_MULT_AREG $__ABC_DSP48E1_MULT_BREG $__ABC_DSP48E1_MULT_CREG $__ABC_DSP48E1_MULT_MREG $__ABC_DSP48E1_MULT_PREG $__ABC_DSP48E1_MULT_DPORT_AREG $__ABC_DSP48E1_MULT_DPORT_BREG $__ABC_DSP48E1_MULT_DPORT_CREG $__ABC_DSP48E1_MULT_DPORT_DREG $__ABC_DSP48E1_MULT_DPORT_ADREG $__ABC_DSP48E1_MULT_DPORT_MREG $__ABC_DSP48E1_MULT_DPORT_PREG " *) +module \$__ABC_DSP48E1_REG (input [47:0] I, output [47:0] O, output P, PCOUT); assign O = I; endmodule -(* techmap_celltype = "$__ABC_DSP48E1_MULT_P_MUX $__ABC_DSP48E1_MULT_PCOUT_MUX $__ABC_DSP48E1_MULT_DPORT_P_MUX $__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX $__ABC_DSP48E1_P_MUX $__ABC_DSP48E1_PCOUT_MUX" *) module \$__ABC_DSP48E1_MUX ( input Aq, Bq, Cq, Dq, ADq, Mq, input [47:0] P, diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box index 79b400d40..ff4f87a0a 100644 --- a/techlibs/xilinx/abc_xc7.box +++ b/techlibs/xilinx/abc_xc7.box @@ -70,306 +70,56 @@ $__ABC_LUT7 2001 0 8 1 # the mux at zero time, the combinatorial delay through # these muxes thus represents the clock-to-q delay at # P/PCOUT. -$__ABC_DSP48E1_MULT_P_MUX 2100 0 55 48 -# A AD B C D M P Pq -2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 -2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 -2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 -2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 -2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 -2952 - 2813 1687 - 1671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 329 -2952 - 2813 1687 - 1671 0 0 0 0 0 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0 0 0 0 0 0 0 0 +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 $__ABC_DSP48E1_MULT 3000 0 263 154 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 - - 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 - -- cgit v1.2.3 From 362a803779ac1a8a3af1e4991b80b0c4c71e02ff Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 19 Sep 2019 18:33:38 -0700 Subject: Revert "Different approach to timing" This reverts commit 41256f48a5f3231e231cbdf9380a26128f272044. --- techlibs/xilinx/abc_map.v | 141 ++++++++---------- techlibs/xilinx/abc_model.v | 105 ++++++------- techlibs/xilinx/abc_unmap.v | 4 +- techlibs/xilinx/abc_xc7.box | 350 +++++++++++++++++++++++++++++++++++++------- 4 files changed, 405 insertions(+), 195 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v index 124ce6d8f..1b7900af8 100644 --- a/techlibs/xilinx/abc_map.v +++ b/techlibs/xilinx/abc_map.v @@ -299,60 +299,49 @@ __CELL__ #( wire [47:0] iC; wire [24:0] iD; - wire pAP, pBP, pCP, pDP, pADP, pMP, pPP; - wire pAPCOUT, pBPCOUT, pCPCOUT, pDPCOUT, pADPCOUT, pMPCOUT, pPPCOUT; + wire pA, pB, pC, pD, pAD, pM, pP; wire [47:0] oP, oPCOUT; - // Disconnect the A-input if MREG is enabled, since - // combinatorial path is broken + // Disconnect the A-input if MREG is enabled, since + // combinatorial path is broken if (AREG == 0 && MREG == 0 && PREG == 0) - assign iA = A, pAP = 1'bx, pAPCOUT = 1'bx; + assign iA = A, pA = 1'bx; else - \$__ABC_DSP48E1_MULT_AREG rA (.I(A), .O(iA), .P(pAP), .PCOUT(pAPCOUT)); + \$__ABC_DSP48E1_REG rA (.I(A), .O(iA), .Q(pA)); if (BREG == 0 && MREG == 0 && PREG == 0) - assign iB = B, pBP = 1'bx, pBPCOUT = 1'bx; + assign iB = B, pB = 1'bx; else - \$__ABC_DSP48E1_MULT_BREG rB (.I(B), .O(iB), .P(pBP), .PCOUT(pBPCOUT)); + \$__ABC_DSP48E1_REG rB (.I(B), .O(iB), .Q(pB)); if (CREG == 0 && PREG == 0) - assign iC = C, pCP = 1'bx, pCPCOUT = 1'bx; + assign iC = C, pC = 1'bx; else - \$__ABC_DSP48E1_MULT_CREG rC (.I(C), .O(iC), .P(pCP), .PCOUT(pCPCOUT)); + \$__ABC_DSP48E1_REG rC (.I(C), .O(iC), .Q(pC)); if (DREG == 0) assign iD = D; else if (techmap_guard) - $error("Invalid DSP48E1 configuration: DREG enabled but USE_DPORT == \"FALSE\""); - assign pDP = 1'bx, pDPCOUT = 1'bx; + $error("Invalid DSP48E1 configuration: DREG enabled but USE_DPORT == \"FALSE\""); + assign pD = 1'bx; if (ADREG == 1 && techmap_guard) $error("Invalid DSP48E1 configuration: ADREG enabled but USE_DPORT == \"FALSE\""); - assign pADP = 1'bx, pADPCOUT = 1'bx; + assign pAD = 1'bx; if (PREG == 0) begin + assign pP = 1'bx; if (MREG == 1) - \$__ABC_DSP48E1_MULT_MREG rM (.P(pMP), .PCOUT(pMPCOUT)); + \$__ABC_DSP48E1_REG rM (.Q(pM)); else - assign pMP = 1'bx, pMPCOUT = 1'bx; - assign pPP = 1'bx, pPPCOUT = 1'bx; + assign pM = 1'bx; end else begin - assign pMP = 1'bx, pMPCOUT = 1'bx; - \$__ABC_DSP48E1_MULT_PREG rP (.P(pPP), .PCOUT(pPPCOUT)); + \$__ABC_DSP48E1_REG rP (.Q(pP)); + assign pM = 1'bx; end - if (MREG == 0 && PREG == 0) begin - \$__ABC_DSP48E1_MUX muxP ( - .Aq(pAP), .Bq(pBP), .Cq(pCP), .Dq(pDP), .ADq(pADP), .Mq(pMP), .P(oP), .Pq(pPP), .O(P) - ); - \$__ABC_DSP48E1_MUX muxPCOUT ( - .Aq(pAPCOUT), .Bq(pBPCOUT), .Cq(pCPCOUT), .Dq(pDPCOUT), .ADq(pADPCOUT), .Mq(pMPCOUT), .P(oPCOUT), .Pq(pPPCOUT), .O(PCOUT) - ); - end - else begin - \$__ABC_DSP48E1_MUX muxP ( - .Aq(pAP), .Bq(pBP), .Cq(pCP), .Dq(pDP), .ADq(pADP), .Mq(pMP), .P(1'bx), .Pq(pPP), .O(P) - ); - \$__ABC_DSP48E1_MUX muxPCOUT ( - .Aq(pAPCOUT), .Bq(pBPCOUT), .Cq(pCPCOUT), .Dq(pDPCOUT), .ADq(pADPCOUT), .Mq(pMPCOUT), .P(1'bx), .Pq(pPPCOUT), .O(PCOUT) - ); - end + \$__ABC_DSP48E1_MULT_P_MUX muxP ( + .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oP), .Pq(pP), .O(P) + ); + \$__ABC_DSP48E1_MULT_PCOUT_MUX muxPCOUT ( + .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oPCOUT), .Pq(pP), .O(PCOUT) + ); `DSP48E1_INST(\$__ABC_DSP48E1_MULT ) end @@ -362,53 +351,46 @@ __CELL__ #( wire [47:0] iC; wire [24:0] iD; - wire pAP, pBP, pCP, pDP, pADP, pMP, pPP; - wire pAPCOUT, pBPCOUT, pCPCOUT, pDPCOUT, pADPCOUT, pMPCOUT, pPPCOUT; + wire pA, pB, pC, pD, pAD, pM, pP; wire [47:0] oP, oPCOUT; // Disconnect the A-input if MREG is enabled, since // combinatorial path is broken if (AREG == 0 && ADREG == 0 && MREG == 0 && PREG == 0) - assign iA = A, pAP = 1'bx, pAPCOUT = 1'bx; + assign iA = A, pA = 1'bx; else - \$__ABC_DSP48E1_MULT_DPORT_AREG rA (.I(A), .O(iA), .P(pAP), .PCOUT(pAPCOUT)); + \$__ABC_DSP48E1_REG rA (.I(A), .O(iA), .Q(pA)); if (BREG == 0 && MREG == 0 && PREG == 0) - assign iB = B, pBP = 1'bx, pBPCOUT = 1'bx; + assign iB = B, pB = 1'bx; else - \$__ABC_DSP48E1_MULT_DPORT_BREG rB (.I(B), .O(iB), .P(pBP), .PCOUT(pBPCOUT)); + \$__ABC_DSP48E1_REG rB (.I(B), .O(iB), .Q(pB)); if (CREG == 0 && PREG == 0) - assign iC = C, pCP = 1'bx, pCPCOUT = 1'bx; + assign iC = C, pC = 1'bx; else - \$__ABC_DSP48E1_MULT_DPORT_CREG rC (.I(C), .O(iC), .P(pCP), .PCOUT(pCPCOUT)); + \$__ABC_DSP48E1_REG rC (.I(C), .O(iC), .Q(pC)); if (DREG == 0 && ADREG == 0) - assign iD = D, pDP = 1'bx, pDPCOUT = 1'bx; + assign iD = D, pD = 1'bx; else - \$__ABC_DSP48E1_MULT_DPORT_DREG rD (.I(D), .O(iD), .P(pDP), .PCOUT(pDPCOUT)); + \$__ABC_DSP48E1_REG rD (.I(D), .O(iD), .Q(pD)); if (PREG == 0) begin - if (MREG == 1) begin - assign pADP = 1'bx, pADPCOUT = 1'bx; - \$__ABC_DSP48E1_MULT_DPORT_MREG rM (.P(pMP), .PCOUT(pMPCOUT)); - end + if (MREG == 1) + \$__ABC_DSP48E1_REG rM (.Q(pM)); else begin + assign pM = 1'bx; if (ADREG == 1) - \$__ABC_DSP48E1_MULT_DPORT_ADPREG rAD (.P(pADP), .PCOUT(pADPCOUT)); + \$__ABC_DSP48E1_REG rAD (.Q(pAD)); else - assign pADP = 1'bx, pADPCOUT = 1'bx; - assign pMP = 1'bx, pMPCOUT = 1'bx; + assign pAD = 1'bx; end - assign pPP = 1'bx, pPPCOUT = 1'bx; end - else begin - assign pADP = 1'bx, pADPCOUT = 1'bx; - assign pMP = 1'bx, pMPCOUT = 1'bx; - \$__ABC_DSP48E1_MULT_DPORT_PREG rP (.P(pPP), .PCOUT(pPPCOUT)); - end + else + \$__ABC_DSP48E1_REG rP (.Q(pP)); - \$__ABC_DSP48E1_MUX muxP ( - .Aq(pAP), .Bq(pBP), .Cq(pCP), .Dq(pDP), .ADq(pADP), .Mq(pMP), .P(oP), .Pq(pPP), .O(P) + \$__ABC_DSP48E1_MULT_DPORT_P_MUX muxP ( + .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oP), .Pq(pP), .O(P) ); - \$__ABC_DSP48E1_MUX muxPCOUT ( - .Aq(pAPCOUT), .Bq(pBPCOUT), .Cq(pCPCOUT), .Dq(pDPCOUT), .ADq(pADPCOUT), .Mq(pMPCOUT), .P(oPCOUT), .Pq(pPPCOUT), .O(PCOUT) + \$__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX muxPCOUT ( + .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oPCOUT), .Pq(pP), .O(PCOUT) ); `DSP48E1_INST(\$__ABC_DSP48E1_MULT_DPORT ) @@ -419,43 +401,42 @@ __CELL__ #( wire [47:0] iC; wire [24:0] iD; - wire pAP, pBP, pCP, pDP, pADP, pMP, pPP; - wire pAPCOUT, pBPCOUT, pCPCOUT, pDPCOUT, pADPCOUT, pMPCOUT, pPPCOUT; + wire pA, pB, pC, pD, pAD, pM, pP; wire [47:0] oP, oPCOUT; // Disconnect the A-input if MREG is enabled, since // combinatorial path is broken if (AREG == 0 && PREG == 0) - assign iA = A, pAP = 1'bx, pAPCOUT = 1'bx; + assign iA = A, pA = 1'bx; else - \$__ABC_DSP48E1_AREG rA (.I(A), .O(iA), .P(pAP), .PCOUT(pAPCOUT)); + \$__ABC_DSP48E1_REG rA (.I(A), .O(iA), .Q(pA)); if (BREG == 0 && PREG == 0) - assign iB = B, pBP = 1'bx, pBPCOUT = 1'bx; + assign iB = B, pB = 1'bx; else - \$__ABC_DSP48E1_BREG rB (.I(B), .O(iB), .P(pB), .PCOUT(pBPCOUT)); + \$__ABC_DSP48E1_REG rB (.I(B), .O(iB), .Q(pB)); if (CREG == 0 && PREG == 0) - assign iC = C, pCP = 1'bx, pCPCOUT = 1'bx; + assign iC = C, pC = 1'bx; else - \$__ABC_DSP48E1_CREG rC (.I(C), .O(iC), .P(pC), .PCOUT(pCPCOUT)); + \$__ABC_DSP48E1_REG rC (.I(C), .O(iC), .Q(pC)); + if (MREG == 1 && techmap_guard) + $error("Invalid DSP48E1 configuration: MREG enabled but USE_MULT == \"NONE\""); + assign pM = 1'bx; if (DREG == 1 && techmap_guard) $error("Invalid DSP48E1 configuration: DREG enabled but USE_DPORT == \"FALSE\""); - assign iD = 25'bx, pDP = 1'bx, pDPCOUT = 1'bx; + assign pD = 1'bx; if (ADREG == 1 && techmap_guard) $error("Invalid DSP48E1 configuration: ADREG enabled but USE_DPORT == \"FALSE\""); - assign pADP = 1'bx, pADPCOUT = 1'bx; - if (MREG == 1 && techmap_guard) - $error("Invalid DSP48E1 configuration: MREG enabled but USE_MULT == \"NONE\""); - assign pMP = 1'bx, pMPCOUT = 1'bx; + assign pAD = 1'bx; if (PREG == 1) - \$__ABC_DSP48E1_PREG rP (.P(pPP), .P(pPCOUT)); + \$__ABC_DSP48E1_REG rP (.Q(pP)); else - assign pPP = 1'bx, pPPCOUT = 1'bx; + assign pP = 1'bx; - \$__ABC_DSP48E1_MUX muxP ( - .Aq(pAP), .Bq(pBP), .Cq(pCP), .Dq(pDP), .ADq(pADP), .Mq(pMP), .P(oP), .Pq(pPP), .O(P) + \$__ABC_DSP48E1_P_MUX muxP ( + .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oP), .Pq(pP), .O(P) ); - \$__ABC_DSP48E1_MUX muxPCOUT ( - .Aq(pAPCOUT), .Bq(pBPCOUT), .Cq(pCPCOUT), .Dq(pDPCOUT), .ADq(pADPCOUT), .Mq(pMPCOUT), .P(oPCOUT), .Pq(pPPCOUT), .O(PCOUT) + \$__ABC_DSP48E1_PCOUT_MUX muxPCOUT ( + .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oPCOUT), .Pq(pP), .O(PCOUT) ); `DSP48E1_INST(\$__ABC_DSP48E1 ) diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc_model.v index 79cca6b7b..a8f6deafc 100644 --- a/techlibs/xilinx/abc_model.v +++ b/techlibs/xilinx/abc_model.v @@ -44,6 +44,48 @@ endmodule module \$__ABC_LUT7 (input A, input [6:0] S, output Y); endmodule +// Boxes used to represent the comb/seq behaviour of DSP48E1 +// With abc_map.v responsible for disconnecting inputs to +// the combinatorial DSP48E1 model by a register (e.g. +// disconnecting A when AREG, MREG or PREG is enabled) +// this blackbox captures the existence of a replacement +// path between AREG/BREG/CREG/etc. and P/PCOUT. +// Since the Aq/ADq/Bq/etc. inputs are assumed to arrive at +// the box at zero time, the combinatorial delay through +// these boxes thus represents the clock-to-q delay +// (arrival time) at P/PCOUT. +// Doing so should means that ABC is able to analyse the +// worst-case delay through to P, regardless of if it was +// through any combinatorial paths (e.g. B, below) or an +// internal register (A2REG). +// However, the true value of being as complete as this is +// questionable since if AREG=1 and BREG=0 (as below) +// then the worse-case path would very likely be through B +// and very unlikely to be through AREG.Q...? +// +// In graphical form: +// +// NEW "PI" >>---+ +// for AREG.Q | +// | +// +---------+ | __ +// A >>--X X-| | +--| \ +// | DSP48E1 |P | |--->> P +// | AREG=1 |-------|__/ +// B >>------| | +// +---------+ +// +`define ABC_DSP48E1_MUX(__NAME__) """ +module __NAME__ (input Aq, ADq, Bq, Cq, Dq, Mq, input [47:0] P, input Pq, output [47:0] O); +endmodule +""" +(* abc_box_id=2100 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_P_MUX ) +(* abc_box_id=2101 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_PCOUT_MUX ) +(* abc_box_id=2102 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_DPORT_P_MUX ) +(* abc_box_id=2103 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX ) +(* abc_box_id=2104 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_P_MUX ) +(* abc_box_id=2105 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_PCOUT_MUX ) + `define ABC_DSP48E1(__NAME__) """ module \$__ABC_DSP48E1_MULT ( output [29:0] ACOUT, @@ -131,66 +173,3 @@ endmodule (* abc_box_id=3000 *) `ABC_DSP48E1(\$__ABC_DSP48E1_MULT ) (* abc_box_id=3001 *) `ABC_DSP48E1(\$__ABC_DSP48E1_MULT_DPORT ) (* abc_box_id=3002 *) `ABC_DSP48E1(\$__ABC_DSP48E1 ) - - -// Modules used to model the comb/seq behaviour of DSP48E1 -// With abc_map.v responsible for splicing the below modules -// into between the combinatorial DSP48E1 box (e.g. disconnecting -// A when AREG, MREG or PREG is enabled and splicing in the -// "$__ABC_DSP48E1_MULT_AREG" blackbox as "REG" in the diagram -// below) this acts to first disables the combinatorial path -// (as there is no connectivity through REG), and secondly, -// since this is blackbox a new PI will be introduced, one which -// will have the relevant arrival time (corresponding to delay from -// AREG to P) attached. -// Note: Since these "$__ABC_DSP48E1*_*REG" modules are of a -// sequential nature, they are not passed as a box to ABC./ -// -// On the other hand, the "$__ABC_DSP48E1_MUX" is a combinatorial -// blackbox that is passed to ABC, with zero delay. -// -// Doing so should means that ABC is able to analyse the -// worst-case delay through to P, regardless of if it was -// through any combinatorial paths (e.g. B, below) or an -// internal register (A2REG). -// However, the true value of being as complete as this is -// questionable since if AREG=1 and BREG=0 (as below) -// then the worse-case path would very likely be through B -// and very unlikely to be through AREG.Q...? -// -// In graphical form: -// -// +-----+ -// +-------| REG |-----+ -// | +-----+ | -// | | -// | +---------+ | __ -// A >>-+X X-| | +--| \ -// | DSP48E1 |P | M |--->> P -// | AREG=1 |-------|__/ -// B >>------| | -// +---------+ -// - -(* abc_box_id=2100 *) -module \$__ABC_DSP48E1_MUX (input Aq, ADq, Bq, Cq, Dq, Mq, input [47:0] P, input Pq, output [47:0] O); -endmodule - -module $__ABC_DSP48E1_MULT_AREG (input [29:0] I, output [29:0] O, (* abc_arrival=2952 *) output P, (* abc_arrival=3098 *) output PCOUT); endmodule -module $__ABC_DSP48E1_MULT_BREG (input [17:0] I, output [17:0] O, (* abc_arrival=2813 *) output P, (* abc_arrival=2960 *) output PCOUT); endmodule -module $__ABC_DSP48E1_MULT_CREG (input [47:0] I, output [47:0] O, (* abc_arrival=1687 *) output P, (* abc_arrival=1835 *) output PCOUT); endmodule -module $__ABC_DSP48E1_MULT_MREG (input [47:0] I, output [47:0] O, (* abc_arrival=1671 *) output P, (* abc_arrival=1819 *) output PCOUT); endmodule -module $__ABC_DSP48E1_MULT_PREG (input [47:0] I, output [47:0] O, (* abc_arrival= 329 *) output P, (* abc_arrival= 435 *) output PCOUT); endmodule - -module $__ABC_DSP48E1_MULT_DPORT_AREG (input [29:0] I, output [29:0] O, (* abc_arrival=3935 *) output P, (* abc_arrival=4083 *) output PCOUT); endmodule -module $__ABC_DSP48E1_MULT_DPORT_BREG (input [17:0] I, output [17:0] O, (* abc_arrival=2813 *) output P, (* abc_arrival=2960 *) output PCOUT); endmodule -module $__ABC_DSP48E1_MULT_DPORT_CREG (input [47:0] I, output [47:0] O, (* abc_arrival=1687 *) output P, (* abc_arrival=1835 *) output PCOUT); endmodule -module $__ABC_DSP48E1_MULT_DPORT_DREG (input [47:0] I, output [47:0] O, (* abc_arrival=3908 *) output P, (* abc_arrival=4056 *) output PCOUT); endmodule -module $__ABC_DSP48E1_MULT_DPORT_ADREG (input [47:0] I, output [47:0] O, (* abc_arrival=2958 *) output P, (* abc_arrival=2859 *) output PCOUT); endmodule -module $__ABC_DSP48E1_MULT_DPORT_MREG (input [47:0] I, output [47:0] O, (* abc_arrival=1671 *) output P, (* abc_arrival=1819 *) output PCOUT); endmodule -module $__ABC_DSP48E1_MULT_DPORT_PREG (input [47:0] I, output [47:0] O, (* abc_arrival= 329 *) output P, (* abc_arrival= 435 *) output PCOUT); endmodule - -module $__ABC_DSP48E1_AREG (input [29:0] I, output [29:0] O, (* abc_arrival=1632 *) output P, (* abc_arrival=1780 *) output PCOUT); endmodule -module $__ABC_DSP48E1_BREG (input [17:0] I, output [17:0] O, (* abc_arrival=1616 *) output P, (* abc_arrival=1765 *) output PCOUT); endmodule -module $__ABC_DSP48E1_CREG (input [47:0] I, output [47:0] O, (* abc_arrival=1687 *) output P, (* abc_arrival=1835 *) output PCOUT); endmodule -module $__ABC_DSP48E1_PREG (input [47:0] I, output [47:0] O, (* abc_arrival= 329 *) output P, (* abc_arrival= 435 *) output PCOUT); endmodule diff --git a/techlibs/xilinx/abc_unmap.v b/techlibs/xilinx/abc_unmap.v index 8700393ab..010041b73 100644 --- a/techlibs/xilinx/abc_unmap.v +++ b/techlibs/xilinx/abc_unmap.v @@ -27,10 +27,10 @@ module \$__ABC_LUT7 (input A, input [6:0] S, output Y); assign Y = A; endmodule -(* techmap_celltype = "$__ABC_DSP48E1_MULT_AREG $__ABC_DSP48E1_MULT_BREG $__ABC_DSP48E1_MULT_CREG $__ABC_DSP48E1_MULT_MREG $__ABC_DSP48E1_MULT_PREG $__ABC_DSP48E1_MULT_DPORT_AREG $__ABC_DSP48E1_MULT_DPORT_BREG $__ABC_DSP48E1_MULT_DPORT_CREG $__ABC_DSP48E1_MULT_DPORT_DREG $__ABC_DSP48E1_MULT_DPORT_ADREG $__ABC_DSP48E1_MULT_DPORT_MREG $__ABC_DSP48E1_MULT_DPORT_PREG " *) -module \$__ABC_DSP48E1_REG (input [47:0] I, output [47:0] O, output P, PCOUT); +module \$__ABC_DSP48E1_REG (input [47:0] I, output [47:0] O, output Q); assign O = I; endmodule +(* techmap_celltype = "$__ABC_DSP48E1_MULT_P_MUX $__ABC_DSP48E1_MULT_PCOUT_MUX $__ABC_DSP48E1_MULT_DPORT_P_MUX $__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX $__ABC_DSP48E1_P_MUX $__ABC_DSP48E1_PCOUT_MUX" *) module \$__ABC_DSP48E1_MUX ( input Aq, Bq, Cq, Dq, ADq, Mq, input [47:0] P, diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box index ff4f87a0a..79b400d40 100644 --- a/techlibs/xilinx/abc_xc7.box +++ b/techlibs/xilinx/abc_xc7.box @@ -70,56 +70,306 @@ $__ABC_LUT7 2001 0 8 1 # the mux at zero time, the combinatorial delay through # these muxes thus represents the clock-to-q delay at # P/PCOUT. -$__ABC_DSP48E1_MUX 2100 0 55 48 -#A AD B C D M P Pq -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 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2823 2823 - - 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 - -- cgit v1.2.3 From e09f80479e6d16cf95c26e406bf06d81b94231f4 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 19 Sep 2019 18:59:28 -0700 Subject: Fix DSP48E1 timing by breaking P path if MREG or PREG --- techlibs/xilinx/abc_map.v | 57 ++--- techlibs/xilinx/abc_model.v | 49 ++-- techlibs/xilinx/abc_unmap.v | 6 +- techlibs/xilinx/abc_xc7.box | 600 ++++++++++++++++++++++---------------------- 4 files changed, 363 insertions(+), 349 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v index 1b7900af8..01307fcf2 100644 --- a/techlibs/xilinx/abc_map.v +++ b/techlibs/xilinx/abc_map.v @@ -292,16 +292,17 @@ __CELL__ #( ); """ - generate - if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin - wire [29:0] iA; - wire [17:0] iB; - wire [47:0] iC; - wire [24:0] iD; + wire [29:0] iA; + wire [17:0] iB; + wire [47:0] iC; + wire [24:0] iD; - wire pA, pB, pC, pD, pAD, pM, pP; - wire [47:0] oP, oPCOUT; + wire pA, pB, pC, pD, pAD, pM, pP; + wire [47:0] oP, mP; + wire [47:0] oPCOUT, mPCOUT; + generate + if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin // Disconnect the A-input if MREG is enabled, since // combinatorial path is broken if (AREG == 0 && MREG == 0 && PREG == 0) @@ -336,24 +337,20 @@ __CELL__ #( assign pM = 1'bx; end + if (MREG == 0 && PREG == 0) + assign mP = oP, mPCOUT = oPCOUT; + else + assign mP = 1'bx, mPCOUT = 1'bx; \$__ABC_DSP48E1_MULT_P_MUX muxP ( - .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oP), .Pq(pP), .O(P) + .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oP), .Mq(pM), .P(mP), .Pq(pP), .O(P) ); \$__ABC_DSP48E1_MULT_PCOUT_MUX muxPCOUT ( - .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oPCOUT), .Pq(pP), .O(PCOUT) + .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oPCOUT), .Mq(pM), .P(mPCOUT), .Pq(pP), .O(PCOUT) ); `DSP48E1_INST(\$__ABC_DSP48E1_MULT ) end else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin - wire [29:0] iA; - wire [17:0] iB; - wire [47:0] iC; - wire [24:0] iD; - - wire pA, pB, pC, pD, pAD, pM, pP; - wire [47:0] oP, oPCOUT; - // Disconnect the A-input if MREG is enabled, since // combinatorial path is broken if (AREG == 0 && ADREG == 0 && MREG == 0 && PREG == 0) @@ -386,24 +383,20 @@ __CELL__ #( else \$__ABC_DSP48E1_REG rP (.Q(pP)); + if (MREG == 0 && PREG == 0) + assign mP = oP, mPCOUT = oPCOUT; + else + assign mP = 1'bx, mPCOUT = 1'bx; \$__ABC_DSP48E1_MULT_DPORT_P_MUX muxP ( - .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oP), .Pq(pP), .O(P) + .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oP), .Mq(pM), .P(mP), .Pq(pP), .O(P) ); \$__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX muxPCOUT ( - .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oPCOUT), .Pq(pP), .O(PCOUT) + .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oPCOUT), .Mq(pM), .P(mPCOUT), .Pq(pP), .O(PCOUT) ); `DSP48E1_INST(\$__ABC_DSP48E1_MULT_DPORT ) end else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin - wire [29:0] iA; - wire [17:0] iB; - wire [47:0] iC; - wire [24:0] iD; - - wire pA, pB, pC, pD, pAD, pM, pP; - wire [47:0] oP, oPCOUT; - // Disconnect the A-input if MREG is enabled, since // combinatorial path is broken if (AREG == 0 && PREG == 0) @@ -432,11 +425,15 @@ __CELL__ #( else assign pP = 1'bx; + if (MREG == 0 && PREG == 0) + assign mP = oP, mPCOUT = oPCOUT; + else + assign mP = 1'bx, mPCOUT = 1'bx; \$__ABC_DSP48E1_P_MUX muxP ( - .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oP), .Pq(pP), .O(P) + .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oP), .Mq(pM), .P(mP), .Pq(pP), .O(P) ); \$__ABC_DSP48E1_PCOUT_MUX muxPCOUT ( - .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oPCOUT), .Pq(pP), .O(PCOUT) + .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oPCOUT), .Mq(pM), .P(mPCOUT), .Pq(pP), .O(PCOUT) ); `DSP48E1_INST(\$__ABC_DSP48E1 ) diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc_model.v index a8f6deafc..1c69dd21c 100644 --- a/techlibs/xilinx/abc_model.v +++ b/techlibs/xilinx/abc_model.v @@ -44,16 +44,30 @@ endmodule module \$__ABC_LUT7 (input A, input [6:0] S, output Y); endmodule -// Boxes used to represent the comb/seq behaviour of DSP48E1 -// With abc_map.v responsible for disconnecting inputs to -// the combinatorial DSP48E1 model by a register (e.g. -// disconnecting A when AREG, MREG or PREG is enabled) -// this blackbox captures the existence of a replacement -// path between AREG/BREG/CREG/etc. and P/PCOUT. -// Since the Aq/ADq/Bq/etc. inputs are assumed to arrive at -// the box at zero time, the combinatorial delay through -// these boxes thus represents the clock-to-q delay -// (arrival time) at P/PCOUT. + +// Modules used to model the comb/seq behaviour of DSP48E1 +// With abc_map.v responsible for splicing the below modules +// into between the combinatorial DSP48E1 box (e.g. disconnecting +// A when AREG, MREG or PREG is enabled and splicing in the +// "$__ABC_DSP48E1_REG" blackbox as "REG" in the diagram below) +// this acts to first disables the combinatorial path (as there +// is no connectivity through REG), and secondly, since this is +// blackbox a new PI will be introduced with an arrival time of +// zero. +// Note: Since these "$__ABC_DSP48E1_REG" modules are of a +// sequential nature, they are not passed as a box to ABC and +// (desirably) represented as PO/PIs. +// +// At the DSP output, we place a blackbox mux ("M" in the diagram +// below) to capture the fact that the critical-path could come +// from any one of its inputs. +// In contrast to "REG", the "$__ABC_DSP48E1_*_MUX" modules are +// combinatorial blackboxes that do get passed to ABC. +// The propagation delay through this box (specified in the box +// file) captures the arrival time of the register (i.e. +// propagation from AREG to P after clock edge), or zero delay +// for the combinatorial path from the DSP. +// // Doing so should means that ABC is able to analyse the // worst-case delay through to P, regardless of if it was // through any combinatorial paths (e.g. B, below) or an @@ -65,18 +79,19 @@ endmodule // // In graphical form: // -// NEW "PI" >>---+ -// for AREG.Q | -// | -// +---------+ | __ -// A >>--X X-| | +--| \ -// | DSP48E1 |P | |--->> P +// +-----+ +// +------>> REG >>----+ +// | +-----+ | +// | | +// | +---------+ | __ +// A >>-+X X-| | +--| \ +// | DSP48E1 |P | M |--->> P // | AREG=1 |-------|__/ // B >>------| | // +---------+ // `define ABC_DSP48E1_MUX(__NAME__) """ -module __NAME__ (input Aq, ADq, Bq, Cq, Dq, Mq, input [47:0] P, input Pq, output [47:0] O); +module __NAME__ (input Aq, ADq, Bq, Cq, Dq, input [47:0] I, input Mq, input [47:0] P, input Pq, output [47:0] O); endmodule """ (* abc_box_id=2100 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_P_MUX ) diff --git a/techlibs/xilinx/abc_unmap.v b/techlibs/xilinx/abc_unmap.v index 010041b73..137829d65 100644 --- a/techlibs/xilinx/abc_unmap.v +++ b/techlibs/xilinx/abc_unmap.v @@ -32,12 +32,14 @@ module \$__ABC_DSP48E1_REG (input [47:0] I, output [47:0] O, output Q); endmodule (* techmap_celltype = "$__ABC_DSP48E1_MULT_P_MUX $__ABC_DSP48E1_MULT_PCOUT_MUX $__ABC_DSP48E1_MULT_DPORT_P_MUX $__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX $__ABC_DSP48E1_P_MUX $__ABC_DSP48E1_PCOUT_MUX" *) module \$__ABC_DSP48E1_MUX ( - input Aq, Bq, Cq, Dq, ADq, Mq, + input Aq, Bq, Cq, Dq, ADq, + input [47:0] I, + input Mq, input [47:0] P, input Pq, output [47:0] O ); - assign O = P; + assign O = I; endmodule (* techmap_celltype = "$__ABC_DSP48E1_MULT $__ABC_DSP48E1_MULT_DPORT $__ABC_DSP48E1" *) diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box index 79b400d40..9b64b4907 100644 --- a/techlibs/xilinx/abc_xc7.box +++ b/techlibs/xilinx/abc_xc7.box @@ -70,306 +70,306 @@ $__ABC_LUT7 2001 0 8 1 # the mux at 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2970 2970 2970 - -- cgit v1.2.3 From 1602516a8b2ebd432528e9ba39a00db4e6edc081 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 19 Sep 2019 19:37:45 -0700 Subject: $__ABC_REG to have WIDTH parameter --- techlibs/xilinx/abc_map.v | 32 ++++++++++++++++---------------- techlibs/xilinx/abc_unmap.v | 3 ++- 2 files changed, 18 insertions(+), 17 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v index 01307fcf2..423da3fdb 100644 --- a/techlibs/xilinx/abc_map.v +++ b/techlibs/xilinx/abc_map.v @@ -308,15 +308,15 @@ __CELL__ #( if (AREG == 0 && MREG == 0 && PREG == 0) assign iA = A, pA = 1'bx; else - \$__ABC_DSP48E1_REG rA (.I(A), .O(iA), .Q(pA)); + \$__ABC_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA)); if (BREG == 0 && MREG == 0 && PREG == 0) assign iB = B, pB = 1'bx; else - \$__ABC_DSP48E1_REG rB (.I(B), .O(iB), .Q(pB)); + \$__ABC_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB)); if (CREG == 0 && PREG == 0) assign iC = C, pC = 1'bx; else - \$__ABC_DSP48E1_REG rC (.I(C), .O(iC), .Q(pC)); + \$__ABC_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC)); if (DREG == 0) assign iD = D; else if (techmap_guard) @@ -328,12 +328,12 @@ __CELL__ #( if (PREG == 0) begin assign pP = 1'bx; if (MREG == 1) - \$__ABC_DSP48E1_REG rM (.Q(pM)); + \$__ABC_REG rM (.Q(pM)); else assign pM = 1'bx; end else begin - \$__ABC_DSP48E1_REG rP (.Q(pP)); + \$__ABC_REG rP (.Q(pP)); assign pM = 1'bx; end @@ -356,32 +356,32 @@ __CELL__ #( if (AREG == 0 && ADREG == 0 && MREG == 0 && PREG == 0) assign iA = A, pA = 1'bx; else - \$__ABC_DSP48E1_REG rA (.I(A), .O(iA), .Q(pA)); + \$__ABC_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA)); if (BREG == 0 && MREG == 0 && PREG == 0) assign iB = B, pB = 1'bx; else - \$__ABC_DSP48E1_REG rB (.I(B), .O(iB), .Q(pB)); + \$__ABC_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB)); if (CREG == 0 && PREG == 0) assign iC = C, pC = 1'bx; else - \$__ABC_DSP48E1_REG rC (.I(C), .O(iC), .Q(pC)); + \$__ABC_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC)); if (DREG == 0 && ADREG == 0) assign iD = D, pD = 1'bx; else - \$__ABC_DSP48E1_REG rD (.I(D), .O(iD), .Q(pD)); + \$__ABC_REG #(.WIDTH(25)) rD (.I(D), .O(iD), .Q(pD)); if (PREG == 0) begin if (MREG == 1) - \$__ABC_DSP48E1_REG rM (.Q(pM)); + \$__ABC_REG rM (.Q(pM)); else begin assign pM = 1'bx; if (ADREG == 1) - \$__ABC_DSP48E1_REG rAD (.Q(pAD)); + \$__ABC_REG rAD (.Q(pAD)); else assign pAD = 1'bx; end end else - \$__ABC_DSP48E1_REG rP (.Q(pP)); + \$__ABC_REG rP (.Q(pP)); if (MREG == 0 && PREG == 0) assign mP = oP, mPCOUT = oPCOUT; @@ -402,15 +402,15 @@ __CELL__ #( if (AREG == 0 && PREG == 0) assign iA = A, pA = 1'bx; else - \$__ABC_DSP48E1_REG rA (.I(A), .O(iA), .Q(pA)); + \$__ABC_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA)); if (BREG == 0 && PREG == 0) assign iB = B, pB = 1'bx; else - \$__ABC_DSP48E1_REG rB (.I(B), .O(iB), .Q(pB)); + \$__ABC_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB)); if (CREG == 0 && PREG == 0) assign iC = C, pC = 1'bx; else - \$__ABC_DSP48E1_REG rC (.I(C), .O(iC), .Q(pC)); + \$__ABC_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC)); if (MREG == 1 && techmap_guard) $error("Invalid DSP48E1 configuration: MREG enabled but USE_MULT == \"NONE\""); assign pM = 1'bx; @@ -421,7 +421,7 @@ __CELL__ #( $error("Invalid DSP48E1 configuration: ADREG enabled but USE_DPORT == \"FALSE\""); assign pAD = 1'bx; if (PREG == 1) - \$__ABC_DSP48E1_REG rP (.Q(pP)); + \$__ABC_REG rP (.Q(pP)); else assign pP = 1'bx; diff --git a/techlibs/xilinx/abc_unmap.v b/techlibs/xilinx/abc_unmap.v index 137829d65..ab007dfd2 100644 --- a/techlibs/xilinx/abc_unmap.v +++ b/techlibs/xilinx/abc_unmap.v @@ -27,7 +27,8 @@ module \$__ABC_LUT7 (input A, input [6:0] S, output Y); assign Y = A; endmodule -module \$__ABC_DSP48E1_REG (input [47:0] I, output [47:0] O, output Q); +module \$__ABC_REG (input [WIDTH-1:0] I, output [WIDTH-1:0] O, output Q); + parameter WIDTH = 1; assign O = I; endmodule (* techmap_celltype = "$__ABC_DSP48E1_MULT_P_MUX $__ABC_DSP48E1_MULT_PCOUT_MUX $__ABC_DSP48E1_MULT_DPORT_P_MUX $__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX $__ABC_DSP48E1_P_MUX $__ABC_DSP48E1_PCOUT_MUX" *) -- cgit v1.2.3 From 691686f92c011a94a649ae7ecc2f4f22b758fc12 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 19 Sep 2019 20:04:52 -0700 Subject: Tidy up, fix undriven --- techlibs/xilinx/abc_map.v | 66 ++++++++++++++++++++++++----------------------- 1 file changed, 34 insertions(+), 32 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v index 423da3fdb..9d78725df 100644 --- a/techlibs/xilinx/abc_map.v +++ b/techlibs/xilinx/abc_map.v @@ -303,8 +303,8 @@ __CELL__ #( generate if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin - // Disconnect the A-input if MREG is enabled, since - // combinatorial path is broken + // Disconnect the A-input if MREG is enabled, since + // combinatorial path is broken if (AREG == 0 && MREG == 0 && PREG == 0) assign iA = A, pA = 1'bx; else @@ -320,21 +320,20 @@ __CELL__ #( if (DREG == 0) assign iD = D; else if (techmap_guard) - $error("Invalid DSP48E1 configuration: DREG enabled but USE_DPORT == \"FALSE\""); + $error("Invalid DSP48E1 configuration: DREG enabled but USE_DPORT == \"FALSE\""); assign pD = 1'bx; if (ADREG == 1 && techmap_guard) $error("Invalid DSP48E1 configuration: ADREG enabled but USE_DPORT == \"FALSE\""); assign pAD = 1'bx; - if (PREG == 0) begin - assign pP = 1'bx; - if (MREG == 1) - \$__ABC_REG rM (.Q(pM)); - else - assign pM = 1'bx; - end - else begin - \$__ABC_REG rP (.Q(pP)); + if (PREG == 0) begin + if (MREG == 1) + \$__ABC_REG rM (.Q(pM)); + else + assign pM = 1'bx; + assign pP = 1'bx; + end else begin assign pM = 1'bx; + \$__ABC_REG rP (.Q(pP)); end if (MREG == 0 && PREG == 0) @@ -351,8 +350,8 @@ __CELL__ #( `DSP48E1_INST(\$__ABC_DSP48E1_MULT ) end else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin - // Disconnect the A-input if MREG is enabled, since - // combinatorial path is broken + // Disconnect the A-input if MREG is enabled, since + // combinatorial path is broken if (AREG == 0 && ADREG == 0 && MREG == 0 && PREG == 0) assign iA = A, pA = 1'bx; else @@ -369,19 +368,22 @@ __CELL__ #( assign iD = D, pD = 1'bx; else \$__ABC_REG #(.WIDTH(25)) rD (.I(D), .O(iD), .Q(pD)); - if (PREG == 0) begin - if (MREG == 1) - \$__ABC_REG rM (.Q(pM)); - else begin - assign pM = 1'bx; + if (PREG == 0) begin + if (MREG == 1) begin + assign pAD = 1'bx; + \$__ABC_REG rM (.Q(pM)); + end else begin if (ADREG == 1) \$__ABC_REG rAD (.Q(pAD)); else assign pAD = 1'bx; - end - end - else + assign pM = 1'bx; + end + assign pP = 1'bx; + end else begin + assign pAD = 1'bx, pM = 1'bx; \$__ABC_REG rP (.Q(pP)); + end if (MREG == 0 && PREG == 0) assign mP = oP, mPCOUT = oPCOUT; @@ -397,8 +399,8 @@ __CELL__ #( `DSP48E1_INST(\$__ABC_DSP48E1_MULT_DPORT ) end else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin - // Disconnect the A-input if MREG is enabled, since - // combinatorial path is broken + // Disconnect the A-input if MREG is enabled, since + // combinatorial path is broken if (AREG == 0 && PREG == 0) assign iA = A, pA = 1'bx; else @@ -411,16 +413,16 @@ __CELL__ #( assign iC = C, pC = 1'bx; else \$__ABC_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC)); - if (MREG == 1 && techmap_guard) - $error("Invalid DSP48E1 configuration: MREG enabled but USE_MULT == \"NONE\""); - assign pM = 1'bx; if (DREG == 1 && techmap_guard) - $error("Invalid DSP48E1 configuration: DREG enabled but USE_DPORT == \"FALSE\""); + $error("Invalid DSP48E1 configuration: DREG enabled but USE_DPORT == \"FALSE\""); assign pD = 1'bx; if (ADREG == 1 && techmap_guard) - $error("Invalid DSP48E1 configuration: ADREG enabled but USE_DPORT == \"FALSE\""); + $error("Invalid DSP48E1 configuration: ADREG enabled but USE_DPORT == \"FALSE\""); assign pAD = 1'bx; - if (PREG == 1) + if (MREG == 1 && techmap_guard) + $error("Invalid DSP48E1 configuration: MREG enabled but USE_MULT == \"NONE\""); + assign pM = 1'bx; + if (PREG == 1) \$__ABC_REG rP (.Q(pP)); else assign pP = 1'bx; @@ -440,6 +442,6 @@ __CELL__ #( end else $error("Invalid DSP48E1 configuration"); - endgenerate - `undef DSP48E1_INST + endgenerate + `undef DSP48E1_INST endmodule -- cgit v1.2.3 From e4f4f6a9d5cf8bb23870fc483f16f66c80ceebab Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 20 Sep 2019 08:41:40 -0700 Subject: Move mul2dsp before wreduce --- techlibs/ice40/synth_ice40.cc | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) (limited to 'techlibs') diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 284bc90d0..225603475 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -265,6 +265,10 @@ struct SynthIce40Pass : public ScriptPass run("opt_clean"); run("check"); run("opt"); + if (help_mode || dsp) + run("techmap -map +/mul2dsp.v -map +/ice40/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 " + "-D DSP_A_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 " + "-D DSP_NAME=$__MUL16X16", "(if -dsp)"); run("wreduce"); run("peepopt"); run("opt_clean"); @@ -273,11 +277,6 @@ struct SynthIce40Pass : public ScriptPass run("opt_expr"); run("opt_clean"); if (help_mode || dsp) { - run("techmap -map +/mul2dsp.v -map +/ice40/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 " - "-D DSP_A_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 " - "-D DSP_NAME=$__MUL16X16", "(if -dsp)"); - run("opt_expr -fine", " (if -dsp)"); - run("wreduce", " (if -dsp)"); run("ice40_dsp", " (if -dsp)"); run("chtype -set $mul t:$__soft_mul","(if -dsp)"); } -- cgit v1.2.3 From 829e4f5d2c8a521b5e4f80e85b9d58191d64f0d5 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 20 Sep 2019 08:56:16 -0700 Subject: Revert "Move mul2dsp before wreduce" This reverts commit e4f4f6a9d5cf8bb23870fc483f16f66c80ceebab. --- techlibs/ice40/synth_ice40.cc | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'techlibs') diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 225603475..284bc90d0 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -265,10 +265,6 @@ struct SynthIce40Pass : public ScriptPass run("opt_clean"); run("check"); run("opt"); - if (help_mode || dsp) - run("techmap -map +/mul2dsp.v -map +/ice40/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 " - "-D DSP_A_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 " - "-D DSP_NAME=$__MUL16X16", "(if -dsp)"); run("wreduce"); run("peepopt"); run("opt_clean"); @@ -277,6 +273,11 @@ struct SynthIce40Pass : public ScriptPass run("opt_expr"); run("opt_clean"); if (help_mode || dsp) { + run("techmap -map +/mul2dsp.v -map +/ice40/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 " + "-D DSP_A_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 " + "-D DSP_NAME=$__MUL16X16", "(if -dsp)"); + run("opt_expr -fine", " (if -dsp)"); + run("wreduce", " (if -dsp)"); run("ice40_dsp", " (if -dsp)"); run("chtype -set $mul t:$__soft_mul","(if -dsp)"); } -- cgit v1.2.3 From 289cf688b76328d62c7416d1327d2d6777b0ffd9 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 20 Sep 2019 09:02:29 -0700 Subject: Re-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine from synth_ice40 --- techlibs/ice40/synth_ice40.cc | 3 +-- techlibs/xilinx/synth_xilinx.cc | 2 +- 2 files changed, 2 insertions(+), 3 deletions(-) (limited to 'techlibs') diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 284bc90d0..7a8f3d70c 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -274,9 +274,8 @@ struct SynthIce40Pass : public ScriptPass run("opt_clean"); if (help_mode || dsp) { run("techmap -map +/mul2dsp.v -map +/ice40/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 " - "-D DSP_A_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 " + "-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 " "-D DSP_NAME=$__MUL16X16", "(if -dsp)"); - run("opt_expr -fine", " (if -dsp)"); run("wreduce", " (if -dsp)"); run("ice40_dsp", " (if -dsp)"); run("chtype -set $mul t:$__soft_mul","(if -dsp)"); diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 6687a0786..022b0d108 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -343,7 +343,7 @@ struct SynthXilinxPass : public ScriptPass if (!nodsp || help_mode) { // NB: Xilinx multipliers are signed only run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_A_MAXWIDTH_PARTIAL=18 -D DSP_B_MAXWIDTH=18 " - "-D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers + "-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers "-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller "-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18"); run("xilinx_dsp"); -- cgit v1.2.3 From ab46d9017b1a6fe6e376278ca9d3bec2e5673f06 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 20 Sep 2019 10:11:36 -0700 Subject: Fix signedness bug --- techlibs/common/mul2dsp.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'techlibs') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index f2b44222e..3ca69b7b1 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -239,9 +239,9 @@ module _80_mul (A, B, Y); ); //assign partial_sum[n] = (last_partial << n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[n-1]; if (A_SIGNED && B_SIGNED) - assign partial_sum[n][Y_WIDTH-1:n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)] = last_partial + partial_sum[n-1][Y_WIDTH-1:n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)]; - else assign partial_sum[n][Y_WIDTH-1:n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)] = last_partial + $signed(partial_sum[n-1][Y_WIDTH-1:n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)]); + else + assign partial_sum[n][Y_WIDTH-1:n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)] = last_partial + partial_sum[n-1][Y_WIDTH-1:n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)]; assign partial_sum[n][n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)-1:0] = partial_sum[n-1][n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)-1:0]; assign Y = partial_sum[n]; end -- cgit v1.2.3 From 4401e5f142d9728c09ac95e1cab9b30c449210fe Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 20 Sep 2019 14:24:31 -0700 Subject: Grammar --- techlibs/xilinx/abc_model.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc_model.v index 1c69dd21c..0a8d531d7 100644 --- a/techlibs/xilinx/abc_model.v +++ b/techlibs/xilinx/abc_model.v @@ -47,7 +47,7 @@ endmodule // Modules used to model the comb/seq behaviour of DSP48E1 // With abc_map.v responsible for splicing the below modules -// into between the combinatorial DSP48E1 box (e.g. disconnecting +// between the combinatorial DSP48E1 box (e.g. disconnecting // A when AREG, MREG or PREG is enabled and splicing in the // "$__ABC_DSP48E1_REG" blackbox as "REG" in the diagram below) // this acts to first disables the combinatorial path (as there -- cgit v1.2.3 From 23d90e0439ffef510632ce45a3d2aff1c129f405 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 23 Sep 2019 18:56:02 -0700 Subject: Add a xilinx_finalise pass --- techlibs/xilinx/Makefile.inc | 1 + techlibs/xilinx/synth_xilinx.cc | 2 + techlibs/xilinx/xilinx_finalise.cc | 84 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 87 insertions(+) create mode 100644 techlibs/xilinx/xilinx_finalise.cc (limited to 'techlibs') diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc index ae82311a9..10d783c3c 100644 --- a/techlibs/xilinx/Makefile.inc +++ b/techlibs/xilinx/Makefile.inc @@ -1,5 +1,6 @@ OBJS += techlibs/xilinx/synth_xilinx.o +OBJS += techlibs/xilinx/xilinx_finalise.o GENFILES += techlibs/xilinx/brams_init_36.vh GENFILES += techlibs/xilinx/brams_init_32.vh diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 022b0d108..c2f8279c2 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -512,6 +512,8 @@ struct SynthXilinxPass : public ScriptPass run("iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I A:top", "(only if '-iopad' or '-ise' and not '-noiopad')"); if (help_mode || ise) run("extractinv -inv INV O:I", "(only if '-ise')"); + if (help_mode || !nodsp) + run("xilinx_finalise", "(skip if '-nodsp')"); } if (check_label("check")) { diff --git a/techlibs/xilinx/xilinx_finalise.cc b/techlibs/xilinx/xilinx_finalise.cc new file mode 100644 index 000000000..db73babe3 --- /dev/null +++ b/techlibs/xilinx/xilinx_finalise.cc @@ -0,0 +1,84 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * (C) 2019 Eddie Hung + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/register.h" +#include "kernel/celltypes.h" +#include "kernel/rtlil.h" +#include "kernel/log.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +struct XilinxFinalisePass : public Pass +{ + XilinxFinalisePass() : Pass("xilinx_finalise", "") { } + + void help() YS_OVERRIDE + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" xilinx_finalise [options]\n"); + log("\n"); + } + + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + { + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) + { + break; + } + extra_args(args, argidx, design); + + log_header(design, "Executing XILINX_FINALISE pass.\n"); + + for (auto module : design->selected_modules()) + for (auto cell : module->selected_cells()) { + if (cell->type != ID(DSP48E1)) + continue; + for (auto &conn : cell->connections_) { + if (!cell->output(conn.first)) + continue; + bool purge = true; + for (auto &chunk : conn.second.chunks()) { + auto it = chunk.wire->attributes.find(ID(unused_bits)); + if (it == chunk.wire->attributes.end()) + continue; + + std::string unused_bits = stringf("%d", chunk.offset); + for (auto i = 1; i < chunk.width; i++) + unused_bits += stringf(" %d", i+chunk.offset); + + if (it->second.decode_string().find(unused_bits) == std::string::npos) { + purge = false; + break; + } + } + + if (purge) { + log_debug("Purging unused port connection %s %s (.%s(%s))\n", cell->type.c_str(), log_id(cell), log_id(conn.first), log_signal(conn.second)); + conn.second = SigSpec(); + } + } + } + } +} XilinxFinalisePass; + +PRIVATE_NAMESPACE_END -- cgit v1.2.3 From 67c2db3486a7b2ff34f89dc861fb66d51ba6101b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 23 Sep 2019 18:56:18 -0700 Subject: Remove (* techmap_autopurge *) from abc_unmap.v since no effect --- techlibs/xilinx/abc_unmap.v | 76 ++++++++++++++++++++++----------------------- 1 file changed, 38 insertions(+), 38 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc_unmap.v b/techlibs/xilinx/abc_unmap.v index ab007dfd2..630cf5f27 100644 --- a/techlibs/xilinx/abc_unmap.v +++ b/techlibs/xilinx/abc_unmap.v @@ -56,44 +56,44 @@ module \$__ABC_DSP48E1 ( output PATTERNDETECT, output [47:0] PCOUT, output UNDERFLOW, - (* techmap_autopurge *) input signed [29:0] A, - (* techmap_autopurge *) input [29:0] ACIN, - (* techmap_autopurge *) input [3:0] ALUMODE, - (* techmap_autopurge *) input signed [17:0] B, - (* techmap_autopurge *) input [17:0] BCIN, - (* techmap_autopurge *) input [47:0] C, - (* techmap_autopurge *) input CARRYCASCIN, - (* techmap_autopurge *) input CARRYIN, - (* techmap_autopurge *) input [2:0] CARRYINSEL, - (* techmap_autopurge *) input CEA1, - (* techmap_autopurge *) input CEA2, - (* techmap_autopurge *) input CEAD, - (* techmap_autopurge *) input CEALUMODE, - (* techmap_autopurge *) input CEB1, - (* techmap_autopurge *) input CEB2, - (* techmap_autopurge *) input CEC, - (* techmap_autopurge *) input CECARRYIN, - (* techmap_autopurge *) input CECTRL, - (* techmap_autopurge *) input CED, - (* techmap_autopurge *) input CEINMODE, - (* techmap_autopurge *) input CEM, - (* techmap_autopurge *) input CEP, - (* techmap_autopurge *) input CLK, - (* techmap_autopurge *) input [24:0] D, - (* techmap_autopurge *) input [4:0] INMODE, - (* techmap_autopurge *) input MULTSIGNIN, - (* techmap_autopurge *) input [6:0] OPMODE, - (* techmap_autopurge *) input [47:0] PCIN, - (* techmap_autopurge *) input RSTA, - (* techmap_autopurge *) input RSTALLCARRYIN, - (* techmap_autopurge *) input RSTALUMODE, - (* techmap_autopurge *) input RSTB, - (* techmap_autopurge *) input RSTC, - (* techmap_autopurge *) input RSTCTRL, - (* techmap_autopurge *) input RSTD, - (* techmap_autopurge *) input RSTINMODE, - (* techmap_autopurge *) input RSTM, - (* techmap_autopurge *) input RSTP + input signed [29:0] A, + input [29:0] ACIN, + input [3:0] ALUMODE, + input signed [17:0] B, + input [17:0] BCIN, + input [47:0] C, + input CARRYCASCIN, + input CARRYIN, + input [2:0] CARRYINSEL, + input CEA1, + input CEA2, + input CEAD, + input CEALUMODE, + input CEB1, + input CEB2, + input CEC, + input CECARRYIN, + input CECTRL, + input CED, + input CEINMODE, + input CEM, + input CEP, + input CLK, + input [24:0] D, + input [4:0] INMODE, + input MULTSIGNIN, + input [6:0] OPMODE, + input [47:0] PCIN, + input RSTA, + input RSTALLCARRYIN, + input RSTALUMODE, + input RSTB, + input RSTC, + input RSTCTRL, + input RSTD, + input RSTINMODE, + input RSTM, + input RSTP ); parameter integer ACASCREG = 1; parameter integer ADREG = 1; -- cgit v1.2.3 From 895e2befa76bd326cc47fd40de112ea067fcaf98 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 23 Sep 2019 19:04:07 -0700 Subject: Vivado does not like zero width port connections --- techlibs/xilinx/xilinx_finalise.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/xilinx_finalise.cc b/techlibs/xilinx/xilinx_finalise.cc index db73babe3..2c0bd3534 100644 --- a/techlibs/xilinx/xilinx_finalise.cc +++ b/techlibs/xilinx/xilinx_finalise.cc @@ -53,7 +53,7 @@ struct XilinxFinalisePass : public Pass for (auto cell : module->selected_cells()) { if (cell->type != ID(DSP48E1)) continue; - for (auto &conn : cell->connections_) { + for (auto conn : cell->connections()) { if (!cell->output(conn.first)) continue; bool purge = true; @@ -74,7 +74,7 @@ struct XilinxFinalisePass : public Pass if (purge) { log_debug("Purging unused port connection %s %s (.%s(%s))\n", cell->type.c_str(), log_id(cell), log_id(conn.first), log_signal(conn.second)); - conn.second = SigSpec(); + cell->unsetPort(conn.first); } } } -- cgit v1.2.3 From 29db96fa1ff89a8224f8ae3c51c754e16a34c31c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 23 Sep 2019 19:52:54 -0700 Subject: Revert "Vivado does not like zero width port connections" This reverts commit 895e2befa76bd326cc47fd40de112ea067fcaf98. --- techlibs/xilinx/xilinx_finalise.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/xilinx_finalise.cc b/techlibs/xilinx/xilinx_finalise.cc index 2c0bd3534..db73babe3 100644 --- a/techlibs/xilinx/xilinx_finalise.cc +++ b/techlibs/xilinx/xilinx_finalise.cc @@ -53,7 +53,7 @@ struct XilinxFinalisePass : public Pass for (auto cell : module->selected_cells()) { if (cell->type != ID(DSP48E1)) continue; - for (auto conn : cell->connections()) { + for (auto &conn : cell->connections_) { if (!cell->output(conn.first)) continue; bool purge = true; @@ -74,7 +74,7 @@ struct XilinxFinalisePass : public Pass if (purge) { log_debug("Purging unused port connection %s %s (.%s(%s))\n", cell->type.c_str(), log_id(cell), log_id(conn.first), log_signal(conn.second)); - cell->unsetPort(conn.first); + conn.second = SigSpec(); } } } -- cgit v1.2.3 From 0f53893104c84e799db12b6bbd3364af4f5ed338 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 23 Sep 2019 19:52:55 -0700 Subject: Revert "Remove (* techmap_autopurge *) from abc_unmap.v since no effect" This reverts commit 67c2db3486a7b2ff34f89dc861fb66d51ba6101b. --- techlibs/xilinx/abc_unmap.v | 76 ++++++++++++++++++++++----------------------- 1 file changed, 38 insertions(+), 38 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc_unmap.v b/techlibs/xilinx/abc_unmap.v index 630cf5f27..ab007dfd2 100644 --- a/techlibs/xilinx/abc_unmap.v +++ b/techlibs/xilinx/abc_unmap.v @@ -56,44 +56,44 @@ module \$__ABC_DSP48E1 ( output PATTERNDETECT, output [47:0] PCOUT, output UNDERFLOW, - input signed [29:0] A, - input [29:0] ACIN, - input [3:0] ALUMODE, - input signed [17:0] B, - input [17:0] BCIN, - input [47:0] C, - input CARRYCASCIN, - input CARRYIN, - input [2:0] CARRYINSEL, - input CEA1, - input CEA2, - input CEAD, - input CEALUMODE, - input CEB1, - input CEB2, - input CEC, - input CECARRYIN, - input CECTRL, - input CED, - input CEINMODE, - input CEM, - input CEP, - input CLK, - input [24:0] D, - input [4:0] INMODE, - input MULTSIGNIN, - input [6:0] OPMODE, - input [47:0] PCIN, - input RSTA, - input RSTALLCARRYIN, - input RSTALUMODE, - input RSTB, - input RSTC, - input RSTCTRL, - input RSTD, - input RSTINMODE, - input RSTM, - input RSTP + (* techmap_autopurge *) input signed [29:0] A, + (* techmap_autopurge *) input [29:0] ACIN, + (* techmap_autopurge *) input [3:0] ALUMODE, + (* techmap_autopurge *) input signed [17:0] B, + (* techmap_autopurge *) input [17:0] BCIN, + (* techmap_autopurge *) input [47:0] C, + (* techmap_autopurge *) input CARRYCASCIN, + (* techmap_autopurge *) input CARRYIN, + (* techmap_autopurge *) input [2:0] CARRYINSEL, + (* techmap_autopurge *) input CEA1, + (* techmap_autopurge *) input CEA2, + (* techmap_autopurge *) input CEAD, + (* techmap_autopurge *) input CEALUMODE, + (* techmap_autopurge *) input CEB1, + (* techmap_autopurge *) input CEB2, + (* techmap_autopurge *) input CEC, + (* techmap_autopurge *) input CECARRYIN, + (* techmap_autopurge *) input CECTRL, + (* techmap_autopurge *) input CED, + (* techmap_autopurge *) input CEINMODE, + (* techmap_autopurge *) input CEM, + (* techmap_autopurge *) input CEP, + (* techmap_autopurge *) input CLK, + (* techmap_autopurge *) input [24:0] D, + (* techmap_autopurge *) input [4:0] INMODE, + (* techmap_autopurge *) input MULTSIGNIN, + (* techmap_autopurge *) input [6:0] OPMODE, + (* techmap_autopurge *) input [47:0] PCIN, + (* techmap_autopurge *) input RSTA, + (* techmap_autopurge *) input RSTALLCARRYIN, + (* techmap_autopurge *) input RSTALUMODE, + (* techmap_autopurge *) input RSTB, + (* techmap_autopurge *) input RSTC, + (* techmap_autopurge *) input RSTCTRL, + (* techmap_autopurge *) input RSTD, + (* techmap_autopurge *) input RSTINMODE, + (* techmap_autopurge *) input RSTM, + (* techmap_autopurge *) input RSTP ); parameter integer ACASCREG = 1; parameter integer ADREG = 1; -- cgit v1.2.3 From 27167848f4c5709c6ca3cb0897bac91c4a2a7cbe Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 23 Sep 2019 19:52:55 -0700 Subject: Revert "Add a xilinx_finalise pass" This reverts commit 23d90e0439ffef510632ce45a3d2aff1c129f405. --- techlibs/xilinx/Makefile.inc | 1 - techlibs/xilinx/synth_xilinx.cc | 2 - techlibs/xilinx/xilinx_finalise.cc | 84 -------------------------------------- 3 files changed, 87 deletions(-) delete mode 100644 techlibs/xilinx/xilinx_finalise.cc (limited to 'techlibs') diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc index 10d783c3c..ae82311a9 100644 --- a/techlibs/xilinx/Makefile.inc +++ b/techlibs/xilinx/Makefile.inc @@ -1,6 +1,5 @@ OBJS += techlibs/xilinx/synth_xilinx.o -OBJS += techlibs/xilinx/xilinx_finalise.o GENFILES += techlibs/xilinx/brams_init_36.vh GENFILES += techlibs/xilinx/brams_init_32.vh diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index c2f8279c2..022b0d108 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -512,8 +512,6 @@ struct SynthXilinxPass : public ScriptPass run("iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I A:top", "(only if '-iopad' or '-ise' and not '-noiopad')"); if (help_mode || ise) run("extractinv -inv INV O:I", "(only if '-ise')"); - if (help_mode || !nodsp) - run("xilinx_finalise", "(skip if '-nodsp')"); } if (check_label("check")) { diff --git a/techlibs/xilinx/xilinx_finalise.cc b/techlibs/xilinx/xilinx_finalise.cc deleted file mode 100644 index db73babe3..000000000 --- a/techlibs/xilinx/xilinx_finalise.cc +++ /dev/null @@ -1,84 +0,0 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2012 Clifford Wolf - * (C) 2019 Eddie Hung - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -#include "kernel/register.h" -#include "kernel/celltypes.h" -#include "kernel/rtlil.h" -#include "kernel/log.h" - -USING_YOSYS_NAMESPACE -PRIVATE_NAMESPACE_BEGIN - -struct XilinxFinalisePass : public Pass -{ - XilinxFinalisePass() : Pass("xilinx_finalise", "") { } - - void help() YS_OVERRIDE - { - // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| - log("\n"); - log(" xilinx_finalise [options]\n"); - log("\n"); - } - - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE - { - size_t argidx; - for (argidx = 1; argidx < args.size(); argidx++) - { - break; - } - extra_args(args, argidx, design); - - log_header(design, "Executing XILINX_FINALISE pass.\n"); - - for (auto module : design->selected_modules()) - for (auto cell : module->selected_cells()) { - if (cell->type != ID(DSP48E1)) - continue; - for (auto &conn : cell->connections_) { - if (!cell->output(conn.first)) - continue; - bool purge = true; - for (auto &chunk : conn.second.chunks()) { - auto it = chunk.wire->attributes.find(ID(unused_bits)); - if (it == chunk.wire->attributes.end()) - continue; - - std::string unused_bits = stringf("%d", chunk.offset); - for (auto i = 1; i < chunk.width; i++) - unused_bits += stringf(" %d", i+chunk.offset); - - if (it->second.decode_string().find(unused_bits) == std::string::npos) { - purge = false; - break; - } - } - - if (purge) { - log_debug("Purging unused port connection %s %s (.%s(%s))\n", cell->type.c_str(), log_id(cell), log_id(conn.first), log_signal(conn.second)); - conn.second = SigSpec(); - } - } - } - } -} XilinxFinalisePass; - -PRIVATE_NAMESPACE_END -- cgit v1.2.3 From 11ac37733d436d5c0217fa6da029d620ec3da1b3 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 23 Sep 2019 21:56:28 -0700 Subject: Add techmap_autopurge to outputs in abc_map.v too --- techlibs/xilinx/abc_map.v | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v index 9d78725df..e4976092c 100644 --- a/techlibs/xilinx/abc_map.v +++ b/techlibs/xilinx/abc_map.v @@ -123,17 +123,17 @@ module SRLC32E ( endmodule module DSP48E1 ( - output [29:0] ACOUT, - output [17:0] BCOUT, - output reg CARRYCASCOUT, - output reg [3:0] CARRYOUT, - output reg MULTSIGNOUT, - output OVERFLOW, - output reg signed [47:0] P, - output PATTERNBDETECT, - output PATTERNDETECT, - output [47:0] PCOUT, - output UNDERFLOW, + (* techmap_autopurge *) output [29:0] ACOUT, + (* techmap_autopurge *) output [17:0] BCOUT, + (* techmap_autopurge *) output reg CARRYCASCOUT, + (* techmap_autopurge *) output reg [3:0] CARRYOUT, + (* techmap_autopurge *) output reg MULTSIGNOUT, + (* techmap_autopurge *) output OVERFLOW, + (* techmap_autopurge *) output reg signed [47:0] P, + (* techmap_autopurge *) output PATTERNBDETECT, + (* techmap_autopurge *) output PATTERNDETECT, + (* techmap_autopurge *) output [47:0] PCOUT, + (* techmap_autopurge *) output UNDERFLOW, (* techmap_autopurge *) input signed [29:0] A, (* techmap_autopurge *) input [29:0] ACIN, (* techmap_autopurge *) input [3:0] ALUMODE, -- cgit v1.2.3 From b41d2fb4e49a5ee8cda1906405f32614b39302bc Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 23 Sep 2019 22:02:22 -0700 Subject: Add (* techmap_autopurge *) to abc_unmap.v too --- techlibs/xilinx/abc_unmap.v | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc_unmap.v b/techlibs/xilinx/abc_unmap.v index ab007dfd2..8bd0579ed 100644 --- a/techlibs/xilinx/abc_unmap.v +++ b/techlibs/xilinx/abc_unmap.v @@ -45,17 +45,17 @@ endmodule (* techmap_celltype = "$__ABC_DSP48E1_MULT $__ABC_DSP48E1_MULT_DPORT $__ABC_DSP48E1" *) module \$__ABC_DSP48E1 ( - output [29:0] ACOUT, - output [17:0] BCOUT, - output reg CARRYCASCOUT, - output reg [3:0] CARRYOUT, - output reg MULTSIGNOUT, - output OVERFLOW, - output reg signed [47:0] P, - output PATTERNBDETECT, - output PATTERNDETECT, - output [47:0] PCOUT, - output UNDERFLOW, + (* techmap_autopurge *) output [29:0] ACOUT, + (* techmap_autopurge *) output [17:0] BCOUT, + (* techmap_autopurge *) output reg CARRYCASCOUT, + (* techmap_autopurge *) output reg [3:0] CARRYOUT, + (* techmap_autopurge *) output reg MULTSIGNOUT, + (* techmap_autopurge *) output OVERFLOW, + (* techmap_autopurge *) output reg signed [47:0] P, + (* techmap_autopurge *) output PATTERNBDETECT, + (* techmap_autopurge *) output PATTERNDETECT, + (* techmap_autopurge *) output [47:0] PCOUT, + (* techmap_autopurge *) output UNDERFLOW, (* techmap_autopurge *) input signed [29:0] A, (* techmap_autopurge *) input [29:0] ACIN, (* techmap_autopurge *) input [3:0] ALUMODE, -- cgit v1.2.3 From 93363c94a2e88e2cdbdb962ff9e10ba5dfe3f586 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 25 Sep 2019 10:33:16 -0700 Subject: Oops. Actually use __NAME__ in ABC_DSP48E1 macro --- techlibs/xilinx/abc_model.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc_model.v index 0a8d531d7..f19235a27 100644 --- a/techlibs/xilinx/abc_model.v +++ b/techlibs/xilinx/abc_model.v @@ -102,7 +102,7 @@ endmodule (* abc_box_id=2105 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_PCOUT_MUX ) `define ABC_DSP48E1(__NAME__) """ -module \$__ABC_DSP48E1_MULT ( +module __NAME__ ( output [29:0] ACOUT, output [17:0] BCOUT, output reg CARRYCASCOUT, -- cgit v1.2.3 From 53ea5daa42db335a69d3fccbf237fe5555f4bccb Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 25 Sep 2019 14:04:36 -0700 Subject: Call 'wreduce' after mul2dsp to avoid unextend() --- techlibs/xilinx/synth_xilinx.cc | 1 + 1 file changed, 1 insertion(+) (limited to 'techlibs') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 022b0d108..ca108e9d6 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -346,6 +346,7 @@ struct SynthXilinxPass : public ScriptPass "-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers "-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller "-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18"); + run("wreduce t:$add"); run("xilinx_dsp"); run("chtype -set $mul t:$__soft_mul"); } -- cgit v1.2.3 From 1d875ac76a354f654f28b9632d83f6b43542e827 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 25 Sep 2019 14:06:21 -0700 Subject: No need for $__mul anymore? --- techlibs/common/mul2dsp.v | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'techlibs') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 3ca69b7b1..25ff28ab5 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -49,7 +49,7 @@ $fatal(1, "Macro DSP_NAME must be defined"); `define MAX(a,b) (a > b ? a : b) `define MIN(a,b) (a < b ? a : b) -(* techmap_celltype = "$mul $__mul" *) +(* techmap_celltype = "$mul" *) module _80_mul (A, B, Y); parameter A_SIGNED = 0; parameter B_SIGNED = 0; @@ -132,9 +132,9 @@ module _80_mul (A, B, Y); end for (i = 0; i < n; i=i+1) begin:slice - \$__mul #( + \$mul #( .A_SIGNED(sign_headroom), - .B_SIGNED(B_SIGNED), + .B_SIGNED(sign_headroom), .A_WIDTH(`DSP_A_MAXWIDTH_PARTIAL), .B_WIDTH(B_WIDTH), .Y_WIDTH(partial_Y_WIDTH) @@ -161,7 +161,7 @@ module _80_mul (A, B, Y); end end - \$__mul #( + \$mul #( .A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(last_A_WIDTH), @@ -197,8 +197,8 @@ module _80_mul (A, B, Y); end for (i = 0; i < n; i=i+1) begin:slice - \$__mul #( - .A_SIGNED(A_SIGNED), + \$mul #( + .A_SIGNED(sign_headroom), .B_SIGNED(sign_headroom), .A_WIDTH(A_WIDTH), .B_WIDTH(`DSP_B_MAXWIDTH_PARTIAL), @@ -226,7 +226,7 @@ module _80_mul (A, B, Y); end end - \$__mul #( + \$mul #( .A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), @@ -271,7 +271,7 @@ module _80_mul (A, B, Y); endgenerate endmodule -(* techmap_celltype = "$mul $__mul" *) +(* techmap_celltype = "$mul" *) module _90_soft_mul (A, B, Y); parameter A_SIGNED = 0; parameter B_SIGNED = 0; -- cgit v1.2.3 From 234738b103d4f2b3d937ed928fd89bc4e31627f1 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 25 Sep 2019 16:51:31 -0700 Subject: Remove _TECHMAP_CELLTYPE_ check since all $mul --- techlibs/common/mul2dsp.v | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) (limited to 'techlibs') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 25ff28ab5..8c6a836f8 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -61,8 +61,6 @@ module _80_mul (A, B, Y); input [B_WIDTH-1:0] B; output [Y_WIDTH-1:0] Y; - parameter _TECHMAP_CELLTYPE_ = ""; - generate if (0) begin end `ifdef DSP_A_MINWIDTH @@ -77,10 +75,8 @@ module _80_mul (A, B, Y); else if (Y_WIDTH < `DSP_Y_MINWIDTH) wire _TECHMAP_FAIL_ = 1; `endif - else if (_TECHMAP_CELLTYPE_ == "$mul" && A_SIGNED != B_SIGNED) - wire _TECHMAP_FAIL_ = 1; `ifdef DSP_SIGNEDONLY - else if (_TECHMAP_CELLTYPE_ == "$mul" && !A_SIGNED) + else if (!A_SIGNED) \$mul #( .A_SIGNED(1), .B_SIGNED(1), @@ -93,7 +89,7 @@ module _80_mul (A, B, Y); .Y(Y) ); `endif - else if (_TECHMAP_CELLTYPE_ == "$mul" && A_WIDTH < B_WIDTH) + else if (A_WIDTH < B_WIDTH) \$mul #( .A_SIGNED(B_SIGNED), .B_SIGNED(A_SIGNED), -- cgit v1.2.3 From 63940913d21fcfb18cd844d7e5b9c8b41a82295b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 25 Sep 2019 17:22:04 -0700 Subject: Only wreduce on t:$add --- techlibs/ice40/synth_ice40.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 7a8f3d70c..98d3e44e3 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -276,7 +276,7 @@ struct SynthIce40Pass : public ScriptPass run("techmap -map +/mul2dsp.v -map +/ice40/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 " "-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 " "-D DSP_NAME=$__MUL16X16", "(if -dsp)"); - run("wreduce", " (if -dsp)"); + run("wreduce t:$add", " (if -dsp)"); run("ice40_dsp", " (if -dsp)"); run("chtype -set $mul t:$__soft_mul","(if -dsp)"); } -- cgit v1.2.3 From f4387e817c3f75a06c9c94f307fa60572ea06383 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 25 Sep 2019 17:24:11 -0700 Subject: Revert "No need for $__mul anymore?" This reverts commit 1d875ac76a354f654f28b9632d83f6b43542e827. --- techlibs/common/mul2dsp.v | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'techlibs') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 8c6a836f8..953fc28d1 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -49,7 +49,7 @@ $fatal(1, "Macro DSP_NAME must be defined"); `define MAX(a,b) (a > b ? a : b) `define MIN(a,b) (a < b ? a : b) -(* techmap_celltype = "$mul" *) +(* techmap_celltype = "$mul $__mul" *) module _80_mul (A, B, Y); parameter A_SIGNED = 0; parameter B_SIGNED = 0; @@ -128,9 +128,9 @@ module _80_mul (A, B, Y); end for (i = 0; i < n; i=i+1) begin:slice - \$mul #( + \$__mul #( .A_SIGNED(sign_headroom), - .B_SIGNED(sign_headroom), + .B_SIGNED(B_SIGNED), .A_WIDTH(`DSP_A_MAXWIDTH_PARTIAL), .B_WIDTH(B_WIDTH), .Y_WIDTH(partial_Y_WIDTH) @@ -157,7 +157,7 @@ module _80_mul (A, B, Y); end end - \$mul #( + \$__mul #( .A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(last_A_WIDTH), @@ -193,8 +193,8 @@ module _80_mul (A, B, Y); end for (i = 0; i < n; i=i+1) begin:slice - \$mul #( - .A_SIGNED(sign_headroom), + \$__mul #( + .A_SIGNED(A_SIGNED), .B_SIGNED(sign_headroom), .A_WIDTH(A_WIDTH), .B_WIDTH(`DSP_B_MAXWIDTH_PARTIAL), @@ -222,7 +222,7 @@ module _80_mul (A, B, Y); end end - \$mul #( + \$__mul #( .A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), @@ -267,7 +267,7 @@ module _80_mul (A, B, Y); endgenerate endmodule -(* techmap_celltype = "$mul" *) +(* techmap_celltype = "$mul $__mul" *) module _90_soft_mul (A, B, Y); parameter A_SIGNED = 0; parameter B_SIGNED = 0; -- cgit v1.2.3 From a4238637acc4e6670ccefb1894b00c602a827408 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 25 Sep 2019 17:25:44 -0700 Subject: Revert "Remove _TECHMAP_CELLTYPE_ check since all $mul" This reverts commit 234738b103d4f2b3d937ed928fd89bc4e31627f1. --- techlibs/common/mul2dsp.v | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'techlibs') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 953fc28d1..3ca69b7b1 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -61,6 +61,8 @@ module _80_mul (A, B, Y); input [B_WIDTH-1:0] B; output [Y_WIDTH-1:0] Y; + parameter _TECHMAP_CELLTYPE_ = ""; + generate if (0) begin end `ifdef DSP_A_MINWIDTH @@ -75,8 +77,10 @@ module _80_mul (A, B, Y); else if (Y_WIDTH < `DSP_Y_MINWIDTH) wire _TECHMAP_FAIL_ = 1; `endif + else if (_TECHMAP_CELLTYPE_ == "$mul" && A_SIGNED != B_SIGNED) + wire _TECHMAP_FAIL_ = 1; `ifdef DSP_SIGNEDONLY - else if (!A_SIGNED) + else if (_TECHMAP_CELLTYPE_ == "$mul" && !A_SIGNED) \$mul #( .A_SIGNED(1), .B_SIGNED(1), @@ -89,7 +93,7 @@ module _80_mul (A, B, Y); .Y(Y) ); `endif - else if (A_WIDTH < B_WIDTH) + else if (_TECHMAP_CELLTYPE_ == "$mul" && A_WIDTH < B_WIDTH) \$mul #( .A_SIGNED(B_SIGNED), .B_SIGNED(A_SIGNED), -- cgit v1.2.3 From 34aa3532fb1df2300da83df4071b46da69e3723c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 25 Sep 2019 17:26:47 -0700 Subject: Remove unnecessary check for A_SIGNED != B_SIGNED; be more explicit --- techlibs/common/mul2dsp.v | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'techlibs') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 3ca69b7b1..9932e288f 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -77,10 +77,8 @@ module _80_mul (A, B, Y); else if (Y_WIDTH < `DSP_Y_MINWIDTH) wire _TECHMAP_FAIL_ = 1; `endif - else if (_TECHMAP_CELLTYPE_ == "$mul" && A_SIGNED != B_SIGNED) - wire _TECHMAP_FAIL_ = 1; `ifdef DSP_SIGNEDONLY - else if (_TECHMAP_CELLTYPE_ == "$mul" && !A_SIGNED) + else if (_TECHMAP_CELLTYPE_ == "$mul" && !A_SIGNED && !B_SIGNED) \$mul #( .A_SIGNED(1), .B_SIGNED(1), -- cgit v1.2.3 From 35aaa8d73a75f36a42eea9ef2b210d9e79e5edc3 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 25 Sep 2019 22:58:55 -0700 Subject: mul2dsp.v slice names --- techlibs/common/mul2dsp.v | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'techlibs') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 9932e288f..60b180ac0 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -129,14 +129,14 @@ module _80_mul (A, B, Y); wire [Y_WIDTH-1:0] partial_sum [n:0]; end - for (i = 0; i < n; i=i+1) begin:slice + for (i = 0; i < n; i=i+1) begin:sliceA \$__mul #( .A_SIGNED(sign_headroom), .B_SIGNED(B_SIGNED), .A_WIDTH(`DSP_A_MAXWIDTH_PARTIAL), .B_WIDTH(B_WIDTH), .Y_WIDTH(partial_Y_WIDTH) - ) mul_slice ( + ) mul ( .A({{sign_headroom{1'b0}}, A[i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom) +: `DSP_A_MAXWIDTH_PARTIAL-sign_headroom]}), .B(B), .Y(partial[i]) @@ -165,7 +165,7 @@ module _80_mul (A, B, Y); .A_WIDTH(last_A_WIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(last_Y_WIDTH) - ) mul_slice_last ( + ) sliceA.last ( .A(A[A_WIDTH-1 -: last_A_WIDTH]), .B(B), .Y(last_partial) @@ -194,7 +194,7 @@ module _80_mul (A, B, Y); wire [Y_WIDTH-1:0] partial_sum [n:0]; end - for (i = 0; i < n; i=i+1) begin:slice + for (i = 0; i < n; i=i+1) begin:sliceB \$__mul #( .A_SIGNED(A_SIGNED), .B_SIGNED(sign_headroom), @@ -230,7 +230,7 @@ module _80_mul (A, B, Y); .A_WIDTH(A_WIDTH), .B_WIDTH(last_B_WIDTH), .Y_WIDTH(last_Y_WIDTH) - ) mul_last ( + ) mul_sliceB_last ( .A(A), .B(B[B_WIDTH-1 -: last_B_WIDTH]), .Y(last_partial) -- cgit v1.2.3 From 27e5bf5aad229ef330bfea932f6b194ec5c09b68 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 26 Sep 2019 09:57:11 -0700 Subject: Stop trying to be too smart by prematurely optimising --- techlibs/common/mul2dsp.v | 40 ++++++---------------------------------- techlibs/ice40/synth_ice40.cc | 8 +++++--- techlibs/xilinx/synth_xilinx.cc | 4 +++- 3 files changed, 14 insertions(+), 38 deletions(-) (limited to 'techlibs') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 60b180ac0..6dcdcf226 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -146,17 +146,8 @@ module _80_mul (A, B, Y); // reduction' approach also exists... if (i == 0) assign partial_sum[i] = partial[i]; - else begin - // Rewrite the following statement explicitly in order - // to save on a call to 'opt_expr -fine' which would - // optimise away the '<<' op and trim size of adder - //assign partial_sum[i] = (partial[i] << i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[i-1]; - if (A_SIGNED && B_SIGNED) - assign partial_sum[i][Y_WIDTH-1:i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)] = partial[i] + $signed(partial_sum[i-1][Y_WIDTH-1:i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)]); - else - assign partial_sum[i][Y_WIDTH-1:i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)] = partial[i] + partial_sum[i-1][Y_WIDTH-1:i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)]; - assign partial_sum[i][i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)-1:0] = partial_sum[i-1][i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)-1:0]; - end + else + assign partial_sum[i] = (partial[i] << (* mul2dsp *) i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) partial_sum[i-1]; end \$__mul #( @@ -170,12 +161,7 @@ module _80_mul (A, B, Y); .B(B), .Y(last_partial) ); - //assign partial_sum[n] = (last_partial << n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[n-1]; - if (A_SIGNED && B_SIGNED) - assign partial_sum[n][Y_WIDTH-1:n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)] = last_partial + $signed(partial_sum[n-1][Y_WIDTH-1:n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)]); - else - assign partial_sum[n][Y_WIDTH-1:n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)] = last_partial + partial_sum[n-1][Y_WIDTH-1:n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)]; - assign partial_sum[n][n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)-1:0] = partial_sum[n-1][n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)-1:0]; + assign partial_sum[n] = (last_partial << (* mul2dsp *) n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) partial_sum[n-1]; assign Y = partial_sum[n]; end else if (B_WIDTH > `DSP_B_MAXWIDTH) begin @@ -211,17 +197,8 @@ module _80_mul (A, B, Y); // reduction' approach also exists... if (i == 0) assign partial_sum[i] = partial[i]; - else begin - // Rewrite the following statement explicitly in order - // to save on a call to 'opt_expr -fine' which would - // optimise away the '<<' op and trim size of adder - //assign partial_sum[i] = (partial[i] << i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[i-1]; - if (A_SIGNED && B_SIGNED) - assign partial_sum[i][Y_WIDTH-1:i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)] = partial[i] + $signed(partial_sum[i-1][Y_WIDTH-1:i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)]); - else - assign partial_sum[i][Y_WIDTH-1:i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)] = partial[i] + partial_sum[i-1][Y_WIDTH-1:i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)]; - assign partial_sum[i][i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)-1:0] = partial_sum[i-1][i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)-1:0]; - end + else + assign partial_sum[i] = (partial[i] << i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[i-1]; end \$__mul #( @@ -235,12 +212,7 @@ module _80_mul (A, B, Y); .B(B[B_WIDTH-1 -: last_B_WIDTH]), .Y(last_partial) ); - //assign partial_sum[n] = (last_partial << n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[n-1]; - if (A_SIGNED && B_SIGNED) - assign partial_sum[n][Y_WIDTH-1:n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)] = last_partial + $signed(partial_sum[n-1][Y_WIDTH-1:n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)]); - else - assign partial_sum[n][Y_WIDTH-1:n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)] = last_partial + partial_sum[n-1][Y_WIDTH-1:n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)]; - assign partial_sum[n][n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)-1:0] = partial_sum[n-1][n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)-1:0]; + assign partial_sum[n] = (last_partial << n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[n-1]; assign Y = partial_sum[n]; end else begin diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 98d3e44e3..694782e5b 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -276,9 +276,11 @@ struct SynthIce40Pass : public ScriptPass run("techmap -map +/mul2dsp.v -map +/ice40/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 " "-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 " "-D DSP_NAME=$__MUL16X16", "(if -dsp)"); - run("wreduce t:$add", " (if -dsp)"); - run("ice40_dsp", " (if -dsp)"); - run("chtype -set $mul t:$__soft_mul","(if -dsp)"); + run("opt_expr -fine a:mul2dsp", " (if -dsp)"); + run("wreduce a:mul2dsp", " (if -dsp)"); + run("ice40_dsp", " (if -dsp)"); + run("setattr -unset mul2dsp a:mul2dsp", "(if -dsp)"); + run("chtype -set $mul t:$__soft_mul", " (if -dsp)"); } run("alumacc"); run("opt"); diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index ca108e9d6..b87fa9f6f 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -346,7 +346,9 @@ struct SynthXilinxPass : public ScriptPass "-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers "-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller "-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18"); - run("wreduce t:$add"); + run("opt_expr -fine a:mul2dsp"); + run("wreduce a:mul2dsp"); + run("setattr -unset mul2dsp a:mul2dsp"); run("xilinx_dsp"); run("chtype -set $mul t:$__soft_mul"); } -- cgit v1.2.3 From 781dda6175c86fcb2b08d055565d3d99a687e636 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 26 Sep 2019 10:15:05 -0700 Subject: select once --- techlibs/ice40/synth_ice40.cc | 12 +++++++----- techlibs/xilinx/synth_xilinx.cc | 8 +++++--- 2 files changed, 12 insertions(+), 8 deletions(-) (limited to 'techlibs') diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 694782e5b..52e13bdc2 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -276,11 +276,13 @@ struct SynthIce40Pass : public ScriptPass run("techmap -map +/mul2dsp.v -map +/ice40/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 " "-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 " "-D DSP_NAME=$__MUL16X16", "(if -dsp)"); - run("opt_expr -fine a:mul2dsp", " (if -dsp)"); - run("wreduce a:mul2dsp", " (if -dsp)"); - run("ice40_dsp", " (if -dsp)"); - run("setattr -unset mul2dsp a:mul2dsp", "(if -dsp)"); - run("chtype -set $mul t:$__soft_mul", " (if -dsp)"); + run("select a:mul2dsp", " (if -dsp)"); + run("opt_expr -fine", " (if -dsp)"); + run("wreduce", " (if -dsp)"); + run("setattr -unset mul2dsp", " (if -dsp)"); + run("select -clear", " (if -dsp)"); + run("ice40_dsp", " (if -dsp)"); + run("chtype -set $mul t:$__soft_mul", "(if -dsp)"); } run("alumacc"); run("opt"); diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index b87fa9f6f..0445eb720 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -346,9 +346,11 @@ struct SynthXilinxPass : public ScriptPass "-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers "-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller "-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18"); - run("opt_expr -fine a:mul2dsp"); - run("wreduce a:mul2dsp"); - run("setattr -unset mul2dsp a:mul2dsp"); + run("select a:mul2dsp"); + run("opt_expr -fine"): + run("wreduce"); + run("setattr -unset mul2dsp"); + run("select -clear"); run("xilinx_dsp"); run("chtype -set $mul t:$__soft_mul"); } -- cgit v1.2.3 From 033aefc0f44abdca50e34cad884c81875dcd7441 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 26 Sep 2019 10:34:14 -0700 Subject: Typo --- techlibs/xilinx/synth_xilinx.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 0445eb720..d73cc3b16 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -347,7 +347,7 @@ struct SynthXilinxPass : public ScriptPass "-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller "-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18"); run("select a:mul2dsp"); - run("opt_expr -fine"): + run("opt_expr -fine"); run("wreduce"); run("setattr -unset mul2dsp"); run("select -clear"); -- cgit v1.2.3 From 84825f937827f3e8fd3702a7ea85b8997ac74534 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 26 Sep 2019 10:45:14 -0700 Subject: Combine 'flatten' & 'coarse' labels in synth_ecp5 so proc run once --- techlibs/ecp5/synth_ecp5.cc | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) (limited to 'techlibs') diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index 0a3dcc62c..1f5b1cb6b 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -226,16 +226,13 @@ struct SynthEcp5Pass : public ScriptPass run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt.c_str())); } - if (flatten && check_label("flatten", "(unless -noflatten)")) + if (check_label("coarse")) { run("proc"); - run("flatten"); + if (flatten || help_mode) + run("flatten"); run("tribuf -logic"); run("deminout"); - } - - if (check_label("coarse")) - { run("opt_expr"); run("opt_clean"); run("check"); @@ -248,9 +245,7 @@ struct SynthEcp5Pass : public ScriptPass run("opt_expr"); run("opt_clean"); if (!nodsp) { - run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=$__MUL18X18", "(unless -nodsp)"); - run("clean", "(unless -nodsp)"); - run("techmap -map +/ecp5/dsp_map.v", "(unless -nodsp)"); + run("techmap -map +/mul2dsp.v -map +/ecp5/dsp_map.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=$__MUL18X18", "(unless -nodsp)"); run("chtype -set $mul t:$__soft_mul", "(unless -nodsp)"); } run("alumacc"); -- cgit v1.2.3 From 90236025b7e1409027550451abe4ffc1cc63f128 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 27 Sep 2019 14:21:47 -0700 Subject: Missing (* mul2dsp *) for sliceB --- techlibs/common/mul2dsp.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'techlibs') diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 6dcdcf226..4cabb4453 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -198,7 +198,7 @@ module _80_mul (A, B, Y); if (i == 0) assign partial_sum[i] = partial[i]; else - assign partial_sum[i] = (partial[i] << i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[i-1]; + assign partial_sum[i] = (partial[i] << (* mul2dsp *) i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) partial_sum[i-1]; end \$__mul #( @@ -212,7 +212,7 @@ module _80_mul (A, B, Y); .B(B[B_WIDTH-1 -: last_B_WIDTH]), .Y(last_partial) ); - assign partial_sum[n] = (last_partial << n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + partial_sum[n-1]; + assign partial_sum[n] = (last_partial << (* mul2dsp *) n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) partial_sum[n-1]; assign Y = partial_sum[n]; end else begin -- cgit v1.2.3 From b3d8a60cbd94176076f23c4ea6c94ec24e6773e0 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 27 Sep 2019 14:32:07 -0700 Subject: Re-order --- techlibs/ice40/synth_ice40.cc | 2 +- techlibs/xilinx/synth_xilinx.cc | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'techlibs') diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 52e13bdc2..841f10244 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -277,9 +277,9 @@ struct SynthIce40Pass : public ScriptPass "-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 " "-D DSP_NAME=$__MUL16X16", "(if -dsp)"); run("select a:mul2dsp", " (if -dsp)"); + run("setattr -unset mul2dsp", " (if -dsp)"); run("opt_expr -fine", " (if -dsp)"); run("wreduce", " (if -dsp)"); - run("setattr -unset mul2dsp", " (if -dsp)"); run("select -clear", " (if -dsp)"); run("ice40_dsp", " (if -dsp)"); run("chtype -set $mul t:$__soft_mul", "(if -dsp)"); diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index d73cc3b16..6c58e0913 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -347,9 +347,9 @@ struct SynthXilinxPass : public ScriptPass "-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller "-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18"); run("select a:mul2dsp"); + run("setattr -unset mul2dsp"); run("opt_expr -fine"); run("wreduce"); - run("setattr -unset mul2dsp"); run("select -clear"); run("xilinx_dsp"); run("chtype -set $mul t:$__soft_mul"); -- cgit v1.2.3