From f1a206ba03c5b6fba2672754d09cc649a60beeb8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 20 Aug 2019 18:17:14 -0700
Subject: Revert "Remove sequential extension"

This reverts commit 091bf4a18b2f4bf84fe62b61577c88d961468b3c.
---
 techlibs/xilinx/abc_map.v       |  97 ++++++++++++++++++++++++++++++++
 techlibs/xilinx/abc_model.v     |  89 ++++++++++++++++++++++++++++++
 techlibs/xilinx/abc_unmap.v     | 119 ++++++++++++++++++++++++++++++++++++++++
 techlibs/xilinx/abc_xc7.box     |  41 ++++++++++++++
 techlibs/xilinx/cells_sim.v     |  24 +++-----
 techlibs/xilinx/synth_xilinx.cc |   6 +-
 6 files changed, 359 insertions(+), 17 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v
index 121862692..a760b3d6d 100644
--- a/techlibs/xilinx/abc_map.v
+++ b/techlibs/xilinx/abc_map.v
@@ -20,6 +20,103 @@
 
 // ============================================================================
 
+module FDRE (output reg Q, input C, CE, D, R);
+  parameter [0:0] INIT = 1'b0;
+  parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  parameter [0:0] IS_R_INVERTED = 1'b0;
+  wire \$nextQ ;
+  \$__ABC_FDRE #(
+    .INIT(INIT),
+    .IS_C_INVERTED(IS_C_INVERTED),
+    .IS_D_INVERTED(IS_D_INVERTED),
+    .IS_R_INVERTED(IS_R_INVERTED),
+    .CLK_POLARITY(!IS_C_INVERTED),
+    .EN_POLARITY(1'b1)
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .R(R)
+  );
+  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
+endmodule
+module FDRE_1 (output reg Q, input C, CE, D, R);
+  parameter [0:0] INIT = 1'b0;
+  wire \$nextQ ;
+  \$__ABC_FDRE_1 #(
+      .INIT(|0),
+    .CLK_POLARITY(1'b0),
+    .EN_POLARITY(1'b1)
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .R(R)
+  );
+  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
+endmodule
+
+module FDCE (output reg Q, input C, CE, D, CLR);
+  parameter [0:0] INIT = 1'b0;
+  parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  parameter [0:0] IS_CLR_INVERTED = 1'b0;
+  wire \$nextQ , \$currQ ;
+  \$__ABC_FDCE #(
+    .INIT(INIT),
+    .IS_C_INVERTED(IS_C_INVERTED),
+    .IS_D_INVERTED(IS_D_INVERTED),
+    .IS_CLR_INVERTED(IS_CLR_INVERTED),
+    .CLK_POLARITY(!IS_C_INVERTED),
+    .EN_POLARITY(1'b1)
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR)
+  );
+  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
+  \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(CLR), .Y(Q));
+endmodule
+module FDCE_1 (output reg Q, input C, CE, D, CLR);
+  parameter [0:0] INIT = 1'b0;
+  wire \$nextQ , \$currQ ;
+  \$__ABC_FDCE_1 #(
+    .INIT(INIT),
+    .CLK_POLARITY(1'b0),
+    .EN_POLARITY(1'b1)
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR)
+  );
+  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
+  \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(CLR), .Y(Q));
+endmodule
+
+module FDPE (output reg Q, input C, CE, D, PRE);
+  parameter [0:0] INIT = 1'b0;
+  parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  parameter [0:0] IS_PRE_INVERTED = 1'b0;
+  wire \$nextQ , \$currQ ;
+  \$__ABC_FDPE #(
+    .INIT(INIT),
+    .IS_C_INVERTED(IS_C_INVERTED),
+    .IS_D_INVERTED(IS_D_INVERTED),
+    .IS_PRE_INVERTED(IS_PRE_INVERTED),
+    .CLK_POLARITY(!IS_C_INVERTED),
+    .EN_POLARITY(1'b1)
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE)
+  );
+  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
+  \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(PRE), .Y(Q));
+endmodule
+module FDPE_1 (output reg Q, input C, CE, D, PRE);
+  parameter [0:0] INIT = 1'b0;
+  wire \$nextQ , \$currQ ;
+  \$__ABC_FDPE_1 #(
+    .INIT(INIT),
+    .CLK_POLARITY(1'b0),
+    .EN_POLARITY(1'b1)
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE)
+  );
+  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
+  \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(PRE), .Y(Q));
+endmodule
+
 module RAM32X1D (
   output DPO, SPO,
   input  D,
diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc_model.v
index e3e9686b5..7162bd213 100644
--- a/techlibs/xilinx/abc_model.v
+++ b/techlibs/xilinx/abc_model.v
@@ -26,6 +26,94 @@ module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
                 : (S0 ? I1 : I0);
 endmodule
 
+module \$__ABC_FF_ (input C, D, output Q);
+endmodule
+
+(* abc_box_id = 1000 *)
+module \$__ABC_ASYNC (input A, S, output Y);
+endmodule
+
+(* abc_box_id=1001, lib_whitebox, abc_flop *)
+module \$__ABC_FDRE ((* abc_flop_q, abc_arrival=303 *) output Q,
+                     (* abc_flop_clk *) input C,
+                     (* abc_flop_en *)  input CE,
+                     (* abc_flop_d *)   input D,
+                     input R, \$pastQ );
+  parameter [0:0] INIT = 1'b0;
+  parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  parameter [0:0] IS_R_INVERTED = 1'b0;
+  parameter CLK_POLARITY = !IS_C_INVERTED;
+  parameter EN_POLARITY = 1'b1;
+  assign Q = (R ^ IS_R_INVERTED) ? 1'b0 : (CE ? (D ^ IS_D_INVERTED) : \$pastQ );
+endmodule
+
+(* abc_box_id=1002, lib_whitebox, abc_flop *)
+module \$__ABC_FDRE_1 ((* abc_flop_q, abc_arrival=303 *) output Q,
+                       (* abc_flop_clk *) input C,
+                       (* abc_flop_en *)  input CE,
+                       (* abc_flop_d *)   input D,
+                       input R, \$pastQ );
+  parameter [0:0] INIT = 1'b0;
+  parameter CLK_POLARITY = 1'b0;
+  parameter EN_POLARITY = 1'b1;
+  assign Q = R ? 1'b0 : (CE ? D : \$pastQ );
+endmodule
+
+(* abc_box_id=1003, lib_whitebox, abc_flop *)
+module \$__ABC_FDCE ((* abc_flop_q, abc_arrival=303 *) output Q,
+                     (* abc_flop_clk *) input C,
+                     (* abc_flop_en *)  input CE,
+                     (* abc_flop_d *)   input D,
+                     input CLR, \$pastQ );
+  parameter [0:0] INIT = 1'b0;
+  parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  parameter [0:0] IS_CLR_INVERTED = 1'b0;
+  parameter CLK_POLARITY = !IS_C_INVERTED;
+  parameter EN_POLARITY = 1'b1;
+  assign Q = (CE && !(CLR ^ IS_CLR_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
+endmodule
+
+(* abc_box_id=1004, lib_whitebox, abc_flop *)
+module \$__ABC_FDCE_1 ((* abc_flop_q, abc_arrival=303 *) output Q,
+                       (* abc_flop_clk *) input C,
+                       (* abc_flop_en *)  input CE,
+                       (* abc_flop_d *)   input D,
+                       input CLR, \$pastQ );
+  parameter [0:0] INIT = 1'b0;
+  parameter CLK_POLARITY = 1'b0;
+  parameter EN_POLARITY = 1'b1;
+  assign Q = (CE && !CLR) ? D : \$pastQ ;
+endmodule
+
+(* abc_box_id=1005, lib_whitebox, abc_flop *)
+module \$__ABC_FDPE ((* abc_flop_q, abc_arrival=303 *) output Q,
+                     (* abc_flop_clk *) input C,
+                     (* abc_flop_en *)  input CE,
+                     (* abc_flop_d *)   input D,
+                     input PRE, \$pastQ );
+  parameter [0:0] INIT = 1'b0;
+  parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  parameter [0:0] IS_PRE_INVERTED = 1'b0;
+  parameter CLK_POLARITY = !IS_C_INVERTED;
+  parameter EN_POLARITY = 1'b1;
+  assign Q = (CE && !(PRE ^ IS_PRE_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
+endmodule
+
+(* abc_box_id=1006, lib_whitebox, abc_flop *)
+module \$__ABC_FDPE_1 ((* abc_flop_q, abc_arrival=303 *) output Q,
+                       (* abc_flop_clk *) input C,
+                       (* abc_flop_en *)  input CE,
+                       (* abc_flop_d *)   input D,
+                       input PRE, \$pastQ );
+  parameter [0:0] INIT = 1'b0; 
+  parameter CLK_POLARITY = 1'b0;
+  parameter EN_POLARITY = 1'b1;
+  assign Q = (CE && !PRE) ? D : \$pastQ ;
+endmodule
+
 (* abc_box_id=2000 *)
 module \$__ABC_LUTMUX6 (input A, input [5:0] S, output Y);
 endmodule
@@ -33,6 +121,7 @@ endmodule
 module \$__ABC_LUTMUX7 (input A, input [6:0] S, output Y);
 endmodule
 
+
 module \$__ABC_RAM32X1D (
   // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
   (* abc_arrival=1153 *) output DPO, SPO,
diff --git a/techlibs/xilinx/abc_unmap.v b/techlibs/xilinx/abc_unmap.v
index 779fc5aac..d00d27e2e 100644
--- a/techlibs/xilinx/abc_unmap.v
+++ b/techlibs/xilinx/abc_unmap.v
@@ -20,6 +20,125 @@
 
 // ============================================================================
 
+module \$__ABC_ASYNC (input A, S, output Y);
+  assign Y = A;
+endmodule
+
+module \$__ABC_FDRE (output Q,
+                     input C,
+                     input CE,
+                     input D,
+                     input R, \$pastQ );
+  parameter [0:0] INIT = 1'b0;
+  parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  parameter [0:0] IS_R_INVERTED = 1'b0;
+  parameter CLK_POLARITY = !IS_C_INVERTED;
+  parameter EN_POLARITY = 1'b1;
+
+  FDRE #(
+    .INIT(INIT),
+    .IS_C_INVERTED(IS_C_INVERTED),
+    .IS_D_INVERTED(IS_D_INVERTED),
+    .IS_R_INVERTED(IS_R_INVERTED),
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(Q), .C(C), .CE(CE), .R(R)
+  );
+endmodule
+
+module \$__ABC_FDRE_1 (output Q,
+                       input C,
+                       input CE,
+                       input D,
+                       input R, \$pastQ );
+  parameter [0:0] INIT = 1'b0;
+  parameter CLK_POLARITY = 1'b0;
+  parameter EN_POLARITY = 1'b1;
+  assign Q = R ? 1'b0 : (CE ? D : \$pastQ );
+
+  FDRE_1 #(
+    .INIT(INIT),
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(Q), .C(C), .CE(CE), .R(R)
+  );
+endmodule
+
+module \$__ABC_FDCE (output Q,
+                     input C,
+                     input CE,
+                     input D,
+                     input CLR, \$pastQ );
+  parameter [0:0] INIT = 1'b0;
+  parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  parameter [0:0] IS_CLR_INVERTED = 1'b0;
+  parameter CLK_POLARITY = !IS_C_INVERTED;
+  parameter EN_POLARITY = 1'b1;
+
+  FDCE #(
+    .INIT(INIT),
+    .IS_C_INVERTED(IS_C_INVERTED),
+    .IS_D_INVERTED(IS_D_INVERTED),
+    .IS_CLR_INVERTED(IS_CLR_INVERTED),
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(Q), .C(C), .CE(CE), .CLR(CLR)
+  );
+endmodule
+
+module \$__ABC_FDCE_1 (output Q,
+                       input C,
+                       input CE,
+                       input D,
+                       input CLR, \$pastQ );
+  parameter [0:0] INIT = 1'b0;
+  parameter CLK_POLARITY = 1'b0;
+  parameter EN_POLARITY = 1'b1;
+
+  FDCE_1 #(
+    .INIT(INIT),
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(Q), .C(C), .CE(CE), .CLR(CLR)
+  );
+endmodule
+
+module \$__ABC_FDPE (output Q,
+                     input C,
+                     input CE,
+                     input D,
+                     input PRE, \$pastQ );
+  parameter [0:0] INIT = 1'b0;
+  parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  parameter [0:0] IS_PRE_INVERTED = 1'b0;
+  parameter CLK_POLARITY = !IS_C_INVERTED;
+  parameter EN_POLARITY = 1'b1;
+
+  FDPE #(
+    .INIT(INIT),
+    .IS_C_INVERTED(IS_C_INVERTED),
+    .IS_D_INVERTED(IS_D_INVERTED),
+    .IS_PRE_INVERTED(IS_PRE_INVERTED),
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(Q), .C(C), .CE(CE), .PRE(PRE)
+  );
+endmodule
+
+module \$__ABC_FDPE_1 (output Q,
+                       input C,
+                       input CE,
+                       input D,
+                       input PRE, \$pastQ );
+  parameter [0:0] INIT = 1'b0;
+  parameter CLK_POLARITY = 1'b0;
+  parameter EN_POLARITY = 1'b1;
+
+  FDPE_1 #(
+    .INIT(INIT),
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(Q), .C(C), .CE(CE), .PRE(PRE)
+  );
+endmodule
+
 module \$__ABC_LUTMUX6 (input A, input [5:0] S, output Y);
   assign Y = A;
 endmodule
diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
index 61b89b8af..c08af6320 100644
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@ -38,6 +38,47 @@ CARRY4 4 1 10 8
 592 540 520 356 -   512 548 292 -   228
 580 526 507 398 385 508 528 378 380 114
 
+# Box to emulate async behaviour of FD[CP]*
+# Inputs: A S
+# Outputs: Y
+$__ABC_ASYNC 1000 0 2 1
+0 764
+
+# The following FD*.{CE,R,CLR,PRE) are offset by 46ps to
+# reflect the -46ps Tsu
+# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L237-L251
+# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L265-L277
+
+# Inputs: C CE D R \$pastQ
+# Outputs: Q
+FDRE 1001 1 5 1
+0 151 0 446 0
+
+# Inputs: C CE D R \$pastQ
+# Outputs: Q
+FDRE_1 1002 1 5 1
+0 151 0 446 0
+
+# Inputs: C CE CLR D \$pastQ
+# Outputs: Q
+FDCE 1003 1 5 1
+0 151 806 0 0
+
+# Inputs: C CE CLR D \$pastQ
+# Outputs: Q
+FDCE_1 1004 1 5 1
+0 151 806 0 0
+
+# Inputs: C CE D PRE \$pastQ
+# Outputs: Q
+FDPE 1005 1 5 1
+0 151 0 806 0
+
+# Inputs: C CE D PRE \$pastQ
+# Outputs: Q
+FDPE_1 1006 1 5 1
+0 151 0 806 0
+
 # SLICEM/A6LUT
 # Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32}
 # Inputs: A S0 S1 S2 S3 S4 S5
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index d879a56ee..1ab718ccc 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -211,8 +211,7 @@ endmodule
 
 `endif
 
-module FDRE ((* abc_arrival=303 *) output reg Q,
-             input C, CE, D, R);
+module FDRE (output reg Q, input C, CE, D, R);
   parameter [0:0] INIT = 1'b0;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -224,8 +223,7 @@ module FDRE ((* abc_arrival=303 *) output reg Q,
   endcase endgenerate
 endmodule
 
-module FDSE ((* abc_arrival=303 *) output reg Q,
-             input C, CE, D, S);
+module FDSE (output reg Q, input C, CE, D, S);
   parameter [0:0] INIT = 1'b1;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -237,8 +235,7 @@ module FDSE ((* abc_arrival=303 *) output reg Q,
   endcase endgenerate
 endmodule
 
-module FDCE ((* abc_arrival=303 *) output reg Q,
-             input C, CE, D, CLR);
+module FDCE (output reg Q, input C, CE, D, CLR);
   parameter [0:0] INIT = 1'b0;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -252,8 +249,7 @@ module FDCE ((* abc_arrival=303 *) output reg Q,
   endcase endgenerate
 endmodule
 
-module FDPE ((* abc_arrival=303 *) output reg Q,
-             input C, CE, D, PRE);
+module FDPE (output reg Q, input C, CE, D, PRE);
   parameter [0:0] INIT = 1'b1;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -267,29 +263,25 @@ module FDPE ((* abc_arrival=303 *) output reg Q,
   endcase endgenerate
 endmodule
 
-module FDRE_1 ((* abc_arrival=303 *) output reg Q,
-               input C, CE, D, R);
+module FDRE_1 (output reg Q, input C, CE, D, R);
   parameter [0:0] INIT = 1'b0;
   initial Q <= INIT;
   always @(negedge C) if (R) Q <= 1'b0; else if(CE) Q <= D;
 endmodule
 
-module FDSE_1 ((* abc_arrival=303 *) output reg Q,
-               input C, CE, D, S);
+module FDSE_1 (output reg Q, input C, CE, D, S);
   parameter [0:0] INIT = 1'b1;
   initial Q <= INIT;
   always @(negedge C) if (S) Q <= 1'b1; else if(CE) Q <= D;
 endmodule
 
-module FDCE_1 ((* abc_arrival=303 *) output reg Q,
-               input C, CE, D, CLR);
+module FDCE_1 (output reg Q, input C, CE, D, CLR);
   parameter [0:0] INIT = 1'b0;
   initial Q <= INIT;
   always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
 endmodule
 
-module FDPE_1 ((* abc_arrival=303 *) output reg Q,
-               input C, CE, D, PRE);
+module FDPE_1 (output reg Q, input C, CE, D, PRE);
   parameter [0:0] INIT = 1'b1;
   initial Q <= INIT;
   always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index b9c4df82f..d28cd2428 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -379,6 +379,8 @@ struct SynthXilinxPass : public ScriptPass
 			std::string techmap_args = "-map +/techmap.v -map +/xilinx/cells_map.v";
 			if (widemux > 0)
 				techmap_args += stringf(" -D MIN_MUX_INPUTS=%d", widemux);
+			if (abc9)
+				techmap_args += " -map +/xilinx/ff_map.v";
 			run("techmap " + techmap_args);
 			run("clean");
 		}
@@ -409,9 +411,11 @@ struct SynthXilinxPass : public ScriptPass
 			//   has performed any necessary retiming
 			if (!nosrl || help_mode)
 				run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')");
-			std::string techmap_args = "-map +/xilinx/lut_map.v -map +/xilinx/ff_map.v";
+			std::string techmap_args = "-map +/xilinx/lut_map.v";
 			if (abc9)
 				techmap_args += " -map +/xilinx/abc_unmap.v";
+			else
+				techmap_args += " -map +/xilinx/ff_map.v";
 			run("techmap " + techmap_args);
 			run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
 					"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
-- 
cgit v1.2.3


From 79b6edb6397c530a7304eb4334f95324a4208aba Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 28 Sep 2019 23:48:17 -0700
Subject: Big rework; flop info now mostly in cells_sim.v

---
 techlibs/xilinx/abc_map.v       |  77 ++++++-----
 techlibs/xilinx/abc_model.v     |  90 +-----------
 techlibs/xilinx/abc_unmap.v     | 122 +----------------
 techlibs/xilinx/abc_xc7.box     |  22 ++-
 techlibs/xilinx/cells_sim.v     | 294 +++++++++++++++++++++++++++++++++-------
 techlibs/xilinx/synth_xilinx.cc |   4 +-
 6 files changed, 314 insertions(+), 295 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v
index 9f96d16be..056f66bbb 100644
--- a/techlibs/xilinx/abc_map.v
+++ b/techlibs/xilinx/abc_map.v
@@ -26,27 +26,23 @@ module FDRE (output reg Q, input C, CE, D, R);
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_R_INVERTED = 1'b0;
   wire \$nextQ ;
-  \$__ABC_FDRE #(
+  FDRE #(
     .INIT(INIT),
     .IS_C_INVERTED(IS_C_INVERTED),
     .IS_D_INVERTED(IS_D_INVERTED),
-    .IS_R_INVERTED(IS_R_INVERTED),
-    .CLK_POLARITY(!IS_C_INVERTED),
-    .EN_POLARITY(1'b1)
+    .IS_R_INVERTED(IS_R_INVERTED)
   ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .R(R)
+    .D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .R(R)
   );
   \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
 endmodule
 module FDRE_1 (output reg Q, input C, CE, D, R);
   parameter [0:0] INIT = 1'b0;
   wire \$nextQ ;
-  \$__ABC_FDRE_1 #(
-      .INIT(|0),
-    .CLK_POLARITY(1'b0),
-    .EN_POLARITY(1'b1)
+  FDRE_1 #(
+    .INIT(|0),
   ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .R(R)
+    .D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .R(R)
   );
   \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
 endmodule
@@ -57,28 +53,24 @@ module FDCE (output reg Q, input C, CE, D, CLR);
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_CLR_INVERTED = 1'b0;
   wire \$nextQ , \$currQ ;
-  \$__ABC_FDCE #(
+  FDCE #(
     .INIT(INIT),
     .IS_C_INVERTED(IS_C_INVERTED),
     .IS_D_INVERTED(IS_D_INVERTED),
-    .IS_CLR_INVERTED(IS_CLR_INVERTED),
-    .CLK_POLARITY(!IS_C_INVERTED),
-    .EN_POLARITY(1'b1)
+    .IS_CLR_INVERTED(IS_CLR_INVERTED)
   ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR)
+    .D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .CLR(CLR)
   );
   \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
-  \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(CLR), .Y(Q));
+  \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(CLR ^ IS_CLR_INVERTED), .Y(Q));
 endmodule
 module FDCE_1 (output reg Q, input C, CE, D, CLR);
   parameter [0:0] INIT = 1'b0;
   wire \$nextQ , \$currQ ;
-  \$__ABC_FDCE_1 #(
-    .INIT(INIT),
-    .CLK_POLARITY(1'b0),
-    .EN_POLARITY(1'b1)
+  FDCE_1 #(
+    .INIT(INIT)
   ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR)
+    .D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .CLR(CLR)
   );
   \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
   \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(CLR), .Y(Q));
@@ -90,33 +82,56 @@ module FDPE (output reg Q, input C, CE, D, PRE);
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_PRE_INVERTED = 1'b0;
   wire \$nextQ , \$currQ ;
-  \$__ABC_FDPE #(
+  FDPE #(
     .INIT(INIT),
     .IS_C_INVERTED(IS_C_INVERTED),
     .IS_D_INVERTED(IS_D_INVERTED),
     .IS_PRE_INVERTED(IS_PRE_INVERTED),
-    .CLK_POLARITY(!IS_C_INVERTED),
-    .EN_POLARITY(1'b1)
   ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE)
+    .D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .PRE(PRE)
   );
   \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
-  \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(PRE), .Y(Q));
+  \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(PRE ^ IS_PRE_INVERTED), .Y(Q));
 endmodule
 module FDPE_1 (output reg Q, input C, CE, D, PRE);
   parameter [0:0] INIT = 1'b0;
   wire \$nextQ , \$currQ ;
-  \$__ABC_FDPE_1 #(
-    .INIT(INIT),
-    .CLK_POLARITY(1'b0),
-    .EN_POLARITY(1'b1)
+  FDPE_1 #(
+    .INIT(INIT)
   ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE)
+    .D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .PRE(PRE)
   );
   \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
   \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(PRE), .Y(Q));
 endmodule
 
+module FDSE (output reg Q, input C, CE, D, S);
+  parameter [0:0] INIT = 1'b0;
+  parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  parameter [0:0] IS_S_INVERTED = 1'b0;
+  wire \$nextQ ;
+  FDSE #(
+    .INIT(INIT),
+    .IS_C_INVERTED(IS_C_INVERTED),
+    .IS_D_INVERTED(IS_D_INVERTED),
+    .IS_S_INVERTED(IS_S_INVERTED)
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .S(S)
+  );
+  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
+endmodule
+module FDSE_1 (output reg Q, input C, CE, D, S);
+  parameter [0:0] INIT = 1'b0;
+  wire \$nextQ ;
+  FDSE_1 #(
+    .INIT(|0),
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .S(S)
+  );
+  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
+endmodule
+
 module RAM32X1D (
   output DPO, SPO,
   input  D,
diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc_model.v
index d94ddb7e5..a2914464d 100644
--- a/techlibs/xilinx/abc_model.v
+++ b/techlibs/xilinx/abc_model.v
@@ -26,97 +26,9 @@ module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
                 : (S0 ? I1 : I0);
 endmodule
 
-module \$__ABC_FF_ (input C, D, output Q);
+module \$__ABC_FF_ (input D, output Q);
 endmodule
 
 (* abc_box_id = 1000 *)
 module \$__ABC_ASYNC (input A, S, output Y);
 endmodule
-
-(* abc_box_id=1001, lib_whitebox, abc_flop *)
-module \$__ABC_FDRE ((* abc_flop_q, abc_arrival=303 *) output Q,
-                     (* abc_flop_clk *) input C,
-                     (* abc_flop_en *)  input CE,
-                     (* abc_flop_d *)   input D,
-                     input R, \$pastQ );
-  parameter [0:0] INIT = 1'b0;
-  parameter [0:0] IS_C_INVERTED = 1'b0;
-  parameter [0:0] IS_D_INVERTED = 1'b0;
-  parameter [0:0] IS_R_INVERTED = 1'b0;
-  parameter CLK_POLARITY = !IS_C_INVERTED;
-  parameter EN_POLARITY = 1'b1;
-  assign Q = (R ^ IS_R_INVERTED) ? 1'b0 : (CE ? (D ^ IS_D_INVERTED) : \$pastQ );
-endmodule
-
-(* abc_box_id=1002, lib_whitebox, abc_flop *)
-module \$__ABC_FDRE_1 ((* abc_flop_q, abc_arrival=303 *) output Q,
-                       (* abc_flop_clk *) input C,
-                       (* abc_flop_en *)  input CE,
-                       (* abc_flop_d *)   input D,
-                       input R, \$pastQ );
-  parameter [0:0] INIT = 1'b0;
-  parameter CLK_POLARITY = 1'b0;
-  parameter EN_POLARITY = 1'b1;
-  assign Q = R ? 1'b0 : (CE ? D : \$pastQ );
-endmodule
-
-(* abc_box_id=1003, lib_whitebox, abc_flop *)
-module \$__ABC_FDCE ((* abc_flop_q, abc_arrival=303 *) output Q,
-                     (* abc_flop_clk *) input C,
-                     (* abc_flop_en *)  input CE,
-                     (* abc_flop_d *)   input D,
-                     input CLR, \$pastQ );
-  parameter [0:0] INIT = 1'b0;
-  parameter [0:0] IS_C_INVERTED = 1'b0;
-  parameter [0:0] IS_D_INVERTED = 1'b0;
-  parameter [0:0] IS_CLR_INVERTED = 1'b0;
-  parameter CLK_POLARITY = !IS_C_INVERTED;
-  parameter EN_POLARITY = 1'b1;
-  assign Q = (CE && !(CLR ^ IS_CLR_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
-endmodule
-
-(* abc_box_id=1004, lib_whitebox, abc_flop *)
-module \$__ABC_FDCE_1 ((* abc_flop_q, abc_arrival=303 *) output Q,
-                       (* abc_flop_clk *) input C,
-                       (* abc_flop_en *)  input CE,
-                       (* abc_flop_d *)   input D,
-                       input CLR, \$pastQ );
-  parameter [0:0] INIT = 1'b0;
-  parameter CLK_POLARITY = 1'b0;
-  parameter EN_POLARITY = 1'b1;
-  assign Q = (CE && !CLR) ? D : \$pastQ ;
-endmodule
-
-(* abc_box_id=1005, lib_whitebox, abc_flop *)
-module \$__ABC_FDPE ((* abc_flop_q, abc_arrival=303 *) output Q,
-                     (* abc_flop_clk *) input C,
-                     (* abc_flop_en *)  input CE,
-                     (* abc_flop_d *)   input D,
-                     input PRE, \$pastQ );
-  parameter [0:0] INIT = 1'b0;
-  parameter [0:0] IS_C_INVERTED = 1'b0;
-  parameter [0:0] IS_D_INVERTED = 1'b0;
-  parameter [0:0] IS_PRE_INVERTED = 1'b0;
-  parameter CLK_POLARITY = !IS_C_INVERTED;
-  parameter EN_POLARITY = 1'b1;
-  assign Q = (CE && !(PRE ^ IS_PRE_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
-endmodule
-
-(* abc_box_id=1006, lib_whitebox, abc_flop *)
-module \$__ABC_FDPE_1 ((* abc_flop_q, abc_arrival=303 *) output Q,
-                       (* abc_flop_clk *) input C,
-                       (* abc_flop_en *)  input CE,
-                       (* abc_flop_d *)   input D,
-                       input PRE, \$pastQ );
-  parameter [0:0] INIT = 1'b0; 
-  parameter CLK_POLARITY = 1'b0;
-  parameter EN_POLARITY = 1'b1;
-  assign Q = (CE && !PRE) ? D : \$pastQ ;
-endmodule
-
-(* abc_box_id=2000 *)
-module \$__ABC_LUT6 (input A, input [5:0] S, output Y);
-endmodule
-(* abc_box_id=2001 *)
-module \$__ABC_LUT7 (input A, input [6:0] S, output Y);
-endmodule
diff --git a/techlibs/xilinx/abc_unmap.v b/techlibs/xilinx/abc_unmap.v
index c24571747..bf8253adb 100644
--- a/techlibs/xilinx/abc_unmap.v
+++ b/techlibs/xilinx/abc_unmap.v
@@ -24,124 +24,6 @@ module \$__ABC_ASYNC (input A, S, output Y);
   assign Y = A;
 endmodule
 
-module \$__ABC_FDRE (output Q,
-                     input C,
-                     input CE,
-                     input D,
-                     input R, \$pastQ );
-  parameter [0:0] INIT = 1'b0;
-  parameter [0:0] IS_C_INVERTED = 1'b0;
-  parameter [0:0] IS_D_INVERTED = 1'b0;
-  parameter [0:0] IS_R_INVERTED = 1'b0;
-  parameter CLK_POLARITY = !IS_C_INVERTED;
-  parameter EN_POLARITY = 1'b1;
-
-  FDRE #(
-    .INIT(INIT),
-    .IS_C_INVERTED(IS_C_INVERTED),
-    .IS_D_INVERTED(IS_D_INVERTED),
-    .IS_R_INVERTED(IS_R_INVERTED),
-  ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(Q), .C(C), .CE(CE), .R(R)
-  );
-endmodule
-
-module \$__ABC_FDRE_1 (output Q,
-                       input C,
-                       input CE,
-                       input D,
-                       input R, \$pastQ );
-  parameter [0:0] INIT = 1'b0;
-  parameter CLK_POLARITY = 1'b0;
-  parameter EN_POLARITY = 1'b1;
-  assign Q = R ? 1'b0 : (CE ? D : \$pastQ );
-
-  FDRE_1 #(
-    .INIT(INIT),
-  ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(Q), .C(C), .CE(CE), .R(R)
-  );
-endmodule
-
-module \$__ABC_FDCE (output Q,
-                     input C,
-                     input CE,
-                     input D,
-                     input CLR, \$pastQ );
-  parameter [0:0] INIT = 1'b0;
-  parameter [0:0] IS_C_INVERTED = 1'b0;
-  parameter [0:0] IS_D_INVERTED = 1'b0;
-  parameter [0:0] IS_CLR_INVERTED = 1'b0;
-  parameter CLK_POLARITY = !IS_C_INVERTED;
-  parameter EN_POLARITY = 1'b1;
-
-  FDCE #(
-    .INIT(INIT),
-    .IS_C_INVERTED(IS_C_INVERTED),
-    .IS_D_INVERTED(IS_D_INVERTED),
-    .IS_CLR_INVERTED(IS_CLR_INVERTED),
-  ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(Q), .C(C), .CE(CE), .CLR(CLR)
-  );
-endmodule
-
-module \$__ABC_FDCE_1 (output Q,
-                       input C,
-                       input CE,
-                       input D,
-                       input CLR, \$pastQ );
-  parameter [0:0] INIT = 1'b0;
-  parameter CLK_POLARITY = 1'b0;
-  parameter EN_POLARITY = 1'b1;
-
-  FDCE_1 #(
-    .INIT(INIT),
-  ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(Q), .C(C), .CE(CE), .CLR(CLR)
-  );
-endmodule
-
-module \$__ABC_FDPE (output Q,
-                     input C,
-                     input CE,
-                     input D,
-                     input PRE, \$pastQ );
-  parameter [0:0] INIT = 1'b0;
-  parameter [0:0] IS_C_INVERTED = 1'b0;
-  parameter [0:0] IS_D_INVERTED = 1'b0;
-  parameter [0:0] IS_PRE_INVERTED = 1'b0;
-  parameter CLK_POLARITY = !IS_C_INVERTED;
-  parameter EN_POLARITY = 1'b1;
-
-  FDPE #(
-    .INIT(INIT),
-    .IS_C_INVERTED(IS_C_INVERTED),
-    .IS_D_INVERTED(IS_D_INVERTED),
-    .IS_PRE_INVERTED(IS_PRE_INVERTED),
-  ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(Q), .C(C), .CE(CE), .PRE(PRE)
-  );
-endmodule
-
-module \$__ABC_FDPE_1 (output Q,
-                       input C,
-                       input CE,
-                       input D,
-                       input PRE, \$pastQ );
-  parameter [0:0] INIT = 1'b0;
-  parameter CLK_POLARITY = 1'b0;
-  parameter EN_POLARITY = 1'b1;
-
-  FDPE_1 #(
-    .INIT(INIT),
-  ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(Q), .C(C), .CE(CE), .PRE(PRE)
-  );
-endmodule
-
-module \$__ABC_LUT6 (input A, input [5:0] S, output Y);
-  assign Y = A;
-endmodule
-module \$__ABC_LUT7 (input A, input [6:0] S, output Y);
-  assign Y = A;
+module \$__ABC_FF_ (input D, output Q);
+  assign Q = D;
 endmodule
diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
index aebb8b975..daaa4d16f 100644
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@ -52,36 +52,46 @@ $__ABC_ASYNC 1000 0 2 1
 # https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L237-L251
 # https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L265-L277
 
-# Inputs: C CE D R \$pastQ
+# Inputs: C CE D R \$currQ
 # Outputs: Q
 FDRE 1001 1 5 1
 0 151 0 446 0
 
-# Inputs: C CE D R \$pastQ
+# Inputs: C CE D R \$currQ
 # Outputs: Q
 FDRE_1 1002 1 5 1
 0 151 0 446 0
 
-# Inputs: C CE CLR D \$pastQ
+# Inputs: C CE CLR D \$currQ
 # Outputs: Q
 FDCE 1003 1 5 1
 0 151 806 0 0
 
-# Inputs: C CE CLR D \$pastQ
+# Inputs: C CE CLR D \$currQ
 # Outputs: Q
 FDCE_1 1004 1 5 1
 0 151 806 0 0
 
-# Inputs: C CE D PRE \$pastQ
+# Inputs: C CE D PRE \$currQ
 # Outputs: Q
 FDPE 1005 1 5 1
 0 151 0 806 0
 
-# Inputs: C CE D PRE \$pastQ
+# Inputs: C CE D PRE \$currQ
 # Outputs: Q
 FDPE_1 1006 1 5 1
 0 151 0 806 0
 
+# Inputs: C CE D S \$currQ
+# Outputs: Q
+FDSE 1007 1 5 1
+0 151 0 446 0
+
+# Inputs: C CE D S \$currQ
+# Outputs: Q
+FDSE_1 1008 1 5 1
+0 151 0 446 0
+
 # SLICEM/A6LUT
 # Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32}
 #   Necessary since RAMD* and SRL* have both combinatorial (i.e.
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index ef4340d10..ee9d48684 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -240,6 +240,7 @@ endmodule
 
 // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L238-L250
 
+(* abc_box_id=1001, lib_whitebox, abc9_flop *)
 module FDRE (
   (* abc_arrival=303 *)
   output reg Q,
@@ -257,35 +258,72 @@ module FDRE (
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_R_INVERTED = 1'b0;
   initial Q <= INIT;
+  wire \$currQ ;
+  reg \$nextQ ;
+  always @* if (R == !IS_R_INVERTED) \$nextQ = 1'b0; else if (CE) \$nextQ = D ^ IS_D_INVERTED; else \$nextQ = \$currQ ;
+`ifdef _ABC
+  // `abc9' requires that complex flops be split into a combinatorial
+  //   box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
+  //   In order to achieve clock-enable behaviour, the current value
+  //   of the sequential output is required which Yosys will
+  //   connect to the special `\$currQ' wire.
+
+  // Special signal indicating clock domain
+  //   (used to partition the module so that `abc9' only performs
+  //    sequential synthesis (reachability analysis) correctly on
+  //    one domain at a time)
+  wire [1:0] \$abc9_clock = {C, IS_C_INVERTED};
+  // Special signal indicating control domain
+  //   (which, combined with this spell type, encodes to `abc9'
+  //    which flops may be merged together)
+  wire [3:0] \$abc9_control = {CE, IS_D_INVERTED, R, IS_R_INVERTED};
+  always @* Q = \$nextQ ;
+`else
+  assign \$currQ = Q;
   generate case (|IS_C_INVERTED)
-    1'b0: always @(posedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
-    1'b1: always @(negedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
+    1'b0: always @(posedge C) Q <= \$nextQ ;
+    1'b1: always @(negedge C) Q <= \$nextQ ;
   endcase endgenerate
+`endif
 endmodule
 
-module FDSE (
+(* abc_box_id=1002, lib_whitebox, abc9_flop *)
+module FDRE_1 (
   (* abc_arrival=303 *)
   output reg Q,
   (* clkbuf_sink *)
-  (* invertible_pin = "IS_C_INVERTED" *)
   input C,
-  input CE,
-  (* invertible_pin = "IS_D_INVERTED" *)
-  input D,
-  (* invertible_pin = "IS_S_INVERTED" *)
-  input S
+  input CE, D, R
 );
-  parameter [0:0] INIT = 1'b1;
-  parameter [0:0] IS_C_INVERTED = 1'b0;
-  parameter [0:0] IS_D_INVERTED = 1'b0;
-  parameter [0:0] IS_S_INVERTED = 1'b0;
+  parameter [0:0] INIT = 1'b0;
   initial Q <= INIT;
-  generate case (|IS_C_INVERTED)
-    1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
-    1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
-  endcase endgenerate
+  wire \$currQ ;
+  reg \$nextQ ;
+  always @* if (R) Q <= 1'b0; else if (CE) Q <= D; else \$nextQ = \$currQ ;
+`ifdef _ABC
+  // `abc9' requires that complex flops be split into a combinatorial
+  //   box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
+  //   In order to achieve clock-enable behaviour, the current value
+  //   of the sequential output is required which Yosys will
+  //   connect to the special `\$currQ' wire.
+
+  // Special signal indicating clock domain
+  //   (used to partition the module so that `abc9' only performs
+  //    sequential synthesis (reachability analysis) correctly on
+  //    one domain at a time)
+  wire [1:0] \$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
+  // Special signal indicating control domain
+  //   (which, combined with this spell type, encodes to `abc9'
+  //    which flops may be merged together)
+  wire [3:0] \$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, R, 1'b0 /* IS_R_INVERTED */};
+  always @* Q = \$nextQ ;
+`else
+  assign \$currQ = Q;
+  always @(negedge C) Q <= \$nextQ ;
+`endif
 endmodule
 
+(* abc_box_id=1003, lib_whitebox, abc9_flop *)
 module FDCE (
   (* abc_arrival=303 *)
   output reg Q,
@@ -303,14 +341,78 @@ module FDCE (
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_CLR_INVERTED = 1'b0;
   initial Q <= INIT;
+  wire \$currQ ;
+  reg \$nextQ ;
+  always @* if (CE) Q <= D ^ IS_D_INVERTED; else \$nextQ = \$currQ ;
+`ifdef _ABC
+  // `abc9' requires that complex flops be split into a combinatorial
+  //   box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
+  //   In order to achieve clock-enable behaviour, the current value
+  //   of the sequential output is required which Yosys will
+  //   connect to the special `\$currQ' wire.
+  // Since this is an async flop, async behaviour is also dealt with
+  //   using the $_ABC_ASYNC box by abc_map.v
+
+  // Special signal indicating clock domain
+  //   (used to partition the module so that `abc9' only performs
+  //    sequential synthesis (reachability analysis) correctly on
+  //    one domain at a time)
+  wire [1:0] \$abc9_clock = {C, IS_C_INVERTED};
+  // Special signal indicating control domain
+  //   (which, combined with this spell type, encodes to `abc9'
+  //    which flops may be merged together)
+  wire [3:0] \$abc9_control = {CE, IS_D_INVERTED, CLR, IS_CLR_INVERTED};
+  always @* Q = \$nextQ ;
+`else
+  assign \$currQ = Q;
   generate case ({|IS_C_INVERTED, |IS_CLR_INVERTED})
-    2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
-    2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
-    2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
-    2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
+    2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else Q <= \$nextQ ;
+    2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else Q <= \$nextQ ;
+    2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else Q <= \$nextQ ;
+    2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else Q <= \$nextQ ;
   endcase endgenerate
+`endif
 endmodule
 
+(* abc_box_id=1004, lib_whitebox, abc9_flop *)
+module FDCE_1 (
+  (* abc_arrival=303 *)
+  output reg Q,
+  (* clkbuf_sink *)
+  input C,
+  input CE, D, CLR
+);
+  parameter [0:0] INIT = 1'b0;
+  initial Q <= INIT;
+  wire \$currQ ;
+  reg \$nextQ ;
+  always @* if (CE) Q <= D; else \$nextQ = \$currQ ;
+`ifdef _ABC
+  // `abc9' requires that complex flops be split into a combinatorial
+  //   box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
+  //   In order to achieve clock-enable behaviour, the current value
+  //   of the sequential output is required which Yosys will
+  //   connect to the special `\$currQ' wire.
+  // Since this is an async flop, async behaviour is also dealt with
+  //   using the $_ABC_ASYNC box by abc_map.v
+
+  // Special signal indicating clock domain
+  //   (used to partition the module so that `abc9' only performs
+  //    sequential synthesis (reachability analysis) correctly on
+  //    one domain at a time)
+  wire [1:0] \$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
+  // Special signal indicating control domain
+  //   (which, combined with this spell type, encodes to `abc9'
+  //    which flops may be merged together)
+  wire [3:0] \$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, CLR, 1'b0 /* IS_CLR_INVERTED */};
+  always @* Q = \$nextQ ;
+`else
+  assign \$currQ = Q;
+  always @(negedge C, posedge CLR) if (CLR == !IS_CLR_INVERTED) Q <= 1'b0; else Q <= \$nextQ ;
+`endif
+endmodule
+
+(* abc_box_id=1005, lib_whitebox, abc9_flop *)
 module FDPE (
   (* abc_arrival=303 *)
   output reg Q,
@@ -328,60 +430,158 @@ module FDPE (
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_PRE_INVERTED = 1'b0;
   initial Q <= INIT;
+  wire \$currQ ;
+  reg \$nextQ ;
+  always @* if (CE) Q <= D ^ IS_D_INVERTED; else \$nextQ = \$currQ ;
+`ifdef _ABC
+  // `abc9' requires that complex flops be split into a combinatorial
+  //   box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
+  //   In order to achieve clock-enable behaviour, the current value
+  //   of the sequential output is required which Yosys will
+  //   connect to the special `\$currQ' wire.
+  // Since this is an async flop, async behaviour is also dealt with
+  //   using the $_ABC_ASYNC box by abc_map.v
+
+  // Special signal indicating clock domain
+  //   (used to partition the module so that `abc9' only performs
+  //    sequential synthesis (reachability analysis) correctly on
+  //    one domain at a time)
+  wire [1:0] \$abc9_clock = {C, IS_C_INVERTED};
+  // Special signal indicating control domain
+  //   (which, combined with this spell type, encodes to `abc9'
+  //    which flops may be merged together)
+  wire [3:0] \$abc9_control = {CE, IS_D_INVERTED, PRE, IS_PRE_INVERTED};
+  always @* Q = \$nextQ ;
+`else
+  assign \$currQ = Q;
   generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED})
-    2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
-    2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
-    2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
-    2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
+    2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= \$nextQ ;
+    2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= \$nextQ ;
+    2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= \$nextQ ;
+    2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= \$nextQ ;
   endcase endgenerate
+`endif
 endmodule
 
-module FDRE_1 (
-  (* abc_arrival=303 *)
-  output reg Q,
-  (* clkbuf_sink *)
-  input C,
-  input CE, D, R
-);
-  parameter [0:0] INIT = 1'b0;
-  initial Q <= INIT;
-  always @(negedge C) if (R) Q <= 1'b0; else if(CE) Q <= D;
-endmodule
-
-module FDSE_1 (
+(* abc_box_id=1006, lib_whitebox, abc9_flop *)
+module FDPE_1 (
   (* abc_arrival=303 *)
   output reg Q,
   (* clkbuf_sink *)
   input C,
-  input CE, D, S
+  input CE, D, PRE
 );
   parameter [0:0] INIT = 1'b1;
   initial Q <= INIT;
-  always @(negedge C) if (S) Q <= 1'b1; else if(CE) Q <= D;
+  wire \$currQ ;
+  reg \$nextQ ;
+  always @* if (CE) Q <= D; else \$nextQ = \$currQ ;
+`ifdef _ABC
+  // `abc9' requires that complex flops be split into a combinatorial
+  //   box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
+  //   In order to achieve clock-enable behaviour, the current value
+  //   of the sequential output is required which Yosys will
+  //   connect to the special `\$currQ' wire.
+  // Since this is an async flop, async behaviour is also dealt with
+  //   using the $_ABC_ASYNC box by abc_map.v
+
+  // Special signal indicating clock domain
+  //   (used to partition the module so that `abc9' only performs
+  //    sequential synthesis (reachability analysis) correctly on
+  //    one domain at a time)
+  wire [1:0] \$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
+  // Special signal indicating control domain
+  //   (which, combined with this spell type, encodes to `abc9'
+  //    which flops may be merged together)
+  wire [3:0] \$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, PRE, 1'b0 /* IS_PRE_INVERTED */};
+  always @* Q = \$nextQ ;
+`else
+  assign \$currQ = Q;
+  always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else Q <= \$nextQ ;
+`endif
 endmodule
 
-module FDCE_1 (
+(* abc_box_id=1007, lib_whitebox, abc9_flop *)
+module FDSE (
   (* abc_arrival=303 *)
   output reg Q,
   (* clkbuf_sink *)
+  (* invertible_pin = "IS_C_INVERTED" *)
   input C,
-  input CE, D, CLR
+  input CE,
+  (* invertible_pin = "IS_D_INVERTED" *)
+  input D,
+  (* invertible_pin = "IS_S_INVERTED" *)
+  input S
 );
-  parameter [0:0] INIT = 1'b0;
+  parameter [0:0] INIT = 1'b1;
+  parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  parameter [0:0] IS_S_INVERTED = 1'b0;
   initial Q <= INIT;
-  always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
+  wire \$currQ ;
+  reg \$nextQ ;
+  always @* if (S == !IS_S_INVERTED) \$nextQ = 1'b1; else if (CE) \$nextQ = D ^ IS_D_INVERTED; else \$nextQ = \$currQ ;
+`ifdef _ABC
+  // `abc9' requires that complex flops be split into a combinatorial
+  //   box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
+  //   In order to achieve clock-enable behaviour, the current value
+  //   of the sequential output is required which Yosys will
+  //   connect to the special `\$currQ' wire.
+
+  // Special signal indicating clock domain
+  //   (used to partition the module so that `abc9' only performs
+  //    sequential synthesis (reachability analysis) correctly on
+  //    one domain at a time)
+  wire [1:0] \$abc9_clock = {C, IS_C_INVERTED};
+  // Special signal indicating control domain
+  //   (which, combined with this spell type, encodes to `abc9'
+  //    which flops may be merged together)
+  wire [3:0] \$abc9_control = {CE, IS_D_INVERTED, S, IS_S_INVERTED};
+  always @* Q = \$nextQ ;
+`else
+  assign \$currQ = Q;
+  generate case (|IS_C_INVERTED)
+    1'b0: always @(posedge C) Q <= \$nextQ ;
+    1'b1: always @(negedge C) Q <= \$nextQ ;
+  endcase endgenerate
+`endif
 endmodule
 
-module FDPE_1 (
+(* abc_box_id=1008, lib_whitebox, abc9_flop *)
+module FDSE_1 (
   (* abc_arrival=303 *)
   output reg Q,
   (* clkbuf_sink *)
   input C,
-  input CE, D, PRE
+  input CE, D, S
 );
   parameter [0:0] INIT = 1'b1;
   initial Q <= INIT;
-  always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
+  wire \$currQ ;
+  reg \$nextQ ;
+  always @* if (S) \$nextQ = 1'b1; else if (CE) \$nextQ = D; else \$nextQ = \$currQ ;
+`ifdef _ABC
+  // `abc9' requires that complex flops be split into a combinatorial
+  //   box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
+  //   In order to achieve clock-enable behaviour, the current value
+  //   of the sequential output is required which Yosys will
+  //   connect to the special `\$currQ' wire.
+
+  // Special signal indicating clock domain
+  //   (used to partition the module so that `abc9' only performs
+  //    sequential synthesis (reachability analysis) correctly on
+  //    one domain at a time)
+  wire [1:0] \$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
+  // Special signal indicating control domain
+  //   (which, combined with this spell type, encodes to `abc9'
+  //    which flops may be merged together)
+  wire [3:0] \$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */};
+  always @* Q = \$nextQ ;
+`else
+  assign \$currQ = Q;
+  always @(negedge C) Q <= \$nextQ ;
+`endif
 endmodule
 
 module RAM32X1D (
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 888b5ed7b..f5143ca82 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -276,9 +276,9 @@ struct SynthXilinxPass : public ScriptPass
 
 		if (check_label("begin")) {
 			if (vpr)
-				run("read_verilog -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
+				run("read_verilog -lib -D_ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
 			else
-				run("read_verilog -lib +/xilinx/cells_sim.v");
+				run("read_verilog -lib -D_ABC +/xilinx/cells_sim.v");
 
 			if (help_mode)
 				run("read_verilog -lib +/xilinx/{family}_cells_xtra.v");
-- 
cgit v1.2.3


From 18ebb86edbade4a94833dead59d69fddd980f5bd Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Sun, 29 Sep 2019 11:25:34 -0700
Subject: FDCE_1 does not have IS_CLR_INVERTED

---
 techlibs/xilinx/cells_sim.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index ee9d48684..cf39bd45b 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -408,7 +408,7 @@ module FDCE_1 (
   always @* Q = \$nextQ ;
 `else
   assign \$currQ = Q;
-  always @(negedge C, posedge CLR) if (CLR == !IS_CLR_INVERTED) Q <= 1'b0; else Q <= \$nextQ ;
+  always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else Q <= \$nextQ ;
 `endif
 endmodule
 
-- 
cgit v1.2.3


From f6203e6bd65f7383f14a15e926fc4b8f5f9a3edf Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Sun, 29 Sep 2019 21:55:53 -0700
Subject: Missing endmodule

---
 techlibs/xilinx/abc_model.v | 1 +
 1 file changed, 1 insertion(+)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc_model.v
index b302e46f6..8255804c2 100644
--- a/techlibs/xilinx/abc_model.v
+++ b/techlibs/xilinx/abc_model.v
@@ -35,6 +35,7 @@ endmodule
 
 (* abc_box_id = 1000 *)
 module \$__ABC_ASYNC (input A, S, output Y);
+endmodule
 
 // Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32}
 //   Necessary since RAMD* and SRL* have both combinatorial (i.e.
-- 
cgit v1.2.3


From 5e9ae90cbba4e9c2abfe5d6a1b90c2256aae1615 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 30 Sep 2019 15:39:24 -0700
Subject: Add explanation to abc_map.v

---
 techlibs/xilinx/abc_map.v | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v
index cb252b828..6a0e18abe 100644
--- a/techlibs/xilinx/abc_map.v
+++ b/techlibs/xilinx/abc_map.v
@@ -18,8 +18,24 @@
  *
  */
 
+// The following techmapping rules are intended to be run (with -max_iter 1)
+//   before invoking the `abc9` pass in order to transform the design into
+//   a format that it understands.
+//
+// For example, (complex) flip-flops are expected to be described as an
+//   combinatorial box (containing all control logic such as clock enable
+//   or synchronous resets) followed by a basic D-Q flop.
+
 // ============================================================================
 
+// The purpose of the following FD* rules are to wrap the flop (which, when
+//   called with the `_ABC' macro set captures contains only its combinatorial
+//   behaviour) with:
+// (a) a special $__ABC_FF_ in front of the FD*'s output, indicating to abc9
+//     the location of its basic D-Q flop
+// (b) a special \$currQ connection that feeds back into the (combinatorial)
+//     FD* cell to facilitate clock-enable behaviour -- note that \$currQ
+//     isn't a real input port, it is one that is understood only by abc9
 module FDRE (output reg Q, input C, CE, D, R);
   parameter [0:0] INIT = 1'b0;
   parameter [0:0] IS_C_INVERTED = 1'b0;
-- 
cgit v1.2.3


From e529872b0170ba269db2d00c96108c86b260e864 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 30 Sep 2019 16:33:40 -0700
Subject: Remove need for $currQ port connection

---
 techlibs/xilinx/abc_map.v   |  69 ++++++++++---------
 techlibs/xilinx/cells_sim.v | 160 ++++++++++++++++++++++----------------------
 2 files changed, 118 insertions(+), 111 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v
index 6a0e18abe..4eec77df9 100644
--- a/techlibs/xilinx/abc_map.v
+++ b/techlibs/xilinx/abc_map.v
@@ -33,34 +33,35 @@
 //   behaviour) with:
 // (a) a special $__ABC_FF_ in front of the FD*'s output, indicating to abc9
 //     the location of its basic D-Q flop
-// (b) a special \$currQ connection that feeds back into the (combinatorial)
-//     FD* cell to facilitate clock-enable behaviour -- note that \$currQ
-//     isn't a real input port, it is one that is understood only by abc9
+// (b) a special TECHMAP_REPLACE_.$currQwire that will be used for feedback
+//     into the (combinatorial) FD* cell to facilitate clock-enable behaviour
 module FDRE (output reg Q, input C, CE, D, R);
   parameter [0:0] INIT = 1'b0;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_R_INVERTED = 1'b0;
-  wire \$nextQ ;
+  wire $nextQ;
   FDRE #(
     .INIT(INIT),
     .IS_C_INVERTED(IS_C_INVERTED),
     .IS_D_INVERTED(IS_D_INVERTED),
     .IS_R_INVERTED(IS_R_INVERTED)
   ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .R(R)
+    .D(D), .Q($nextQ), .C(C), .CE(CE), .R(R)
   );
-  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
+  wire _TECHMAP_REPLACE_.$currQ = Q;
+  \$__ABC_FF_ abc_dff (.D($nextQ), .Q(Q));
 endmodule
 module FDRE_1 (output reg Q, input C, CE, D, R);
   parameter [0:0] INIT = 1'b0;
-  wire \$nextQ ;
+  wire $nextQ;
   FDRE_1 #(
     .INIT(|0),
   ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .R(R)
+    .D(D), .Q($nextQ), .C(C), .CE(CE), .R(R)
   );
-  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
+  wire _TECHMAP_REPLACE_.$currQ = Q;
+  \$__ABC_FF_ abc_dff (.D($nextQ), .Q(Q));
 endmodule
 
 module FDCE (output reg Q, input C, CE, D, CLR);
@@ -68,28 +69,30 @@ module FDCE (output reg Q, input C, CE, D, CLR);
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_CLR_INVERTED = 1'b0;
-  wire \$nextQ , \$currQ ;
+  wire $currQ, $nextQ;
   FDCE #(
     .INIT(INIT),
     .IS_C_INVERTED(IS_C_INVERTED),
     .IS_D_INVERTED(IS_D_INVERTED),
     .IS_CLR_INVERTED(IS_CLR_INVERTED)
   ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .CLR(CLR)
+    .D(D), .Q($nextQ),  .C(C), .CE(CE), .CLR(CLR)
   );
-  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
-  \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(CLR ^ IS_CLR_INVERTED), .Y(Q));
+  wire _TECHMAP_REPLACE_.$currQ = Q;
+  \$__ABC_FF_ abc_dff (.D($nextQ), .Q($currQ));
+  \$__ABC_ASYNC abc_async (.A($currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(Q));
 endmodule
 module FDCE_1 (output reg Q, input C, CE, D, CLR);
   parameter [0:0] INIT = 1'b0;
-  wire \$nextQ , \$currQ ;
+  wire $nextQ, $currQ;
   FDCE_1 #(
     .INIT(INIT)
   ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .CLR(CLR)
+    .D(D), .Q($nextQ), .C(C), .CE(CE), .CLR(CLR)
   );
-  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
-  \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(CLR), .Y(Q));
+  wire _TECHMAP_REPLACE_.$currQ = Q;
+  \$__ABC_FF_ abc_dff (.D($nextQ), .Q($currQ));
+  \$__ABC_ASYNC abc_async (.A($currQ), .S(CLR), .Y(Q));
 endmodule
 
 module FDPE (output reg Q, input C, CE, D, PRE);
@@ -97,28 +100,30 @@ module FDPE (output reg Q, input C, CE, D, PRE);
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_PRE_INVERTED = 1'b0;
-  wire \$nextQ , \$currQ ;
+  wire $nextQ, $currQ;
   FDPE #(
     .INIT(INIT),
     .IS_C_INVERTED(IS_C_INVERTED),
     .IS_D_INVERTED(IS_D_INVERTED),
     .IS_PRE_INVERTED(IS_PRE_INVERTED),
   ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .PRE(PRE)
+    .D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(PRE)
   );
-  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
-  \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(PRE ^ IS_PRE_INVERTED), .Y(Q));
+  wire _TECHMAP_REPLACE_.$currQ = Q;
+  \$__ABC_FF_ abc_dff (.D($nextQ), .Q($currQ));
+  \$__ABC_ASYNC abc_async (.A($currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(Q));
 endmodule
 module FDPE_1 (output reg Q, input C, CE, D, PRE);
   parameter [0:0] INIT = 1'b0;
-  wire \$nextQ , \$currQ ;
+  wire $nextQ, $currQ;
   FDPE_1 #(
     .INIT(INIT)
   ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .PRE(PRE)
+    .D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(PRE)
   );
-  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
-  \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(PRE), .Y(Q));
+  wire _TECHMAP_REPLACE_.$currQ = Q;
+  \$__ABC_FF_ abc_dff (.D($nextQ), .Q($currQ));
+  \$__ABC_ASYNC abc_async (.A($currQ), .S(PRE), .Y(Q));
 endmodule
 
 module FDSE (output reg Q, input C, CE, D, S);
@@ -126,26 +131,28 @@ module FDSE (output reg Q, input C, CE, D, S);
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_S_INVERTED = 1'b0;
-  wire \$nextQ ;
+  wire $nextQ;
   FDSE #(
     .INIT(INIT),
     .IS_C_INVERTED(IS_C_INVERTED),
     .IS_D_INVERTED(IS_D_INVERTED),
     .IS_S_INVERTED(IS_S_INVERTED)
   ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .S(S)
+    .D(D), .Q($nextQ), .C(C), .CE(CE), .S(S)
   );
-  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
+  wire _TECHMAP_REPLACE_.$currQ = Q;
+  \$__ABC_FF_ abc_dff (.D($nextQ), .Q(Q));
 endmodule
 module FDSE_1 (output reg Q, input C, CE, D, S);
   parameter [0:0] INIT = 1'b0;
-  wire \$nextQ ;
+  wire $nextQ;
   FDSE_1 #(
     .INIT(|0),
   ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .S(S)
+    .D(D), .Q($nextQ), .C(C), .CE(CE), .S(S)
   );
-  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
+  wire _TECHMAP_REPLACE_.$currQ = Q;
+  \$__ABC_FF_ abc_dff (.D($nextQ), .Q(Q));
 endmodule
 
 module RAM32X1D (
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 3aa686e81..7ab28b0aa 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -258,31 +258,31 @@ module FDRE (
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_R_INVERTED = 1'b0;
   initial Q <= INIT;
-  wire \$currQ ;
-  reg \$nextQ ;
-  always @* if (R == !IS_R_INVERTED) \$nextQ = 1'b0; else if (CE) \$nextQ = D ^ IS_D_INVERTED; else \$nextQ = \$currQ ;
+  wire $currQ;
+  reg $nextQ;
+  always @* if (R == !IS_R_INVERTED) $nextQ = 1'b0; else if (CE) $nextQ = D ^ IS_D_INVERTED; else $nextQ = $currQ;
 `ifdef _ABC
   // `abc9' requires that complex flops be split into a combinatorial
   //   box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
   //   In order to achieve clock-enable behaviour, the current value
   //   of the sequential output is required which Yosys will
-  //   connect to the special `\$currQ' wire.
+  //   connect to the special `$currQ' wire.
 
   // Special signal indicating clock domain
   //   (used to partition the module so that `abc9' only performs
   //    sequential synthesis (reachability analysis) correctly on
   //    one domain at a time)
-  wire [1:0] \$abc9_clock = {C, IS_C_INVERTED};
+  wire [1:0] $abc9_clock = {C, IS_C_INVERTED};
   // Special signal indicating control domain
   //   (which, combined with this spell type, encodes to `abc9'
   //    which flops may be merged together)
-  wire [3:0] \$abc9_control = {CE, IS_D_INVERTED, R, IS_R_INVERTED};
-  always @* Q = \$nextQ ;
+  wire [3:0] $abc9_control = {CE, IS_D_INVERTED, R, IS_R_INVERTED};
+  always @* Q = $nextQ;
 `else
-  assign \$currQ = Q;
+  assign $currQ = Q;
   generate case (|IS_C_INVERTED)
-    1'b0: always @(posedge C) Q <= \$nextQ ;
-    1'b1: always @(negedge C) Q <= \$nextQ ;
+    1'b0: always @(posedge C) Q <= $nextQ;
+    1'b1: always @(negedge C) Q <= $nextQ;
   endcase endgenerate
 `endif
 endmodule
@@ -297,29 +297,29 @@ module FDRE_1 (
 );
   parameter [0:0] INIT = 1'b0;
   initial Q <= INIT;
-  wire \$currQ ;
-  reg \$nextQ ;
-  always @* if (R) Q <= 1'b0; else if (CE) Q <= D; else \$nextQ = \$currQ ;
+  wire $currQ;
+  reg $nextQ;
+  always @* if (R) Q <= 1'b0; else if (CE) Q <= D; else $nextQ = $currQ;
 `ifdef _ABC
   // `abc9' requires that complex flops be split into a combinatorial
   //   box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
   //   In order to achieve clock-enable behaviour, the current value
   //   of the sequential output is required which Yosys will
-  //   connect to the special `\$currQ' wire.
+  //   connect to the special `$currQ' wire.
 
   // Special signal indicating clock domain
   //   (used to partition the module so that `abc9' only performs
   //    sequential synthesis (reachability analysis) correctly on
   //    one domain at a time)
-  wire [1:0] \$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
+  wire [1:0] $abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
   // Special signal indicating control domain
   //   (which, combined with this spell type, encodes to `abc9'
   //    which flops may be merged together)
-  wire [3:0] \$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, R, 1'b0 /* IS_R_INVERTED */};
-  always @* Q = \$nextQ ;
+  wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, R, 1'b0 /* IS_R_INVERTED */};
+  always @* Q = $nextQ;
 `else
-  assign \$currQ = Q;
-  always @(negedge C) Q <= \$nextQ ;
+  assign $currQ = Q;
+  always @(negedge C) Q <= $nextQ;
 `endif
 endmodule
 
@@ -341,15 +341,15 @@ module FDCE (
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_CLR_INVERTED = 1'b0;
   initial Q <= INIT;
-  wire \$currQ ;
-  reg \$nextQ ;
-  always @* if (CE) Q <= D ^ IS_D_INVERTED; else \$nextQ = \$currQ ;
+  wire $currQ;
+  reg $nextQ;
+  always @* if (CE) Q <= D ^ IS_D_INVERTED; else $nextQ = $currQ;
 `ifdef _ABC
   // `abc9' requires that complex flops be split into a combinatorial
   //   box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
   //   In order to achieve clock-enable behaviour, the current value
   //   of the sequential output is required which Yosys will
-  //   connect to the special `\$currQ' wire.
+  //   connect to the special `$currQ' wire.
   // Since this is an async flop, async behaviour is also dealt with
   //   using the $_ABC_ASYNC box by abc_map.v
 
@@ -357,19 +357,19 @@ module FDCE (
   //   (used to partition the module so that `abc9' only performs
   //    sequential synthesis (reachability analysis) correctly on
   //    one domain at a time)
-  wire [1:0] \$abc9_clock = {C, IS_C_INVERTED};
+  wire [1:0] $abc9_clock = {C, IS_C_INVERTED};
   // Special signal indicating control domain
   //   (which, combined with this spell type, encodes to `abc9'
   //    which flops may be merged together)
-  wire [3:0] \$abc9_control = {CE, IS_D_INVERTED, CLR, IS_CLR_INVERTED};
-  always @* Q = \$nextQ ;
+  wire [3:0] $abc9_control = {CE, IS_D_INVERTED, CLR, IS_CLR_INVERTED};
+  always @* Q = $nextQ;
 `else
-  assign \$currQ = Q;
+  assign $currQ = Q;
   generate case ({|IS_C_INVERTED, |IS_CLR_INVERTED})
-    2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else Q <= \$nextQ ;
-    2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else Q <= \$nextQ ;
-    2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else Q <= \$nextQ ;
-    2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else Q <= \$nextQ ;
+    2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else Q <= $nextQ;
+    2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else Q <= $nextQ;
+    2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else Q <= $nextQ;
+    2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else Q <= $nextQ;
   endcase endgenerate
 `endif
 endmodule
@@ -384,15 +384,15 @@ module FDCE_1 (
 );
   parameter [0:0] INIT = 1'b0;
   initial Q <= INIT;
-  wire \$currQ ;
-  reg \$nextQ ;
-  always @* if (CE) Q <= D; else \$nextQ = \$currQ ;
+  wire $currQ;
+  reg $nextQ;
+  always @* if (CE) Q <= D; else $nextQ = $currQ;
 `ifdef _ABC
   // `abc9' requires that complex flops be split into a combinatorial
   //   box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
   //   In order to achieve clock-enable behaviour, the current value
   //   of the sequential output is required which Yosys will
-  //   connect to the special `\$currQ' wire.
+  //   connect to the special `$currQ' wire.
   // Since this is an async flop, async behaviour is also dealt with
   //   using the $_ABC_ASYNC box by abc_map.v
 
@@ -400,15 +400,15 @@ module FDCE_1 (
   //   (used to partition the module so that `abc9' only performs
   //    sequential synthesis (reachability analysis) correctly on
   //    one domain at a time)
-  wire [1:0] \$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
+  wire [1:0] $abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
   // Special signal indicating control domain
   //   (which, combined with this spell type, encodes to `abc9'
   //    which flops may be merged together)
-  wire [3:0] \$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, CLR, 1'b0 /* IS_CLR_INVERTED */};
-  always @* Q = \$nextQ ;
+  wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, CLR, 1'b0 /* IS_CLR_INVERTED */};
+  always @* Q = $nextQ;
 `else
-  assign \$currQ = Q;
-  always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else Q <= \$nextQ ;
+  assign $currQ = Q;
+  always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else Q <= $nextQ;
 `endif
 endmodule
 
@@ -430,15 +430,15 @@ module FDPE (
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_PRE_INVERTED = 1'b0;
   initial Q <= INIT;
-  wire \$currQ ;
-  reg \$nextQ ;
-  always @* if (CE) Q <= D ^ IS_D_INVERTED; else \$nextQ = \$currQ ;
+  wire $currQ;
+  reg $nextQ;
+  always @* if (CE) Q <= D ^ IS_D_INVERTED; else $nextQ = $currQ;
 `ifdef _ABC
   // `abc9' requires that complex flops be split into a combinatorial
   //   box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
   //   In order to achieve clock-enable behaviour, the current value
   //   of the sequential output is required which Yosys will
-  //   connect to the special `\$currQ' wire.
+  //   connect to the special `$currQ' wire.
   // Since this is an async flop, async behaviour is also dealt with
   //   using the $_ABC_ASYNC box by abc_map.v
 
@@ -446,19 +446,19 @@ module FDPE (
   //   (used to partition the module so that `abc9' only performs
   //    sequential synthesis (reachability analysis) correctly on
   //    one domain at a time)
-  wire [1:0] \$abc9_clock = {C, IS_C_INVERTED};
+  wire [1:0] $abc9_clock = {C, IS_C_INVERTED};
   // Special signal indicating control domain
   //   (which, combined with this spell type, encodes to `abc9'
   //    which flops may be merged together)
-  wire [3:0] \$abc9_control = {CE, IS_D_INVERTED, PRE, IS_PRE_INVERTED};
-  always @* Q = \$nextQ ;
+  wire [3:0] $abc9_control = {CE, IS_D_INVERTED, PRE, IS_PRE_INVERTED};
+  always @* Q = $nextQ;
 `else
-  assign \$currQ = Q;
+  assign $currQ = Q;
   generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED})
-    2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= \$nextQ ;
-    2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= \$nextQ ;
-    2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= \$nextQ ;
-    2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= \$nextQ ;
+    2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= $nextQ;
+    2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= $nextQ;
+    2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= $nextQ;
+    2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= $nextQ;
   endcase endgenerate
 `endif
 endmodule
@@ -473,15 +473,15 @@ module FDPE_1 (
 );
   parameter [0:0] INIT = 1'b1;
   initial Q <= INIT;
-  wire \$currQ ;
-  reg \$nextQ ;
-  always @* if (CE) Q <= D; else \$nextQ = \$currQ ;
+  wire $currQ;
+  reg $nextQ;
+  always @* if (CE) Q <= D; else $nextQ = $currQ;
 `ifdef _ABC
   // `abc9' requires that complex flops be split into a combinatorial
   //   box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
   //   In order to achieve clock-enable behaviour, the current value
   //   of the sequential output is required which Yosys will
-  //   connect to the special `\$currQ' wire.
+  //   connect to the special `$currQ' wire.
   // Since this is an async flop, async behaviour is also dealt with
   //   using the $_ABC_ASYNC box by abc_map.v
 
@@ -489,15 +489,15 @@ module FDPE_1 (
   //   (used to partition the module so that `abc9' only performs
   //    sequential synthesis (reachability analysis) correctly on
   //    one domain at a time)
-  wire [1:0] \$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
+  wire [1:0] $abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
   // Special signal indicating control domain
   //   (which, combined with this spell type, encodes to `abc9'
   //    which flops may be merged together)
-  wire [3:0] \$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, PRE, 1'b0 /* IS_PRE_INVERTED */};
-  always @* Q = \$nextQ ;
+  wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, PRE, 1'b0 /* IS_PRE_INVERTED */};
+  always @* Q = $nextQ;
 `else
-  assign \$currQ = Q;
-  always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else Q <= \$nextQ ;
+  assign $currQ = Q;
+  always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else Q <= $nextQ;
 `endif
 endmodule
 
@@ -519,31 +519,31 @@ module FDSE (
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_S_INVERTED = 1'b0;
   initial Q <= INIT;
-  wire \$currQ ;
-  reg \$nextQ ;
-  always @* if (S == !IS_S_INVERTED) \$nextQ = 1'b1; else if (CE) \$nextQ = D ^ IS_D_INVERTED; else \$nextQ = \$currQ ;
+  wire $currQ;
+  reg $nextQ;
+  always @* if (S == !IS_S_INVERTED) $nextQ = 1'b1; else if (CE) $nextQ = D ^ IS_D_INVERTED; else $nextQ = $currQ;
 `ifdef _ABC
   // `abc9' requires that complex flops be split into a combinatorial
   //   box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
   //   In order to achieve clock-enable behaviour, the current value
   //   of the sequential output is required which Yosys will
-  //   connect to the special `\$currQ' wire.
+  //   connect to the special `$currQ' wire.
 
   // Special signal indicating clock domain
   //   (used to partition the module so that `abc9' only performs
   //    sequential synthesis (reachability analysis) correctly on
   //    one domain at a time)
-  wire [1:0] \$abc9_clock = {C, IS_C_INVERTED};
+  wire [1:0] $abc9_clock = {C, IS_C_INVERTED};
   // Special signal indicating control domain
   //   (which, combined with this spell type, encodes to `abc9'
   //    which flops may be merged together)
-  wire [3:0] \$abc9_control = {CE, IS_D_INVERTED, S, IS_S_INVERTED};
-  always @* Q = \$nextQ ;
+  wire [3:0] $abc9_control = {CE, IS_D_INVERTED, S, IS_S_INVERTED};
+  always @* Q = $nextQ;
 `else
-  assign \$currQ = Q;
+  assign $currQ = Q;
   generate case (|IS_C_INVERTED)
-    1'b0: always @(posedge C) Q <= \$nextQ ;
-    1'b1: always @(negedge C) Q <= \$nextQ ;
+    1'b0: always @(posedge C) Q <= $nextQ;
+    1'b1: always @(negedge C) Q <= $nextQ;
   endcase endgenerate
 `endif
 endmodule
@@ -558,29 +558,29 @@ module FDSE_1 (
 );
   parameter [0:0] INIT = 1'b1;
   initial Q <= INIT;
-  wire \$currQ ;
-  reg \$nextQ ;
-  always @* if (S) \$nextQ = 1'b1; else if (CE) \$nextQ = D; else \$nextQ = \$currQ ;
+  wire $currQ;
+  reg $nextQ;
+  always @* if (S) $nextQ = 1'b1; else if (CE) $nextQ = D; else $nextQ = $currQ;
 `ifdef _ABC
   // `abc9' requires that complex flops be split into a combinatorial
   //   box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
   //   In order to achieve clock-enable behaviour, the current value
   //   of the sequential output is required which Yosys will
-  //   connect to the special `\$currQ' wire.
+  //   connect to the special `$currQ' wire.
 
   // Special signal indicating clock domain
   //   (used to partition the module so that `abc9' only performs
   //    sequential synthesis (reachability analysis) correctly on
   //    one domain at a time)
-  wire [1:0] \$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
+  wire [1:0] $abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
   // Special signal indicating control domain
   //   (which, combined with this spell type, encodes to `abc9'
   //    which flops may be merged together)
-  wire [3:0] \$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */};
-  always @* Q = \$nextQ ;
+  wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */};
+  always @* Q = $nextQ;
 `else
-  assign \$currQ = Q;
-  always @(negedge C) Q <= \$nextQ ;
+  assign $currQ = Q;
+  always @(negedge C) Q <= $nextQ;
 `endif
 endmodule
 
-- 
cgit v1.2.3


From 03ebe43e3edce03d3dc24f80c05e16cdb7b76748 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 1 Oct 2019 13:05:56 -0700
Subject: Escape Verilog identifiers for legality outside of Yosys

---
 techlibs/xilinx/cells_sim.v | 96 ++++++++++++++++++++++-----------------------
 1 file changed, 48 insertions(+), 48 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 7ab28b0aa..84139cd9c 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -258,9 +258,9 @@ module FDRE (
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_R_INVERTED = 1'b0;
   initial Q <= INIT;
-  wire $currQ;
-  reg $nextQ;
-  always @* if (R == !IS_R_INVERTED) $nextQ = 1'b0; else if (CE) $nextQ = D ^ IS_D_INVERTED; else $nextQ = $currQ;
+  wire \$currQ ;
+  reg \$nextQ ;
+  always @* if (R == !IS_R_INVERTED) $nextQ = 1'b0; else if (CE) $nextQ = D ^ IS_D_INVERTED; else $nextQ = \$currQ ;
 `ifdef _ABC
   // `abc9' requires that complex flops be split into a combinatorial
   //   box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
@@ -277,12 +277,12 @@ module FDRE (
   //   (which, combined with this spell type, encodes to `abc9'
   //    which flops may be merged together)
   wire [3:0] $abc9_control = {CE, IS_D_INVERTED, R, IS_R_INVERTED};
-  always @* Q = $nextQ;
+  always @* Q = \$nextQ ;
 `else
   assign $currQ = Q;
   generate case (|IS_C_INVERTED)
-    1'b0: always @(posedge C) Q <= $nextQ;
-    1'b1: always @(negedge C) Q <= $nextQ;
+    1'b0: always @(posedge C) Q <= \$nextQ ;
+    1'b1: always @(negedge C) Q <= \$nextQ ;
   endcase endgenerate
 `endif
 endmodule
@@ -297,9 +297,9 @@ module FDRE_1 (
 );
   parameter [0:0] INIT = 1'b0;
   initial Q <= INIT;
-  wire $currQ;
-  reg $nextQ;
-  always @* if (R) Q <= 1'b0; else if (CE) Q <= D; else $nextQ = $currQ;
+  wire \$currQ ;
+  reg \$nextQ ;
+  always @* if (R) Q <= 1'b0; else if (CE) Q <= D; else $nextQ = \$currQ ;
 `ifdef _ABC
   // `abc9' requires that complex flops be split into a combinatorial
   //   box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
@@ -316,10 +316,10 @@ module FDRE_1 (
   //   (which, combined with this spell type, encodes to `abc9'
   //    which flops may be merged together)
   wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, R, 1'b0 /* IS_R_INVERTED */};
-  always @* Q = $nextQ;
+  always @* Q = \$nextQ ;
 `else
   assign $currQ = Q;
-  always @(negedge C) Q <= $nextQ;
+  always @(negedge C) Q <= \$nextQ ;
 `endif
 endmodule
 
@@ -341,9 +341,9 @@ module FDCE (
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_CLR_INVERTED = 1'b0;
   initial Q <= INIT;
-  wire $currQ;
-  reg $nextQ;
-  always @* if (CE) Q <= D ^ IS_D_INVERTED; else $nextQ = $currQ;
+  wire \$currQ ;
+  reg \$nextQ ;
+  always @* if (CE) Q <= D ^ IS_D_INVERTED; else $nextQ = \$currQ ;
 `ifdef _ABC
   // `abc9' requires that complex flops be split into a combinatorial
   //   box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
@@ -362,14 +362,14 @@ module FDCE (
   //   (which, combined with this spell type, encodes to `abc9'
   //    which flops may be merged together)
   wire [3:0] $abc9_control = {CE, IS_D_INVERTED, CLR, IS_CLR_INVERTED};
-  always @* Q = $nextQ;
+  always @* Q = \$nextQ ;
 `else
   assign $currQ = Q;
   generate case ({|IS_C_INVERTED, |IS_CLR_INVERTED})
-    2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else Q <= $nextQ;
-    2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else Q <= $nextQ;
-    2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else Q <= $nextQ;
-    2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else Q <= $nextQ;
+    2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else Q <= \$nextQ ;
+    2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else Q <= \$nextQ ;
+    2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else Q <= \$nextQ ;
+    2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else Q <= \$nextQ ;
   endcase endgenerate
 `endif
 endmodule
@@ -384,9 +384,9 @@ module FDCE_1 (
 );
   parameter [0:0] INIT = 1'b0;
   initial Q <= INIT;
-  wire $currQ;
-  reg $nextQ;
-  always @* if (CE) Q <= D; else $nextQ = $currQ;
+  wire \$currQ ;
+  reg \$nextQ ;
+  always @* if (CE) Q <= D; else $nextQ = \$currQ ;
 `ifdef _ABC
   // `abc9' requires that complex flops be split into a combinatorial
   //   box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
@@ -405,10 +405,10 @@ module FDCE_1 (
   //   (which, combined with this spell type, encodes to `abc9'
   //    which flops may be merged together)
   wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, CLR, 1'b0 /* IS_CLR_INVERTED */};
-  always @* Q = $nextQ;
+  always @* Q = \$nextQ ;
 `else
   assign $currQ = Q;
-  always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else Q <= $nextQ;
+  always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else Q <= \$nextQ ;
 `endif
 endmodule
 
@@ -430,9 +430,9 @@ module FDPE (
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_PRE_INVERTED = 1'b0;
   initial Q <= INIT;
-  wire $currQ;
-  reg $nextQ;
-  always @* if (CE) Q <= D ^ IS_D_INVERTED; else $nextQ = $currQ;
+  wire \$currQ ;
+  reg \$nextQ ;
+  always @* if (CE) Q <= D ^ IS_D_INVERTED; else $nextQ = \$currQ ;
 `ifdef _ABC
   // `abc9' requires that complex flops be split into a combinatorial
   //   box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
@@ -451,14 +451,14 @@ module FDPE (
   //   (which, combined with this spell type, encodes to `abc9'
   //    which flops may be merged together)
   wire [3:0] $abc9_control = {CE, IS_D_INVERTED, PRE, IS_PRE_INVERTED};
-  always @* Q = $nextQ;
+  always @* Q = \$nextQ ;
 `else
   assign $currQ = Q;
   generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED})
-    2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= $nextQ;
-    2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= $nextQ;
-    2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= $nextQ;
-    2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= $nextQ;
+    2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= \$nextQ ;
+    2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= \$nextQ ;
+    2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= \$nextQ ;
+    2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= \$nextQ ;
   endcase endgenerate
 `endif
 endmodule
@@ -473,9 +473,9 @@ module FDPE_1 (
 );
   parameter [0:0] INIT = 1'b1;
   initial Q <= INIT;
-  wire $currQ;
-  reg $nextQ;
-  always @* if (CE) Q <= D; else $nextQ = $currQ;
+  wire \$currQ ;
+  reg \$nextQ ;
+  always @* if (CE) Q <= D; else $nextQ = \$currQ ;
 `ifdef _ABC
   // `abc9' requires that complex flops be split into a combinatorial
   //   box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
@@ -494,10 +494,10 @@ module FDPE_1 (
   //   (which, combined with this spell type, encodes to `abc9'
   //    which flops may be merged together)
   wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, PRE, 1'b0 /* IS_PRE_INVERTED */};
-  always @* Q = $nextQ;
+  always @* Q = \$nextQ ;
 `else
   assign $currQ = Q;
-  always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else Q <= $nextQ;
+  always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else Q <= \$nextQ ;
 `endif
 endmodule
 
@@ -519,9 +519,9 @@ module FDSE (
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_S_INVERTED = 1'b0;
   initial Q <= INIT;
-  wire $currQ;
-  reg $nextQ;
-  always @* if (S == !IS_S_INVERTED) $nextQ = 1'b1; else if (CE) $nextQ = D ^ IS_D_INVERTED; else $nextQ = $currQ;
+  wire \$currQ ;
+  reg \$nextQ ;
+  always @* if (S == !IS_S_INVERTED) $nextQ = 1'b1; else if (CE) $nextQ = D ^ IS_D_INVERTED; else $nextQ = \$currQ ;
 `ifdef _ABC
   // `abc9' requires that complex flops be split into a combinatorial
   //   box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
@@ -538,12 +538,12 @@ module FDSE (
   //   (which, combined with this spell type, encodes to `abc9'
   //    which flops may be merged together)
   wire [3:0] $abc9_control = {CE, IS_D_INVERTED, S, IS_S_INVERTED};
-  always @* Q = $nextQ;
+  always @* Q = \$nextQ ;
 `else
   assign $currQ = Q;
   generate case (|IS_C_INVERTED)
-    1'b0: always @(posedge C) Q <= $nextQ;
-    1'b1: always @(negedge C) Q <= $nextQ;
+    1'b0: always @(posedge C) Q <= \$nextQ ;
+    1'b1: always @(negedge C) Q <= \$nextQ ;
   endcase endgenerate
 `endif
 endmodule
@@ -558,9 +558,9 @@ module FDSE_1 (
 );
   parameter [0:0] INIT = 1'b1;
   initial Q <= INIT;
-  wire $currQ;
-  reg $nextQ;
-  always @* if (S) $nextQ = 1'b1; else if (CE) $nextQ = D; else $nextQ = $currQ;
+  wire \$currQ ;
+  reg \$nextQ ;
+  always @* if (S) $nextQ = 1'b1; else if (CE) $nextQ = D; else $nextQ = \$currQ ;
 `ifdef _ABC
   // `abc9' requires that complex flops be split into a combinatorial
   //   box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
@@ -577,10 +577,10 @@ module FDSE_1 (
   //   (which, combined with this spell type, encodes to `abc9'
   //    which flops may be merged together)
   wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */};
-  always @* Q = $nextQ;
+  always @* Q = \$nextQ ;
 `else
   assign $currQ = Q;
-  always @(negedge C) Q <= $nextQ;
+  always @(negedge C) Q <= \$nextQ ;
 `endif
 endmodule
 
-- 
cgit v1.2.3


From 5299884f049e73c395fdff090b345b15d54aab1e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 1 Oct 2019 13:41:08 -0700
Subject: More fixes

---
 techlibs/xilinx/cells_sim.v | 32 ++++++++++++++++----------------
 1 file changed, 16 insertions(+), 16 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 84139cd9c..04aa60f91 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -260,7 +260,7 @@ module FDRE (
   initial Q <= INIT;
   wire \$currQ ;
   reg \$nextQ ;
-  always @* if (R == !IS_R_INVERTED) $nextQ = 1'b0; else if (CE) $nextQ = D ^ IS_D_INVERTED; else $nextQ = \$currQ ;
+  always @* if (R == !IS_R_INVERTED) \$nextQ = 1'b0; else if (CE) \$nextQ = D ^ IS_D_INVERTED; else \$nextQ = \$currQ ;
 `ifdef _ABC
   // `abc9' requires that complex flops be split into a combinatorial
   //   box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
@@ -279,7 +279,7 @@ module FDRE (
   wire [3:0] $abc9_control = {CE, IS_D_INVERTED, R, IS_R_INVERTED};
   always @* Q = \$nextQ ;
 `else
-  assign $currQ = Q;
+  assign \$currQ = Q;
   generate case (|IS_C_INVERTED)
     1'b0: always @(posedge C) Q <= \$nextQ ;
     1'b1: always @(negedge C) Q <= \$nextQ ;
@@ -299,7 +299,7 @@ module FDRE_1 (
   initial Q <= INIT;
   wire \$currQ ;
   reg \$nextQ ;
-  always @* if (R) Q <= 1'b0; else if (CE) Q <= D; else $nextQ = \$currQ ;
+  always @* if (R) Q <= 1'b0; else if (CE) Q <= D; else \$nextQ = \$currQ ;
 `ifdef _ABC
   // `abc9' requires that complex flops be split into a combinatorial
   //   box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
@@ -318,7 +318,7 @@ module FDRE_1 (
   wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, R, 1'b0 /* IS_R_INVERTED */};
   always @* Q = \$nextQ ;
 `else
-  assign $currQ = Q;
+  assign \$currQ = Q;
   always @(negedge C) Q <= \$nextQ ;
 `endif
 endmodule
@@ -343,7 +343,7 @@ module FDCE (
   initial Q <= INIT;
   wire \$currQ ;
   reg \$nextQ ;
-  always @* if (CE) Q <= D ^ IS_D_INVERTED; else $nextQ = \$currQ ;
+  always @* if (CE) Q <= D ^ IS_D_INVERTED; else \$nextQ = \$currQ ;
 `ifdef _ABC
   // `abc9' requires that complex flops be split into a combinatorial
   //   box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
@@ -364,7 +364,7 @@ module FDCE (
   wire [3:0] $abc9_control = {CE, IS_D_INVERTED, CLR, IS_CLR_INVERTED};
   always @* Q = \$nextQ ;
 `else
-  assign $currQ = Q;
+  assign \$currQ = Q;
   generate case ({|IS_C_INVERTED, |IS_CLR_INVERTED})
     2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else Q <= \$nextQ ;
     2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else Q <= \$nextQ ;
@@ -386,7 +386,7 @@ module FDCE_1 (
   initial Q <= INIT;
   wire \$currQ ;
   reg \$nextQ ;
-  always @* if (CE) Q <= D; else $nextQ = \$currQ ;
+  always @* if (CE) Q <= D; else \$nextQ = \$currQ ;
 `ifdef _ABC
   // `abc9' requires that complex flops be split into a combinatorial
   //   box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
@@ -407,7 +407,7 @@ module FDCE_1 (
   wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, CLR, 1'b0 /* IS_CLR_INVERTED */};
   always @* Q = \$nextQ ;
 `else
-  assign $currQ = Q;
+  assign \$currQ = Q;
   always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else Q <= \$nextQ ;
 `endif
 endmodule
@@ -432,7 +432,7 @@ module FDPE (
   initial Q <= INIT;
   wire \$currQ ;
   reg \$nextQ ;
-  always @* if (CE) Q <= D ^ IS_D_INVERTED; else $nextQ = \$currQ ;
+  always @* if (CE) Q <= D ^ IS_D_INVERTED; else \$nextQ = \$currQ ;
 `ifdef _ABC
   // `abc9' requires that complex flops be split into a combinatorial
   //   box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
@@ -453,7 +453,7 @@ module FDPE (
   wire [3:0] $abc9_control = {CE, IS_D_INVERTED, PRE, IS_PRE_INVERTED};
   always @* Q = \$nextQ ;
 `else
-  assign $currQ = Q;
+  assign \$currQ = Q;
   generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED})
     2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= \$nextQ ;
     2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= \$nextQ ;
@@ -475,7 +475,7 @@ module FDPE_1 (
   initial Q <= INIT;
   wire \$currQ ;
   reg \$nextQ ;
-  always @* if (CE) Q <= D; else $nextQ = \$currQ ;
+  always @* if (CE) Q <= D; else \$nextQ = \$currQ ;
 `ifdef _ABC
   // `abc9' requires that complex flops be split into a combinatorial
   //   box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
@@ -496,7 +496,7 @@ module FDPE_1 (
   wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, PRE, 1'b0 /* IS_PRE_INVERTED */};
   always @* Q = \$nextQ ;
 `else
-  assign $currQ = Q;
+  assign \$currQ = Q;
   always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else Q <= \$nextQ ;
 `endif
 endmodule
@@ -521,7 +521,7 @@ module FDSE (
   initial Q <= INIT;
   wire \$currQ ;
   reg \$nextQ ;
-  always @* if (S == !IS_S_INVERTED) $nextQ = 1'b1; else if (CE) $nextQ = D ^ IS_D_INVERTED; else $nextQ = \$currQ ;
+  always @* if (S == !IS_S_INVERTED) \$nextQ = 1'b1; else if (CE) \$nextQ = D ^ IS_D_INVERTED; else \$nextQ = \$currQ ;
 `ifdef _ABC
   // `abc9' requires that complex flops be split into a combinatorial
   //   box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
@@ -540,7 +540,7 @@ module FDSE (
   wire [3:0] $abc9_control = {CE, IS_D_INVERTED, S, IS_S_INVERTED};
   always @* Q = \$nextQ ;
 `else
-  assign $currQ = Q;
+  assign \$currQ = Q;
   generate case (|IS_C_INVERTED)
     1'b0: always @(posedge C) Q <= \$nextQ ;
     1'b1: always @(negedge C) Q <= \$nextQ ;
@@ -560,7 +560,7 @@ module FDSE_1 (
   initial Q <= INIT;
   wire \$currQ ;
   reg \$nextQ ;
-  always @* if (S) $nextQ = 1'b1; else if (CE) $nextQ = D; else $nextQ = \$currQ ;
+  always @* if (S) \$nextQ = 1'b1; else if (CE) \$nextQ = D; else \$nextQ = \$currQ ;
 `ifdef _ABC
   // `abc9' requires that complex flops be split into a combinatorial
   //   box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
@@ -579,7 +579,7 @@ module FDSE_1 (
   wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */};
   always @* Q = \$nextQ ;
 `else
-  assign $currQ = Q;
+  assign \$currQ = Q;
   always @(negedge C) Q <= \$nextQ ;
 `endif
 endmodule
-- 
cgit v1.2.3


From 655f1b2ac559f73a7d781ae25afd1ab3b898afc0 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 3 Oct 2019 10:11:25 -0700
Subject: English

---
 techlibs/xilinx/abc_map.v | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v
index 4eec77df9..db996fbc3 100644
--- a/techlibs/xilinx/abc_map.v
+++ b/techlibs/xilinx/abc_map.v
@@ -29,11 +29,11 @@
 // ============================================================================
 
 // The purpose of the following FD* rules are to wrap the flop (which, when
-//   called with the `_ABC' macro set captures contains only its combinatorial
+//   called with the `_ABC' macro set captures only its combinatorial
 //   behaviour) with:
 // (a) a special $__ABC_FF_ in front of the FD*'s output, indicating to abc9
-//     the location of its basic D-Q flop
-// (b) a special TECHMAP_REPLACE_.$currQwire that will be used for feedback
+//     the connectivity of its basic D-Q flop
+// (b) a special TECHMAP_REPLACE_.$currQ wire that will be used for feedback
 //     into the (combinatorial) FD* cell to facilitate clock-enable behaviour
 module FDRE (output reg Q, input C, CE, D, R);
   parameter [0:0] INIT = 1'b0;
-- 
cgit v1.2.3


From 7959e9d6b25d7afefded4b14e14ccf2b0b5af553 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 4 Oct 2019 17:21:14 -0700
Subject: Fix merge issues

---
 techlibs/xilinx/abc9_map.v   | 18 +++++++++---------
 techlibs/xilinx/abc9_unmap.v |  1 +
 2 files changed, 10 insertions(+), 9 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v
index 0b81be15f..05063f86d 100644
--- a/techlibs/xilinx/abc9_map.v
+++ b/techlibs/xilinx/abc9_map.v
@@ -31,7 +31,7 @@
 // The purpose of the following FD* rules are to wrap the flop (which, when
 //   called with the `_ABC' macro set captures only its combinatorial
 //   behaviour) with:
-// (a) a special $__ABC_FF_ in front of the FD*'s output, indicating to abc9
+// (a) a special $__ABC9_FF_ in front of the FD*'s output, indicating to abc9
 //     the connectivity of its basic D-Q flop
 // (b) a special TECHMAP_REPLACE_.$currQ wire that will be used for feedback
 //     into the (combinatorial) FD* cell to facilitate clock-enable behaviour
@@ -50,7 +50,7 @@ module FDRE (output reg Q, input C, CE, D, R);
     .D(D), .Q($nextQ), .C(C), .CE(CE), .R(R)
   );
   wire _TECHMAP_REPLACE_.$currQ = Q;
-  \$__ABC_FF_ abc_dff (.D($nextQ), .Q(Q));
+  \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q));
 endmodule
 module FDRE_1 (output reg Q, input C, CE, D, R);
   parameter [0:0] INIT = 1'b0;
@@ -61,7 +61,7 @@ module FDRE_1 (output reg Q, input C, CE, D, R);
     .D(D), .Q($nextQ), .C(C), .CE(CE), .R(R)
   );
   wire _TECHMAP_REPLACE_.$currQ = Q;
-  \$__ABC_FF_ abc_dff (.D($nextQ), .Q(Q));
+  \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q));
 endmodule
 
 module FDCE (output reg Q, input C, CE, D, CLR);
@@ -79,7 +79,7 @@ module FDCE (output reg Q, input C, CE, D, CLR);
     .D(D), .Q($nextQ),  .C(C), .CE(CE), .CLR(CLR)
   );
   wire _TECHMAP_REPLACE_.$currQ = Q;
-  \$__ABC_FF_ abc_dff (.D($nextQ), .Q($currQ));
+  \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($currQ));
   \$__ABC_ASYNC abc_async (.A($currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(Q));
 endmodule
 module FDCE_1 (output reg Q, input C, CE, D, CLR);
@@ -91,7 +91,7 @@ module FDCE_1 (output reg Q, input C, CE, D, CLR);
     .D(D), .Q($nextQ), .C(C), .CE(CE), .CLR(CLR)
   );
   wire _TECHMAP_REPLACE_.$currQ = Q;
-  \$__ABC_FF_ abc_dff (.D($nextQ), .Q($currQ));
+  \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($currQ));
   \$__ABC_ASYNC abc_async (.A($currQ), .S(CLR), .Y(Q));
 endmodule
 
@@ -110,7 +110,7 @@ module FDPE (output reg Q, input C, CE, D, PRE);
     .D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(PRE)
   );
   wire _TECHMAP_REPLACE_.$currQ = Q;
-  \$__ABC_FF_ abc_dff (.D($nextQ), .Q($currQ));
+  \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($currQ));
   \$__ABC_ASYNC abc_async (.A($currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(Q));
 endmodule
 module FDPE_1 (output reg Q, input C, CE, D, PRE);
@@ -122,7 +122,7 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE);
     .D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(PRE)
   );
   wire _TECHMAP_REPLACE_.$currQ = Q;
-  \$__ABC_FF_ abc_dff (.D($nextQ), .Q($currQ));
+  \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($currQ));
   \$__ABC_ASYNC abc_async (.A($currQ), .S(PRE), .Y(Q));
 endmodule
 
@@ -141,7 +141,7 @@ module FDSE (output reg Q, input C, CE, D, S);
     .D(D), .Q($nextQ), .C(C), .CE(CE), .S(S)
   );
   wire _TECHMAP_REPLACE_.$currQ = Q;
-  \$__ABC_FF_ abc_dff (.D($nextQ), .Q(Q));
+  \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q));
 endmodule
 module FDSE_1 (output reg Q, input C, CE, D, S);
   parameter [0:0] INIT = 1'b0;
@@ -152,7 +152,7 @@ module FDSE_1 (output reg Q, input C, CE, D, S);
     .D(D), .Q($nextQ), .C(C), .CE(CE), .S(S)
   );
   wire _TECHMAP_REPLACE_.$currQ = Q;
-  \$__ABC_FF_ abc_dff (.D($nextQ), .Q(Q));
+  \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q));
 endmodule
 
 module RAM32X1D (
diff --git a/techlibs/xilinx/abc9_unmap.v b/techlibs/xilinx/abc9_unmap.v
index f97b0bc66..21fe78d08 100644
--- a/techlibs/xilinx/abc9_unmap.v
+++ b/techlibs/xilinx/abc9_unmap.v
@@ -26,6 +26,7 @@ endmodule
 
 module \$__ABC9_FF_ (input D, output Q);
   assign Q = D;
+endmodule
 
 module \$__ABC9_LUT6 (input A, input [5:0] S, output Y);
   assign Y = A;
-- 
cgit v1.2.3


From d4212d128b5985cf09f5e7f14bc06e7323e644ac Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 4 Oct 2019 17:27:05 -0700
Subject: Use read_args for read_verilog

---
 techlibs/xilinx/synth_xilinx.cc | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 16b607aac..caeeb3266 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -283,10 +283,13 @@ struct SynthXilinxPass : public ScriptPass
 			ff_map_file = "+/xilinx/xc7_ff_map.v";
 
 		if (check_label("begin")) {
+			std::string read_args;
 			if (vpr)
-				run("read_verilog -lib -D_ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
-			else
-				run("read_verilog -lib -D_ABC +/xilinx/cells_sim.v");
+				read_args += " -D_EXPLICIT_CARRY";
+			if (abc9)
+				read_args += " -D_ABC9";
+			read_args += " -lib +/xilinx/cells_sim.v";
+			run("read_verilog" + read_args);
 
 			if (help_mode)
 				run("read_verilog -lib +/xilinx/{family}_cells_xtra.v");
-- 
cgit v1.2.3


From a2ef93f03a1f75c25329c66d0e7d69da71e88e1f Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 4 Oct 2019 17:56:38 -0700
Subject: abc -> abc9

---
 techlibs/xilinx/synth_xilinx.cc | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 6c598acf2..07f3d9a8a 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -481,13 +481,13 @@ struct SynthXilinxPass : public ScriptPass
 							"will use timing for 'xc7' instead.\n", family.c_str());
 				run("techmap -map +/xilinx/abc9_map.v -max_iter 1");
 				run("read_verilog -icells -lib +/xilinx/abc9_model.v");
-				std::string abc9_opts = " -box +/xilinx/abc_xc7.box";
+				std::string abc9_opts = " -box +/xilinx/abc9_xc7.box";
 				abc9_opts += stringf(" -W %d", XC7_WIRE_DELAY);
 				abc9_opts += " -nomfs";
 				if (nowidelut)
-					abc9_opts += " -lut +/xilinx/abc_xc7_nowide.lut";
+					abc9_opts += " -lut +/xilinx/abc9_xc7_nowide.lut";
 				else
-					abc9_opts += " -lut +/xilinx/abc_xc7.lut";
+					abc9_opts += " -lut +/xilinx/abc9_xc7.lut";
 				run("abc9" + abc9_opts);
 			}
 			else {
-- 
cgit v1.2.3


From 3879ca13983a6e3f7d4653b1d80dacd14fbe82df Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 5 Oct 2019 22:55:18 -0700
Subject: Do not require changes to cells_sim.v; try and work out comb model

---
 techlibs/xilinx/abc9_map.v   | 199 ++++++++++++++++++++++++++++++++++----
 techlibs/xilinx/abc9_model.v |   5 +-
 techlibs/xilinx/abc9_xc7.box |   2 +-
 techlibs/xilinx/cells_sim.v  | 224 ++++---------------------------------------
 4 files changed, 200 insertions(+), 230 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v
index 05063f86d..ef7a1a09f 100644
--- a/techlibs/xilinx/abc9_map.v
+++ b/techlibs/xilinx/abc9_map.v
@@ -49,8 +49,57 @@ module FDRE (output reg Q, input C, CE, D, R);
   ) _TECHMAP_REPLACE_ (
     .D(D), .Q($nextQ), .C(C), .CE(CE), .R(R)
   );
-  wire _TECHMAP_REPLACE_.$currQ = Q;
+  // `abc9' requires that complex flops be split into a combinatorial box
+  //   feeding a simple flop ($_ABC9_FF_).
+  // Yosys will automatically analyse the simulation model (described in
+  //   cells_sim.v) and detach any $_DFF_P_ or $_DFF_N_ cells present in
+  //   order to extract the combinatorial control logic left behind.
+  //   Specifically, a simulation model similar to the one below:
+  //
+  //           ++===================================++
+  //           ||                        Sim model  ||
+  //           ||      /\/\/\/\                     ||
+  //       D -->>-----<        >     +------+       ||
+  //       R -->>-----<  Comb. >     |$_DFF_|       ||
+  //      CE -->>-----<  logic >-----| [NP]_|---+---->>-- Q
+  //           ||  +--<        >     +------+   |   ||
+  //           ||  |   \/\/\/\/                 |   ||
+  //           ||  |                            |   ||
+  //           ||  +----------------------------+   ||
+  //           ||                                   ||
+  //           ++===================================++
+  //
+  //   is transformed into:
+  //
+  //           ++==================++
+  //           ||         Comb box ||
+  //           ||                  ||
+  //           ||      /\/\/\/\    ||
+  //      D  -->>-----<        >   ||            +------+
+  //      R  -->>-----<  Comb. >   ||            |$_ABC_|
+  //     CE  -->>-----<  logic >--->>-- $nextQ --|  FF_ |--+-->> Q
+  // $currQ +-->>-----<        >   ||            +------+  |
+  //        |  ||      \/\/\/\/    ||                      |
+  //        |  ||                  ||                      |
+  //        |  ++==================++                      |
+  //        |                                              |
+  //        +----------------------------------------------+
   \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q));
+
+  // Special signal indicating clock domain
+  //   (used to partition the module so that `abc9' only performs
+  //    sequential synthesis (reachability analysis) correctly on
+  //    one domain at a time)
+  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
+  // Special signal indicating control domain
+  //   (which, combined with this cell type, encodes to `abc9'
+  //    which flops may be merged together)
+  wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, R, IS_R_INVERTED};
+  // Special signal indicating the current value of the flip-flop
+  //   In order to achieve clock-enable behaviour, the current value
+  //   of the sequential output is required which Yosys will
+  //   connect to the special `$currQ' wire.
+  wire _TECHMAP_REPLACE_.$currQ = Q;
 endmodule
 module FDRE_1 (output reg Q, input C, CE, D, R);
   parameter [0:0] INIT = 1'b0;
@@ -60,8 +109,22 @@ module FDRE_1 (output reg Q, input C, CE, D, R);
   ) _TECHMAP_REPLACE_ (
     .D(D), .Q($nextQ), .C(C), .CE(CE), .R(R)
   );
-  wire _TECHMAP_REPLACE_.$currQ = Q;
   \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q));
+
+  // Special signal indicating clock domain
+  //   (used to partition the module so that `abc9' only performs
+  //    sequential synthesis (reachability analysis) correctly on
+  //    one domain at a time)
+  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
+  // Special signal indicating control domain
+  //   (which, combined with this spell type, encodes to `abc9'
+  //    which flops may be merged together)
+  wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, R, 1'b0 /* IS_R_INVERTED */};
+  // Special signal indicating the current value of the flip-flop
+  //   In order to achieve clock-enable behaviour, the current value
+  //   of the sequential output is required which Yosys will
+  //   connect to the special `$currQ' wire.
+  wire _TECHMAP_REPLACE_.$currQ = Q;
 endmodule
 
 module FDCE (output reg Q, input C, CE, D, CLR);
@@ -69,18 +132,38 @@ module FDCE (output reg Q, input C, CE, D, CLR);
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_CLR_INVERTED = 1'b0;
-  wire $currQ, $nextQ;
+  wire $nextQ, $currQ;
   FDCE #(
     .INIT(INIT),
     .IS_C_INVERTED(IS_C_INVERTED),
     .IS_D_INVERTED(IS_D_INVERTED),
     .IS_CLR_INVERTED(IS_CLR_INVERTED)
   ) _TECHMAP_REPLACE_ (
-    .D(D), .Q($nextQ),  .C(C), .CE(CE), .CLR(CLR)
+    .D(D), .Q($nextQ),  .C(C), .CE(CE), .CLR(IS_CLR_INVERTED)
+                                         // ^^^ Note that async
+                                         //     control is disabled
+                                         //     and captured by
+                                         //     $__ABC9_ASYNC below
   );
-  wire _TECHMAP_REPLACE_.$currQ = Q;
   \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($currQ));
-  \$__ABC_ASYNC abc_async (.A($currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(Q));
+  // Since this is an async flop, async behaviour is also dealt with
+  //   using the $_ABC9_ASYNC box by abc9_map.v
+  \$__ABC9_ASYNC abc_async (.A($currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(Q));
+
+  // Special signal indicating clock domain
+  //   (used to partition the module so that `abc9' only performs
+  //    sequential synthesis (reachability analysis) correctly on
+  //    one domain at a time)
+  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
+  // Special signal indicating control domain
+  //   (which, combined with this spell type, encodes to `abc9'
+  //    which flops may be merged together)
+  wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, CLR, IS_CLR_INVERTED};
+  // Special signal indicating the current value of the flip-flop
+  //   In order to achieve clock-enable behaviour, the current value
+  //   of the sequential output is required which Yosys will
+  //   connect to the special `$currQ' wire.
+  wire _TECHMAP_REPLACE_.$currQ = $currQ;
 endmodule
 module FDCE_1 (output reg Q, input C, CE, D, CLR);
   parameter [0:0] INIT = 1'b0;
@@ -88,11 +171,29 @@ module FDCE_1 (output reg Q, input C, CE, D, CLR);
   FDCE_1 #(
     .INIT(INIT)
   ) _TECHMAP_REPLACE_ (
-    .D(D), .Q($nextQ), .C(C), .CE(CE), .CLR(CLR)
+    .D(D), .Q($nextQ), .C(C), .CE(CE), .CLR(1'b0)
+                                         // ^^^ Note that async
+                                         //     control is disabled
+                                         //     and captured by
+                                         //     $__ABC9_ASYNC below
   );
-  wire _TECHMAP_REPLACE_.$currQ = Q;
   \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($currQ));
-  \$__ABC_ASYNC abc_async (.A($currQ), .S(CLR), .Y(Q));
+  \$__ABC9_ASYNC abc_async (.A($currQ), .S(CLR), .Y(Q));
+
+  // Special signal indicating clock domain
+  //   (used to partition the module so that `abc9' only performs
+  //    sequential synthesis (reachability analysis) correctly on
+  //    one domain at a time)
+  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
+  // Special signal indicating control domain
+  //   (which, combined with this spell type, encodes to `abc9'
+  //    which flops may be merged together)
+  wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, CLR, 1'b0 /* IS_CLR_INVERTED */};
+  // Special signal indicating the current value of the flip-flop
+  //   In order to achieve clock-enable behaviour, the current value
+  //   of the sequential output is required which Yosys will
+  //   connect to the special `$currQ' wire.
+  wire _TECHMAP_REPLACE_.$currQ = $currQ;
 endmodule
 
 module FDPE (output reg Q, input C, CE, D, PRE);
@@ -107,11 +208,29 @@ module FDPE (output reg Q, input C, CE, D, PRE);
     .IS_D_INVERTED(IS_D_INVERTED),
     .IS_PRE_INVERTED(IS_PRE_INVERTED),
   ) _TECHMAP_REPLACE_ (
-    .D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(PRE)
+    .D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(IS_PRE_INVERTED)
+                                         // ^^^ Note that async
+                                         //     control is disabled
+                                         //     and captured by
+                                         //     $__ABC9_ASYNC below
   );
-  wire _TECHMAP_REPLACE_.$currQ = Q;
   \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($currQ));
-  \$__ABC_ASYNC abc_async (.A($currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(Q));
+  \$__ABC9_ASYNC abc_async (.A($currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(Q));
+
+  // Special signal indicating clock domain
+  //   (used to partition the module so that `abc9' only performs
+  //    sequential synthesis (reachability analysis) correctly on
+  //    one domain at a time)
+  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
+  // Special signal indicating control domain
+  //   (which, combined with this spell type, encodes to `abc9'
+  //    which flops may be merged together)
+  wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, PRE, IS_PRE_INVERTED};
+  // Special signal indicating the current value of the flip-flop
+  //   In order to achieve clock-enable behaviour, the current value
+  //   of the sequential output is required which Yosys will
+  //   connect to the special `$currQ' wire.
+  wire _TECHMAP_REPLACE_.$currQ = $currQ;
 endmodule
 module FDPE_1 (output reg Q, input C, CE, D, PRE);
   parameter [0:0] INIT = 1'b0;
@@ -119,11 +238,29 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE);
   FDPE_1 #(
     .INIT(INIT)
   ) _TECHMAP_REPLACE_ (
-    .D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(PRE)
+    .D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(1'b0)
+                                         // ^^^ Note that async
+                                         //     control is disabled
+                                         //     and captured by
+                                         //     $__ABC9_ASYNC below
   );
-  wire _TECHMAP_REPLACE_.$currQ = Q;
   \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($currQ));
-  \$__ABC_ASYNC abc_async (.A($currQ), .S(PRE), .Y(Q));
+  \$__ABC9_ASYNC abc_async (.A($currQ), .S(PRE), .Y(Q));
+
+  // Special signal indicating clock domain
+  //   (used to partition the module so that `abc9' only performs
+  //    sequential synthesis (reachability analysis) correctly on
+  //    one domain at a time)
+  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
+  // Special signal indicating control domain
+  //   (which, combined with this spell type, encodes to `abc9'
+  //    which flops may be merged together)
+  wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, PRE, 1'b0 /* IS_PRE_INVERTED */};
+  // Special signal indicating the current value of the flip-flop
+  //   In order to achieve clock-enable behaviour, the current value
+  //   of the sequential output is required which Yosys will
+  //   connect to the special `$currQ' wire.
+  wire _TECHMAP_REPLACE_.$currQ = $currQ;
 endmodule
 
 module FDSE (output reg Q, input C, CE, D, S);
@@ -140,8 +277,22 @@ module FDSE (output reg Q, input C, CE, D, S);
   ) _TECHMAP_REPLACE_ (
     .D(D), .Q($nextQ), .C(C), .CE(CE), .S(S)
   );
-  wire _TECHMAP_REPLACE_.$currQ = Q;
   \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q));
+
+  // Special signal indicating clock domain
+  //   (used to partition the module so that `abc9' only performs
+  //    sequential synthesis (reachability analysis) correctly on
+  //    one domain at a time)
+  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
+  // Special signal indicating control domain
+  //   (which, combined with this spell type, encodes to `abc9'
+  //    which flops may be merged together)
+  wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, S, IS_S_INVERTED};
+  // Special signal indicating the current value of the flip-flop
+  //   In order to achieve clock-enable behaviour, the current value
+  //   of the sequential output is required which Yosys will
+  //   connect to the special `$currQ' wire.
+  wire _TECHMAP_REPLACE_.$currQ = Q;
 endmodule
 module FDSE_1 (output reg Q, input C, CE, D, S);
   parameter [0:0] INIT = 1'b0;
@@ -151,8 +302,22 @@ module FDSE_1 (output reg Q, input C, CE, D, S);
   ) _TECHMAP_REPLACE_ (
     .D(D), .Q($nextQ), .C(C), .CE(CE), .S(S)
   );
-  wire _TECHMAP_REPLACE_.$currQ = Q;
   \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q));
+
+  // Special signal indicating clock domain
+  //   (used to partition the module so that `abc9' only performs
+  //    sequential synthesis (reachability analysis) correctly on
+  //    one domain at a time)
+  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
+  // Special signal indicating control domain
+  //   (which, combined with this spell type, encodes to `abc9'
+  //    which flops may be merged together)
+  wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */};
+  // Special signal indicating the current value of the flip-flop
+  //   In order to achieve clock-enable behaviour, the current value
+  //   of the sequential output is required which Yosys will
+  //   connect to the special `$currQ' wire.
+  wire _TECHMAP_REPLACE_.$currQ = Q;
 endmodule
 
 module RAM32X1D (
diff --git a/techlibs/xilinx/abc9_model.v b/techlibs/xilinx/abc9_model.v
index 74b5cf66a..c17d6744a 100644
--- a/techlibs/xilinx/abc9_model.v
+++ b/techlibs/xilinx/abc9_model.v
@@ -30,11 +30,8 @@ module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
                 : (S0 ? I1 : I0);
 endmodule
 
-module \$__ABC_FF_ (input D, output Q);
-endmodule
-
 (* abc_box_id = 1000 *)
-module \$__ABC_ASYNC (input A, S, output Y);
+module \$__ABC9_ASYNC (input A, S, output Y);
 endmodule
 
 // Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32}
diff --git a/techlibs/xilinx/abc9_xc7.box b/techlibs/xilinx/abc9_xc7.box
index 6814b101f..24b1898a4 100644
--- a/techlibs/xilinx/abc9_xc7.box
+++ b/techlibs/xilinx/abc9_xc7.box
@@ -44,7 +44,7 @@ CARRY4 4 1 10 8
 # Box to emulate async behaviour of FD[CP]*
 # Inputs: A S
 # Outputs: Y
-$__ABC_ASYNC 1000 0 2 1
+$__ABC9_ASYNC 1000 0 2 1
 0 764
 
 # The following FD*.{CE,R,CLR,PRE) are offset by 46ps to
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 309ee500a..35d9aac96 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -258,33 +258,10 @@ module FDRE (
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_R_INVERTED = 1'b0;
   initial Q <= INIT;
-  wire \$currQ ;
-  reg \$nextQ ;
-  always @* if (R == !IS_R_INVERTED) \$nextQ = 1'b0; else if (CE) \$nextQ = D ^ IS_D_INVERTED; else \$nextQ = \$currQ ;
-`ifdef _ABC9
-  // `abc9' requires that complex flops be split into a combinatorial
-  //   box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v)
-  //   In order to achieve clock-enable behaviour, the current value
-  //   of the sequential output is required which Yosys will
-  //   connect to the special `$currQ' wire.
-
-  // Special signal indicating clock domain
-  //   (used to partition the module so that `abc9' only performs
-  //    sequential synthesis (reachability analysis) correctly on
-  //    one domain at a time)
-  wire [1:0] $abc9_clock = {C, IS_C_INVERTED};
-  // Special signal indicating control domain
-  //   (which, combined with this spell type, encodes to `abc9'
-  //    which flops may be merged together)
-  wire [3:0] $abc9_control = {CE, IS_D_INVERTED, R, IS_R_INVERTED};
-  always @* Q = \$nextQ ;
-`else
-  assign \$currQ = Q;
   generate case (|IS_C_INVERTED)
-    1'b0: always @(posedge C) Q <= \$nextQ ;
-    1'b1: always @(negedge C) Q <= \$nextQ ;
+    1'b0: always @(posedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
+    1'b1: always @(negedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
   endcase endgenerate
-`endif
 endmodule
 
 (* abc9_box_id=1002, lib_whitebox, abc9_flop *)
@@ -297,30 +274,7 @@ module FDRE_1 (
 );
   parameter [0:0] INIT = 1'b0;
   initial Q <= INIT;
-  wire \$currQ ;
-  reg \$nextQ ;
-  always @* if (R) Q <= 1'b0; else if (CE) Q <= D; else \$nextQ = \$currQ ;
-`ifdef _ABC9
-  // `abc9' requires that complex flops be split into a combinatorial
-  //   box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v)
-  //   In order to achieve clock-enable behaviour, the current value
-  //   of the sequential output is required which Yosys will
-  //   connect to the special `$currQ' wire.
-
-  // Special signal indicating clock domain
-  //   (used to partition the module so that `abc9' only performs
-  //    sequential synthesis (reachability analysis) correctly on
-  //    one domain at a time)
-  wire [1:0] $abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
-  // Special signal indicating control domain
-  //   (which, combined with this spell type, encodes to `abc9'
-  //    which flops may be merged together)
-  wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, R, 1'b0 /* IS_R_INVERTED */};
-  always @* Q = \$nextQ ;
-`else
-  assign \$currQ = Q;
-  always @(negedge C) Q <= \$nextQ ;
-`endif
+  always @(negedge C) if (R) Q <= 1'b0; else if (CE) Q <= D;
 endmodule
 
 (* abc9_box_id=1003, lib_whitebox, abc9_flop *)
@@ -341,37 +295,12 @@ module FDCE (
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_CLR_INVERTED = 1'b0;
   initial Q <= INIT;
-  wire \$currQ ;
-  reg \$nextQ ;
-  always @* if (CE) Q <= D ^ IS_D_INVERTED; else \$nextQ = \$currQ ;
-`ifdef _ABC9
-  // `abc9' requires that complex flops be split into a combinatorial
-  //   box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v)
-  //   In order to achieve clock-enable behaviour, the current value
-  //   of the sequential output is required which Yosys will
-  //   connect to the special `$currQ' wire.
-  // Since this is an async flop, async behaviour is also dealt with
-  //   using the $_ABC9_ASYNC box by abc9_map.v
-
-  // Special signal indicating clock domain
-  //   (used to partition the module so that `abc9' only performs
-  //    sequential synthesis (reachability analysis) correctly on
-  //    one domain at a time)
-  wire [1:0] $abc9_clock = {C, IS_C_INVERTED};
-  // Special signal indicating control domain
-  //   (which, combined with this spell type, encodes to `abc9'
-  //    which flops may be merged together)
-  wire [3:0] $abc9_control = {CE, IS_D_INVERTED, CLR, IS_CLR_INVERTED};
-  always @* Q = \$nextQ ;
-`else
-  assign \$currQ = Q;
   generate case ({|IS_C_INVERTED, |IS_CLR_INVERTED})
-    2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else Q <= \$nextQ ;
-    2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else Q <= \$nextQ ;
-    2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else Q <= \$nextQ ;
-    2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else Q <= \$nextQ ;
+    2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
+    2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
+    2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
+    2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
   endcase endgenerate
-`endif
 endmodule
 
 (* abc9_box_id=1004, lib_whitebox, abc9_flop *)
@@ -384,32 +313,7 @@ module FDCE_1 (
 );
   parameter [0:0] INIT = 1'b0;
   initial Q <= INIT;
-  wire \$currQ ;
-  reg \$nextQ ;
-  always @* if (CE) Q <= D; else \$nextQ = \$currQ ;
-`ifdef _ABC9
-  // `abc9' requires that complex flops be split into a combinatorial
-  //   box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v)
-  //   In order to achieve clock-enable behaviour, the current value
-  //   of the sequential output is required which Yosys will
-  //   connect to the special `$currQ' wire.
-  // Since this is an async flop, async behaviour is also dealt with
-  //   using the $_ABC9_ASYNC box by abc9_map.v
-
-  // Special signal indicating clock domain
-  //   (used to partition the module so that `abc9' only performs
-  //    sequential synthesis (reachability analysis) correctly on
-  //    one domain at a time)
-  wire [1:0] $abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
-  // Special signal indicating control domain
-  //   (which, combined with this spell type, encodes to `abc9'
-  //    which flops may be merged together)
-  wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, CLR, 1'b0 /* IS_CLR_INVERTED */};
-  always @* Q = \$nextQ ;
-`else
-  assign \$currQ = Q;
-  always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else Q <= \$nextQ ;
-`endif
+  always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
 endmodule
 
 (* abc9_box_id=1005, lib_whitebox, abc9_flop *)
@@ -430,37 +334,12 @@ module FDPE (
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_PRE_INVERTED = 1'b0;
   initial Q <= INIT;
-  wire \$currQ ;
-  reg \$nextQ ;
-  always @* if (CE) Q <= D ^ IS_D_INVERTED; else \$nextQ = \$currQ ;
-`ifdef _ABC9
-  // `abc9' requires that complex flops be split into a combinatorial
-  //   box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v)
-  //   In order to achieve clock-enable behaviour, the current value
-  //   of the sequential output is required which Yosys will
-  //   connect to the special `$currQ' wire.
-  // Since this is an async flop, async behaviour is also dealt with
-  //   using the $_ABC9_ASYNC box by abc9_map.v
-
-  // Special signal indicating clock domain
-  //   (used to partition the module so that `abc9' only performs
-  //    sequential synthesis (reachability analysis) correctly on
-  //    one domain at a time)
-  wire [1:0] $abc9_clock = {C, IS_C_INVERTED};
-  // Special signal indicating control domain
-  //   (which, combined with this spell type, encodes to `abc9'
-  //    which flops may be merged together)
-  wire [3:0] $abc9_control = {CE, IS_D_INVERTED, PRE, IS_PRE_INVERTED};
-  always @* Q = \$nextQ ;
-`else
-  assign \$currQ = Q;
   generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED})
-    2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= \$nextQ ;
-    2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= \$nextQ ;
-    2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= \$nextQ ;
-    2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= \$nextQ ;
+    2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= Q ;
+    2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= Q ;
+    2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= Q ;
+    2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= Q ;
   endcase endgenerate
-`endif
 endmodule
 
 (* abc9_box_id=1006, lib_whitebox, abc9_flop *)
@@ -473,32 +352,7 @@ module FDPE_1 (
 );
   parameter [0:0] INIT = 1'b1;
   initial Q <= INIT;
-  wire \$currQ ;
-  reg \$nextQ ;
-  always @* if (CE) Q <= D; else \$nextQ = \$currQ ;
-`ifdef _ABC9
-  // `abc9' requires that complex flops be split into a combinatorial
-  //   box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v)
-  //   In order to achieve clock-enable behaviour, the current value
-  //   of the sequential output is required which Yosys will
-  //   connect to the special `$currQ' wire.
-  // Since this is an async flop, async behaviour is also dealt with
-  //   using the $_ABC9_ASYNC box by abc9_map.v
-
-  // Special signal indicating clock domain
-  //   (used to partition the module so that `abc9' only performs
-  //    sequential synthesis (reachability analysis) correctly on
-  //    one domain at a time)
-  wire [1:0] $abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
-  // Special signal indicating control domain
-  //   (which, combined with this spell type, encodes to `abc9'
-  //    which flops may be merged together)
-  wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, PRE, 1'b0 /* IS_PRE_INVERTED */};
-  always @* Q = \$nextQ ;
-`else
-  assign \$currQ = Q;
-  always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else Q <= \$nextQ ;
-`endif
+  always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
 endmodule
 
 (* abc9_box_id=1007, lib_whitebox, abc9_flop *)
@@ -519,33 +373,10 @@ module FDSE (
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_S_INVERTED = 1'b0;
   initial Q <= INIT;
-  wire \$currQ ;
-  reg \$nextQ ;
-  always @* if (S == !IS_S_INVERTED) \$nextQ = 1'b1; else if (CE) \$nextQ = D ^ IS_D_INVERTED; else \$nextQ = \$currQ ;
-`ifdef _ABC9
-  // `abc9' requires that complex flops be split into a combinatorial
-  //   box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v)
-  //   In order to achieve clock-enable behaviour, the current value
-  //   of the sequential output is required which Yosys will
-  //   connect to the special `$currQ' wire.
-
-  // Special signal indicating clock domain
-  //   (used to partition the module so that `abc9' only performs
-  //    sequential synthesis (reachability analysis) correctly on
-  //    one domain at a time)
-  wire [1:0] $abc9_clock = {C, IS_C_INVERTED};
-  // Special signal indicating control domain
-  //   (which, combined with this spell type, encodes to `abc9'
-  //    which flops may be merged together)
-  wire [3:0] $abc9_control = {CE, IS_D_INVERTED, S, IS_S_INVERTED};
-  always @* Q = \$nextQ ;
-`else
-  assign \$currQ = Q;
   generate case (|IS_C_INVERTED)
-    1'b0: always @(posedge C) Q <= \$nextQ ;
-    1'b1: always @(negedge C) Q <= \$nextQ ;
+    1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
+    1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
   endcase endgenerate
-`endif
 endmodule
 
 (* abc9_box_id=1008, lib_whitebox, abc9_flop *)
@@ -558,30 +389,7 @@ module FDSE_1 (
 );
   parameter [0:0] INIT = 1'b1;
   initial Q <= INIT;
-  wire \$currQ ;
-  reg \$nextQ ;
-  always @* if (S) \$nextQ = 1'b1; else if (CE) \$nextQ = D; else \$nextQ = \$currQ ;
-`ifdef _ABC9
-  // `abc9' requires that complex flops be split into a combinatorial
-  //   box (this module) feeding a simple flop ($_ABC9_FF_ in abc9_map.v)
-  //   In order to achieve clock-enable behaviour, the current value
-  //   of the sequential output is required which Yosys will
-  //   connect to the special `$currQ' wire.
-
-  // Special signal indicating clock domain
-  //   (used to partition the module so that `abc9' only performs
-  //    sequential synthesis (reachability analysis) correctly on
-  //    one domain at a time)
-  wire [1:0] $abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
-  // Special signal indicating control domain
-  //   (which, combined with this spell type, encodes to `abc9'
-  //    which flops may be merged together)
-  wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */};
-  always @* Q = \$nextQ ;
-`else
-  assign \$currQ = Q;
-  always @(negedge C) Q <= \$nextQ ;
-`endif
+  always @(negedge C) if (S) Q <= 1'b1; else if (CE) Q <= D;
 endmodule
 
 module LDCE (
-- 
cgit v1.2.3


From 1dc22607c38486d9e1a2b56f749d1eca35d405d2 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 7 Oct 2019 12:21:52 -0700
Subject: Remove -D_ABC9

---
 techlibs/xilinx/synth_xilinx.cc | 2 --
 1 file changed, 2 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 07f3d9a8a..a99aef7c7 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -286,8 +286,6 @@ struct SynthXilinxPass : public ScriptPass
 			std::string read_args;
 			if (vpr)
 				read_args += " -D_EXPLICIT_CARRY";
-			if (abc9)
-				read_args += " -D_ABC9";
 			read_args += " -lib +/xilinx/cells_sim.v";
 			run("read_verilog" + read_args);
 
-- 
cgit v1.2.3


From bae3d8705d844912699b0ed502630040ce4efa85 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 7 Oct 2019 12:54:45 -0700
Subject: Update comments in abc9_map.v

---
 techlibs/xilinx/abc9_map.v | 188 ++++++++++++++-------------------------------
 1 file changed, 57 insertions(+), 131 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v
index ef7a1a09f..feaf979ad 100644
--- a/techlibs/xilinx/abc9_map.v
+++ b/techlibs/xilinx/abc9_map.v
@@ -28,12 +28,53 @@
 
 // ============================================================================
 
-// The purpose of the following FD* rules are to wrap the flop (which, when
-//   called with the `_ABC' macro set captures only its combinatorial
-//   behaviour) with:
+// `abc9' requires that complex flops be split into a combinatorial box
+//   feeding a simple flop ($_ABC9_FF_).
+// Yosys will automatically analyse the simulation model (described in
+//   cells_sim.v) and detach any $_DFF_P_ or $_DFF_N_ cells present in
+//   order to extract the combinatorial control logic left behind.
+//   Specifically, a simulation model similar to the one below:
+//
+//           ++===================================++
+//           ||                        Sim model  ||
+//           ||      /\/\/\/\                     ||
+//       D -->>-----<        >     +------+       ||
+//       R -->>-----<  Comb. >     |$_DFF_|       ||
+//      CE -->>-----<  logic >-----| [NP]_|---+---->>-- Q
+//           ||  +--<        >     +------+   |   ||
+//           ||  |   \/\/\/\/                 |   ||
+//           ||  |                            |   ||
+//           ||  +----------------------------+   ||
+//           ||                                   ||
+//           ++===================================++
+//
+//   is transformed into:
+//
+//           ++==================++
+//           ||         Comb box ||
+//           ||                  ||
+//           ||      /\/\/\/\    ||
+//      D  -->>-----<        >   ||            +------+
+//      R  -->>-----<  Comb. >   ||            |$_ABC_|
+//     CE  -->>-----<  logic >--->>-- $nextQ --|  FF_ |--+-->> Q
+// $currQ +-->>-----<        >   ||            +------+  |
+//        |  ||      \/\/\/\/    ||                      |
+//        |  ||                  ||                      |
+//        |  ++==================++                      |
+//        |                                              |
+//        +----------------------------------------------+
+//
+// The purpose of the following FD* rules are to wrap the flop with:
 // (a) a special $__ABC9_FF_ in front of the FD*'s output, indicating to abc9
 //     the connectivity of its basic D-Q flop
-// (b) a special TECHMAP_REPLACE_.$currQ wire that will be used for feedback
+// (b) a special _TECHMAP_REPLACE_.$abc9_clock wire to capture its clock
+//     domain (used when partitioning the module so that `abc9' only
+//     performs sequential synthesis (with reachability analysis) correctly on
+//     one domain at a time)
+// (c) a special _TECHMAP_REPLACE_.$abc9_control that captures the control 
+//     domain (which, combined with this cell type, encodes to `abc9' which
+//     flops may be merged together)
+// (d) a special _TECHMAP_REPLACE_.$currQ wire that will be used for feedback
 //     into the (combinatorial) FD* cell to facilitate clock-enable behaviour
 module FDRE (output reg Q, input C, CE, D, R);
   parameter [0:0] INIT = 1'b0;
@@ -49,56 +90,11 @@ module FDRE (output reg Q, input C, CE, D, R);
   ) _TECHMAP_REPLACE_ (
     .D(D), .Q($nextQ), .C(C), .CE(CE), .R(R)
   );
-  // `abc9' requires that complex flops be split into a combinatorial box
-  //   feeding a simple flop ($_ABC9_FF_).
-  // Yosys will automatically analyse the simulation model (described in
-  //   cells_sim.v) and detach any $_DFF_P_ or $_DFF_N_ cells present in
-  //   order to extract the combinatorial control logic left behind.
-  //   Specifically, a simulation model similar to the one below:
-  //
-  //           ++===================================++
-  //           ||                        Sim model  ||
-  //           ||      /\/\/\/\                     ||
-  //       D -->>-----<        >     +------+       ||
-  //       R -->>-----<  Comb. >     |$_DFF_|       ||
-  //      CE -->>-----<  logic >-----| [NP]_|---+---->>-- Q
-  //           ||  +--<        >     +------+   |   ||
-  //           ||  |   \/\/\/\/                 |   ||
-  //           ||  |                            |   ||
-  //           ||  +----------------------------+   ||
-  //           ||                                   ||
-  //           ++===================================++
-  //
-  //   is transformed into:
-  //
-  //           ++==================++
-  //           ||         Comb box ||
-  //           ||                  ||
-  //           ||      /\/\/\/\    ||
-  //      D  -->>-----<        >   ||            +------+
-  //      R  -->>-----<  Comb. >   ||            |$_ABC_|
-  //     CE  -->>-----<  logic >--->>-- $nextQ --|  FF_ |--+-->> Q
-  // $currQ +-->>-----<        >   ||            +------+  |
-  //        |  ||      \/\/\/\/    ||                      |
-  //        |  ||                  ||                      |
-  //        |  ++==================++                      |
-  //        |                                              |
-  //        +----------------------------------------------+
   \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q));
 
-  // Special signal indicating clock domain
-  //   (used to partition the module so that `abc9' only performs
-  //    sequential synthesis (reachability analysis) correctly on
-  //    one domain at a time)
+  // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
-  // Special signal indicating control domain
-  //   (which, combined with this cell type, encodes to `abc9'
-  //    which flops may be merged together)
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, R, IS_R_INVERTED};
-  // Special signal indicating the current value of the flip-flop
-  //   In order to achieve clock-enable behaviour, the current value
-  //   of the sequential output is required which Yosys will
-  //   connect to the special `$currQ' wire.
   wire _TECHMAP_REPLACE_.$currQ = Q;
 endmodule
 module FDRE_1 (output reg Q, input C, CE, D, R);
@@ -111,19 +107,9 @@ module FDRE_1 (output reg Q, input C, CE, D, R);
   );
   \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q));
 
-  // Special signal indicating clock domain
-  //   (used to partition the module so that `abc9' only performs
-  //    sequential synthesis (reachability analysis) correctly on
-  //    one domain at a time)
+  // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
-  // Special signal indicating control domain
-  //   (which, combined with this spell type, encodes to `abc9'
-  //    which flops may be merged together)
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, R, 1'b0 /* IS_R_INVERTED */};
-  // Special signal indicating the current value of the flip-flop
-  //   In order to achieve clock-enable behaviour, the current value
-  //   of the sequential output is required which Yosys will
-  //   connect to the special `$currQ' wire.
   wire _TECHMAP_REPLACE_.$currQ = Q;
 endmodule
 
@@ -142,7 +128,7 @@ module FDCE (output reg Q, input C, CE, D, CLR);
     .D(D), .Q($nextQ),  .C(C), .CE(CE), .CLR(IS_CLR_INVERTED)
                                          // ^^^ Note that async
                                          //     control is disabled
-                                         //     and captured by
+                                         //     here but captured by
                                          //     $__ABC9_ASYNC below
   );
   \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($currQ));
@@ -150,19 +136,9 @@ module FDCE (output reg Q, input C, CE, D, CLR);
   //   using the $_ABC9_ASYNC box by abc9_map.v
   \$__ABC9_ASYNC abc_async (.A($currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(Q));
 
-  // Special signal indicating clock domain
-  //   (used to partition the module so that `abc9' only performs
-  //    sequential synthesis (reachability analysis) correctly on
-  //    one domain at a time)
+  // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
-  // Special signal indicating control domain
-  //   (which, combined with this spell type, encodes to `abc9'
-  //    which flops may be merged together)
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, CLR, IS_CLR_INVERTED};
-  // Special signal indicating the current value of the flip-flop
-  //   In order to achieve clock-enable behaviour, the current value
-  //   of the sequential output is required which Yosys will
-  //   connect to the special `$currQ' wire.
   wire _TECHMAP_REPLACE_.$currQ = $currQ;
 endmodule
 module FDCE_1 (output reg Q, input C, CE, D, CLR);
@@ -174,25 +150,15 @@ module FDCE_1 (output reg Q, input C, CE, D, CLR);
     .D(D), .Q($nextQ), .C(C), .CE(CE), .CLR(1'b0)
                                          // ^^^ Note that async
                                          //     control is disabled
-                                         //     and captured by
+                                         //     here but captured by
                                          //     $__ABC9_ASYNC below
   );
   \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($currQ));
   \$__ABC9_ASYNC abc_async (.A($currQ), .S(CLR), .Y(Q));
 
-  // Special signal indicating clock domain
-  //   (used to partition the module so that `abc9' only performs
-  //    sequential synthesis (reachability analysis) correctly on
-  //    one domain at a time)
+  // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
-  // Special signal indicating control domain
-  //   (which, combined with this spell type, encodes to `abc9'
-  //    which flops may be merged together)
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, CLR, 1'b0 /* IS_CLR_INVERTED */};
-  // Special signal indicating the current value of the flip-flop
-  //   In order to achieve clock-enable behaviour, the current value
-  //   of the sequential output is required which Yosys will
-  //   connect to the special `$currQ' wire.
   wire _TECHMAP_REPLACE_.$currQ = $currQ;
 endmodule
 
@@ -211,25 +177,15 @@ module FDPE (output reg Q, input C, CE, D, PRE);
     .D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(IS_PRE_INVERTED)
                                          // ^^^ Note that async
                                          //     control is disabled
-                                         //     and captured by
+                                         //     here but captured by
                                          //     $__ABC9_ASYNC below
   );
   \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($currQ));
   \$__ABC9_ASYNC abc_async (.A($currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(Q));
 
-  // Special signal indicating clock domain
-  //   (used to partition the module so that `abc9' only performs
-  //    sequential synthesis (reachability analysis) correctly on
-  //    one domain at a time)
+  // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
-  // Special signal indicating control domain
-  //   (which, combined with this spell type, encodes to `abc9'
-  //    which flops may be merged together)
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, PRE, IS_PRE_INVERTED};
-  // Special signal indicating the current value of the flip-flop
-  //   In order to achieve clock-enable behaviour, the current value
-  //   of the sequential output is required which Yosys will
-  //   connect to the special `$currQ' wire.
   wire _TECHMAP_REPLACE_.$currQ = $currQ;
 endmodule
 module FDPE_1 (output reg Q, input C, CE, D, PRE);
@@ -241,25 +197,15 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE);
     .D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(1'b0)
                                          // ^^^ Note that async
                                          //     control is disabled
-                                         //     and captured by
+                                         //     here but captured by
                                          //     $__ABC9_ASYNC below
   );
   \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($currQ));
   \$__ABC9_ASYNC abc_async (.A($currQ), .S(PRE), .Y(Q));
 
-  // Special signal indicating clock domain
-  //   (used to partition the module so that `abc9' only performs
-  //    sequential synthesis (reachability analysis) correctly on
-  //    one domain at a time)
+  // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
-  // Special signal indicating control domain
-  //   (which, combined with this spell type, encodes to `abc9'
-  //    which flops may be merged together)
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, PRE, 1'b0 /* IS_PRE_INVERTED */};
-  // Special signal indicating the current value of the flip-flop
-  //   In order to achieve clock-enable behaviour, the current value
-  //   of the sequential output is required which Yosys will
-  //   connect to the special `$currQ' wire.
   wire _TECHMAP_REPLACE_.$currQ = $currQ;
 endmodule
 
@@ -279,19 +225,9 @@ module FDSE (output reg Q, input C, CE, D, S);
   );
   \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q));
 
-  // Special signal indicating clock domain
-  //   (used to partition the module so that `abc9' only performs
-  //    sequential synthesis (reachability analysis) correctly on
-  //    one domain at a time)
+  // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
-  // Special signal indicating control domain
-  //   (which, combined with this spell type, encodes to `abc9'
-  //    which flops may be merged together)
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, S, IS_S_INVERTED};
-  // Special signal indicating the current value of the flip-flop
-  //   In order to achieve clock-enable behaviour, the current value
-  //   of the sequential output is required which Yosys will
-  //   connect to the special `$currQ' wire.
   wire _TECHMAP_REPLACE_.$currQ = Q;
 endmodule
 module FDSE_1 (output reg Q, input C, CE, D, S);
@@ -304,19 +240,9 @@ module FDSE_1 (output reg Q, input C, CE, D, S);
   );
   \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q));
 
-  // Special signal indicating clock domain
-  //   (used to partition the module so that `abc9' only performs
-  //    sequential synthesis (reachability analysis) correctly on
-  //    one domain at a time)
+  // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
-  // Special signal indicating control domain
-  //   (which, combined with this spell type, encodes to `abc9'
-  //    which flops may be merged together)
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */};
-  // Special signal indicating the current value of the flip-flop
-  //   In order to achieve clock-enable behaviour, the current value
-  //   of the sequential output is required which Yosys will
-  //   connect to the special `$currQ' wire.
   wire _TECHMAP_REPLACE_.$currQ = Q;
 endmodule
 
-- 
cgit v1.2.3


From b2e34f932ac37e66435d413ab7a9f0074dc0343f Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 7 Oct 2019 15:31:43 -0700
Subject: Rename $currQ to $abc9_currQ

---
 techlibs/xilinx/abc9_map.v | 92 +++++++++++++++++++++++-----------------------
 1 file changed, 46 insertions(+), 46 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v
index feaf979ad..ee319a8e3 100644
--- a/techlibs/xilinx/abc9_map.v
+++ b/techlibs/xilinx/abc9_map.v
@@ -35,34 +35,34 @@
 //   order to extract the combinatorial control logic left behind.
 //   Specifically, a simulation model similar to the one below:
 //
-//           ++===================================++
-//           ||                        Sim model  ||
-//           ||      /\/\/\/\                     ||
-//       D -->>-----<        >     +------+       ||
-//       R -->>-----<  Comb. >     |$_DFF_|       ||
-//      CE -->>-----<  logic >-----| [NP]_|---+---->>-- Q
-//           ||  +--<        >     +------+   |   ||
-//           ||  |   \/\/\/\/                 |   ||
-//           ||  |                            |   ||
-//           ||  +----------------------------+   ||
-//           ||                                   ||
-//           ++===================================++
+//                ++===================================++
+//                ||                        Sim model  ||
+//                ||      /\/\/\/\                     ||
+//            D -->>-----<        >     +------+       ||
+//            R -->>-----<  Comb. >     |$_DFF_|       ||
+//           CE -->>-----<  logic >-----| [NP]_|---+---->>-- Q
+//                ||  +--<        >     +------+   |   ||
+//                ||  |   \/\/\/\/                 |   ||
+//                ||  |                            |   ||
+//                ||  +----------------------------+   ||
+//                ||                                   ||
+//                ++===================================++
 //
 //   is transformed into:
 //
-//           ++==================++
-//           ||         Comb box ||
-//           ||                  ||
-//           ||      /\/\/\/\    ||
-//      D  -->>-----<        >   ||            +------+
-//      R  -->>-----<  Comb. >   ||            |$_ABC_|
-//     CE  -->>-----<  logic >--->>-- $nextQ --|  FF_ |--+-->> Q
-// $currQ +-->>-----<        >   ||            +------+  |
-//        |  ||      \/\/\/\/    ||                      |
-//        |  ||                  ||                      |
-//        |  ++==================++                      |
-//        |                                              |
-//        +----------------------------------------------+
+//                ++==================++
+//                ||         Comb box ||
+//                ||                  ||
+//                ||      /\/\/\/\    ||
+//           D  -->>-----<        >   ||            +------+
+//           R  -->>-----<  Comb. >   ||            |$_ABC_|
+//          CE  -->>-----<  logic >--->>-- $nextQ --|  FF_ |--+-->> Q
+// $abc9_currQ +-->>-----<        >   ||            +------+  |
+//             |  ||      \/\/\/\/    ||                      |
+//             |  ||                  ||                      |
+//             |  ++==================++                      |
+//             |                                              |
+//             +----------------------------------------------+
 //
 // The purpose of the following FD* rules are to wrap the flop with:
 // (a) a special $__ABC9_FF_ in front of the FD*'s output, indicating to abc9
@@ -74,7 +74,7 @@
 // (c) a special _TECHMAP_REPLACE_.$abc9_control that captures the control 
 //     domain (which, combined with this cell type, encodes to `abc9' which
 //     flops may be merged together)
-// (d) a special _TECHMAP_REPLACE_.$currQ wire that will be used for feedback
+// (d) a special _TECHMAP_REPLACE_.$abc9_currQ wire that will be used for feedback
 //     into the (combinatorial) FD* cell to facilitate clock-enable behaviour
 module FDRE (output reg Q, input C, CE, D, R);
   parameter [0:0] INIT = 1'b0;
@@ -95,7 +95,7 @@ module FDRE (output reg Q, input C, CE, D, R);
   // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, R, IS_R_INVERTED};
-  wire _TECHMAP_REPLACE_.$currQ = Q;
+  wire _TECHMAP_REPLACE_.$abc9_currQ = Q;
 endmodule
 module FDRE_1 (output reg Q, input C, CE, D, R);
   parameter [0:0] INIT = 1'b0;
@@ -110,7 +110,7 @@ module FDRE_1 (output reg Q, input C, CE, D, R);
   // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, R, 1'b0 /* IS_R_INVERTED */};
-  wire _TECHMAP_REPLACE_.$currQ = Q;
+  wire _TECHMAP_REPLACE_.$abc9_currQ = Q;
 endmodule
 
 module FDCE (output reg Q, input C, CE, D, CLR);
@@ -118,7 +118,7 @@ module FDCE (output reg Q, input C, CE, D, CLR);
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_CLR_INVERTED = 1'b0;
-  wire $nextQ, $currQ;
+  wire $nextQ, $abc9_currQ;
   FDCE #(
     .INIT(INIT),
     .IS_C_INVERTED(IS_C_INVERTED),
@@ -131,19 +131,19 @@ module FDCE (output reg Q, input C, CE, D, CLR);
                                          //     here but captured by
                                          //     $__ABC9_ASYNC below
   );
-  \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($currQ));
+  \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ));
   // Since this is an async flop, async behaviour is also dealt with
   //   using the $_ABC9_ASYNC box by abc9_map.v
-  \$__ABC9_ASYNC abc_async (.A($currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(Q));
+  \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(Q));
 
   // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, CLR, IS_CLR_INVERTED};
-  wire _TECHMAP_REPLACE_.$currQ = $currQ;
+  wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
 endmodule
 module FDCE_1 (output reg Q, input C, CE, D, CLR);
   parameter [0:0] INIT = 1'b0;
-  wire $nextQ, $currQ;
+  wire $nextQ, $abc9_currQ;
   FDCE_1 #(
     .INIT(INIT)
   ) _TECHMAP_REPLACE_ (
@@ -153,13 +153,13 @@ module FDCE_1 (output reg Q, input C, CE, D, CLR);
                                          //     here but captured by
                                          //     $__ABC9_ASYNC below
   );
-  \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($currQ));
-  \$__ABC9_ASYNC abc_async (.A($currQ), .S(CLR), .Y(Q));
+  \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ));
+  \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(CLR), .Y(Q));
 
   // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, CLR, 1'b0 /* IS_CLR_INVERTED */};
-  wire _TECHMAP_REPLACE_.$currQ = $currQ;
+  wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
 endmodule
 
 module FDPE (output reg Q, input C, CE, D, PRE);
@@ -167,7 +167,7 @@ module FDPE (output reg Q, input C, CE, D, PRE);
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_PRE_INVERTED = 1'b0;
-  wire $nextQ, $currQ;
+  wire $nextQ, $abc9_currQ;
   FDPE #(
     .INIT(INIT),
     .IS_C_INVERTED(IS_C_INVERTED),
@@ -180,17 +180,17 @@ module FDPE (output reg Q, input C, CE, D, PRE);
                                          //     here but captured by
                                          //     $__ABC9_ASYNC below
   );
-  \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($currQ));
-  \$__ABC9_ASYNC abc_async (.A($currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(Q));
+  \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ));
+  \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(Q));
 
   // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, PRE, IS_PRE_INVERTED};
-  wire _TECHMAP_REPLACE_.$currQ = $currQ;
+  wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
 endmodule
 module FDPE_1 (output reg Q, input C, CE, D, PRE);
   parameter [0:0] INIT = 1'b0;
-  wire $nextQ, $currQ;
+  wire $nextQ, $abc9_currQ;
   FDPE_1 #(
     .INIT(INIT)
   ) _TECHMAP_REPLACE_ (
@@ -200,13 +200,13 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE);
                                          //     here but captured by
                                          //     $__ABC9_ASYNC below
   );
-  \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($currQ));
-  \$__ABC9_ASYNC abc_async (.A($currQ), .S(PRE), .Y(Q));
+  \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ));
+  \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(PRE), .Y(Q));
 
   // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, PRE, 1'b0 /* IS_PRE_INVERTED */};
-  wire _TECHMAP_REPLACE_.$currQ = $currQ;
+  wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
 endmodule
 
 module FDSE (output reg Q, input C, CE, D, S);
@@ -228,7 +228,7 @@ module FDSE (output reg Q, input C, CE, D, S);
   // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, S, IS_S_INVERTED};
-  wire _TECHMAP_REPLACE_.$currQ = Q;
+  wire _TECHMAP_REPLACE_.$abc9_currQ = Q;
 endmodule
 module FDSE_1 (output reg Q, input C, CE, D, S);
   parameter [0:0] INIT = 1'b0;
@@ -243,7 +243,7 @@ module FDSE_1 (output reg Q, input C, CE, D, S);
   // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */};
-  wire _TECHMAP_REPLACE_.$currQ = Q;
+  wire _TECHMAP_REPLACE_.$abc9_currQ = Q;
 endmodule
 
 module RAM32X1D (
-- 
cgit v1.2.3


From 4f0818275fe44c451be59235616061be8ff5e382 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 7 Oct 2019 15:58:55 -0700
Subject: Cleanup

---
 techlibs/xilinx/abc9_map.v | 9 ++-------
 1 file changed, 2 insertions(+), 7 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v
index ee319a8e3..95546db37 100644
--- a/techlibs/xilinx/abc9_map.v
+++ b/techlibs/xilinx/abc9_map.v
@@ -25,11 +25,6 @@
 // For example, (complex) flip-flops are expected to be described as an
 //   combinatorial box (containing all control logic such as clock enable
 //   or synchronous resets) followed by a basic D-Q flop.
-
-// ============================================================================
-
-// `abc9' requires that complex flops be split into a combinatorial box
-//   feeding a simple flop ($_ABC9_FF_).
 // Yosys will automatically analyse the simulation model (described in
 //   cells_sim.v) and detach any $_DFF_P_ or $_DFF_N_ cells present in
 //   order to extract the combinatorial control logic left behind.
@@ -55,8 +50,8 @@
 //                ||                  ||
 //                ||      /\/\/\/\    ||
 //           D  -->>-----<        >   ||            +------+
-//           R  -->>-----<  Comb. >   ||            |$_ABC_|
-//          CE  -->>-----<  logic >--->>-- $nextQ --|  FF_ |--+-->> Q
+//           R  -->>-----<  Comb. >   ||            |$__ABC|
+//          CE  -->>-----<  logic >--->>-- $nextQ --| _FF_ |--+-->> Q
 // $abc9_currQ +-->>-----<        >   ||            +------+  |
 //             |  ||      \/\/\/\/    ||                      |
 //             |  ||                  ||                      |
-- 
cgit v1.2.3


From 344619079d42e541fee8dc370318d9927cd6fb95 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 19 Nov 2019 16:57:07 -0800
Subject: Do not drop async control signals in abc_map.v

---
 techlibs/xilinx/abc9_map.v | 28 ++++++++++++++++------------
 1 file changed, 16 insertions(+), 12 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v
index 95546db37..fc224e832 100644
--- a/techlibs/xilinx/abc9_map.v
+++ b/techlibs/xilinx/abc9_map.v
@@ -120,10 +120,11 @@ module FDCE (output reg Q, input C, CE, D, CLR);
     .IS_D_INVERTED(IS_D_INVERTED),
     .IS_CLR_INVERTED(IS_CLR_INVERTED)
   ) _TECHMAP_REPLACE_ (
-    .D(D), .Q($nextQ),  .C(C), .CE(CE), .CLR(IS_CLR_INVERTED)
+    .D(D), .Q($nextQ),  .C(C), .CE(CE), .CLR(CLR)
                                          // ^^^ Note that async
-                                         //     control is disabled
-                                         //     here but captured by
+                                         //     control is not directly
+                                         //     supported by abc9 but its
+                                         //     behaviour is captured by
                                          //     $__ABC9_ASYNC below
   );
   \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ));
@@ -142,10 +143,11 @@ module FDCE_1 (output reg Q, input C, CE, D, CLR);
   FDCE_1 #(
     .INIT(INIT)
   ) _TECHMAP_REPLACE_ (
-    .D(D), .Q($nextQ), .C(C), .CE(CE), .CLR(1'b0)
+    .D(D), .Q($nextQ), .C(C), .CE(CE), .CLR(CLR)
                                          // ^^^ Note that async
-                                         //     control is disabled
-                                         //     here but captured by
+                                         //     control is not directly
+                                         //     supported by abc9 but its
+                                         //     behaviour is captured by
                                          //     $__ABC9_ASYNC below
   );
   \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ));
@@ -169,10 +171,11 @@ module FDPE (output reg Q, input C, CE, D, PRE);
     .IS_D_INVERTED(IS_D_INVERTED),
     .IS_PRE_INVERTED(IS_PRE_INVERTED),
   ) _TECHMAP_REPLACE_ (
-    .D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(IS_PRE_INVERTED)
+    .D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(PRE)
                                          // ^^^ Note that async
-                                         //     control is disabled
-                                         //     here but captured by
+                                         //     control is not directly
+                                         //     supported by abc9 but its
+                                         //     behaviour is captured by
                                          //     $__ABC9_ASYNC below
   );
   \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ));
@@ -189,10 +192,11 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE);
   FDPE_1 #(
     .INIT(INIT)
   ) _TECHMAP_REPLACE_ (
-    .D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(1'b0)
+    .D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(PRE)
                                          // ^^^ Note that async
-                                         //     control is disabled
-                                         //     here but captured by
+                                         //     control is not directly
+                                         //     supported by abc9 but its
+                                         //     behaviour is captured by
                                          //     $__ABC9_ASYNC below
   );
   \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ));
-- 
cgit v1.2.3


From df63d75ff35e1441360a4b28a12b32b3d00f1190 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 20 Nov 2019 11:26:59 -0800
Subject: Fix INIT values

---
 techlibs/xilinx/abc9_map.v | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v
index 95546db37..d2c0abeb6 100644
--- a/techlibs/xilinx/abc9_map.v
+++ b/techlibs/xilinx/abc9_map.v
@@ -96,7 +96,7 @@ module FDRE_1 (output reg Q, input C, CE, D, R);
   parameter [0:0] INIT = 1'b0;
   wire $nextQ;
   FDRE_1 #(
-    .INIT(|0),
+    .INIT(INIT),
   ) _TECHMAP_REPLACE_ (
     .D(D), .Q($nextQ), .C(C), .CE(CE), .R(R)
   );
@@ -205,7 +205,7 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE);
 endmodule
 
 module FDSE (output reg Q, input C, CE, D, S);
-  parameter [0:0] INIT = 1'b0;
+  parameter [0:0] INIT = 1'b1;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_S_INVERTED = 1'b0;
@@ -226,10 +226,10 @@ module FDSE (output reg Q, input C, CE, D, S);
   wire _TECHMAP_REPLACE_.$abc9_currQ = Q;
 endmodule
 module FDSE_1 (output reg Q, input C, CE, D, S);
-  parameter [0:0] INIT = 1'b0;
+  parameter [0:0] INIT = 1'b1;
   wire $nextQ;
   FDSE_1 #(
-    .INIT(|0),
+    .INIT(INIT),
   ) _TECHMAP_REPLACE_ (
     .D(D), .Q($nextQ), .C(C), .CE(CE), .S(S)
   );
-- 
cgit v1.2.3


From af3055fe8354e0a082bd8415448fcbeb5ee435f6 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 20 Nov 2019 14:30:56 -0800
Subject: Add blackbox model for $__ABC9_FF_ so that clock partitioning works

---
 techlibs/xilinx/abc9_model.v | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc9_model.v b/techlibs/xilinx/abc9_model.v
index c17d6744a..cc0e5ec41 100644
--- a/techlibs/xilinx/abc9_model.v
+++ b/techlibs/xilinx/abc9_model.v
@@ -30,6 +30,9 @@ module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
                 : (S0 ? I1 : I0);
 endmodule
 
+module \$__ABC9_FF_ (input D, output Q);
+endmodule
+
 (* abc_box_id = 1000 *)
 module \$__ABC9_ASYNC (input A, S, output Y);
 endmodule
-- 
cgit v1.2.3


From eb11c06a69c3b50e39cf363926992b40a9c440c3 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 23 Nov 2019 10:18:22 -0800
Subject: For abc9, run clkpart before ff_map and after abc9

---
 techlibs/xilinx/synth_xilinx.cc | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index b5c203d1f..7105ba429 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -513,6 +513,7 @@ struct SynthXilinxPass : public ScriptPass
 
 		if (check_label("map_ffs")) {
 			if (abc9 || help_mode) {
+				run("clkpart -set_attr clkpart 1", "('-abc9' only)");
 				run("techmap -map " + ff_map_file, "('-abc9' only)");
 			}
 		}
@@ -537,6 +538,7 @@ struct SynthXilinxPass : public ScriptPass
 				else
 					abc9_opts += " -lut +/xilinx/abc9_xc7.lut";
 				run("abc9" + abc9_opts);
+				run("clkpart -unpart clkpart");
 			}
 			else {
 				if (nowidelut)
-- 
cgit v1.2.3


From 6a2eb5d8f9286b9574647c03e2bdc8b63fccbe4d Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 25 Nov 2019 12:36:13 -0800
Subject: Special abc9_clock wire to contain only clock signal

---
 techlibs/xilinx/abc9_map.v | 22 ++++++++++------------
 1 file changed, 10 insertions(+), 12 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v
index 9913b229f..29ddf7133 100644
--- a/techlibs/xilinx/abc9_map.v
+++ b/techlibs/xilinx/abc9_map.v
@@ -62,10 +62,8 @@
 // The purpose of the following FD* rules are to wrap the flop with:
 // (a) a special $__ABC9_FF_ in front of the FD*'s output, indicating to abc9
 //     the connectivity of its basic D-Q flop
-// (b) a special _TECHMAP_REPLACE_.$abc9_clock wire to capture its clock
-//     domain (used when partitioning the module so that `abc9' only
-//     performs sequential synthesis (with reachability analysis) correctly on
-//     one domain at a time)
+// (b) a special _TECHMAP_REPLACE_.$abc9_clock wire to indicate its clock
+//     signal, used to extract the delay target
 // (c) a special _TECHMAP_REPLACE_.$abc9_control that captures the control 
 //     domain (which, combined with this cell type, encodes to `abc9' which
 //     flops may be merged together)
@@ -88,7 +86,7 @@ module FDRE (output reg Q, input C, CE, D, R);
   \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q));
 
   // Special signals
-  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, R, IS_R_INVERTED};
   wire _TECHMAP_REPLACE_.$abc9_currQ = Q;
 endmodule
@@ -103,7 +101,7 @@ module FDRE_1 (output reg Q, input C, CE, D, R);
   \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q));
 
   // Special signals
-  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, R, 1'b0 /* IS_R_INVERTED */};
   wire _TECHMAP_REPLACE_.$abc9_currQ = Q;
 endmodule
@@ -133,7 +131,7 @@ module FDCE (output reg Q, input C, CE, D, CLR);
   \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(Q));
 
   // Special signals
-  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, CLR, IS_CLR_INVERTED};
   wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
 endmodule
@@ -154,7 +152,7 @@ module FDCE_1 (output reg Q, input C, CE, D, CLR);
   \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(CLR), .Y(Q));
 
   // Special signals
-  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, CLR, 1'b0 /* IS_CLR_INVERTED */};
   wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
 endmodule
@@ -182,7 +180,7 @@ module FDPE (output reg Q, input C, CE, D, PRE);
   \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(Q));
 
   // Special signals
-  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, PRE, IS_PRE_INVERTED};
   wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
 endmodule
@@ -203,7 +201,7 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE);
   \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(PRE), .Y(Q));
 
   // Special signals
-  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, PRE, 1'b0 /* IS_PRE_INVERTED */};
   wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
 endmodule
@@ -225,7 +223,7 @@ module FDSE (output reg Q, input C, CE, D, S);
   \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q));
 
   // Special signals
-  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, S, IS_S_INVERTED};
   wire _TECHMAP_REPLACE_.$abc9_currQ = Q;
 endmodule
@@ -240,7 +238,7 @@ module FDSE_1 (output reg Q, input C, CE, D, S);
   \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q));
 
   // Special signals
-  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */};
   wire _TECHMAP_REPLACE_.$abc9_currQ = Q;
 endmodule
-- 
cgit v1.2.3


From 739f5309062f6e60809a2ebe4eda4602cca6fc41 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 26 Nov 2019 14:51:39 -0800
Subject: Move 'clean' from map_luts to finalize

---
 techlibs/xilinx/synth_xilinx.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 7105ba429..6e8ced0df 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -560,7 +560,6 @@ struct SynthXilinxPass : public ScriptPass
 			else
 				techmap_args += " -map " + ff_map_file;
 			run("techmap " + techmap_args);
-			run("clean");
 		}
 
 		if (check_label("finalize")) {
@@ -575,6 +574,7 @@ struct SynthXilinxPass : public ScriptPass
 				run("iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I A:top", "(only if '-iopad' or '-ise' and not '-noiopad')");
 			if (help_mode || ise)
 				run("extractinv -inv INV O:I", "(only if '-ise')");
+			run("clean");
 		}
 
 		if (check_label("check")) {
-- 
cgit v1.2.3


From df8dc6d1fb1f9fc47a8356b5f0bf572a1ea140d2 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 27 Nov 2019 09:10:34 -0800
Subject: ean call after abc{,9}

---
 techlibs/xilinx/synth_xilinx.cc | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 6e8ced0df..5bc55387b 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -538,6 +538,7 @@ struct SynthXilinxPass : public ScriptPass
 				else
 					abc9_opts += " -lut +/xilinx/abc9_xc7.lut";
 				run("abc9" + abc9_opts);
+				run("clean");
 				run("clkpart -unpart clkpart");
 			}
 			else {
@@ -545,8 +546,8 @@ struct SynthXilinxPass : public ScriptPass
 					run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : ""));
 				else
 					run("abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
+				run("clean");
 			}
-			run("clean");
 
 			// This shregmap call infers fixed length shift registers after abc
 			//   has performed any necessary retiming
-- 
cgit v1.2.3


From b1ab7c16c41f0a14b8b14a041367f2259b3c0e37 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 28 Nov 2019 12:59:43 -0800
Subject: clkpart -unpart into 'finalize'

---
 techlibs/xilinx/synth_xilinx.cc | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 5bc55387b..554c42d68 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -538,16 +538,14 @@ struct SynthXilinxPass : public ScriptPass
 				else
 					abc9_opts += " -lut +/xilinx/abc9_xc7.lut";
 				run("abc9" + abc9_opts);
-				run("clean");
-				run("clkpart -unpart clkpart");
 			}
 			else {
 				if (nowidelut)
 					run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : ""));
 				else
 					run("abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
-				run("clean");
 			}
+			run("clean");
 
 			// This shregmap call infers fixed length shift registers after abc
 			//   has performed any necessary retiming
@@ -564,6 +562,9 @@ struct SynthXilinxPass : public ScriptPass
 		}
 
 		if (check_label("finalize")) {
+			if (help_mode || abc9)
+				run("clkpart -unpart clkpart", "(only if 'abc9')");
+
 			bool do_iopad = iopad || (ise && !noiopad);
 			if (help_mode || !noclkbuf) {
 				if (help_mode || do_iopad)
-- 
cgit v1.2.3


From 19bfb4195818be12e6fb962de29ca32444498c22 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 2 Dec 2019 14:17:06 -0800
Subject: Add INIT value to abc9_control

---
 techlibs/xilinx/abc9_map.v | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v
index 29ddf7133..b8defcb64 100644
--- a/techlibs/xilinx/abc9_map.v
+++ b/techlibs/xilinx/abc9_map.v
@@ -87,7 +87,7 @@ module FDRE (output reg Q, input C, CE, D, R);
 
   // Special signals
   wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
-  wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, R, IS_R_INVERTED};
+  wire [4:0] _TECHMAP_REPLACE_.$abc9_control = {INIT, CE, IS_D_INVERTED, R, IS_R_INVERTED};
   wire _TECHMAP_REPLACE_.$abc9_currQ = Q;
 endmodule
 module FDRE_1 (output reg Q, input C, CE, D, R);
@@ -102,7 +102,7 @@ module FDRE_1 (output reg Q, input C, CE, D, R);
 
   // Special signals
   wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
-  wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, R, 1'b0 /* IS_R_INVERTED */};
+  wire [4:0] _TECHMAP_REPLACE_.$abc9_control = {INIT, CE, 1'b0 /* IS_D_INVERTED */, R, 1'b0 /* IS_R_INVERTED */};
   wire _TECHMAP_REPLACE_.$abc9_currQ = Q;
 endmodule
 
@@ -132,7 +132,7 @@ module FDCE (output reg Q, input C, CE, D, CLR);
 
   // Special signals
   wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
-  wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, CLR, IS_CLR_INVERTED};
+  wire [4:0] _TECHMAP_REPLACE_.$abc9_control = {INIT, CE, IS_D_INVERTED, CLR, IS_CLR_INVERTED};
   wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
 endmodule
 module FDCE_1 (output reg Q, input C, CE, D, CLR);
@@ -153,7 +153,7 @@ module FDCE_1 (output reg Q, input C, CE, D, CLR);
 
   // Special signals
   wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
-  wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, CLR, 1'b0 /* IS_CLR_INVERTED */};
+  wire [4:0] _TECHMAP_REPLACE_.$abc9_control = {INIT, CE, 1'b0 /* IS_D_INVERTED */, CLR, 1'b0 /* IS_CLR_INVERTED */};
   wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
 endmodule
 
@@ -181,7 +181,7 @@ module FDPE (output reg Q, input C, CE, D, PRE);
 
   // Special signals
   wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
-  wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, PRE, IS_PRE_INVERTED};
+  wire [4:0] _TECHMAP_REPLACE_.$abc9_control = {INIT, CE, IS_D_INVERTED, PRE, IS_PRE_INVERTED};
   wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
 endmodule
 module FDPE_1 (output reg Q, input C, CE, D, PRE);
@@ -202,7 +202,7 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE);
 
   // Special signals
   wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
-  wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, PRE, 1'b0 /* IS_PRE_INVERTED */};
+  wire [4:0] _TECHMAP_REPLACE_.$abc9_control = {INIT, CE, 1'b0 /* IS_D_INVERTED */, PRE, 1'b0 /* IS_PRE_INVERTED */};
   wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
 endmodule
 
@@ -224,7 +224,7 @@ module FDSE (output reg Q, input C, CE, D, S);
 
   // Special signals
   wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
-  wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, S, IS_S_INVERTED};
+  wire [4:0] _TECHMAP_REPLACE_.$abc9_control = {INIT, CE, IS_D_INVERTED, S, IS_S_INVERTED};
   wire _TECHMAP_REPLACE_.$abc9_currQ = Q;
 endmodule
 module FDSE_1 (output reg Q, input C, CE, D, S);
@@ -239,7 +239,7 @@ module FDSE_1 (output reg Q, input C, CE, D, S);
 
   // Special signals
   wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
-  wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */};
+  wire [4:0] _TECHMAP_REPLACE_.$abc9_control = {INIT, CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */};
   wire _TECHMAP_REPLACE_.$abc9_currQ = Q;
 endmodule
 
-- 
cgit v1.2.3


From 0add5965c7bb369bc9dd883c559bcd890d911c14 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 3 Dec 2019 14:27:45 -0800
Subject: techmap abc_unmap.v before xilinx_srl -fixed

---
 techlibs/xilinx/synth_xilinx.cc | 11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 554c42d68..3fffd81f6 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -538,6 +538,7 @@ struct SynthXilinxPass : public ScriptPass
 				else
 					abc9_opts += " -lut +/xilinx/abc9_xc7.lut";
 				run("abc9" + abc9_opts);
+				run("techmap -map +/xilinx/abc9_unmap.v");
 			}
 			else {
 				if (nowidelut)
@@ -553,12 +554,10 @@ struct SynthXilinxPass : public ScriptPass
 				run("xilinx_srl -fixed -minlen 3", "(skip if '-nosrl')");
 			std::string techmap_args = "-map +/xilinx/lut_map.v -map +/xilinx/cells_map.v";
 			if (help_mode)
-				techmap_args += " [-map " + ff_map_file + "]";
-			else if (abc9)
-				techmap_args += " -map +/xilinx/abc9_unmap.v";
-			else
-				techmap_args += " -map " + ff_map_file;
-			run("techmap " + techmap_args);
+				techmap_args += stringf("[-map %s]", ff_map_file.c_str());
+			else if (!abc9)
+				techmap_args += stringf(" -map %s", ff_map_file.c_str());
+			run("techmap " + techmap_args, "(option without '-abc9')");
 		}
 
 		if (check_label("finalize")) {
-- 
cgit v1.2.3


From f98aa1c13fdba69a2ceedd1f3b6613816c60a637 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 3 Dec 2019 15:40:44 -0800
Subject: Revert "Add INIT value to abc9_control"

This reverts commit 19bfb4195818be12e6fb962de29ca32444498c22.
---
 techlibs/xilinx/abc9_map.v | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v
index b8defcb64..29ddf7133 100644
--- a/techlibs/xilinx/abc9_map.v
+++ b/techlibs/xilinx/abc9_map.v
@@ -87,7 +87,7 @@ module FDRE (output reg Q, input C, CE, D, R);
 
   // Special signals
   wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
-  wire [4:0] _TECHMAP_REPLACE_.$abc9_control = {INIT, CE, IS_D_INVERTED, R, IS_R_INVERTED};
+  wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, R, IS_R_INVERTED};
   wire _TECHMAP_REPLACE_.$abc9_currQ = Q;
 endmodule
 module FDRE_1 (output reg Q, input C, CE, D, R);
@@ -102,7 +102,7 @@ module FDRE_1 (output reg Q, input C, CE, D, R);
 
   // Special signals
   wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
-  wire [4:0] _TECHMAP_REPLACE_.$abc9_control = {INIT, CE, 1'b0 /* IS_D_INVERTED */, R, 1'b0 /* IS_R_INVERTED */};
+  wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, R, 1'b0 /* IS_R_INVERTED */};
   wire _TECHMAP_REPLACE_.$abc9_currQ = Q;
 endmodule
 
@@ -132,7 +132,7 @@ module FDCE (output reg Q, input C, CE, D, CLR);
 
   // Special signals
   wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
-  wire [4:0] _TECHMAP_REPLACE_.$abc9_control = {INIT, CE, IS_D_INVERTED, CLR, IS_CLR_INVERTED};
+  wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, CLR, IS_CLR_INVERTED};
   wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
 endmodule
 module FDCE_1 (output reg Q, input C, CE, D, CLR);
@@ -153,7 +153,7 @@ module FDCE_1 (output reg Q, input C, CE, D, CLR);
 
   // Special signals
   wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
-  wire [4:0] _TECHMAP_REPLACE_.$abc9_control = {INIT, CE, 1'b0 /* IS_D_INVERTED */, CLR, 1'b0 /* IS_CLR_INVERTED */};
+  wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, CLR, 1'b0 /* IS_CLR_INVERTED */};
   wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
 endmodule
 
@@ -181,7 +181,7 @@ module FDPE (output reg Q, input C, CE, D, PRE);
 
   // Special signals
   wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
-  wire [4:0] _TECHMAP_REPLACE_.$abc9_control = {INIT, CE, IS_D_INVERTED, PRE, IS_PRE_INVERTED};
+  wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, PRE, IS_PRE_INVERTED};
   wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
 endmodule
 module FDPE_1 (output reg Q, input C, CE, D, PRE);
@@ -202,7 +202,7 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE);
 
   // Special signals
   wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
-  wire [4:0] _TECHMAP_REPLACE_.$abc9_control = {INIT, CE, 1'b0 /* IS_D_INVERTED */, PRE, 1'b0 /* IS_PRE_INVERTED */};
+  wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, PRE, 1'b0 /* IS_PRE_INVERTED */};
   wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
 endmodule
 
@@ -224,7 +224,7 @@ module FDSE (output reg Q, input C, CE, D, S);
 
   // Special signals
   wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
-  wire [4:0] _TECHMAP_REPLACE_.$abc9_control = {INIT, CE, IS_D_INVERTED, S, IS_S_INVERTED};
+  wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, S, IS_S_INVERTED};
   wire _TECHMAP_REPLACE_.$abc9_currQ = Q;
 endmodule
 module FDSE_1 (output reg Q, input C, CE, D, S);
@@ -239,7 +239,7 @@ module FDSE_1 (output reg Q, input C, CE, D, S);
 
   // Special signals
   wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
-  wire [4:0] _TECHMAP_REPLACE_.$abc9_control = {INIT, CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */};
+  wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */};
   wire _TECHMAP_REPLACE_.$abc9_currQ = Q;
 endmodule
 
-- 
cgit v1.2.3


From a181ff66d3094e5740b0c803e6fafa8e91bb11e5 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 3 Dec 2019 18:47:09 -0800
Subject: Add abc9_init wire, attach to abc9_flop cell

---
 techlibs/xilinx/abc9_map.v | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v
index 29ddf7133..98a4457ae 100644
--- a/techlibs/xilinx/abc9_map.v
+++ b/techlibs/xilinx/abc9_map.v
@@ -64,10 +64,12 @@
 //     the connectivity of its basic D-Q flop
 // (b) a special _TECHMAP_REPLACE_.$abc9_clock wire to indicate its clock
 //     signal, used to extract the delay target
-// (c) a special _TECHMAP_REPLACE_.$abc9_control that captures the control 
+// (c) a special _TECHMAP_REPLACE_.$abc9_control wire that captures the control
 //     domain (which, combined with this cell type, encodes to `abc9' which
 //     flops may be merged together)
-// (d) a special _TECHMAP_REPLACE_.$abc9_currQ wire that will be used for feedback
+// (d) a special _TECHMAP_REPLACE_.$abc9_init wire to encode the flop's initial
+//     state
+// (e) a special _TECHMAP_REPLACE_.$abc9_currQ wire that will be used for feedback
 //     into the (combinatorial) FD* cell to facilitate clock-enable behaviour
 module FDRE (output reg Q, input C, CE, D, R);
   parameter [0:0] INIT = 1'b0;
@@ -88,6 +90,7 @@ module FDRE (output reg Q, input C, CE, D, R);
   // Special signals
   wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, R, IS_R_INVERTED};
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_init = INIT;
   wire _TECHMAP_REPLACE_.$abc9_currQ = Q;
 endmodule
 module FDRE_1 (output reg Q, input C, CE, D, R);
@@ -103,6 +106,7 @@ module FDRE_1 (output reg Q, input C, CE, D, R);
   // Special signals
   wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, R, 1'b0 /* IS_R_INVERTED */};
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_init = INIT;
   wire _TECHMAP_REPLACE_.$abc9_currQ = Q;
 endmodule
 
@@ -133,6 +137,7 @@ module FDCE (output reg Q, input C, CE, D, CLR);
   // Special signals
   wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, CLR, IS_CLR_INVERTED};
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_init = INIT;
   wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
 endmodule
 module FDCE_1 (output reg Q, input C, CE, D, CLR);
@@ -154,6 +159,7 @@ module FDCE_1 (output reg Q, input C, CE, D, CLR);
   // Special signals
   wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, CLR, 1'b0 /* IS_CLR_INVERTED */};
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_init = INIT;
   wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
 endmodule
 
@@ -182,6 +188,7 @@ module FDPE (output reg Q, input C, CE, D, PRE);
   // Special signals
   wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, PRE, IS_PRE_INVERTED};
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_init = INIT;
   wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
 endmodule
 module FDPE_1 (output reg Q, input C, CE, D, PRE);
@@ -203,6 +210,7 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE);
   // Special signals
   wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, PRE, 1'b0 /* IS_PRE_INVERTED */};
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_init = INIT;
   wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
 endmodule
 
@@ -225,6 +233,7 @@ module FDSE (output reg Q, input C, CE, D, S);
   // Special signals
   wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, S, IS_S_INVERTED};
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_init = INIT;
   wire _TECHMAP_REPLACE_.$abc9_currQ = Q;
 endmodule
 module FDSE_1 (output reg Q, input C, CE, D, S);
@@ -240,6 +249,7 @@ module FDSE_1 (output reg Q, input C, CE, D, S);
   // Special signals
   wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */};
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_init = INIT;
   wire _TECHMAP_REPLACE_.$abc9_currQ = Q;
 endmodule
 
-- 
cgit v1.2.3


From 31ef4cc7048b9da557ee78bb791c5bb7210e9fc5 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 4 Dec 2019 16:11:02 -0800
Subject: abc9_map.v to do `zinit' and make INIT = 1'b0

---
 techlibs/xilinx/abc9_map.v | 182 ++++++++++++++++++++++++++++-----------------
 1 file changed, 112 insertions(+), 70 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v
index 98a4457ae..8939b46a0 100644
--- a/techlibs/xilinx/abc9_map.v
+++ b/techlibs/xilinx/abc9_map.v
@@ -71,43 +71,55 @@
 //     state
 // (e) a special _TECHMAP_REPLACE_.$abc9_currQ wire that will be used for feedback
 //     into the (combinatorial) FD* cell to facilitate clock-enable behaviour
+// In order to perform sequential synthesis, `abc9' also requires that
+// the initial value of all flops be zero.
 module FDRE (output reg Q, input C, CE, D, R);
   parameter [0:0] INIT = 1'b0;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_R_INVERTED = 1'b0;
-  wire $nextQ;
+  wire DD, QQ, $nextQ;
+  generate if (INIT == 1'b1)
+    assign DD = ~D, Q = ~QQ;
+  else
+    assign DD = D, Q = QQ;
+  endgenerate
   FDRE #(
-    .INIT(INIT),
+    .INIT(1'b0),
     .IS_C_INVERTED(IS_C_INVERTED),
     .IS_D_INVERTED(IS_D_INVERTED),
     .IS_R_INVERTED(IS_R_INVERTED)
   ) _TECHMAP_REPLACE_ (
-    .D(D), .Q($nextQ), .C(C), .CE(CE), .R(R)
+    .D(DD), .Q($nextQ), .C(C), .CE(CE), .R(R)
   );
-  \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q));
+  \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(QQ));
 
   // Special signals
   wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, R, IS_R_INVERTED};
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_init = INIT;
-  wire _TECHMAP_REPLACE_.$abc9_currQ = Q;
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
 endmodule
 module FDRE_1 (output reg Q, input C, CE, D, R);
   parameter [0:0] INIT = 1'b0;
-  wire $nextQ;
+  wire DD, QQ, $nextQ;
+  generate if (INIT == 1'b1)
+    assign DD = ~D, Q = ~QQ;
+  else
+    assign DD = D, Q = QQ;
+  endgenerate
   FDRE_1 #(
-    .INIT(INIT),
+    .INIT(1'b0),
   ) _TECHMAP_REPLACE_ (
-    .D(D), .Q($nextQ), .C(C), .CE(CE), .R(R)
+    .D(DD), .Q($nextQ), .C(C), .CE(CE), .R(R)
   );
-  \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q));
+  \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(QQ));
 
   // Special signals
   wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, R, 1'b0 /* IS_R_INVERTED */};
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_init = INIT;
-  wire _TECHMAP_REPLACE_.$abc9_currQ = Q;
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
 endmodule
 
 module FDCE (output reg Q, input C, CE, D, CLR);
@@ -115,103 +127,123 @@ module FDCE (output reg Q, input C, CE, D, CLR);
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_CLR_INVERTED = 1'b0;
-  wire $nextQ, $abc9_currQ;
+  wire DD, QQ, $nextQ, $abc9_currQ;
+  generate if (INIT == 1'b1)
+    assign DD = ~D, Q = ~QQ;
+  else
+    assign DD = D, Q = QQ;
+  endgenerate
   FDCE #(
-    .INIT(INIT),
+    .INIT(1'b0),
     .IS_C_INVERTED(IS_C_INVERTED),
     .IS_D_INVERTED(IS_D_INVERTED),
     .IS_CLR_INVERTED(IS_CLR_INVERTED)
   ) _TECHMAP_REPLACE_ (
-    .D(D), .Q($nextQ),  .C(C), .CE(CE), .CLR(CLR)
-                                         // ^^^ Note that async
-                                         //     control is not directly
-                                         //     supported by abc9 but its
-                                         //     behaviour is captured by
-                                         //     $__ABC9_ASYNC below
+    .D(DD), .Q($nextQ), .C(C), .CE(CE), .CLR(CLR)
+                                          // ^^^ Note that async
+                                          //     control is not directly
+                                          //     supported by abc9 but its
+                                          //     behaviour is captured by
+                                          //     $__ABC9_ASYNC below
   );
   \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ));
   // Since this is an async flop, async behaviour is also dealt with
   //   using the $_ABC9_ASYNC box by abc9_map.v
-  \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(Q));
+  \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(QQ));
 
   // Special signals
   wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, CLR, IS_CLR_INVERTED};
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_init = INIT;
-  wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
 endmodule
 module FDCE_1 (output reg Q, input C, CE, D, CLR);
   parameter [0:0] INIT = 1'b0;
-  wire $nextQ, $abc9_currQ;
+  wire DD, QQ, $nextQ, $abc9_currQ;
+  generate if (INIT == 1'b1)
+    assign DD = ~D, Q = ~QQ;
+  else
+    assign DD = D, Q = QQ;
+  endgenerate
   FDCE_1 #(
-    .INIT(INIT)
+    .INIT(1'b0)
   ) _TECHMAP_REPLACE_ (
-    .D(D), .Q($nextQ), .C(C), .CE(CE), .CLR(CLR)
-                                         // ^^^ Note that async
-                                         //     control is not directly
-                                         //     supported by abc9 but its
-                                         //     behaviour is captured by
-                                         //     $__ABC9_ASYNC below
+    .D(DD), .Q($nextQ), .C(C), .CE(CE), .CLR(CLR)
+                                          // ^^^ Note that async
+                                          //     control is not directly
+                                          //     supported by abc9 but its
+                                          //     behaviour is captured by
+                                          //     $__ABC9_ASYNC below
   );
   \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ));
-  \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(CLR), .Y(Q));
+  \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(CLR), .Y(QQ));
 
   // Special signals
   wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, CLR, 1'b0 /* IS_CLR_INVERTED */};
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_init = INIT;
-  wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
 endmodule
 
 module FDPE (output reg Q, input C, CE, D, PRE);
-  parameter [0:0] INIT = 1'b0;
+  parameter [0:0] INIT = 1'b1;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_PRE_INVERTED = 1'b0;
-  wire $nextQ, $abc9_currQ;
+  wire DD, QQ, $nextQ, $abc9_currQ;
+  generate if (INIT == 1'b1)
+    assign DD = ~D, Q = ~QQ;
+  else
+    assign DD = D, Q = QQ;
+  endgenerate
   FDPE #(
-    .INIT(INIT),
+    .INIT(1'b0),
     .IS_C_INVERTED(IS_C_INVERTED),
     .IS_D_INVERTED(IS_D_INVERTED),
     .IS_PRE_INVERTED(IS_PRE_INVERTED),
   ) _TECHMAP_REPLACE_ (
-    .D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(PRE)
-                                         // ^^^ Note that async
-                                         //     control is not directly
-                                         //     supported by abc9 but its
-                                         //     behaviour is captured by
-                                         //     $__ABC9_ASYNC below
+    .D(DD), .Q($nextQ), .C(C), .CE(CE), .PRE(PRE)
+                                          // ^^^ Note that async
+                                          //     control is not directly
+                                          //     supported by abc9 but its
+                                          //     behaviour is captured by
+                                          //     $__ABC9_ASYNC below
   );
   \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ));
-  \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(Q));
+  \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(QQ));
 
   // Special signals
   wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, PRE, IS_PRE_INVERTED};
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_init = INIT;
-  wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
 endmodule
 module FDPE_1 (output reg Q, input C, CE, D, PRE);
-  parameter [0:0] INIT = 1'b0;
-  wire $nextQ, $abc9_currQ;
+  parameter [0:0] INIT = 1'b1;
+  wire DD, QQ, $nextQ, $abc9_currQ;
+  generate if (INIT == 1'b1)
+    assign DD = ~D, Q = ~QQ;
+  else
+    assign DD = D, Q = QQ;
+  endgenerate
   FDPE_1 #(
-    .INIT(INIT)
+    .INIT(1'b0),
   ) _TECHMAP_REPLACE_ (
-    .D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(PRE)
-                                         // ^^^ Note that async
-                                         //     control is not directly
-                                         //     supported by abc9 but its
-                                         //     behaviour is captured by
-                                         //     $__ABC9_ASYNC below
+    .D(DD), .Q($nextQ), .C(C), .CE(CE), .PRE(PRE)
+                                          // ^^^ Note that async
+                                          //     control is not directly
+                                          //     supported by abc9 but its
+                                          //     behaviour is captured by
+                                          //     $__ABC9_ASYNC below
   );
   \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ));
-  \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(PRE), .Y(Q));
+  \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(PRE), .Y(QQ));
 
   // Special signals
   wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, PRE, 1'b0 /* IS_PRE_INVERTED */};
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_init = INIT;
-  wire _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
 endmodule
 
 module FDSE (output reg Q, input C, CE, D, S);
@@ -219,38 +251,48 @@ module FDSE (output reg Q, input C, CE, D, S);
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_S_INVERTED = 1'b0;
-  wire $nextQ;
+  wire DD, QQ, $nextQ;
+  generate if (INIT == 1'b1)
+    assign DD = ~D, Q = ~QQ;
+  else
+    assign DD = D, Q = QQ;
+  endgenerate
   FDSE #(
-    .INIT(INIT),
+    .INIT(1'b0),
     .IS_C_INVERTED(IS_C_INVERTED),
     .IS_D_INVERTED(IS_D_INVERTED),
     .IS_S_INVERTED(IS_S_INVERTED)
   ) _TECHMAP_REPLACE_ (
-    .D(D), .Q($nextQ), .C(C), .CE(CE), .S(S)
+    .D(DD), .Q($nextQ), .C(C), .CE(CE), .S(S)
   );
-  \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q));
+  \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(QQ));
 
   // Special signals
   wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, S, IS_S_INVERTED};
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_init = INIT;
-  wire _TECHMAP_REPLACE_.$abc9_currQ = Q;
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
 endmodule
 module FDSE_1 (output reg Q, input C, CE, D, S);
   parameter [0:0] INIT = 1'b1;
-  wire $nextQ;
+  wire DD, QQ, $nextQ;
+  generate if (INIT == 1'b1)
+    assign DD = ~D, Q = ~QQ;
+  else
+    assign DD = D, Q = QQ;
+  endgenerate
   FDSE_1 #(
-    .INIT(INIT),
+    .INIT(1'b0),
   ) _TECHMAP_REPLACE_ (
-    .D(D), .Q($nextQ), .C(C), .CE(CE), .S(S)
+    .D(DD), .Q($nextQ), .C(C), .CE(CE), .S(S)
   );
-  \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q));
+  \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(QQ));
 
   // Special signals
   wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */};
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_init = INIT;
-  wire _TECHMAP_REPLACE_.$abc9_currQ = Q;
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
 endmodule
 
 module RAM32X1D (
-- 
cgit v1.2.3


From b43986c5a1e9c41865139df9c0b5f9750c26762c Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 4 Dec 2019 16:34:34 -0800
Subject: output reg Q -> output Q to suppress warning

---
 techlibs/xilinx/abc9_map.v | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v
index 8939b46a0..d84b9a8fa 100644
--- a/techlibs/xilinx/abc9_map.v
+++ b/techlibs/xilinx/abc9_map.v
@@ -73,7 +73,7 @@
 //     into the (combinatorial) FD* cell to facilitate clock-enable behaviour
 // In order to perform sequential synthesis, `abc9' also requires that
 // the initial value of all flops be zero.
-module FDRE (output reg Q, input C, CE, D, R);
+module FDRE (output Q, input C, CE, D, R);
   parameter [0:0] INIT = 1'b0;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -100,7 +100,7 @@ module FDRE (output reg Q, input C, CE, D, R);
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
 endmodule
-module FDRE_1 (output reg Q, input C, CE, D, R);
+module FDRE_1 (output Q, input C, CE, D, R);
   parameter [0:0] INIT = 1'b0;
   wire DD, QQ, $nextQ;
   generate if (INIT == 1'b1)
@@ -122,7 +122,7 @@ module FDRE_1 (output reg Q, input C, CE, D, R);
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
 endmodule
 
-module FDCE (output reg Q, input C, CE, D, CLR);
+module FDCE (output Q, input C, CE, D, CLR);
   parameter [0:0] INIT = 1'b0;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -157,7 +157,7 @@ module FDCE (output reg Q, input C, CE, D, CLR);
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
 endmodule
-module FDCE_1 (output reg Q, input C, CE, D, CLR);
+module FDCE_1 (output Q, input C, CE, D, CLR);
   parameter [0:0] INIT = 1'b0;
   wire DD, QQ, $nextQ, $abc9_currQ;
   generate if (INIT == 1'b1)
@@ -185,7 +185,7 @@ module FDCE_1 (output reg Q, input C, CE, D, CLR);
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
 endmodule
 
-module FDPE (output reg Q, input C, CE, D, PRE);
+module FDPE (output Q, input C, CE, D, PRE);
   parameter [0:0] INIT = 1'b1;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -218,7 +218,7 @@ module FDPE (output reg Q, input C, CE, D, PRE);
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
 endmodule
-module FDPE_1 (output reg Q, input C, CE, D, PRE);
+module FDPE_1 (output Q, input C, CE, D, PRE);
   parameter [0:0] INIT = 1'b1;
   wire DD, QQ, $nextQ, $abc9_currQ;
   generate if (INIT == 1'b1)
@@ -246,7 +246,7 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE);
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
 endmodule
 
-module FDSE (output reg Q, input C, CE, D, S);
+module FDSE (output Q, input C, CE, D, S);
   parameter [0:0] INIT = 1'b1;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -273,7 +273,7 @@ module FDSE (output reg Q, input C, CE, D, S);
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
 endmodule
-module FDSE_1 (output reg Q, input C, CE, D, S);
+module FDSE_1 (output Q, input C, CE, D, S);
   parameter [0:0] INIT = 1'b1;
   wire DD, QQ, $nextQ;
   generate if (INIT == 1'b1)
-- 
cgit v1.2.3


From 258a34e6f148928e80f13416b28d6bba6988c78a Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 4 Dec 2019 20:33:24 -0800
Subject: Oh deary me

---
 techlibs/xilinx/cells_sim.v | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index d845b324f..2fda3b8fd 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -378,10 +378,10 @@ module FDPE (
   parameter [0:0] IS_PRE_INVERTED = 1'b0;
   initial Q <= INIT;
   generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED})
-    2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= Q ;
-    2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= Q ;
-    2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= Q ;
-    2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= Q ;
+    2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
+    2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
+    2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
+    2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
   endcase endgenerate
 endmodule
 
-- 
cgit v1.2.3


From 19bc429482418aa42861ca0f195d86bc9577e320 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 4 Dec 2019 21:36:41 -0800
Subject: abc9_map.v to transform INIT=1 to INIT=0

---
 techlibs/xilinx/abc9_map.v | 319 ++++++++++++++++++++++++++++-----------------
 1 file changed, 201 insertions(+), 118 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v
index d84b9a8fa..3fa5f5a1c 100644
--- a/techlibs/xilinx/abc9_map.v
+++ b/techlibs/xilinx/abc9_map.v
@@ -71,27 +71,39 @@
 //     state
 // (e) a special _TECHMAP_REPLACE_.$abc9_currQ wire that will be used for feedback
 //     into the (combinatorial) FD* cell to facilitate clock-enable behaviour
+//
 // In order to perform sequential synthesis, `abc9' also requires that
 // the initial value of all flops be zero.
+
 module FDRE (output Q, input C, CE, D, R);
   parameter [0:0] INIT = 1'b0;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_R_INVERTED = 1'b0;
-  wire DD, QQ, $nextQ;
-  generate if (INIT == 1'b1)
-    assign DD = ~D, Q = ~QQ;
-  else
-    assign DD = D, Q = QQ;
+  wire QQ, $nextQ;
+  generate if (INIT == 1'b1) begin
+    assign Q = ~QQ;
+    FDSE #(
+      .INIT(1'b0),
+      .IS_C_INVERTED(IS_C_INVERTED),
+      .IS_D_INVERTED(IS_D_INVERTED),
+      .IS_S_INVERTED(IS_R_INVERTED)
+    ) _TECHMAP_REPLACE_ (
+      .D(~D), .Q($nextQ), .C(C), .CE(CE), .S(R)
+    );
+  end
+  else begin
+    assign Q = QQ;
+    FDRE #(
+      .INIT(1'b0),
+      .IS_C_INVERTED(IS_C_INVERTED),
+      .IS_D_INVERTED(IS_D_INVERTED),
+      .IS_R_INVERTED(IS_R_INVERTED)
+    ) _TECHMAP_REPLACE_ (
+      .D(D), .Q($nextQ), .C(C), .CE(CE), .R(R)
+    );
+  end
   endgenerate
-  FDRE #(
-    .INIT(1'b0),
-    .IS_C_INVERTED(IS_C_INVERTED),
-    .IS_D_INVERTED(IS_D_INVERTED),
-    .IS_R_INVERTED(IS_R_INVERTED)
-  ) _TECHMAP_REPLACE_ (
-    .D(DD), .Q($nextQ), .C(C), .CE(CE), .R(R)
-  );
   \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(QQ));
 
   // Special signals
@@ -102,17 +114,24 @@ module FDRE (output Q, input C, CE, D, R);
 endmodule
 module FDRE_1 (output Q, input C, CE, D, R);
   parameter [0:0] INIT = 1'b0;
-  wire DD, QQ, $nextQ;
-  generate if (INIT == 1'b1)
-    assign DD = ~D, Q = ~QQ;
-  else
-    assign DD = D, Q = QQ;
+  wire QQ, $nextQ;
+  generate if (INIT == 1'b1) begin
+    assign Q = ~QQ;
+    FDSE_1 #(
+      .INIT(1'b0)
+    ) _TECHMAP_REPLACE_ (
+      .D(~D), .Q($nextQ), .C(C), .CE(CE), .S(R)
+    );
+  end
+  else begin
+    assign Q = QQ;
+    FDRE_1 #(
+      .INIT(1'b0)
+    ) _TECHMAP_REPLACE_ (
+      .D(D), .Q($nextQ), .C(C), .CE(CE), .R(R)
+    );
+  end
   endgenerate
-  FDRE_1 #(
-    .INIT(1'b0),
-  ) _TECHMAP_REPLACE_ (
-    .D(DD), .Q($nextQ), .C(C), .CE(CE), .R(R)
-  );
   \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(QQ));
 
   // Special signals
@@ -127,25 +146,39 @@ module FDCE (output Q, input C, CE, D, CLR);
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_CLR_INVERTED = 1'b0;
-  wire DD, QQ, $nextQ, $abc9_currQ;
-  generate if (INIT == 1'b1)
-    assign DD = ~D, Q = ~QQ;
-  else
-    assign DD = D, Q = QQ;
-  endgenerate
-  FDCE #(
-    .INIT(1'b0),
-    .IS_C_INVERTED(IS_C_INVERTED),
-    .IS_D_INVERTED(IS_D_INVERTED),
-    .IS_CLR_INVERTED(IS_CLR_INVERTED)
-  ) _TECHMAP_REPLACE_ (
-    .D(DD), .Q($nextQ), .C(C), .CE(CE), .CLR(CLR)
-                                          // ^^^ Note that async
-                                          //     control is not directly
-                                          //     supported by abc9 but its
-                                          //     behaviour is captured by
-                                          //     $__ABC9_ASYNC below
-  );
+  wire QQ, $nextQ, $abc9_currQ;
+  generate if (INIT == 1'b1) begin
+    assign Q = ~QQ;
+    FDPE #(
+      .INIT(1'b0),
+      .IS_C_INVERTED(IS_C_INVERTED),
+      .IS_D_INVERTED(IS_D_INVERTED),
+      .IS_PRE_INVERTED(IS_CLR_INVERTED)
+    ) _TECHMAP_REPLACE_ (
+      .D(~D), .Q($nextQ), .C(C), .CE(CE), .PRE(CLR)
+                                            // ^^^ Note that async
+                                            //     control is not directly
+                                            //     supported by abc9 but its
+                                            //     behaviour is captured by
+                                            //     $__ABC9_ASYNC below
+    );
+  end
+  else begin
+    assign Q = QQ;
+    FDCE #(
+      .INIT(1'b0),
+      .IS_C_INVERTED(IS_C_INVERTED),
+      .IS_D_INVERTED(IS_D_INVERTED),
+      .IS_CLR_INVERTED(IS_CLR_INVERTED)
+    ) _TECHMAP_REPLACE_ (
+      .D(D), .Q($nextQ), .C(C), .CE(CE), .CLR(CLR)
+                                           // ^^^ Note that async
+                                           //     control is not directly
+                                           //     supported by abc9 but its
+                                           //     behaviour is captured by
+                                           //     $__ABC9_ASYNC below
+    );
+  end endgenerate
   \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ));
   // Since this is an async flop, async behaviour is also dealt with
   //   using the $_ABC9_ASYNC box by abc9_map.v
@@ -159,22 +192,32 @@ module FDCE (output Q, input C, CE, D, CLR);
 endmodule
 module FDCE_1 (output Q, input C, CE, D, CLR);
   parameter [0:0] INIT = 1'b0;
-  wire DD, QQ, $nextQ, $abc9_currQ;
-  generate if (INIT == 1'b1)
-    assign DD = ~D, Q = ~QQ;
-  else
-    assign DD = D, Q = QQ;
-  endgenerate
-  FDCE_1 #(
-    .INIT(1'b0)
-  ) _TECHMAP_REPLACE_ (
-    .D(DD), .Q($nextQ), .C(C), .CE(CE), .CLR(CLR)
-                                          // ^^^ Note that async
-                                          //     control is not directly
-                                          //     supported by abc9 but its
-                                          //     behaviour is captured by
-                                          //     $__ABC9_ASYNC below
-  );
+  generate if (INIT == 1'b1) begin
+    assign Q = ~QQ;
+    FDPE_1 #(
+      .INIT(1'b0)
+    ) _TECHMAP_REPLACE_ (
+      .D(~D), .Q($nextQ), .C(C), .CE(CE), .PRE(CLR)
+                                            // ^^^ Note that async
+                                            //     control is not directly
+                                            //     supported by abc9 but its
+                                            //     behaviour is captured by
+                                            //     $__ABC9_ASYNC below
+    );
+  end
+  else begin
+    assign Q = QQ;
+    FDCE_1 #(
+      .INIT(1'b0)
+    ) _TECHMAP_REPLACE_ (
+      .D(D), .Q($nextQ), .C(C), .CE(CE), .CLR(CLR)
+                                           // ^^^ Note that async
+                                           //     control is not directly
+                                           //     supported by abc9 but its
+                                           //     behaviour is captured by
+                                           //     $__ABC9_ASYNC below
+    );
+  end endgenerate
   \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ));
   \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(CLR), .Y(QQ));
 
@@ -190,25 +233,39 @@ module FDPE (output Q, input C, CE, D, PRE);
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_PRE_INVERTED = 1'b0;
-  wire DD, QQ, $nextQ, $abc9_currQ;
-  generate if (INIT == 1'b1)
-    assign DD = ~D, Q = ~QQ;
-  else
-    assign DD = D, Q = QQ;
-  endgenerate
-  FDPE #(
-    .INIT(1'b0),
-    .IS_C_INVERTED(IS_C_INVERTED),
-    .IS_D_INVERTED(IS_D_INVERTED),
-    .IS_PRE_INVERTED(IS_PRE_INVERTED),
-  ) _TECHMAP_REPLACE_ (
-    .D(DD), .Q($nextQ), .C(C), .CE(CE), .PRE(PRE)
-                                          // ^^^ Note that async
-                                          //     control is not directly
-                                          //     supported by abc9 but its
-                                          //     behaviour is captured by
-                                          //     $__ABC9_ASYNC below
-  );
+  wire QQ, $nextQ, $abc9_currQ;
+  generate if (INIT == 1'b1) begin
+    assign Q = ~QQ;
+    FDCE #(
+      .INIT(1'b0),
+      .IS_C_INVERTED(IS_C_INVERTED),
+      .IS_D_INVERTED(IS_D_INVERTED),
+      .IS_CLR_INVERTED(IS_PRE_INVERTED),
+    ) _TECHMAP_REPLACE_ (
+      .D(~D), .Q($nextQ), .C(C), .CE(CE), .CLR(PRE)
+                                            // ^^^ Note that async
+                                            //     control is not directly
+                                            //     supported by abc9 but its
+                                            //     behaviour is captured by
+                                            //     $__ABC9_ASYNC below
+    );
+  end
+  else begin
+    assign Q = QQ;
+    FDPE #(
+      .INIT(1'b0),
+      .IS_C_INVERTED(IS_C_INVERTED),
+      .IS_D_INVERTED(IS_D_INVERTED),
+      .IS_PRE_INVERTED(IS_PRE_INVERTED),
+    ) _TECHMAP_REPLACE_ (
+      .D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(PRE)
+                                           // ^^^ Note that async
+                                           //     control is not directly
+                                           //     supported by abc9 but its
+                                           //     behaviour is captured by
+                                           //     $__ABC9_ASYNC below
+    );
+  end endgenerate
   \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ));
   \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(QQ));
 
@@ -220,22 +277,33 @@ module FDPE (output Q, input C, CE, D, PRE);
 endmodule
 module FDPE_1 (output Q, input C, CE, D, PRE);
   parameter [0:0] INIT = 1'b1;
-  wire DD, QQ, $nextQ, $abc9_currQ;
-  generate if (INIT == 1'b1)
-    assign DD = ~D, Q = ~QQ;
-  else
-    assign DD = D, Q = QQ;
-  endgenerate
-  FDPE_1 #(
-    .INIT(1'b0),
-  ) _TECHMAP_REPLACE_ (
-    .D(DD), .Q($nextQ), .C(C), .CE(CE), .PRE(PRE)
-                                          // ^^^ Note that async
-                                          //     control is not directly
-                                          //     supported by abc9 but its
-                                          //     behaviour is captured by
-                                          //     $__ABC9_ASYNC below
-  );
+  wire QQ, $nextQ, $abc9_currQ;
+  generate if (INIT == 1'b1) begin
+    assign Q = ~QQ;
+    FDCE_1 #(
+      .INIT(1'b0)
+    ) _TECHMAP_REPLACE_ (
+      .D(~D), .Q($nextQ), .C(C), .CE(CE), .CLR(PRE)
+                                            // ^^^ Note that async
+                                            //     control is not directly
+                                            //     supported by abc9 but its
+                                            //     behaviour is captured by
+                                            //     $__ABC9_ASYNC below
+    );
+  end
+  else begin
+    assign Q = QQ;
+    FDPE_1 #(
+      .INIT(1'b0)
+    ) _TECHMAP_REPLACE_ (
+      .D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(PRE)
+                                           // ^^^ Note that async
+                                           //     control is not directly
+                                           //     supported by abc9 but its
+                                           //     behaviour is captured by
+                                           //     $__ABC9_ASYNC below
+    );
+  end endgenerate
   \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ));
   \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(PRE), .Y(QQ));
 
@@ -251,20 +319,29 @@ module FDSE (output Q, input C, CE, D, S);
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_S_INVERTED = 1'b0;
-  wire DD, QQ, $nextQ;
-  generate if (INIT == 1'b1)
-    assign DD = ~D, Q = ~QQ;
-  else
-    assign DD = D, Q = QQ;
-  endgenerate
-  FDSE #(
-    .INIT(1'b0),
-    .IS_C_INVERTED(IS_C_INVERTED),
-    .IS_D_INVERTED(IS_D_INVERTED),
-    .IS_S_INVERTED(IS_S_INVERTED)
-  ) _TECHMAP_REPLACE_ (
-    .D(DD), .Q($nextQ), .C(C), .CE(CE), .S(S)
-  );
+  wire QQ, $nextQ;
+  generate if (INIT == 1'b1) begin
+    assign Q = ~QQ;
+    FDRE #(
+      .INIT(1'b0),
+      .IS_C_INVERTED(IS_C_INVERTED),
+      .IS_D_INVERTED(IS_D_INVERTED),
+      .IS_R_INVERTED(IS_S_INVERTED)
+    ) _TECHMAP_REPLACE_ (
+      .D(~D), .Q($nextQ), .C(C), .CE(CE), .R(S)
+    );
+  end
+  else begin
+    assign Q = QQ;
+    FDSE #(
+      .INIT(1'b0),
+      .IS_C_INVERTED(IS_C_INVERTED),
+      .IS_D_INVERTED(IS_D_INVERTED),
+      .IS_S_INVERTED(IS_S_INVERTED)
+    ) _TECHMAP_REPLACE_ (
+      .D(D), .Q($nextQ), .C(C), .CE(CE), .S(S)
+    );
+  end endgenerate
   \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(QQ));
 
   // Special signals
@@ -275,17 +352,23 @@ module FDSE (output Q, input C, CE, D, S);
 endmodule
 module FDSE_1 (output Q, input C, CE, D, S);
   parameter [0:0] INIT = 1'b1;
-  wire DD, QQ, $nextQ;
-  generate if (INIT == 1'b1)
-    assign DD = ~D, Q = ~QQ;
-  else
-    assign DD = D, Q = QQ;
-  endgenerate
-  FDSE_1 #(
-    .INIT(1'b0),
-  ) _TECHMAP_REPLACE_ (
-    .D(DD), .Q($nextQ), .C(C), .CE(CE), .S(S)
-  );
+  wire QQ, $nextQ;
+  generate if (INIT == 1'b1) begin
+    assign Q = ~QQ;
+    FDRE_1 #(
+      .INIT(1'b0)
+    ) _TECHMAP_REPLACE_ (
+      .D(~D), .Q($nextQ), .C(C), .CE(CE), .R(S)
+    );
+  end
+  else begin
+    assign Q = QQ;
+    FDSE_1 #(
+      .INIT(1'b0)
+    ) _TECHMAP_REPLACE_ (
+      .D(D), .Q($nextQ), .C(C), .CE(CE), .S(S)
+    );
+  end endgenerate
   \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(QQ));
 
   // Special signals
-- 
cgit v1.2.3


From 0d248dd7bae707505071b309b55bac75facccab8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 4 Dec 2019 23:04:40 -0800
Subject: Missing wire declaration

---
 techlibs/xilinx/abc9_map.v | 1 +
 1 file changed, 1 insertion(+)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v
index 3fa5f5a1c..d2159f82d 100644
--- a/techlibs/xilinx/abc9_map.v
+++ b/techlibs/xilinx/abc9_map.v
@@ -192,6 +192,7 @@ module FDCE (output Q, input C, CE, D, CLR);
 endmodule
 module FDCE_1 (output Q, input C, CE, D, CLR);
   parameter [0:0] INIT = 1'b0;
+  wire QQ, $nextQ, $abc9_currQ;
   generate if (INIT == 1'b1) begin
     assign Q = ~QQ;
     FDPE_1 #(
-- 
cgit v1.2.3


From 864bff14f11fc67bac40f77e5bf17c7fc61ad9f6 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 5 Dec 2019 11:11:53 -0800
Subject: Revert "Special abc9_clock wire to contain only clock signal"

This reverts commit 6a2eb5d8f9286b9574647c03e2bdc8b63fccbe4d.
---
 techlibs/xilinx/abc9_map.v | 22 ++++++++++++----------
 1 file changed, 12 insertions(+), 10 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v
index d2159f82d..4d76a5232 100644
--- a/techlibs/xilinx/abc9_map.v
+++ b/techlibs/xilinx/abc9_map.v
@@ -62,8 +62,10 @@
 // The purpose of the following FD* rules are to wrap the flop with:
 // (a) a special $__ABC9_FF_ in front of the FD*'s output, indicating to abc9
 //     the connectivity of its basic D-Q flop
-// (b) a special _TECHMAP_REPLACE_.$abc9_clock wire to indicate its clock
-//     signal, used to extract the delay target
+// (b) a special _TECHMAP_REPLACE_.$abc9_clock wire to capture its clock
+//     domain (used when partitioning the module so that `abc9' only
+//     performs sequential synthesis (with reachability analysis) correctly on
+//     one domain at a time) and used to infert the delay target
 // (c) a special _TECHMAP_REPLACE_.$abc9_control wire that captures the control
 //     domain (which, combined with this cell type, encodes to `abc9' which
 //     flops may be merged together)
@@ -107,7 +109,7 @@ module FDRE (output Q, input C, CE, D, R);
   \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(QQ));
 
   // Special signals
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
+  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, R, IS_R_INVERTED};
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
@@ -135,7 +137,7 @@ module FDRE_1 (output Q, input C, CE, D, R);
   \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(QQ));
 
   // Special signals
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
+  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, R, 1'b0 /* IS_R_INVERTED */};
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
@@ -185,7 +187,7 @@ module FDCE (output Q, input C, CE, D, CLR);
   \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(QQ));
 
   // Special signals
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
+  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, CLR, IS_CLR_INVERTED};
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
@@ -223,7 +225,7 @@ module FDCE_1 (output Q, input C, CE, D, CLR);
   \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(CLR), .Y(QQ));
 
   // Special signals
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
+  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, CLR, 1'b0 /* IS_CLR_INVERTED */};
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
@@ -271,7 +273,7 @@ module FDPE (output Q, input C, CE, D, PRE);
   \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(QQ));
 
   // Special signals
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
+  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, PRE, IS_PRE_INVERTED};
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
@@ -309,7 +311,7 @@ module FDPE_1 (output Q, input C, CE, D, PRE);
   \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(PRE), .Y(QQ));
 
   // Special signals
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
+  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, PRE, 1'b0 /* IS_PRE_INVERTED */};
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
@@ -346,7 +348,7 @@ module FDSE (output Q, input C, CE, D, S);
   \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(QQ));
 
   // Special signals
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
+  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, S, IS_S_INVERTED};
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
@@ -373,7 +375,7 @@ module FDSE_1 (output Q, input C, CE, D, S);
   \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(QQ));
 
   // Special signals
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_clock = C;
+  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
   wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */};
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
-- 
cgit v1.2.3


From 02786b0aa0eb45a53b92b86b192d5ae5846366bd Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 5 Dec 2019 17:25:26 -0800
Subject: Remove clkpart

---
 techlibs/xilinx/synth_xilinx.cc | 4 ----
 1 file changed, 4 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 3fffd81f6..30be9832c 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -513,7 +513,6 @@ struct SynthXilinxPass : public ScriptPass
 
 		if (check_label("map_ffs")) {
 			if (abc9 || help_mode) {
-				run("clkpart -set_attr clkpart 1", "('-abc9' only)");
 				run("techmap -map " + ff_map_file, "('-abc9' only)");
 			}
 		}
@@ -561,9 +560,6 @@ struct SynthXilinxPass : public ScriptPass
 		}
 
 		if (check_label("finalize")) {
-			if (help_mode || abc9)
-				run("clkpart -unpart clkpart", "(only if 'abc9')");
-
 			bool do_iopad = iopad || (ise && !noiopad);
 			if (help_mode || !noclkbuf) {
 				if (help_mode || do_iopad)
-- 
cgit v1.2.3


From ec0acc9f85af0d21ea722375788b372cc416f173 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 5 Dec 2019 23:18:27 -0800
Subject: abc9 to use mergeability class to differentiate sync/async

---
 techlibs/xilinx/abc9_map.v | 27 +++++++++++++++------------
 1 file changed, 15 insertions(+), 12 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v
index 4d76a5232..d5d5a89f6 100644
--- a/techlibs/xilinx/abc9_map.v
+++ b/techlibs/xilinx/abc9_map.v
@@ -62,16 +62,18 @@
 // The purpose of the following FD* rules are to wrap the flop with:
 // (a) a special $__ABC9_FF_ in front of the FD*'s output, indicating to abc9
 //     the connectivity of its basic D-Q flop
-// (b) a special _TECHMAP_REPLACE_.$abc9_clock wire to capture its clock
+// (b) an optional $__ABC9_ASYNC_ cell in front of $__ABC_FF_'s output to
+//     capture asynchronous behaviour
+// (c) a special _TECHMAP_REPLACE_.$abc9_clock wire to capture its clock
 //     domain (used when partitioning the module so that `abc9' only
 //     performs sequential synthesis (with reachability analysis) correctly on
 //     one domain at a time) and used to infert the delay target
-// (c) a special _TECHMAP_REPLACE_.$abc9_control wire that captures the control
+// (d) a special _TECHMAP_REPLACE_.$abc9_control wire that captures the control
 //     domain (which, combined with this cell type, encodes to `abc9' which
 //     flops may be merged together)
-// (d) a special _TECHMAP_REPLACE_.$abc9_init wire to encode the flop's initial
+// (e) a special _TECHMAP_REPLACE_.$abc9_init wire to encode the flop's initial
 //     state
-// (e) a special _TECHMAP_REPLACE_.$abc9_currQ wire that will be used for feedback
+// (f) a special _TECHMAP_REPLACE_.$abc9_currQ wire that will be used for feedback
 //     into the (combinatorial) FD* cell to facilitate clock-enable behaviour
 //
 // In order to perform sequential synthesis, `abc9' also requires that
@@ -110,7 +112,7 @@ module FDRE (output Q, input C, CE, D, R);
 
   // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
-  wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, R, IS_R_INVERTED};
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_control = {1'b0 /* async */};
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
 endmodule
@@ -138,7 +140,7 @@ module FDRE_1 (output Q, input C, CE, D, R);
 
   // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
-  wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, R, 1'b0 /* IS_R_INVERTED */};
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_control = {1'b1 /* async */};
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
 endmodule
@@ -188,7 +190,7 @@ module FDCE (output Q, input C, CE, D, CLR);
 
   // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
-  wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, CLR, IS_CLR_INVERTED};
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_control = {1'b1 /* async */};
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
 endmodule
@@ -226,7 +228,7 @@ module FDCE_1 (output Q, input C, CE, D, CLR);
 
   // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
-  wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, CLR, 1'b0 /* IS_CLR_INVERTED */};
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_control = {1'b1 /* async */};
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
 endmodule
@@ -274,7 +276,7 @@ module FDPE (output Q, input C, CE, D, PRE);
 
   // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
-  wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, PRE, IS_PRE_INVERTED};
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_control = {1'b1 /* async */};
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
 endmodule
@@ -312,7 +314,8 @@ module FDPE_1 (output Q, input C, CE, D, PRE);
 
   // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
-  wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, PRE, 1'b0 /* IS_PRE_INVERTED */};
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_control = {1'b1 /* async */};
+>>>>>>> d3b23690... abc9 to use mergeability class to differentiate sync/async
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
 endmodule
@@ -349,7 +352,7 @@ module FDSE (output Q, input C, CE, D, S);
 
   // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
-  wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, IS_D_INVERTED, S, IS_S_INVERTED};
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_control = {1'b0 /* async */};
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
 endmodule
@@ -376,7 +379,7 @@ module FDSE_1 (output Q, input C, CE, D, S);
 
   // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
-  wire [3:0] _TECHMAP_REPLACE_.$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */};
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_control = {1'b0 /* async */};
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
 endmodule
-- 
cgit v1.2.3


From c767525441ebc6a21b29bf0c1208049cd38adc8e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 6 Dec 2019 16:23:09 -0800
Subject: Remove creation of $abc9_control_wire

---
 techlibs/xilinx/abc9_map.v | 22 ++++++----------------
 1 file changed, 6 insertions(+), 16 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v
index d5d5a89f6..49000ea25 100644
--- a/techlibs/xilinx/abc9_map.v
+++ b/techlibs/xilinx/abc9_map.v
@@ -65,15 +65,14 @@
 // (b) an optional $__ABC9_ASYNC_ cell in front of $__ABC_FF_'s output to
 //     capture asynchronous behaviour
 // (c) a special _TECHMAP_REPLACE_.$abc9_clock wire to capture its clock
-//     domain (used when partitioning the module so that `abc9' only
+//     domain and polarity (used when partitioning the module so that `abc9' only
 //     performs sequential synthesis (with reachability analysis) correctly on
-//     one domain at a time) and used to infert the delay target
-// (d) a special _TECHMAP_REPLACE_.$abc9_control wire that captures the control
-//     domain (which, combined with this cell type, encodes to `abc9' which
-//     flops may be merged together)
-// (e) a special _TECHMAP_REPLACE_.$abc9_init wire to encode the flop's initial
+//     one domain at a time) and also used to infer the optional delay target
+//     from the (* abc9_clock_period = %d *) attribute attached to any wire
+//     within
+// (d) a special _TECHMAP_REPLACE_.$abc9_init wire to encode the flop's initial
 //     state
-// (f) a special _TECHMAP_REPLACE_.$abc9_currQ wire that will be used for feedback
+// (e) a special _TECHMAP_REPLACE_.$abc9_currQ wire that will be used for feedback
 //     into the (combinatorial) FD* cell to facilitate clock-enable behaviour
 //
 // In order to perform sequential synthesis, `abc9' also requires that
@@ -112,7 +111,6 @@ module FDRE (output Q, input C, CE, D, R);
 
   // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_control = {1'b0 /* async */};
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
 endmodule
@@ -140,7 +138,6 @@ module FDRE_1 (output Q, input C, CE, D, R);
 
   // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_control = {1'b1 /* async */};
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
 endmodule
@@ -190,7 +187,6 @@ module FDCE (output Q, input C, CE, D, CLR);
 
   // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_control = {1'b1 /* async */};
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
 endmodule
@@ -228,7 +224,6 @@ module FDCE_1 (output Q, input C, CE, D, CLR);
 
   // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_control = {1'b1 /* async */};
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
 endmodule
@@ -276,7 +271,6 @@ module FDPE (output Q, input C, CE, D, PRE);
 
   // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_control = {1'b1 /* async */};
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
 endmodule
@@ -314,8 +308,6 @@ module FDPE_1 (output Q, input C, CE, D, PRE);
 
   // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_control = {1'b1 /* async */};
->>>>>>> d3b23690... abc9 to use mergeability class to differentiate sync/async
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
 endmodule
@@ -352,7 +344,6 @@ module FDSE (output Q, input C, CE, D, S);
 
   // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_control = {1'b0 /* async */};
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
 endmodule
@@ -379,7 +370,6 @@ module FDSE_1 (output Q, input C, CE, D, S);
 
   // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_control = {1'b0 /* async */};
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
 endmodule
-- 
cgit v1.2.3


From 49c2e59b2a4fce770bdaa74177adff0ee995f90d Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 9 Dec 2019 15:44:19 -0800
Subject: Fix comment

---
 techlibs/xilinx/abc9_xc7.box | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc9_xc7.box b/techlibs/xilinx/abc9_xc7.box
index 24b1898a4..4e632c0fa 100644
--- a/techlibs/xilinx/abc9_xc7.box
+++ b/techlibs/xilinx/abc9_xc7.box
@@ -107,7 +107,7 @@ $__ABC9_LUT6 2000 0 7 1
 # SLICEM/A6LUT + F7BMUX
 # Box to emulate comb/seq behaviour of RAMD128
 # Inputs: A S0 S1 S2 S3 S4 S5 S6
-# Outputs: DPO SPO
+# Outputs: Y
 $__ABC9_LUT7 2001 0 8 1
 0 1047 1036 877 812 643 532 478
 
-- 
cgit v1.2.3


From 3eed8835b5911c4c635e0cade0978987c09c7ab5 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 12 Dec 2019 14:56:15 -0800
Subject: abc9_map.v: fix Xilinx LUTRAM

---
 techlibs/xilinx/abc9_map.v | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v
index 49000ea25..d04cdb5eb 100644
--- a/techlibs/xilinx/abc9_map.v
+++ b/techlibs/xilinx/abc9_map.v
@@ -393,8 +393,8 @@ module RAM32X1D (
     .A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4),
     .DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4)
   );
-  \$__ABC9_LUT6 dpo (.A(\$DPO ), .S({1'b0, A0, A1, A2, A3, A4}), .Y(DPO));
-  \$__ABC9_LUT6 spo (.A(\$SPO ), .S({1'b0, A0, A1, A2, A3, A4}), .Y(SPO));
+  \$__ABC9_LUT6 spo (.A(\$SPO ), .S({1'b1, A4, A3, A2, A1, A0}), .Y(SPO));
+  \$__ABC9_LUT6 dpo (.A(\$DPO ), .S({1'b1, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}), .Y(DPO));
 endmodule
 
 module RAM64X1D (
@@ -416,8 +416,8 @@ module RAM64X1D (
     .A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4), .A5(A5),
     .DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4), .DPRA5(DPRA5)
   );
-  \$__ABC9_LUT6 dpo (.A(\$DPO ), .S({A0, A1, A2, A3, A4, A5}), .Y(DPO));
-  \$__ABC9_LUT6 spo (.A(\$SPO ), .S({A0, A1, A2, A3, A4, A5}), .Y(SPO));
+  \$__ABC9_LUT6 spo (.A(\$SPO ), .S({A5, A4, A3, A2, A1, A0}), .Y(SPO));
+  \$__ABC9_LUT6 dpo (.A(\$DPO ), .S({DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}), .Y(DPO));
 endmodule
 
 module RAM128X1D (
@@ -438,8 +438,8 @@ module RAM128X1D (
     .A(A),
     .DPRA(DPRA)
   );
-  \$__ABC9_LUT7 dpo (.A(\$DPO ), .S(A), .Y(DPO));
   \$__ABC9_LUT7 spo (.A(\$SPO ), .S(A), .Y(SPO));
+  \$__ABC9_LUT7 dpo (.A(\$DPO ), .S(DPRA), .Y(DPO));
 endmodule
 
 module SRL16E (
@@ -455,7 +455,7 @@ module SRL16E (
     .Q(\$Q ),
     .A0(A0), .A1(A1), .A2(A2), .A3(A3), .CE(CE), .CLK(CLK), .D(D)
   );
-  \$__ABC9_LUT6 q (.A(\$Q ), .S({1'b1, A0, A1, A2, A3, 1'b1}), .Y(Q));
+  \$__ABC9_LUT6 q (.A(\$Q ), .S({1'b1, A3, A2, A1, A0, 1'b1}), .Y(Q));
 endmodule
 
 module SRLC32E (
-- 
cgit v1.2.3


From 979bf36fb00ec61ec7e27f074079e0464be03be7 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 19 Dec 2019 11:23:41 -0800
Subject: Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_t

---
 techlibs/xilinx/abc9_map.v   | 32 ++++++++++++++++++--------------
 techlibs/xilinx/abc9_model.v | 14 +++++++++++---
 techlibs/xilinx/abc9_unmap.v |  3 ++-
 techlibs/xilinx/abc9_xc7.box | 26 ++++++++++++++++----------
 techlibs/xilinx/cells_sim.v  | 16 ++++++++--------
 5 files changed, 55 insertions(+), 36 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v
index d04cdb5eb..b36d93c5d 100644
--- a/techlibs/xilinx/abc9_map.v
+++ b/techlibs/xilinx/abc9_map.v
@@ -161,8 +161,10 @@ module FDCE (output Q, input C, CE, D, CLR);
                                             //     control is not directly
                                             //     supported by abc9 but its
                                             //     behaviour is captured by
-                                            //     $__ABC9_ASYNC below
+                                            //     $__ABC9_ASYNC1 below
     );
+    // Since this is an async flop, async behaviour is dealt with here
+    \$__ABC9_ASYNC0 abc_async (.A($abc9_currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(QQ));
   end
   else begin
     assign Q = QQ;
@@ -177,13 +179,12 @@ module FDCE (output Q, input C, CE, D, CLR);
                                            //     control is not directly
                                            //     supported by abc9 but its
                                            //     behaviour is captured by
-                                           //     $__ABC9_ASYNC below
+                                           //     $__ABC9_ASYNC0 below
     );
+    // Since this is an async flop, async behaviour is dealt with here
+    \$__ABC9_ASYNC1 abc_async (.A($abc9_currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(QQ));
   end endgenerate
   \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ));
-  // Since this is an async flop, async behaviour is also dealt with
-  //   using the $_ABC9_ASYNC box by abc9_map.v
-  \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(QQ));
 
   // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
@@ -203,8 +204,9 @@ module FDCE_1 (output Q, input C, CE, D, CLR);
                                             //     control is not directly
                                             //     supported by abc9 but its
                                             //     behaviour is captured by
-                                            //     $__ABC9_ASYNC below
+                                            //     $__ABC9_ASYNC1 below
     );
+    \$__ABC9_ASYNC1 abc_async (.A($abc9_currQ), .S(CLR), .Y(QQ));
   end
   else begin
     assign Q = QQ;
@@ -216,11 +218,11 @@ module FDCE_1 (output Q, input C, CE, D, CLR);
                                            //     control is not directly
                                            //     supported by abc9 but its
                                            //     behaviour is captured by
-                                           //     $__ABC9_ASYNC below
+                                           //     $__ABC9_ASYNC0 below
     );
+    \$__ABC9_ASYNC0 abc_async (.A($abc9_currQ), .S(CLR), .Y(QQ));
   end endgenerate
   \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ));
-  \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(CLR), .Y(QQ));
 
   // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
@@ -247,8 +249,9 @@ module FDPE (output Q, input C, CE, D, PRE);
                                             //     control is not directly
                                             //     supported by abc9 but its
                                             //     behaviour is captured by
-                                            //     $__ABC9_ASYNC below
+                                            //     $__ABC9_ASYNC0 below
     );
+    \$__ABC9_ASYNC0 abc_async (.A($abc9_currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(QQ));
   end
   else begin
     assign Q = QQ;
@@ -263,11 +266,11 @@ module FDPE (output Q, input C, CE, D, PRE);
                                            //     control is not directly
                                            //     supported by abc9 but its
                                            //     behaviour is captured by
-                                           //     $__ABC9_ASYNC below
+                                           //     $__ABC9_ASYNC1 below
     );
+    \$__ABC9_ASYNC1 abc_async (.A($abc9_currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(QQ));
   end endgenerate
   \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ));
-  \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(QQ));
 
   // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
@@ -287,8 +290,9 @@ module FDPE_1 (output Q, input C, CE, D, PRE);
                                             //     control is not directly
                                             //     supported by abc9 but its
                                             //     behaviour is captured by
-                                            //     $__ABC9_ASYNC below
+                                            //     $__ABC9_ASYNC0 below
     );
+    \$__ABC9_ASYNC0 abc_async (.A($abc9_currQ), .S(PRE), .Y(QQ));
   end
   else begin
     assign Q = QQ;
@@ -300,11 +304,11 @@ module FDPE_1 (output Q, input C, CE, D, PRE);
                                            //     control is not directly
                                            //     supported by abc9 but its
                                            //     behaviour is captured by
-                                           //     $__ABC9_ASYNC below
+                                           //     $__ABC9_ASYNC1 below
     );
+    \$__ABC9_ASYNC1 abc_async (.A($abc9_currQ), .S(PRE), .Y(QQ));
   end endgenerate
   \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ));
-  \$__ABC9_ASYNC abc_async (.A($abc9_currQ), .S(PRE), .Y(QQ));
 
   // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
diff --git a/techlibs/xilinx/abc9_model.v b/techlibs/xilinx/abc9_model.v
index cc0e5ec41..c793396a4 100644
--- a/techlibs/xilinx/abc9_model.v
+++ b/techlibs/xilinx/abc9_model.v
@@ -33,11 +33,19 @@ endmodule
 module \$__ABC9_FF_ (input D, output Q);
 endmodule
 
+// Box to emulate async behaviour of FDC*
 (* abc_box_id = 1000 *)
-module \$__ABC9_ASYNC (input A, S, output Y);
+module \$__ABC9_ASYNC0 (input A, S, output Y);
+  assign Y = S ? 1'b0 : A;
 endmodule
 
-// Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32}
+// Box to emulate async behaviour of FDP*
+(* abc_box_id = 1001 *)
+module \$__ABC9_ASYNC1 (input A, S, output Y);
+  assign Y = S ? 1'b0 : A;
+endmodule
+
+// Box to emulate comb/seq behaviour of RAM{32,64} and SRL{16,32}
 //   Necessary since RAMD* and SRL* have both combinatorial (i.e.
 //   same-cycle read operation) and sequential (write operation
 //   is only committed on the next clock edge).
@@ -46,7 +54,7 @@ endmodule
 (* abc9_box_id=2000 *)
 module \$__ABC9_LUT6 (input A, input [5:0] S, output Y);
 endmodule
-// Box to emulate comb/seq behaviour of RAMD128
+// Box to emulate comb/seq behaviour of RAM128
 (* abc9_box_id=2001 *)
 module \$__ABC9_LUT7 (input A, input [6:0] S, output Y);
 endmodule
diff --git a/techlibs/xilinx/abc9_unmap.v b/techlibs/xilinx/abc9_unmap.v
index 21fe78d08..46526007d 100644
--- a/techlibs/xilinx/abc9_unmap.v
+++ b/techlibs/xilinx/abc9_unmap.v
@@ -20,7 +20,8 @@
 
 // ============================================================================
 
-module \$__ABC9_ASYNC (input A, S, output Y);
+(* techmap_celltype = "$__ABC9_ASYNC0 $__ABC9_ASYNC1" *)
+module \$__ABC9_ASYNC01 (input A, S, output Y);
   assign Y = A;
 endmodule
 
diff --git a/techlibs/xilinx/abc9_xc7.box b/techlibs/xilinx/abc9_xc7.box
index 4e632c0fa..a2d119284 100644
--- a/techlibs/xilinx/abc9_xc7.box
+++ b/techlibs/xilinx/abc9_xc7.box
@@ -41,10 +41,16 @@ CARRY4 4 1 10 8
 592 540 520 356 -   512 548 292 -   228
 580 526 507 398 385 508 528 378 380 114
 
-# Box to emulate async behaviour of FD[CP]*
+# Box to emulate async behaviour of FDC*
 # Inputs: A S
 # Outputs: Y
-$__ABC9_ASYNC 1000 0 2 1
+$__ABC9_ASYNC0 1000 1 2 1
+0 764
+
+# Box to emulate async behaviour of FDP*
+# Inputs: A S
+# Outputs: Y
+$__ABC9_ASYNC1 1001 1 2 1
 0 764
 
 # The following FD*.{CE,R,CLR,PRE) are offset by 46ps to
@@ -54,42 +60,42 @@ $__ABC9_ASYNC 1000 0 2 1
 
 # Inputs: C CE D R \$currQ
 # Outputs: Q
-FDRE 1001 1 5 1
+FDRE 1100 1 5 1
 0 151 0 446 0
 
 # Inputs: C CE D R \$currQ
 # Outputs: Q
-FDRE_1 1002 1 5 1
+FDRE_1 1101 1 5 1
 0 151 0 446 0
 
 # Inputs: C CE CLR D \$currQ
 # Outputs: Q
-FDCE 1003 1 5 1
+FDCE 1102 1 5 1
 0 151 806 0 0
 
 # Inputs: C CE CLR D \$currQ
 # Outputs: Q
-FDCE_1 1004 1 5 1
+FDCE_1 1103 1 5 1
 0 151 806 0 0
 
 # Inputs: C CE D PRE \$currQ
 # Outputs: Q
-FDPE 1005 1 5 1
+FDPE 1104 1 5 1
 0 151 0 806 0
 
 # Inputs: C CE D PRE \$currQ
 # Outputs: Q
-FDPE_1 1006 1 5 1
+FDPE_1 1105 1 5 1
 0 151 0 806 0
 
 # Inputs: C CE D S \$currQ
 # Outputs: Q
-FDSE 1007 1 5 1
+FDSE 1106 1 5 1
 0 151 0 446 0
 
 # Inputs: C CE D S \$currQ
 # Outputs: Q
-FDSE_1 1008 1 5 1
+FDSE_1 1107 1 5 1
 0 151 0 446 0
 
 # SLICEM/A6LUT
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 7941a94cd..d7dff8975 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -283,7 +283,7 @@ endmodule
 
 // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L238-L250
 
-(* abc9_box_id=1001, lib_whitebox, abc9_flop *)
+(* abc9_box_id=1100, lib_whitebox, abc9_flop *)
 module FDRE (
   (* abc9_arrival=303 *)
   output reg Q,
@@ -307,7 +307,7 @@ module FDRE (
   endcase endgenerate
 endmodule
 
-(* abc9_box_id=1002, lib_whitebox, abc9_flop *)
+(* abc9_box_id=1101, lib_whitebox, abc9_flop *)
 module FDRE_1 (
   (* abc9_arrival=303 *)
   output reg Q,
@@ -355,7 +355,7 @@ module FDRSE (
       Q <= d;
 endmodule
 
-(* abc9_box_id=1003, lib_whitebox, abc9_flop *)
+(* abc9_box_id=1102, lib_whitebox, abc9_flop *)
 module FDCE (
   (* abc9_arrival=303 *)
   output reg Q,
@@ -381,7 +381,7 @@ module FDCE (
   endcase endgenerate
 endmodule
 
-(* abc9_box_id=1004, lib_whitebox, abc9_flop *)
+(* abc9_box_id=1103, lib_whitebox, abc9_flop *)
 module FDCE_1 (
   (* abc9_arrival=303 *)
   output reg Q,
@@ -394,7 +394,7 @@ module FDCE_1 (
   always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
 endmodule
 
-(* abc9_box_id=1005, lib_whitebox, abc9_flop *)
+(* abc9_box_id=1104, lib_whitebox, abc9_flop *)
 module FDPE (
   (* abc9_arrival=303 *)
   output reg Q,
@@ -420,7 +420,7 @@ module FDPE (
   endcase endgenerate
 endmodule
 
-(* abc9_box_id=1006, lib_whitebox, abc9_flop *)
+(* abc9_box_id=1105, lib_whitebox, abc9_flop *)
 module FDPE_1 (
   (* abc9_arrival=303 *)
   output reg Q,
@@ -433,7 +433,7 @@ module FDPE_1 (
   always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
 endmodule
 
-(* abc9_box_id=1007, lib_whitebox, abc9_flop *)
+(* abc9_box_id=1106, lib_whitebox, abc9_flop *)
 module FDSE (
   (* abc9_arrival=303 *)
   output reg Q,
@@ -457,7 +457,7 @@ module FDSE (
   endcase endgenerate
 endmodule
 
-(* abc9_box_id=1008, lib_whitebox, abc9_flop *)
+(* abc9_box_id=1107, lib_whitebox, abc9_flop *)
 module FDSE_1 (
   (* abc9_arrival=303 *)
   output reg Q,
-- 
cgit v1.2.3


From 45f0f1486bbe30cdbf22c94b165879568af1a37a Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 19 Dec 2019 11:24:39 -0800
Subject: Add RAM{32,64}M to abc9_map.v

---
 techlibs/xilinx/abc9_map.v | 78 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 78 insertions(+)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v
index b36d93c5d..d2d7d9114 100644
--- a/techlibs/xilinx/abc9_map.v
+++ b/techlibs/xilinx/abc9_map.v
@@ -446,6 +446,84 @@ module RAM128X1D (
   \$__ABC9_LUT7 dpo (.A(\$DPO ), .S(DPRA), .Y(DPO));
 endmodule
 
+module RAM32M (
+  output [1:0] DOA,
+  output [1:0] DOB,
+  output [1:0] DOC,
+  output [1:0] DOD,
+  (* techmap_autopurge *) input [4:0] ADDRA,
+  (* techmap_autopurge *) input [4:0] ADDRB,
+  (* techmap_autopurge *) input [4:0] ADDRC,
+  (* techmap_autopurge *) input [4:0] ADDRD,
+  (* techmap_autopurge *) input [1:0] DIA,
+  (* techmap_autopurge *) input [1:0] DIB,
+  (* techmap_autopurge *) input [1:0] DIC,
+  (* techmap_autopurge *) input [1:0] DID,
+  (* techmap_autopurge *) input WCLK,
+  (* techmap_autopurge *) input WE
+);
+  parameter [63:0] INIT_A = 64'h0000000000000000;
+  parameter [63:0] INIT_B = 64'h0000000000000000;
+  parameter [63:0] INIT_C = 64'h0000000000000000;
+  parameter [63:0] INIT_D = 64'h0000000000000000;
+  parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+  wire [1:0] \$DOA , \$DOB , \$DOC , \$DOD ;
+  RAM32M #(
+    .INIT_A(INIT_A), .INIT_B(INIT_B), .INIT_C(INIT_C), .INIT_D(INIT_D),
+    .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
+  ) _TECHMAP_REPLACE_ (
+    .DOA(\$DOA ), .DOB(\$DOB ), .DOC(\$DOC ), .DOD(\$DOD ),
+    .WCLK(WCLK), .WE(WE),
+    .ADDRA(ADDRA), .ADDRB(ADDRB), .ADDRC(ADDRC), .ADDRD(ADDRD),
+    .DIA(DIA), .DIB(DIB), .DIC(DIC), .DID(DID)
+  );
+  \$__ABC9_LUT6 doa0 (.A(\$DOA [0]), .S({1'b1, ADDRA}), .Y(DOA[0]));
+  \$__ABC9_LUT6 doa1 (.A(\$DOA [1]), .S({1'b1, ADDRA}), .Y(DOA[1]));
+  \$__ABC9_LUT6 dob0 (.A(\$DOB [0]), .S({1'b1, ADDRB}), .Y(DOB[0]));
+  \$__ABC9_LUT6 dob1 (.A(\$DOB [1]), .S({1'b1, ADDRB}), .Y(DOB[1]));
+  \$__ABC9_LUT6 doc0 (.A(\$DOC [0]), .S({1'b1, ADDRC}), .Y(DOC[0]));
+  \$__ABC9_LUT6 doc1 (.A(\$DOC [1]), .S({1'b1, ADDRC}), .Y(DOC[1]));
+  \$__ABC9_LUT6 dod0 (.A(\$DOD [0]), .S({1'b1, ADDRD}), .Y(DOD[0]));
+  \$__ABC9_LUT6 dod1 (.A(\$DOD [1]), .S({1'b1, ADDRD}), .Y(DOD[1]));
+endmodule
+
+module RAM64M (
+  output DOA,
+  output DOB,
+  output DOC,
+  output DOD,
+  (* techmap_autopurge *) input [5:0] ADDRA,
+  (* techmap_autopurge *) input [5:0] ADDRB,
+  (* techmap_autopurge *) input [5:0] ADDRC,
+  (* techmap_autopurge *) input [5:0] ADDRD,
+  (* techmap_autopurge *) input DIA,
+  (* techmap_autopurge *) input DIB,
+  (* techmap_autopurge *) input DIC,
+  (* techmap_autopurge *) input DID,
+  (* techmap_autopurge *) input WCLK,
+  (* techmap_autopurge *) input WE
+);
+  parameter [63:0] INIT_A = 64'h0000000000000000;
+  parameter [63:0] INIT_B = 64'h0000000000000000;
+  parameter [63:0] INIT_C = 64'h0000000000000000;
+  parameter [63:0] INIT_D = 64'h0000000000000000;
+  parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+  wire \$DOA , \$DOB , \$DOC , \$DOD ;
+  RAM64M #(
+    .INIT_A(INIT_A), .INIT_B(INIT_B), .INIT_C(INIT_C), .INIT_D(INIT_D),
+    .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
+  ) _TECHMAP_REPLACE_ (
+    .DOA(\$DOA ), .DOB(\$DOB ), .DOC(\$DOC ), .DOD(\$DOD ),
+    .WCLK(WCLK), .WE(WE),
+    .ADDRA(ADDRA), .ADDRB(ADDRB), .ADDRC(ADDRC), .ADDRD(ADDRD),
+    .DIA(DIA), .DIB(DIB), .DIC(DIC), .DID(DID)
+  );
+  \$__ABC9_LUT6 doa (.A(\$DOA ), .S(ADDRA), .Y(DOA));
+  \$__ABC9_LUT6 dob (.A(\$DOB ), .S(ADDRB), .Y(DOB));
+  \$__ABC9_LUT6 doc (.A(\$DOC ), .S(ADDRC), .Y(DOC));
+  \$__ABC9_LUT6 dod (.A(\$DOD ), .S(ADDRD), .Y(DOD));
+endmodule
+
 module SRL16E (
   output Q,
   (* techmap_autopurge *) input A0, A1, A2, A3, CE, CLK, D
-- 
cgit v1.2.3


From d7ada6649766cfa32b077a744e066476278afd02 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 30 Dec 2019 14:13:16 -0800
Subject: Add "synth_xilinx -dff" option, cleanup abc9

---
 techlibs/xilinx/abc9_map.v      | 84 +++++++++++++++++++++++++++++++++++++++++
 techlibs/xilinx/synth_xilinx.cc | 16 +++++++-
 2 files changed, 98 insertions(+), 2 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v
index d2d7d9114..1e17d4766 100644
--- a/techlibs/xilinx/abc9_map.v
+++ b/techlibs/xilinx/abc9_map.v
@@ -83,6 +83,7 @@ module FDRE (output Q, input C, CE, D, R);
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_R_INVERTED = 1'b0;
+`ifdef DFF_MODE
   wire QQ, $nextQ;
   generate if (INIT == 1'b1) begin
     assign Q = ~QQ;
@@ -113,9 +114,21 @@ module FDRE (output Q, input C, CE, D, R);
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
+`else
+  (* abc9_keep *)
+  FDRE #(
+    .INIT(INIT),
+    .IS_C_INVERTED(IS_C_INVERTED),
+    .IS_D_INVERTED(IS_D_INVERTED),
+    .IS_R_INVERTED(IS_R_INVERTED)
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(Q), .C(C), .CE(CE), .R(R)
+  );
+`endif
 endmodule
 module FDRE_1 (output Q, input C, CE, D, R);
   parameter [0:0] INIT = 1'b0;
+`ifdef DFF_MODE
   wire QQ, $nextQ;
   generate if (INIT == 1'b1) begin
     assign Q = ~QQ;
@@ -140,6 +153,14 @@ module FDRE_1 (output Q, input C, CE, D, R);
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
+`else
+  (* abc9_keep *)
+  FDRE_1 #(
+    .INIT(INIT)
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(Q), .C(C), .CE(CE), .R(R)
+  );
+`endif
 endmodule
 
 module FDCE (output Q, input C, CE, D, CLR);
@@ -147,6 +168,7 @@ module FDCE (output Q, input C, CE, D, CLR);
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_CLR_INVERTED = 1'b0;
+`ifdef DFF_MODE
   wire QQ, $nextQ, $abc9_currQ;
   generate if (INIT == 1'b1) begin
     assign Q = ~QQ;
@@ -190,9 +212,21 @@ module FDCE (output Q, input C, CE, D, CLR);
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
+`else
+  (* abc9_keep *)
+  FDCE #(
+    .INIT(INIT),
+    .IS_C_INVERTED(IS_C_INVERTED),
+    .IS_D_INVERTED(IS_D_INVERTED),
+    .IS_CLR_INVERTED(IS_CLR_INVERTED)
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(Q), .C(C), .CE(CE), .CLR(CLR)
+  );
+`endif
 endmodule
 module FDCE_1 (output Q, input C, CE, D, CLR);
   parameter [0:0] INIT = 1'b0;
+`ifdef DFF_MODE
   wire QQ, $nextQ, $abc9_currQ;
   generate if (INIT == 1'b1) begin
     assign Q = ~QQ;
@@ -228,6 +262,14 @@ module FDCE_1 (output Q, input C, CE, D, CLR);
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
+`else
+  (* abc9_keep *)
+  FDCE_1 #(
+    .INIT(INIT)
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(Q), .C(C), .CE(CE), .CLR(CLR)
+  );
+`endif
 endmodule
 
 module FDPE (output Q, input C, CE, D, PRE);
@@ -235,6 +277,7 @@ module FDPE (output Q, input C, CE, D, PRE);
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_PRE_INVERTED = 1'b0;
+`ifdef DFF_MODE
   wire QQ, $nextQ, $abc9_currQ;
   generate if (INIT == 1'b1) begin
     assign Q = ~QQ;
@@ -276,9 +319,21 @@ module FDPE (output Q, input C, CE, D, PRE);
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
+`else
+  (* abc9_keep *)
+  FDPE #(
+    .INIT(INIT),
+    .IS_C_INVERTED(IS_C_INVERTED),
+    .IS_D_INVERTED(IS_D_INVERTED),
+    .IS_PRE_INVERTED(IS_PRE_INVERTED),
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(Q), .C(C), .CE(CE), .PRE(PRE)
+  );
+`endif
 endmodule
 module FDPE_1 (output Q, input C, CE, D, PRE);
   parameter [0:0] INIT = 1'b1;
+`ifdef DFF_MODE
   wire QQ, $nextQ, $abc9_currQ;
   generate if (INIT == 1'b1) begin
     assign Q = ~QQ;
@@ -314,6 +369,14 @@ module FDPE_1 (output Q, input C, CE, D, PRE);
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = $abc9_currQ;
+`else
+  (* abc9_keep *)
+  FDPE_1 #(
+    .INIT(INIT)
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(Q), .C(C), .CE(CE), .PRE(PRE)
+  );
+`endif
 endmodule
 
 module FDSE (output Q, input C, CE, D, S);
@@ -321,6 +384,7 @@ module FDSE (output Q, input C, CE, D, S);
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_S_INVERTED = 1'b0;
+`ifdef DFF_MODE
   wire QQ, $nextQ;
   generate if (INIT == 1'b1) begin
     assign Q = ~QQ;
@@ -350,9 +414,21 @@ module FDSE (output Q, input C, CE, D, S);
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
+`else
+  (* abc9_keep *)
+  FDSE #(
+    .INIT(INIT),
+    .IS_C_INVERTED(IS_C_INVERTED),
+    .IS_D_INVERTED(IS_D_INVERTED),
+    .IS_S_INVERTED(IS_S_INVERTED)
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(Q), .C(C), .CE(CE), .S(S)
+  );
+`endif
 endmodule
 module FDSE_1 (output Q, input C, CE, D, S);
   parameter [0:0] INIT = 1'b1;
+`ifdef DFF_MODE
   wire QQ, $nextQ;
   generate if (INIT == 1'b1) begin
     assign Q = ~QQ;
@@ -376,6 +452,14 @@ module FDSE_1 (output Q, input C, CE, D, S);
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
   wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
   wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
+`else
+  (* abc9_keep *)
+  FDSE_1 #(
+    .INIT(INIT)
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(Q), .C(C), .CE(CE), .S(S)
+  );
+`endif
 endmodule
 
 module RAM32X1D (
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index ac6fedc58..e7069f286 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -109,6 +109,9 @@ struct SynthXilinxPass : public ScriptPass
 		log("    -flatten\n");
 		log("        flatten design before synthesis\n");
 		log("\n");
+		log("    -dff\n");
+		log("        run 'abc9' with -dff option\n");
+		log("\n");
 		log("    -retime\n");
 		log("        run 'abc' with -dff option\n");
 		log("\n");
@@ -122,7 +125,8 @@ struct SynthXilinxPass : public ScriptPass
 	}
 
 	std::string top_opt, edif_file, blif_file, family;
-	bool flatten, retime, vpr, ise, iopad, noiopad, noclkbuf, nobram, nolutram, nosrl, nocarry, nowidelut, nodsp, uram, abc9;
+	bool flatten, retime, vpr, ise, iopad, noiopad, noclkbuf, nobram, nolutram, nosrl, nocarry, nowidelut, nodsp, uram;
+	bool abc9, dff_mode;
 	bool flatten_before_abc;
 	int widemux;
 
@@ -148,6 +152,7 @@ struct SynthXilinxPass : public ScriptPass
 		nodsp = false;
 		uram = false;
 		abc9 = false;
+		dff_mode = false;
 		flatten_before_abc = false;
 		widemux = 0;
 	}
@@ -256,6 +261,10 @@ struct SynthXilinxPass : public ScriptPass
 				uram = true;
 				continue;
 			}
+			if (args[argidx] == "-dff") {
+				dff_mode = true;
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
@@ -540,7 +549,10 @@ struct SynthXilinxPass : public ScriptPass
 				if (family != "xc7")
 					log_warning("'synth_xilinx -abc9' not currently supported for the '%s' family, "
 							"will use timing for 'xc7' instead.\n", family.c_str());
-				run("techmap -map +/xilinx/abc9_map.v -max_iter 1");
+				std::string techmap_args = "-map +/xilinx/abc9_map.v -max_iter 1";
+				if (dff_mode)
+					techmap_args += " -D DFF_MODE";
+				run("techmap " + techmap_args);
 				run("read_verilog -icells -lib +/xilinx/abc9_model.v");
 				std::string abc9_opts = " -box +/xilinx/abc9_xc7.box";
 				abc9_opts += stringf(" -W %d", XC7_WIRE_DELAY);
-- 
cgit v1.2.3


From a038294a87b44a8eadfb62453f1fd76eec5a04ef Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 30 Dec 2019 14:19:29 -0800
Subject: Tidy up abc9_map.v

---
 techlibs/xilinx/abc9_map.v | 206 ++++++++++++++++++++++-----------------------
 1 file changed, 103 insertions(+), 103 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v
index 1e17d4766..2cabe57d7 100644
--- a/techlibs/xilinx/abc9_map.v
+++ b/techlibs/xilinx/abc9_map.v
@@ -49,10 +49,10 @@
 //                ||         Comb box ||
 //                ||                  ||
 //                ||      /\/\/\/\    ||
-//           D  -->>-----<        >   ||            +------+
-//           R  -->>-----<  Comb. >   ||            |$__ABC|
-//          CE  -->>-----<  logic >--->>-- $nextQ --| _FF_ |--+-->> Q
-// $abc9_currQ +-->>-----<        >   ||            +------+  |
+//           D  -->>-----<        >   ||
+//           R  -->>-----<  Comb. >   ||        +----------+
+//          CE  -->>-----<  logic >--->>-- $Q --|$__ABC_FF_|--+-->> Q
+// $abc9_currQ +-->>-----<        >   ||        +----------+  |
 //             |  ||      \/\/\/\/    ||                      |
 //             |  ||                  ||                      |
 //             |  ++==================++                      |
@@ -84,7 +84,7 @@ module FDRE (output Q, input C, CE, D, R);
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_R_INVERTED = 1'b0;
 `ifdef DFF_MODE
-  wire QQ, $nextQ;
+  wire QQ, $Q;
   generate if (INIT == 1'b1) begin
     assign Q = ~QQ;
     FDSE #(
@@ -93,7 +93,7 @@ module FDRE (output Q, input C, CE, D, R);
       .IS_D_INVERTED(IS_D_INVERTED),
       .IS_S_INVERTED(IS_R_INVERTED)
     ) _TECHMAP_REPLACE_ (
-      .D(~D), .Q($nextQ), .C(C), .CE(CE), .S(R)
+      .D(~D), .Q($Q), .C(C), .CE(CE), .S(R)
     );
   end
   else begin
@@ -104,11 +104,11 @@ module FDRE (output Q, input C, CE, D, R);
       .IS_D_INVERTED(IS_D_INVERTED),
       .IS_R_INVERTED(IS_R_INVERTED)
     ) _TECHMAP_REPLACE_ (
-      .D(D), .Q($nextQ), .C(C), .CE(CE), .R(R)
+      .D(D), .Q($Q), .C(C), .CE(CE), .R(R)
     );
   end
   endgenerate
-  \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(QQ));
+  $__ABC9_FF_ abc_dff (.D($Q), .Q(QQ));
 
   // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
@@ -129,13 +129,13 @@ endmodule
 module FDRE_1 (output Q, input C, CE, D, R);
   parameter [0:0] INIT = 1'b0;
 `ifdef DFF_MODE
-  wire QQ, $nextQ;
+  wire QQ, $Q;
   generate if (INIT == 1'b1) begin
     assign Q = ~QQ;
     FDSE_1 #(
       .INIT(1'b0)
     ) _TECHMAP_REPLACE_ (
-      .D(~D), .Q($nextQ), .C(C), .CE(CE), .S(R)
+      .D(~D), .Q($Q), .C(C), .CE(CE), .S(R)
     );
   end
   else begin
@@ -143,11 +143,11 @@ module FDRE_1 (output Q, input C, CE, D, R);
     FDRE_1 #(
       .INIT(1'b0)
     ) _TECHMAP_REPLACE_ (
-      .D(D), .Q($nextQ), .C(C), .CE(CE), .R(R)
+      .D(D), .Q($Q), .C(C), .CE(CE), .R(R)
     );
   end
   endgenerate
-  \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(QQ));
+  $__ABC9_FF_ abc_dff (.D($Q), .Q(QQ));
 
   // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
@@ -169,7 +169,7 @@ module FDCE (output Q, input C, CE, D, CLR);
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_CLR_INVERTED = 1'b0;
 `ifdef DFF_MODE
-  wire QQ, $nextQ, $abc9_currQ;
+  wire QQ, $Q, $abc9_currQ;
   generate if (INIT == 1'b1) begin
     assign Q = ~QQ;
     FDPE #(
@@ -178,7 +178,7 @@ module FDCE (output Q, input C, CE, D, CLR);
       .IS_D_INVERTED(IS_D_INVERTED),
       .IS_PRE_INVERTED(IS_CLR_INVERTED)
     ) _TECHMAP_REPLACE_ (
-      .D(~D), .Q($nextQ), .C(C), .CE(CE), .PRE(CLR)
+      .D(~D), .Q($Q), .C(C), .CE(CE), .PRE(CLR)
                                             // ^^^ Note that async
                                             //     control is not directly
                                             //     supported by abc9 but its
@@ -186,7 +186,7 @@ module FDCE (output Q, input C, CE, D, CLR);
                                             //     $__ABC9_ASYNC1 below
     );
     // Since this is an async flop, async behaviour is dealt with here
-    \$__ABC9_ASYNC0 abc_async (.A($abc9_currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(QQ));
+    $__ABC9_ASYNC0 abc_async (.A($abc9_currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(QQ));
   end
   else begin
     assign Q = QQ;
@@ -196,7 +196,7 @@ module FDCE (output Q, input C, CE, D, CLR);
       .IS_D_INVERTED(IS_D_INVERTED),
       .IS_CLR_INVERTED(IS_CLR_INVERTED)
     ) _TECHMAP_REPLACE_ (
-      .D(D), .Q($nextQ), .C(C), .CE(CE), .CLR(CLR)
+      .D(D), .Q($Q), .C(C), .CE(CE), .CLR(CLR)
                                            // ^^^ Note that async
                                            //     control is not directly
                                            //     supported by abc9 but its
@@ -204,9 +204,9 @@ module FDCE (output Q, input C, CE, D, CLR);
                                            //     $__ABC9_ASYNC0 below
     );
     // Since this is an async flop, async behaviour is dealt with here
-    \$__ABC9_ASYNC1 abc_async (.A($abc9_currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(QQ));
+    $__ABC9_ASYNC1 abc_async (.A($abc9_currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(QQ));
   end endgenerate
-  \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ));
+  $__ABC9_FF_ abc_dff (.D($Q), .Q($abc9_currQ));
 
   // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
@@ -227,36 +227,36 @@ endmodule
 module FDCE_1 (output Q, input C, CE, D, CLR);
   parameter [0:0] INIT = 1'b0;
 `ifdef DFF_MODE
-  wire QQ, $nextQ, $abc9_currQ;
+  wire QQ, $Q, $abc9_currQ;
   generate if (INIT == 1'b1) begin
     assign Q = ~QQ;
     FDPE_1 #(
       .INIT(1'b0)
     ) _TECHMAP_REPLACE_ (
-      .D(~D), .Q($nextQ), .C(C), .CE(CE), .PRE(CLR)
+      .D(~D), .Q($Q), .C(C), .CE(CE), .PRE(CLR)
                                             // ^^^ Note that async
                                             //     control is not directly
                                             //     supported by abc9 but its
                                             //     behaviour is captured by
                                             //     $__ABC9_ASYNC1 below
     );
-    \$__ABC9_ASYNC1 abc_async (.A($abc9_currQ), .S(CLR), .Y(QQ));
+    $__ABC9_ASYNC1 abc_async (.A($abc9_currQ), .S(CLR), .Y(QQ));
   end
   else begin
     assign Q = QQ;
     FDCE_1 #(
       .INIT(1'b0)
     ) _TECHMAP_REPLACE_ (
-      .D(D), .Q($nextQ), .C(C), .CE(CE), .CLR(CLR)
+      .D(D), .Q($Q), .C(C), .CE(CE), .CLR(CLR)
                                            // ^^^ Note that async
                                            //     control is not directly
                                            //     supported by abc9 but its
                                            //     behaviour is captured by
                                            //     $__ABC9_ASYNC0 below
     );
-    \$__ABC9_ASYNC0 abc_async (.A($abc9_currQ), .S(CLR), .Y(QQ));
+    $__ABC9_ASYNC0 abc_async (.A($abc9_currQ), .S(CLR), .Y(QQ));
   end endgenerate
-  \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ));
+  $__ABC9_FF_ abc_dff (.D($Q), .Q($abc9_currQ));
 
   // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
@@ -278,7 +278,7 @@ module FDPE (output Q, input C, CE, D, PRE);
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_PRE_INVERTED = 1'b0;
 `ifdef DFF_MODE
-  wire QQ, $nextQ, $abc9_currQ;
+  wire QQ, $Q, $abc9_currQ;
   generate if (INIT == 1'b1) begin
     assign Q = ~QQ;
     FDCE #(
@@ -287,14 +287,14 @@ module FDPE (output Q, input C, CE, D, PRE);
       .IS_D_INVERTED(IS_D_INVERTED),
       .IS_CLR_INVERTED(IS_PRE_INVERTED),
     ) _TECHMAP_REPLACE_ (
-      .D(~D), .Q($nextQ), .C(C), .CE(CE), .CLR(PRE)
+      .D(~D), .Q($Q), .C(C), .CE(CE), .CLR(PRE)
                                             // ^^^ Note that async
                                             //     control is not directly
                                             //     supported by abc9 but its
                                             //     behaviour is captured by
                                             //     $__ABC9_ASYNC0 below
     );
-    \$__ABC9_ASYNC0 abc_async (.A($abc9_currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(QQ));
+    $__ABC9_ASYNC0 abc_async (.A($abc9_currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(QQ));
   end
   else begin
     assign Q = QQ;
@@ -304,16 +304,16 @@ module FDPE (output Q, input C, CE, D, PRE);
       .IS_D_INVERTED(IS_D_INVERTED),
       .IS_PRE_INVERTED(IS_PRE_INVERTED),
     ) _TECHMAP_REPLACE_ (
-      .D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(PRE)
+      .D(D), .Q($Q), .C(C), .CE(CE), .PRE(PRE)
                                            // ^^^ Note that async
                                            //     control is not directly
                                            //     supported by abc9 but its
                                            //     behaviour is captured by
                                            //     $__ABC9_ASYNC1 below
     );
-    \$__ABC9_ASYNC1 abc_async (.A($abc9_currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(QQ));
+    $__ABC9_ASYNC1 abc_async (.A($abc9_currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(QQ));
   end endgenerate
-  \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ));
+  $__ABC9_FF_ abc_dff (.D($Q), .Q($abc9_currQ));
 
   // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
@@ -334,36 +334,36 @@ endmodule
 module FDPE_1 (output Q, input C, CE, D, PRE);
   parameter [0:0] INIT = 1'b1;
 `ifdef DFF_MODE
-  wire QQ, $nextQ, $abc9_currQ;
+  wire QQ, $Q, $abc9_currQ;
   generate if (INIT == 1'b1) begin
     assign Q = ~QQ;
     FDCE_1 #(
       .INIT(1'b0)
     ) _TECHMAP_REPLACE_ (
-      .D(~D), .Q($nextQ), .C(C), .CE(CE), .CLR(PRE)
+      .D(~D), .Q($Q), .C(C), .CE(CE), .CLR(PRE)
                                             // ^^^ Note that async
                                             //     control is not directly
                                             //     supported by abc9 but its
                                             //     behaviour is captured by
                                             //     $__ABC9_ASYNC0 below
     );
-    \$__ABC9_ASYNC0 abc_async (.A($abc9_currQ), .S(PRE), .Y(QQ));
+    $__ABC9_ASYNC0 abc_async (.A($abc9_currQ), .S(PRE), .Y(QQ));
   end
   else begin
     assign Q = QQ;
     FDPE_1 #(
       .INIT(1'b0)
     ) _TECHMAP_REPLACE_ (
-      .D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(PRE)
+      .D(D), .Q($Q), .C(C), .CE(CE), .PRE(PRE)
                                            // ^^^ Note that async
                                            //     control is not directly
                                            //     supported by abc9 but its
                                            //     behaviour is captured by
                                            //     $__ABC9_ASYNC1 below
     );
-    \$__ABC9_ASYNC1 abc_async (.A($abc9_currQ), .S(PRE), .Y(QQ));
+    $__ABC9_ASYNC1 abc_async (.A($abc9_currQ), .S(PRE), .Y(QQ));
   end endgenerate
-  \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ));
+  $__ABC9_FF_ abc_dff (.D($Q), .Q($abc9_currQ));
 
   // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
@@ -385,7 +385,7 @@ module FDSE (output Q, input C, CE, D, S);
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_S_INVERTED = 1'b0;
 `ifdef DFF_MODE
-  wire QQ, $nextQ;
+  wire QQ, $Q;
   generate if (INIT == 1'b1) begin
     assign Q = ~QQ;
     FDRE #(
@@ -394,7 +394,7 @@ module FDSE (output Q, input C, CE, D, S);
       .IS_D_INVERTED(IS_D_INVERTED),
       .IS_R_INVERTED(IS_S_INVERTED)
     ) _TECHMAP_REPLACE_ (
-      .D(~D), .Q($nextQ), .C(C), .CE(CE), .R(S)
+      .D(~D), .Q($Q), .C(C), .CE(CE), .R(S)
     );
   end
   else begin
@@ -405,10 +405,10 @@ module FDSE (output Q, input C, CE, D, S);
       .IS_D_INVERTED(IS_D_INVERTED),
       .IS_S_INVERTED(IS_S_INVERTED)
     ) _TECHMAP_REPLACE_ (
-      .D(D), .Q($nextQ), .C(C), .CE(CE), .S(S)
+      .D(D), .Q($Q), .C(C), .CE(CE), .S(S)
     );
   end endgenerate
-  \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(QQ));
+  $__ABC9_FF_ abc_dff (.D($Q), .Q(QQ));
 
   // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
@@ -429,13 +429,13 @@ endmodule
 module FDSE_1 (output Q, input C, CE, D, S);
   parameter [0:0] INIT = 1'b1;
 `ifdef DFF_MODE
-  wire QQ, $nextQ;
+  wire QQ, $Q;
   generate if (INIT == 1'b1) begin
     assign Q = ~QQ;
     FDRE_1 #(
       .INIT(1'b0)
     ) _TECHMAP_REPLACE_ (
-      .D(~D), .Q($nextQ), .C(C), .CE(CE), .R(S)
+      .D(~D), .Q($Q), .C(C), .CE(CE), .R(S)
     );
   end
   else begin
@@ -443,10 +443,10 @@ module FDSE_1 (output Q, input C, CE, D, S);
     FDSE_1 #(
       .INIT(1'b0)
     ) _TECHMAP_REPLACE_ (
-      .D(D), .Q($nextQ), .C(C), .CE(CE), .S(S)
+      .D(D), .Q($Q), .C(C), .CE(CE), .S(S)
     );
   end endgenerate
-  \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(QQ));
+  $__ABC9_FF_ abc_dff (.D($Q), .Q(QQ));
 
   // Special signals
   wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
@@ -472,17 +472,17 @@ module RAM32X1D (
 );
   parameter INIT = 32'h0;
   parameter IS_WCLK_INVERTED = 1'b0;
-  wire \$DPO , \$SPO ;
+  wire $DPO, $SPO;
   RAM32X1D #(
     .INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
   ) _TECHMAP_REPLACE_ (
-    .DPO(\$DPO ), .SPO(\$SPO ),
+    .DPO($DPO), .SPO($SPO),
     .D(D), .WCLK(WCLK), .WE(WE),
     .A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4),
     .DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4)
   );
-  \$__ABC9_LUT6 spo (.A(\$SPO ), .S({1'b1, A4, A3, A2, A1, A0}), .Y(SPO));
-  \$__ABC9_LUT6 dpo (.A(\$DPO ), .S({1'b1, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}), .Y(DPO));
+  $__ABC9_LUT6 spo (.A($SPO), .S({1'b1, A4, A3, A2, A1, A0}), .Y(SPO));
+  $__ABC9_LUT6 dpo (.A($DPO), .S({1'b1, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}), .Y(DPO));
 endmodule
 
 module RAM64X1D (
@@ -495,17 +495,17 @@ module RAM64X1D (
 );
   parameter INIT = 64'h0;
   parameter IS_WCLK_INVERTED = 1'b0;
-  wire \$DPO , \$SPO ;
+  wire $DPO, $SPO;
   RAM64X1D #(
     .INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
   ) _TECHMAP_REPLACE_ (
-    .DPO(\$DPO ), .SPO(\$SPO ),
+    .DPO($DPO), .SPO($SPO),
     .D(D), .WCLK(WCLK), .WE(WE),
     .A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4), .A5(A5),
     .DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4), .DPRA5(DPRA5)
   );
-  \$__ABC9_LUT6 spo (.A(\$SPO ), .S({A5, A4, A3, A2, A1, A0}), .Y(SPO));
-  \$__ABC9_LUT6 dpo (.A(\$DPO ), .S({DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}), .Y(DPO));
+  $__ABC9_LUT6 spo (.A($SPO), .S({A5, A4, A3, A2, A1, A0}), .Y(SPO));
+  $__ABC9_LUT6 dpo (.A($DPO), .S({DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}), .Y(DPO));
 endmodule
 
 module RAM128X1D (
@@ -517,17 +517,17 @@ module RAM128X1D (
 );
   parameter INIT = 128'h0;
   parameter IS_WCLK_INVERTED = 1'b0;
-  wire \$DPO , \$SPO ;
+  wire $DPO, $SPO;
   RAM128X1D #(
     .INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
   ) _TECHMAP_REPLACE_ (
-    .DPO(\$DPO ), .SPO(\$SPO ),
+    .DPO($DPO), .SPO($SPO),
     .D(D), .WCLK(WCLK), .WE(WE),
     .A(A),
     .DPRA(DPRA)
   );
-  \$__ABC9_LUT7 spo (.A(\$SPO ), .S(A), .Y(SPO));
-  \$__ABC9_LUT7 dpo (.A(\$DPO ), .S(DPRA), .Y(DPO));
+  $__ABC9_LUT7 spo (.A($SPO), .S(A), .Y(SPO));
+  $__ABC9_LUT7 dpo (.A($DPO), .S(DPRA), .Y(DPO));
 endmodule
 
 module RAM32M (
@@ -551,24 +551,24 @@ module RAM32M (
   parameter [63:0] INIT_C = 64'h0000000000000000;
   parameter [63:0] INIT_D = 64'h0000000000000000;
   parameter [0:0] IS_WCLK_INVERTED = 1'b0;
-  wire [1:0] \$DOA , \$DOB , \$DOC , \$DOD ;
+  wire [1:0] $DOA, $DOB, $DOC, $DOD;
   RAM32M #(
     .INIT_A(INIT_A), .INIT_B(INIT_B), .INIT_C(INIT_C), .INIT_D(INIT_D),
     .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
   ) _TECHMAP_REPLACE_ (
-    .DOA(\$DOA ), .DOB(\$DOB ), .DOC(\$DOC ), .DOD(\$DOD ),
+    .DOA($DOA), .DOB($DOB), .DOC($DOC), .DOD($DOD),
     .WCLK(WCLK), .WE(WE),
     .ADDRA(ADDRA), .ADDRB(ADDRB), .ADDRC(ADDRC), .ADDRD(ADDRD),
     .DIA(DIA), .DIB(DIB), .DIC(DIC), .DID(DID)
   );
-  \$__ABC9_LUT6 doa0 (.A(\$DOA [0]), .S({1'b1, ADDRA}), .Y(DOA[0]));
-  \$__ABC9_LUT6 doa1 (.A(\$DOA [1]), .S({1'b1, ADDRA}), .Y(DOA[1]));
-  \$__ABC9_LUT6 dob0 (.A(\$DOB [0]), .S({1'b1, ADDRB}), .Y(DOB[0]));
-  \$__ABC9_LUT6 dob1 (.A(\$DOB [1]), .S({1'b1, ADDRB}), .Y(DOB[1]));
-  \$__ABC9_LUT6 doc0 (.A(\$DOC [0]), .S({1'b1, ADDRC}), .Y(DOC[0]));
-  \$__ABC9_LUT6 doc1 (.A(\$DOC [1]), .S({1'b1, ADDRC}), .Y(DOC[1]));
-  \$__ABC9_LUT6 dod0 (.A(\$DOD [0]), .S({1'b1, ADDRD}), .Y(DOD[0]));
-  \$__ABC9_LUT6 dod1 (.A(\$DOD [1]), .S({1'b1, ADDRD}), .Y(DOD[1]));
+  $__ABC9_LUT6 doa0 (.A($DOA[0]), .S({1'b1, ADDRA}), .Y(DOA[0]));
+  $__ABC9_LUT6 doa1 (.A($DOA[1]), .S({1'b1, ADDRA}), .Y(DOA[1]));
+  $__ABC9_LUT6 dob0 (.A($DOB[0]), .S({1'b1, ADDRB}), .Y(DOB[0]));
+  $__ABC9_LUT6 dob1 (.A($DOB[1]), .S({1'b1, ADDRB}), .Y(DOB[1]));
+  $__ABC9_LUT6 doc0 (.A($DOC[0]), .S({1'b1, ADDRC}), .Y(DOC[0]));
+  $__ABC9_LUT6 doc1 (.A($DOC[1]), .S({1'b1, ADDRC}), .Y(DOC[1]));
+  $__ABC9_LUT6 dod0 (.A($DOD[0]), .S({1'b1, ADDRD}), .Y(DOD[0]));
+  $__ABC9_LUT6 dod1 (.A($DOD[1]), .S({1'b1, ADDRD}), .Y(DOD[1]));
 endmodule
 
 module RAM64M (
@@ -592,20 +592,20 @@ module RAM64M (
   parameter [63:0] INIT_C = 64'h0000000000000000;
   parameter [63:0] INIT_D = 64'h0000000000000000;
   parameter [0:0] IS_WCLK_INVERTED = 1'b0;
-  wire \$DOA , \$DOB , \$DOC , \$DOD ;
+  wire $DOA, $DOB, $DOC, $DOD;
   RAM64M #(
     .INIT_A(INIT_A), .INIT_B(INIT_B), .INIT_C(INIT_C), .INIT_D(INIT_D),
     .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
   ) _TECHMAP_REPLACE_ (
-    .DOA(\$DOA ), .DOB(\$DOB ), .DOC(\$DOC ), .DOD(\$DOD ),
+    .DOA($DOA), .DOB($DOB), .DOC($DOC), .DOD($DOD),
     .WCLK(WCLK), .WE(WE),
     .ADDRA(ADDRA), .ADDRB(ADDRB), .ADDRC(ADDRC), .ADDRD(ADDRD),
     .DIA(DIA), .DIB(DIB), .DIC(DIC), .DID(DID)
   );
-  \$__ABC9_LUT6 doa (.A(\$DOA ), .S(ADDRA), .Y(DOA));
-  \$__ABC9_LUT6 dob (.A(\$DOB ), .S(ADDRB), .Y(DOB));
-  \$__ABC9_LUT6 doc (.A(\$DOC ), .S(ADDRC), .Y(DOC));
-  \$__ABC9_LUT6 dod (.A(\$DOD ), .S(ADDRD), .Y(DOD));
+  $__ABC9_LUT6 doa (.A($DOA), .S(ADDRA), .Y(DOA));
+  $__ABC9_LUT6 dob (.A($DOB), .S(ADDRB), .Y(DOB));
+  $__ABC9_LUT6 doc (.A($DOC), .S(ADDRC), .Y(DOC));
+  $__ABC9_LUT6 dod (.A($DOD), .S(ADDRD), .Y(DOD));
 endmodule
 
 module SRL16E (
@@ -614,14 +614,14 @@ module SRL16E (
 );
   parameter [15:0] INIT = 16'h0000;
   parameter [0:0] IS_CLK_INVERTED = 1'b0;
-  wire \$Q ;
+  wire $Q;
   SRL16E #(
     .INIT(INIT), .IS_CLK_INVERTED(IS_CLK_INVERTED)
   ) _TECHMAP_REPLACE_ (
-    .Q(\$Q ),
+    .Q($Q),
     .A0(A0), .A1(A1), .A2(A2), .A3(A3), .CE(CE), .CLK(CLK), .D(D)
   );
-  \$__ABC9_LUT6 q (.A(\$Q ), .S({1'b1, A3, A2, A1, A0, 1'b1}), .Y(Q));
+  $__ABC9_LUT6 q (.A($Q), .S({1'b1, A3, A2, A1, A0, 1'b1}), .Y(Q));
 endmodule
 
 module SRLC32E (
@@ -632,14 +632,14 @@ module SRLC32E (
 );
   parameter [31:0] INIT = 32'h00000000;
   parameter [0:0] IS_CLK_INVERTED = 1'b0;
-  wire \$Q ;
+  wire $Q;
   SRLC32E #(
     .INIT(INIT), .IS_CLK_INVERTED(IS_CLK_INVERTED)
   ) _TECHMAP_REPLACE_ (
-    .Q(\$Q ), .Q31(Q31),
+    .Q($Q), .Q31(Q31),
     .A(A), .CE(CE), .CLK(CLK), .D(D)
   );
-  \$__ABC9_LUT6 q (.A(\$Q ), .S({1'b1, A}), .Y(Q));
+  $__ABC9_LUT6 q (.A($Q), .S({1'b1, A}), .Y(Q));
 endmodule
 
 module DSP48E1 (
@@ -828,15 +828,15 @@ __CELL__ #(
         if (AREG == 0 && MREG == 0 && PREG == 0)
             assign iA = A, pA = 1'bx;
         else
-            \$__ABC9_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA));
+            $__ABC9_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA));
         if (BREG == 0 && MREG == 0 && PREG == 0)
             assign iB = B, pB = 1'bx;
         else
-            \$__ABC9_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB));
+            $__ABC9_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB));
         if (CREG == 0 && PREG == 0)
             assign iC = C, pC = 1'bx;
         else
-            \$__ABC9_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC));
+            $__ABC9_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC));
         if (DREG == 0)
             assign iD = D;
         else if (techmap_guard)
@@ -847,27 +847,27 @@ __CELL__ #(
         assign pAD = 1'bx;
     if (PREG == 0) begin
         if (MREG == 1)
-        \$__ABC9_REG rM (.Q(pM));
+        $__ABC9_REG rM (.Q(pM));
         else
         assign pM = 1'bx;
         assign pP = 1'bx;
     end else begin
             assign pM = 1'bx;
-            \$__ABC9_REG rP (.Q(pP));
+            $__ABC9_REG rP (.Q(pP));
         end
 
         if (MREG == 0 && PREG == 0)
             assign mP = oP, mPCOUT = oPCOUT;
         else
             assign mP = 1'bx, mPCOUT = 1'bx;
-        \$__ABC9_DSP48E1_MULT_P_MUX muxP (
+        $__ABC9_DSP48E1_MULT_P_MUX muxP (
             .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oP), .Mq(pM), .P(mP), .Pq(pP), .O(P)
         );
-        \$__ABC9_DSP48E1_MULT_PCOUT_MUX muxPCOUT (
+        $__ABC9_DSP48E1_MULT_PCOUT_MUX muxPCOUT (
             .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oPCOUT), .Mq(pM), .P(mPCOUT), .Pq(pP), .O(PCOUT)
         );
 
-        `DSP48E1_INST(\$__ABC9_DSP48E1_MULT )
+        `DSP48E1_INST($__ABC9_DSP48E1_MULT )
     end
     else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin
         // Disconnect the A-input if MREG is enabled, since
@@ -875,26 +875,26 @@ __CELL__ #(
         if (AREG == 0 && ADREG == 0 && MREG == 0 && PREG == 0)
             assign iA = A, pA = 1'bx;
         else
-            \$__ABC9_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA));
+            $__ABC9_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA));
         if (BREG == 0 && MREG == 0 && PREG == 0)
             assign iB = B, pB = 1'bx;
         else
-            \$__ABC9_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB));
+            $__ABC9_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB));
         if (CREG == 0 && PREG == 0)
             assign iC = C, pC = 1'bx;
         else
-            \$__ABC9_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC));
+            $__ABC9_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC));
         if (DREG == 0 && ADREG == 0)
             assign iD = D, pD = 1'bx;
         else
-            \$__ABC9_REG #(.WIDTH(25)) rD (.I(D), .O(iD), .Q(pD));
+            $__ABC9_REG #(.WIDTH(25)) rD (.I(D), .O(iD), .Q(pD));
         if (PREG == 0) begin
             if (MREG == 1) begin
                 assign pAD = 1'bx;
-        \$__ABC9_REG rM (.Q(pM));
+        $__ABC9_REG rM (.Q(pM));
             end else begin
                 if (ADREG == 1)
-                    \$__ABC9_REG rAD (.Q(pAD));
+                    $__ABC9_REG rAD (.Q(pAD));
                 else
                     assign pAD = 1'bx;
         assign pM = 1'bx;
@@ -902,21 +902,21 @@ __CELL__ #(
         assign pP = 1'bx;
     end else begin
             assign pAD = 1'bx, pM = 1'bx;
-            \$__ABC9_REG rP (.Q(pP));
+            $__ABC9_REG rP (.Q(pP));
         end
 
         if (MREG == 0 && PREG == 0)
             assign mP = oP, mPCOUT = oPCOUT;
         else
             assign mP = 1'bx, mPCOUT = 1'bx;
-        \$__ABC9_DSP48E1_MULT_DPORT_P_MUX muxP (
+        $__ABC9_DSP48E1_MULT_DPORT_P_MUX muxP (
             .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oP), .Mq(pM), .P(mP), .Pq(pP), .O(P)
         );
-        \$__ABC9_DSP48E1_MULT_DPORT_PCOUT_MUX muxPCOUT (
+        $__ABC9_DSP48E1_MULT_DPORT_PCOUT_MUX muxPCOUT (
             .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oPCOUT), .Mq(pM), .P(mPCOUT), .Pq(pP), .O(PCOUT)
         );
 
-        `DSP48E1_INST(\$__ABC9_DSP48E1_MULT_DPORT )
+        `DSP48E1_INST($__ABC9_DSP48E1_MULT_DPORT )
     end
     else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin
         // Disconnect the A-input if MREG is enabled, since
@@ -924,15 +924,15 @@ __CELL__ #(
         if (AREG == 0 && PREG == 0)
             assign iA = A, pA = 1'bx;
         else
-            \$__ABC9_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA));
+            $__ABC9_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA));
         if (BREG == 0 && PREG == 0)
             assign iB = B, pB = 1'bx;
         else
-            \$__ABC9_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB));
+            $__ABC9_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB));
         if (CREG == 0 && PREG == 0)
             assign iC = C, pC = 1'bx;
         else
-            \$__ABC9_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC));
+            $__ABC9_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC));
         if (DREG == 1 && techmap_guard)
             $error("Invalid DSP48E1 configuration: DREG enabled but USE_DPORT == \"FALSE\"");
         assign pD = 1'bx;
@@ -943,7 +943,7 @@ __CELL__ #(
             $error("Invalid DSP48E1 configuration: MREG enabled but USE_MULT == \"NONE\"");
         assign pM = 1'bx;
         if (PREG == 1)
-            \$__ABC9_REG rP (.Q(pP));
+            $__ABC9_REG rP (.Q(pP));
         else
             assign pP = 1'bx;
 
@@ -951,14 +951,14 @@ __CELL__ #(
             assign mP = oP, mPCOUT = oPCOUT;
         else
             assign mP = 1'bx, mPCOUT = 1'bx;
-        \$__ABC9_DSP48E1_P_MUX muxP (
+        $__ABC9_DSP48E1_P_MUX muxP (
             .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oP), .Mq(pM), .P(mP), .Pq(pP), .O(P)
         );
-        \$__ABC9_DSP48E1_PCOUT_MUX muxPCOUT (
+        $__ABC9_DSP48E1_PCOUT_MUX muxPCOUT (
             .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oPCOUT), .Mq(pM), .P(mPCOUT), .Pq(pP), .O(PCOUT)
         );
 
-        `DSP48E1_INST(\$__ABC9_DSP48E1 )
+        `DSP48E1_INST($__ABC9_DSP48E1 )
     end
     else
         $error("Invalid DSP48E1 configuration");
-- 
cgit v1.2.3


From eb4e767053f4731c9f4b82c4dd53504e5fe50802 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 27 Dec 2019 12:03:19 -0800
Subject: Do not offset FD* box timings due to -46ps Tsu

---
 techlibs/xilinx/abc9_xc7.box | 33 +++++++++++++++++++++------------
 1 file changed, 21 insertions(+), 12 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/abc9_xc7.box b/techlibs/xilinx/abc9_xc7.box
index a2d119284..16606d14e 100644
--- a/techlibs/xilinx/abc9_xc7.box
+++ b/techlibs/xilinx/abc9_xc7.box
@@ -53,50 +53,59 @@ $__ABC9_ASYNC0 1000 1 2 1
 $__ABC9_ASYNC1 1001 1 2 1
 0 764
 
-# The following FD*.{CE,R,CLR,PRE) are offset by 46ps to
-# reflect the -46ps Tsu
-# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L237-L251
-# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L265-L277
+# Max delays from https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L237-L251
+#                 https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L265-L277
+
+# NB: Inputs/Outputs must be ordered alphabetically
+#     (with exception for \$currQ)
 
 # Inputs: C CE D R \$currQ
 # Outputs: Q
 FDRE 1100 1 5 1
-0 151 0 446 0
+#0 109 -46 404 0
+0 109 0 404 0 # Clamp -46ps Tsu
 
 # Inputs: C CE D R \$currQ
 # Outputs: Q
 FDRE_1 1101 1 5 1
-0 151 0 446 0
+#0 109 0 -46 404
+0 109 0 0 404 # Clamp -46ps Tsu
 
 # Inputs: C CE CLR D \$currQ
 # Outputs: Q
 FDCE 1102 1 5 1
-0 151 806 0 0
+#0 109 764 -46 0
+0 109 764 0 0 # Clamp -46ps Tsu
 
 # Inputs: C CE CLR D \$currQ
 # Outputs: Q
 FDCE_1 1103 1 5 1
-0 151 806 0 0
+#0 109 764 -46 0
+0 109 764 0 0 # Clamp -46ps Tsu
 
 # Inputs: C CE D PRE \$currQ
 # Outputs: Q
 FDPE 1104 1 5 1
-0 151 0 806 0
+#0 109 -46 764 0
+0 109 0 764 0 # Clamp -46ps Tsu
 
 # Inputs: C CE D PRE \$currQ
 # Outputs: Q
 FDPE_1 1105 1 5 1
-0 151 0 806 0
+#0 109 -46 764 0
+0 109 0 764 0 # Clamp -46ps Tsu
 
 # Inputs: C CE D S \$currQ
 # Outputs: Q
 FDSE 1106 1 5 1
-0 151 0 446 0
+#0 109 -46 446 0
+0 109 0 446 0 # Clamp -46ps Tsu
 
 # Inputs: C CE D S \$currQ
 # Outputs: Q
 FDSE_1 1107 1 5 1
-0 151 0 446 0
+#0 109 -46 446 0
+0 109 0 446 0 # Clamp -46ps Tsu
 
 # SLICEM/A6LUT
 # Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32}
-- 
cgit v1.2.3