From 61fc411c5d7237e420ee6eb9f6eb093e70d1007d Mon Sep 17 00:00:00 2001 From: Larry Doolittle Date: Sun, 24 Feb 2019 22:08:52 -0800 Subject: Clean up some whitepsace outliers --- techlibs/ecp5/cells_sim.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'techlibs') diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index 507ab1beb..f27540bd7 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -57,7 +57,7 @@ module TRELLIS_RAM16X2 ( input RAD0, RAD1, RAD2, RAD3, output DO0, DO1 ); - parameter WCKMUX = "WCK"; + parameter WCKMUX = "WCK"; parameter WREMUX = "WRE"; parameter INITVAL_0 = 16'h0000; parameter INITVAL_1 = 16'h0000; @@ -104,7 +104,7 @@ module TRELLIS_DPR16X4 ( input [3:0] RAD, output [3:0] DO ); - parameter WCKMUX = "WCK"; + parameter WCKMUX = "WCK"; parameter WREMUX = "WRE"; parameter [63:0] INITVAL = 64'h0000000000000000; -- cgit v1.2.3