From 5c166e76e52cdaf6ea97952c17d3d79185a59f96 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 21 Jul 2016 14:23:22 +0200
Subject: Added $initstate cell type and vlog function

---
 techlibs/common/simlib.v | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

(limited to 'techlibs')

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 38687489a..8ab124034 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1313,6 +1313,23 @@ endmodule
 
 // --------------------------------------------------------
 
+module \$initstate (Y);
+
+output reg Y = 1;
+reg [3:0] cnt = 1;
+reg trig = 0;
+
+initial trig <= 1;
+
+always @(cnt, trig) begin
+	Y <= |cnt;
+	cnt <= cnt + |cnt;
+end
+
+endmodule
+
+// --------------------------------------------------------
+
 module \$equiv (A, B, Y);
 
 input A, B;
-- 
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