From 489caf32c54ee250338eca72c5f0098106d17788 Mon Sep 17 00:00:00 2001 From: Andrew Zonenberg Date: Wed, 30 Mar 2016 01:07:20 -0700 Subject: Initial work on greenpak4 counter extraction. Doesn't work but a decent start --- techlibs/greenpak4/cells_sim.v | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) (limited to 'techlibs') diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index 3acea01d2..6e3003f5e 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -91,6 +91,33 @@ module GP_COUNT8(input CLK, input wire RST, output reg OUT); parameter CLKIN_DIVIDE = 1; //more complex hard IP blocks are not supported for simulation yet + + reg[7:0] count = COUNT_TO; + + //Combinatorially output whenever we wrap low + always @(*) begin + OUT <= (count == 8'h0); + end + + //datasheet is unclear but experimental testing confirms that POR value is COUNT_TO. + //Reset value is clearly 0 except in count/FSM cells where it's configurable. + //Datasheet seems to indicate that reset is asynchronous, but for now we model as sync due to Yosys issues... + always @(posedge CLK) begin + + count <= count - 1'd1; + + if(count == 0) + count <= COUNT_MAX; + + /* + if((RESET_MODE == "RISING") && RST) + count <= 0; + if((RESET_MODE == "FALLING") && !RST) + count <= 0; + if((RESET_MODE == "BITH") && RST) + count <= 0; + */ + end endmodule -- cgit v1.2.3