From 0f6cf8b8e4c3574aefae9f613161a5a5648fb04f Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tristan.gingold@cern.ch>
Date: Wed, 24 Nov 2021 17:09:59 +0100
Subject: sf2: add a test for $alu gate

---
 techlibs/sf2/tests/test_arith.ys | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)
 create mode 100644 techlibs/sf2/tests/test_arith.ys

(limited to 'techlibs')

diff --git a/techlibs/sf2/tests/test_arith.ys b/techlibs/sf2/tests/test_arith.ys
new file mode 100644
index 000000000..da7b96602
--- /dev/null
+++ b/techlibs/sf2/tests/test_arith.ys
@@ -0,0 +1,22 @@
+# Our implementation
+read_verilog ../arith_map.v
+read_verilog ../cells_sim.v
+read_verilog -DSIMLIB_NOCHECKS ../../common/simlib.v
+rename \$__SF2_ALU gate
+hierarchy -top gate -chparam A_WIDTH 4 -chparam B_WIDTH 5 -chparam Y_WIDTH 5
+flatten
+opt
+write_verilog gate.v
+
+# The reference
+read_verilog -DSIMLIB_NOCHECKS ../../common/simlib.v
+rename \$alu gold
+hierarchy -top gold -chparam A_WIDTH 4 -chparam B_WIDTH 5 -chparam Y_WIDTH 5
+flatten
+proc
+clean
+write_verilog gold.v
+
+read_verilog gate.v
+miter -equiv -flatten -make_outputs gold gate miter
+sat -verify -prove trigger 0 -show-ports miter
-- 
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