From fc3d74616f284eaccdc7d105cd77572953602d7f Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 12 Jul 2019 00:50:42 -0700
Subject: Combine SB_CARRY+SB_LUT into one $__ICE40_CARRY_LUT4 box

---
 techlibs/ice40/abc_hx.box | 12 ++++--------
 techlibs/ice40/abc_lp.box | 12 ++++--------
 techlibs/ice40/abc_u.box  | 14 +++++---------
 3 files changed, 13 insertions(+), 25 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/ice40/abc_hx.box b/techlibs/ice40/abc_hx.box
index f8e12b527..4b55297dd 100644
--- a/techlibs/ice40/abc_hx.box
+++ b/techlibs/ice40/abc_hx.box
@@ -3,15 +3,11 @@
 # NB: Inputs/Outputs must be ordered alphabetically
 #     (with exceptions for carry in/out)
 
-# Inputs: I0 I1 CI
-# Outputs: CO
+# Inputs: A B CI
+# Outputs: O CO
 #   (NB: carry chain input/output must be last
 #        input/output and have been moved there
 #        overriding the alphabetical ordering)
-SB_CARRY 1 1 3 1
+$__ICE40_CARRY_LUT4 1 1 3 2
+400 379 316
 259 231 126
-
-# Inputs: I0 I1 I2 I3
-# Outputs: O
-SB_LUT4 2 1 4 1
-449 400 379 316
diff --git a/techlibs/ice40/abc_lp.box b/techlibs/ice40/abc_lp.box
index fbe4c56e6..b85346370 100644
--- a/techlibs/ice40/abc_lp.box
+++ b/techlibs/ice40/abc_lp.box
@@ -3,15 +3,11 @@
 # NB: Inputs/Outputs must be ordered alphabetically
 #     (with exceptions for carry in/out)
 
-# Inputs: CI I0 I1
-# Outputs: CO
+# Inputs: A B CI
+# Outputs: O CO
 #   (NB: carry chain input/output must be last
 #        input/output and have been moved there
 #        overriding the alphabetical ordering)
-SB_CARRY 1 1 3 1
+$__ICE40_CARRY_LUT4 1 1 3 2
+589 558 465
 675 609 186 
-
-# Inputs: I0 I1 I2 I3
-# Outputs: O
-SB_LUT4 2 1 4 1
-661 589 558 465
diff --git a/techlibs/ice40/abc_u.box b/techlibs/ice40/abc_u.box
index f44deabc4..3a71addef 100644
--- a/techlibs/ice40/abc_u.box
+++ b/techlibs/ice40/abc_u.box
@@ -3,15 +3,11 @@
 # NB: Inputs/Outputs must be ordered alphabetically
 #     (with exceptions for carry in/out)
 
-# Inputs: I0 I1 CI
-# Outputs: CO
+# Inputs: A B CI
+# Outputs: O CO
 #   (NB: carry chain input/output must be last
 #        input/output and have been moved there
 #        overriding the alphabetical ordering)
-SB_CARRY 1 1 3 1
-675 609 278
-
-# Inputs: I0 I1 I2 I3
-# Outputs: O
-SB_LUT4 2 1 4 1
-1285 1231 1205 874
+$__ICE40_CARRY_LUT4 1 1 3 2
+1231 1205 875
+675  609  278
-- 
cgit v1.2.3


From c6e16e1334dcbd8bb556ab566130cc7936f06a69 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 12 Jul 2019 00:51:37 -0700
Subject: _ABC macro will map and unmap to this new box

---
 techlibs/ice40/arith_map.v | 10 ++++++++++
 techlibs/ice40/cells_map.v | 24 ++++++++++++++++++++++++
 2 files changed, 34 insertions(+)

(limited to 'techlibs')

diff --git a/techlibs/ice40/arith_map.v b/techlibs/ice40/arith_map.v
index 4449fdc1b..6d45e4a6b 100644
--- a/techlibs/ice40/arith_map.v
+++ b/techlibs/ice40/arith_map.v
@@ -44,6 +44,15 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO);
 
 	genvar i;
 	generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
+`ifdef _ABC
+		\$__ICE40_CARRY_LUT4 carry (
+			.A(AA[i]),
+			.B(BB[i]),
+			.CI(C[i]),
+			.CO(CO[i]),
+            .O(Y[i])
+		);
+`else
 		SB_CARRY carry (
 			.I0(AA[i]),
 			.I1(BB[i]),
@@ -63,6 +72,7 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO);
 			.I3(C[i]),
 			.O(Y[i])
 		);
+`endif
 	end endgenerate
 
 	assign X = AA ^ BB;
diff --git a/techlibs/ice40/cells_map.v b/techlibs/ice40/cells_map.v
index 759549e30..5dca63e19 100644
--- a/techlibs/ice40/cells_map.v
+++ b/techlibs/ice40/cells_map.v
@@ -61,3 +61,27 @@ module \$lut (A, Y);
   endgenerate
 endmodule
 `endif
+
+`ifdef _ABC
+module \$__ICE40_CARRY_LUT4 (output CO, O, input A, B, CI);
+  SB_CARRY carry (
+    .I0(A),
+    .I1(B),
+    .CI(CI),
+    .CO(CO)
+  );
+  SB_LUT4 #(
+    //         I0: 1010 1010 1010 1010
+    //         I1: 1100 1100 1100 1100
+    //         I2: 1111 0000 1111 0000
+    //         I3: 1111 1111 0000 0000
+    .LUT_INIT(16'b 0110_1001_1001_0110)
+  ) adder (
+    .I0(1'b0),
+    .I1(A),
+    .I2(B),
+    .I3(CI),
+    .O(O)
+  );
+endmodule
+`endif
-- 
cgit v1.2.3


From a79ff2501e7b73b4af958d23d247951b107bb054 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 12 Jul 2019 00:52:19 -0700
Subject: Add new box to cells_sim.v

---
 techlibs/ice40/cells_sim.v | 27 +++++++++++++++++++++++++--
 1 file changed, 25 insertions(+), 2 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index b746ba4e5..cf36f5cfb 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -127,7 +127,7 @@ endmodule
 
 // SiliconBlue Logic Cells
 
-(* abc_box_id = 2, lib_whitebox *)
+(* lib_whitebox *)
 module SB_LUT4 (output O, input I0, I1, I2, I3);
 	parameter [15:0] LUT_INIT = 0;
 	wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
@@ -136,11 +136,34 @@ module SB_LUT4 (output O, input I0, I1, I2, I3);
 	assign O = I0 ? s1[1] : s1[0];
 endmodule
 
-(* abc_box_id = 1, abc_carry="CI,CO", lib_whitebox *)
+(* lib_whitebox *)
 module SB_CARRY (output CO, input I0, I1, CI);
 	assign CO = (I0 && I1) || ((I0 || I1) && CI);
 endmodule
 
+(* abc_box_id = 1, abc_carry="CI,CO", lib_whitebox *)
+module \$__ICE40_CARRY_LUT4 (output CO, O, input A, B, CI);
+	SB_CARRY carry (
+		.I0(A),
+		.I1(B),
+		.CI(CI),
+		.CO(CO)
+	);
+	SB_LUT4 #(
+		//         I0: 1010 1010 1010 1010
+		//         I1: 1100 1100 1100 1100
+		//         I2: 1111 0000 1111 0000
+		//         I3: 1111 1111 0000 0000
+		.LUT_INIT(16'b 0110_1001_1001_0110)
+	) adder (
+		.I0(1'b0),
+		.I1(A),
+		.I2(B),
+		.I3(CI),
+		.O(O)
+	);
+endmodule
+
 // Positive Edge SiliconBlue FF Cells
 
 module SB_DFF (output `SB_DFF_REG, input C, D);
-- 
cgit v1.2.3


From 0f5bddcd792ed2da2b9a3eb12e775537f394e771 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 12 Jul 2019 00:52:31 -0700
Subject: ice40_opt to handle this box and opt back to SB_LUT4

---
 techlibs/ice40/ice40_opt.cc | 48 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)

(limited to 'techlibs')

diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index f528607d6..b22fc83fe 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -83,6 +83,54 @@ static void run_ice40_opts(Module *module)
 			}
 			continue;
 		}
+
+		if (cell->type == "$__ICE40_CARRY_LUT4")
+		{
+			SigSpec non_const_inputs, replacement_output;
+			int count_zeros = 0, count_ones = 0;
+
+			SigBit inbit[3] = {
+				cell->getPort("\\A"),
+				cell->getPort("\\B"),
+				cell->getPort("\\CI")
+			};
+			for (int i = 0; i < 3; i++)
+				if (inbit[i].wire == nullptr) {
+					if (inbit[i] == State::S1)
+						count_ones++;
+					else
+						count_zeros++;
+				} else
+					non_const_inputs.append(inbit[i]);
+
+			if (count_zeros >= 2)
+				replacement_output = State::S0;
+			else if (count_ones >= 2)
+				replacement_output = State::S1;
+			else if (GetSize(non_const_inputs) == 1)
+				replacement_output = non_const_inputs;
+
+			if (GetSize(replacement_output)) {
+				optimized_co.insert(sigmap(cell->getPort("\\CO")[0]));
+				module->connect(cell->getPort("\\CO")[0], replacement_output);
+				module->design->scratchpad_set_bool("opt.did_something", true);
+				log("Optimized SB_CARRY from $__ICE40_CARRY_LUT4 cell (leaving behind SB_LUT4) %s.%s: CO=%s\n",
+						log_id(module), log_id(cell), log_signal(replacement_output));
+				cell->type = "\\SB_LUT4";
+				sb_lut_cells.push_back(cell);
+				cell->setPort("\\I0", RTLIL::S0);
+				cell->setPort("\\I1", inbit[0]);
+				cell->setPort("\\I2", inbit[1]);
+				cell->setPort("\\I3", inbit[2]);
+				cell->unsetPort("\\A");
+				cell->unsetPort("\\B");
+				cell->unsetPort("\\CI");
+				cell->unsetPort("\\CO");
+				cell->setParam("\\LUT_INIT", std::string("0110100110010110"));
+				sb_lut_cells.push_back(cell);
+			}
+			continue;
+		}
 	}
 
 	for (auto cell : sb_lut_cells)
-- 
cgit v1.2.3


From 62ac5ebd02e18add18a11f4c19002f4059b091b7 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 12 Jul 2019 00:53:01 -0700
Subject: Map to and from this box if -abc9

---
 techlibs/ice40/synth_ice40.cc | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 2c75215cb..59f6d1863 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -242,7 +242,7 @@ struct SynthIce40Pass : public ScriptPass
 	{
 		if (check_label("begin"))
 		{
-			run("read_verilog -lib -D_ABC +/ice40/cells_sim.v");
+			run("read_verilog -icells -lib -D_ABC +/ice40/cells_sim.v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 			run("proc");
 		}
@@ -298,7 +298,7 @@ struct SynthIce40Pass : public ScriptPass
 			if (nocarry)
 				run("techmap");
 			else
-				run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
+				run("techmap -map +/techmap.v -map +/ice40/arith_map.v" + std::string(abc == "abc9" ? " -D _ABC" : ""));
 			if (retime || help_mode)
 				run(abc + " -dff", "(only if -retime)");
 			run("ice40_opt");
@@ -342,6 +342,7 @@ struct SynthIce40Pass : public ScriptPass
 					else
 						wire_delay = 250;
 					run(abc + stringf(" -W %d -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", wire_delay, device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
+					run("techmap -D NO_LUT -D _ABC -map +/ice40/cells_map.v");
 				}
 				else
 					run(abc + " -dress -lut 4", "(skip if -noabc)");
-- 
cgit v1.2.3


From 4de03bd5e6cd72b3eb2a70d5735e7526d7a6f8a8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 12 Jul 2019 01:08:48 -0700
Subject: Remove double push

---
 techlibs/ice40/ice40_opt.cc | 1 -
 1 file changed, 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index b22fc83fe..4e50b250e 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -117,7 +117,6 @@ static void run_ice40_opts(Module *module)
 				log("Optimized SB_CARRY from $__ICE40_CARRY_LUT4 cell (leaving behind SB_LUT4) %s.%s: CO=%s\n",
 						log_id(module), log_id(cell), log_signal(replacement_output));
 				cell->type = "\\SB_LUT4";
-				sb_lut_cells.push_back(cell);
 				cell->setPort("\\I0", RTLIL::S0);
 				cell->setPort("\\I1", inbit[0]);
 				cell->setPort("\\I2", inbit[1]);
-- 
cgit v1.2.3


From e0e5d7d68eee0d1a83b048d9d9fde94673ff5673 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 12 Jul 2019 01:15:22 -0700
Subject: Fix spacing

---
 techlibs/ice40/arith_map.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/ice40/arith_map.v b/techlibs/ice40/arith_map.v
index 6d45e4a6b..abba18c37 100644
--- a/techlibs/ice40/arith_map.v
+++ b/techlibs/ice40/arith_map.v
@@ -50,7 +50,7 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO);
 			.B(BB[i]),
 			.CI(C[i]),
 			.CO(CO[i]),
-            .O(Y[i])
+			.O(Y[i])
 		);
 `else
 		SB_CARRY carry (
-- 
cgit v1.2.3


From 28274dfb09fb48637f82949ce601a417eb3d0b82 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 12 Jul 2019 01:17:53 -0700
Subject: Off by one

---
 techlibs/ice40/abc_u.box | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/ice40/abc_u.box b/techlibs/ice40/abc_u.box
index 3a71addef..95c2c3d81 100644
--- a/techlibs/ice40/abc_u.box
+++ b/techlibs/ice40/abc_u.box
@@ -9,5 +9,5 @@
 #        input/output and have been moved there
 #        overriding the alphabetical ordering)
 $__ICE40_CARRY_LUT4 1 1 3 2
-1231 1205 875
+1231 1205 874
 675  609  278
-- 
cgit v1.2.3


From 7a912f22b2c3976d72a25ffd605a1cf598b67983 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 12 Jul 2019 01:32:10 -0700
Subject: Use Const::from_string() not its constructor...

---
 techlibs/ice40/ice40_opt.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index 4e50b250e..67e8771b4 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -125,7 +125,7 @@ static void run_ice40_opts(Module *module)
 				cell->unsetPort("\\B");
 				cell->unsetPort("\\CI");
 				cell->unsetPort("\\CO");
-				cell->setParam("\\LUT_INIT", std::string("0110100110010110"));
+				cell->setParam("\\LUT_INIT", RTLIL::Const::from_string("0110100110010110"));
 				sb_lut_cells.push_back(cell);
 			}
 			continue;
-- 
cgit v1.2.3


From d032198facc05634bd617328e1865e7f0d8d953c Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 13 Jul 2019 01:11:00 -0700
Subject: ice40_opt to $__ICE40_CARRY_LUT4 into $lut not SB_LUT

---
 techlibs/ice40/ice40_opt.cc | 16 +++++++---------
 1 file changed, 7 insertions(+), 9 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index 67e8771b4..38910dffa 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -114,19 +114,17 @@ static void run_ice40_opts(Module *module)
 				optimized_co.insert(sigmap(cell->getPort("\\CO")[0]));
 				module->connect(cell->getPort("\\CO")[0], replacement_output);
 				module->design->scratchpad_set_bool("opt.did_something", true);
-				log("Optimized SB_CARRY from $__ICE40_CARRY_LUT4 cell (leaving behind SB_LUT4) %s.%s: CO=%s\n",
+				log("Optimized $__ICE40_CARRY_LUT4 cell into $lut (without SB_CARRY) %s.%s: CO=%s\n",
 						log_id(module), log_id(cell), log_signal(replacement_output));
-				cell->type = "\\SB_LUT4";
-				cell->setPort("\\I0", RTLIL::S0);
-				cell->setPort("\\I1", inbit[0]);
-				cell->setPort("\\I2", inbit[1]);
-				cell->setPort("\\I3", inbit[2]);
-				cell->unsetPort("\\A");
+				cell->type = "$lut";
+				cell->setPort("\\A", { RTLIL::S0, inbit[0], inbit[1], inbit[2] });
+				cell->setPort("\\Y", cell->getPort("\\O"));
 				cell->unsetPort("\\B");
 				cell->unsetPort("\\CI");
 				cell->unsetPort("\\CO");
-				cell->setParam("\\LUT_INIT", RTLIL::Const::from_string("0110100110010110"));
-				sb_lut_cells.push_back(cell);
+				cell->unsetPort("\\O");
+				cell->setParam("\\LUT", RTLIL::Const::from_string("0110100110010110"));
+				cell->setParam("\\WIDTH", 4);
 			}
 			continue;
 		}
-- 
cgit v1.2.3


From 5fb27c071bb072644dbb38cf8a516628c2afe15b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 15 Jul 2019 12:03:51 -0700
Subject: $__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark

---
 techlibs/ice40/abc_hx.box   | 2 +-
 techlibs/ice40/abc_lp.box   | 2 +-
 techlibs/ice40/abc_u.box    | 2 +-
 techlibs/ice40/arith_map.v  | 2 +-
 techlibs/ice40/cells_map.v  | 2 +-
 techlibs/ice40/cells_sim.v  | 2 +-
 techlibs/ice40/ice40_opt.cc | 4 ++--
 7 files changed, 8 insertions(+), 8 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/ice40/abc_hx.box b/techlibs/ice40/abc_hx.box
index 4b55297dd..c0ea742e2 100644
--- a/techlibs/ice40/abc_hx.box
+++ b/techlibs/ice40/abc_hx.box
@@ -8,6 +8,6 @@
 #   (NB: carry chain input/output must be last
 #        input/output and have been moved there
 #        overriding the alphabetical ordering)
-$__ICE40_CARRY_LUT4 1 1 3 2
+$__ICE40_FULL_ADDER 1 1 3 2
 400 379 316
 259 231 126
diff --git a/techlibs/ice40/abc_lp.box b/techlibs/ice40/abc_lp.box
index b85346370..d73b6d649 100644
--- a/techlibs/ice40/abc_lp.box
+++ b/techlibs/ice40/abc_lp.box
@@ -8,6 +8,6 @@
 #   (NB: carry chain input/output must be last
 #        input/output and have been moved there
 #        overriding the alphabetical ordering)
-$__ICE40_CARRY_LUT4 1 1 3 2
+$__ICE40_FULL_ADDER 1 1 3 2
 589 558 465
 675 609 186 
diff --git a/techlibs/ice40/abc_u.box b/techlibs/ice40/abc_u.box
index 95c2c3d81..42d666051 100644
--- a/techlibs/ice40/abc_u.box
+++ b/techlibs/ice40/abc_u.box
@@ -8,6 +8,6 @@
 #   (NB: carry chain input/output must be last
 #        input/output and have been moved there
 #        overriding the alphabetical ordering)
-$__ICE40_CARRY_LUT4 1 1 3 2
+$__ICE40_FULL_ADDER 1 1 3 2
 1231 1205 874
 675  609  278
diff --git a/techlibs/ice40/arith_map.v b/techlibs/ice40/arith_map.v
index abba18c37..fe83a8e38 100644
--- a/techlibs/ice40/arith_map.v
+++ b/techlibs/ice40/arith_map.v
@@ -45,7 +45,7 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO);
 	genvar i;
 	generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
 `ifdef _ABC
-		\$__ICE40_CARRY_LUT4 carry (
+		\$__ICE40_FULL_ADDER carry (
 			.A(AA[i]),
 			.B(BB[i]),
 			.CI(C[i]),
diff --git a/techlibs/ice40/cells_map.v b/techlibs/ice40/cells_map.v
index 5dca63e19..b4b831165 100644
--- a/techlibs/ice40/cells_map.v
+++ b/techlibs/ice40/cells_map.v
@@ -63,7 +63,7 @@ endmodule
 `endif
 
 `ifdef _ABC
-module \$__ICE40_CARRY_LUT4 (output CO, O, input A, B, CI);
+module \$__ICE40_FULL_ADDER (output CO, O, input A, B, CI);
   SB_CARRY carry (
     .I0(A),
     .I1(B),
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index cf36f5cfb..609facc93 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -142,7 +142,7 @@ module SB_CARRY (output CO, input I0, I1, CI);
 endmodule
 
 (* abc_box_id = 1, abc_carry="CI,CO", lib_whitebox *)
-module \$__ICE40_CARRY_LUT4 (output CO, O, input A, B, CI);
+module \$__ICE40_FULL_ADDER (output CO, O, input A, B, CI);
 	SB_CARRY carry (
 		.I0(A),
 		.I1(B),
diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index 38910dffa..e492454fb 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -84,7 +84,7 @@ static void run_ice40_opts(Module *module)
 			continue;
 		}
 
-		if (cell->type == "$__ICE40_CARRY_LUT4")
+		if (cell->type == "$__ICE40_FULL_ADDER")
 		{
 			SigSpec non_const_inputs, replacement_output;
 			int count_zeros = 0, count_ones = 0;
@@ -114,7 +114,7 @@ static void run_ice40_opts(Module *module)
 				optimized_co.insert(sigmap(cell->getPort("\\CO")[0]));
 				module->connect(cell->getPort("\\CO")[0], replacement_output);
 				module->design->scratchpad_set_bool("opt.did_something", true);
-				log("Optimized $__ICE40_CARRY_LUT4 cell into $lut (without SB_CARRY) %s.%s: CO=%s\n",
+				log("Optimized $__ICE40_FULL_ADDER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n",
 						log_id(module), log_id(cell), log_signal(replacement_output));
 				cell->type = "$lut";
 				cell->setPort("\\A", { RTLIL::S0, inbit[0], inbit[1], inbit[2] });
-- 
cgit v1.2.3


From 7a58ee78dc8bd2c257498dc947081a1bba7bb54f Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 16 Jul 2019 12:45:29 -0700
Subject: gen_lut to return correctly sized LUT mask

---
 techlibs/common/cmp2lut.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/common/cmp2lut.v b/techlibs/common/cmp2lut.v
index 8aa1eb957..0d0757767 100644
--- a/techlibs/common/cmp2lut.v
+++ b/techlibs/common/cmp2lut.v
@@ -27,7 +27,7 @@ parameter _TECHMAP_CONSTVAL_A_ = 0;
 parameter _TECHMAP_CONSTMSK_B_ = 0;
 parameter _TECHMAP_CONSTVAL_B_ = 0;
 
-function automatic integer gen_lut;
+function automatic [(1 << `LUT_WIDTH)-1:0] gen_lut;
 	input integer width;
 	input integer operation;
 	input integer swap;
-- 
cgit v1.2.3


From ba099bfe9befccc42df99d2930fdbc686152187c Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Thu, 11 Jul 2019 10:56:59 +0000
Subject: synth_{ice40,ecp5}: more sensible pass label naming.

---
 techlibs/ecp5/synth_ecp5.cc   | 10 +++++++---
 techlibs/ice40/synth_ice40.cc |  4 ++--
 2 files changed, 9 insertions(+), 5 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 9f409ca51..3d189a9f1 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -231,23 +231,27 @@ struct SynthEcp5Pass : public ScriptPass
 			run("synth -run coarse");
 		}
 
-		if (!nobram && check_label("bram", "(skip if -nobram)"))
+		if (!nobram && check_label("map_bram", "(skip if -nobram)"))
 		{
 			run("memory_bram -rules +/ecp5/bram.txt");
 			run("techmap -map +/ecp5/brams_map.v");
 		}
 
-		if (!nodram && check_label("dram", "(skip if -nodram)"))
+		if (!nodram && check_label("map_dram", "(skip if -nodram)"))
 		{
 			run("memory_bram -rules +/ecp5/dram.txt");
 			run("techmap -map +/ecp5/drams_map.v");
 		}
 
-		if (check_label("fine"))
+		if (check_label("map_ffram"))
 		{
 			run("opt -fast -mux_undef -undriven -fine");
 			run("memory_map");
 			run("opt -undriven -fine");
+		}
+
+		if (check_label("map_gates"))
+		{
 			if (noccu2)
 				run("techmap");
 			else
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 0474e76e9..1a20f7049 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -275,14 +275,14 @@ struct SynthIce40Pass : public ScriptPass
 			run("opt_clean");
 		}
 
-		if (!nobram && check_label("bram", "(skip if -nobram)"))
+		if (!nobram && check_label("map_bram", "(skip if -nobram)"))
 		{
 			run("memory_bram -rules +/ice40/brams.txt");
 			run("techmap -map +/ice40/brams_map.v");
 			run("ice40_braminit");
 		}
 
-		if (check_label("map"))
+		if (check_label("map_ffram"))
 		{
 			run("opt -fast -mux_undef -undriven -fine");
 			run("memory_map");
-- 
cgit v1.2.3


From 698ab9beeed7ee585117cc1e5f5126a9092942df Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Tue, 16 Jul 2019 20:44:55 +0000
Subject: synth_ecp5: rename dram to lutram everywhere.

---
 techlibs/ecp5/Makefile.inc  |  4 ++--
 techlibs/ecp5/dram.txt      | 17 -----------------
 techlibs/ecp5/drams_map.v   | 28 ----------------------------
 techlibs/ecp5/lutram.txt    | 17 +++++++++++++++++
 techlibs/ecp5/lutrams_map.v | 28 ++++++++++++++++++++++++++++
 techlibs/ecp5/synth_ecp5.cc | 22 +++++++++++-----------
 6 files changed, 58 insertions(+), 58 deletions(-)
 delete mode 100644 techlibs/ecp5/dram.txt
 delete mode 100644 techlibs/ecp5/drams_map.v
 create mode 100644 techlibs/ecp5/lutram.txt
 create mode 100644 techlibs/ecp5/lutrams_map.v

(limited to 'techlibs')

diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc
index ff39ba4fe..73e18112f 100644
--- a/techlibs/ecp5/Makefile.inc
+++ b/techlibs/ecp5/Makefile.inc
@@ -4,8 +4,8 @@ OBJS += techlibs/ecp5/synth_ecp5.o techlibs/ecp5/ecp5_ffinit.o
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_map.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_sim.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_bb.v))
-$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/drams_map.v))
-$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/dram.txt))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/lutrams_map.v))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/lutram.txt))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/brams_map.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram.txt))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/arith_map.v))
diff --git a/techlibs/ecp5/dram.txt b/techlibs/ecp5/dram.txt
deleted file mode 100644
index b94357429..000000000
--- a/techlibs/ecp5/dram.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-bram $__TRELLIS_DPR16X4
-  init 1
-  abits 4
-  dbits 4
-  groups 2
-  ports  1 1
-  wrmode 0 1
-  enable 0 1
-  transp 0 0
-  clocks 0 1
-  clkpol 0 2
-endbram
-
-match $__TRELLIS_DPR16X4
-  make_outreg
-  min wports 1
-endmatch
diff --git a/techlibs/ecp5/drams_map.v b/techlibs/ecp5/drams_map.v
deleted file mode 100644
index 3b3de831f..000000000
--- a/techlibs/ecp5/drams_map.v
+++ /dev/null
@@ -1,28 +0,0 @@
-module \$__TRELLIS_DPR16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
-	parameter [63:0] INIT = 64'bx;
-	parameter CLKPOL2 = 1;
-	input CLK1;
-
-	input [3:0] A1ADDR;
-	output [3:0] A1DATA;
-
-	input [3:0] B1ADDR;
-	input [3:0] B1DATA;
-	input B1EN;
-
-	localparam WCKMUX = CLKPOL2 ? "WCK" : "INV";
-
-	TRELLIS_DPR16X4 #(
-		.INITVAL(INIT),
-		.WCKMUX(WCKMUX),
-		.WREMUX("WRE")
-	) _TECHMAP_REPLACE_ (
-		.RAD(A1ADDR),
-		.DO(A1DATA),
-
-		.WAD(B1ADDR),
-		.DI(B1DATA),
-		.WCK(CLK1),
-		.WRE(B1EN)
-	);
-endmodule
diff --git a/techlibs/ecp5/lutram.txt b/techlibs/ecp5/lutram.txt
new file mode 100644
index 000000000..b94357429
--- /dev/null
+++ b/techlibs/ecp5/lutram.txt
@@ -0,0 +1,17 @@
+bram $__TRELLIS_DPR16X4
+  init 1
+  abits 4
+  dbits 4
+  groups 2
+  ports  1 1
+  wrmode 0 1
+  enable 0 1
+  transp 0 0
+  clocks 0 1
+  clkpol 0 2
+endbram
+
+match $__TRELLIS_DPR16X4
+  make_outreg
+  min wports 1
+endmatch
diff --git a/techlibs/ecp5/lutrams_map.v b/techlibs/ecp5/lutrams_map.v
new file mode 100644
index 000000000..3b3de831f
--- /dev/null
+++ b/techlibs/ecp5/lutrams_map.v
@@ -0,0 +1,28 @@
+module \$__TRELLIS_DPR16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
+	parameter [63:0] INIT = 64'bx;
+	parameter CLKPOL2 = 1;
+	input CLK1;
+
+	input [3:0] A1ADDR;
+	output [3:0] A1DATA;
+
+	input [3:0] B1ADDR;
+	input [3:0] B1DATA;
+	input B1EN;
+
+	localparam WCKMUX = CLKPOL2 ? "WCK" : "INV";
+
+	TRELLIS_DPR16X4 #(
+		.INITVAL(INIT),
+		.WCKMUX(WCKMUX),
+		.WREMUX("WRE")
+	) _TECHMAP_REPLACE_ (
+		.RAD(A1ADDR),
+		.DO(A1DATA),
+
+		.WAD(B1ADDR),
+		.DI(B1DATA),
+		.WCK(CLK1),
+		.WRE(B1EN)
+	);
+endmodule
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 3d189a9f1..143d1f95c 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -71,10 +71,10 @@ struct SynthEcp5Pass : public ScriptPass
 		log("        do not use flipflops with CE in output netlist\n");
 		log("\n");
 		log("    -nobram\n");
-		log("        do not use BRAM cells in output netlist\n");
+		log("        do not use block RAM cells in output netlist\n");
 		log("\n");
-		log("    -nodram\n");
-		log("        do not use distributed RAM cells in output netlist\n");
+		log("    -nolutram\n");
+		log("        do not use LUT RAM cells in output netlist\n");
 		log("\n");
 		log("    -nowidelut\n");
 		log("        do not use PFU muxes to implement LUTs larger than LUT4s\n");
@@ -96,7 +96,7 @@ struct SynthEcp5Pass : public ScriptPass
 	}
 
 	string top_opt, blif_file, edif_file, json_file;
-	bool noccu2, nodffe, nobram, nodram, nowidelut, flatten, retime, abc2, abc9, vpr;
+	bool noccu2, nodffe, nobram, nolutram, nowidelut, flatten, retime, abc2, abc9, vpr;
 
 	void clear_flags() YS_OVERRIDE
 	{
@@ -107,7 +107,7 @@ struct SynthEcp5Pass : public ScriptPass
 		noccu2 = false;
 		nodffe = false;
 		nobram = false;
-		nodram = false;
+		nolutram = false;
 		nowidelut = false;
 		flatten = true;
 		retime = false;
@@ -172,11 +172,11 @@ struct SynthEcp5Pass : public ScriptPass
 				nobram = true;
 				continue;
 			}
-			if (args[argidx] == "-nodram") {
-				nodram = true;
+			if (args[argidx] == "-nolutram" || /*deprecated alias*/ args[argidx] == "-nodram") {
+				nolutram = true;
 				continue;
 			}
-			if (args[argidx] == "-nowidelut" || args[argidx] == "-nomux") {
+			if (args[argidx] == "-nowidelut" || /*deprecated alias*/ args[argidx] == "-nomux") {
 				nowidelut = true;
 				continue;
 			}
@@ -237,10 +237,10 @@ struct SynthEcp5Pass : public ScriptPass
 			run("techmap -map +/ecp5/brams_map.v");
 		}
 
-		if (!nodram && check_label("map_dram", "(skip if -nodram)"))
+		if (!nolutram && check_label("map_lutram", "(skip if -nolutram)"))
 		{
-			run("memory_bram -rules +/ecp5/dram.txt");
-			run("techmap -map +/ecp5/drams_map.v");
+			run("memory_bram -rules +/ecp5/lutram.txt");
+			run("techmap -map +/ecp5/lutrams_map.v");
 		}
 
 		if (check_label("map_ffram"))
-- 
cgit v1.2.3


From f28e38de9994151ea4e22608441dbc9e116d7b8c Mon Sep 17 00:00:00 2001
From: Sylvain Munaut <tnt@246tNt.com>
Date: Tue, 16 Jul 2019 23:57:15 +0200
Subject: ice40: Adapt the relut process passes to the new $lut <=> SB_LUT4
 port map

The new mapping introduced in 437fec0d88b4a2ad172edf0d1a861a38845f3b1d
needed matching adaptation when converting and optimizing LUTs during
the relut process

Fixes #1187

(Diagnosis of the issue by @daveshah1 on IRC)

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
---
 techlibs/ice40/ice40_unlut.cc | 6 +++---
 techlibs/ice40/synth_ice40.cc | 2 +-
 2 files changed, 4 insertions(+), 4 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/ice40/ice40_unlut.cc b/techlibs/ice40/ice40_unlut.cc
index d16e6e6a3..f3f70ac1f 100644
--- a/techlibs/ice40/ice40_unlut.cc
+++ b/techlibs/ice40/ice40_unlut.cc
@@ -56,10 +56,10 @@ static void run_ice40_unlut(Module *module)
 			cell->unsetParam("\\LUT_INIT");
 
 			cell->setPort("\\A", SigSpec({
-				get_bit_or_zero(cell->getPort("\\I3")),
-				get_bit_or_zero(cell->getPort("\\I2")),
+				get_bit_or_zero(cell->getPort("\\I0")),
 				get_bit_or_zero(cell->getPort("\\I1")),
-				get_bit_or_zero(cell->getPort("\\I0"))
+				get_bit_or_zero(cell->getPort("\\I2")),
+				get_bit_or_zero(cell->getPort("\\I3"))
 			}));
 			cell->setPort("\\Y", cell->getPort("\\O")[0]);
 			cell->unsetPort("\\I0");
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index b3d30791a..78ac5ea13 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -345,7 +345,7 @@ struct SynthIce40Pass : public ScriptPass
 			}
 			run("clean");
 			run("ice40_unlut");
-			run("opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3");
+			run("opt_lut -dlogic SB_CARRY:I0=2:I1=1:CI=0");
 		}
 
 		if (check_label("map_cells"))
-- 
cgit v1.2.3


From c78ab8ebc53bc78d5f1910e311b1e4305df4ca48 Mon Sep 17 00:00:00 2001
From: Dan Ravensloft <dan.ravensloft@gmail.com>
Date: Thu, 18 Jul 2019 16:46:21 +0100
Subject: synth_intel: rename for consistency with #1184

Also fix a typo in the help message.
---
 techlibs/intel/synth_intel.cc | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc
index 09c9ba3af..4f355ce88 100644
--- a/techlibs/intel/synth_intel.cc
+++ b/techlibs/intel/synth_intel.cc
@@ -62,10 +62,10 @@ struct SynthIntelPass : public ScriptPass {
 		log("        synonymous to the end of the command list.\n");
 		log("\n");
 		log("    -noiopads\n");
-		log("        do not use altsyncram cells in output netlist\n");
+		log("        do not use IO pad cells in output netlist\n");
 		log("\n");
 		log("    -nobram\n");
-		log("        do not use altsyncram cells in output netlist\n");
+		log("        do not use block RAM cells in output netlist\n");
 		log("\n");
 		log("    -noflatten\n");
 		log("        do not flatten design before synthesis\n");
@@ -191,12 +191,12 @@ struct SynthIntelPass : public ScriptPass {
 			run("synth -run coarse");
 		}
 
-		if (!nobram && check_label("bram", "(skip if -nobram)")) {
+		if (!nobram && check_label("map_bram", "(skip if -nobram)")) {
 			run("memory_bram -rules +/intel/common/brams.txt");
 			run("techmap -map +/intel/common/brams_map.v");
 		}
 
-		if (check_label("fine")) {
+		if (check_label("map_ffram")) {
 			run("opt -fast -mux_undef -undriven -fine -full");
 			run("memory_map");
 			run("opt -undriven -fine");
-- 
cgit v1.2.3


From 060e77c09b51aabe712315d5fd655f62a765d62f Mon Sep 17 00:00:00 2001
From: Ben Widawsky <ben@bwidawsk.net>
Date: Mon, 8 Jul 2019 12:03:00 -0700
Subject: intel_synth: Minor code cleanups

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 techlibs/intel/synth_intel.cc | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc
index 09c9ba3af..69f3b6334 100644
--- a/techlibs/intel/synth_intel.cc
+++ b/techlibs/intel/synth_intel.cc
@@ -147,8 +147,12 @@ struct SynthIntelPass : public ScriptPass {
 
 		if (!design->full_selection())
 			log_cmd_error("This command only operates on fully selected designs!\n");
-		if (family_opt != "max10" && family_opt != "a10gx" && family_opt != "cyclonev" && family_opt != "cycloneiv" &&
-		    family_opt != "cycloneive" && family_opt != "cyclone10")
+		if (family_opt != "max10" &&
+		    family_opt != "a10gx" &&
+		    family_opt != "cyclonev" &&
+		    family_opt != "cycloneiv" &&
+		    family_opt != "cycloneive" &&
+		    family_opt != "cyclone10")
 			log_cmd_error("Invalid or not family specified: '%s'\n", family_opt.c_str());
 
 		log_header(design, "Executing SYNTH_INTEL pass.\n");
-- 
cgit v1.2.3


From 809b94a67b0b666018b35536d4de327e99378a6f Mon Sep 17 00:00:00 2001
From: Ben Widawsky <ben@bwidawsk.net>
Date: Mon, 8 Jul 2019 12:24:24 -0700
Subject: intel_synth: Make family explicit and match

The help and code default to MAX10 for the family, however the couple of
if ladders defaulted to cycloneive. Fix this inconsistency and the next
patch will clean it up.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 techlibs/intel/synth_intel.cc | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc
index 69f3b6334..9d5d593a4 100644
--- a/techlibs/intel/synth_intel.cc
+++ b/techlibs/intel/synth_intel.cc
@@ -176,8 +176,10 @@ struct SynthIntelPass : public ScriptPass {
 				run("read_verilog -sv -lib +/intel/cyclone10/cells_sim.v");
 			else if (check_label("family") && family_opt == "cycloneiv")
 				run("read_verilog -sv -lib +/intel/cycloneiv/cells_sim.v");
-			else
+			else if (check_label("family") && family_opt == "cycloneive")
 				run("read_verilog -sv -lib +/intel/cycloneive/cells_sim.v");
+			else
+				log_cmd_error("Invalid or not family specified: '%s'\n", family_opt.c_str());
 			// Misc and common cells
 			run("read_verilog -sv -lib +/intel/common/m9k_bb.v");
 			run("read_verilog -sv -lib +/intel/common/altpll_bb.v");
@@ -236,8 +238,10 @@ struct SynthIntelPass : public ScriptPass {
 				run("techmap -map +/intel/cyclone10/cells_map.v");
 			else if (family_opt == "cycloneiv")
 				run("techmap -map +/intel/cycloneiv/cells_map.v");
-			else
+			else if (family_opt == "cycloneive")
 				run("techmap -map +/intel/cycloneive/cells_map.v");
+			else
+				log_cmd_error("Invalid or not family specified: '%s'\n", family_opt.c_str());
 			run("dffinit -highlow -ff dffeas q power_up");
 			run("clean -purge");
 		}
-- 
cgit v1.2.3


From f950a7a75d4353e0e31c523365a10926bc6180af Mon Sep 17 00:00:00 2001
From: Ben Widawsky <ben@bwidawsk.net>
Date: Mon, 8 Jul 2019 12:37:24 -0700
Subject: intel_synth: Small code cleanup to remove if ladder

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 techlibs/intel/synth_intel.cc | 38 ++++++++++----------------------------
 1 file changed, 10 insertions(+), 28 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc
index 9d5d593a4..5d6254ff6 100644
--- a/techlibs/intel/synth_intel.cc
+++ b/techlibs/intel/synth_intel.cc
@@ -166,20 +166,12 @@ struct SynthIntelPass : public ScriptPass {
 	void script() YS_OVERRIDE
 	{
 		if (check_label("begin")) {
-			if (check_label("family") && family_opt == "max10")
-				run("read_verilog -sv -lib +/intel/max10/cells_sim.v");
-			else if (check_label("family") && family_opt == "a10gx")
-				run("read_verilog -sv -lib +/intel/a10gx/cells_sim.v");
-			else if (check_label("family") && family_opt == "cyclonev")
-				run("read_verilog -sv -lib +/intel/cyclonev/cells_sim.v");
-			else if (check_label("family") && family_opt == "cyclone10")
-				run("read_verilog -sv -lib +/intel/cyclone10/cells_sim.v");
-			else if (check_label("family") && family_opt == "cycloneiv")
-				run("read_verilog -sv -lib +/intel/cycloneiv/cells_sim.v");
-			else if (check_label("family") && family_opt == "cycloneive")
-				run("read_verilog -sv -lib +/intel/cycloneive/cells_sim.v");
-			else
-				log_cmd_error("Invalid or not family specified: '%s'\n", family_opt.c_str());
+			string cmd = "read_verilog -sv -lib +/intel/FAMILY/cells_sim.v";
+			cmd.replace(cmd.find("FAMILY"), 6, family_opt);
+
+			if (check_label("family"))
+				run(cmd);
+
 			// Misc and common cells
 			run("read_verilog -sv -lib +/intel/common/m9k_bb.v");
 			run("read_verilog -sv -lib +/intel/common/altpll_bb.v");
@@ -228,20 +220,10 @@ struct SynthIntelPass : public ScriptPass {
 		if (check_label("map_cells")) {
 			if (!noiopads)
 				run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I", "(unless -noiopads)");
-			if (family_opt == "max10")
-				run("techmap -map +/intel/max10/cells_map.v");
-			else if (family_opt == "a10gx")
-				run("techmap -map +/intel/a10gx/cells_map.v");
-			else if (family_opt == "cyclonev")
-				run("techmap -map +/intel/cyclonev/cells_map.v");
-			else if (family_opt == "cyclone10")
-				run("techmap -map +/intel/cyclone10/cells_map.v");
-			else if (family_opt == "cycloneiv")
-				run("techmap -map +/intel/cycloneiv/cells_map.v");
-			else if (family_opt == "cycloneive")
-				run("techmap -map +/intel/cycloneive/cells_map.v");
-			else
-				log_cmd_error("Invalid or not family specified: '%s'\n", family_opt.c_str());
+			string cmd = "techmap -map +/intel/FAMILY/cells_map.v";
+			cmd.replace(cmd.find("FAMILY"), 6, family_opt);
+			run(cmd);
+
 			run("dffinit -highlow -ff dffeas q power_up");
 			run("clean -purge");
 		}
-- 
cgit v1.2.3


From 999811572a652a60003b98b120a5e2da20aad059 Mon Sep 17 00:00:00 2001
From: Ben Widawsky <ben@bwidawsk.net>
Date: Mon, 8 Jul 2019 12:41:22 -0700
Subject: intel_synth: Fix help message

cyclonev has been a "supported" family since the initial commit. The old
commit message suggested to use a10gx which is incorrect.

Aside from the obvious lack of functional change due to this just being
a help message, users who were previously using "a10gx" for "cyclonev" will
also have no functional change by using "cyclonev" instead.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 techlibs/intel/synth_intel.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs')

diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc
index 5d6254ff6..0b44a835f 100644
--- a/techlibs/intel/synth_intel.cc
+++ b/techlibs/intel/synth_intel.cc
@@ -40,7 +40,7 @@ struct SynthIntelPass : public ScriptPass {
 		log("        generate the synthesis netlist for the specified family.\n");
 		log("        MAX10 is the default target if not family argument specified.\n");
 		log("        For Cyclone GX devices, use cycloneiv argument; For Cyclone E, use cycloneive.\n");
-		log("        Cyclone V and Arria 10 GX devices are experimental, use it with a10gx argument.\n");
+		log("        Cyclone V and Arria 10 GX devices are experimental.\n");
 		log("\n");
 		log("    -top <module>\n");
 		log("        use the specified module as top module (default='top')\n");
-- 
cgit v1.2.3


From 50f5e29724bb6ea7f19279be7613ce693b7ea2da Mon Sep 17 00:00:00 2001
From: Dan Ravensloft <dan.ravensloft@gmail.com>
Date: Thu, 18 Jul 2019 17:28:21 +0100
Subject: synth_intel: s/not family/no family/

---
 techlibs/intel/synth_intel.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc
index 0b44a835f..9a6df8c45 100644
--- a/techlibs/intel/synth_intel.cc
+++ b/techlibs/intel/synth_intel.cc
@@ -38,7 +38,7 @@ struct SynthIntelPass : public ScriptPass {
 		log("\n");
 		log("    -family < max10 | a10gx | cyclone10 | cyclonev | cycloneiv | cycloneive>\n");
 		log("        generate the synthesis netlist for the specified family.\n");
-		log("        MAX10 is the default target if not family argument specified.\n");
+		log("        MAX10 is the default target if no family argument specified.\n");
 		log("        For Cyclone GX devices, use cycloneiv argument; For Cyclone E, use cycloneive.\n");
 		log("        Cyclone V and Arria 10 GX devices are experimental.\n");
 		log("\n");
@@ -153,7 +153,7 @@ struct SynthIntelPass : public ScriptPass {
 		    family_opt != "cycloneiv" &&
 		    family_opt != "cycloneive" &&
 		    family_opt != "cyclone10")
-			log_cmd_error("Invalid or not family specified: '%s'\n", family_opt.c_str());
+			log_cmd_error("Invalid or no family specified: '%s'\n", family_opt.c_str());
 
 		log_header(design, "Executing SYNTH_INTEL pass.\n");
 		log_push();
-- 
cgit v1.2.3


From 0c999ac2c4379273d560319d28591627de345a6a Mon Sep 17 00:00:00 2001
From: Dan Ravensloft <dan.ravensloft@gmail.com>
Date: Thu, 18 Jul 2019 18:41:34 +0100
Subject: synth_intel: Use stringf

---
 techlibs/intel/synth_intel.cc | 9 ++-------
 1 file changed, 2 insertions(+), 7 deletions(-)

(limited to 'techlibs')

diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc
index 9a6df8c45..58ef25e17 100644
--- a/techlibs/intel/synth_intel.cc
+++ b/techlibs/intel/synth_intel.cc
@@ -166,11 +166,8 @@ struct SynthIntelPass : public ScriptPass {
 	void script() YS_OVERRIDE
 	{
 		if (check_label("begin")) {
-			string cmd = "read_verilog -sv -lib +/intel/FAMILY/cells_sim.v";
-			cmd.replace(cmd.find("FAMILY"), 6, family_opt);
-
 			if (check_label("family"))
-				run(cmd);
+				run(stringf("read_verilog -sv -lib +/intel/%s/cells_sim.v", family_opt.c_str()));
 
 			// Misc and common cells
 			run("read_verilog -sv -lib +/intel/common/m9k_bb.v");
@@ -220,9 +217,7 @@ struct SynthIntelPass : public ScriptPass {
 		if (check_label("map_cells")) {
 			if (!noiopads)
 				run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I", "(unless -noiopads)");
-			string cmd = "techmap -map +/intel/FAMILY/cells_map.v";
-			cmd.replace(cmd.find("FAMILY"), 6, family_opt);
-			run(cmd);
+                        run(stringf("techmap -map +/intel/%s/cells_map.v", family_opt.c_str()));
 
 			run("dffinit -highlow -ff dffeas q power_up");
 			run("clean -purge");
-- 
cgit v1.2.3