From 6db181471ec1a45eb47a0bffd7378b22c1f7e24d Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 26 Jun 2019 10:47:03 -0700 Subject: Grrr --- techlibs/xilinx/synth_xilinx.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'techlibs/xilinx') diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index ced132968..dfe4c647b 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -153,8 +153,8 @@ struct SynthXilinxPass : public ScriptPass nocarry = true; continue; } - if (args[argidx] == "-nomux") { - nomux = true; + if (args[argidx] == "-nowidelut") { + nowidelut = true; continue; } if (args[argidx] == "-vpr") { -- cgit v1.2.3 From b7bef15b16abf1674d9c2efc58536db3abaf0e3d Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 26 Jun 2019 19:58:09 -0700 Subject: Add "WE" to dist RAM's abc_scc_break --- techlibs/xilinx/cells_sim.v | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'techlibs/xilinx') diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 04381e3b9..4ecf8277b 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -281,7 +281,7 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE); always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D; endmodule -(* abc_box_id = 4, abc_scc_break="D" *) +(* abc_box_id = 4, abc_scc_break="D,WE" *) module RAM32X1D ( output DPO, SPO, input D, WCLK, WE, @@ -299,7 +299,7 @@ module RAM32X1D ( always @(posedge clk) if (WE) mem[a] <= D; endmodule -(* abc_box_id = 5, abc_scc_break="D" *) +(* abc_box_id = 5, abc_scc_break="D,WE" *) module RAM64X1D ( output DPO, SPO, input D, WCLK, WE, @@ -317,7 +317,7 @@ module RAM64X1D ( always @(posedge clk) if (WE) mem[a] <= D; endmodule -(* abc_box_id = 6, abc_scc_break="D" *) +(* abc_box_id = 6, abc_scc_break="D,WE" *) module RAM128X1D ( output DPO, SPO, input D, WCLK, WE, -- cgit v1.2.3 From a7a88109f5b750862b8e45c194e8094fd32b8a5f Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 26 Jun 2019 20:00:15 -0700 Subject: Update comment on boxes --- techlibs/xilinx/abc_xc7.box | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'techlibs/xilinx') diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box index 96966a71c..6dd71d758 100644 --- a/techlibs/xilinx/abc_xc7.box +++ b/techlibs/xilinx/abc_xc7.box @@ -18,8 +18,9 @@ MUXF8 2 1 3 1 # Inputs: CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3 CI # Outputs: O0 O1 O2 O3 CO0 CO1 CO2 CO3 # (NB: carry chain input/output must be last -# input/output and have been moved there -# overriding the alphabetical ordering) +# input/output and the entire bus has been +# moved there overriding the otherwise +# alphabetical ordering) CARRY4 3 1 10 8 482 - - - - 223 - - - 222 598 407 - - - 400 205 - - 334 -- cgit v1.2.3