From a270af00cc133ac03ec97cf81ed0a7146b7b225e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 23 Aug 2019 11:21:44 -0700 Subject: Put abc_* attributes above port --- techlibs/xilinx/cells_sim.v | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) (limited to 'techlibs/xilinx') diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index bec9ea1a0..e3897d9a6 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -183,9 +183,11 @@ endmodule (* abc_box_id = 4, lib_whitebox *) module CARRY4( - (* abc_carry *) output [3:0] CO, + (* abc_carry *) + output [3:0] CO, output [3:0] O, - (* abc_carry *) input CI, + (* abc_carry *) + input CI, input CYINIT, input [3:0] DI, S ); @@ -298,9 +300,11 @@ endmodule (* abc_box_id = 5 *) module RAM32X1D ( output DPO, SPO, - (* abc_scc_break *) input D, + (* abc_scc_break *) + input D, input WCLK, - (* abc_scc_break *) input WE, + (* abc_scc_break *) + input WE, input A0, A1, A2, A3, A4, input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4 ); @@ -318,7 +322,8 @@ endmodule (* abc_box_id = 6 *) module RAM64X1D ( output DPO, SPO, - (* abc_scc_break *) input D, + (* abc_scc_break *) + input D, input WCLK, (* abc_scc_break *) input WE, input A0, A1, A2, A3, A4, A5, @@ -338,9 +343,11 @@ endmodule (* abc_box_id = 7 *) module RAM128X1D ( output DPO, SPO, - (* abc_scc_break *) input D, + (* abc_scc_break *) + input D, input WCLK, - (* abc_scc_break *) input WE, + (* abc_scc_break *) + input WE, input [6:0] A, DPRA ); parameter INIT = 128'h0; -- cgit v1.2.3 From 509c353fe981c95ca667a637bf2b47477962a60b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 23 Aug 2019 11:23:50 -0700 Subject: Forgot one --- techlibs/xilinx/cells_sim.v | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'techlibs/xilinx') diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index e3897d9a6..3ad96d7fb 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -325,7 +325,8 @@ module RAM64X1D ( (* abc_scc_break *) input D, input WCLK, - (* abc_scc_break *) input WE, + (* abc_scc_break *) + input WE, input A0, A1, A2, A3, A4, A5, input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5 ); -- cgit v1.2.3