From 89adef352fde57fa599d66fe404c3c2b9e607a7f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Mon, 3 Feb 2020 18:37:28 +0100 Subject: xilinx: Add support for LUT RAM on LUT4-based devices. There are multiple other kinds of RAMs supported on these devices, but RAM16X1D is the only dual-port one. Fixes #1549 --- techlibs/xilinx/Makefile.inc | 3 +- techlibs/xilinx/lut4_lutrams.txt | 19 +++++ techlibs/xilinx/lut6_lutrams.txt | 143 +++++++++++++++++++++++++++++++++ techlibs/xilinx/lutrams.txt | 167 --------------------------------------- techlibs/xilinx/synth_xilinx.cc | 3 +- 5 files changed, 165 insertions(+), 170 deletions(-) create mode 100644 techlibs/xilinx/lut4_lutrams.txt create mode 100644 techlibs/xilinx/lut6_lutrams.txt delete mode 100644 techlibs/xilinx/lutrams.txt (limited to 'techlibs/xilinx') diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc index 7785bf81c..d07bae12a 100644 --- a/techlibs/xilinx/Makefile.inc +++ b/techlibs/xilinx/Makefile.inc @@ -38,7 +38,8 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcu_brams_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcup_urams.txt)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcup_urams_map.v)) -$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams.txt)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut4_lutrams.txt)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut6_lutrams.txt)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_ff_map.v)) diff --git a/techlibs/xilinx/lut4_lutrams.txt b/techlibs/xilinx/lut4_lutrams.txt new file mode 100644 index 000000000..2b344a9ee --- /dev/null +++ b/techlibs/xilinx/lut4_lutrams.txt @@ -0,0 +1,19 @@ +bram $__XILINX_RAM16X1D + init 1 + abits 4 + dbits 1 + groups 2 + ports 1 1 + wrmode 0 1 + enable 0 1 + transp 0 0 + clocks 0 1 + clkpol 0 2 +endbram + + +match $__XILINX_RAM16X1D + min bits 2 + min wports 1 + make_outreg +endmatch diff --git a/techlibs/xilinx/lut6_lutrams.txt b/techlibs/xilinx/lut6_lutrams.txt new file mode 100644 index 000000000..3b3cb81e1 --- /dev/null +++ b/techlibs/xilinx/lut6_lutrams.txt @@ -0,0 +1,143 @@ +bram $__XILINX_RAM32X1D + init 1 + abits 5 + dbits 1 + groups 2 + ports 1 1 + wrmode 0 1 + enable 0 1 + transp 0 0 + clocks 0 1 + clkpol 0 2 +endbram + +bram $__XILINX_RAM64X1D + init 1 + abits 6 + dbits 1 + groups 2 + ports 1 1 + wrmode 0 1 + enable 0 1 + transp 0 0 + clocks 0 1 + clkpol 0 2 +endbram + +bram $__XILINX_RAM128X1D + init 1 + abits 7 + dbits 1 + groups 2 + ports 1 1 + wrmode 0 1 + enable 0 1 + transp 0 0 + clocks 0 1 + clkpol 0 2 +endbram + + +bram $__XILINX_RAM32X6SDP + init 1 + abits 5 + dbits 6 + groups 2 + ports 1 1 + wrmode 0 1 + enable 0 1 + transp 0 0 + clocks 0 1 + clkpol 0 2 +endbram + +bram $__XILINX_RAM64X3SDP + init 1 + abits 6 + dbits 3 + groups 2 + ports 1 1 + wrmode 0 1 + enable 0 1 + transp 0 0 + clocks 0 1 + clkpol 0 2 +endbram + +bram $__XILINX_RAM32X2Q + init 1 + abits 5 + dbits 2 + groups 2 + ports 3 1 + wrmode 0 1 + enable 0 1 + transp 0 0 + clocks 0 1 + clkpol 0 2 +endbram + +bram $__XILINX_RAM64X1Q + init 1 + abits 6 + dbits 1 + groups 2 + ports 3 1 + wrmode 0 1 + enable 0 1 + transp 0 0 + clocks 0 1 + clkpol 0 2 +endbram + + +match $__XILINX_RAM32X1D + min bits 3 + min wports 1 + make_outreg + or_next_if_better +endmatch + +match $__XILINX_RAM64X1D + min bits 5 + min wports 1 + make_outreg + or_next_if_better +endmatch + +match $__XILINX_RAM128X1D + min bits 9 + min wports 1 + make_outreg + or_next_if_better +endmatch + + +match $__XILINX_RAM32X6SDP + min bits 5 + min wports 1 + make_outreg + or_next_if_better +endmatch + +match $__XILINX_RAM64X3SDP + min bits 6 + min wports 1 + make_outreg + or_next_if_better +endmatch + +match $__XILINX_RAM32X2Q + min bits 5 + min rports 2 + min wports 1 + make_outreg + or_next_if_better +endmatch + +match $__XILINX_RAM64X1Q + min bits 5 + min rports 2 + min wports 1 + make_outreg +endmatch diff --git a/techlibs/xilinx/lutrams.txt b/techlibs/xilinx/lutrams.txt deleted file mode 100644 index faf66bc18..000000000 --- a/techlibs/xilinx/lutrams.txt +++ /dev/null @@ -1,167 +0,0 @@ - -bram $__XILINX_RAM16X1D - init 1 - abits 4 - dbits 1 - groups 2 - ports 1 1 - wrmode 0 1 - enable 0 1 - transp 0 0 - clocks 0 1 - clkpol 0 2 -endbram - -bram $__XILINX_RAM32X1D - init 1 - abits 5 - dbits 1 - groups 2 - ports 1 1 - wrmode 0 1 - enable 0 1 - transp 0 0 - clocks 0 1 - clkpol 0 2 -endbram - -bram $__XILINX_RAM64X1D - init 1 - abits 6 - dbits 1 - groups 2 - ports 1 1 - wrmode 0 1 - enable 0 1 - transp 0 0 - clocks 0 1 - clkpol 0 2 -endbram - -bram $__XILINX_RAM128X1D - init 1 - abits 7 - dbits 1 - groups 2 - ports 1 1 - wrmode 0 1 - enable 0 1 - transp 0 0 - clocks 0 1 - clkpol 0 2 -endbram - - -bram $__XILINX_RAM32X6SDP - init 1 - abits 5 - dbits 6 - groups 2 - ports 1 1 - wrmode 0 1 - enable 0 1 - transp 0 0 - clocks 0 1 - clkpol 0 2 -endbram - -bram $__XILINX_RAM64X3SDP - init 1 - abits 6 - dbits 3 - groups 2 - ports 1 1 - wrmode 0 1 - enable 0 1 - transp 0 0 - clocks 0 1 - clkpol 0 2 -endbram - -bram $__XILINX_RAM32X2Q - init 1 - abits 5 - dbits 2 - groups 2 - ports 3 1 - wrmode 0 1 - enable 0 1 - transp 0 0 - clocks 0 1 - clkpol 0 2 -endbram - -bram $__XILINX_RAM64X1Q - init 1 - abits 6 - dbits 1 - groups 2 - ports 3 1 - wrmode 0 1 - enable 0 1 - transp 0 0 - clocks 0 1 - clkpol 0 2 -endbram - - -# Disabled for now, pending support for LUT4 arches -# since on LUT6 arches this occupies same area as -# a RAM32X1D -#match $__XILINX_RAM16X1D -# min bits 2 -# min wports 1 -# make_outreg -# or_next_if_better -#endmatch - -match $__XILINX_RAM32X1D - min bits 3 - min wports 1 - make_outreg - or_next_if_better -endmatch - -match $__XILINX_RAM64X1D - min bits 5 - min wports 1 - make_outreg - or_next_if_better -endmatch - -match $__XILINX_RAM128X1D - min bits 9 - min wports 1 - make_outreg - or_next_if_better -endmatch - - -match $__XILINX_RAM32X6SDP - min bits 5 - min wports 1 - make_outreg - or_next_if_better -endmatch - -match $__XILINX_RAM64X3SDP - min bits 6 - min wports 1 - make_outreg - or_next_if_better -endmatch - -match $__XILINX_RAM32X2Q - min bits 5 - min rports 2 - min wports 1 - make_outreg - or_next_if_better -endmatch - -match $__XILINX_RAM64X1Q - min bits 5 - min rports 2 - min wports 1 - make_outreg -endmatch diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index fe58eb6d3..556f85a20 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -318,7 +318,6 @@ struct SynthXilinxPass : public ScriptPass if (lut_size != 6) { log_warning("Shift register inference not yet supported for family %s.\n", family.c_str()); nosrl = true; - nolutram = true; } if (widemux != 0 && widemux < 2) @@ -518,7 +517,7 @@ struct SynthXilinxPass : public ScriptPass if (check_label("map_lutram", "(skip if '-nolutram')")) { if (!nolutram || help_mode) { - run("memory_bram -rules +/xilinx/lutrams.txt"); + run("memory_bram -rules +/xilinx/lut" + lut_size_s + "_lutrams.txt"); run("techmap -map +/xilinx/lutrams_map.v"); } } -- cgit v1.2.3