From efd04880dbeb2021c503c82ad962fe8c5d6802d4 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 24 Jun 2019 16:16:50 -0700
Subject: Add RAM32X1D support

---
 techlibs/xilinx/cells_sim.v   | 17 +++++++++++++++++
 techlibs/xilinx/cells_xtra.sh |  4 ++--
 techlibs/xilinx/cells_xtra.v  | 18 ------------------
 techlibs/xilinx/drams.txt     | 20 ++++++++++++++++++++
 techlibs/xilinx/drams_map.v   | 34 ++++++++++++++++++++++++++++++++++
 5 files changed, 73 insertions(+), 20 deletions(-)

(limited to 'techlibs/xilinx')

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 3a4540b83..50d588a9e 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -278,6 +278,23 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE);
   always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
 endmodule
 
+module RAM32X1D (
+  output DPO, SPO,
+  input  D, WCLK, WE,
+  input  A0, A1, A2, A3, A4,
+  input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4,
+);
+  parameter INIT = 32'h0;
+  parameter IS_WCLK_INVERTED = 1'b0;
+  wire [4:0] a = {A4, A3, A2, A1, A0};
+  wire [4:0] dpra = {DPRA4, DPRA3, DPRA2, DPRA1, DPRA0};
+  reg [31:0] mem = INIT;
+  assign SPO = mem[a];
+  assign DPO = mem[dpra];
+  wire clk = WCLK ^ IS_WCLK_INVERTED;
+  always @(posedge clk) if (WE) mem[a] <= D;
+endmodule
+
 module RAM64X1D (
   output DPO, SPO,
   input  D, WCLK, WE,
diff --git a/techlibs/xilinx/cells_xtra.sh b/techlibs/xilinx/cells_xtra.sh
index 8e39b440d..83863bf0b 100644
--- a/techlibs/xilinx/cells_xtra.sh
+++ b/techlibs/xilinx/cells_xtra.sh
@@ -116,11 +116,11 @@ function xtract_cell_decl()
 	xtract_cell_decl PS7 "(* keep *)"
 	xtract_cell_decl PULLDOWN
 	xtract_cell_decl PULLUP
-	xtract_cell_decl RAM128X1D
+	#xtract_cell_decl RAM128X1D
 	xtract_cell_decl RAM128X1S
 	xtract_cell_decl RAM256X1S
 	xtract_cell_decl RAM32M
-	xtract_cell_decl RAM32X1D
+	#xtract_cell_decl RAM32X1D
 	xtract_cell_decl RAM32X1S
 	xtract_cell_decl RAM32X1S_1
 	xtract_cell_decl RAM32X2S
diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v
index fbcc74682..6220da703 100644
--- a/techlibs/xilinx/cells_xtra.v
+++ b/techlibs/xilinx/cells_xtra.v
@@ -3655,17 +3655,6 @@ module PULLUP (...);
     output O;
 endmodule
 
-module RAM128X1D (...);
-    parameter [127:0] INIT = 128'h00000000000000000000000000000000;
-    parameter [0:0] IS_WCLK_INVERTED = 1'b0;
-    output DPO, SPO;
-    input [6:0] A;
-    input [6:0] DPRA;
-    input D;
-    input WCLK;
-    input WE;
-endmodule
-
 module RAM128X1S (...);
     parameter [127:0] INIT = 128'h00000000000000000000000000000000;
     parameter [0:0] IS_WCLK_INVERTED = 1'b0;
@@ -3705,13 +3694,6 @@ module RAM32M (...);
     input WE;
 endmodule
 
-module RAM32X1D (...);
-    parameter [31:0] INIT = 32'h00000000;
-    parameter [0:0] IS_WCLK_INVERTED = 1'b0;
-    output DPO, SPO;
-    input A0, A1, A2, A3, A4, D, DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, WCLK, WE;
-endmodule
-
 module RAM32X1S (...);
     parameter [31:0] INIT = 32'h00000000;
     parameter [0:0] IS_WCLK_INVERTED = 1'b0;
diff --git a/techlibs/xilinx/drams.txt b/techlibs/xilinx/drams.txt
index 91632bcee..2613c206c 100644
--- a/techlibs/xilinx/drams.txt
+++ b/techlibs/xilinx/drams.txt
@@ -1,4 +1,17 @@
 
+bram $__XILINX_RAM32X1D
+  init 1
+  abits 5
+  dbits 1
+  groups 2
+  ports  1 1
+  wrmode 0 1
+  enable 0 1
+  transp 0 0
+  clocks 0 1
+  clkpol 0 2
+endbram
+
 bram $__XILINX_RAM64X1D
   init 1
   abits 6
@@ -25,6 +38,13 @@ bram $__XILINX_RAM128X1D
   clkpol 0 2
 endbram
 
+match $__XILINX_RAM32X1D
+  min bits 3
+  min wports 1
+  make_outreg
+  or_next_if_better
+endmatch
+
 match $__XILINX_RAM64X1D
   min bits 5
   min wports 1
diff --git a/techlibs/xilinx/drams_map.v b/techlibs/xilinx/drams_map.v
index 47476b592..77041ca86 100644
--- a/techlibs/xilinx/drams_map.v
+++ b/techlibs/xilinx/drams_map.v
@@ -1,4 +1,38 @@
 
+module \$__XILINX_RAM32X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
+	parameter [31:0] INIT = 32'bx;
+	parameter CLKPOL2 = 1;
+	input CLK1;
+
+	input [4:0] A1ADDR;
+	output A1DATA;
+
+	input [4:0] B1ADDR;
+	input B1DATA;
+	input B1EN;
+
+	RAM32X1D #(
+		.INIT(INIT),
+		.IS_WCLK_INVERTED(!CLKPOL2)
+	) _TECHMAP_REPLACE_ (
+		.DPRA0(A1ADDR[0]),
+		.DPRA1(A1ADDR[1]),
+		.DPRA2(A1ADDR[2]),
+		.DPRA3(A1ADDR[3]),
+		.DPRA4(A1ADDR[4]),
+		.DPO(A1DATA),
+
+		.A0(B1ADDR[0]),
+		.A1(B1ADDR[1]),
+		.A2(B1ADDR[2]),
+		.A3(B1ADDR[3]),
+		.A4(B1ADDR[4]),
+		.D(B1DATA),
+		.WCLK(CLK1),
+		.WE(B1EN)
+	);
+endmodule
+
 module \$__XILINX_RAM64X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
 	parameter [63:0] INIT = 64'bx;
 	parameter CLKPOL2 = 1;
-- 
cgit v1.2.3