From 30854b9c7f23e2817a445761022668d6b0f7c0ef Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Tue, 4 Feb 2020 15:35:47 +0100 Subject: xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*. --- techlibs/xilinx/xc7_xcu_brams.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'techlibs/xilinx/xc7_xcu_brams.txt') diff --git a/techlibs/xilinx/xc7_xcu_brams.txt b/techlibs/xilinx/xc7_xcu_brams.txt index c63218ae1..650367abf 100644 --- a/techlibs/xilinx/xc7_xcu_brams.txt +++ b/techlibs/xilinx/xc7_xcu_brams.txt @@ -1,3 +1,5 @@ +# Virtex 6, Series 7, Ultrascale, Ultrascale Plus block RAM rules. + bram $__XILINX_RAMB36_SDP init 1 abits 9 -- cgit v1.2.3