From 816fe6bbe0ad90f7a696dd208dae6db8139dfd00 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 1 Feb 2015 17:09:34 +0100 Subject: Added Xilinx example for Basys3 board --- techlibs/xilinx/cells_sim.v | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'techlibs/xilinx/cells_sim.v') diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 285d63dbf..c7f07e400 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -19,7 +19,7 @@ module OBUF(output O, input I); assign O = I; endmodule -module BUFGP(output O, input I); +module BUFG(output O, input I); assign O = I; endmodule @@ -27,6 +27,10 @@ module OBUFT(output O, input I, T); assign O = T ? 1'bz : I; endmodule +module IOBUF(inout IO, output O, input I, T); + assign O = IO, IO = T ? 1'bz : I; +endmodule + module INV(output O, input I); assign O = !I; endmodule -- cgit v1.2.3