From 979bf36fb00ec61ec7e27f074079e0464be03be7 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 19 Dec 2019 11:23:41 -0800 Subject: Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_t --- techlibs/xilinx/abc9_model.v | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) (limited to 'techlibs/xilinx/abc9_model.v') diff --git a/techlibs/xilinx/abc9_model.v b/techlibs/xilinx/abc9_model.v index cc0e5ec41..c793396a4 100644 --- a/techlibs/xilinx/abc9_model.v +++ b/techlibs/xilinx/abc9_model.v @@ -33,11 +33,19 @@ endmodule module \$__ABC9_FF_ (input D, output Q); endmodule +// Box to emulate async behaviour of FDC* (* abc_box_id = 1000 *) -module \$__ABC9_ASYNC (input A, S, output Y); +module \$__ABC9_ASYNC0 (input A, S, output Y); + assign Y = S ? 1'b0 : A; endmodule -// Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32} +// Box to emulate async behaviour of FDP* +(* abc_box_id = 1001 *) +module \$__ABC9_ASYNC1 (input A, S, output Y); + assign Y = S ? 1'b0 : A; +endmodule + +// Box to emulate comb/seq behaviour of RAM{32,64} and SRL{16,32} // Necessary since RAMD* and SRL* have both combinatorial (i.e. // same-cycle read operation) and sequential (write operation // is only committed on the next clock edge). @@ -46,7 +54,7 @@ endmodule (* abc9_box_id=2000 *) module \$__ABC9_LUT6 (input A, input [5:0] S, output Y); endmodule -// Box to emulate comb/seq behaviour of RAMD128 +// Box to emulate comb/seq behaviour of RAM128 (* abc9_box_id=2001 *) module \$__ABC9_LUT7 (input A, input [6:0] S, output Y); endmodule -- cgit v1.2.3