From efed2420d686c35f79c4f68e56b460f8e534a6ea Mon Sep 17 00:00:00 2001 From: c60k28 Date: Sat, 31 Mar 2018 22:48:47 -0600 Subject: Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal value for the POWER_UP parameter. Fixed and tested Cyclone V device --- techlibs/intel/synth_intel.cc | 27 +++++++++++++++++++++++---- 1 file changed, 23 insertions(+), 4 deletions(-) (limited to 'techlibs/intel/synth_intel.cc') diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc index 9e632c861..dfed7a285 100644 --- a/techlibs/intel/synth_intel.cc +++ b/techlibs/intel/synth_intel.cc @@ -36,7 +36,7 @@ struct SynthIntelPass : public ScriptPass { log("\n"); log("This command runs synthesis for Intel FPGAs.\n"); log("\n"); - log(" -family < max10 | a10gx | cyclonev | cycloneiv | cycloneive>\n"); + log(" -family < max10 | a10gx | cyclone10 | cyclonev | cycloneiv | cycloneive>\n"); log(" generate the synthesis netlist for the specified family.\n"); log(" MAX10 is the default target if not family argument specified.\n"); log(" For Cyclone GX devices, use cycloneiv argument; For Cyclone E, use cycloneive.\n"); @@ -49,6 +49,11 @@ struct SynthIntelPass : public ScriptPass { log(" write the design to the specified Verilog Quartus Mapping File. Writing of an\n"); log(" output file is omitted if this parameter is not specified.\n"); log("\n"); + log(" -vpr \n"); + log(" write BLIF files for VPR flow experiments. The synthesized BLIF output file is not\n"); + log(" compatible with the Quartus flow. Writing of an\n"); + log(" output file is omitted if this parameter is not specified.\n"); + log("\n"); log(" -run :\n"); log(" only run the commands between the labels (see below). an empty\n"); log(" from label is synonymous to 'begin', and empty to label is\n"); @@ -68,7 +73,7 @@ struct SynthIntelPass : public ScriptPass { log("\n"); } - string top_opt, family_opt, vout_file; + string top_opt, family_opt, vout_file, blif_file; bool retime, flatten, nobram; virtual void clear_flags() YS_OVERRIDE @@ -76,6 +81,7 @@ struct SynthIntelPass : public ScriptPass { top_opt = "-auto-top"; family_opt = "max10"; vout_file = ""; + blif_file = ""; retime = false; flatten = true; nobram = false; @@ -101,6 +107,10 @@ struct SynthIntelPass : public ScriptPass { vout_file = args[++argidx]; continue; } + if (args[argidx] == "-vpr" && argidx+1 < args.size()) { + blif_file = args[++argidx]; + continue; + } if (args[argidx] == "-run" && argidx+1 < args.size()) { size_t pos = args[argidx+1].find(':'); if (pos == std::string::npos) @@ -198,7 +208,7 @@ struct SynthIntelPass : public ScriptPass { if (check_label("map_luts")) { if(family_opt=="a10gx" || family_opt=="cyclonev") - run("abc -luts 2:2,3,6:5,10" + string(retime ? " -dff" : "")); + run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : "")); else run("abc -lut 4" + string(retime ? " -dff" : "")); run("clean"); @@ -236,7 +246,16 @@ struct SynthIntelPass : public ScriptPass { run(stringf("write_verilog -attr2comment -defparam -nohex -decimal -renameprefix syn_ %s", help_mode ? "" : vout_file.c_str())); } - } + + if (check_label("vpr")) + { + if (!blif_file.empty() || help_mode) + { + run(stringf("opt_clean -purge")); + run(stringf("write_blif %s", help_mode ? "" : blif_file.c_str())); + } + } + } } SynthIntelPass; PRIVATE_NAMESPACE_END -- cgit v1.2.3 From b4c1d3084ffb2b0a5ec2207cb46004fd89cdae80 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 30 Apr 2018 13:02:56 +0200 Subject: Add "synth_intel --noiopads" Signed-off-by: Clifford Wolf --- techlibs/intel/synth_intel.cc | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) (limited to 'techlibs/intel/synth_intel.cc') diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc index dfed7a285..c51949bd4 100644 --- a/techlibs/intel/synth_intel.cc +++ b/techlibs/intel/synth_intel.cc @@ -59,6 +59,9 @@ struct SynthIntelPass : public ScriptPass { log(" from label is synonymous to 'begin', and empty to label is\n"); log(" synonymous to the end of the command list.\n"); log("\n"); + log(" -noiopads\n"); + log(" do not use altsyncram cells in output netlist\n"); + log("\n"); log(" -nobram\n"); log(" do not use altsyncram cells in output netlist\n"); log("\n"); @@ -74,7 +77,7 @@ struct SynthIntelPass : public ScriptPass { } string top_opt, family_opt, vout_file, blif_file; - bool retime, flatten, nobram; + bool retime, flatten, nobram, noiopads; virtual void clear_flags() YS_OVERRIDE { @@ -85,6 +88,7 @@ struct SynthIntelPass : public ScriptPass { retime = false; flatten = true; nobram = false; + noiopads = false; } virtual void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE @@ -119,6 +123,10 @@ struct SynthIntelPass : public ScriptPass { run_to = args[argidx].substr(pos+1); continue; } + if (args[argidx] == "-noiopads") { + noiopads = true; + continue; + } if (args[argidx] == "-nobram") { nobram = true; continue; @@ -216,7 +224,8 @@ struct SynthIntelPass : public ScriptPass { if (check_label("map_cells")) { - run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I"); + if (!noiopads) + run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I", "(unless -noiopads)"); if(family_opt=="max10") run("techmap -map +/intel/max10/cells_map.v"); else if(family_opt=="a10gx") -- cgit v1.2.3 From 3aa4484a3cd9a2e82fddd499cde575eaf8c565cc Mon Sep 17 00:00:00 2001 From: Henner Zeller Date: Fri, 20 Jul 2018 23:41:18 -0700 Subject: Consistent use of 'override' for virtual methods in derived classes. o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established) --- techlibs/intel/synth_intel.cc | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'techlibs/intel/synth_intel.cc') diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc index c51949bd4..d74f295ec 100644 --- a/techlibs/intel/synth_intel.cc +++ b/techlibs/intel/synth_intel.cc @@ -28,7 +28,7 @@ PRIVATE_NAMESPACE_BEGIN struct SynthIntelPass : public ScriptPass { SynthIntelPass() : ScriptPass("synth_intel", "synthesis for Intel (Altera) FPGAs.") { } - virtual void help() YS_OVERRIDE + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -79,7 +79,7 @@ struct SynthIntelPass : public ScriptPass { string top_opt, family_opt, vout_file, blif_file; bool retime, flatten, nobram, noiopads; - virtual void clear_flags() YS_OVERRIDE + void clear_flags() YS_OVERRIDE { top_opt = "-auto-top"; family_opt = "max10"; @@ -91,7 +91,7 @@ struct SynthIntelPass : public ScriptPass { noiopads = false; } - virtual void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { string run_from, run_to; clear_flags(); @@ -156,7 +156,7 @@ struct SynthIntelPass : public ScriptPass { log_pop(); } - virtual void script() YS_OVERRIDE + void script() YS_OVERRIDE { if (check_label("begin")) { @@ -255,7 +255,7 @@ struct SynthIntelPass : public ScriptPass { run(stringf("write_verilog -attr2comment -defparam -nohex -decimal -renameprefix syn_ %s", help_mode ? "" : vout_file.c_str())); } - + if (check_label("vpr")) { if (!blif_file.empty() || help_mode) @@ -264,7 +264,7 @@ struct SynthIntelPass : public ScriptPass { run(stringf("write_blif %s", help_mode ? "" : blif_file.c_str())); } } - } + } } SynthIntelPass; PRIVATE_NAMESPACE_END -- cgit v1.2.3