From efed2420d686c35f79c4f68e56b460f8e534a6ea Mon Sep 17 00:00:00 2001 From: c60k28 Date: Sat, 31 Mar 2018 22:48:47 -0600 Subject: Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal value for the POWER_UP parameter. Fixed and tested Cyclone V device --- techlibs/intel/cyclonev/cells_map.v | 75 +++++++++++++++++++++---------------- 1 file changed, 43 insertions(+), 32 deletions(-) (limited to 'techlibs/intel/cyclonev/cells_map.v') diff --git a/techlibs/intel/cyclonev/cells_map.v b/techlibs/intel/cyclonev/cells_map.v index 9fe8db2da..bd60d4e17 100644 --- a/techlibs/intel/cyclonev/cells_map.v +++ b/techlibs/intel/cyclonev/cells_map.v @@ -16,33 +16,45 @@ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ +// > c60k28 (Viacheslav, VT) [at] yandex [dot] com +// > Intel FPGA technology mapping. User must first simulate the generated \ +// > netlist before going to test it on board. +// > Changelog: 1) The missing power_up parameter in the techmap introduces a problem in Quartus mapper. Fixed. +// 2) Cyclone V 7-input LUT function was wrong implemented. Removed abc option to map this function \ +// and added the explanation in this file instead. Such function needs to be implemented. + // Normal mode DFF negedge clk, negedge reset module \$_DFF_N_ (input D, C, output Q); parameter WYSIWYG="TRUE"; - dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); + parameter power_up=1'bx; + dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); endmodule // Normal mode DFF module \$_DFF_P_ (input D, C, output Q); parameter WYSIWYG="TRUE"; - dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); + parameter power_up=1'bx; + dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); endmodule // Async Active Low Reset DFF module \$_DFF_PN0_ (input D, C, R, output Q); parameter WYSIWYG="TRUE"; - dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); + parameter power_up=1'bx; + dffeas #(.is_wysiwyg(WYSIWYG), .power_up("power_up")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); endmodule // Async Active High Reset DFF module \$_DFF_PP0_ (input D, C, R, output Q); parameter WYSIWYG="TRUE"; + parameter power_up=1'bx; wire R_i = ~ R; - dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); + dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); endmodule module \$__DFFE_PP0 (input D, C, E, R, output Q); parameter WYSIWYG="TRUE"; + parameter power_up=1'bx; wire E_i = ~ E; - dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0)); + dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0)); endmodule // Input buffer map @@ -61,6 +73,10 @@ module \$lut (A, Y); parameter LUT = 0; input [WIDTH-1:0] A; output Y; + wire VCC; + wire GND; + assign {VCC,GND} = {1'b1,1'b0}; + generate if (WIDTH == 1) begin assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function @@ -72,11 +88,11 @@ module \$lut (A, Y); (.combout(Y), .dataa(A[0]), .datab(A[1]), - .datac(1'b1), - .datad(1'b1), - .datae(1'b1), - .dataf(1'b1), - .datag(1'b1)); + .datac(VCC), + .datad(VCC), + .datae(VCC), + .dataf(VCC), + .datag(VCC)); end else if(WIDTH == 3) begin @@ -86,10 +102,10 @@ module \$lut (A, Y); .dataa(A[0]), .datab(A[1]), .datac(A[2]), - .datad(1'b1), - .datae(1'b1), - .dataf(1'b1), - .datag(1'b1)); + .datad(VCC), + .datae(VCC), + .dataf(VCC), + .datag(VCC)); end else if(WIDTH == 4) begin @@ -100,9 +116,9 @@ module \$lut (A, Y); .datab(A[1]), .datac(A[2]), .datad(A[3]), - .datae(1'b1), - .dataf(1'b1), - .datag(1'b1)); + .datae(VCC), + .dataf(VCC), + .datag(VCC)); end else if(WIDTH == 5) begin @@ -114,8 +130,8 @@ module \$lut (A, Y); .datac(A[2]), .datad(A[3]), .datae(A[4]), - .dataf(1'b1), - .datag(1'b1)); + .dataf(VCC), + .datag(VCC)); end else if(WIDTH == 6) begin @@ -128,21 +144,16 @@ module \$lut (A, Y); .datad(A[3]), .datae(A[4]), .dataf(A[5]), - .datag(1'b1)); + .datag(VCC)); end - else + /*else if(WIDTH == 7) begin - cyclonev_lcell_comb #(.lut_mask(LUT), .shared_arith("off"), .extended_lut("off")) - _TECHMAP_REPLACE_ - (.combout(Y), - .dataa(A[0]), - .datab(A[1]), - .datac(A[2]), - .datad(A[3]), - .datae(A[4]), - .dataf(A[5]), - .datag(A[6])); - end + TODO: There's not a just 7-input function on Cyclone V, see the following note: + **Extended LUT Mode** + Use extended LUT mode to implement a specific set of 7-input functions. The set must + be a 2-to-1 multiplexer fed by two arbitrary 5-input functions sharing four inputs. + [source](Device Interfaces and Integration Basics for Cyclone V Devices). + end*/ else wire _TECHMAP_FAIL_ = 1; endgenerate -- cgit v1.2.3