From fdafb74eb77e33e9fa2b4e591804d1d02c122ff9 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 12 Mar 2020 12:57:01 -0700
Subject: kernel: use more ID::*

---
 techlibs/ice40/ice40_ffinit.cc |  6 +++---
 techlibs/ice40/ice40_ffssr.cc  | 14 +++++++-------
 techlibs/ice40/ice40_opt.cc    | 14 +++++++-------
 3 files changed, 17 insertions(+), 17 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/ice40_ffinit.cc b/techlibs/ice40/ice40_ffinit.cc
index c098736e9..29c999ff4 100644
--- a/techlibs/ice40/ice40_ffinit.cc
+++ b/techlibs/ice40/ice40_ffinit.cc
@@ -133,13 +133,13 @@ struct Ice40FfinitPass : public Pass {
 				if (type_str.back() == 'S') {
 					type_str.back() = 'R';
 					cell->type = type_str;
-					cell->setPort("\\R", cell->getPort("\\S"));
-					cell->unsetPort("\\S");
+					cell->setPort("\\R", cell->getPort(ID::S));
+					cell->unsetPort(ID::S);
 				} else
 				if (type_str.back() == 'R') {
 					type_str.back() = 'S';
 					cell->type = type_str;
-					cell->setPort("\\S", cell->getPort("\\R"));
+					cell->setPort(ID::S, cell->getPort("\\R"));
 					cell->unsetPort("\\R");
 				}
 
diff --git a/techlibs/ice40/ice40_ffssr.cc b/techlibs/ice40/ice40_ffssr.cc
index a7649d7a0..dae981618 100644
--- a/techlibs/ice40/ice40_ffssr.cc
+++ b/techlibs/ice40/ice40_ffssr.cc
@@ -72,11 +72,11 @@ struct Ice40FfssrPass : public Pass {
 				if (cell->type != "$_MUX_")
 					continue;
 
-				SigBit bit_a = sigmap(cell->getPort("\\A"));
-				SigBit bit_b = sigmap(cell->getPort("\\B"));
+				SigBit bit_a = sigmap(cell->getPort(ID::A));
+				SigBit bit_b = sigmap(cell->getPort(ID::B));
 
 				if (bit_a.wire == nullptr || bit_b.wire == nullptr)
-					sr_muxes[sigmap(cell->getPort("\\Y"))] = cell;
+					sr_muxes[sigmap(cell->getPort(ID::Y))] = cell;
 			}
 
 			for (auto cell : ff_cells)
@@ -95,9 +95,9 @@ struct Ice40FfssrPass : public Pass {
 					continue;
 
 				Cell *mux_cell = sr_muxes.at(bit_d);
-				SigBit bit_a = sigmap(mux_cell->getPort("\\A"));
-				SigBit bit_b = sigmap(mux_cell->getPort("\\B"));
-				SigBit bit_s = sigmap(mux_cell->getPort("\\S"));
+				SigBit bit_a = sigmap(mux_cell->getPort(ID::A));
+				SigBit bit_b = sigmap(mux_cell->getPort(ID::B));
+				SigBit bit_s = sigmap(mux_cell->getPort(ID::S));
 
 				log("  Merging %s (A=%s, B=%s, S=%s) into %s (%s).\n", log_id(mux_cell),
 						log_signal(bit_a), log_signal(bit_b), log_signal(bit_s), log_id(cell), log_id(cell->type));
@@ -116,7 +116,7 @@ struct Ice40FfssrPass : public Pass {
 
 				if (sr_val == State::S1) {
 					cell->type = cell->type.str() + "SS";
-					cell->setPort("\\S", sr_sig);
+					cell->setPort(ID::S, sr_sig);
 					cell->setPort("\\D", bit_d);
 				} else {
 					cell->type = cell->type.str() + "SR";
diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index 925ab31bb..7667f28cb 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -95,8 +95,8 @@ static void run_ice40_opts(Module *module)
 			int count_zeros = 0, count_ones = 0;
 
 			SigBit inbit[3] = {
-				cell->getPort("\\A"),
-				cell->getPort("\\B"),
+				cell->getPort(ID::A),
+				cell->getPort(ID::B),
 				cell->getPort("\\CI")
 			};
 			for (int i = 0; i < 3; i++)
@@ -140,9 +140,9 @@ static void run_ice40_opts(Module *module)
 						log_id(module), log_id(cell), log_signal(replacement_output));
 				cell->type = "$lut";
 				auto I3 = get_bit_or_zero(cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID(CI) : ID(I3)));
-				cell->setPort("\\A", { I3, inbit[1], inbit[0], get_bit_or_zero(cell->getPort("\\I0")) });
-				cell->setPort("\\Y", cell->getPort("\\O"));
-				cell->unsetPort("\\B");
+				cell->setPort(ID::A, { I3, inbit[1], inbit[0], get_bit_or_zero(cell->getPort("\\I0")) });
+				cell->setPort(ID::Y, cell->getPort("\\O"));
+				cell->unsetPort(ID::B);
 				cell->unsetPort("\\CI");
 				cell->unsetPort("\\I0");
 				cell->unsetPort("\\I3");
@@ -182,13 +182,13 @@ static void run_ice40_opts(Module *module)
 		cell->setParam("\\LUT", cell->getParam("\\LUT_INIT"));
 		cell->unsetParam("\\LUT_INIT");
 
-		cell->setPort("\\A", SigSpec({
+		cell->setPort(ID::A, SigSpec({
 			get_bit_or_zero(cell->getPort("\\I3")),
 			get_bit_or_zero(cell->getPort("\\I2")),
 			get_bit_or_zero(cell->getPort("\\I1")),
 			get_bit_or_zero(cell->getPort("\\I0"))
 		}));
-		cell->setPort("\\Y", cell->getPort("\\O")[0]);
+		cell->setPort(ID::Y, cell->getPort("\\O")[0]);
 		cell->unsetPort("\\I0");
 		cell->unsetPort("\\I1");
 		cell->unsetPort("\\I2");
-- 
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