From e3709e5ee6b28c1156b4768373e244c32c7c5aba Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 28 Aug 2019 18:51:14 -0700 Subject: LX -> LP --- techlibs/ice40/cells_sim.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs/ice40') diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index 34134d02a..fe80c998d 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -3,7 +3,7 @@ // `define SB_DFF_REG reg Q `define ABC_ARRIVAL_HX(TIME) `ifdef ICE40_HX (* abc_arrival=TIME *) `endif -`define ABC_ARRIVAL_LX(TIME) `ifdef ICE40_LX (* abc_arrival=TIME *) `endif +`define ABC_ARRIVAL_LP(TIME) `ifdef ICE40_LP (* abc_arrival=TIME *) `endif `define ABC_ARRIVAL_U(TIME) `ifdef ICE40_U (* abc_arrival=TIME *) `endif // SiliconBlue IO Cells -- cgit v1.2.3 href='/cgit/'>cgit logo index : openwrt/upstream
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path: root/target/linux/lantiq/patches-4.14/0030-GPIO-add-named-gpio-exports.patch
blob: 95cdf8c5af8174c695215c354cfddfdf0b6b674b (plain) 
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