From 266c1ae1226656d90ee6416c214ef64fe8b5906f Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 18 Jul 2019 15:38:09 -0700
Subject: synth_ice40 to decompose into 16x16

---
 techlibs/ice40/synth_ice40.cc | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 0474e76e9..66446deb7 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -265,8 +265,10 @@ struct SynthIce40Pass : public ScriptPass
 			run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4");
 			run("opt_expr");
 			run("opt_clean");
-			if (help_mode || dsp)
+			if (help_mode || dsp) {
+				run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 -D DSP_NAME=$__MUL16X16");
 				run("ice40_dsp", "(if -dsp)");
+			}
 			run("alumacc");
 			run("opt");
 			run("fsm");
-- 
cgit v1.2.3


From bddd641290d3c01d86144362cd0e16c82e0bcfd8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 18 Jul 2019 21:03:54 -0700
Subject: Fix SB_MAC sim model -- do not sign extend internal products?

---
 techlibs/ice40/cells_sim.v | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 609facc93..4402f8d36 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -1363,9 +1363,9 @@ module SB_MAC16 (
 	wire [15:0] p_Ah_Bh, p_Al_Bh, p_Ah_Bl, p_Al_Bl;
 	wire [15:0] Ah, Al, Bh, Bl;
 	assign Ah = {A_SIGNED ? {8{iA[15]}} : 8'b0, iA[15: 8]};
-	assign Al = {A_SIGNED ? {8{iA[ 7]}} : 8'b0, iA[ 7: 0]};
+	assign Al = {A_SIGNED && MODE_8x8 ? {8{iA[ 7]}} : 8'b0, iA[ 7: 0]};
 	assign Bh = {B_SIGNED ? {8{iB[15]}} : 8'b0, iB[15: 8]};
-	assign Bl = {B_SIGNED ? {8{iB[ 7]}} : 8'b0, iB[ 7: 0]};
+	assign Bl = {B_SIGNED && MODE_8x8 ? {8{iB[ 7]}} : 8'b0, iB[ 7: 0]};
 	assign p_Ah_Bh = Ah * Bh;
 	assign p_Al_Bh = Al * Bh;
 	assign p_Ah_Bl = Ah * Bl;
-- 
cgit v1.2.3


From 3dc3c749d5c7c10e1aa504f48794ef0a87513a82 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 19 Jul 2019 11:41:00 -0700
Subject: Add DSP_MINWIDTH=11 for ice40 since ice40_dsp uses this threshold

---
 techlibs/ice40/synth_ice40.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 5053e445d..77bd0ac81 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -266,7 +266,7 @@ struct SynthIce40Pass : public ScriptPass
 			run("opt_expr");
 			run("opt_clean");
 			if (help_mode || dsp) {
-				run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 -D DSP_NAME=$__MUL16X16");
+				run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 -D DSP_MINWIDTH=11 -D DSP_NAME=$__MUL16X16", "(if -dsp)");
 				run("ice40_dsp", "(if -dsp)");
 			}
 			run("alumacc");
-- 
cgit v1.2.3


From 47fd042b9f8a92df1e1d59042068e7846c4ce808 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 19 Jul 2019 20:20:33 -0700
Subject: Indirection via $__soft_mul

---
 techlibs/ice40/synth_ice40.cc | 1 +
 1 file changed, 1 insertion(+)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 77bd0ac81..fcb177491 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -268,6 +268,7 @@ struct SynthIce40Pass : public ScriptPass
 			if (help_mode || dsp) {
 				run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 -D DSP_MINWIDTH=11 -D DSP_NAME=$__MUL16X16", "(if -dsp)");
 				run("ice40_dsp", "(if -dsp)");
+				run("chtype -set $mul t:$__soft_mul");
 			}
 			run("alumacc");
 			run("opt");
-- 
cgit v1.2.3


From 5e70b8a22bf38e622943b0546255befd539fa884 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 22 Jul 2019 13:48:33 -0700
Subject: opt and wreduce necessary for -dsp

---
 techlibs/ice40/synth_ice40.cc | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index fcb177491..ce88a0542 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -267,8 +267,10 @@ struct SynthIce40Pass : public ScriptPass
 			run("opt_clean");
 			if (help_mode || dsp) {
 				run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 -D DSP_MINWIDTH=11 -D DSP_NAME=$__MUL16X16", "(if -dsp)");
-				run("ice40_dsp", "(if -dsp)");
-				run("chtype -set $mul t:$__soft_mul");
+				run("opt_expr", "                     (if -dsp)");
+				run("wreduce", "                      (if -dsp)");
+				run("ice40_dsp", "                    (if -dsp)");
+				run("chtype -set $mul t:$__soft_mul","(if -dsp)");
 			}
 			run("alumacc");
 			run("opt");
-- 
cgit v1.2.3


From 4d71ab384d640f53435d2e4773b2277f385cda27 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 22 Jul 2019 15:08:26 -0700
Subject: Rename according to vendor doc TN1295

---
 techlibs/ice40/synth_ice40.cc | 1 +
 1 file changed, 1 insertion(+)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index ce88a0542..50e071a1a 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -271,6 +271,7 @@ struct SynthIce40Pass : public ScriptPass
 				run("wreduce", "                      (if -dsp)");
 				run("ice40_dsp", "                    (if -dsp)");
 				run("chtype -set $mul t:$__soft_mul","(if -dsp)");
+				run("dump A:top");
 			}
 			run("alumacc");
 			run("opt");
-- 
cgit v1.2.3


From cb505c50d3572a0622110b31b950b43cffc995db Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 22 Jul 2019 16:14:15 -0700
Subject: Remove debug

---
 techlibs/ice40/synth_ice40.cc | 1 -
 1 file changed, 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 50e071a1a..ce88a0542 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -271,7 +271,6 @@ struct SynthIce40Pass : public ScriptPass
 				run("wreduce", "                      (if -dsp)");
 				run("ice40_dsp", "                    (if -dsp)");
 				run("chtype -set $mul t:$__soft_mul","(if -dsp)");
-				run("dump A:top");
 			}
 			run("alumacc");
 			run("opt");
-- 
cgit v1.2.3


From 915f4e34bfdf1fd2b9f97d1c15a55e2c4c49f428 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 1 Aug 2019 13:20:34 -0700
Subject: DSP_MINWIDTH -> DSP_{A,B,Y}_MINWIDTH

---
 techlibs/ice40/synth_ice40.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index ce88a0542..2cc5fd5fd 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -266,7 +266,7 @@ struct SynthIce40Pass : public ScriptPass
 			run("opt_expr");
 			run("opt_clean");
 			if (help_mode || dsp) {
-				run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 -D DSP_MINWIDTH=11 -D DSP_NAME=$__MUL16X16", "(if -dsp)");
+				run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 -D DSP_NAME=$__MUL16X16", "(if -dsp)");
 				run("opt_expr", "                     (if -dsp)");
 				run("wreduce", "                      (if -dsp)");
 				run("ice40_dsp", "                    (if -dsp)");
-- 
cgit v1.2.3


From a206aed977e92a63aa52137690e20897f27df458 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 7 Aug 2019 13:59:07 -0700
Subject: Run "opt_expr -fine" instead of "wreduce" due to #1213

---
 techlibs/ice40/synth_ice40.cc | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 2cc5fd5fd..09759f359 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -267,8 +267,7 @@ struct SynthIce40Pass : public ScriptPass
 			run("opt_clean");
 			if (help_mode || dsp) {
 				run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 -D DSP_NAME=$__MUL16X16", "(if -dsp)");
-				run("opt_expr", "                     (if -dsp)");
-				run("wreduce", "                      (if -dsp)");
+				run("opt_expr -fine", "               (if -dsp)");
 				run("ice40_dsp", "                    (if -dsp)");
 				run("chtype -set $mul t:$__soft_mul","(if -dsp)");
 			}
-- 
cgit v1.2.3


From 2c0be7aa5d7dcdf18678fb7b09ba1b3b5dd00998 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 8 Aug 2019 12:56:05 -0700
Subject: Rework ice40_dsp to map to SB_MAC16 earlier, and check before packing

---
 techlibs/ice40/Makefile.inc   |  1 +
 techlibs/ice40/dsp_map.v      | 34 ++++++++++++++++++++++++++++++++++
 techlibs/ice40/synth_ice40.cc |  2 +-
 3 files changed, 36 insertions(+), 1 deletion(-)
 create mode 100644 techlibs/ice40/dsp_map.v

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/Makefile.inc b/techlibs/ice40/Makefile.inc
index d258d5a5d..b0eadab44 100644
--- a/techlibs/ice40/Makefile.inc
+++ b/techlibs/ice40/Makefile.inc
@@ -28,6 +28,7 @@ $(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_sim.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/latches_map.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams.txt))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams_map.v))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/dsp_map.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_hx.box))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_hx.lut))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_lp.box))
diff --git a/techlibs/ice40/dsp_map.v b/techlibs/ice40/dsp_map.v
new file mode 100644
index 000000000..06fa73956
--- /dev/null
+++ b/techlibs/ice40/dsp_map.v
@@ -0,0 +1,34 @@
+module \$__MUL16X16 (input [15:0] A, input [15:0] B, output [31:0] Y);
+	parameter A_SIGNED = 0;
+	parameter B_SIGNED = 0;
+	parameter A_WIDTH = 0;
+	parameter B_WIDTH = 0;
+	parameter Y_WIDTH = 0;
+
+	SB_MAC16 #(
+		.NEG_TRIGGER(1'b0),
+		.C_REG(1'b0),
+		.A_REG(1'b0),
+		.B_REG(1'b0),
+		.D_REG(1'b0),
+		.TOP_8x8_MULT_REG(1'b0),
+		.BOT_8x8_MULT_REG(1'b0),
+		.PIPELINE_16x16_MULT_REG1(1'b0),
+		.PIPELINE_16x16_MULT_REG2(1'b0),
+		.TOPOUTPUT_SELECT(2'b11),
+		.TOPADDSUB_LOWERINPUT(2'b0),
+		.TOPADDSUB_UPPERINPUT(1'b0),
+		.TOPADDSUB_CARRYSELECT(2'b0),
+		.BOTOUTPUT_SELECT(2'b11),
+		.BOTADDSUB_LOWERINPUT(2'b0),
+		.BOTADDSUB_UPPERINPUT(1'b0),
+		.BOTADDSUB_CARRYSELECT(2'b0),
+		.MODE_8x8(1'b0),
+		.A_SIGNED(A_SIGNED),
+		.B_SIGNED(B_SIGNED)
+	) _TECHMAP_REPLACE_ (
+		.A(A),
+		.B(B),
+		.O(Y),
+	);
+endmodule
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 09759f359..9c3670c7c 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -266,7 +266,7 @@ struct SynthIce40Pass : public ScriptPass
 			run("opt_expr");
 			run("opt_clean");
 			if (help_mode || dsp) {
-				run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 -D DSP_NAME=$__MUL16X16", "(if -dsp)");
+				run("techmap -map +/mul2dsp.v -map +/ice40/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 -D DSP_NAME=$__MUL16X16", "(if -dsp)");
 				run("opt_expr -fine", "               (if -dsp)");
 				run("ice40_dsp", "                    (if -dsp)");
 				run("chtype -set $mul t:$__soft_mul","(if -dsp)");
-- 
cgit v1.2.3


From 6d254f2de802ccd71b6514b0f5e4c0b44c415ae4 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 9 Aug 2019 17:05:56 -0700
Subject: Add wreduce to synth_ice40 -dsp as well

---
 techlibs/ice40/synth_ice40.cc | 1 +
 1 file changed, 1 insertion(+)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 9c3670c7c..02598401c 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -268,6 +268,7 @@ struct SynthIce40Pass : public ScriptPass
 			if (help_mode || dsp) {
 				run("techmap -map +/mul2dsp.v -map +/ice40/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 -D DSP_NAME=$__MUL16X16", "(if -dsp)");
 				run("opt_expr -fine", "               (if -dsp)");
+				run("wreduce", "                      (if -dsp)");
 				run("ice40_dsp", "                    (if -dsp)");
 				run("chtype -set $mul t:$__soft_mul","(if -dsp)");
 			}
-- 
cgit v1.2.3


From e4f89e01b5710eb9e2e6675a1df13a5a2637b206 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 17:21:12 -0700
Subject: Specify ice40 family to cells_sim.v using define

---
 techlibs/ice40/synth_ice40.cc | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index c6de81bd9..2f77c03db 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -238,7 +238,14 @@ struct SynthIce40Pass : public ScriptPass
 	{
 		if (check_label("begin"))
 		{
-			run("read_verilog -icells -lib +/ice40/cells_sim.v");
+			std::string define;
+			if (device_opt == "lp")
+				define = "-D ICE40_LX";
+			else if (device_opt == "u")
+				define = "-D ICE40_U";
+			else
+				define = "-D ICE40_HX";
+			run("read_verilog -icells " + define + " -lib +/ice40/cells_sim.v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 			run("proc");
 		}
-- 
cgit v1.2.3


From 2421cb3fed1a990219227ed3cf0632eb221e9698 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 17:21:37 -0700
Subject: Add arrival times for HX devices

---
 techlibs/ice40/cells_sim.v | 135 ++++++++++++++++++++++++++++++++++++++-------
 1 file changed, 114 insertions(+), 21 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 02726605f..261d99c9b 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -2,6 +2,10 @@
 `define SB_DFF_REG reg Q = 0
 // `define SB_DFF_REG reg Q
 
+`define ABC_ARRIVAL_HX(TIME) `ifdef ICE40_HX (* abc_arrival=TIME *) `endif
+`define ABC_ARRIVAL_LX(TIME) `ifdef ICE40_LX (* abc_arrival=TIME *) `endif
+`define ABC_ARRIVAL_U(TIME)  `ifdef ICE40_U (* abc_arrival=TIME *) `endif
+
 // SiliconBlue IO Cells
 
 module SB_IO (
@@ -169,20 +173,34 @@ module \$__ICE40_CARRY_WRAPPER (
 	);
 endmodule
 
+// Max delay from: https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
+
 // Positive Edge SiliconBlue FF Cells
 
-module SB_DFF (output `SB_DFF_REG, input C, D);
+module SB_DFF (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, D
+);
 	always @(posedge C)
 		Q <= D;
 endmodule
 
-module SB_DFFE (output `SB_DFF_REG, input C, E, D);
+module SB_DFFE (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, E, D
+);
 	always @(posedge C)
 		if (E)
 			Q <= D;
 endmodule
 
-module SB_DFFSR (output `SB_DFF_REG, input C, R, D);
+module SB_DFFSR (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, R, D
+);
 	always @(posedge C)
 		if (R)
 			Q <= 0;
@@ -190,7 +208,11 @@ module SB_DFFSR (output `SB_DFF_REG, input C, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFR (output `SB_DFF_REG, input C, R, D);
+module SB_DFFR (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, R, D
+);
 	always @(posedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -198,7 +220,11 @@ module SB_DFFR (output `SB_DFF_REG, input C, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFSS (output `SB_DFF_REG, input C, S, D);
+module SB_DFFSS (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, S, D
+);
 	always @(posedge C)
 		if (S)
 			Q <= 1;
@@ -206,7 +232,11 @@ module SB_DFFSS (output `SB_DFF_REG, input C, S, D);
 			Q <= D;
 endmodule
 
-module SB_DFFS (output `SB_DFF_REG, input C, S, D);
+module SB_DFFS (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, S, D
+);
 	always @(posedge C, posedge S)
 		if (S)
 			Q <= 1;
@@ -214,7 +244,11 @@ module SB_DFFS (output `SB_DFF_REG, input C, S, D);
 			Q <= D;
 endmodule
 
-module SB_DFFESR (output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFESR (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, E, R, D
+);
 	always @(posedge C)
 		if (E) begin
 			if (R)
@@ -224,7 +258,11 @@ module SB_DFFESR (output `SB_DFF_REG, input C, E, R, D);
 		end
 endmodule
 
-module SB_DFFER (output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFER (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, E, R, D
+);
 	always @(posedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -232,7 +270,11 @@ module SB_DFFER (output `SB_DFF_REG, input C, E, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFESS (output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFESS (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, E, S, D
+);
 	always @(posedge C)
 		if (E) begin
 			if (S)
@@ -242,7 +284,11 @@ module SB_DFFESS (output `SB_DFF_REG, input C, E, S, D);
 		end
 endmodule
 
-module SB_DFFES (output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFES (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, E, S, D
+);
 	always @(posedge C, posedge S)
 		if (S)
 			Q <= 1;
@@ -252,18 +298,30 @@ endmodule
 
 // Negative Edge SiliconBlue FF Cells
 
-module SB_DFFN (output `SB_DFF_REG, input C, D);
+module SB_DFFN (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, D
+);
 	always @(negedge C)
 		Q <= D;
 endmodule
 
-module SB_DFFNE (output `SB_DFF_REG, input C, E, D);
+module SB_DFFNE (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, E, D
+);
 	always @(negedge C)
 		if (E)
 			Q <= D;
 endmodule
 
-module SB_DFFNSR (output `SB_DFF_REG, input C, R, D);
+module SB_DFFNSR (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, R, D
+);
 	always @(negedge C)
 		if (R)
 			Q <= 0;
@@ -271,7 +329,11 @@ module SB_DFFNSR (output `SB_DFF_REG, input C, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNR (output `SB_DFF_REG, input C, R, D);
+module SB_DFFNR (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, R, D
+);
 	always @(negedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -279,7 +341,11 @@ module SB_DFFNR (output `SB_DFF_REG, input C, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNSS (output `SB_DFF_REG, input C, S, D);
+module SB_DFFNSS (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, S, D
+);
 	always @(negedge C)
 		if (S)
 			Q <= 1;
@@ -287,7 +353,11 @@ module SB_DFFNSS (output `SB_DFF_REG, input C, S, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNS (output `SB_DFF_REG, input C, S, D);
+module SB_DFFNS (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, S, D
+);
 	always @(negedge C, posedge S)
 		if (S)
 			Q <= 1;
@@ -295,7 +365,11 @@ module SB_DFFNS (output `SB_DFF_REG, input C, S, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNESR (output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFNESR (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, E, R, D
+);
 	always @(negedge C)
 		if (E) begin
 			if (R)
@@ -305,7 +379,11 @@ module SB_DFFNESR (output `SB_DFF_REG, input C, E, R, D);
 		end
 endmodule
 
-module SB_DFFNER (output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFNER (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, E, R, D
+);
 	always @(negedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -313,7 +391,11 @@ module SB_DFFNER (output `SB_DFF_REG, input C, E, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNESS (output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFNESS (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, E, S, D
+);
 	always @(negedge C)
 		if (E) begin
 			if (S)
@@ -323,7 +405,11 @@ module SB_DFFNESS (output `SB_DFF_REG, input C, E, S, D);
 		end
 endmodule
 
-module SB_DFFNES (output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFNES (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, E, S, D
+);
 	always @(negedge C, posedge S)
 		if (S)
 			Q <= 1;
@@ -334,6 +420,7 @@ endmodule
 // SiliconBlue RAM Cells
 
 module SB_RAM40_4K (
+	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
 	output [15:0] RDATA,
 	input         RCLK, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -502,6 +589,7 @@ module SB_RAM40_4K (
 endmodule
 
 module SB_RAM40_4KNR (
+	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
 	output [15:0] RDATA,
 	input         RCLKN, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -567,6 +655,7 @@ module SB_RAM40_4KNR (
 endmodule
 
 module SB_RAM40_4KNW (
+	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
 	output [15:0] RDATA,
 	input         RCLK, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -632,6 +721,7 @@ module SB_RAM40_4KNW (
 endmodule
 
 module SB_RAM40_4KNRNW (
+	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
 	output [15:0] RDATA,
 	input         RCLKN, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -700,7 +790,10 @@ endmodule
 
 module ICESTORM_LC (
 	input I0, I1, I2, I3, CIN, CLK, CEN, SR,
-	output LO, O, COUT
+	output LO,
+	`ABC_ARRIVAL_HX(540)
+	output O,
+	output COUT
 );
 	parameter [15:0] LUT_INIT = 0;
 
-- 
cgit v1.2.3


From c0b99ed0e8c8c6adf76d70fa71c9753957162e04 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 18:45:09 -0700
Subject: Do not overwrite LUT param

---
 techlibs/ice40/ice40_opt.cc | 1 -
 1 file changed, 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index 58f106f7c..ea56d3f4d 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -125,7 +125,6 @@ static void run_ice40_opts(Module *module)
 				cell->unsetPort("\\I3");
 				cell->unsetPort("\\CO");
 				cell->unsetPort("\\O");
-				cell->setParam("\\LUT", RTLIL::Const::from_string("0110100110010110"));
 				cell->setParam("\\WIDTH", 4);
 			}
 			continue;
-- 
cgit v1.2.3


From e3709e5ee6b28c1156b4768373e244c32c7c5aba Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 18:51:14 -0700
Subject: LX -> LP

---
 techlibs/ice40/cells_sim.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 34134d02a..fe80c998d 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -3,7 +3,7 @@
 // `define SB_DFF_REG reg Q
 
 `define ABC_ARRIVAL_HX(TIME) `ifdef ICE40_HX (* abc_arrival=TIME *) `endif
-`define ABC_ARRIVAL_LX(TIME) `ifdef ICE40_LX (* abc_arrival=TIME *) `endif
+`define ABC_ARRIVAL_LP(TIME) `ifdef ICE40_LP (* abc_arrival=TIME *) `endif
 `define ABC_ARRIVAL_U(TIME)  `ifdef ICE40_U (* abc_arrival=TIME *) `endif
 
 // SiliconBlue IO Cells
-- 
cgit v1.2.3


From 927f1e3754987ab794566a521c7a1149d4fbf6a7 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 18:56:25 -0700
Subject: Add LP timings

---
 techlibs/ice40/cells_sim.v | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index fe80c998d..b86ec3ea5 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -174,11 +174,13 @@ module \$__ICE40_CARRY_WRAPPER (
 endmodule
 
 // Max delay from: https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
+//                 https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
 
 // Positive Edge SiliconBlue FF Cells
 
 module SB_DFF (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, D
 );
@@ -188,6 +190,7 @@ endmodule
 
 module SB_DFFE (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, E, D
 );
@@ -198,6 +201,7 @@ endmodule
 
 module SB_DFFSR (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -210,6 +214,7 @@ endmodule
 
 module SB_DFFR (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -222,6 +227,7 @@ endmodule
 
 module SB_DFFSS (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -234,6 +240,7 @@ endmodule
 
 module SB_DFFS (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -246,6 +253,7 @@ endmodule
 
 module SB_DFFESR (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -260,6 +268,7 @@ endmodule
 
 module SB_DFFER (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -272,6 +281,7 @@ endmodule
 
 module SB_DFFESS (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -286,6 +296,7 @@ endmodule
 
 module SB_DFFES (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -300,6 +311,7 @@ endmodule
 
 module SB_DFFN (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, D
 );
@@ -309,6 +321,7 @@ endmodule
 
 module SB_DFFNE (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, E, D
 );
@@ -319,6 +332,7 @@ endmodule
 
 module SB_DFFNSR (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -331,6 +345,7 @@ endmodule
 
 module SB_DFFNR (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -343,6 +358,7 @@ endmodule
 
 module SB_DFFNSS (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -355,6 +371,7 @@ endmodule
 
 module SB_DFFNS (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -367,6 +384,7 @@ endmodule
 
 module SB_DFFNESR (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -381,6 +399,7 @@ endmodule
 
 module SB_DFFNER (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -393,6 +412,7 @@ endmodule
 
 module SB_DFFNESS (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -407,6 +427,7 @@ endmodule
 
 module SB_DFFNES (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -421,6 +442,7 @@ endmodule
 
 module SB_RAM40_4K (
 	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
+	`ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
 	output [15:0] RDATA,
 	input         RCLK, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -590,6 +612,7 @@ endmodule
 
 module SB_RAM40_4KNR (
 	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
+	`ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
 	output [15:0] RDATA,
 	input         RCLKN, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -656,6 +679,7 @@ endmodule
 
 module SB_RAM40_4KNW (
 	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
+	`ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
 	output [15:0] RDATA,
 	input         RCLK, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -722,6 +746,7 @@ endmodule
 
 module SB_RAM40_4KNRNW (
 	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
+	`ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
 	output [15:0] RDATA,
 	input         RCLKN, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -792,6 +817,7 @@ module ICESTORM_LC (
 	input I0, I1, I2, I3, CIN, CLK, CEN, SR,
 	output LO,
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output O,
 	output COUT
 );
-- 
cgit v1.2.3


From 0f4e9f6bc5a5a564b2ddccb0fbebdfa5735aeefd Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 18:57:34 -0700
Subject: Round not floor

---
 techlibs/ice40/cells_sim.v | 42 +++++++++++++++++++++---------------------
 1 file changed, 21 insertions(+), 21 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index b86ec3ea5..f5fe800f7 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -180,7 +180,7 @@ endmodule
 
 module SB_DFF (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, D
 );
@@ -190,7 +190,7 @@ endmodule
 
 module SB_DFFE (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, E, D
 );
@@ -201,7 +201,7 @@ endmodule
 
 module SB_DFFSR (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -214,7 +214,7 @@ endmodule
 
 module SB_DFFR (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -227,7 +227,7 @@ endmodule
 
 module SB_DFFSS (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -240,7 +240,7 @@ endmodule
 
 module SB_DFFS (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -253,7 +253,7 @@ endmodule
 
 module SB_DFFESR (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -268,7 +268,7 @@ endmodule
 
 module SB_DFFER (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -281,7 +281,7 @@ endmodule
 
 module SB_DFFESS (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -296,7 +296,7 @@ endmodule
 
 module SB_DFFES (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -311,7 +311,7 @@ endmodule
 
 module SB_DFFN (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, D
 );
@@ -321,7 +321,7 @@ endmodule
 
 module SB_DFFNE (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, E, D
 );
@@ -332,7 +332,7 @@ endmodule
 
 module SB_DFFNSR (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -345,7 +345,7 @@ endmodule
 
 module SB_DFFNR (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -358,7 +358,7 @@ endmodule
 
 module SB_DFFNSS (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -371,7 +371,7 @@ endmodule
 
 module SB_DFFNS (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -384,7 +384,7 @@ endmodule
 
 module SB_DFFNESR (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -399,7 +399,7 @@ endmodule
 
 module SB_DFFNER (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -412,7 +412,7 @@ endmodule
 
 module SB_DFFNESS (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -427,7 +427,7 @@ endmodule
 
 module SB_DFFNES (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -817,7 +817,7 @@ module ICESTORM_LC (
 	input I0, I1, I2, I3, CIN, CLK, CEN, SR,
 	output LO,
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output O,
 	output COUT
 );
-- 
cgit v1.2.3


From 4bda902f1b9dccb5603c2beebd71392cbfe34eb9 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 19:02:54 -0700
Subject: LX -> LP

---
 techlibs/ice40/synth_ice40.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 2f77c03db..a3890268a 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -240,7 +240,7 @@ struct SynthIce40Pass : public ScriptPass
 		{
 			std::string define;
 			if (device_opt == "lp")
-				define = "-D ICE40_LX";
+				define = "-D ICE40_LP";
 			else if (device_opt == "u")
 				define = "-D ICE40_U";
 			else
-- 
cgit v1.2.3


From efa4ee5c0e6201f357d7c02a7deeb1ba1c23c368 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 19:03:29 -0700
Subject: Add arrival times for U

---
 techlibs/ice40/cells_sim.v | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index f5fe800f7..116188acb 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -175,12 +175,14 @@ endmodule
 
 // Max delay from: https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
 //                 https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
+//                 https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
 
 // Positive Edge SiliconBlue FF Cells
 
 module SB_DFF (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, D
 );
@@ -191,6 +193,7 @@ endmodule
 module SB_DFFE (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, D
 );
@@ -202,6 +205,7 @@ endmodule
 module SB_DFFSR (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -215,6 +219,7 @@ endmodule
 module SB_DFFR (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -228,6 +233,7 @@ endmodule
 module SB_DFFSS (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -241,6 +247,7 @@ endmodule
 module SB_DFFS (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -254,6 +261,7 @@ endmodule
 module SB_DFFESR (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -269,6 +277,7 @@ endmodule
 module SB_DFFER (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -282,6 +291,7 @@ endmodule
 module SB_DFFESS (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -297,6 +307,7 @@ endmodule
 module SB_DFFES (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -312,6 +323,7 @@ endmodule
 module SB_DFFN (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, D
 );
@@ -322,6 +334,7 @@ endmodule
 module SB_DFFNE (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, D
 );
@@ -333,6 +346,7 @@ endmodule
 module SB_DFFNSR (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -346,6 +360,7 @@ endmodule
 module SB_DFFNR (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -359,6 +374,7 @@ endmodule
 module SB_DFFNSS (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -372,6 +388,7 @@ endmodule
 module SB_DFFNS (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -385,6 +402,7 @@ endmodule
 module SB_DFFNESR (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -400,6 +418,7 @@ endmodule
 module SB_DFFNER (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -413,6 +432,7 @@ endmodule
 module SB_DFFNESS (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -428,6 +448,7 @@ endmodule
 module SB_DFFNES (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -443,6 +464,7 @@ endmodule
 module SB_RAM40_4K (
 	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
 	`ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
+	`ABC_ARRIVAL_U(1179)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
 	output [15:0] RDATA,
 	input         RCLK, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -613,6 +635,7 @@ endmodule
 module SB_RAM40_4KNR (
 	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
 	`ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
+	`ABC_ARRIVAL_U(1179)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
 	output [15:0] RDATA,
 	input         RCLKN, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -680,6 +703,7 @@ endmodule
 module SB_RAM40_4KNW (
 	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
 	`ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
+	`ABC_ARRIVAL_U(1179)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
 	output [15:0] RDATA,
 	input         RCLK, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -747,6 +771,7 @@ endmodule
 module SB_RAM40_4KNRNW (
 	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
 	`ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
+	`ABC_ARRIVAL_U(1179)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
 	output [15:0] RDATA,
 	input         RCLKN, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -818,6 +843,7 @@ module ICESTORM_LC (
 	output LO,
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output O,
 	output COUT
 );
-- 
cgit v1.2.3


From 309684af16c763f7874beb605d0834c64975d004 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 19:07:28 -0700
Subject: Add arrival for SB_MAC16.O

---
 techlibs/ice40/cells_sim.v | 1 +
 1 file changed, 1 insertion(+)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 116188acb..f4cc342eb 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -1445,6 +1445,7 @@ module SB_MAC16 (
 	input ADDSUBTOP, ADDSUBBOT,
 	input OHOLDTOP, OHOLDBOT,
 	input CI, ACCUMCI, SIGNEXTIN,
+	`ABC_ARRIVAL_U(1984)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L587
 	output [31:0] O,
 	output CO, ACCUMCO, SIGNEXTOUT
 );
-- 
cgit v1.2.3


From e8e38308689a760b69bd2910a36701b19f64656d Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 19:09:29 -0700
Subject: Comment out SB_MAC16 arrival time for now, need to handle all its
 modes

---
 techlibs/ice40/cells_sim.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index f4cc342eb..8e5e0358e 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -1445,7 +1445,7 @@ module SB_MAC16 (
 	input ADDSUBTOP, ADDSUBBOT,
 	input OHOLDTOP, OHOLDBOT,
 	input CI, ACCUMCI, SIGNEXTIN,
-	`ABC_ARRIVAL_U(1984)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L587
+	//`ABC_ARRIVAL_U(1984)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
 	output [31:0] O,
 	output CO, ACCUMCO, SIGNEXTOUT
 );
-- 
cgit v1.2.3


From 3b9b0fcd0630133092b23a18453eb420534b2369 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 19 Sep 2019 14:57:38 -0700
Subject: Tidy up synth_ice40, only restrict DSP_B_MINWIDTH=2

---
 techlibs/ice40/synth_ice40.cc | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 55aa72aa7..284bc90d0 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -273,7 +273,9 @@ struct SynthIce40Pass : public ScriptPass
 			run("opt_expr");
 			run("opt_clean");
 			if (help_mode || dsp) {
-				run("techmap -map +/mul2dsp.v -map +/ice40/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 -D DSP_NAME=$__MUL16X16", "(if -dsp)");
+				run("techmap -map +/mul2dsp.v -map +/ice40/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 "
+						"-D DSP_A_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 "
+						"-D DSP_NAME=$__MUL16X16", "(if -dsp)");
 				run("opt_expr -fine", "               (if -dsp)");
 				run("wreduce", "                      (if -dsp)");
 				run("ice40_dsp", "                    (if -dsp)");
-- 
cgit v1.2.3


From e4f4f6a9d5cf8bb23870fc483f16f66c80ceebab Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 20 Sep 2019 08:41:40 -0700
Subject: Move mul2dsp before wreduce

---
 techlibs/ice40/synth_ice40.cc | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 284bc90d0..225603475 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -265,6 +265,10 @@ struct SynthIce40Pass : public ScriptPass
 			run("opt_clean");
 			run("check");
 			run("opt");
+			if (help_mode || dsp)
+				run("techmap -map +/mul2dsp.v -map +/ice40/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 "
+						"-D DSP_A_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 "
+						"-D DSP_NAME=$__MUL16X16", "(if -dsp)");
 			run("wreduce");
 			run("peepopt");
 			run("opt_clean");
@@ -273,11 +277,6 @@ struct SynthIce40Pass : public ScriptPass
 			run("opt_expr");
 			run("opt_clean");
 			if (help_mode || dsp) {
-				run("techmap -map +/mul2dsp.v -map +/ice40/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 "
-						"-D DSP_A_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 "
-						"-D DSP_NAME=$__MUL16X16", "(if -dsp)");
-				run("opt_expr -fine", "               (if -dsp)");
-				run("wreduce", "                      (if -dsp)");
 				run("ice40_dsp", "                    (if -dsp)");
 				run("chtype -set $mul t:$__soft_mul","(if -dsp)");
 			}
-- 
cgit v1.2.3


From 829e4f5d2c8a521b5e4f80e85b9d58191d64f0d5 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 20 Sep 2019 08:56:16 -0700
Subject: Revert "Move mul2dsp before wreduce"

This reverts commit e4f4f6a9d5cf8bb23870fc483f16f66c80ceebab.
---
 techlibs/ice40/synth_ice40.cc | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 225603475..284bc90d0 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -265,10 +265,6 @@ struct SynthIce40Pass : public ScriptPass
 			run("opt_clean");
 			run("check");
 			run("opt");
-			if (help_mode || dsp)
-				run("techmap -map +/mul2dsp.v -map +/ice40/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 "
-						"-D DSP_A_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 "
-						"-D DSP_NAME=$__MUL16X16", "(if -dsp)");
 			run("wreduce");
 			run("peepopt");
 			run("opt_clean");
@@ -277,6 +273,11 @@ struct SynthIce40Pass : public ScriptPass
 			run("opt_expr");
 			run("opt_clean");
 			if (help_mode || dsp) {
+				run("techmap -map +/mul2dsp.v -map +/ice40/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 "
+						"-D DSP_A_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 "
+						"-D DSP_NAME=$__MUL16X16", "(if -dsp)");
+				run("opt_expr -fine", "               (if -dsp)");
+				run("wreduce", "                      (if -dsp)");
 				run("ice40_dsp", "                    (if -dsp)");
 				run("chtype -set $mul t:$__soft_mul","(if -dsp)");
 			}
-- 
cgit v1.2.3


From 289cf688b76328d62c7416d1327d2d6777b0ffd9 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 20 Sep 2019 09:02:29 -0700
Subject: Re-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine from synth_ice40

---
 techlibs/ice40/synth_ice40.cc | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 284bc90d0..7a8f3d70c 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -274,9 +274,8 @@ struct SynthIce40Pass : public ScriptPass
 			run("opt_clean");
 			if (help_mode || dsp) {
 				run("techmap -map +/mul2dsp.v -map +/ice40/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 "
-						"-D DSP_A_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 "
+						"-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 "
 						"-D DSP_NAME=$__MUL16X16", "(if -dsp)");
-				run("opt_expr -fine", "               (if -dsp)");
 				run("wreduce", "                      (if -dsp)");
 				run("ice40_dsp", "                    (if -dsp)");
 				run("chtype -set $mul t:$__soft_mul","(if -dsp)");
-- 
cgit v1.2.3


From 63940913d21fcfb18cd844d7e5b9c8b41a82295b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 25 Sep 2019 17:22:04 -0700
Subject: Only wreduce on t:$add

---
 techlibs/ice40/synth_ice40.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 7a8f3d70c..98d3e44e3 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -276,7 +276,7 @@ struct SynthIce40Pass : public ScriptPass
 				run("techmap -map +/mul2dsp.v -map +/ice40/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 "
 						"-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 "
 						"-D DSP_NAME=$__MUL16X16", "(if -dsp)");
-				run("wreduce", "                      (if -dsp)");
+				run("wreduce t:$add", "               (if -dsp)");
 				run("ice40_dsp", "                    (if -dsp)");
 				run("chtype -set $mul t:$__soft_mul","(if -dsp)");
 			}
-- 
cgit v1.2.3


From 27e5bf5aad229ef330bfea932f6b194ec5c09b68 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 26 Sep 2019 09:57:11 -0700
Subject: Stop trying to be too smart by prematurely optimising

---
 techlibs/ice40/synth_ice40.cc | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 98d3e44e3..694782e5b 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -276,9 +276,11 @@ struct SynthIce40Pass : public ScriptPass
 				run("techmap -map +/mul2dsp.v -map +/ice40/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 "
 						"-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 "
 						"-D DSP_NAME=$__MUL16X16", "(if -dsp)");
-				run("wreduce t:$add", "               (if -dsp)");
-				run("ice40_dsp", "                    (if -dsp)");
-				run("chtype -set $mul t:$__soft_mul","(if -dsp)");
+				run("opt_expr -fine a:mul2dsp", "        (if -dsp)");
+				run("wreduce a:mul2dsp", "               (if -dsp)");
+				run("ice40_dsp", "                       (if -dsp)");
+				run("setattr -unset mul2dsp a:mul2dsp", "(if -dsp)");
+				run("chtype -set $mul t:$__soft_mul", "  (if -dsp)");
 			}
 			run("alumacc");
 			run("opt");
-- 
cgit v1.2.3


From 781dda6175c86fcb2b08d055565d3d99a687e636 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 26 Sep 2019 10:15:05 -0700
Subject: select once

---
 techlibs/ice40/synth_ice40.cc | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 694782e5b..52e13bdc2 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -276,11 +276,13 @@ struct SynthIce40Pass : public ScriptPass
 				run("techmap -map +/mul2dsp.v -map +/ice40/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 "
 						"-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 "
 						"-D DSP_NAME=$__MUL16X16", "(if -dsp)");
-				run("opt_expr -fine a:mul2dsp", "        (if -dsp)");
-				run("wreduce a:mul2dsp", "               (if -dsp)");
-				run("ice40_dsp", "                       (if -dsp)");
-				run("setattr -unset mul2dsp a:mul2dsp", "(if -dsp)");
-				run("chtype -set $mul t:$__soft_mul", "  (if -dsp)");
+				run("select a:mul2dsp", "              (if -dsp)");
+				run("opt_expr -fine", "                (if -dsp)");
+				run("wreduce", "                       (if -dsp)");
+				run("setattr -unset mul2dsp", "        (if -dsp)");
+				run("select -clear", "                 (if -dsp)");
+				run("ice40_dsp", "                     (if -dsp)");
+				run("chtype -set $mul t:$__soft_mul", "(if -dsp)");
 			}
 			run("alumacc");
 			run("opt");
-- 
cgit v1.2.3


From b3d8a60cbd94176076f23c4ea6c94ec24e6773e0 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 27 Sep 2019 14:32:07 -0700
Subject: Re-order

---
 techlibs/ice40/synth_ice40.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 52e13bdc2..841f10244 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -277,9 +277,9 @@ struct SynthIce40Pass : public ScriptPass
 						"-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 "
 						"-D DSP_NAME=$__MUL16X16", "(if -dsp)");
 				run("select a:mul2dsp", "              (if -dsp)");
+				run("setattr -unset mul2dsp", "        (if -dsp)");
 				run("opt_expr -fine", "                (if -dsp)");
 				run("wreduce", "                       (if -dsp)");
-				run("setattr -unset mul2dsp", "        (if -dsp)");
 				run("select -clear", "                 (if -dsp)");
 				run("ice40_dsp", "                     (if -dsp)");
 				run("chtype -set $mul t:$__soft_mul", "(if -dsp)");
-- 
cgit v1.2.3