From d81a090d89d87837d3e18f9c724fe5c89ddf1f64 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 19 Aug 2019 09:56:17 -0700 Subject: Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro --- techlibs/ice40/cells_sim.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'techlibs/ice40') diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index 5b18fec27..ab04808f4 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -143,11 +143,11 @@ endmodule (* abc_box_id = 1, lib_whitebox *) module \$__ICE40_FULL_ADDER ( - (* abc_carry_out *) output CO, + (* abc_carry *) output CO, output O, input A, input B, - (* abc_carry_in *) input CI + (* abc_carry *) input CI ); SB_CARRY carry ( .I0(A), -- cgit v1.2.3