From 323dd0e608b38116db1e2bcda1ebc4ba98823990 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Thu, 14 Feb 2019 13:19:27 -0800
Subject: synth_ice40 to have new -abc9 arg

---
 techlibs/ice40/synth_ice40.cc | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index f900453e8..f77ea7f80 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -89,13 +89,16 @@ struct SynthIce40Pass : public ScriptPass
 		log("        generate an output netlist (and BLIF file) suitable for VPR\n");
 		log("        (this feature is experimental and incomplete)\n");
 		log("\n");
+		log("    -abc9\n");
+		log("        use abc9 instead of abc\n");
+		log("\n");
 		log("\n");
 		log("The following commands are executed by this synthesis command:\n");
 		help_script();
 		log("\n");
 	}
 
-	string top_opt, blif_file, edif_file, json_file;
+	string top_opt, blif_file, edif_file, json_file, abc;
 	bool nocarry, nodffe, nobram, flatten, retime, relut, noabc, abc2, vpr;
 	int min_ce_use;
 
@@ -115,6 +118,7 @@ struct SynthIce40Pass : public ScriptPass
 		noabc = false;
 		abc2 = false;
 		vpr = false;
+		abc = "abc";
 	}
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@@ -193,6 +197,10 @@ struct SynthIce40Pass : public ScriptPass
 				vpr = true;
 				continue;
 			}
+			if (args[argidx] == "-abc9") {
+				abc = "abc9";
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
@@ -249,7 +257,7 @@ struct SynthIce40Pass : public ScriptPass
 			else
 				run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
 			if (retime || help_mode)
-				run("abc -dff", "(only if -retime)");
+				run(abc + " -dff", "(only if -retime)");
 			run("ice40_opt");
 		}
 
@@ -273,7 +281,7 @@ struct SynthIce40Pass : public ScriptPass
 		if (check_label("map_luts"))
 		{
 			if (abc2 || help_mode) {
-				run("abc", "      (only if -abc2)");
+				run(abc, "      (only if -abc2)");
 				run("ice40_opt", "(only if -abc2)");
 			}
 			run("techmap -map +/ice40/latches_map.v");
@@ -282,7 +290,7 @@ struct SynthIce40Pass : public ScriptPass
 				run("techmap -map +/gate2lut.v -D LUT_WIDTH=4", "(only if -noabc)");
 			}
 			if (!noabc) {
-				run("abc -lut 4", "(skip if -noabc)");
+				run(abc + " -lut 4", "(skip if -noabc)");
 			}
 			run("clean");
 			if (relut || help_mode) {
-- 
cgit v1.2.3


From 7980118d74aae04479be3b9e9b59f95bf3bfbfe5 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 16 Apr 2019 16:39:30 -0700
Subject: Add ice40 box files

---
 techlibs/ice40/Makefile.inc   | 3 +++
 techlibs/ice40/cells.box      | 6 ++++++
 techlibs/ice40/cells_box.v    | 5 +++++
 techlibs/ice40/cells_sim.v    | 1 +
 techlibs/ice40/lut.lut        | 4 ++++
 techlibs/ice40/synth_ice40.cc | 9 ++++++++-
 6 files changed, 27 insertions(+), 1 deletion(-)
 create mode 100644 techlibs/ice40/cells.box
 create mode 100644 techlibs/ice40/cells_box.v
 create mode 100644 techlibs/ice40/lut.lut

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/Makefile.inc b/techlibs/ice40/Makefile.inc
index 723b59d6f..cd992bb24 100644
--- a/techlibs/ice40/Makefile.inc
+++ b/techlibs/ice40/Makefile.inc
@@ -28,6 +28,9 @@ $(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_sim.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/latches_map.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams.txt))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams_map.v))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/cells.box))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_box.v))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/lut.lut))
 
 $(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init1.vh))
 $(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init2.vh))
diff --git a/techlibs/ice40/cells.box b/techlibs/ice40/cells.box
new file mode 100644
index 000000000..e4cfb71e6
--- /dev/null
+++ b/techlibs/ice40/cells.box
@@ -0,0 +1,6 @@
+# NB: Inputs/Outputs must be ordered alphabetically
+
+# Inputs: CI I0 I1
+# Outputs: CO
+SB_CARRY 1 1 3 1
+126 259 231
diff --git a/techlibs/ice40/cells_box.v b/techlibs/ice40/cells_box.v
new file mode 100644
index 000000000..cca88f9aa
--- /dev/null
+++ b/techlibs/ice40/cells_box.v
@@ -0,0 +1,5 @@
+(* abc_box_id = 1 *)
+module SB_CARRY (output CO, input CI, I0, I1);
+	assign CO = (I0 && I1) || ((I0 || I1) && CI);
+endmodule
+
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 62a28364b..322c1e5c7 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -881,6 +881,7 @@ module SB_WARMBOOT (
 );
 endmodule
 
+(* nomem2reg *)
 module SB_SPRAM256KA (
 	input [13:0] ADDRESS,
 	input [15:0] DATAIN,
diff --git a/techlibs/ice40/lut.lut b/techlibs/ice40/lut.lut
new file mode 100644
index 000000000..48da89f46
--- /dev/null
+++ b/techlibs/ice40/lut.lut
@@ -0,0 +1,4 @@
+1	1	316
+2	1	316 379
+3	1	316 379 400
+4	1	316	379	400	449
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 6c77e5482..3faa10b4f 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -316,7 +316,14 @@ struct SynthIce40Pass : public ScriptPass
 				run("techmap -map +/gate2lut.v -D LUT_WIDTH=4", "(only if -noabc)");
 			}
 			if (!noabc) {
-				run(abc + " -dress -lut 4", "(skip if -noabc)");
+				if (abc == "abc9") {
+					run("read_verilog +/ice40/cells_box.v");
+					run("techmap -map +/techmap.v A:abc_box_id");
+					run(abc + " -dress -lut +/ice40/lut.lut -box +/ice40/cells.box", "(skip if -noabc)");
+					run("blackbox A:abc_box_id");
+				}
+				else
+					run(abc + " -lut 4", "(skip if -noabc)");
 			}
 			run("clean");
 			if (relut || help_mode) {
-- 
cgit v1.2.3


From 743c164eee06abb44601e00304db18cdb36a180f Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 16 Apr 2019 17:34:11 -0700
Subject: Add SB_LUT4 to box library

---
 techlibs/ice40/cells.box   | 7 +++++++
 techlibs/ice40/cells_box.v | 7 +++++++
 techlibs/ice40/lut.lut     | 2 ++
 3 files changed, 16 insertions(+)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells.box b/techlibs/ice40/cells.box
index e4cfb71e6..d775efa78 100644
--- a/techlibs/ice40/cells.box
+++ b/techlibs/ice40/cells.box
@@ -1,6 +1,13 @@
+# From https://github.com/cliffordwolf/icestorm/blob/81c33a3/icefuzz/timings_hx8k.txt
+
 # NB: Inputs/Outputs must be ordered alphabetically
 
 # Inputs: CI I0 I1
 # Outputs: CO
 SB_CARRY 1 1 3 1
 126 259 231
+
+# Inputs: I0 I1 I2 I3
+# Outputs: O
+SB_LUT4 2 1 4 1
+316 379 400 449
diff --git a/techlibs/ice40/cells_box.v b/techlibs/ice40/cells_box.v
index cca88f9aa..e2a54a42c 100644
--- a/techlibs/ice40/cells_box.v
+++ b/techlibs/ice40/cells_box.v
@@ -3,3 +3,10 @@ module SB_CARRY (output CO, input CI, I0, I1);
 	assign CO = (I0 && I1) || ((I0 || I1) && CI);
 endmodule
 
+(* abc_box_id = 2 *)
+module SB_LUT4 (output O, input I0, I1, I2, I3);
+	parameter [15:0] LUT_INIT = 0;
+	// Indicate this is a black-box
+	assign O = 1'b0;
+endmodule
+
diff --git a/techlibs/ice40/lut.lut b/techlibs/ice40/lut.lut
index 48da89f46..6fa0682da 100644
--- a/techlibs/ice40/lut.lut
+++ b/techlibs/ice40/lut.lut
@@ -1,3 +1,5 @@
+# From https://github.com/cliffordwolf/icestorm/blob/81c33a3/icefuzz/timings_hx8k.txt
+
 1	1	316
 2	1	316 379
 3	1	316 379 400
-- 
cgit v1.2.3


From 17fb6c35229bddc636021def319547e4d8fdf271 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 17 Apr 2019 08:40:50 -0700
Subject: Fix spacing

---
 techlibs/ice40/lut.lut | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/lut.lut b/techlibs/ice40/lut.lut
index 6fa0682da..eef997869 100644
--- a/techlibs/ice40/lut.lut
+++ b/techlibs/ice40/lut.lut
@@ -1,6 +1,6 @@
 # From https://github.com/cliffordwolf/icestorm/blob/81c33a3/icefuzz/timings_hx8k.txt
-
-1	1	316
-2	1	316 379
-3	1	316 379 400
-4	1	316	379	400	449
+#       I3  I2  I1  I0
+1   1   316
+2   1   316 379
+3   1   316 379 400
+4   1   316 379 400 449
-- 
cgit v1.2.3


From a7632ab3326c5247b8152a53808413b259c13253 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 17 Apr 2019 11:10:04 -0700
Subject: Try using an ICE40_CARRY_LUT primitive to avoid ABC issues

---
 techlibs/ice40/arith_map.v    | 37 ++++++++++++++++++++++---------------
 techlibs/ice40/cells.box      | 12 ++++--------
 techlibs/ice40/cells_box.v    | 24 +++++++++++++++---------
 techlibs/ice40/cells_map.v    | 24 ++++++++++++++++++++++++
 techlibs/ice40/cells_sim.v    | 22 ++++++++++++++++++++++
 techlibs/ice40/ice40_opt.cc   | 16 ++++++++++++++--
 techlibs/ice40/synth_ice40.cc |  2 +-
 7 files changed, 102 insertions(+), 35 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/arith_map.v b/techlibs/ice40/arith_map.v
index 4449fdc1b..eefc375dd 100644
--- a/techlibs/ice40/arith_map.v
+++ b/techlibs/ice40/arith_map.v
@@ -44,25 +44,32 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO);
 
 	genvar i;
 	generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
-		SB_CARRY carry (
-			.I0(AA[i]),
-			.I1(BB[i]),
-			.CI(C[i]),
-			.CO(CO[i])
-		);
-		SB_LUT4 #(
-			//         I0: 1010 1010 1010 1010
-			//         I1: 1100 1100 1100 1100
-			//         I2: 1111 0000 1111 0000
-			//         I3: 1111 1111 0000 0000
-			.LUT_INIT(16'b 0110_1001_1001_0110)
-		) adder (
-			.I0(1'b0),
+		ICE40_CARRY_LUT carry_lut (
 			.I1(AA[i]),
 			.I2(BB[i]),
-			.I3(C[i]),
+			.CI(C[i]),
+			.CO(CO[i]),
 			.O(Y[i])
 		);
+//		SB_CARRY carry (
+//			.I0(AA[i]),
+//			.I1(BB[i]),
+//			.CI(C[i]),
+//			.CO(CO[i])
+//		);
+//		SB_LUT4 #(
+//			//         I0: 1010 1010 1010 1010
+//			//         I1: 1100 1100 1100 1100
+//			//         I2: 1111 0000 1111 0000
+//			//         I3: 1111 1111 0000 0000
+//			.LUT_INIT(16'b 0110_1001_1001_0110)
+//		) adder (
+//			.I0(1'b0),
+//			.I1(AA[i]),
+//			.I2(BB[i]),
+//			.I3(C[i]),
+//			.O(Y[i])
+//		);
 	end endgenerate
 
 	assign X = AA ^ BB;
diff --git a/techlibs/ice40/cells.box b/techlibs/ice40/cells.box
index d775efa78..34d1f372e 100644
--- a/techlibs/ice40/cells.box
+++ b/techlibs/ice40/cells.box
@@ -2,12 +2,8 @@
 
 # NB: Inputs/Outputs must be ordered alphabetically
 
-# Inputs: CI I0 I1
-# Outputs: CO
-SB_CARRY 1 1 3 1
+# Inputs: CI I1 I2
+# Outputs: CO O
+ICE40_CARRY_LUT 1 1 3 2
 126 259 231
-
-# Inputs: I0 I1 I2 I3
-# Outputs: O
-SB_LUT4 2 1 4 1
-316 379 400 449
+316 400 379
diff --git a/techlibs/ice40/cells_box.v b/techlibs/ice40/cells_box.v
index e2a54a42c..d0eb8708c 100644
--- a/techlibs/ice40/cells_box.v
+++ b/techlibs/ice40/cells_box.v
@@ -1,12 +1,18 @@
 (* abc_box_id = 1 *)
-module SB_CARRY (output CO, input CI, I0, I1);
-	assign CO = (I0 && I1) || ((I0 || I1) && CI);
-endmodule
+module ICE40_CARRY_LUT (output CO, O, input CI, I1, I2);
+	assign CO = (I1 && I2) || ((I1 || I2) && CI);
 
-(* abc_box_id = 2 *)
-module SB_LUT4 (output O, input I0, I1, I2, I3);
-	parameter [15:0] LUT_INIT = 0;
-	// Indicate this is a black-box
-	assign O = 1'b0;
-endmodule
+	wire I0, I3;
+	assign I0 = 1'b0;
+	assign I3 = CI;
 
+	//                            I0: 1010 1010 1010 1010
+	//                            I1: 1100 1100 1100 1100
+	//                            I2: 1111 0000 1111 0000
+	//                            I3: 1111 1111 0000 0000
+	localparam [15:0] LUT_INIT = 16'b 0110_1001_1001_0110;
+	wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
+	wire [3:0] s2 = I2 ?       s3[ 7:4] :       s3[3:0];
+	wire [1:0] s1 = I1 ?       s2[ 3:2] :       s2[1:0];
+	assign O = I0 ? s1[1] : s1[0];
+endmodule
diff --git a/techlibs/ice40/cells_map.v b/techlibs/ice40/cells_map.v
index d0ddfd02e..d4c611686 100644
--- a/techlibs/ice40/cells_map.v
+++ b/techlibs/ice40/cells_map.v
@@ -57,3 +57,27 @@ module \$lut (A, Y);
   endgenerate
 endmodule
 `endif
+
+`ifndef NO_CARRY
+module ICE40_CARRY_LUT (output CO, O, input CI, I1, I2);
+	SB_CARRY carry (
+		.I0(I1),
+		.I1(I2),
+		.CI(CI),
+		.CO(CO),
+	);
+	SB_LUT4 #(
+		//         I0: 1010 1010 1010 1010
+		//         I1: 1100 1100 1100 1100
+		//         I2: 1111 0000 1111 0000
+		//         I3: 1111 1111 0000 0000
+		.LUT_INIT(16'b 0110_1001_1001_0110)
+	) adder (
+		.I0(1'b0),
+		.I1(I1),
+		.I2(I2),
+		.I3(CI),
+		.O(O)
+	);
+endmodule
+`endif
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 322c1e5c7..b5a739a63 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -1384,3 +1384,25 @@ module SB_MAC16 (
 	assign LCI = (BOTADDSUB_CARRYSELECT == 0) ? 1'b0 : (BOTADDSUB_CARRYSELECT == 1) ? 1'b1 : (BOTADDSUB_CARRYSELECT == 2) ? ACCUMCI : CI;
 	assign O = {Oh, Ol};
 endmodule
+
+module ICE40_CARRY_LUT (input CI, input I1, input I2, output CO, output O);
+	SB_CARRY carry (
+		.I0(I1),
+		.I1(I2),
+		.CI(CI),
+		.CO(CO),
+	);
+	SB_LUT4 #(
+		//         I0: 1010 1010 1010 1010
+		//         I1: 1100 1100 1100 1100
+		//         I2: 1111 0000 1111 0000
+		//         I3: 1111 1111 0000 0000
+		.LUT_INIT(16'b 0110_1001_1001_0110)
+	) adder (
+		.I0(1'b0),
+		.I1(I1),
+		.I2(I2),
+		.I3(CI),
+		.O(O)
+	);
+endmodule
diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index f528607d6..edb293b93 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -47,16 +47,20 @@ static void run_ice40_opts(Module *module)
 			continue;
 		}
 
-		if (cell->type == "\\SB_CARRY")
+		if (cell->type.in("\\SB_CARRY", "\\ICE40_CARRY_LUT"))
 		{
 			SigSpec non_const_inputs, replacement_output;
 			int count_zeros = 0, count_ones = 0;
 
 			SigBit inbit[3] = {
-				get_bit_or_zero(cell->getPort("\\I0")),
 				get_bit_or_zero(cell->getPort("\\I1")),
 				get_bit_or_zero(cell->getPort("\\CI"))
 			};
+			if (cell->type == "\\SB_CARRY")
+				inbit[2] = get_bit_or_zero(cell->getPort("\\I0"));
+			else if (cell->type == "\\ICE40_CARRY_LUT")
+				inbit[2] = get_bit_or_zero(cell->getPort("\\I2"));
+			else log_abort();
 			for (int i = 0; i < 3; i++)
 				if (inbit[i].wire == nullptr) {
 					if (inbit[i] == State::S1)
@@ -79,6 +83,14 @@ static void run_ice40_opts(Module *module)
 				module->design->scratchpad_set_bool("opt.did_something", true);
 				log("Optimized away SB_CARRY cell %s.%s: CO=%s\n",
 						log_id(module), log_id(cell), log_signal(replacement_output));
+
+				if (cell->type == "\\ICE40_CARRY_LUT")
+					module->addLut(NEW_ID,
+						{ RTLIL::S0, cell->getPort("\\I1"), cell->getPort("\\I2"), cell->getPort("\\CI") },
+						cell->getPort("\\O"),
+						RTLIL::Const("0110_1001_1001_0110"),
+						cell->get_src_attribute());
+
 				module->remove(cell);
 			}
 			continue;
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 3faa10b4f..d09a1184c 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -296,7 +296,7 @@ struct SynthIce40Pass : public ScriptPass
 				run("opt_merge");
 				run(stringf("dff2dffe -unmap-mince %d", min_ce_use));
 			}
-			run("techmap -D NO_LUT -map +/ice40/cells_map.v");
+			run("techmap -D NO_LUT -D NO_CARRY -map +/ice40/cells_map.v");
 			run("opt_expr -mux_undef");
 			run("simplemap");
 			run("ice40_ffinit");
-- 
cgit v1.2.3


From c1ebe51a75ef8ce47d6b1406fa87b15bd8f97760 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 17 Apr 2019 11:10:20 -0700
Subject: Revert "Try using an ICE40_CARRY_LUT primitive to avoid ABC issues"

This reverts commit a7632ab3326c5247b8152a53808413b259c13253.
---
 techlibs/ice40/arith_map.v    | 37 +++++++++++++++----------------------
 techlibs/ice40/cells.box      | 12 ++++++++----
 techlibs/ice40/cells_box.v    | 24 +++++++++---------------
 techlibs/ice40/cells_map.v    | 24 ------------------------
 techlibs/ice40/cells_sim.v    | 22 ----------------------
 techlibs/ice40/ice40_opt.cc   | 16 ++--------------
 techlibs/ice40/synth_ice40.cc |  2 +-
 7 files changed, 35 insertions(+), 102 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/arith_map.v b/techlibs/ice40/arith_map.v
index eefc375dd..4449fdc1b 100644
--- a/techlibs/ice40/arith_map.v
+++ b/techlibs/ice40/arith_map.v
@@ -44,32 +44,25 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO);
 
 	genvar i;
 	generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
-		ICE40_CARRY_LUT carry_lut (
+		SB_CARRY carry (
+			.I0(AA[i]),
+			.I1(BB[i]),
+			.CI(C[i]),
+			.CO(CO[i])
+		);
+		SB_LUT4 #(
+			//         I0: 1010 1010 1010 1010
+			//         I1: 1100 1100 1100 1100
+			//         I2: 1111 0000 1111 0000
+			//         I3: 1111 1111 0000 0000
+			.LUT_INIT(16'b 0110_1001_1001_0110)
+		) adder (
+			.I0(1'b0),
 			.I1(AA[i]),
 			.I2(BB[i]),
-			.CI(C[i]),
-			.CO(CO[i]),
+			.I3(C[i]),
 			.O(Y[i])
 		);
-//		SB_CARRY carry (
-//			.I0(AA[i]),
-//			.I1(BB[i]),
-//			.CI(C[i]),
-//			.CO(CO[i])
-//		);
-//		SB_LUT4 #(
-//			//         I0: 1010 1010 1010 1010
-//			//         I1: 1100 1100 1100 1100
-//			//         I2: 1111 0000 1111 0000
-//			//         I3: 1111 1111 0000 0000
-//			.LUT_INIT(16'b 0110_1001_1001_0110)
-//		) adder (
-//			.I0(1'b0),
-//			.I1(AA[i]),
-//			.I2(BB[i]),
-//			.I3(C[i]),
-//			.O(Y[i])
-//		);
 	end endgenerate
 
 	assign X = AA ^ BB;
diff --git a/techlibs/ice40/cells.box b/techlibs/ice40/cells.box
index 34d1f372e..d775efa78 100644
--- a/techlibs/ice40/cells.box
+++ b/techlibs/ice40/cells.box
@@ -2,8 +2,12 @@
 
 # NB: Inputs/Outputs must be ordered alphabetically
 
-# Inputs: CI I1 I2
-# Outputs: CO O
-ICE40_CARRY_LUT 1 1 3 2
+# Inputs: CI I0 I1
+# Outputs: CO
+SB_CARRY 1 1 3 1
 126 259 231
-316 400 379
+
+# Inputs: I0 I1 I2 I3
+# Outputs: O
+SB_LUT4 2 1 4 1
+316 379 400 449
diff --git a/techlibs/ice40/cells_box.v b/techlibs/ice40/cells_box.v
index d0eb8708c..e2a54a42c 100644
--- a/techlibs/ice40/cells_box.v
+++ b/techlibs/ice40/cells_box.v
@@ -1,18 +1,12 @@
 (* abc_box_id = 1 *)
-module ICE40_CARRY_LUT (output CO, O, input CI, I1, I2);
-	assign CO = (I1 && I2) || ((I1 || I2) && CI);
-
-	wire I0, I3;
-	assign I0 = 1'b0;
-	assign I3 = CI;
+module SB_CARRY (output CO, input CI, I0, I1);
+	assign CO = (I0 && I1) || ((I0 || I1) && CI);
+endmodule
 
-	//                            I0: 1010 1010 1010 1010
-	//                            I1: 1100 1100 1100 1100
-	//                            I2: 1111 0000 1111 0000
-	//                            I3: 1111 1111 0000 0000
-	localparam [15:0] LUT_INIT = 16'b 0110_1001_1001_0110;
-	wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
-	wire [3:0] s2 = I2 ?       s3[ 7:4] :       s3[3:0];
-	wire [1:0] s1 = I1 ?       s2[ 3:2] :       s2[1:0];
-	assign O = I0 ? s1[1] : s1[0];
+(* abc_box_id = 2 *)
+module SB_LUT4 (output O, input I0, I1, I2, I3);
+	parameter [15:0] LUT_INIT = 0;
+	// Indicate this is a black-box
+	assign O = 1'b0;
 endmodule
+
diff --git a/techlibs/ice40/cells_map.v b/techlibs/ice40/cells_map.v
index d4c611686..d0ddfd02e 100644
--- a/techlibs/ice40/cells_map.v
+++ b/techlibs/ice40/cells_map.v
@@ -57,27 +57,3 @@ module \$lut (A, Y);
   endgenerate
 endmodule
 `endif
-
-`ifndef NO_CARRY
-module ICE40_CARRY_LUT (output CO, O, input CI, I1, I2);
-	SB_CARRY carry (
-		.I0(I1),
-		.I1(I2),
-		.CI(CI),
-		.CO(CO),
-	);
-	SB_LUT4 #(
-		//         I0: 1010 1010 1010 1010
-		//         I1: 1100 1100 1100 1100
-		//         I2: 1111 0000 1111 0000
-		//         I3: 1111 1111 0000 0000
-		.LUT_INIT(16'b 0110_1001_1001_0110)
-	) adder (
-		.I0(1'b0),
-		.I1(I1),
-		.I2(I2),
-		.I3(CI),
-		.O(O)
-	);
-endmodule
-`endif
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index b5a739a63..322c1e5c7 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -1384,25 +1384,3 @@ module SB_MAC16 (
 	assign LCI = (BOTADDSUB_CARRYSELECT == 0) ? 1'b0 : (BOTADDSUB_CARRYSELECT == 1) ? 1'b1 : (BOTADDSUB_CARRYSELECT == 2) ? ACCUMCI : CI;
 	assign O = {Oh, Ol};
 endmodule
-
-module ICE40_CARRY_LUT (input CI, input I1, input I2, output CO, output O);
-	SB_CARRY carry (
-		.I0(I1),
-		.I1(I2),
-		.CI(CI),
-		.CO(CO),
-	);
-	SB_LUT4 #(
-		//         I0: 1010 1010 1010 1010
-		//         I1: 1100 1100 1100 1100
-		//         I2: 1111 0000 1111 0000
-		//         I3: 1111 1111 0000 0000
-		.LUT_INIT(16'b 0110_1001_1001_0110)
-	) adder (
-		.I0(1'b0),
-		.I1(I1),
-		.I2(I2),
-		.I3(CI),
-		.O(O)
-	);
-endmodule
diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index edb293b93..f528607d6 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -47,20 +47,16 @@ static void run_ice40_opts(Module *module)
 			continue;
 		}
 
-		if (cell->type.in("\\SB_CARRY", "\\ICE40_CARRY_LUT"))
+		if (cell->type == "\\SB_CARRY")
 		{
 			SigSpec non_const_inputs, replacement_output;
 			int count_zeros = 0, count_ones = 0;
 
 			SigBit inbit[3] = {
+				get_bit_or_zero(cell->getPort("\\I0")),
 				get_bit_or_zero(cell->getPort("\\I1")),
 				get_bit_or_zero(cell->getPort("\\CI"))
 			};
-			if (cell->type == "\\SB_CARRY")
-				inbit[2] = get_bit_or_zero(cell->getPort("\\I0"));
-			else if (cell->type == "\\ICE40_CARRY_LUT")
-				inbit[2] = get_bit_or_zero(cell->getPort("\\I2"));
-			else log_abort();
 			for (int i = 0; i < 3; i++)
 				if (inbit[i].wire == nullptr) {
 					if (inbit[i] == State::S1)
@@ -83,14 +79,6 @@ static void run_ice40_opts(Module *module)
 				module->design->scratchpad_set_bool("opt.did_something", true);
 				log("Optimized away SB_CARRY cell %s.%s: CO=%s\n",
 						log_id(module), log_id(cell), log_signal(replacement_output));
-
-				if (cell->type == "\\ICE40_CARRY_LUT")
-					module->addLut(NEW_ID,
-						{ RTLIL::S0, cell->getPort("\\I1"), cell->getPort("\\I2"), cell->getPort("\\CI") },
-						cell->getPort("\\O"),
-						RTLIL::Const("0110_1001_1001_0110"),
-						cell->get_src_attribute());
-
 				module->remove(cell);
 			}
 			continue;
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index d09a1184c..3faa10b4f 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -296,7 +296,7 @@ struct SynthIce40Pass : public ScriptPass
 				run("opt_merge");
 				run(stringf("dff2dffe -unmap-mince %d", min_ce_use));
 			}
-			run("techmap -D NO_LUT -D NO_CARRY -map +/ice40/cells_map.v");
+			run("techmap -D NO_LUT -map +/ice40/cells_map.v");
 			run("opt_expr -mux_undef");
 			run("simplemap");
 			run("ice40_ffinit");
-- 
cgit v1.2.3


From 42c33db22caeffa05bde59d915a4433b756929a1 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 17 Apr 2019 12:15:34 -0700
Subject: Rename to abc.*

---
 techlibs/ice40/abc.box     | 13 +++++++++++++
 techlibs/ice40/abc.lut     |  6 ++++++
 techlibs/ice40/abc.v       | 12 ++++++++++++
 techlibs/ice40/cells.box   | 13 -------------
 techlibs/ice40/cells_box.v | 12 ------------
 techlibs/ice40/lut.lut     |  6 ------
 6 files changed, 31 insertions(+), 31 deletions(-)
 create mode 100644 techlibs/ice40/abc.box
 create mode 100644 techlibs/ice40/abc.lut
 create mode 100644 techlibs/ice40/abc.v
 delete mode 100644 techlibs/ice40/cells.box
 delete mode 100644 techlibs/ice40/cells_box.v
 delete mode 100644 techlibs/ice40/lut.lut

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/abc.box b/techlibs/ice40/abc.box
new file mode 100644
index 000000000..d775efa78
--- /dev/null
+++ b/techlibs/ice40/abc.box
@@ -0,0 +1,13 @@
+# From https://github.com/cliffordwolf/icestorm/blob/81c33a3/icefuzz/timings_hx8k.txt
+
+# NB: Inputs/Outputs must be ordered alphabetically
+
+# Inputs: CI I0 I1
+# Outputs: CO
+SB_CARRY 1 1 3 1
+126 259 231
+
+# Inputs: I0 I1 I2 I3
+# Outputs: O
+SB_LUT4 2 1 4 1
+316 379 400 449
diff --git a/techlibs/ice40/abc.lut b/techlibs/ice40/abc.lut
new file mode 100644
index 000000000..eef997869
--- /dev/null
+++ b/techlibs/ice40/abc.lut
@@ -0,0 +1,6 @@
+# From https://github.com/cliffordwolf/icestorm/blob/81c33a3/icefuzz/timings_hx8k.txt
+#       I3  I2  I1  I0
+1   1   316
+2   1   316 379
+3   1   316 379 400
+4   1   316 379 400 449
diff --git a/techlibs/ice40/abc.v b/techlibs/ice40/abc.v
new file mode 100644
index 000000000..e2a54a42c
--- /dev/null
+++ b/techlibs/ice40/abc.v
@@ -0,0 +1,12 @@
+(* abc_box_id = 1 *)
+module SB_CARRY (output CO, input CI, I0, I1);
+	assign CO = (I0 && I1) || ((I0 || I1) && CI);
+endmodule
+
+(* abc_box_id = 2 *)
+module SB_LUT4 (output O, input I0, I1, I2, I3);
+	parameter [15:0] LUT_INIT = 0;
+	// Indicate this is a black-box
+	assign O = 1'b0;
+endmodule
+
diff --git a/techlibs/ice40/cells.box b/techlibs/ice40/cells.box
deleted file mode 100644
index d775efa78..000000000
--- a/techlibs/ice40/cells.box
+++ /dev/null
@@ -1,13 +0,0 @@
-# From https://github.com/cliffordwolf/icestorm/blob/81c33a3/icefuzz/timings_hx8k.txt
-
-# NB: Inputs/Outputs must be ordered alphabetically
-
-# Inputs: CI I0 I1
-# Outputs: CO
-SB_CARRY 1 1 3 1
-126 259 231
-
-# Inputs: I0 I1 I2 I3
-# Outputs: O
-SB_LUT4 2 1 4 1
-316 379 400 449
diff --git a/techlibs/ice40/cells_box.v b/techlibs/ice40/cells_box.v
deleted file mode 100644
index e2a54a42c..000000000
--- a/techlibs/ice40/cells_box.v
+++ /dev/null
@@ -1,12 +0,0 @@
-(* abc_box_id = 1 *)
-module SB_CARRY (output CO, input CI, I0, I1);
-	assign CO = (I0 && I1) || ((I0 || I1) && CI);
-endmodule
-
-(* abc_box_id = 2 *)
-module SB_LUT4 (output O, input I0, I1, I2, I3);
-	parameter [15:0] LUT_INIT = 0;
-	// Indicate this is a black-box
-	assign O = 1'b0;
-endmodule
-
diff --git a/techlibs/ice40/lut.lut b/techlibs/ice40/lut.lut
deleted file mode 100644
index eef997869..000000000
--- a/techlibs/ice40/lut.lut
+++ /dev/null
@@ -1,6 +0,0 @@
-# From https://github.com/cliffordwolf/icestorm/blob/81c33a3/icefuzz/timings_hx8k.txt
-#       I3  I2  I1  I0
-1   1   316
-2   1   316 379
-3   1   316 379 400
-4   1   316 379 400 449
-- 
cgit v1.2.3


From 4fb9ccfcd81db6d2e574bea3d142b714126d1123 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 17 Apr 2019 12:22:03 -0700
Subject: synth_ice40 to use renamed files

---
 techlibs/ice40/synth_ice40.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 3faa10b4f..91cd063a2 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -317,9 +317,9 @@ struct SynthIce40Pass : public ScriptPass
 			}
 			if (!noabc) {
 				if (abc == "abc9") {
-					run("read_verilog +/ice40/cells_box.v");
+					run("read_verilog +/ice40/abc.v");
 					run("techmap -map +/techmap.v A:abc_box_id");
-					run(abc + " -dress -lut +/ice40/lut.lut -box +/ice40/cells.box", "(skip if -noabc)");
+					run(abc + " -dress -lut +/ice40/abc.lut -box +/ice40/abc.box", "(skip if -noabc)");
 					run("blackbox A:abc_box_id");
 				}
 				else
-- 
cgit v1.2.3


From 1eade0667102b50afa927f64e22968dd28365167 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 17 Apr 2019 12:27:02 -0700
Subject: Also update Makefile.inc

---
 techlibs/ice40/Makefile.inc | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/Makefile.inc b/techlibs/ice40/Makefile.inc
index cd992bb24..abfede011 100644
--- a/techlibs/ice40/Makefile.inc
+++ b/techlibs/ice40/Makefile.inc
@@ -28,9 +28,9 @@ $(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_sim.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/latches_map.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams.txt))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams_map.v))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/cells.box))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_box.v))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/lut.lut))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc.box))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc.v))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc.lut))
 
 $(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init1.vh))
 $(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init2.vh))
-- 
cgit v1.2.3


From 58847df1b94d2caaa1fe959acb04425397f3567f Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 17 Apr 2019 12:27:45 -0700
Subject: Mark seq output ports with "abc_flop_q" attr

---
 techlibs/ice40/cells_sim.v | 48 +++++++++++++++++++++++-----------------------
 1 file changed, 24 insertions(+), 24 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 322c1e5c7..cf7b9d252 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -132,18 +132,18 @@ endmodule
 
 // Positive Edge SiliconBlue FF Cells
 
-module SB_DFF (output `SB_DFF_REG, input C, D);
+module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, D);
 	always @(posedge C)
 		Q <= D;
 endmodule
 
-module SB_DFFE (output `SB_DFF_REG, input C, E, D);
+module SB_DFFE ((* abc_flop_q *) output `SB_DFF_REG, input C, E, D);
 	always @(posedge C)
 		if (E)
 			Q <= D;
 endmodule
 
-module SB_DFFSR (output `SB_DFF_REG, input C, R, D);
+module SB_DFFSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
 	always @(posedge C)
 		if (R)
 			Q <= 0;
@@ -151,7 +151,7 @@ module SB_DFFSR (output `SB_DFF_REG, input C, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFR (output `SB_DFF_REG, input C, R, D);
+module SB_DFFR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
 	always @(posedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -159,7 +159,7 @@ module SB_DFFR (output `SB_DFF_REG, input C, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFSS (output `SB_DFF_REG, input C, S, D);
+module SB_DFFSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
 	always @(posedge C)
 		if (S)
 			Q <= 1;
@@ -167,7 +167,7 @@ module SB_DFFSS (output `SB_DFF_REG, input C, S, D);
 			Q <= D;
 endmodule
 
-module SB_DFFS (output `SB_DFF_REG, input C, S, D);
+module SB_DFFS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
 	always @(posedge C, posedge S)
 		if (S)
 			Q <= 1;
@@ -175,7 +175,7 @@ module SB_DFFS (output `SB_DFF_REG, input C, S, D);
 			Q <= D;
 endmodule
 
-module SB_DFFESR (output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
 	always @(posedge C)
 		if (E) begin
 			if (R)
@@ -185,7 +185,7 @@ module SB_DFFESR (output `SB_DFF_REG, input C, E, R, D);
 		end
 endmodule
 
-module SB_DFFER (output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
 	always @(posedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -193,7 +193,7 @@ module SB_DFFER (output `SB_DFF_REG, input C, E, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFESS (output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
 	always @(posedge C)
 		if (E) begin
 			if (S)
@@ -203,7 +203,7 @@ module SB_DFFESS (output `SB_DFF_REG, input C, E, S, D);
 		end
 endmodule
 
-module SB_DFFES (output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFES ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
 	always @(posedge C, posedge S)
 		if (S)
 			Q <= 1;
@@ -213,18 +213,18 @@ endmodule
 
 // Negative Edge SiliconBlue FF Cells
 
-module SB_DFFN (output `SB_DFF_REG, input C, D);
+module SB_DFFN ((* abc_flop_q *) output `SB_DFF_REG, input C, D);
 	always @(negedge C)
 		Q <= D;
 endmodule
 
-module SB_DFFNE (output `SB_DFF_REG, input C, E, D);
+module SB_DFFNE ((* abc_flop_q *) output `SB_DFF_REG, input C, E, D);
 	always @(negedge C)
 		if (E)
 			Q <= D;
 endmodule
 
-module SB_DFFNSR (output `SB_DFF_REG, input C, R, D);
+module SB_DFFNSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
 	always @(negedge C)
 		if (R)
 			Q <= 0;
@@ -232,7 +232,7 @@ module SB_DFFNSR (output `SB_DFF_REG, input C, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNR (output `SB_DFF_REG, input C, R, D);
+module SB_DFFNR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
 	always @(negedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -240,7 +240,7 @@ module SB_DFFNR (output `SB_DFF_REG, input C, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNSS (output `SB_DFF_REG, input C, S, D);
+module SB_DFFNSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
 	always @(negedge C)
 		if (S)
 			Q <= 1;
@@ -248,7 +248,7 @@ module SB_DFFNSS (output `SB_DFF_REG, input C, S, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNS (output `SB_DFF_REG, input C, S, D);
+module SB_DFFNS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
 	always @(negedge C, posedge S)
 		if (S)
 			Q <= 1;
@@ -256,7 +256,7 @@ module SB_DFFNS (output `SB_DFF_REG, input C, S, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNESR (output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFNESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
 	always @(negedge C)
 		if (E) begin
 			if (R)
@@ -266,7 +266,7 @@ module SB_DFFNESR (output `SB_DFF_REG, input C, E, R, D);
 		end
 endmodule
 
-module SB_DFFNER (output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFNER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
 	always @(negedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -274,7 +274,7 @@ module SB_DFFNER (output `SB_DFF_REG, input C, E, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNESS (output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFNESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
 	always @(negedge C)
 		if (E) begin
 			if (S)
@@ -284,7 +284,7 @@ module SB_DFFNESS (output `SB_DFF_REG, input C, E, S, D);
 		end
 endmodule
 
-module SB_DFFNES (output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFNES ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
 	always @(negedge C, posedge S)
 		if (S)
 			Q <= 1;
@@ -295,7 +295,7 @@ endmodule
 // SiliconBlue RAM Cells
 
 module SB_RAM40_4K (
-	output [15:0] RDATA,
+	(* abc_flop_q *) output [15:0] RDATA,
 	input         RCLK, RCLKE, RE,
 	input  [10:0] RADDR,
 	input         WCLK, WCLKE, WE,
@@ -463,7 +463,7 @@ module SB_RAM40_4K (
 endmodule
 
 module SB_RAM40_4KNR (
-	output [15:0] RDATA,
+	(* abc_flop_q *) output [15:0] RDATA,
 	input         RCLKN, RCLKE, RE,
 	input  [10:0] RADDR,
 	input         WCLK, WCLKE, WE,
@@ -528,7 +528,7 @@ module SB_RAM40_4KNR (
 endmodule
 
 module SB_RAM40_4KNW (
-	output [15:0] RDATA,
+	(* abc_flop_q *) output [15:0] RDATA,
 	input         RCLK, RCLKE, RE,
 	input  [10:0] RADDR,
 	input         WCLKN, WCLKE, WE,
@@ -593,7 +593,7 @@ module SB_RAM40_4KNW (
 endmodule
 
 module SB_RAM40_4KNRNW (
-	output [15:0] RDATA,
+	(* abc_flop_q *) output [15:0] RDATA,
 	input         RCLKN, RCLKE, RE,
 	input  [10:0] RADDR,
 	input         WCLKN, WCLKE, WE,
-- 
cgit v1.2.3


From 437fec0d88b4a2ad172edf0d1a861a38845f3b1d Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 17 Apr 2019 13:01:17 -0700
Subject: Map to SB_LUT4 from fastest input first

---
 techlibs/ice40/cells_map.v | 18 +++++++++++-------
 1 file changed, 11 insertions(+), 7 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_map.v b/techlibs/ice40/cells_map.v
index d0ddfd02e..287c48b11 100644
--- a/techlibs/ice40/cells_map.v
+++ b/techlibs/ice40/cells_map.v
@@ -37,20 +37,24 @@ module \$lut (A, Y);
 
   generate
     if (WIDTH == 1) begin
-      SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
-        .I0(A[0]), .I1(1'b0), .I2(1'b0), .I3(1'b0));
+      localparam [15:0] INIT = {{8{LUT[1]}}, {8{LUT[0]}}};
+      SB_LUT4 #(.LUT_INIT(INIT)) _TECHMAP_REPLACE_ (.O(Y),
+        .I0(1'b0), .I1(1'b0), .I2(1'b0), .I3(A[0]));
     end else
     if (WIDTH == 2) begin
-      SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
-        .I0(A[0]), .I1(A[1]), .I2(1'b0), .I3(1'b0));
+      localparam [15:0] INIT = {{4{LUT[3]}}, {4{LUT[1]}}, {4{LUT[2]}}, {4{LUT[0]}}};
+      SB_LUT4 #(.LUT_INIT(INIT)) _TECHMAP_REPLACE_ (.O(Y),
+        .I0(1'b0), .I1(1'b0), .I2(A[1]), .I3(A[0]));
     end else
     if (WIDTH == 3) begin
-      SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
-        .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(1'b0));
+      localparam [15:0] INIT = {{2{LUT[7]}}, {2{LUT[3]}}, {2{LUT[5]}}, {2{LUT[1]}}, {2{LUT[6]}}, {2{LUT[2]}}, {2{LUT[4]}}, {2{LUT[0]}}};
+      SB_LUT4 #(.LUT_INIT(INIT)) _TECHMAP_REPLACE_ (.O(Y),
+        .I0(1'b0), .I1(A[2]), .I2(A[1]), .I3(A[0]));
     end else
     if (WIDTH == 4) begin
+      localparam [15:0] INIT = {LUT[15], LUT[7], LUT[11], LUT[3], LUT[13], LUT[5], LUT[9], LUT[1], LUT[14], LUT[6], LUT[10], LUT[2], LUT[12], LUT[4], LUT[8], LUT[0]};
       SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
-        .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]));
+        .I0(A[3]), .I1(A[2]), .I2(A[1]), .I3(A[0]));
     end else begin
       wire _TECHMAP_FAIL_ = 1;
     end
-- 
cgit v1.2.3


From 671cca59a9f63f9fb7102727eb4dee1b18fe3ef6 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 17 Apr 2019 14:44:08 -0700
Subject: Missing abc_flop_q attribute on SPRAM

---
 techlibs/ice40/cells_sim.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index cf7b9d252..70cd51ed1 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -887,7 +887,7 @@ module SB_SPRAM256KA (
 	input [15:0] DATAIN,
 	input [3:0] MASKWREN,
 	input WREN, CHIPSELECT, CLOCK, STANDBY, SLEEP, POWEROFF,
-	output reg [15:0] DATAOUT
+	(* abc_flop_q *) output reg [15:0] DATAOUT
 );
 `ifndef BLACKBOX
 `ifndef EQUIV
-- 
cgit v1.2.3


From 6f3e5297dbf1a0b28e6bfa51990f957939d722d7 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 17 Apr 2019 15:04:46 -0700
Subject: Add "-device" argument to synth_ice40

---
 techlibs/ice40/Makefile.inc   |  6 ++++--
 techlibs/ice40/abc.box        | 13 -------------
 techlibs/ice40/abc.lut        |  6 ------
 techlibs/ice40/hx8k.box       | 13 +++++++++++++
 techlibs/ice40/hx8k.lut       |  6 ++++++
 techlibs/ice40/synth_ice40.cc | 15 +++++++++++++--
 6 files changed, 36 insertions(+), 23 deletions(-)
 delete mode 100644 techlibs/ice40/abc.box
 delete mode 100644 techlibs/ice40/abc.lut
 create mode 100644 techlibs/ice40/hx8k.box
 create mode 100644 techlibs/ice40/hx8k.lut

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/Makefile.inc b/techlibs/ice40/Makefile.inc
index abfede011..efcea6e98 100644
--- a/techlibs/ice40/Makefile.inc
+++ b/techlibs/ice40/Makefile.inc
@@ -28,9 +28,11 @@ $(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_sim.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/latches_map.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams.txt))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams_map.v))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc.box))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/abc.v))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc.lut))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/hx8k.box))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/hx8k.lut))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/up5k.box))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/up5k.lut))
 
 $(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init1.vh))
 $(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init2.vh))
diff --git a/techlibs/ice40/abc.box b/techlibs/ice40/abc.box
deleted file mode 100644
index d775efa78..000000000
--- a/techlibs/ice40/abc.box
+++ /dev/null
@@ -1,13 +0,0 @@
-# From https://github.com/cliffordwolf/icestorm/blob/81c33a3/icefuzz/timings_hx8k.txt
-
-# NB: Inputs/Outputs must be ordered alphabetically
-
-# Inputs: CI I0 I1
-# Outputs: CO
-SB_CARRY 1 1 3 1
-126 259 231
-
-# Inputs: I0 I1 I2 I3
-# Outputs: O
-SB_LUT4 2 1 4 1
-316 379 400 449
diff --git a/techlibs/ice40/abc.lut b/techlibs/ice40/abc.lut
deleted file mode 100644
index eef997869..000000000
--- a/techlibs/ice40/abc.lut
+++ /dev/null
@@ -1,6 +0,0 @@
-# From https://github.com/cliffordwolf/icestorm/blob/81c33a3/icefuzz/timings_hx8k.txt
-#       I3  I2  I1  I0
-1   1   316
-2   1   316 379
-3   1   316 379 400
-4   1   316 379 400 449
diff --git a/techlibs/ice40/hx8k.box b/techlibs/ice40/hx8k.box
new file mode 100644
index 000000000..c31f7bf39
--- /dev/null
+++ b/techlibs/ice40/hx8k.box
@@ -0,0 +1,13 @@
+# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_hx8k.txt
+
+# NB: Inputs/Outputs must be ordered alphabetically
+
+# Inputs: CI I0 I1
+# Outputs: CO
+SB_CARRY 1 1 3 1
+126 259 231
+
+# Inputs: I0 I1 I2 I3
+# Outputs: O
+SB_LUT4 2 1 4 1
+449 400 379 316
diff --git a/techlibs/ice40/hx8k.lut b/techlibs/ice40/hx8k.lut
new file mode 100644
index 000000000..3b3bb11e2
--- /dev/null
+++ b/techlibs/ice40/hx8k.lut
@@ -0,0 +1,6 @@
+# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_hx8k.txt
+#       I3  I2  I1  I0
+1   1   316
+2   1   316 379
+3   1   316 379 400
+4   1   316 379 400 449
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 91cd063a2..2981875eb 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -37,6 +37,10 @@ struct SynthIce40Pass : public ScriptPass
 		log("\n");
 		log("This command runs synthesis for iCE40 FPGAs.\n");
 		log("\n");
+		log("    -device < hx1k | lp384 | lp1k | lp8k | hx8k | u4k | up5k >\n");
+		log("        optimise the synthesis netlist for the specified device.\n");
+		log("        HX1K is the default target if no device argument specified.\n");
+		log("\n");
 		log("    -top <module>\n");
 		log("        use the specified module as top module\n");
 		log("\n");
@@ -102,7 +106,7 @@ struct SynthIce40Pass : public ScriptPass
 	}
 
 
-	string top_opt, blif_file, edif_file, json_file, abc;
+	string top_opt, blif_file, edif_file, json_file, abc, device_opt;
 	bool nocarry, nodffe, nobram, dsp, flatten, retime, relut, noabc, abc2, vpr;
 	int min_ce_use;
 
@@ -124,6 +128,7 @@ struct SynthIce40Pass : public ScriptPass
 		abc2 = false;
 		vpr = false;
 		abc = "abc";
+		device_opt = "hx1k";
 	}
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@@ -210,12 +215,18 @@ struct SynthIce40Pass : public ScriptPass
 				abc = "abc9";
 				continue;
 			}
+			if (args[argidx] == "-device" && argidx+1 < args.size()) {
+				device_opt = args[++argidx];
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
 
 		if (!design->full_selection())
 			log_cmd_error("This command only operates on fully selected designs!\n");
+		if (device_opt != "hx1k" && device_opt !="lp384" && device_opt != "lp1k" && device_opt !="lp8k" && device_opt !="hx8k" && device_opt != "u4k" && device_opt != "up5k")
+			log_cmd_error("Invalid or no family specified: '%s'\n", device_opt.c_str());
 
 		log_header(design, "Executing SYNTH_ICE40 pass.\n");
 		log_push();
@@ -319,7 +330,7 @@ struct SynthIce40Pass : public ScriptPass
 				if (abc == "abc9") {
 					run("read_verilog +/ice40/abc.v");
 					run("techmap -map +/techmap.v A:abc_box_id");
-					run(abc + " -dress -lut +/ice40/abc.lut -box +/ice40/abc.box", "(skip if -noabc)");
+					run(abc + stringf(" -dress -lut +/ice40/%s.lut -box +/ice40/%s.box", device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
 					run("blackbox A:abc_box_id");
 				}
 				else
-- 
cgit v1.2.3


From 3105a8a6531545efefe228fb4fc4b7b09ae127e8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 17 Apr 2019 15:07:44 -0700
Subject: Update error message

---
 techlibs/ice40/synth_ice40.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 2981875eb..62589ad87 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -226,7 +226,7 @@ struct SynthIce40Pass : public ScriptPass
 		if (!design->full_selection())
 			log_cmd_error("This command only operates on fully selected designs!\n");
 		if (device_opt != "hx1k" && device_opt !="lp384" && device_opt != "lp1k" && device_opt !="lp8k" && device_opt !="hx8k" && device_opt != "u4k" && device_opt != "up5k")
-			log_cmd_error("Invalid or no family specified: '%s'\n", device_opt.c_str());
+			log_cmd_error("Invalid or no device specified: '%s'\n", device_opt.c_str());
 
 		log_header(design, "Executing SYNTH_ICE40 pass.\n");
 		log_push();
-- 
cgit v1.2.3


From 5c0853fc518bbbad77b819a5c916e438d0e33cb0 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 17 Apr 2019 15:10:39 -0700
Subject: Add up5k timings

---
 techlibs/ice40/up5k.box | 13 +++++++++++++
 techlibs/ice40/up5k.lut |  6 ++++++
 2 files changed, 19 insertions(+)
 create mode 100644 techlibs/ice40/up5k.box
 create mode 100644 techlibs/ice40/up5k.lut

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/up5k.box b/techlibs/ice40/up5k.box
new file mode 100644
index 000000000..94df1df8f
--- /dev/null
+++ b/techlibs/ice40/up5k.box
@@ -0,0 +1,13 @@
+# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_up5k.txt
+
+# NB: Inputs/Outputs must be ordered alphabetically
+
+# Inputs: CI I0 I1
+# Outputs: CO
+SB_CARRY 1 1 3 1
+278 675 609
+
+# Inputs: I0 I1 I2 I3
+# Outputs: O
+SB_LUT4 2 1 4 1
+1285 1231 1205 874
diff --git a/techlibs/ice40/up5k.lut b/techlibs/ice40/up5k.lut
new file mode 100644
index 000000000..1e4fcadb6
--- /dev/null
+++ b/techlibs/ice40/up5k.lut
@@ -0,0 +1,6 @@
+# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_up5k.txt
+#       I3  I2  I1  I0
+1   1   874
+2   1   874 1205
+3   1   874 1205 1231
+4   1   874 1205 1231 1285
-- 
cgit v1.2.3


From c795e14d25b42ae28bd4b8f7e259e969442437b3 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 17 Apr 2019 15:19:02 -0700
Subject: Reduce to three devices: hx, lp, u

---
 techlibs/ice40/hx.box         | 13 +++++++++++++
 techlibs/ice40/hx.lut         |  6 ++++++
 techlibs/ice40/hx8k.box       | 13 -------------
 techlibs/ice40/hx8k.lut       |  6 ------
 techlibs/ice40/lp.box         | 13 +++++++++++++
 techlibs/ice40/lp.lut         |  6 ++++++
 techlibs/ice40/synth_ice40.cc |  8 ++++----
 techlibs/ice40/u.box          | 13 +++++++++++++
 techlibs/ice40/u.lut          |  6 ++++++
 techlibs/ice40/up5k.box       | 13 -------------
 techlibs/ice40/up5k.lut       |  6 ------
 11 files changed, 61 insertions(+), 42 deletions(-)
 create mode 100644 techlibs/ice40/hx.box
 create mode 100644 techlibs/ice40/hx.lut
 delete mode 100644 techlibs/ice40/hx8k.box
 delete mode 100644 techlibs/ice40/hx8k.lut
 create mode 100644 techlibs/ice40/lp.box
 create mode 100644 techlibs/ice40/lp.lut
 create mode 100644 techlibs/ice40/u.box
 create mode 100644 techlibs/ice40/u.lut
 delete mode 100644 techlibs/ice40/up5k.box
 delete mode 100644 techlibs/ice40/up5k.lut

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/hx.box b/techlibs/ice40/hx.box
new file mode 100644
index 000000000..c31f7bf39
--- /dev/null
+++ b/techlibs/ice40/hx.box
@@ -0,0 +1,13 @@
+# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_hx8k.txt
+
+# NB: Inputs/Outputs must be ordered alphabetically
+
+# Inputs: CI I0 I1
+# Outputs: CO
+SB_CARRY 1 1 3 1
+126 259 231
+
+# Inputs: I0 I1 I2 I3
+# Outputs: O
+SB_LUT4 2 1 4 1
+449 400 379 316
diff --git a/techlibs/ice40/hx.lut b/techlibs/ice40/hx.lut
new file mode 100644
index 000000000..3b3bb11e2
--- /dev/null
+++ b/techlibs/ice40/hx.lut
@@ -0,0 +1,6 @@
+# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_hx8k.txt
+#       I3  I2  I1  I0
+1   1   316
+2   1   316 379
+3   1   316 379 400
+4   1   316 379 400 449
diff --git a/techlibs/ice40/hx8k.box b/techlibs/ice40/hx8k.box
deleted file mode 100644
index c31f7bf39..000000000
--- a/techlibs/ice40/hx8k.box
+++ /dev/null
@@ -1,13 +0,0 @@
-# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_hx8k.txt
-
-# NB: Inputs/Outputs must be ordered alphabetically
-
-# Inputs: CI I0 I1
-# Outputs: CO
-SB_CARRY 1 1 3 1
-126 259 231
-
-# Inputs: I0 I1 I2 I3
-# Outputs: O
-SB_LUT4 2 1 4 1
-449 400 379 316
diff --git a/techlibs/ice40/hx8k.lut b/techlibs/ice40/hx8k.lut
deleted file mode 100644
index 3b3bb11e2..000000000
--- a/techlibs/ice40/hx8k.lut
+++ /dev/null
@@ -1,6 +0,0 @@
-# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_hx8k.txt
-#       I3  I2  I1  I0
-1   1   316
-2   1   316 379
-3   1   316 379 400
-4   1   316 379 400 449
diff --git a/techlibs/ice40/lp.box b/techlibs/ice40/lp.box
new file mode 100644
index 000000000..7eb8e86e0
--- /dev/null
+++ b/techlibs/ice40/lp.box
@@ -0,0 +1,13 @@
+# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_lp8k.txt
+
+# NB: Inputs/Outputs must be ordered alphabetically
+
+# Inputs: CI I0 I1
+# Outputs: CO
+SB_CARRY 1 1 3 1
+186 675 609
+
+# Inputs: I0 I1 I2 I3
+# Outputs: O
+SB_LUT4 2 1 4 1
+465 558 589 661
diff --git a/techlibs/ice40/lp.lut b/techlibs/ice40/lp.lut
new file mode 100644
index 000000000..e72f760a2
--- /dev/null
+++ b/techlibs/ice40/lp.lut
@@ -0,0 +1,6 @@
+# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_lp8k.txt
+#       I3  I2  I1  I0
+1   1   465
+2   1   465 558
+3   1   465 558 589
+4   1   465 558 589 661
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 62589ad87..7c95588e4 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -37,9 +37,9 @@ struct SynthIce40Pass : public ScriptPass
 		log("\n");
 		log("This command runs synthesis for iCE40 FPGAs.\n");
 		log("\n");
-		log("    -device < hx1k | lp384 | lp1k | lp8k | hx8k | u4k | up5k >\n");
+		log("    -device < hx | lp | u >\n");
 		log("        optimise the synthesis netlist for the specified device.\n");
-		log("        HX1K is the default target if no device argument specified.\n");
+		log("        HX is the default target if no device argument specified.\n");
 		log("\n");
 		log("    -top <module>\n");
 		log("        use the specified module as top module\n");
@@ -128,7 +128,7 @@ struct SynthIce40Pass : public ScriptPass
 		abc2 = false;
 		vpr = false;
 		abc = "abc";
-		device_opt = "hx1k";
+		device_opt = "hx";
 	}
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@@ -225,7 +225,7 @@ struct SynthIce40Pass : public ScriptPass
 
 		if (!design->full_selection())
 			log_cmd_error("This command only operates on fully selected designs!\n");
-		if (device_opt != "hx1k" && device_opt !="lp384" && device_opt != "lp1k" && device_opt !="lp8k" && device_opt !="hx8k" && device_opt != "u4k" && device_opt != "up5k")
+		if (device_opt != "hx" && device_opt != "lp" && device_opt !="u")
 			log_cmd_error("Invalid or no device specified: '%s'\n", device_opt.c_str());
 
 		log_header(design, "Executing SYNTH_ICE40 pass.\n");
diff --git a/techlibs/ice40/u.box b/techlibs/ice40/u.box
new file mode 100644
index 000000000..94df1df8f
--- /dev/null
+++ b/techlibs/ice40/u.box
@@ -0,0 +1,13 @@
+# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_up5k.txt
+
+# NB: Inputs/Outputs must be ordered alphabetically
+
+# Inputs: CI I0 I1
+# Outputs: CO
+SB_CARRY 1 1 3 1
+278 675 609
+
+# Inputs: I0 I1 I2 I3
+# Outputs: O
+SB_LUT4 2 1 4 1
+1285 1231 1205 874
diff --git a/techlibs/ice40/u.lut b/techlibs/ice40/u.lut
new file mode 100644
index 000000000..1e4fcadb6
--- /dev/null
+++ b/techlibs/ice40/u.lut
@@ -0,0 +1,6 @@
+# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_up5k.txt
+#       I3  I2  I1  I0
+1   1   874
+2   1   874 1205
+3   1   874 1205 1231
+4   1   874 1205 1231 1285
diff --git a/techlibs/ice40/up5k.box b/techlibs/ice40/up5k.box
deleted file mode 100644
index 94df1df8f..000000000
--- a/techlibs/ice40/up5k.box
+++ /dev/null
@@ -1,13 +0,0 @@
-# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_up5k.txt
-
-# NB: Inputs/Outputs must be ordered alphabetically
-
-# Inputs: CI I0 I1
-# Outputs: CO
-SB_CARRY 1 1 3 1
-278 675 609
-
-# Inputs: I0 I1 I2 I3
-# Outputs: O
-SB_LUT4 2 1 4 1
-1285 1231 1205 874
diff --git a/techlibs/ice40/up5k.lut b/techlibs/ice40/up5k.lut
deleted file mode 100644
index 1e4fcadb6..000000000
--- a/techlibs/ice40/up5k.lut
+++ /dev/null
@@ -1,6 +0,0 @@
-# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_up5k.txt
-#       I3  I2  I1  I0
-1   1   874
-2   1   874 1205
-3   1   874 1205 1231
-4   1   874 1205 1231 1285
-- 
cgit v1.2.3


From 8fd455c91070e1e4cf05cbece79999fef04bb9b9 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 17 Apr 2019 15:19:48 -0700
Subject: Update Makefile.inc too

---
 techlibs/ice40/Makefile.inc | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/Makefile.inc b/techlibs/ice40/Makefile.inc
index efcea6e98..cb2121a11 100644
--- a/techlibs/ice40/Makefile.inc
+++ b/techlibs/ice40/Makefile.inc
@@ -29,10 +29,12 @@ $(eval $(call add_share_file,share/ice40,techlibs/ice40/latches_map.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams.txt))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams_map.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/abc.v))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/hx8k.box))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/hx8k.lut))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/up5k.box))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/up5k.lut))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/hx.box))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/hx.lut))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/lp.box))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/lp.lut))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/u.box))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/u.lut))
 
 $(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init1.vh))
 $(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init2.vh))
-- 
cgit v1.2.3


From ed5e75ed7d5a4515e23a496570c7eb03f48742b0 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 18 Apr 2019 09:02:58 -0700
Subject: Rename to abc_*.{box,lut}

---
 techlibs/ice40/abc_hx.box  | 13 +++++++++++++
 techlibs/ice40/abc_lp.box  | 13 +++++++++++++
 techlibs/ice40/abc_lp.lut  |  6 ++++++
 techlibs/ice40/abc_lut.box |  6 ++++++
 techlibs/ice40/abc_u.box   | 13 +++++++++++++
 techlibs/ice40/abc_u.lut   |  6 ++++++
 techlibs/ice40/hx.box      | 13 -------------
 techlibs/ice40/hx.lut      |  6 ------
 techlibs/ice40/lp.box      | 13 -------------
 techlibs/ice40/lp.lut      |  6 ------
 techlibs/ice40/u.box       | 13 -------------
 techlibs/ice40/u.lut       |  6 ------
 12 files changed, 57 insertions(+), 57 deletions(-)
 create mode 100644 techlibs/ice40/abc_hx.box
 create mode 100644 techlibs/ice40/abc_lp.box
 create mode 100644 techlibs/ice40/abc_lp.lut
 create mode 100644 techlibs/ice40/abc_lut.box
 create mode 100644 techlibs/ice40/abc_u.box
 create mode 100644 techlibs/ice40/abc_u.lut
 delete mode 100644 techlibs/ice40/hx.box
 delete mode 100644 techlibs/ice40/hx.lut
 delete mode 100644 techlibs/ice40/lp.box
 delete mode 100644 techlibs/ice40/lp.lut
 delete mode 100644 techlibs/ice40/u.box
 delete mode 100644 techlibs/ice40/u.lut

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/abc_hx.box b/techlibs/ice40/abc_hx.box
new file mode 100644
index 000000000..c31f7bf39
--- /dev/null
+++ b/techlibs/ice40/abc_hx.box
@@ -0,0 +1,13 @@
+# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_hx8k.txt
+
+# NB: Inputs/Outputs must be ordered alphabetically
+
+# Inputs: CI I0 I1
+# Outputs: CO
+SB_CARRY 1 1 3 1
+126 259 231
+
+# Inputs: I0 I1 I2 I3
+# Outputs: O
+SB_LUT4 2 1 4 1
+449 400 379 316
diff --git a/techlibs/ice40/abc_lp.box b/techlibs/ice40/abc_lp.box
new file mode 100644
index 000000000..7eb8e86e0
--- /dev/null
+++ b/techlibs/ice40/abc_lp.box
@@ -0,0 +1,13 @@
+# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_lp8k.txt
+
+# NB: Inputs/Outputs must be ordered alphabetically
+
+# Inputs: CI I0 I1
+# Outputs: CO
+SB_CARRY 1 1 3 1
+186 675 609
+
+# Inputs: I0 I1 I2 I3
+# Outputs: O
+SB_LUT4 2 1 4 1
+465 558 589 661
diff --git a/techlibs/ice40/abc_lp.lut b/techlibs/ice40/abc_lp.lut
new file mode 100644
index 000000000..e72f760a2
--- /dev/null
+++ b/techlibs/ice40/abc_lp.lut
@@ -0,0 +1,6 @@
+# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_lp8k.txt
+#       I3  I2  I1  I0
+1   1   465
+2   1   465 558
+3   1   465 558 589
+4   1   465 558 589 661
diff --git a/techlibs/ice40/abc_lut.box b/techlibs/ice40/abc_lut.box
new file mode 100644
index 000000000..3b3bb11e2
--- /dev/null
+++ b/techlibs/ice40/abc_lut.box
@@ -0,0 +1,6 @@
+# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_hx8k.txt
+#       I3  I2  I1  I0
+1   1   316
+2   1   316 379
+3   1   316 379 400
+4   1   316 379 400 449
diff --git a/techlibs/ice40/abc_u.box b/techlibs/ice40/abc_u.box
new file mode 100644
index 000000000..94df1df8f
--- /dev/null
+++ b/techlibs/ice40/abc_u.box
@@ -0,0 +1,13 @@
+# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_up5k.txt
+
+# NB: Inputs/Outputs must be ordered alphabetically
+
+# Inputs: CI I0 I1
+# Outputs: CO
+SB_CARRY 1 1 3 1
+278 675 609
+
+# Inputs: I0 I1 I2 I3
+# Outputs: O
+SB_LUT4 2 1 4 1
+1285 1231 1205 874
diff --git a/techlibs/ice40/abc_u.lut b/techlibs/ice40/abc_u.lut
new file mode 100644
index 000000000..1e4fcadb6
--- /dev/null
+++ b/techlibs/ice40/abc_u.lut
@@ -0,0 +1,6 @@
+# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_up5k.txt
+#       I3  I2  I1  I0
+1   1   874
+2   1   874 1205
+3   1   874 1205 1231
+4   1   874 1205 1231 1285
diff --git a/techlibs/ice40/hx.box b/techlibs/ice40/hx.box
deleted file mode 100644
index c31f7bf39..000000000
--- a/techlibs/ice40/hx.box
+++ /dev/null
@@ -1,13 +0,0 @@
-# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_hx8k.txt
-
-# NB: Inputs/Outputs must be ordered alphabetically
-
-# Inputs: CI I0 I1
-# Outputs: CO
-SB_CARRY 1 1 3 1
-126 259 231
-
-# Inputs: I0 I1 I2 I3
-# Outputs: O
-SB_LUT4 2 1 4 1
-449 400 379 316
diff --git a/techlibs/ice40/hx.lut b/techlibs/ice40/hx.lut
deleted file mode 100644
index 3b3bb11e2..000000000
--- a/techlibs/ice40/hx.lut
+++ /dev/null
@@ -1,6 +0,0 @@
-# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_hx8k.txt
-#       I3  I2  I1  I0
-1   1   316
-2   1   316 379
-3   1   316 379 400
-4   1   316 379 400 449
diff --git a/techlibs/ice40/lp.box b/techlibs/ice40/lp.box
deleted file mode 100644
index 7eb8e86e0..000000000
--- a/techlibs/ice40/lp.box
+++ /dev/null
@@ -1,13 +0,0 @@
-# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_lp8k.txt
-
-# NB: Inputs/Outputs must be ordered alphabetically
-
-# Inputs: CI I0 I1
-# Outputs: CO
-SB_CARRY 1 1 3 1
-186 675 609
-
-# Inputs: I0 I1 I2 I3
-# Outputs: O
-SB_LUT4 2 1 4 1
-465 558 589 661
diff --git a/techlibs/ice40/lp.lut b/techlibs/ice40/lp.lut
deleted file mode 100644
index e72f760a2..000000000
--- a/techlibs/ice40/lp.lut
+++ /dev/null
@@ -1,6 +0,0 @@
-# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_lp8k.txt
-#       I3  I2  I1  I0
-1   1   465
-2   1   465 558
-3   1   465 558 589
-4   1   465 558 589 661
diff --git a/techlibs/ice40/u.box b/techlibs/ice40/u.box
deleted file mode 100644
index 94df1df8f..000000000
--- a/techlibs/ice40/u.box
+++ /dev/null
@@ -1,13 +0,0 @@
-# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_up5k.txt
-
-# NB: Inputs/Outputs must be ordered alphabetically
-
-# Inputs: CI I0 I1
-# Outputs: CO
-SB_CARRY 1 1 3 1
-278 675 609
-
-# Inputs: I0 I1 I2 I3
-# Outputs: O
-SB_LUT4 2 1 4 1
-1285 1231 1205 874
diff --git a/techlibs/ice40/u.lut b/techlibs/ice40/u.lut
deleted file mode 100644
index 1e4fcadb6..000000000
--- a/techlibs/ice40/u.lut
+++ /dev/null
@@ -1,6 +0,0 @@
-# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_up5k.txt
-#       I3  I2  I1  I0
-1   1   874
-2   1   874 1205
-3   1   874 1205 1231
-4   1   874 1205 1231 1285
-- 
cgit v1.2.3


From 8024f4189738af196f7ce432d95c73efd1f02955 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 18 Apr 2019 09:04:34 -0700
Subject: Fix rename

---
 techlibs/ice40/abc_hx.lut  | 6 ++++++
 techlibs/ice40/abc_lut.box | 6 ------
 2 files changed, 6 insertions(+), 6 deletions(-)
 create mode 100644 techlibs/ice40/abc_hx.lut
 delete mode 100644 techlibs/ice40/abc_lut.box

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/abc_hx.lut b/techlibs/ice40/abc_hx.lut
new file mode 100644
index 000000000..3b3bb11e2
--- /dev/null
+++ b/techlibs/ice40/abc_hx.lut
@@ -0,0 +1,6 @@
+# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_hx8k.txt
+#       I3  I2  I1  I0
+1   1   316
+2   1   316 379
+3   1   316 379 400
+4   1   316 379 400 449
diff --git a/techlibs/ice40/abc_lut.box b/techlibs/ice40/abc_lut.box
deleted file mode 100644
index 3b3bb11e2..000000000
--- a/techlibs/ice40/abc_lut.box
+++ /dev/null
@@ -1,6 +0,0 @@
-# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_hx8k.txt
-#       I3  I2  I1  I0
-1   1   316
-2   1   316 379
-3   1   316 379 400
-4   1   316 379 400 449
-- 
cgit v1.2.3


From 7b6ab937c14ae30d331527c71dffbc050aaba13c Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 18 Apr 2019 09:05:22 -0700
Subject: Make SB_LUT4 a blackbox

---
 techlibs/ice40/abc_hx.box | 2 +-
 techlibs/ice40/abc_lp.box | 2 +-
 techlibs/ice40/abc_u.box  | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/abc_hx.box b/techlibs/ice40/abc_hx.box
index c31f7bf39..5a18a8423 100644
--- a/techlibs/ice40/abc_hx.box
+++ b/techlibs/ice40/abc_hx.box
@@ -9,5 +9,5 @@ SB_CARRY 1 1 3 1
 
 # Inputs: I0 I1 I2 I3
 # Outputs: O
-SB_LUT4 2 1 4 1
+SB_LUT4 2 0 4 1
 449 400 379 316
diff --git a/techlibs/ice40/abc_lp.box b/techlibs/ice40/abc_lp.box
index 7eb8e86e0..87fe81585 100644
--- a/techlibs/ice40/abc_lp.box
+++ b/techlibs/ice40/abc_lp.box
@@ -9,5 +9,5 @@ SB_CARRY 1 1 3 1
 
 # Inputs: I0 I1 I2 I3
 # Outputs: O
-SB_LUT4 2 1 4 1
+SB_LUT4 2 0 4 1
 465 558 589 661
diff --git a/techlibs/ice40/abc_u.box b/techlibs/ice40/abc_u.box
index 94df1df8f..5035a4169 100644
--- a/techlibs/ice40/abc_u.box
+++ b/techlibs/ice40/abc_u.box
@@ -9,5 +9,5 @@ SB_CARRY 1 1 3 1
 
 # Inputs: I0 I1 I2 I3
 # Outputs: O
-SB_LUT4 2 1 4 1
+SB_LUT4 2 0 4 1
 1285 1231 1205 874
-- 
cgit v1.2.3


From 9278192efe5ae6382f4e011abaf417b45a6abfef Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 18 Apr 2019 09:58:34 -0700
Subject: Also update Makefile.inc

---
 techlibs/ice40/Makefile.inc | 13 ++++++-------
 1 file changed, 6 insertions(+), 7 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/Makefile.inc b/techlibs/ice40/Makefile.inc
index cb2121a11..d258d5a5d 100644
--- a/techlibs/ice40/Makefile.inc
+++ b/techlibs/ice40/Makefile.inc
@@ -28,13 +28,12 @@ $(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_sim.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/latches_map.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams.txt))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams_map.v))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc.v))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/hx.box))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/hx.lut))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/lp.box))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/lp.lut))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/u.box))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/u.lut))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_hx.box))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_hx.lut))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_lp.box))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_lp.lut))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_u.box))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_u.lut))
 
 $(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init1.vh))
 $(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init2.vh))
-- 
cgit v1.2.3


From 4c327cf316404fbedb1d26b0aebecaaf01d46f6b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 18 Apr 2019 10:32:41 -0700
Subject: Use new -wb flag for ABC flow

---
 techlibs/ice40/abc.v          | 12 ------------
 techlibs/ice40/cells_sim.v    |  2 ++
 techlibs/ice40/synth_ice40.cc | 10 +++-------
 3 files changed, 5 insertions(+), 19 deletions(-)
 delete mode 100644 techlibs/ice40/abc.v

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/abc.v b/techlibs/ice40/abc.v
deleted file mode 100644
index e2a54a42c..000000000
--- a/techlibs/ice40/abc.v
+++ /dev/null
@@ -1,12 +0,0 @@
-(* abc_box_id = 1 *)
-module SB_CARRY (output CO, input CI, I0, I1);
-	assign CO = (I0 && I1) || ((I0 || I1) && CI);
-endmodule
-
-(* abc_box_id = 2 *)
-module SB_LUT4 (output O, input I0, I1, I2, I3);
-	parameter [15:0] LUT_INIT = 0;
-	// Indicate this is a black-box
-	assign O = 1'b0;
-endmodule
-
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 70cd51ed1..dba563e37 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -118,6 +118,7 @@ endmodule
 
 // SiliconBlue Logic Cells
 
+(* abc_box_id = 2 *)
 module SB_LUT4 (output O, input I0, I1, I2, I3);
 	parameter [15:0] LUT_INIT = 0;
 	wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
@@ -126,6 +127,7 @@ module SB_LUT4 (output O, input I0, I1, I2, I3);
 	assign O = I0 ? s1[1] : s1[0];
 endmodule
 
+(* abc_box_id = 1, whitebox *)
 module SB_CARRY (output CO, input I0, I1, CI);
 	assign CO = (I0 && I1) || ((I0 || I1) && CI);
 endmodule
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 7c95588e4..84abf7181 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -240,7 +240,7 @@ struct SynthIce40Pass : public ScriptPass
 	{
 		if (check_label("begin"))
 		{
-			run("read_verilog -lib +/ice40/cells_sim.v");
+			run("read_verilog -wb +/ice40/cells_sim.v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 			run("proc");
 		}
@@ -327,12 +327,8 @@ struct SynthIce40Pass : public ScriptPass
 				run("techmap -map +/gate2lut.v -D LUT_WIDTH=4", "(only if -noabc)");
 			}
 			if (!noabc) {
-				if (abc == "abc9") {
-					run("read_verilog +/ice40/abc.v");
-					run("techmap -map +/techmap.v A:abc_box_id");
-					run(abc + stringf(" -dress -lut +/ice40/%s.lut -box +/ice40/%s.box", device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
-					run("blackbox A:abc_box_id");
-				}
+				if (abc == "abc9")
+					run(abc + stringf(" -dress -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
 				else
 					run(abc + " -lut 4", "(skip if -noabc)");
 			}
-- 
cgit v1.2.3


From ca1eb98a975e1d95629f8e55bfdd021221edf0b7 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 18 Apr 2019 17:46:32 -0700
Subject: Add SB_DFF* to boxes

---
 techlibs/ice40/abc_hx.box | 104 +++++++++++++++++++++++++++++++++++++++++++++-
 techlibs/ice40/abc_lp.box | 104 +++++++++++++++++++++++++++++++++++++++++++++-
 techlibs/ice40/abc_u.box  | 104 +++++++++++++++++++++++++++++++++++++++++++++-
 3 files changed, 306 insertions(+), 6 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/abc_hx.box b/techlibs/ice40/abc_hx.box
index 5a18a8423..9ebdae18b 100644
--- a/techlibs/ice40/abc_hx.box
+++ b/techlibs/ice40/abc_hx.box
@@ -2,12 +2,112 @@
 
 # NB: Inputs/Outputs must be ordered alphabetically
 
+# Inputs: C D
+# Outputs: Q
+SB_DFF 1 0 2 1
+- -
+
+# Inputs: C D E
+# Outputs: Q
+SB_DFFE 2 0 3 1
+- - -
+
+# Inputs: C D R
+# Outputs: Q
+SB_DFFSR 3 0 3 1
+- - -
+
+# Inputs: C D R
+# Outputs: Q
+SB_DFFR 4 0 3 1
+- - -
+
+# Inputs: C D S
+# Outputs: Q
+SB_DFFSS 5 0 3 1
+- - -
+
+# Inputs: C D S
+# Outputs: Q
+SB_DFFS 6 0 3 1
+- - -
+
+# Inputs: C D E R
+# Outputs: Q
+SB_DFFESR 7 0 4 1
+- - - -
+
+# Inputs: C D E R
+# Outputs: Q
+SB_DFFER 8 0 4 1
+- - - -
+
+# Inputs: C D E S
+# Outputs: Q
+SB_DFFESS 9 0 4 1
+- - - -
+
+# Inputs: C D E S
+# Outputs: Q
+SB_DFFES 10 0 4 1
+- - - -
+
+# Inputs: C D
+# Outputs: Q
+SB_DFFN 11 0 2 1
+- -
+
+# Inputs: C D E
+# Outputs: Q
+SB_DFFNE 12 0 3 1
+- - -
+
+# Inputs: C D R
+# Outputs: Q
+SB_DFFNSR 13 0 3 1
+- - -
+
+# Inputs: C D R
+# Outputs: Q
+SB_DFFNR 14 0 3 1
+- - -
+
+# Inputs: C D S
+# Outputs: Q
+SB_DFFNSS 15 0 3 1
+- - -
+
+# Inputs: C D S
+# Outputs: Q
+SB_DFFNS 16 0 3 1
+- - -
+
+# Inputs: C D E R
+# Outputs: Q
+SB_DFFNESR 17 0 4 1
+- - - -
+
+# Inputs: C D E R
+# Outputs: Q
+SB_DFFNER 18 0 4 1
+- - - -
+
+# Inputs: C D E S
+# Outputs: Q
+SB_DFFNESS 19 0 4 1
+- - - -
+
+# Inputs: C D E S
+# Outputs: Q
+SB_DFFNES 20 0 4 1
+- - - -
+
 # Inputs: CI I0 I1
 # Outputs: CO
-SB_CARRY 1 1 3 1
+SB_CARRY 21 1 3 1
 126 259 231
 
 # Inputs: I0 I1 I2 I3
 # Outputs: O
-SB_LUT4 2 0 4 1
+SB_LUT4 22 0 4 1
 449 400 379 316
diff --git a/techlibs/ice40/abc_lp.box b/techlibs/ice40/abc_lp.box
index 87fe81585..464821dac 100644
--- a/techlibs/ice40/abc_lp.box
+++ b/techlibs/ice40/abc_lp.box
@@ -2,12 +2,112 @@
 
 # NB: Inputs/Outputs must be ordered alphabetically
 
+# Inputs: C D
+# Outputs: Q
+SB_DFF 1 0 2 1
+- -
+
+# Inputs: C D E
+# Outputs: Q
+SB_DFFE 2 0 3 1
+- - -
+
+# Inputs: C D R
+# Outputs: Q
+SB_DFFSR 3 0 3 1
+- - -
+
+# Inputs: C D R
+# Outputs: Q
+SB_DFFR 4 0 3 1
+- - -
+
+# Inputs: C D S
+# Outputs: Q
+SB_DFFSS 5 0 3 1
+- - -
+
+# Inputs: C D S
+# Outputs: Q
+SB_DFFS 6 0 3 1
+- - -
+
+# Inputs: C D E R
+# Outputs: Q
+SB_DFFESR 7 0 4 1
+- - - -
+
+# Inputs: C D E R
+# Outputs: Q
+SB_DFFER 8 0 4 1
+- - - -
+
+# Inputs: C D E S
+# Outputs: Q
+SB_DFFESS 9 0 4 1
+- - - -
+
+# Inputs: C D E S
+# Outputs: Q
+SB_DFFES 10 0 4 1
+- - - -
+
+# Inputs: C D
+# Outputs: Q
+SB_DFFN 11 0 2 1
+- -
+
+# Inputs: C D E
+# Outputs: Q
+SB_DFFNE 12 0 3 1
+- - -
+
+# Inputs: C D R
+# Outputs: Q
+SB_DFFNSR 13 0 3 1
+- - -
+
+# Inputs: C D R
+# Outputs: Q
+SB_DFFNR 14 0 3 1
+- - -
+
+# Inputs: C D S
+# Outputs: Q
+SB_DFFNSS 15 0 3 1
+- - -
+
+# Inputs: C D S
+# Outputs: Q
+SB_DFFNS 16 0 3 1
+- - -
+
+# Inputs: C D E R
+# Outputs: Q
+SB_DFFNESR 17 0 4 1
+- - - -
+
+# Inputs: C D E R
+# Outputs: Q
+SB_DFFNER 18 0 4 1
+- - - -
+
+# Inputs: C D E S
+# Outputs: Q
+SB_DFFNESS 19 0 4 1
+- - - -
+
+# Inputs: C D E S
+# Outputs: Q
+SB_DFFNES 20 0 4 1
+- - - -
+
 # Inputs: CI I0 I1
 # Outputs: CO
-SB_CARRY 1 1 3 1
+SB_CARRY 21 1 3 1
 186 675 609
 
 # Inputs: I0 I1 I2 I3
 # Outputs: O
-SB_LUT4 2 0 4 1
+SB_LUT4 22 0 4 1
 465 558 589 661
diff --git a/techlibs/ice40/abc_u.box b/techlibs/ice40/abc_u.box
index 5035a4169..314bff401 100644
--- a/techlibs/ice40/abc_u.box
+++ b/techlibs/ice40/abc_u.box
@@ -2,12 +2,112 @@
 
 # NB: Inputs/Outputs must be ordered alphabetically
 
+# Inputs: C D
+# Outputs: Q
+SB_DFF 1 0 2 1
+- -
+
+# Inputs: C D E
+# Outputs: Q
+SB_DFFE 2 0 3 1
+- - -
+
+# Inputs: C D R
+# Outputs: Q
+SB_DFFSR 3 0 3 1
+- - -
+
+# Inputs: C D R
+# Outputs: Q
+SB_DFFR 4 0 3 1
+- - -
+
+# Inputs: C D S
+# Outputs: Q
+SB_DFFSS 5 0 3 1
+- - -
+
+# Inputs: C D S
+# Outputs: Q
+SB_DFFS 6 0 3 1
+- - -
+
+# Inputs: C D E R
+# Outputs: Q
+SB_DFFESR 7 0 4 1
+- - - -
+
+# Inputs: C D E R
+# Outputs: Q
+SB_DFFER 8 0 4 1
+- - - -
+
+# Inputs: C D E S
+# Outputs: Q
+SB_DFFESS 9 0 4 1
+- - - -
+
+# Inputs: C D E S
+# Outputs: Q
+SB_DFFES 10 0 4 1
+- - - -
+
+# Inputs: C D
+# Outputs: Q
+SB_DFFN 11 0 2 1
+- -
+
+# Inputs: C D E
+# Outputs: Q
+SB_DFFNE 12 0 3 1
+- - -
+
+# Inputs: C D R
+# Outputs: Q
+SB_DFFNSR 13 0 3 1
+- - -
+
+# Inputs: C D R
+# Outputs: Q
+SB_DFFNR 14 0 3 1
+- - -
+
+# Inputs: C D S
+# Outputs: Q
+SB_DFFNSS 15 0 3 1
+- - -
+
+# Inputs: C D S
+# Outputs: Q
+SB_DFFNS 16 0 3 1
+- - -
+
+# Inputs: C D E R
+# Outputs: Q
+SB_DFFNESR 17 0 4 1
+- - - -
+
+# Inputs: C D E R
+# Outputs: Q
+SB_DFFNER 18 0 4 1
+- - - -
+
+# Inputs: C D E S
+# Outputs: Q
+SB_DFFNESS 19 0 4 1
+- - - -
+
+# Inputs: C D E S
+# Outputs: Q
+SB_DFFNES 20 0 4 1
+- - - -
+
 # Inputs: CI I0 I1
 # Outputs: CO
-SB_CARRY 1 1 3 1
+SB_CARRY 21 1 3 1
 278 675 609
 
 # Inputs: I0 I1 I2 I3
 # Outputs: O
-SB_LUT4 2 0 4 1
+SB_LUT4 22 0 4 1
 1285 1231 1205 874
-- 
cgit v1.2.3


From cf66416110f60b7dce10a78960898ceb52f51626 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 18 Apr 2019 17:46:53 -0700
Subject: Annotate SB_DFF* with abc_flop and abc_box_id

---
 techlibs/ice40/cells_sim.v | 71 ++++++++++++++++++++++++++++++++--------------
 1 file changed, 49 insertions(+), 22 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index dba563e37..a6f1fc9de 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -118,7 +118,7 @@ endmodule
 
 // SiliconBlue Logic Cells
 
-(* abc_box_id = 2 *)
+(* abc_box_id = 22 *
 module SB_LUT4 (output O, input I0, I1, I2, I3);
 	parameter [15:0] LUT_INIT = 0;
 	wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
@@ -127,25 +127,35 @@ module SB_LUT4 (output O, input I0, I1, I2, I3);
 	assign O = I0 ? s1[1] : s1[0];
 endmodule
 
-(* abc_box_id = 1, whitebox *)
+(* abc_box_id = 21, whitebox *)
 module SB_CARRY (output CO, input I0, I1, CI);
 	assign CO = (I0 && I1) || ((I0 || I1) && CI);
 endmodule
 
 // Positive Edge SiliconBlue FF Cells
 
-module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, D);
+(* abc_box_id = 1, abc_flop *)
+`ifdef ABC_FLOPS
+    (* whitebox *)
+`endif
+module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, (* abc_flop_d *) input D);
+`ifndef ABC_FLOPS
 	always @(posedge C)
 		Q <= D;
+`else
+    assign Q = D;
+`endif
 endmodule
 
-module SB_DFFE ((* abc_flop_q *) output `SB_DFF_REG, input C, E, D);
+//(* abc_box_id = 2, abc_flop *)
+module SB_DFFE ((* abc_flop_q *) output `SB_DFF_REG, input C, E, (* abc_flop_d *) input D);
 	always @(posedge C)
 		if (E)
 			Q <= D;
 endmodule
 
-module SB_DFFSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
+//(* abc_box_id = 3, abc_flop *)
+module SB_DFFSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, (* abc_flop_d *) input D);
 	always @(posedge C)
 		if (R)
 			Q <= 0;
@@ -153,7 +163,8 @@ module SB_DFFSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
+//(* abc_box_id = 4, abc_flop *)
+module SB_DFFR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, (* abc_flop_d *) input D);
 	always @(posedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -161,7 +172,8 @@ module SB_DFFR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
+//(* abc_box_id = 5, abc_flop *)
+module SB_DFFSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, (* abc_flop_d *) input D);
 	always @(posedge C)
 		if (S)
 			Q <= 1;
@@ -169,7 +181,8 @@ module SB_DFFSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
 			Q <= D;
 endmodule
 
-module SB_DFFS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
+//(* abc_box_id = 6, abc_flop *)
+module SB_DFFS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, (* abc_flop_d *) input D);
 	always @(posedge C, posedge S)
 		if (S)
 			Q <= 1;
@@ -177,7 +190,8 @@ module SB_DFFS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
 			Q <= D;
 endmodule
 
-module SB_DFFESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
+//(* abc_box_id = 7, abc_flop *)
+module SB_DFFESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, (* abc_flop_d *) input D);
 	always @(posedge C)
 		if (E) begin
 			if (R)
@@ -187,7 +201,8 @@ module SB_DFFESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
 		end
 endmodule
 
-module SB_DFFER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
+//(* abc_box_id = 8, abc_flop *)
+module SB_DFFER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, (* abc_flop_d *) input D);
 	always @(posedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -195,7 +210,8 @@ module SB_DFFER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
+//(* abc_box_id = 9, abc_flop *)
+module SB_DFFESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, (* abc_flop_d *) input D);
 	always @(posedge C)
 		if (E) begin
 			if (S)
@@ -205,7 +221,8 @@ module SB_DFFESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
 		end
 endmodule
 
-module SB_DFFES ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
+//(* abc_box_id = 10, abc_flop *)
+module SB_DFFES ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, (* abc_flop_d *) input D);
 	always @(posedge C, posedge S)
 		if (S)
 			Q <= 1;
@@ -215,18 +232,21 @@ endmodule
 
 // Negative Edge SiliconBlue FF Cells
 
-module SB_DFFN ((* abc_flop_q *) output `SB_DFF_REG, input C, D);
+//(* abc_box_id = 11, abc_flop *)
+module SB_DFFN ((* abc_flop_q *) output `SB_DFF_REG, input C, (* abc_flop_d *) input D);
 	always @(negedge C)
 		Q <= D;
 endmodule
 
-module SB_DFFNE ((* abc_flop_q *) output `SB_DFF_REG, input C, E, D);
+//(* abc_box_id = 12, abc_flop *)
+module SB_DFFNE ((* abc_flop_q *) output `SB_DFF_REG, input C, E, (* abc_flop_d *) input D);
 	always @(negedge C)
 		if (E)
 			Q <= D;
 endmodule
 
-module SB_DFFNSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
+//(* abc_box_id = 13, abc_flop *)
+module SB_DFFNSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, (* abc_flop_d *) input D);
 	always @(negedge C)
 		if (R)
 			Q <= 0;
@@ -234,7 +254,8 @@ module SB_DFFNSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
+//(* abc_box_id = 14, abc_flop *)
+module SB_DFFNR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, (* abc_flop_d *) input D);
 	always @(negedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -242,7 +263,8 @@ module SB_DFFNR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
+//(* abc_box_id = 15, abc_flop *)
+module SB_DFFNSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, (* abc_flop_d *) input D);
 	always @(negedge C)
 		if (S)
 			Q <= 1;
@@ -250,7 +272,8 @@ module SB_DFFNSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
+//(* abc_box_id = 16, abc_flop *)
+module SB_DFFNS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, (* abc_flop_d *) input D);
 	always @(negedge C, posedge S)
 		if (S)
 			Q <= 1;
@@ -258,7 +281,8 @@ module SB_DFFNS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
+//(* abc_box_id = 17, abc_flop *)
+module SB_DFFNESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, (* abc_flop_d *) input D);
 	always @(negedge C)
 		if (E) begin
 			if (R)
@@ -268,7 +292,8 @@ module SB_DFFNESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
 		end
 endmodule
 
-module SB_DFFNER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
+//(* abc_box_id = 18, abc_flop *)
+module SB_DFFNER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, (* abc_flop_d *) input D);
 	always @(negedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -276,7 +301,8 @@ module SB_DFFNER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
+//(* abc_box_id = 19, abc_flop *)
+module SB_DFFNESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, (* abc_flop_d *) input D);
 	always @(negedge C)
 		if (E) begin
 			if (S)
@@ -286,7 +312,8 @@ module SB_DFFNESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
 		end
 endmodule
 
-module SB_DFFNES ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
+//(* abc_box_id = 20, abc_flop *)
+module SB_DFFNES ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, (* abc_flop_d *) input D);
 	always @(negedge C, posedge S)
 		if (S)
 			Q <= 1;
-- 
cgit v1.2.3


From 0919f36b88bed88e6dbfa23381540dc8ee035962 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 18 Apr 2019 17:50:11 -0700
Subject: Missing close bracket

---
 techlibs/ice40/cells_sim.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index a6f1fc9de..1d104c5d7 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -118,7 +118,7 @@ endmodule
 
 // SiliconBlue Logic Cells
 
-(* abc_box_id = 22 *
+(* abc_box_id = 22 *)
 module SB_LUT4 (output O, input I0, I1, I2, I3);
 	parameter [15:0] LUT_INIT = 0;
 	wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
-- 
cgit v1.2.3


From 19b660ff6e8b493ff3de43ce59e393c56b9a6b3b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 18 Apr 2019 23:07:16 -0700
Subject: Fix SB_DFF comb model

---
 techlibs/ice40/cells_sim.v    | 2 +-
 techlibs/ice40/synth_ice40.cc | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 1d104c5d7..c49b29ab3 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -143,7 +143,7 @@ module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, (* abc_flop_d *) in
 	always @(posedge C)
 		Q <= D;
 `else
-    assign Q = D;
+    always @* Q = D;
 `endif
 endmodule
 
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 84abf7181..d5d354701 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -240,7 +240,7 @@ struct SynthIce40Pass : public ScriptPass
 	{
 		if (check_label("begin"))
 		{
-			run("read_verilog -wb +/ice40/cells_sim.v");
+			run("read_verilog -wb -D ABC_FLOPS +/ice40/cells_sim.v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 			run("proc");
 		}
@@ -293,7 +293,7 @@ struct SynthIce40Pass : public ScriptPass
 				run("techmap");
 			else
 				run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
-			if (retime || help_mode)
+			if ((retime || help_mode) && abc != "abc9")
 				run(abc + " -dff", "(only if -retime)");
 			run("ice40_opt");
 		}
-- 
cgit v1.2.3


From 2776925bcf04e67d1c33812e102d1195dca393bf Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 19 Apr 2019 08:36:38 -0700
Subject: Make SB_DFF whitebox

---
 techlibs/ice40/abc_hx.box | 2 +-
 techlibs/ice40/abc_lp.box | 2 +-
 techlibs/ice40/abc_u.box  | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/abc_hx.box b/techlibs/ice40/abc_hx.box
index 9ebdae18b..994f3091d 100644
--- a/techlibs/ice40/abc_hx.box
+++ b/techlibs/ice40/abc_hx.box
@@ -4,7 +4,7 @@
 
 # Inputs: C D
 # Outputs: Q
-SB_DFF 1 0 2 1
+SB_DFF 1 1 2 1
 - -
 
 # Inputs: C D E
diff --git a/techlibs/ice40/abc_lp.box b/techlibs/ice40/abc_lp.box
index 464821dac..002b7bba4 100644
--- a/techlibs/ice40/abc_lp.box
+++ b/techlibs/ice40/abc_lp.box
@@ -4,7 +4,7 @@
 
 # Inputs: C D
 # Outputs: Q
-SB_DFF 1 0 2 1
+SB_DFF 1 1 2 1
 - -
 
 # Inputs: C D E
diff --git a/techlibs/ice40/abc_u.box b/techlibs/ice40/abc_u.box
index 314bff401..cb336181c 100644
--- a/techlibs/ice40/abc_u.box
+++ b/techlibs/ice40/abc_u.box
@@ -4,7 +4,7 @@
 
 # Inputs: C D
 # Outputs: Q
-SB_DFF 1 0 2 1
+SB_DFF 1 1 2 1
 - -
 
 # Inputs: C D E
-- 
cgit v1.2.3


From af4652522fd01aaec84664e65d7fe1474c578c49 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 19 Apr 2019 21:09:55 -0700
Subject: ABC_FLOPS -> ABC_MODEL -- only whitebox if ABC_MODEL set

---
 techlibs/ice40/cells_sim.v    | 9 ++++++---
 techlibs/ice40/synth_ice40.cc | 2 +-
 2 files changed, 7 insertions(+), 4 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index c49b29ab3..a98bc30d9 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -127,7 +127,10 @@ module SB_LUT4 (output O, input I0, I1, I2, I3);
 	assign O = I0 ? s1[1] : s1[0];
 endmodule
 
-(* abc_box_id = 21, whitebox *)
+(* abc_box_id = 21 *)
+`ifdef ABC_MODEL
+    (* whitebox *)
+`endif
 module SB_CARRY (output CO, input I0, I1, CI);
 	assign CO = (I0 && I1) || ((I0 || I1) && CI);
 endmodule
@@ -135,11 +138,11 @@ endmodule
 // Positive Edge SiliconBlue FF Cells
 
 (* abc_box_id = 1, abc_flop *)
-`ifdef ABC_FLOPS
+`ifdef ABC_MODEL
     (* whitebox *)
 `endif
 module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, (* abc_flop_d *) input D);
-`ifndef ABC_FLOPS
+`ifndef ABC_MODEL
 	always @(posedge C)
 		Q <= D;
 `else
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index d5d354701..7cedecdff 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -240,7 +240,7 @@ struct SynthIce40Pass : public ScriptPass
 	{
 		if (check_label("begin"))
 		{
-			run("read_verilog -wb -D ABC_FLOPS +/ice40/cells_sim.v");
+			run("read_verilog -wb -D ABC_MODEL +/ice40/cells_sim.v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 			run("proc");
 		}
-- 
cgit v1.2.3


From d7f0700bae9785a55353ca76fe9f354ee4ffe03e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Sun, 21 Apr 2019 15:19:02 -0700
Subject: Convert to use #945

---
 techlibs/ice40/cells_sim.v    | 10 ++--------
 techlibs/ice40/synth_ice40.cc |  2 +-
 2 files changed, 3 insertions(+), 9 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index a98bc30d9..93d970762 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -127,20 +127,14 @@ module SB_LUT4 (output O, input I0, I1, I2, I3);
 	assign O = I0 ? s1[1] : s1[0];
 endmodule
 
-(* abc_box_id = 21 *)
-`ifdef ABC_MODEL
-    (* whitebox *)
-`endif
+(* abc_box_id = 21, lib_whitebox *)
 module SB_CARRY (output CO, input I0, I1, CI);
 	assign CO = (I0 && I1) || ((I0 || I1) && CI);
 endmodule
 
 // Positive Edge SiliconBlue FF Cells
 
-(* abc_box_id = 1, abc_flop *)
-`ifdef ABC_MODEL
-    (* whitebox *)
-`endif
+(* abc_box_id = 1, abc_flop, lib_whitebox *)
 module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, (* abc_flop_d *) input D);
 `ifndef ABC_MODEL
 	always @(posedge C)
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 7cedecdff..718f9d9e0 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -240,7 +240,7 @@ struct SynthIce40Pass : public ScriptPass
 	{
 		if (check_label("begin"))
 		{
-			run("read_verilog -wb -D ABC_MODEL +/ice40/cells_sim.v");
+			run("read_verilog -lib -D ABC_MODEL +/ice40/cells_sim.v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 			run("proc");
 		}
-- 
cgit v1.2.3


From 91c3afcab723d85d3c6931561cb13ad7b70e7e5c Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 23 Apr 2019 13:42:06 -0700
Subject: Use nonblocking

---
 techlibs/ice40/cells_sim.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 40e54f9f0..40972766d 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -149,7 +149,7 @@ module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, (* abc_flop_d *) in
 	always @(posedge C)
 		Q <= D;
 `else
-    always @* Q = D;
+    always @* Q <= D;
 `endif
 endmodule
 
-- 
cgit v1.2.3


From 9f44a7171528b90e85b2f33ef8823660fbd95609 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 3 Jun 2019 09:23:43 -0700
Subject: Consistent with xilinx

---
 techlibs/ice40/abc_hx.box     | 2 +-
 techlibs/ice40/cells_sim.v    | 2 +-
 techlibs/ice40/synth_ice40.cc | 4 ++--
 3 files changed, 4 insertions(+), 4 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/abc_hx.box b/techlibs/ice40/abc_hx.box
index 994f3091d..9ebdae18b 100644
--- a/techlibs/ice40/abc_hx.box
+++ b/techlibs/ice40/abc_hx.box
@@ -4,7 +4,7 @@
 
 # Inputs: C D
 # Outputs: Q
-SB_DFF 1 1 2 1
+SB_DFF 1 0 2 1
 - -
 
 # Inputs: C D E
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index b5e10fb20..6897aeeb4 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -145,7 +145,7 @@ endmodule
 
 (* abc_box_id = 1, abc_flop, lib_whitebox *)
 module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, (* abc_flop_d *) input D);
-`ifndef ABC_MODEL
+`ifndef _ABC
 	always @(posedge C)
 		Q <= D;
 `else
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 168161a90..5afa042b0 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -240,7 +240,7 @@ struct SynthIce40Pass : public ScriptPass
 	{
 		if (check_label("begin"))
 		{
-			run("read_verilog -lib -D ABC_MODEL +/ice40/cells_sim.v");
+			run("read_verilog -lib -D_ABC +/ice40/cells_sim.v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 			run("proc");
 		}
@@ -334,7 +334,7 @@ struct SynthIce40Pass : public ScriptPass
 				if (abc == "abc9")
 					run(abc + stringf(" -dress -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
 				else
-					run(abc + " -lut 4", "(skip if -noabc)");
+					run(abc + " -dress -lut 4", "(skip if -noabc)");
 			}
 			run("clean");
 			if (relut || help_mode) {
-- 
cgit v1.2.3


From 4da25c76b365b7c90a368c36def81d1122434b95 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 3 Jun 2019 09:33:42 -0700
Subject: Ooopsie

---
 techlibs/ice40/cells_map.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_map.v b/techlibs/ice40/cells_map.v
index 287c48b11..759549e30 100644
--- a/techlibs/ice40/cells_map.v
+++ b/techlibs/ice40/cells_map.v
@@ -53,7 +53,7 @@ module \$lut (A, Y);
     end else
     if (WIDTH == 4) begin
       localparam [15:0] INIT = {LUT[15], LUT[7], LUT[11], LUT[3], LUT[13], LUT[5], LUT[9], LUT[1], LUT[14], LUT[6], LUT[10], LUT[2], LUT[12], LUT[4], LUT[8], LUT[0]};
-      SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
+      SB_LUT4 #(.LUT_INIT(INIT)) _TECHMAP_REPLACE_ (.O(Y),
         .I0(A[3]), .I1(A[2]), .I2(A[1]), .I3(A[0]));
     end else begin
       wire _TECHMAP_FAIL_ = 1;
-- 
cgit v1.2.3


From 00927703177d01ad27559aad827b72068b80b12a Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 3 Jun 2019 12:34:55 -0700
Subject: Make SB_LUT4 a whitebox, SB_DFF a blackbox (for now)

---
 techlibs/ice40/abc_hx.box  | 2 +-
 techlibs/ice40/abc_lp.box  | 4 ++--
 techlibs/ice40/abc_u.box   | 4 ++--
 techlibs/ice40/cells_sim.v | 6 +++---
 4 files changed, 8 insertions(+), 8 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/abc_hx.box b/techlibs/ice40/abc_hx.box
index 9ebdae18b..a0655643d 100644
--- a/techlibs/ice40/abc_hx.box
+++ b/techlibs/ice40/abc_hx.box
@@ -109,5 +109,5 @@ SB_CARRY 21 1 3 1
 
 # Inputs: I0 I1 I2 I3
 # Outputs: O
-SB_LUT4 22 0 4 1
+SB_LUT4 22 1 4 1
 449 400 379 316
diff --git a/techlibs/ice40/abc_lp.box b/techlibs/ice40/abc_lp.box
index 002b7bba4..dbc98d0c4 100644
--- a/techlibs/ice40/abc_lp.box
+++ b/techlibs/ice40/abc_lp.box
@@ -4,7 +4,7 @@
 
 # Inputs: C D
 # Outputs: Q
-SB_DFF 1 1 2 1
+SB_DFF 1 0 2 1
 - -
 
 # Inputs: C D E
@@ -109,5 +109,5 @@ SB_CARRY 21 1 3 1
 
 # Inputs: I0 I1 I2 I3
 # Outputs: O
-SB_LUT4 22 0 4 1
+SB_LUT4 22 1 4 1
 465 558 589 661
diff --git a/techlibs/ice40/abc_u.box b/techlibs/ice40/abc_u.box
index cb336181c..3b5834e40 100644
--- a/techlibs/ice40/abc_u.box
+++ b/techlibs/ice40/abc_u.box
@@ -4,7 +4,7 @@
 
 # Inputs: C D
 # Outputs: Q
-SB_DFF 1 1 2 1
+SB_DFF 1 0 2 1
 - -
 
 # Inputs: C D E
@@ -109,5 +109,5 @@ SB_CARRY 21 1 3 1
 
 # Inputs: I0 I1 I2 I3
 # Outputs: O
-SB_LUT4 22 0 4 1
+SB_LUT4 22 1 4 1
 1285 1231 1205 874
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 6897aeeb4..b9f381266 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -127,7 +127,7 @@ endmodule
 
 // SiliconBlue Logic Cells
 
-(* abc_box_id = 22 *)
+(* abc_box_id = 22, lib_whitebox *)
 module SB_LUT4 (output O, input I0, I1, I2, I3);
 	parameter [15:0] LUT_INIT = 0;
 	wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
@@ -136,8 +136,8 @@ module SB_LUT4 (output O, input I0, I1, I2, I3);
 	assign O = I0 ? s1[1] : s1[0];
 endmodule
 
-(* abc_box_id = 21, lib_whitebox *)
-module SB_CARRY (output CO, input I0, I1, CI);
+(* abc_box_id = 21, abc_carry, lib_whitebox *)
+module SB_CARRY ((* abc_carry_out *) output CO, input I0, I1, (* abc_carry_in *) input CI);
 	assign CO = (I0 && I1) || ((I0 || I1) && CI);
 endmodule
 
-- 
cgit v1.2.3


From abf90b040331f9fd48c9e4bdb4bbb952db4c2d04 Mon Sep 17 00:00:00 2001
From: Simon Schubert <2@0x2c.org>
Date: Mon, 10 Jun 2019 11:49:08 +0200
Subject: ice40/cells_sim.v: Add support for RGB_DRV/LED_DRV_CUR for u4k

---
 techlibs/ice40/cells_sim.v | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index e89405b22..f9945b2b5 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -973,6 +973,30 @@ parameter RGB1_CURRENT = "0b000000";
 parameter RGB2_CURRENT = "0b000000";
 endmodule
 
+(* blackbox *)
+module SB_LED_DRV_CUR(
+	input EN,
+	output LEDPU
+);
+endmodule
+
+(* blackbox *)
+module SB_RGB_DRV(
+	input RGBLEDEN,
+	input RGB0PWM,
+	input RGB1PWM,
+	input RGB2PWM,
+	input RGBPU,
+	output RGB0,
+	output RGB1,
+	output RGB2
+);
+parameter CURRENT_MODE = "0b0";
+parameter RGB0_CURRENT = "0b000000";
+parameter RGB1_CURRENT = "0b000000";
+parameter RGB2_CURRENT = "0b000000";
+endmodule
+
 (* blackbox *)
 module SB_I2C(
 	input  SBCLKI,
-- 
cgit v1.2.3


From f9433cc34bd52d4807c318a6b26f63cdd15d35c0 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 12 Jun 2019 09:29:30 -0700
Subject: Remove abc_flop{,_d} attributes from ice40/cells_sim.v

---
 techlibs/ice40/cells_sim.v | 60 ++++++++++++++++------------------------------
 1 file changed, 20 insertions(+), 40 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 523dd8cbe..55b4d98c9 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -143,8 +143,7 @@ endmodule
 
 // Positive Edge SiliconBlue FF Cells
 
-(* abc_box_id = 1, abc_flop, lib_whitebox *)
-module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, (* abc_flop_d *) input D);
+module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, D);
 `ifndef _ABC
 	always @(posedge C)
 		Q <= D;
@@ -153,15 +152,13 @@ module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, (* abc_flop_d *) in
 `endif
 endmodule
 
-//(* abc_box_id = 2, abc_flop *)
-module SB_DFFE ((* abc_flop_q *) output `SB_DFF_REG, input C, E, (* abc_flop_d *) input D);
+module SB_DFFE ((* abc_flop_q *) output `SB_DFF_REG, input C, E, D);
 	always @(posedge C)
 		if (E)
 			Q <= D;
 endmodule
 
-//(* abc_box_id = 3, abc_flop *)
-module SB_DFFSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, (* abc_flop_d *) input D);
+module SB_DFFSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
 	always @(posedge C)
 		if (R)
 			Q <= 0;
@@ -169,8 +166,7 @@ module SB_DFFSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, (* abc_flop_d
 			Q <= D;
 endmodule
 
-//(* abc_box_id = 4, abc_flop *)
-module SB_DFFR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, (* abc_flop_d *) input D);
+module SB_DFFR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
 	always @(posedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -178,8 +174,7 @@ module SB_DFFR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, (* abc_flop_d *
 			Q <= D;
 endmodule
 
-//(* abc_box_id = 5, abc_flop *)
-module SB_DFFSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, (* abc_flop_d *) input D);
+module SB_DFFSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
 	always @(posedge C)
 		if (S)
 			Q <= 1;
@@ -187,8 +182,7 @@ module SB_DFFSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, (* abc_flop_d
 			Q <= D;
 endmodule
 
-//(* abc_box_id = 6, abc_flop *)
-module SB_DFFS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, (* abc_flop_d *) input D);
+module SB_DFFS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
 	always @(posedge C, posedge S)
 		if (S)
 			Q <= 1;
@@ -196,8 +190,7 @@ module SB_DFFS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, (* abc_flop_d *
 			Q <= D;
 endmodule
 
-//(* abc_box_id = 7, abc_flop *)
-module SB_DFFESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, (* abc_flop_d *) input D);
+module SB_DFFESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
 	always @(posedge C)
 		if (E) begin
 			if (R)
@@ -207,8 +200,7 @@ module SB_DFFESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, (* abc_flo
 		end
 endmodule
 
-//(* abc_box_id = 8, abc_flop *)
-module SB_DFFER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, (* abc_flop_d *) input D);
+module SB_DFFER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
 	always @(posedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -216,8 +208,7 @@ module SB_DFFER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, (* abc_flop
 			Q <= D;
 endmodule
 
-//(* abc_box_id = 9, abc_flop *)
-module SB_DFFESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, (* abc_flop_d *) input D);
+module SB_DFFESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
 	always @(posedge C)
 		if (E) begin
 			if (S)
@@ -227,8 +218,7 @@ module SB_DFFESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, (* abc_flo
 		end
 endmodule
 
-//(* abc_box_id = 10, abc_flop *)
-module SB_DFFES ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, (* abc_flop_d *) input D);
+module SB_DFFES ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
 	always @(posedge C, posedge S)
 		if (S)
 			Q <= 1;
@@ -238,21 +228,18 @@ endmodule
 
 // Negative Edge SiliconBlue FF Cells
 
-//(* abc_box_id = 11, abc_flop *)
-module SB_DFFN ((* abc_flop_q *) output `SB_DFF_REG, input C, (* abc_flop_d *) input D);
+module SB_DFFN ((* abc_flop_q *) output `SB_DFF_REG, input C, D);
 	always @(negedge C)
 		Q <= D;
 endmodule
 
-//(* abc_box_id = 12, abc_flop *)
-module SB_DFFNE ((* abc_flop_q *) output `SB_DFF_REG, input C, E, (* abc_flop_d *) input D);
+module SB_DFFNE ((* abc_flop_q *) output `SB_DFF_REG, input C, E, D);
 	always @(negedge C)
 		if (E)
 			Q <= D;
 endmodule
 
-//(* abc_box_id = 13, abc_flop *)
-module SB_DFFNSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, (* abc_flop_d *) input D);
+module SB_DFFNSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
 	always @(negedge C)
 		if (R)
 			Q <= 0;
@@ -260,8 +247,7 @@ module SB_DFFNSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, (* abc_flop_d
 			Q <= D;
 endmodule
 
-//(* abc_box_id = 14, abc_flop *)
-module SB_DFFNR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, (* abc_flop_d *) input D);
+module SB_DFFNR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
 	always @(negedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -269,8 +255,7 @@ module SB_DFFNR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, (* abc_flop_d
 			Q <= D;
 endmodule
 
-//(* abc_box_id = 15, abc_flop *)
-module SB_DFFNSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, (* abc_flop_d *) input D);
+module SB_DFFNSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
 	always @(negedge C)
 		if (S)
 			Q <= 1;
@@ -278,8 +263,7 @@ module SB_DFFNSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, (* abc_flop_d
 			Q <= D;
 endmodule
 
-//(* abc_box_id = 16, abc_flop *)
-module SB_DFFNS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, (* abc_flop_d *) input D);
+module SB_DFFNS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
 	always @(negedge C, posedge S)
 		if (S)
 			Q <= 1;
@@ -287,8 +271,7 @@ module SB_DFFNS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, (* abc_flop_d
 			Q <= D;
 endmodule
 
-//(* abc_box_id = 17, abc_flop *)
-module SB_DFFNESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, (* abc_flop_d *) input D);
+module SB_DFFNESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
 	always @(negedge C)
 		if (E) begin
 			if (R)
@@ -298,8 +281,7 @@ module SB_DFFNESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, (* abc_fl
 		end
 endmodule
 
-//(* abc_box_id = 18, abc_flop *)
-module SB_DFFNER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, (* abc_flop_d *) input D);
+module SB_DFFNER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
 	always @(negedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -307,8 +289,7 @@ module SB_DFFNER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, (* abc_flo
 			Q <= D;
 endmodule
 
-//(* abc_box_id = 19, abc_flop *)
-module SB_DFFNESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, (* abc_flop_d *) input D);
+module SB_DFFNESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
 	always @(negedge C)
 		if (E) begin
 			if (S)
@@ -318,8 +299,7 @@ module SB_DFFNESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, (* abc_fl
 		end
 endmodule
 
-//(* abc_box_id = 20, abc_flop *)
-module SB_DFFNES ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, (* abc_flop_d *) input D);
+module SB_DFFNES ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
 	always @(negedge C, posedge S)
 		if (S)
 			Q <= 1;
-- 
cgit v1.2.3


From 2052806d3361dca8a866aee0665af223db51bdbd Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 13 Jun 2019 08:24:33 -0700
Subject: Fix LP SB_LUT4 timing

---
 techlibs/ice40/abc_lp.box | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/abc_lp.box b/techlibs/ice40/abc_lp.box
index dbc98d0c4..eb1cd0937 100644
--- a/techlibs/ice40/abc_lp.box
+++ b/techlibs/ice40/abc_lp.box
@@ -110,4 +110,4 @@ SB_CARRY 21 1 3 1
 # Inputs: I0 I1 I2 I3
 # Outputs: O
 SB_LUT4 22 1 4 1
-465 558 589 661
+661 589 558 465
-- 
cgit v1.2.3


From 627a62a797ef9e676ba9d89f53f927d0c2463585 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 14 Jun 2019 10:32:46 -0700
Subject: Make doc consistent

---
 techlibs/ice40/synth_ice40.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 5afa042b0..a60829764 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -97,7 +97,7 @@ struct SynthIce40Pass : public ScriptPass
 		log("        (this feature is experimental and incomplete)\n");
 		log("\n");
 		log("    -abc9\n");
-		log("        use abc9 instead of abc\n");
+		log("        use new ABC9 flow (EXPERIMENTAL)\n");
 		log("\n");
 		log("\n");
 		log("The following commands are executed by this synthesis command:\n");
-- 
cgit v1.2.3


From ee428f73abdbbde95601e583db186d86a8fa6b91 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 14 Jun 2019 10:37:52 -0700
Subject: Remove WIP ABC9 flop support

---
 techlibs/ice40/cells_sim.v | 50 +++++++++++++++++++++++-----------------------
 1 file changed, 25 insertions(+), 25 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 55b4d98c9..031afa85c 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -143,7 +143,7 @@ endmodule
 
 // Positive Edge SiliconBlue FF Cells
 
-module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, D);
+module SB_DFF (output `SB_DFF_REG, input C, D);
 `ifndef _ABC
 	always @(posedge C)
 		Q <= D;
@@ -152,13 +152,13 @@ module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, D);
 `endif
 endmodule
 
-module SB_DFFE ((* abc_flop_q *) output `SB_DFF_REG, input C, E, D);
+module SB_DFFE (output `SB_DFF_REG, input C, E, D);
 	always @(posedge C)
 		if (E)
 			Q <= D;
 endmodule
 
-module SB_DFFSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
+module SB_DFFSR (output `SB_DFF_REG, input C, R, D);
 	always @(posedge C)
 		if (R)
 			Q <= 0;
@@ -166,7 +166,7 @@ module SB_DFFSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
+module SB_DFFR (output `SB_DFF_REG, input C, R, D);
 	always @(posedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -174,7 +174,7 @@ module SB_DFFR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
+module SB_DFFSS (output `SB_DFF_REG, input C, S, D);
 	always @(posedge C)
 		if (S)
 			Q <= 1;
@@ -182,7 +182,7 @@ module SB_DFFSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
 			Q <= D;
 endmodule
 
-module SB_DFFS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
+module SB_DFFS (output `SB_DFF_REG, input C, S, D);
 	always @(posedge C, posedge S)
 		if (S)
 			Q <= 1;
@@ -190,7 +190,7 @@ module SB_DFFS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
 			Q <= D;
 endmodule
 
-module SB_DFFESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFESR (output `SB_DFF_REG, input C, E, R, D);
 	always @(posedge C)
 		if (E) begin
 			if (R)
@@ -200,7 +200,7 @@ module SB_DFFESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
 		end
 endmodule
 
-module SB_DFFER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFER (output `SB_DFF_REG, input C, E, R, D);
 	always @(posedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -208,7 +208,7 @@ module SB_DFFER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFESS (output `SB_DFF_REG, input C, E, S, D);
 	always @(posedge C)
 		if (E) begin
 			if (S)
@@ -218,7 +218,7 @@ module SB_DFFESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
 		end
 endmodule
 
-module SB_DFFES ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFES (output `SB_DFF_REG, input C, E, S, D);
 	always @(posedge C, posedge S)
 		if (S)
 			Q <= 1;
@@ -228,18 +228,18 @@ endmodule
 
 // Negative Edge SiliconBlue FF Cells
 
-module SB_DFFN ((* abc_flop_q *) output `SB_DFF_REG, input C, D);
+module SB_DFFN (output `SB_DFF_REG, input C, D);
 	always @(negedge C)
 		Q <= D;
 endmodule
 
-module SB_DFFNE ((* abc_flop_q *) output `SB_DFF_REG, input C, E, D);
+module SB_DFFNE (output `SB_DFF_REG, input C, E, D);
 	always @(negedge C)
 		if (E)
 			Q <= D;
 endmodule
 
-module SB_DFFNSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
+module SB_DFFNSR (output `SB_DFF_REG, input C, R, D);
 	always @(negedge C)
 		if (R)
 			Q <= 0;
@@ -247,7 +247,7 @@ module SB_DFFNSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
+module SB_DFFNR (output `SB_DFF_REG, input C, R, D);
 	always @(negedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -255,7 +255,7 @@ module SB_DFFNR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
+module SB_DFFNSS (output `SB_DFF_REG, input C, S, D);
 	always @(negedge C)
 		if (S)
 			Q <= 1;
@@ -263,7 +263,7 @@ module SB_DFFNSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
+module SB_DFFNS (output `SB_DFF_REG, input C, S, D);
 	always @(negedge C, posedge S)
 		if (S)
 			Q <= 1;
@@ -271,7 +271,7 @@ module SB_DFFNS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFNESR (output `SB_DFF_REG, input C, E, R, D);
 	always @(negedge C)
 		if (E) begin
 			if (R)
@@ -281,7 +281,7 @@ module SB_DFFNESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
 		end
 endmodule
 
-module SB_DFFNER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFNER (output `SB_DFF_REG, input C, E, R, D);
 	always @(negedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -289,7 +289,7 @@ module SB_DFFNER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFNESS (output `SB_DFF_REG, input C, E, S, D);
 	always @(negedge C)
 		if (E) begin
 			if (S)
@@ -299,7 +299,7 @@ module SB_DFFNESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
 		end
 endmodule
 
-module SB_DFFNES ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFNES (output `SB_DFF_REG, input C, E, S, D);
 	always @(negedge C, posedge S)
 		if (S)
 			Q <= 1;
@@ -310,7 +310,7 @@ endmodule
 // SiliconBlue RAM Cells
 
 module SB_RAM40_4K (
-	(* abc_flop_q *) output [15:0] RDATA,
+	output [15:0] RDATA,
 	input         RCLK, RCLKE, RE,
 	input  [10:0] RADDR,
 	input         WCLK, WCLKE, WE,
@@ -478,7 +478,7 @@ module SB_RAM40_4K (
 endmodule
 
 module SB_RAM40_4KNR (
-	(* abc_flop_q *) output [15:0] RDATA,
+	output [15:0] RDATA,
 	input         RCLKN, RCLKE, RE,
 	input  [10:0] RADDR,
 	input         WCLK, WCLKE, WE,
@@ -543,7 +543,7 @@ module SB_RAM40_4KNR (
 endmodule
 
 module SB_RAM40_4KNW (
-	(* abc_flop_q *) output [15:0] RDATA,
+	output [15:0] RDATA,
 	input         RCLK, RCLKE, RE,
 	input  [10:0] RADDR,
 	input         WCLKN, WCLKE, WE,
@@ -608,7 +608,7 @@ module SB_RAM40_4KNW (
 endmodule
 
 module SB_RAM40_4KNRNW (
-	(* abc_flop_q *) output [15:0] RDATA,
+	output [15:0] RDATA,
 	input         RCLKN, RCLKE, RE,
 	input  [10:0] RADDR,
 	input         WCLKN, WCLKE, WE,
@@ -902,7 +902,7 @@ module SB_SPRAM256KA (
 	input [15:0] DATAIN,
 	input [3:0] MASKWREN,
 	input WREN, CHIPSELECT, CLOCK, STANDBY, SLEEP, POWEROFF,
-	(* abc_flop_q *) output reg [15:0] DATAOUT
+	output reg [15:0] DATAOUT
 );
 `ifndef BLACKBOX
 `ifndef EQUIV
-- 
cgit v1.2.3


From 97d265637505a239e3d328a3ee7e26c6fd5d6744 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 14 Jun 2019 12:00:02 -0700
Subject: Resolve comments from @daveshah1

---
 techlibs/ice40/synth_ice40.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index a60829764..d8e9786c5 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -332,7 +332,7 @@ struct SynthIce40Pass : public ScriptPass
 			}
 			if (!noabc) {
 				if (abc == "abc9")
-					run(abc + stringf(" -dress -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
+					run(abc + stringf(" -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
 				else
 					run(abc + " -dress -lut 4", "(skip if -noabc)");
 			}
-- 
cgit v1.2.3


From 0d888ee7edada1349b76360f85124a81d0766cd2 Mon Sep 17 00:00:00 2001
From: acw1251 <acwright@mit.edu>
Date: Wed, 19 Jun 2019 15:27:04 -0400
Subject: Fixed the help summary line for a few commands

---
 techlibs/ice40/ice40_unlut.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/ice40_unlut.cc b/techlibs/ice40/ice40_unlut.cc
index 2428a8e78..bec3c4c96 100644
--- a/techlibs/ice40/ice40_unlut.cc
+++ b/techlibs/ice40/ice40_unlut.cc
@@ -74,7 +74,7 @@ static void run_ice40_unlut(Module *module)
 }
 
 struct Ice40UnlutPass : public Pass {
-	Ice40UnlutPass() : Pass("ice40_unlut", "iCE40: perform simple optimizations") { }
+	Ice40UnlutPass() : Pass("ice40_unlut", "iCE40: transform SBLUT4 cells to $lut cells") { }
 	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
-- 
cgit v1.2.3


From ce29ede801e4cbfa430c56833f3f0bf98b18063f Mon Sep 17 00:00:00 2001
From: acw1251 <acwright@mit.edu>
Date: Wed, 19 Jun 2019 16:39:46 -0400
Subject: Fixed small typo in ice40_unlut help summary

---
 techlibs/ice40/ice40_unlut.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/ice40_unlut.cc b/techlibs/ice40/ice40_unlut.cc
index bec3c4c96..d16e6e6a3 100644
--- a/techlibs/ice40/ice40_unlut.cc
+++ b/techlibs/ice40/ice40_unlut.cc
@@ -74,7 +74,7 @@ static void run_ice40_unlut(Module *module)
 }
 
 struct Ice40UnlutPass : public Pass {
-	Ice40UnlutPass() : Pass("ice40_unlut", "iCE40: transform SBLUT4 cells to $lut cells") { }
+	Ice40UnlutPass() : Pass("ice40_unlut", "iCE40: transform SB_LUT4 cells to $lut cells") { }
 	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
-- 
cgit v1.2.3


From 63182ed57d3a62c8c5e316cea48216024afb38a4 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 22 Jun 2019 14:27:41 -0700
Subject: Fix and cleanup ice40 boxes for carry in/out

---
 techlibs/ice40/abc_hx.box  | 112 ++++-----------------------------------------
 techlibs/ice40/abc_lp.box  | 110 +++-----------------------------------------
 techlibs/ice40/abc_u.box   | 112 ++++-----------------------------------------
 techlibs/ice40/cells_sim.v |   4 +-
 4 files changed, 25 insertions(+), 313 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/abc_hx.box b/techlibs/ice40/abc_hx.box
index a0655643d..f8e12b527 100644
--- a/techlibs/ice40/abc_hx.box
+++ b/techlibs/ice40/abc_hx.box
@@ -1,113 +1,17 @@
 # From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_hx8k.txt
 
 # NB: Inputs/Outputs must be ordered alphabetically
+#     (with exceptions for carry in/out)
 
-# Inputs: C D
-# Outputs: Q
-SB_DFF 1 0 2 1
-- -
-
-# Inputs: C D E
-# Outputs: Q
-SB_DFFE 2 0 3 1
-- - -
-
-# Inputs: C D R
-# Outputs: Q
-SB_DFFSR 3 0 3 1
-- - -
-
-# Inputs: C D R
-# Outputs: Q
-SB_DFFR 4 0 3 1
-- - -
-
-# Inputs: C D S
-# Outputs: Q
-SB_DFFSS 5 0 3 1
-- - -
-
-# Inputs: C D S
-# Outputs: Q
-SB_DFFS 6 0 3 1
-- - -
-
-# Inputs: C D E R
-# Outputs: Q
-SB_DFFESR 7 0 4 1
-- - - -
-
-# Inputs: C D E R
-# Outputs: Q
-SB_DFFER 8 0 4 1
-- - - -
-
-# Inputs: C D E S
-# Outputs: Q
-SB_DFFESS 9 0 4 1
-- - - -
-
-# Inputs: C D E S
-# Outputs: Q
-SB_DFFES 10 0 4 1
-- - - -
-
-# Inputs: C D
-# Outputs: Q
-SB_DFFN 11 0 2 1
-- -
-
-# Inputs: C D E
-# Outputs: Q
-SB_DFFNE 12 0 3 1
-- - -
-
-# Inputs: C D R
-# Outputs: Q
-SB_DFFNSR 13 0 3 1
-- - -
-
-# Inputs: C D R
-# Outputs: Q
-SB_DFFNR 14 0 3 1
-- - -
-
-# Inputs: C D S
-# Outputs: Q
-SB_DFFNSS 15 0 3 1
-- - -
-
-# Inputs: C D S
-# Outputs: Q
-SB_DFFNS 16 0 3 1
-- - -
-
-# Inputs: C D E R
-# Outputs: Q
-SB_DFFNESR 17 0 4 1
-- - - -
-
-# Inputs: C D E R
-# Outputs: Q
-SB_DFFNER 18 0 4 1
-- - - -
-
-# Inputs: C D E S
-# Outputs: Q
-SB_DFFNESS 19 0 4 1
-- - - -
-
-# Inputs: C D E S
-# Outputs: Q
-SB_DFFNES 20 0 4 1
-- - - -
-
-# Inputs: CI I0 I1
+# Inputs: I0 I1 CI
 # Outputs: CO
-SB_CARRY 21 1 3 1
-126 259 231
+#   (NB: carry chain input/output must be last
+#        input/output and have been moved there
+#        overriding the alphabetical ordering)
+SB_CARRY 1 1 3 1
+259 231 126
 
 # Inputs: I0 I1 I2 I3
 # Outputs: O
-SB_LUT4 22 1 4 1
+SB_LUT4 2 1 4 1
 449 400 379 316
diff --git a/techlibs/ice40/abc_lp.box b/techlibs/ice40/abc_lp.box
index eb1cd0937..fbe4c56e6 100644
--- a/techlibs/ice40/abc_lp.box
+++ b/techlibs/ice40/abc_lp.box
@@ -1,113 +1,17 @@
 # From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_lp8k.txt
 
 # NB: Inputs/Outputs must be ordered alphabetically
-
-# Inputs: C D
-# Outputs: Q
-SB_DFF 1 0 2 1
-- -
-
-# Inputs: C D E
-# Outputs: Q
-SB_DFFE 2 0 3 1
-- - -
-
-# Inputs: C D R
-# Outputs: Q
-SB_DFFSR 3 0 3 1
-- - -
-
-# Inputs: C D R
-# Outputs: Q
-SB_DFFR 4 0 3 1
-- - -
-
-# Inputs: C D S
-# Outputs: Q
-SB_DFFSS 5 0 3 1
-- - -
-
-# Inputs: C D S
-# Outputs: Q
-SB_DFFS 6 0 3 1
-- - -
-
-# Inputs: C D E R
-# Outputs: Q
-SB_DFFESR 7 0 4 1
-- - - -
-
-# Inputs: C D E R
-# Outputs: Q
-SB_DFFER 8 0 4 1
-- - - -
-
-# Inputs: C D E S
-# Outputs: Q
-SB_DFFESS 9 0 4 1
-- - - -
-
-# Inputs: C D E S
-# Outputs: Q
-SB_DFFES 10 0 4 1
-- - - -
-
-# Inputs: C D
-# Outputs: Q
-SB_DFFN 11 0 2 1
-- -
-
-# Inputs: C D E
-# Outputs: Q
-SB_DFFNE 12 0 3 1
-- - -
-
-# Inputs: C D R
-# Outputs: Q
-SB_DFFNSR 13 0 3 1
-- - -
-
-# Inputs: C D R
-# Outputs: Q
-SB_DFFNR 14 0 3 1
-- - -
-
-# Inputs: C D S
-# Outputs: Q
-SB_DFFNSS 15 0 3 1
-- - -
-
-# Inputs: C D S
-# Outputs: Q
-SB_DFFNS 16 0 3 1
-- - -
-
-# Inputs: C D E R
-# Outputs: Q
-SB_DFFNESR 17 0 4 1
-- - - -
-
-# Inputs: C D E R
-# Outputs: Q
-SB_DFFNER 18 0 4 1
-- - - -
-
-# Inputs: C D E S
-# Outputs: Q
-SB_DFFNESS 19 0 4 1
-- - - -
-
-# Inputs: C D E S
-# Outputs: Q
-SB_DFFNES 20 0 4 1
-- - - -
+#     (with exceptions for carry in/out)
 
 # Inputs: CI I0 I1
 # Outputs: CO
-SB_CARRY 21 1 3 1
-186 675 609
+#   (NB: carry chain input/output must be last
+#        input/output and have been moved there
+#        overriding the alphabetical ordering)
+SB_CARRY 1 1 3 1
+675 609 186 
 
 # Inputs: I0 I1 I2 I3
 # Outputs: O
-SB_LUT4 22 1 4 1
+SB_LUT4 2 1 4 1
 661 589 558 465
diff --git a/techlibs/ice40/abc_u.box b/techlibs/ice40/abc_u.box
index 3b5834e40..f44deabc4 100644
--- a/techlibs/ice40/abc_u.box
+++ b/techlibs/ice40/abc_u.box
@@ -1,113 +1,17 @@
 # From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_up5k.txt
 
 # NB: Inputs/Outputs must be ordered alphabetically
+#     (with exceptions for carry in/out)
 
-# Inputs: C D
-# Outputs: Q
-SB_DFF 1 0 2 1
-- -
-
-# Inputs: C D E
-# Outputs: Q
-SB_DFFE 2 0 3 1
-- - -
-
-# Inputs: C D R
-# Outputs: Q
-SB_DFFSR 3 0 3 1
-- - -
-
-# Inputs: C D R
-# Outputs: Q
-SB_DFFR 4 0 3 1
-- - -
-
-# Inputs: C D S
-# Outputs: Q
-SB_DFFSS 5 0 3 1
-- - -
-
-# Inputs: C D S
-# Outputs: Q
-SB_DFFS 6 0 3 1
-- - -
-
-# Inputs: C D E R
-# Outputs: Q
-SB_DFFESR 7 0 4 1
-- - - -
-
-# Inputs: C D E R
-# Outputs: Q
-SB_DFFER 8 0 4 1
-- - - -
-
-# Inputs: C D E S
-# Outputs: Q
-SB_DFFESS 9 0 4 1
-- - - -
-
-# Inputs: C D E S
-# Outputs: Q
-SB_DFFES 10 0 4 1
-- - - -
-
-# Inputs: C D
-# Outputs: Q
-SB_DFFN 11 0 2 1
-- -
-
-# Inputs: C D E
-# Outputs: Q
-SB_DFFNE 12 0 3 1
-- - -
-
-# Inputs: C D R
-# Outputs: Q
-SB_DFFNSR 13 0 3 1
-- - -
-
-# Inputs: C D R
-# Outputs: Q
-SB_DFFNR 14 0 3 1
-- - -
-
-# Inputs: C D S
-# Outputs: Q
-SB_DFFNSS 15 0 3 1
-- - -
-
-# Inputs: C D S
-# Outputs: Q
-SB_DFFNS 16 0 3 1
-- - -
-
-# Inputs: C D E R
-# Outputs: Q
-SB_DFFNESR 17 0 4 1
-- - - -
-
-# Inputs: C D E R
-# Outputs: Q
-SB_DFFNER 18 0 4 1
-- - - -
-
-# Inputs: C D E S
-# Outputs: Q
-SB_DFFNESS 19 0 4 1
-- - - -
-
-# Inputs: C D E S
-# Outputs: Q
-SB_DFFNES 20 0 4 1
-- - - -
-
-# Inputs: CI I0 I1
+# Inputs: I0 I1 CI
 # Outputs: CO
-SB_CARRY 21 1 3 1
-278 675 609
+#   (NB: carry chain input/output must be last
+#        input/output and have been moved there
+#        overriding the alphabetical ordering)
+SB_CARRY 1 1 3 1
+675 609 278
 
 # Inputs: I0 I1 I2 I3
 # Outputs: O
-SB_LUT4 22 1 4 1
+SB_LUT4 2 1 4 1
 1285 1231 1205 874
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 031afa85c..317ae2c1f 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -127,7 +127,7 @@ endmodule
 
 // SiliconBlue Logic Cells
 
-(* abc_box_id = 22, lib_whitebox *)
+(* abc_box_id = 2, lib_whitebox *)
 module SB_LUT4 (output O, input I0, I1, I2, I3);
 	parameter [15:0] LUT_INIT = 0;
 	wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
@@ -136,7 +136,7 @@ module SB_LUT4 (output O, input I0, I1, I2, I3);
 	assign O = I0 ? s1[1] : s1[0];
 endmodule
 
-(* abc_box_id = 21, abc_carry, lib_whitebox *)
+(* abc_box_id = 1, abc_carry, lib_whitebox *)
 module SB_CARRY ((* abc_carry_out *) output CO, input I0, I1, (* abc_carry_in *) input CI);
 	assign CO = (I0 && I1) || ((I0 || I1) && CI);
 endmodule
-- 
cgit v1.2.3


From 0dd850e6552a74430559ed63c3a9a67aa1c84512 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Wed, 26 Jun 2019 11:39:44 +0100
Subject: abc9: Add wire delays to synth_ice40

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ice40/synth_ice40.cc | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index d8e9786c5..a782f00b9 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -331,8 +331,16 @@ struct SynthIce40Pass : public ScriptPass
 				run("techmap -map +/gate2lut.v -D LUT_WIDTH=4", "(only if -noabc)");
 			}
 			if (!noabc) {
-				if (abc == "abc9")
-					run(abc + stringf(" -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
+				if (abc == "abc9") {
+					int wire_delay;
+					if (device_opt == "lp")
+						wire_delay = 400;
+					else if (device_opt == "u")
+						wire_delay = 750;
+					else
+						wire_delay = 250;
+					run(abc + stringf(" -W %d -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", wire_delay, device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
+				}
 				else
 					run(abc + " -dress -lut 4", "(skip if -noabc)");
 			}
-- 
cgit v1.2.3


From 9398921af1d21b47aa291d240a1f274418adcaf2 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 27 Jun 2019 16:07:14 -0700
Subject: Refactor for one "abc_carry" attribute on module

---
 techlibs/ice40/cells_sim.v | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 317ae2c1f..c7e4101e1 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -136,8 +136,8 @@ module SB_LUT4 (output O, input I0, I1, I2, I3);
 	assign O = I0 ? s1[1] : s1[0];
 endmodule
 
-(* abc_box_id = 1, abc_carry, lib_whitebox *)
-module SB_CARRY ((* abc_carry_out *) output CO, input I0, I1, (* abc_carry_in *) input CI);
+(* abc_box_id = 1, abc_carry="CI,CO", lib_whitebox *)
+module SB_CARRY (output CO, input I0, I1, CI);
 	assign CO = (I0 && I1) || ((I0 || I1) && CI);
 endmodule
 
-- 
cgit v1.2.3


From 4daa74679779a45542b36c1f3630bd1fbae9ec7b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 27 Jun 2019 16:11:39 -0700
Subject: Remove noise from ice40/cells_sim.v

---
 techlibs/ice40/cells_sim.v | 5 -----
 1 file changed, 5 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index c7e4101e1..b746ba4e5 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -144,12 +144,8 @@ endmodule
 // Positive Edge SiliconBlue FF Cells
 
 module SB_DFF (output `SB_DFF_REG, input C, D);
-`ifndef _ABC
 	always @(posedge C)
 		Q <= D;
-`else
-    always @* Q <= D;
-`endif
 endmodule
 
 module SB_DFFE (output `SB_DFF_REG, input C, E, D);
@@ -896,7 +892,6 @@ module SB_WARMBOOT (
 );
 endmodule
 
-(* nomem2reg *)
 module SB_SPRAM256KA (
 	input [13:0] ADDRESS,
 	input [15:0] DATAIN,
-- 
cgit v1.2.3


From af8a5ae5fe35d65742eb17db8cd2bacda93e916e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 27 Jun 2019 16:12:20 -0700
Subject: Extraneous newline

---
 techlibs/ice40/synth_ice40.cc | 1 -
 1 file changed, 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index a782f00b9..caef420d4 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -105,7 +105,6 @@ struct SynthIce40Pass : public ScriptPass
 		log("\n");
 	}
 
-
 	string top_opt, blif_file, edif_file, json_file, abc, device_opt;
 	bool nocarry, nodffe, nobram, dsp, flatten, retime, relut, noabc, abc2, vpr;
 	int min_ce_use;
-- 
cgit v1.2.3


From 03705f69f4e7fbd19181297cd4de68472a5f4ba3 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 28 Jun 2019 09:49:01 -0700
Subject: Update synth_ice40 -device doc to be relevant for -abc9 only

---
 techlibs/ice40/synth_ice40.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index caef420d4..9dd5d81f7 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -38,8 +38,8 @@ struct SynthIce40Pass : public ScriptPass
 		log("This command runs synthesis for iCE40 FPGAs.\n");
 		log("\n");
 		log("    -device < hx | lp | u >\n");
-		log("        optimise the synthesis netlist for the specified device.\n");
-		log("        HX is the default target if no device argument specified.\n");
+		log("        relevant only for '-abc9' flow, optimise timing for the specified device.\n");
+		log("        default: hx\n");
 		log("\n");
 		log("    -top <module>\n");
 		log("        use the specified module as top module\n");
-- 
cgit v1.2.3


From 6bbd286e033ed25bb49684316a86d6227dec4cd7 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 10 Jul 2019 12:47:48 -0700
Subject: Error out if -abc9 and -retime specified

---
 techlibs/ice40/synth_ice40.cc | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 9dd5d81f7..2c75215cb 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -227,6 +227,9 @@ struct SynthIce40Pass : public ScriptPass
 		if (device_opt != "hx" && device_opt != "lp" && device_opt !="u")
 			log_cmd_error("Invalid or no device specified: '%s'\n", device_opt.c_str());
 
+		if (abc == "abc9" && retime)
+			log_cmd_error("-retime option not currently compatible with -abc9!\n");
+
 		log_header(design, "Executing SYNTH_ICE40 pass.\n");
 		log_push();
 
@@ -296,7 +299,7 @@ struct SynthIce40Pass : public ScriptPass
 				run("techmap");
 			else
 				run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
-			if ((retime || help_mode) && abc != "abc9")
+			if (retime || help_mode)
 				run(abc + " -dff", "(only if -retime)");
 			run("ice40_opt");
 		}
-- 
cgit v1.2.3


From a8c5f7f41ec0c829c29ae425b0074eb33fa2a30c Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Thu, 11 Jul 2019 10:46:45 +0000
Subject: synth_ice40: fix help text typo. NFC.

---
 techlibs/ice40/synth_ice40.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 2c75215cb..78c62213e 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -78,7 +78,7 @@ struct SynthIce40Pass : public ScriptPass
 		log("\n");
 		log("    -dffe_min_ce_use <min_ce_use>\n");
 		log("        do not use SB_DFFE* cells if the resulting CE line would go to less\n");
-		log("        than min_ce_use SB_DFFE*in output netlist\n");
+		log("        than min_ce_use SB_DFFE* in output netlist\n");
 		log("\n");
 		log("    -nobram\n");
 		log("        do not use SB_RAM40_4K* cells in output netlist\n");
-- 
cgit v1.2.3


From b700a4b1c5dd086874c7024edb10674cf3c3a7c4 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Thu, 11 Jul 2019 10:46:30 +0000
Subject: synth_ice40: switch -relut to be always on.

---
 techlibs/ice40/synth_ice40.cc | 14 ++++----------
 1 file changed, 4 insertions(+), 10 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 78c62213e..0474e76e9 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -67,9 +67,6 @@ struct SynthIce40Pass : public ScriptPass
 		log("    -retime\n");
 		log("        run 'abc' with -dff option\n");
 		log("\n");
-		log("    -relut\n");
-		log("        combine LUTs after synthesis\n");
-		log("\n");
 		log("    -nocarry\n");
 		log("        do not use SB_CARRY cells in output netlist\n");
 		log("\n");
@@ -106,7 +103,7 @@ struct SynthIce40Pass : public ScriptPass
 	}
 
 	string top_opt, blif_file, edif_file, json_file, abc, device_opt;
-	bool nocarry, nodffe, nobram, dsp, flatten, retime, relut, noabc, abc2, vpr;
+	bool nocarry, nodffe, nobram, dsp, flatten, retime, noabc, abc2, vpr;
 	int min_ce_use;
 
 	void clear_flags() YS_OVERRIDE
@@ -122,7 +119,6 @@ struct SynthIce40Pass : public ScriptPass
 		dsp = false;
 		flatten = true;
 		retime = false;
-		relut = false;
 		noabc = false;
 		abc2 = false;
 		vpr = false;
@@ -175,7 +171,7 @@ struct SynthIce40Pass : public ScriptPass
 				continue;
 			}
 			if (args[argidx] == "-relut") {
-				relut = true;
+				// removed, opt_lut is always run
 				continue;
 			}
 			if (args[argidx] == "-nocarry") {
@@ -347,10 +343,8 @@ struct SynthIce40Pass : public ScriptPass
 					run(abc + " -dress -lut 4", "(skip if -noabc)");
 			}
 			run("clean");
-			if (relut || help_mode) {
-				run("ice40_unlut", "                            (only if -relut)");
-				run("opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3", "(only if -relut)");
-			}
+			run("ice40_unlut");
+			run("opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3");
 		}
 
 		if (check_label("map_cells"))
-- 
cgit v1.2.3


From fc3d74616f284eaccdc7d105cd77572953602d7f Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 12 Jul 2019 00:50:42 -0700
Subject: Combine SB_CARRY+SB_LUT into one $__ICE40_CARRY_LUT4 box

---
 techlibs/ice40/abc_hx.box | 12 ++++--------
 techlibs/ice40/abc_lp.box | 12 ++++--------
 techlibs/ice40/abc_u.box  | 14 +++++---------
 3 files changed, 13 insertions(+), 25 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/abc_hx.box b/techlibs/ice40/abc_hx.box
index f8e12b527..4b55297dd 100644
--- a/techlibs/ice40/abc_hx.box
+++ b/techlibs/ice40/abc_hx.box
@@ -3,15 +3,11 @@
 # NB: Inputs/Outputs must be ordered alphabetically
 #     (with exceptions for carry in/out)
 
-# Inputs: I0 I1 CI
-# Outputs: CO
+# Inputs: A B CI
+# Outputs: O CO
 #   (NB: carry chain input/output must be last
 #        input/output and have been moved there
 #        overriding the alphabetical ordering)
-SB_CARRY 1 1 3 1
+$__ICE40_CARRY_LUT4 1 1 3 2
+400 379 316
 259 231 126
-
-# Inputs: I0 I1 I2 I3
-# Outputs: O
-SB_LUT4 2 1 4 1
-449 400 379 316
diff --git a/techlibs/ice40/abc_lp.box b/techlibs/ice40/abc_lp.box
index fbe4c56e6..b85346370 100644
--- a/techlibs/ice40/abc_lp.box
+++ b/techlibs/ice40/abc_lp.box
@@ -3,15 +3,11 @@
 # NB: Inputs/Outputs must be ordered alphabetically
 #     (with exceptions for carry in/out)
 
-# Inputs: CI I0 I1
-# Outputs: CO
+# Inputs: A B CI
+# Outputs: O CO
 #   (NB: carry chain input/output must be last
 #        input/output and have been moved there
 #        overriding the alphabetical ordering)
-SB_CARRY 1 1 3 1
+$__ICE40_CARRY_LUT4 1 1 3 2
+589 558 465
 675 609 186 
-
-# Inputs: I0 I1 I2 I3
-# Outputs: O
-SB_LUT4 2 1 4 1
-661 589 558 465
diff --git a/techlibs/ice40/abc_u.box b/techlibs/ice40/abc_u.box
index f44deabc4..3a71addef 100644
--- a/techlibs/ice40/abc_u.box
+++ b/techlibs/ice40/abc_u.box
@@ -3,15 +3,11 @@
 # NB: Inputs/Outputs must be ordered alphabetically
 #     (with exceptions for carry in/out)
 
-# Inputs: I0 I1 CI
-# Outputs: CO
+# Inputs: A B CI
+# Outputs: O CO
 #   (NB: carry chain input/output must be last
 #        input/output and have been moved there
 #        overriding the alphabetical ordering)
-SB_CARRY 1 1 3 1
-675 609 278
-
-# Inputs: I0 I1 I2 I3
-# Outputs: O
-SB_LUT4 2 1 4 1
-1285 1231 1205 874
+$__ICE40_CARRY_LUT4 1 1 3 2
+1231 1205 875
+675  609  278
-- 
cgit v1.2.3


From c6e16e1334dcbd8bb556ab566130cc7936f06a69 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 12 Jul 2019 00:51:37 -0700
Subject: _ABC macro will map and unmap to this new box

---
 techlibs/ice40/arith_map.v | 10 ++++++++++
 techlibs/ice40/cells_map.v | 24 ++++++++++++++++++++++++
 2 files changed, 34 insertions(+)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/arith_map.v b/techlibs/ice40/arith_map.v
index 4449fdc1b..6d45e4a6b 100644
--- a/techlibs/ice40/arith_map.v
+++ b/techlibs/ice40/arith_map.v
@@ -44,6 +44,15 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO);
 
 	genvar i;
 	generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
+`ifdef _ABC
+		\$__ICE40_CARRY_LUT4 carry (
+			.A(AA[i]),
+			.B(BB[i]),
+			.CI(C[i]),
+			.CO(CO[i]),
+            .O(Y[i])
+		);
+`else
 		SB_CARRY carry (
 			.I0(AA[i]),
 			.I1(BB[i]),
@@ -63,6 +72,7 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO);
 			.I3(C[i]),
 			.O(Y[i])
 		);
+`endif
 	end endgenerate
 
 	assign X = AA ^ BB;
diff --git a/techlibs/ice40/cells_map.v b/techlibs/ice40/cells_map.v
index 759549e30..5dca63e19 100644
--- a/techlibs/ice40/cells_map.v
+++ b/techlibs/ice40/cells_map.v
@@ -61,3 +61,27 @@ module \$lut (A, Y);
   endgenerate
 endmodule
 `endif
+
+`ifdef _ABC
+module \$__ICE40_CARRY_LUT4 (output CO, O, input A, B, CI);
+  SB_CARRY carry (
+    .I0(A),
+    .I1(B),
+    .CI(CI),
+    .CO(CO)
+  );
+  SB_LUT4 #(
+    //         I0: 1010 1010 1010 1010
+    //         I1: 1100 1100 1100 1100
+    //         I2: 1111 0000 1111 0000
+    //         I3: 1111 1111 0000 0000
+    .LUT_INIT(16'b 0110_1001_1001_0110)
+  ) adder (
+    .I0(1'b0),
+    .I1(A),
+    .I2(B),
+    .I3(CI),
+    .O(O)
+  );
+endmodule
+`endif
-- 
cgit v1.2.3


From a79ff2501e7b73b4af958d23d247951b107bb054 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 12 Jul 2019 00:52:19 -0700
Subject: Add new box to cells_sim.v

---
 techlibs/ice40/cells_sim.v | 27 +++++++++++++++++++++++++--
 1 file changed, 25 insertions(+), 2 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index b746ba4e5..cf36f5cfb 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -127,7 +127,7 @@ endmodule
 
 // SiliconBlue Logic Cells
 
-(* abc_box_id = 2, lib_whitebox *)
+(* lib_whitebox *)
 module SB_LUT4 (output O, input I0, I1, I2, I3);
 	parameter [15:0] LUT_INIT = 0;
 	wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
@@ -136,11 +136,34 @@ module SB_LUT4 (output O, input I0, I1, I2, I3);
 	assign O = I0 ? s1[1] : s1[0];
 endmodule
 
-(* abc_box_id = 1, abc_carry="CI,CO", lib_whitebox *)
+(* lib_whitebox *)
 module SB_CARRY (output CO, input I0, I1, CI);
 	assign CO = (I0 && I1) || ((I0 || I1) && CI);
 endmodule
 
+(* abc_box_id = 1, abc_carry="CI,CO", lib_whitebox *)
+module \$__ICE40_CARRY_LUT4 (output CO, O, input A, B, CI);
+	SB_CARRY carry (
+		.I0(A),
+		.I1(B),
+		.CI(CI),
+		.CO(CO)
+	);
+	SB_LUT4 #(
+		//         I0: 1010 1010 1010 1010
+		//         I1: 1100 1100 1100 1100
+		//         I2: 1111 0000 1111 0000
+		//         I3: 1111 1111 0000 0000
+		.LUT_INIT(16'b 0110_1001_1001_0110)
+	) adder (
+		.I0(1'b0),
+		.I1(A),
+		.I2(B),
+		.I3(CI),
+		.O(O)
+	);
+endmodule
+
 // Positive Edge SiliconBlue FF Cells
 
 module SB_DFF (output `SB_DFF_REG, input C, D);
-- 
cgit v1.2.3


From 0f5bddcd792ed2da2b9a3eb12e775537f394e771 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 12 Jul 2019 00:52:31 -0700
Subject: ice40_opt to handle this box and opt back to SB_LUT4

---
 techlibs/ice40/ice40_opt.cc | 48 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index f528607d6..b22fc83fe 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -83,6 +83,54 @@ static void run_ice40_opts(Module *module)
 			}
 			continue;
 		}
+
+		if (cell->type == "$__ICE40_CARRY_LUT4")
+		{
+			SigSpec non_const_inputs, replacement_output;
+			int count_zeros = 0, count_ones = 0;
+
+			SigBit inbit[3] = {
+				cell->getPort("\\A"),
+				cell->getPort("\\B"),
+				cell->getPort("\\CI")
+			};
+			for (int i = 0; i < 3; i++)
+				if (inbit[i].wire == nullptr) {
+					if (inbit[i] == State::S1)
+						count_ones++;
+					else
+						count_zeros++;
+				} else
+					non_const_inputs.append(inbit[i]);
+
+			if (count_zeros >= 2)
+				replacement_output = State::S0;
+			else if (count_ones >= 2)
+				replacement_output = State::S1;
+			else if (GetSize(non_const_inputs) == 1)
+				replacement_output = non_const_inputs;
+
+			if (GetSize(replacement_output)) {
+				optimized_co.insert(sigmap(cell->getPort("\\CO")[0]));
+				module->connect(cell->getPort("\\CO")[0], replacement_output);
+				module->design->scratchpad_set_bool("opt.did_something", true);
+				log("Optimized SB_CARRY from $__ICE40_CARRY_LUT4 cell (leaving behind SB_LUT4) %s.%s: CO=%s\n",
+						log_id(module), log_id(cell), log_signal(replacement_output));
+				cell->type = "\\SB_LUT4";
+				sb_lut_cells.push_back(cell);
+				cell->setPort("\\I0", RTLIL::S0);
+				cell->setPort("\\I1", inbit[0]);
+				cell->setPort("\\I2", inbit[1]);
+				cell->setPort("\\I3", inbit[2]);
+				cell->unsetPort("\\A");
+				cell->unsetPort("\\B");
+				cell->unsetPort("\\CI");
+				cell->unsetPort("\\CO");
+				cell->setParam("\\LUT_INIT", std::string("0110100110010110"));
+				sb_lut_cells.push_back(cell);
+			}
+			continue;
+		}
 	}
 
 	for (auto cell : sb_lut_cells)
-- 
cgit v1.2.3


From 62ac5ebd02e18add18a11f4c19002f4059b091b7 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 12 Jul 2019 00:53:01 -0700
Subject: Map to and from this box if -abc9

---
 techlibs/ice40/synth_ice40.cc | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 2c75215cb..59f6d1863 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -242,7 +242,7 @@ struct SynthIce40Pass : public ScriptPass
 	{
 		if (check_label("begin"))
 		{
-			run("read_verilog -lib -D_ABC +/ice40/cells_sim.v");
+			run("read_verilog -icells -lib -D_ABC +/ice40/cells_sim.v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 			run("proc");
 		}
@@ -298,7 +298,7 @@ struct SynthIce40Pass : public ScriptPass
 			if (nocarry)
 				run("techmap");
 			else
-				run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
+				run("techmap -map +/techmap.v -map +/ice40/arith_map.v" + std::string(abc == "abc9" ? " -D _ABC" : ""));
 			if (retime || help_mode)
 				run(abc + " -dff", "(only if -retime)");
 			run("ice40_opt");
@@ -342,6 +342,7 @@ struct SynthIce40Pass : public ScriptPass
 					else
 						wire_delay = 250;
 					run(abc + stringf(" -W %d -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", wire_delay, device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
+					run("techmap -D NO_LUT -D _ABC -map +/ice40/cells_map.v");
 				}
 				else
 					run(abc + " -dress -lut 4", "(skip if -noabc)");
-- 
cgit v1.2.3


From 4de03bd5e6cd72b3eb2a70d5735e7526d7a6f8a8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 12 Jul 2019 01:08:48 -0700
Subject: Remove double push

---
 techlibs/ice40/ice40_opt.cc | 1 -
 1 file changed, 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index b22fc83fe..4e50b250e 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -117,7 +117,6 @@ static void run_ice40_opts(Module *module)
 				log("Optimized SB_CARRY from $__ICE40_CARRY_LUT4 cell (leaving behind SB_LUT4) %s.%s: CO=%s\n",
 						log_id(module), log_id(cell), log_signal(replacement_output));
 				cell->type = "\\SB_LUT4";
-				sb_lut_cells.push_back(cell);
 				cell->setPort("\\I0", RTLIL::S0);
 				cell->setPort("\\I1", inbit[0]);
 				cell->setPort("\\I2", inbit[1]);
-- 
cgit v1.2.3


From e0e5d7d68eee0d1a83b048d9d9fde94673ff5673 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 12 Jul 2019 01:15:22 -0700
Subject: Fix spacing

---
 techlibs/ice40/arith_map.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/arith_map.v b/techlibs/ice40/arith_map.v
index 6d45e4a6b..abba18c37 100644
--- a/techlibs/ice40/arith_map.v
+++ b/techlibs/ice40/arith_map.v
@@ -50,7 +50,7 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO);
 			.B(BB[i]),
 			.CI(C[i]),
 			.CO(CO[i]),
-            .O(Y[i])
+			.O(Y[i])
 		);
 `else
 		SB_CARRY carry (
-- 
cgit v1.2.3


From 28274dfb09fb48637f82949ce601a417eb3d0b82 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 12 Jul 2019 01:17:53 -0700
Subject: Off by one

---
 techlibs/ice40/abc_u.box | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/abc_u.box b/techlibs/ice40/abc_u.box
index 3a71addef..95c2c3d81 100644
--- a/techlibs/ice40/abc_u.box
+++ b/techlibs/ice40/abc_u.box
@@ -9,5 +9,5 @@
 #        input/output and have been moved there
 #        overriding the alphabetical ordering)
 $__ICE40_CARRY_LUT4 1 1 3 2
-1231 1205 875
+1231 1205 874
 675  609  278
-- 
cgit v1.2.3


From 7a912f22b2c3976d72a25ffd605a1cf598b67983 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 12 Jul 2019 01:32:10 -0700
Subject: Use Const::from_string() not its constructor...

---
 techlibs/ice40/ice40_opt.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index 4e50b250e..67e8771b4 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -125,7 +125,7 @@ static void run_ice40_opts(Module *module)
 				cell->unsetPort("\\B");
 				cell->unsetPort("\\CI");
 				cell->unsetPort("\\CO");
-				cell->setParam("\\LUT_INIT", std::string("0110100110010110"));
+				cell->setParam("\\LUT_INIT", RTLIL::Const::from_string("0110100110010110"));
 				sb_lut_cells.push_back(cell);
 			}
 			continue;
-- 
cgit v1.2.3


From d032198facc05634bd617328e1865e7f0d8d953c Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 13 Jul 2019 01:11:00 -0700
Subject: ice40_opt to $__ICE40_CARRY_LUT4 into $lut not SB_LUT

---
 techlibs/ice40/ice40_opt.cc | 16 +++++++---------
 1 file changed, 7 insertions(+), 9 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index 67e8771b4..38910dffa 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -114,19 +114,17 @@ static void run_ice40_opts(Module *module)
 				optimized_co.insert(sigmap(cell->getPort("\\CO")[0]));
 				module->connect(cell->getPort("\\CO")[0], replacement_output);
 				module->design->scratchpad_set_bool("opt.did_something", true);
-				log("Optimized SB_CARRY from $__ICE40_CARRY_LUT4 cell (leaving behind SB_LUT4) %s.%s: CO=%s\n",
+				log("Optimized $__ICE40_CARRY_LUT4 cell into $lut (without SB_CARRY) %s.%s: CO=%s\n",
 						log_id(module), log_id(cell), log_signal(replacement_output));
-				cell->type = "\\SB_LUT4";
-				cell->setPort("\\I0", RTLIL::S0);
-				cell->setPort("\\I1", inbit[0]);
-				cell->setPort("\\I2", inbit[1]);
-				cell->setPort("\\I3", inbit[2]);
-				cell->unsetPort("\\A");
+				cell->type = "$lut";
+				cell->setPort("\\A", { RTLIL::S0, inbit[0], inbit[1], inbit[2] });
+				cell->setPort("\\Y", cell->getPort("\\O"));
 				cell->unsetPort("\\B");
 				cell->unsetPort("\\CI");
 				cell->unsetPort("\\CO");
-				cell->setParam("\\LUT_INIT", RTLIL::Const::from_string("0110100110010110"));
-				sb_lut_cells.push_back(cell);
+				cell->unsetPort("\\O");
+				cell->setParam("\\LUT", RTLIL::Const::from_string("0110100110010110"));
+				cell->setParam("\\WIDTH", 4);
 			}
 			continue;
 		}
-- 
cgit v1.2.3


From 5fb27c071bb072644dbb38cf8a516628c2afe15b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 15 Jul 2019 12:03:51 -0700
Subject: $__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark

---
 techlibs/ice40/abc_hx.box   | 2 +-
 techlibs/ice40/abc_lp.box   | 2 +-
 techlibs/ice40/abc_u.box    | 2 +-
 techlibs/ice40/arith_map.v  | 2 +-
 techlibs/ice40/cells_map.v  | 2 +-
 techlibs/ice40/cells_sim.v  | 2 +-
 techlibs/ice40/ice40_opt.cc | 4 ++--
 7 files changed, 8 insertions(+), 8 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/abc_hx.box b/techlibs/ice40/abc_hx.box
index 4b55297dd..c0ea742e2 100644
--- a/techlibs/ice40/abc_hx.box
+++ b/techlibs/ice40/abc_hx.box
@@ -8,6 +8,6 @@
 #   (NB: carry chain input/output must be last
 #        input/output and have been moved there
 #        overriding the alphabetical ordering)
-$__ICE40_CARRY_LUT4 1 1 3 2
+$__ICE40_FULL_ADDER 1 1 3 2
 400 379 316
 259 231 126
diff --git a/techlibs/ice40/abc_lp.box b/techlibs/ice40/abc_lp.box
index b85346370..d73b6d649 100644
--- a/techlibs/ice40/abc_lp.box
+++ b/techlibs/ice40/abc_lp.box
@@ -8,6 +8,6 @@
 #   (NB: carry chain input/output must be last
 #        input/output and have been moved there
 #        overriding the alphabetical ordering)
-$__ICE40_CARRY_LUT4 1 1 3 2
+$__ICE40_FULL_ADDER 1 1 3 2
 589 558 465
 675 609 186 
diff --git a/techlibs/ice40/abc_u.box b/techlibs/ice40/abc_u.box
index 95c2c3d81..42d666051 100644
--- a/techlibs/ice40/abc_u.box
+++ b/techlibs/ice40/abc_u.box
@@ -8,6 +8,6 @@
 #   (NB: carry chain input/output must be last
 #        input/output and have been moved there
 #        overriding the alphabetical ordering)
-$__ICE40_CARRY_LUT4 1 1 3 2
+$__ICE40_FULL_ADDER 1 1 3 2
 1231 1205 874
 675  609  278
diff --git a/techlibs/ice40/arith_map.v b/techlibs/ice40/arith_map.v
index abba18c37..fe83a8e38 100644
--- a/techlibs/ice40/arith_map.v
+++ b/techlibs/ice40/arith_map.v
@@ -45,7 +45,7 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO);
 	genvar i;
 	generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
 `ifdef _ABC
-		\$__ICE40_CARRY_LUT4 carry (
+		\$__ICE40_FULL_ADDER carry (
 			.A(AA[i]),
 			.B(BB[i]),
 			.CI(C[i]),
diff --git a/techlibs/ice40/cells_map.v b/techlibs/ice40/cells_map.v
index 5dca63e19..b4b831165 100644
--- a/techlibs/ice40/cells_map.v
+++ b/techlibs/ice40/cells_map.v
@@ -63,7 +63,7 @@ endmodule
 `endif
 
 `ifdef _ABC
-module \$__ICE40_CARRY_LUT4 (output CO, O, input A, B, CI);
+module \$__ICE40_FULL_ADDER (output CO, O, input A, B, CI);
   SB_CARRY carry (
     .I0(A),
     .I1(B),
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index cf36f5cfb..609facc93 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -142,7 +142,7 @@ module SB_CARRY (output CO, input I0, I1, CI);
 endmodule
 
 (* abc_box_id = 1, abc_carry="CI,CO", lib_whitebox *)
-module \$__ICE40_CARRY_LUT4 (output CO, O, input A, B, CI);
+module \$__ICE40_FULL_ADDER (output CO, O, input A, B, CI);
 	SB_CARRY carry (
 		.I0(A),
 		.I1(B),
diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index 38910dffa..e492454fb 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -84,7 +84,7 @@ static void run_ice40_opts(Module *module)
 			continue;
 		}
 
-		if (cell->type == "$__ICE40_CARRY_LUT4")
+		if (cell->type == "$__ICE40_FULL_ADDER")
 		{
 			SigSpec non_const_inputs, replacement_output;
 			int count_zeros = 0, count_ones = 0;
@@ -114,7 +114,7 @@ static void run_ice40_opts(Module *module)
 				optimized_co.insert(sigmap(cell->getPort("\\CO")[0]));
 				module->connect(cell->getPort("\\CO")[0], replacement_output);
 				module->design->scratchpad_set_bool("opt.did_something", true);
-				log("Optimized $__ICE40_CARRY_LUT4 cell into $lut (without SB_CARRY) %s.%s: CO=%s\n",
+				log("Optimized $__ICE40_FULL_ADDER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n",
 						log_id(module), log_id(cell), log_signal(replacement_output));
 				cell->type = "$lut";
 				cell->setPort("\\A", { RTLIL::S0, inbit[0], inbit[1], inbit[2] });
-- 
cgit v1.2.3


From ba099bfe9befccc42df99d2930fdbc686152187c Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Thu, 11 Jul 2019 10:56:59 +0000
Subject: synth_{ice40,ecp5}: more sensible pass label naming.

---
 techlibs/ice40/synth_ice40.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 0474e76e9..1a20f7049 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -275,14 +275,14 @@ struct SynthIce40Pass : public ScriptPass
 			run("opt_clean");
 		}
 
-		if (!nobram && check_label("bram", "(skip if -nobram)"))
+		if (!nobram && check_label("map_bram", "(skip if -nobram)"))
 		{
 			run("memory_bram -rules +/ice40/brams.txt");
 			run("techmap -map +/ice40/brams_map.v");
 			run("ice40_braminit");
 		}
 
-		if (check_label("map"))
+		if (check_label("map_ffram"))
 		{
 			run("opt -fast -mux_undef -undriven -fine");
 			run("memory_map");
-- 
cgit v1.2.3


From f28e38de9994151ea4e22608441dbc9e116d7b8c Mon Sep 17 00:00:00 2001
From: Sylvain Munaut <tnt@246tNt.com>
Date: Tue, 16 Jul 2019 23:57:15 +0200
Subject: ice40: Adapt the relut process passes to the new $lut <=> SB_LUT4
 port map

The new mapping introduced in 437fec0d88b4a2ad172edf0d1a861a38845f3b1d
needed matching adaptation when converting and optimizing LUTs during
the relut process

Fixes #1187

(Diagnosis of the issue by @daveshah1 on IRC)

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
---
 techlibs/ice40/ice40_unlut.cc | 6 +++---
 techlibs/ice40/synth_ice40.cc | 2 +-
 2 files changed, 4 insertions(+), 4 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/ice40_unlut.cc b/techlibs/ice40/ice40_unlut.cc
index d16e6e6a3..f3f70ac1f 100644
--- a/techlibs/ice40/ice40_unlut.cc
+++ b/techlibs/ice40/ice40_unlut.cc
@@ -56,10 +56,10 @@ static void run_ice40_unlut(Module *module)
 			cell->unsetParam("\\LUT_INIT");
 
 			cell->setPort("\\A", SigSpec({
-				get_bit_or_zero(cell->getPort("\\I3")),
-				get_bit_or_zero(cell->getPort("\\I2")),
+				get_bit_or_zero(cell->getPort("\\I0")),
 				get_bit_or_zero(cell->getPort("\\I1")),
-				get_bit_or_zero(cell->getPort("\\I0"))
+				get_bit_or_zero(cell->getPort("\\I2")),
+				get_bit_or_zero(cell->getPort("\\I3"))
 			}));
 			cell->setPort("\\Y", cell->getPort("\\O")[0]);
 			cell->unsetPort("\\I0");
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index b3d30791a..78ac5ea13 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -345,7 +345,7 @@ struct SynthIce40Pass : public ScriptPass
 			}
 			run("clean");
 			run("ice40_unlut");
-			run("opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3");
+			run("opt_lut -dlogic SB_CARRY:I0=2:I1=1:CI=0");
 		}
 
 		if (check_label("map_cells"))
-- 
cgit v1.2.3


From f7753720feaf466a089f4b96fca27ed4130b5be8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 19 Jul 2019 08:45:35 -0700
Subject: Don't copy ref if exists already

---
 techlibs/ice40/tests/test_dsp_model.sh | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/tests/test_dsp_model.sh b/techlibs/ice40/tests/test_dsp_model.sh
index 1bc0cc688..2d42c23ad 100644
--- a/techlibs/ice40/tests/test_dsp_model.sh
+++ b/techlibs/ice40/tests/test_dsp_model.sh
@@ -1,7 +1,9 @@
 #!/bin/bash
 set -ex
 sed 's/SB_MAC16/SB_MAC16_UUT/; /SB_MAC16_UUT/,/endmodule/ p; d;' < ../cells_sim.v > test_dsp_model_uut.v
-cat /opt/lscc/iCEcube2.2017.01/verilog/sb_ice_syn.v > test_dsp_model_ref.v
+if [ ! -f "test_dsp_model_ref.v" ]; then
+	cat /opt/lscc/iCEcube2.2017.01/verilog/sb_ice_syn.v > test_dsp_model_ref.v
+fi
 for tb in testbench \
 		testbench_comb_8x8_A testbench_comb_8x8_B testbench_comb_16x16 \
 		testbench_seq_16x16_A testbench_seq_16x16_B
-- 
cgit v1.2.3


From 171cd2ff738cdb8027b9b6efb988bab8744264a9 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 19 Jul 2019 08:52:49 -0700
Subject: Add tests for all combinations of A and B signedness for comb mul

---
 techlibs/ice40/tests/test_dsp_model.sh |   5 +-
 techlibs/ice40/tests/test_dsp_model.v  | 225 +++++++++++++++++++++++++++++++++
 2 files changed, 229 insertions(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/tests/test_dsp_model.sh b/techlibs/ice40/tests/test_dsp_model.sh
index 2d42c23ad..75f95ab29 100644
--- a/techlibs/ice40/tests/test_dsp_model.sh
+++ b/techlibs/ice40/tests/test_dsp_model.sh
@@ -6,7 +6,10 @@ if [ ! -f "test_dsp_model_ref.v" ]; then
 fi
 for tb in testbench \
 		testbench_comb_8x8_A testbench_comb_8x8_B testbench_comb_16x16 \
-		testbench_seq_16x16_A testbench_seq_16x16_B
+		testbench_seq_16x16_A testbench_seq_16x16_B \
+		testbench_comb_8x8_A_signedA testbench_comb_8x8_A_signedB testbench_comb_8x8_A_signedAB \
+		testbench_comb_8x8_B_signedA testbench_comb_8x8_B_signedB testbench_comb_8x8_B_signedAB \
+		testbench_comb_16x16_B_signedA testbench_comb_16x16_B_signedB testbench_comb_16x16_B_signedAB
 do
 	iverilog -s $tb -o test_dsp_model test_dsp_model.v test_dsp_model_uut.v test_dsp_model_ref.v
 	vvp -N ./test_dsp_model
diff --git a/techlibs/ice40/tests/test_dsp_model.v b/techlibs/ice40/tests/test_dsp_model.v
index 594bd4ad3..f4f6858f0 100644
--- a/techlibs/ice40/tests/test_dsp_model.v
+++ b/techlibs/ice40/tests/test_dsp_model.v
@@ -241,6 +241,81 @@ module testbench_comb_8x8_A;
 	) testbench ();
 endmodule
 
+module testbench_comb_8x8_A_signedA;
+	testbench #(
+		.NEG_TRIGGER               (0),
+		.C_REG                     (0),
+		.A_REG                     (0),
+		.B_REG                     (0),
+		.D_REG                     (0),
+		.TOP_8x8_MULT_REG          (0),
+		.BOT_8x8_MULT_REG          (0),
+		.PIPELINE_16x16_MULT_REG1  (0),
+		.PIPELINE_16x16_MULT_REG2  (0),
+		.TOPOUTPUT_SELECT          (2),   // 0=P, 1=Q, 2=8x8, 3=16x16
+		.TOPADDSUB_LOWERINPUT      (0),   // 0=A, 1=8x8, 2=16x16, 3=S-EXT
+		.TOPADDSUB_UPPERINPUT      (0),   // 0=Q, 1=C
+		.TOPADDSUB_CARRYSELECT     (0),   // 0=0, 1=1, 2=ACI, 3=CI
+		.BOTOUTPUT_SELECT          (2),   // 0=R, 1=S, 2=8x8, 3=16x16
+		.BOTADDSUB_LOWERINPUT      (0),   // 0=B, 1=8x8, 2=16x16, 3=S-EXT
+		.BOTADDSUB_UPPERINPUT      (0),   // 0=S, 1=D
+		.BOTADDSUB_CARRYSELECT     (0),   // 0=0, 1=1, 2=ACI, 3=CI
+		.MODE_8x8                  (0),
+		.A_SIGNED                  (1),
+		.B_SIGNED                  (0)
+	) testbench ();
+endmodule
+
+module testbench_comb_8x8_A_signedB;
+	testbench #(
+		.NEG_TRIGGER               (0),
+		.C_REG                     (0),
+		.A_REG                     (0),
+		.B_REG                     (0),
+		.D_REG                     (0),
+		.TOP_8x8_MULT_REG          (0),
+		.BOT_8x8_MULT_REG          (0),
+		.PIPELINE_16x16_MULT_REG1  (0),
+		.PIPELINE_16x16_MULT_REG2  (0),
+		.TOPOUTPUT_SELECT          (2),   // 0=P, 1=Q, 2=8x8, 3=16x16
+		.TOPADDSUB_LOWERINPUT      (0),   // 0=A, 1=8x8, 2=16x16, 3=S-EXT
+		.TOPADDSUB_UPPERINPUT      (0),   // 0=Q, 1=C
+		.TOPADDSUB_CARRYSELECT     (0),   // 0=0, 1=1, 2=ACI, 3=CI
+		.BOTOUTPUT_SELECT          (2),   // 0=R, 1=S, 2=8x8, 3=16x16
+		.BOTADDSUB_LOWERINPUT      (0),   // 0=B, 1=8x8, 2=16x16, 3=S-EXT
+		.BOTADDSUB_UPPERINPUT      (0),   // 0=S, 1=D
+		.BOTADDSUB_CARRYSELECT     (0),   // 0=0, 1=1, 2=ACI, 3=CI
+		.MODE_8x8                  (0),
+		.A_SIGNED                  (0),
+		.B_SIGNED                  (1)
+	) testbench ();
+endmodule
+
+module testbench_comb_8x8_A_signedAB;
+	testbench #(
+		.NEG_TRIGGER               (0),
+		.C_REG                     (0),
+		.A_REG                     (0),
+		.B_REG                     (0),
+		.D_REG                     (0),
+		.TOP_8x8_MULT_REG          (0),
+		.BOT_8x8_MULT_REG          (0),
+		.PIPELINE_16x16_MULT_REG1  (0),
+		.PIPELINE_16x16_MULT_REG2  (0),
+		.TOPOUTPUT_SELECT          (2),   // 0=P, 1=Q, 2=8x8, 3=16x16
+		.TOPADDSUB_LOWERINPUT      (0),   // 0=A, 1=8x8, 2=16x16, 3=S-EXT
+		.TOPADDSUB_UPPERINPUT      (0),   // 0=Q, 1=C
+		.TOPADDSUB_CARRYSELECT     (0),   // 0=0, 1=1, 2=ACI, 3=CI
+		.BOTOUTPUT_SELECT          (2),   // 0=R, 1=S, 2=8x8, 3=16x16
+		.BOTADDSUB_LOWERINPUT      (0),   // 0=B, 1=8x8, 2=16x16, 3=S-EXT
+		.BOTADDSUB_UPPERINPUT      (0),   // 0=S, 1=D
+		.BOTADDSUB_CARRYSELECT     (0),   // 0=0, 1=1, 2=ACI, 3=CI
+		.MODE_8x8                  (0),
+		.A_SIGNED                  (1),
+		.B_SIGNED                  (1)
+	) testbench ();
+endmodule
+
 module testbench_comb_8x8_B;
 	testbench #(
 		.NEG_TRIGGER               (0),
@@ -266,6 +341,81 @@ module testbench_comb_8x8_B;
 	) testbench ();
 endmodule
 
+module testbench_comb_8x8_B_signedA;
+	testbench #(
+		.NEG_TRIGGER               (0),
+		.C_REG                     (0),
+		.A_REG                     (0),
+		.B_REG                     (0),
+		.D_REG                     (0),
+		.TOP_8x8_MULT_REG          (0),
+		.BOT_8x8_MULT_REG          (0),
+		.PIPELINE_16x16_MULT_REG1  (0),
+		.PIPELINE_16x16_MULT_REG2  (0),
+		.TOPOUTPUT_SELECT          (0),   // 0=P, 1=Q, 2=8x8, 3=16x16
+		.TOPADDSUB_LOWERINPUT      (1),   // 0=A, 1=8x8, 2=16x16, 3=S-EXT
+		.TOPADDSUB_UPPERINPUT      (1),   // 0=Q, 1=C
+		.TOPADDSUB_CARRYSELECT     (0),   // 0=0, 1=1, 2=ACI, 3=CI
+		.BOTOUTPUT_SELECT          (0),   // 0=R, 1=S, 2=8x8, 3=16x16
+		.BOTADDSUB_LOWERINPUT      (1),   // 0=B, 1=8x8, 2=16x16, 3=S-EXT
+		.BOTADDSUB_UPPERINPUT      (1),   // 0=S, 1=D
+		.BOTADDSUB_CARRYSELECT     (0),   // 0=0, 1=1, 2=ACI, 3=CI
+		.MODE_8x8                  (0),
+		.A_SIGNED                  (1),
+		.B_SIGNED                  (0)
+	) testbench ();
+endmodule
+
+module testbench_comb_8x8_B_signedB;
+	testbench #(
+		.NEG_TRIGGER               (0),
+		.C_REG                     (0),
+		.A_REG                     (0),
+		.B_REG                     (0),
+		.D_REG                     (0),
+		.TOP_8x8_MULT_REG          (0),
+		.BOT_8x8_MULT_REG          (0),
+		.PIPELINE_16x16_MULT_REG1  (0),
+		.PIPELINE_16x16_MULT_REG2  (0),
+		.TOPOUTPUT_SELECT          (0),   // 0=P, 1=Q, 2=8x8, 3=16x16
+		.TOPADDSUB_LOWERINPUT      (1),   // 0=A, 1=8x8, 2=16x16, 3=S-EXT
+		.TOPADDSUB_UPPERINPUT      (1),   // 0=Q, 1=C
+		.TOPADDSUB_CARRYSELECT     (0),   // 0=0, 1=1, 2=ACI, 3=CI
+		.BOTOUTPUT_SELECT          (0),   // 0=R, 1=S, 2=8x8, 3=16x16
+		.BOTADDSUB_LOWERINPUT      (1),   // 0=B, 1=8x8, 2=16x16, 3=S-EXT
+		.BOTADDSUB_UPPERINPUT      (1),   // 0=S, 1=D
+		.BOTADDSUB_CARRYSELECT     (0),   // 0=0, 1=1, 2=ACI, 3=CI
+		.MODE_8x8                  (0),
+		.A_SIGNED                  (0),
+		.B_SIGNED                  (1)
+	) testbench ();
+endmodule
+
+module testbench_comb_8x8_B_signedAB;
+	testbench #(
+		.NEG_TRIGGER               (0),
+		.C_REG                     (0),
+		.A_REG                     (0),
+		.B_REG                     (0),
+		.D_REG                     (0),
+		.TOP_8x8_MULT_REG          (0),
+		.BOT_8x8_MULT_REG          (0),
+		.PIPELINE_16x16_MULT_REG1  (0),
+		.PIPELINE_16x16_MULT_REG2  (0),
+		.TOPOUTPUT_SELECT          (0),   // 0=P, 1=Q, 2=8x8, 3=16x16
+		.TOPADDSUB_LOWERINPUT      (1),   // 0=A, 1=8x8, 2=16x16, 3=S-EXT
+		.TOPADDSUB_UPPERINPUT      (1),   // 0=Q, 1=C
+		.TOPADDSUB_CARRYSELECT     (0),   // 0=0, 1=1, 2=ACI, 3=CI
+		.BOTOUTPUT_SELECT          (0),   // 0=R, 1=S, 2=8x8, 3=16x16
+		.BOTADDSUB_LOWERINPUT      (1),   // 0=B, 1=8x8, 2=16x16, 3=S-EXT
+		.BOTADDSUB_UPPERINPUT      (1),   // 0=S, 1=D
+		.BOTADDSUB_CARRYSELECT     (0),   // 0=0, 1=1, 2=ACI, 3=CI
+		.MODE_8x8                  (0),
+		.A_SIGNED                  (1),
+		.B_SIGNED                  (1)
+	) testbench ();
+endmodule
+
 module testbench_comb_16x16;
 	testbench #(
 		.NEG_TRIGGER               (0),
@@ -291,6 +441,81 @@ module testbench_comb_16x16;
 	) testbench ();
 endmodule
 
+module testbench_comb_16x16_signedA;
+	testbench #(
+		.NEG_TRIGGER               (0),
+		.C_REG                     (0),
+		.A_REG                     (0),
+		.B_REG                     (0),
+		.D_REG                     (0),
+		.TOP_8x8_MULT_REG          (0),
+		.BOT_8x8_MULT_REG          (0),
+		.PIPELINE_16x16_MULT_REG1  (0),
+		.PIPELINE_16x16_MULT_REG2  (0),
+		.TOPOUTPUT_SELECT          (0),   // 0=P, 1=Q, 2=8x8, 3=16x16
+		.TOPADDSUB_LOWERINPUT      (2),   // 0=A, 1=8x8, 2=16x16, 3=S-EXT
+		.TOPADDSUB_UPPERINPUT      (1),   // 0=Q, 1=C
+		.TOPADDSUB_CARRYSELECT     (2),   // 0=0, 1=1, 2=ACI, 3=CI
+		.BOTOUTPUT_SELECT          (0),   // 0=R, 1=S, 2=8x8, 3=16x16
+		.BOTADDSUB_LOWERINPUT      (2),   // 0=B, 1=8x8, 2=16x16, 3=S-EXT
+		.BOTADDSUB_UPPERINPUT      (1),   // 0=S, 1=D
+		.BOTADDSUB_CARRYSELECT     (2),   // 0=0, 1=1, 2=ACI, 3=CI
+		.MODE_8x8                  (0),
+		.A_SIGNED                  (1),
+		.B_SIGNED                  (0)
+	) testbench ();
+endmodule
+
+module testbench_comb_16x16_signedB;
+	testbench #(
+		.NEG_TRIGGER               (0),
+		.C_REG                     (0),
+		.A_REG                     (0),
+		.B_REG                     (0),
+		.D_REG                     (0),
+		.TOP_8x8_MULT_REG          (0),
+		.BOT_8x8_MULT_REG          (0),
+		.PIPELINE_16x16_MULT_REG1  (0),
+		.PIPELINE_16x16_MULT_REG2  (0),
+		.TOPOUTPUT_SELECT          (0),   // 0=P, 1=Q, 2=8x8, 3=16x16
+		.TOPADDSUB_LOWERINPUT      (2),   // 0=A, 1=8x8, 2=16x16, 3=S-EXT
+		.TOPADDSUB_UPPERINPUT      (1),   // 0=Q, 1=C
+		.TOPADDSUB_CARRYSELECT     (2),   // 0=0, 1=1, 2=ACI, 3=CI
+		.BOTOUTPUT_SELECT          (0),   // 0=R, 1=S, 2=8x8, 3=16x16
+		.BOTADDSUB_LOWERINPUT      (2),   // 0=B, 1=8x8, 2=16x16, 3=S-EXT
+		.BOTADDSUB_UPPERINPUT      (1),   // 0=S, 1=D
+		.BOTADDSUB_CARRYSELECT     (2),   // 0=0, 1=1, 2=ACI, 3=CI
+		.MODE_8x8                  (0),
+		.A_SIGNED                  (0),
+		.B_SIGNED                  (1)
+	) testbench ();
+endmodule
+
+module testbench_comb_16x16_signedAB;
+	testbench #(
+		.NEG_TRIGGER               (0),
+		.C_REG                     (0),
+		.A_REG                     (0),
+		.B_REG                     (0),
+		.D_REG                     (0),
+		.TOP_8x8_MULT_REG          (0),
+		.BOT_8x8_MULT_REG          (0),
+		.PIPELINE_16x16_MULT_REG1  (0),
+		.PIPELINE_16x16_MULT_REG2  (0),
+		.TOPOUTPUT_SELECT          (0),   // 0=P, 1=Q, 2=8x8, 3=16x16
+		.TOPADDSUB_LOWERINPUT      (2),   // 0=A, 1=8x8, 2=16x16, 3=S-EXT
+		.TOPADDSUB_UPPERINPUT      (1),   // 0=Q, 1=C
+		.TOPADDSUB_CARRYSELECT     (2),   // 0=0, 1=1, 2=ACI, 3=CI
+		.BOTOUTPUT_SELECT          (0),   // 0=R, 1=S, 2=8x8, 3=16x16
+		.BOTADDSUB_LOWERINPUT      (2),   // 0=B, 1=8x8, 2=16x16, 3=S-EXT
+		.BOTADDSUB_UPPERINPUT      (1),   // 0=S, 1=D
+		.BOTADDSUB_CARRYSELECT     (2),   // 0=0, 1=1, 2=ACI, 3=CI
+		.MODE_8x8                  (0),
+		.A_SIGNED                  (1),
+		.B_SIGNED                  (1)
+	) testbench ();
+endmodule
+
 module testbench_seq_16x16_A;
 	testbench #(
 		.NEG_TRIGGER               (0),
-- 
cgit v1.2.3


From 3c84271543379a5a3845d5dcdb49a5e6fbafbc66 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Fri, 19 Jul 2019 17:13:34 +0100
Subject: ice40/cells_sim.v: LSB of A/B only signed in 8x8 mode

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ice40/cells_sim.v | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 609facc93..4402f8d36 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -1363,9 +1363,9 @@ module SB_MAC16 (
 	wire [15:0] p_Ah_Bh, p_Al_Bh, p_Ah_Bl, p_Al_Bl;
 	wire [15:0] Ah, Al, Bh, Bl;
 	assign Ah = {A_SIGNED ? {8{iA[15]}} : 8'b0, iA[15: 8]};
-	assign Al = {A_SIGNED ? {8{iA[ 7]}} : 8'b0, iA[ 7: 0]};
+	assign Al = {A_SIGNED && MODE_8x8 ? {8{iA[ 7]}} : 8'b0, iA[ 7: 0]};
 	assign Bh = {B_SIGNED ? {8{iB[15]}} : 8'b0, iB[15: 8]};
-	assign Bl = {B_SIGNED ? {8{iB[ 7]}} : 8'b0, iB[ 7: 0]};
+	assign Bl = {B_SIGNED && MODE_8x8 ? {8{iB[ 7]}} : 8'b0, iB[ 7: 0]};
 	assign p_Ah_Bh = Ah * Bh;
 	assign p_Al_Bh = Al * Bh;
 	assign p_Ah_Bl = Ah * Bl;
-- 
cgit v1.2.3


From 79f14c751417685e7405855a96fc7a37f5bc7fbf Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Fri, 19 Jul 2019 17:33:41 +0100
Subject: ice40/cells_sim.v: Fix sign of J and K partial products

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ice40/cells_sim.v | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 4402f8d36..2205be27d 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -1366,10 +1366,10 @@ module SB_MAC16 (
 	assign Al = {A_SIGNED && MODE_8x8 ? {8{iA[ 7]}} : 8'b0, iA[ 7: 0]};
 	assign Bh = {B_SIGNED ? {8{iB[15]}} : 8'b0, iB[15: 8]};
 	assign Bl = {B_SIGNED && MODE_8x8 ? {8{iB[ 7]}} : 8'b0, iB[ 7: 0]};
-	assign p_Ah_Bh = Ah * Bh;
-	assign p_Al_Bh = Al * Bh;
-	assign p_Ah_Bl = Ah * Bl;
-	assign p_Al_Bl = Al * Bl;
+	assign p_Ah_Bh = Ah * Bh; // F
+	assign p_Al_Bh = {8'b0, Al[7:0]} * Bh; // J
+	assign p_Ah_Bl = Ah * {8'b0, Bl[7:0]}; // K
+	assign p_Al_Bl = Al * Bl; // G
 
 	// Regs F and J
 	reg [15:0] rF, rJ;
@@ -1400,7 +1400,9 @@ module SB_MAC16 (
 	assign iG = BOT_8x8_MULT_REG ? rG : p_Al_Bl;
 
 	// Adder Stage
-	assign iL = iG + (iK << 8) + (iJ << 8) + (iF << 16);
+	wire [23:0] iK_e = {A_SIGNED ? {8{iK[15]}} : 8'b0, iK};
+	wire [23:0] iJ_e = {B_SIGNED ? {8{iJ[15]}} : 8'b0, iJ};
+	assign iL = iG + (iK_e << 8) + (iJ_e << 8) + (iF << 16);
 
 	// Reg H
 	reg [31:0] rH;
-- 
cgit v1.2.3


From 80884d6f7bd10d79e89ad3893ae557aa64af9742 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Fri, 19 Jul 2019 17:33:57 +0100
Subject: ice40: Fix test_dsp_model.sh

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ice40/tests/test_dsp_model.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/tests/test_dsp_model.sh b/techlibs/ice40/tests/test_dsp_model.sh
index 75f95ab29..1e564d1b2 100644
--- a/techlibs/ice40/tests/test_dsp_model.sh
+++ b/techlibs/ice40/tests/test_dsp_model.sh
@@ -9,7 +9,7 @@ for tb in testbench \
 		testbench_seq_16x16_A testbench_seq_16x16_B \
 		testbench_comb_8x8_A_signedA testbench_comb_8x8_A_signedB testbench_comb_8x8_A_signedAB \
 		testbench_comb_8x8_B_signedA testbench_comb_8x8_B_signedB testbench_comb_8x8_B_signedAB \
-		testbench_comb_16x16_B_signedA testbench_comb_16x16_B_signedB testbench_comb_16x16_B_signedAB
+		testbench_comb_16x16_signedA testbench_comb_16x16_signedB testbench_comb_16x16_signedAB
 do
 	iverilog -s $tb -o test_dsp_model test_dsp_model.v test_dsp_model_uut.v test_dsp_model_ref.v
 	vvp -N ./test_dsp_model
-- 
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