From a270af00cc133ac03ec97cf81ed0a7146b7b225e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 23 Aug 2019 11:21:44 -0700
Subject: Put abc_* attributes above port

---
 techlibs/ice40/cells_sim.v | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index ab04808f4..c7f3bdad2 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -143,11 +143,13 @@ endmodule
 
 (* abc_box_id = 1, lib_whitebox *)
 module \$__ICE40_FULL_ADDER (
-	(* abc_carry *) output CO,
+	(* abc_carry *)
+	output CO,
 	output O,
 	input A,
 	input B,
-	(* abc_carry *) input CI
+	(* abc_carry *)
+	input CI
 );
 	SB_CARRY carry (
 		.I0(A),
-- 
cgit v1.2.3


From 129df7184a2b85553366f9d56e26ac4eaccc5a52 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 17:07:07 -0700
Subject: Update to new $__ICE40_CARRY_WRAPPER

---
 techlibs/ice40/cells_sim.v | 19 ++++++++-----------
 1 file changed, 8 insertions(+), 11 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index c7f3bdad2..02726605f 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -142,15 +142,16 @@ module SB_CARRY (output CO, input I0, I1, CI);
 endmodule
 
 (* abc_box_id = 1, lib_whitebox *)
-module \$__ICE40_FULL_ADDER (
+module \$__ICE40_CARRY_WRAPPER (
 	(* abc_carry *)
 	output CO,
 	output O,
-	input A,
-	input B,
+	input A, B,
 	(* abc_carry *)
-	input CI
+	input CI,
+	input I0, I3,
 );
+	parameter LUT = 0;
 	SB_CARRY carry (
 		.I0(A),
 		.I1(B),
@@ -158,16 +159,12 @@ module \$__ICE40_FULL_ADDER (
 		.CO(CO)
 	);
 	SB_LUT4 #(
-		//         I0: 1010 1010 1010 1010
-		//         I1: 1100 1100 1100 1100
-		//         I2: 1111 0000 1111 0000
-		//         I3: 1111 1111 0000 0000
-		.LUT_INIT(16'b 0110_1001_1001_0110)
+		.LUT_INIT(LUT)
 	) adder (
-		.I0(1'b0),
+		.I0(I0),
 		.I1(A),
 		.I2(B),
-		.I3(CI),
+		.I3(I3),
 		.O(O)
 	);
 endmodule
-- 
cgit v1.2.3


From 077e9d4ada7fbc75ab87fe7f390d58e2d53b4472 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 17:07:24 -0700
Subject: Update box size and timings

---
 techlibs/ice40/abc_hx.box | 8 ++++----
 techlibs/ice40/abc_lp.box | 8 ++++----
 techlibs/ice40/abc_u.box  | 8 ++++----
 3 files changed, 12 insertions(+), 12 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/abc_hx.box b/techlibs/ice40/abc_hx.box
index c0ea742e2..571152129 100644
--- a/techlibs/ice40/abc_hx.box
+++ b/techlibs/ice40/abc_hx.box
@@ -3,11 +3,11 @@
 # NB: Inputs/Outputs must be ordered alphabetically
 #     (with exceptions for carry in/out)
 
-# Inputs: A B CI
+# Inputs: A B I0 I3 CI
 # Outputs: O CO
 #   (NB: carry chain input/output must be last
 #        input/output and have been moved there
 #        overriding the alphabetical ordering)
-$__ICE40_FULL_ADDER 1 1 3 2
-400 379 316
-259 231 126
+$__ICE40_FULL_ADDER 1 1 5 2
+400 379 449 316 316
+259 231 -   -   126
diff --git a/techlibs/ice40/abc_lp.box b/techlibs/ice40/abc_lp.box
index d73b6d649..a9f8699fc 100644
--- a/techlibs/ice40/abc_lp.box
+++ b/techlibs/ice40/abc_lp.box
@@ -3,11 +3,11 @@
 # NB: Inputs/Outputs must be ordered alphabetically
 #     (with exceptions for carry in/out)
 
-# Inputs: A B CI
+# Inputs: A B I0 I3 CI
 # Outputs: O CO
 #   (NB: carry chain input/output must be last
 #        input/output and have been moved there
 #        overriding the alphabetical ordering)
-$__ICE40_FULL_ADDER 1 1 3 2
-589 558 465
-675 609 186 
+$__ICE40_FULL_ADDER 1 1 5 2
+589 558 661 465 465
+675 609 -   -   186
diff --git a/techlibs/ice40/abc_u.box b/techlibs/ice40/abc_u.box
index 42d666051..bc8a8d9cd 100644
--- a/techlibs/ice40/abc_u.box
+++ b/techlibs/ice40/abc_u.box
@@ -3,11 +3,11 @@
 # NB: Inputs/Outputs must be ordered alphabetically
 #     (with exceptions for carry in/out)
 
-# Inputs: A B CI
+# Inputs: A B I0 I3 CI
 # Outputs: O CO
 #   (NB: carry chain input/output must be last
 #        input/output and have been moved there
 #        overriding the alphabetical ordering)
-$__ICE40_FULL_ADDER 1 1 3 2
-1231 1205 874
-675  609  278
+$__ICE40_FULL_ADDER 1 1 5 2
+1231 1205 1285 874 874
+675  609  -    -   278
-- 
cgit v1.2.3


From 2aedee1f0e0f6a6214241f51f5c12d4b67c3ef6f Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 17:07:36 -0700
Subject: Remove $__ICE40_FULL_ADDER handling from ice40_opt; cannot reason
 with

CARRY_WRAPPER in the same way since I0 and I3 could be used
---
 techlibs/ice40/ice40_opt.cc | 45 ---------------------------------------------
 1 file changed, 45 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index d5106b805..f528607d6 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -83,51 +83,6 @@ static void run_ice40_opts(Module *module)
 			}
 			continue;
 		}
-
-		if (cell->type == "$__ICE40_FULL_ADDER")
-		{
-			SigSpec non_const_inputs, replacement_output;
-			int count_zeros = 0, count_ones = 0;
-
-			SigBit inbit[3] = {
-				cell->getPort("\\A"),
-				cell->getPort("\\B"),
-				cell->getPort("\\CI")
-			};
-			for (int i = 0; i < 3; i++)
-				if (inbit[i].wire == nullptr) {
-					if (inbit[i] == State::S1)
-						count_ones++;
-					else
-						count_zeros++;
-				} else
-					non_const_inputs.append(inbit[i]);
-
-			if (count_zeros >= 2)
-				replacement_output = State::S0;
-			else if (count_ones >= 2)
-				replacement_output = State::S1;
-			else if (GetSize(non_const_inputs) == 1)
-				replacement_output = non_const_inputs;
-
-			if (GetSize(replacement_output)) {
-				optimized_co.insert(sigmap(cell->getPort("\\CO")[0]));
-				module->connect(cell->getPort("\\CO")[0], replacement_output);
-				module->design->scratchpad_set_bool("opt.did_something", true);
-				log("Optimized $__ICE40_FULL_ADDER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n",
-						log_id(module), log_id(cell), log_signal(replacement_output));
-				cell->type = "$lut";
-				cell->setPort("\\A", { State::S0, inbit[0], inbit[1], inbit[2] });
-				cell->setPort("\\Y", cell->getPort("\\O"));
-				cell->unsetPort("\\B");
-				cell->unsetPort("\\CI");
-				cell->unsetPort("\\CO");
-				cell->unsetPort("\\O");
-				cell->setParam("\\LUT", RTLIL::Const::from_string("0110100110010110"));
-				cell->setParam("\\WIDTH", 4);
-			}
-			continue;
-		}
 	}
 
 	for (auto cell : sb_lut_cells)
-- 
cgit v1.2.3


From e4f89e01b5710eb9e2e6675a1df13a5a2637b206 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 17:21:12 -0700
Subject: Specify ice40 family to cells_sim.v using define

---
 techlibs/ice40/synth_ice40.cc | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index c6de81bd9..2f77c03db 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -238,7 +238,14 @@ struct SynthIce40Pass : public ScriptPass
 	{
 		if (check_label("begin"))
 		{
-			run("read_verilog -icells -lib +/ice40/cells_sim.v");
+			std::string define;
+			if (device_opt == "lp")
+				define = "-D ICE40_LX";
+			else if (device_opt == "u")
+				define = "-D ICE40_U";
+			else
+				define = "-D ICE40_HX";
+			run("read_verilog -icells " + define + " -lib +/ice40/cells_sim.v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 			run("proc");
 		}
-- 
cgit v1.2.3


From 2421cb3fed1a990219227ed3cf0632eb221e9698 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 17:21:37 -0700
Subject: Add arrival times for HX devices

---
 techlibs/ice40/cells_sim.v | 135 ++++++++++++++++++++++++++++++++++++++-------
 1 file changed, 114 insertions(+), 21 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 02726605f..261d99c9b 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -2,6 +2,10 @@
 `define SB_DFF_REG reg Q = 0
 // `define SB_DFF_REG reg Q
 
+`define ABC_ARRIVAL_HX(TIME) `ifdef ICE40_HX (* abc_arrival=TIME *) `endif
+`define ABC_ARRIVAL_LX(TIME) `ifdef ICE40_LX (* abc_arrival=TIME *) `endif
+`define ABC_ARRIVAL_U(TIME)  `ifdef ICE40_U (* abc_arrival=TIME *) `endif
+
 // SiliconBlue IO Cells
 
 module SB_IO (
@@ -169,20 +173,34 @@ module \$__ICE40_CARRY_WRAPPER (
 	);
 endmodule
 
+// Max delay from: https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
+
 // Positive Edge SiliconBlue FF Cells
 
-module SB_DFF (output `SB_DFF_REG, input C, D);
+module SB_DFF (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, D
+);
 	always @(posedge C)
 		Q <= D;
 endmodule
 
-module SB_DFFE (output `SB_DFF_REG, input C, E, D);
+module SB_DFFE (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, E, D
+);
 	always @(posedge C)
 		if (E)
 			Q <= D;
 endmodule
 
-module SB_DFFSR (output `SB_DFF_REG, input C, R, D);
+module SB_DFFSR (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, R, D
+);
 	always @(posedge C)
 		if (R)
 			Q <= 0;
@@ -190,7 +208,11 @@ module SB_DFFSR (output `SB_DFF_REG, input C, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFR (output `SB_DFF_REG, input C, R, D);
+module SB_DFFR (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, R, D
+);
 	always @(posedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -198,7 +220,11 @@ module SB_DFFR (output `SB_DFF_REG, input C, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFSS (output `SB_DFF_REG, input C, S, D);
+module SB_DFFSS (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, S, D
+);
 	always @(posedge C)
 		if (S)
 			Q <= 1;
@@ -206,7 +232,11 @@ module SB_DFFSS (output `SB_DFF_REG, input C, S, D);
 			Q <= D;
 endmodule
 
-module SB_DFFS (output `SB_DFF_REG, input C, S, D);
+module SB_DFFS (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, S, D
+);
 	always @(posedge C, posedge S)
 		if (S)
 			Q <= 1;
@@ -214,7 +244,11 @@ module SB_DFFS (output `SB_DFF_REG, input C, S, D);
 			Q <= D;
 endmodule
 
-module SB_DFFESR (output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFESR (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, E, R, D
+);
 	always @(posedge C)
 		if (E) begin
 			if (R)
@@ -224,7 +258,11 @@ module SB_DFFESR (output `SB_DFF_REG, input C, E, R, D);
 		end
 endmodule
 
-module SB_DFFER (output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFER (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, E, R, D
+);
 	always @(posedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -232,7 +270,11 @@ module SB_DFFER (output `SB_DFF_REG, input C, E, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFESS (output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFESS (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, E, S, D
+);
 	always @(posedge C)
 		if (E) begin
 			if (S)
@@ -242,7 +284,11 @@ module SB_DFFESS (output `SB_DFF_REG, input C, E, S, D);
 		end
 endmodule
 
-module SB_DFFES (output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFES (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, E, S, D
+);
 	always @(posedge C, posedge S)
 		if (S)
 			Q <= 1;
@@ -252,18 +298,30 @@ endmodule
 
 // Negative Edge SiliconBlue FF Cells
 
-module SB_DFFN (output `SB_DFF_REG, input C, D);
+module SB_DFFN (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, D
+);
 	always @(negedge C)
 		Q <= D;
 endmodule
 
-module SB_DFFNE (output `SB_DFF_REG, input C, E, D);
+module SB_DFFNE (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, E, D
+);
 	always @(negedge C)
 		if (E)
 			Q <= D;
 endmodule
 
-module SB_DFFNSR (output `SB_DFF_REG, input C, R, D);
+module SB_DFFNSR (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, R, D
+);
 	always @(negedge C)
 		if (R)
 			Q <= 0;
@@ -271,7 +329,11 @@ module SB_DFFNSR (output `SB_DFF_REG, input C, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNR (output `SB_DFF_REG, input C, R, D);
+module SB_DFFNR (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, R, D
+);
 	always @(negedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -279,7 +341,11 @@ module SB_DFFNR (output `SB_DFF_REG, input C, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNSS (output `SB_DFF_REG, input C, S, D);
+module SB_DFFNSS (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, S, D
+);
 	always @(negedge C)
 		if (S)
 			Q <= 1;
@@ -287,7 +353,11 @@ module SB_DFFNSS (output `SB_DFF_REG, input C, S, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNS (output `SB_DFF_REG, input C, S, D);
+module SB_DFFNS (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, S, D
+);
 	always @(negedge C, posedge S)
 		if (S)
 			Q <= 1;
@@ -295,7 +365,11 @@ module SB_DFFNS (output `SB_DFF_REG, input C, S, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNESR (output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFNESR (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, E, R, D
+);
 	always @(negedge C)
 		if (E) begin
 			if (R)
@@ -305,7 +379,11 @@ module SB_DFFNESR (output `SB_DFF_REG, input C, E, R, D);
 		end
 endmodule
 
-module SB_DFFNER (output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFNER (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, E, R, D
+);
 	always @(negedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -313,7 +391,11 @@ module SB_DFFNER (output `SB_DFF_REG, input C, E, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNESS (output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFNESS (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, E, S, D
+);
 	always @(negedge C)
 		if (E) begin
 			if (S)
@@ -323,7 +405,11 @@ module SB_DFFNESS (output `SB_DFF_REG, input C, E, S, D);
 		end
 endmodule
 
-module SB_DFFNES (output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFNES (
+	`ABC_ARRIVAL_HX(540)
+	output `SB_DFF_REG,
+	input C, E, S, D
+);
 	always @(negedge C, posedge S)
 		if (S)
 			Q <= 1;
@@ -334,6 +420,7 @@ endmodule
 // SiliconBlue RAM Cells
 
 module SB_RAM40_4K (
+	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
 	output [15:0] RDATA,
 	input         RCLK, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -502,6 +589,7 @@ module SB_RAM40_4K (
 endmodule
 
 module SB_RAM40_4KNR (
+	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
 	output [15:0] RDATA,
 	input         RCLKN, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -567,6 +655,7 @@ module SB_RAM40_4KNR (
 endmodule
 
 module SB_RAM40_4KNW (
+	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
 	output [15:0] RDATA,
 	input         RCLK, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -632,6 +721,7 @@ module SB_RAM40_4KNW (
 endmodule
 
 module SB_RAM40_4KNRNW (
+	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
 	output [15:0] RDATA,
 	input         RCLKN, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -700,7 +790,10 @@ endmodule
 
 module ICESTORM_LC (
 	input I0, I1, I2, I3, CIN, CLK, CEN, SR,
-	output LO, O, COUT
+	output LO,
+	`ABC_ARRIVAL_HX(540)
+	output O,
+	output COUT
 );
 	parameter [15:0] LUT_INIT = 0;
 
-- 
cgit v1.2.3


From e569f138704a28654cc52c917bba4decffa29f54 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 17:22:44 -0700
Subject: Revert "Remove $__ICE40_FULL_ADDER handling from ice40_opt; cannot
 reason with"

This reverts commit 2aedee1f0e0f6a6214241f51f5c12d4b67c3ef6f.
---
 techlibs/ice40/ice40_opt.cc | 45 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 45 insertions(+)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index f528607d6..d5106b805 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -83,6 +83,51 @@ static void run_ice40_opts(Module *module)
 			}
 			continue;
 		}
+
+		if (cell->type == "$__ICE40_FULL_ADDER")
+		{
+			SigSpec non_const_inputs, replacement_output;
+			int count_zeros = 0, count_ones = 0;
+
+			SigBit inbit[3] = {
+				cell->getPort("\\A"),
+				cell->getPort("\\B"),
+				cell->getPort("\\CI")
+			};
+			for (int i = 0; i < 3; i++)
+				if (inbit[i].wire == nullptr) {
+					if (inbit[i] == State::S1)
+						count_ones++;
+					else
+						count_zeros++;
+				} else
+					non_const_inputs.append(inbit[i]);
+
+			if (count_zeros >= 2)
+				replacement_output = State::S0;
+			else if (count_ones >= 2)
+				replacement_output = State::S1;
+			else if (GetSize(non_const_inputs) == 1)
+				replacement_output = non_const_inputs;
+
+			if (GetSize(replacement_output)) {
+				optimized_co.insert(sigmap(cell->getPort("\\CO")[0]));
+				module->connect(cell->getPort("\\CO")[0], replacement_output);
+				module->design->scratchpad_set_bool("opt.did_something", true);
+				log("Optimized $__ICE40_FULL_ADDER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n",
+						log_id(module), log_id(cell), log_signal(replacement_output));
+				cell->type = "$lut";
+				cell->setPort("\\A", { State::S0, inbit[0], inbit[1], inbit[2] });
+				cell->setPort("\\Y", cell->getPort("\\O"));
+				cell->unsetPort("\\B");
+				cell->unsetPort("\\CI");
+				cell->unsetPort("\\CO");
+				cell->unsetPort("\\O");
+				cell->setParam("\\LUT", RTLIL::Const::from_string("0110100110010110"));
+				cell->setParam("\\WIDTH", 4);
+			}
+			continue;
+		}
 	}
 
 	for (auto cell : sb_lut_cells)
-- 
cgit v1.2.3


From f5b4bc847c02d6c3e06c086a1375840ccac936cd Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 17:25:05 -0700
Subject: Adapt to $__ICE40_CARRY_WRAPPER

---
 techlibs/ice40/ice40_opt.cc | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index d5106b805..58f106f7c 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -84,7 +84,7 @@ static void run_ice40_opts(Module *module)
 			continue;
 		}
 
-		if (cell->type == "$__ICE40_FULL_ADDER")
+		if (cell->type == "$__ICE40_CARRY_WRAPPER")
 		{
 			SigSpec non_const_inputs, replacement_output;
 			int count_zeros = 0, count_ones = 0;
@@ -114,13 +114,15 @@ static void run_ice40_opts(Module *module)
 				optimized_co.insert(sigmap(cell->getPort("\\CO")[0]));
 				module->connect(cell->getPort("\\CO")[0], replacement_output);
 				module->design->scratchpad_set_bool("opt.did_something", true);
-				log("Optimized $__ICE40_FULL_ADDER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n",
+				log("Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n",
 						log_id(module), log_id(cell), log_signal(replacement_output));
 				cell->type = "$lut";
-				cell->setPort("\\A", { State::S0, inbit[0], inbit[1], inbit[2] });
+				cell->setPort("\\A", { cell->getPort("\\I0"), inbit[0], inbit[1], cell->getPort("\\I3") });
 				cell->setPort("\\Y", cell->getPort("\\O"));
 				cell->unsetPort("\\B");
 				cell->unsetPort("\\CI");
+				cell->unsetPort("\\I0");
+				cell->unsetPort("\\I3");
 				cell->unsetPort("\\CO");
 				cell->unsetPort("\\O");
 				cell->setParam("\\LUT", RTLIL::Const::from_string("0110100110010110"));
-- 
cgit v1.2.3


From d46d38e4d5e1502ea5cb6075161c87bd837af9eb Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 17:25:54 -0700
Subject: Trailing comma

---
 techlibs/ice40/cells_sim.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 02726605f..2a7487f6b 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -149,7 +149,7 @@ module \$__ICE40_CARRY_WRAPPER (
 	input A, B,
 	(* abc_carry *)
 	input CI,
-	input I0, I3,
+	input I0, I3
 );
 	parameter LUT = 0;
 	SB_CARRY carry (
-- 
cgit v1.2.3


From c0b99ed0e8c8c6adf76d70fa71c9753957162e04 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 18:45:09 -0700
Subject: Do not overwrite LUT param

---
 techlibs/ice40/ice40_opt.cc | 1 -
 1 file changed, 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index 58f106f7c..ea56d3f4d 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -125,7 +125,6 @@ static void run_ice40_opts(Module *module)
 				cell->unsetPort("\\I3");
 				cell->unsetPort("\\CO");
 				cell->unsetPort("\\O");
-				cell->setParam("\\LUT", RTLIL::Const::from_string("0110100110010110"));
 				cell->setParam("\\WIDTH", 4);
 			}
 			continue;
-- 
cgit v1.2.3


From a4f641f2303bc6f04751a15ec49cf2658ea8eb63 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 18:45:09 -0700
Subject: Do not overwrite LUT param

---
 techlibs/ice40/ice40_opt.cc | 1 -
 1 file changed, 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index 58f106f7c..ea56d3f4d 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -125,7 +125,6 @@ static void run_ice40_opts(Module *module)
 				cell->unsetPort("\\I3");
 				cell->unsetPort("\\CO");
 				cell->unsetPort("\\O");
-				cell->setParam("\\LUT", RTLIL::Const::from_string("0110100110010110"));
 				cell->setParam("\\WIDTH", 4);
 			}
 			continue;
-- 
cgit v1.2.3


From e3709e5ee6b28c1156b4768373e244c32c7c5aba Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 18:51:14 -0700
Subject: LX -> LP

---
 techlibs/ice40/cells_sim.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 34134d02a..fe80c998d 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -3,7 +3,7 @@
 // `define SB_DFF_REG reg Q
 
 `define ABC_ARRIVAL_HX(TIME) `ifdef ICE40_HX (* abc_arrival=TIME *) `endif
-`define ABC_ARRIVAL_LX(TIME) `ifdef ICE40_LX (* abc_arrival=TIME *) `endif
+`define ABC_ARRIVAL_LP(TIME) `ifdef ICE40_LP (* abc_arrival=TIME *) `endif
 `define ABC_ARRIVAL_U(TIME)  `ifdef ICE40_U (* abc_arrival=TIME *) `endif
 
 // SiliconBlue IO Cells
-- 
cgit v1.2.3


From 927f1e3754987ab794566a521c7a1149d4fbf6a7 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 18:56:25 -0700
Subject: Add LP timings

---
 techlibs/ice40/cells_sim.v | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index fe80c998d..b86ec3ea5 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -174,11 +174,13 @@ module \$__ICE40_CARRY_WRAPPER (
 endmodule
 
 // Max delay from: https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
+//                 https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
 
 // Positive Edge SiliconBlue FF Cells
 
 module SB_DFF (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, D
 );
@@ -188,6 +190,7 @@ endmodule
 
 module SB_DFFE (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, E, D
 );
@@ -198,6 +201,7 @@ endmodule
 
 module SB_DFFSR (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -210,6 +214,7 @@ endmodule
 
 module SB_DFFR (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -222,6 +227,7 @@ endmodule
 
 module SB_DFFSS (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -234,6 +240,7 @@ endmodule
 
 module SB_DFFS (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -246,6 +253,7 @@ endmodule
 
 module SB_DFFESR (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -260,6 +268,7 @@ endmodule
 
 module SB_DFFER (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -272,6 +281,7 @@ endmodule
 
 module SB_DFFESS (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -286,6 +296,7 @@ endmodule
 
 module SB_DFFES (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -300,6 +311,7 @@ endmodule
 
 module SB_DFFN (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, D
 );
@@ -309,6 +321,7 @@ endmodule
 
 module SB_DFFNE (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, E, D
 );
@@ -319,6 +332,7 @@ endmodule
 
 module SB_DFFNSR (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -331,6 +345,7 @@ endmodule
 
 module SB_DFFNR (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -343,6 +358,7 @@ endmodule
 
 module SB_DFFNSS (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -355,6 +371,7 @@ endmodule
 
 module SB_DFFNS (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -367,6 +384,7 @@ endmodule
 
 module SB_DFFNESR (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -381,6 +399,7 @@ endmodule
 
 module SB_DFFNER (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -393,6 +412,7 @@ endmodule
 
 module SB_DFFNESS (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -407,6 +427,7 @@ endmodule
 
 module SB_DFFNES (
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -421,6 +442,7 @@ endmodule
 
 module SB_RAM40_4K (
 	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
+	`ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
 	output [15:0] RDATA,
 	input         RCLK, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -590,6 +612,7 @@ endmodule
 
 module SB_RAM40_4KNR (
 	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
+	`ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
 	output [15:0] RDATA,
 	input         RCLKN, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -656,6 +679,7 @@ endmodule
 
 module SB_RAM40_4KNW (
 	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
+	`ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
 	output [15:0] RDATA,
 	input         RCLK, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -722,6 +746,7 @@ endmodule
 
 module SB_RAM40_4KNRNW (
 	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
+	`ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
 	output [15:0] RDATA,
 	input         RCLKN, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -792,6 +817,7 @@ module ICESTORM_LC (
 	input I0, I1, I2, I3, CIN, CLK, CEN, SR,
 	output LO,
 	`ABC_ARRIVAL_HX(540)
+	`ABC_ARRIVAL_LP(795)
 	output O,
 	output COUT
 );
-- 
cgit v1.2.3


From 0f4e9f6bc5a5a564b2ddccb0fbebdfa5735aeefd Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 18:57:34 -0700
Subject: Round not floor

---
 techlibs/ice40/cells_sim.v | 42 +++++++++++++++++++++---------------------
 1 file changed, 21 insertions(+), 21 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index b86ec3ea5..f5fe800f7 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -180,7 +180,7 @@ endmodule
 
 module SB_DFF (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, D
 );
@@ -190,7 +190,7 @@ endmodule
 
 module SB_DFFE (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, E, D
 );
@@ -201,7 +201,7 @@ endmodule
 
 module SB_DFFSR (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -214,7 +214,7 @@ endmodule
 
 module SB_DFFR (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -227,7 +227,7 @@ endmodule
 
 module SB_DFFSS (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -240,7 +240,7 @@ endmodule
 
 module SB_DFFS (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -253,7 +253,7 @@ endmodule
 
 module SB_DFFESR (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -268,7 +268,7 @@ endmodule
 
 module SB_DFFER (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -281,7 +281,7 @@ endmodule
 
 module SB_DFFESS (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -296,7 +296,7 @@ endmodule
 
 module SB_DFFES (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -311,7 +311,7 @@ endmodule
 
 module SB_DFFN (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, D
 );
@@ -321,7 +321,7 @@ endmodule
 
 module SB_DFFNE (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, E, D
 );
@@ -332,7 +332,7 @@ endmodule
 
 module SB_DFFNSR (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -345,7 +345,7 @@ endmodule
 
 module SB_DFFNR (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -358,7 +358,7 @@ endmodule
 
 module SB_DFFNSS (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -371,7 +371,7 @@ endmodule
 
 module SB_DFFNS (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -384,7 +384,7 @@ endmodule
 
 module SB_DFFNESR (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -399,7 +399,7 @@ endmodule
 
 module SB_DFFNER (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -412,7 +412,7 @@ endmodule
 
 module SB_DFFNESS (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -427,7 +427,7 @@ endmodule
 
 module SB_DFFNES (
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -817,7 +817,7 @@ module ICESTORM_LC (
 	input I0, I1, I2, I3, CIN, CLK, CEN, SR,
 	output LO,
 	`ABC_ARRIVAL_HX(540)
-	`ABC_ARRIVAL_LP(795)
+	`ABC_ARRIVAL_LP(796)
 	output O,
 	output COUT
 );
-- 
cgit v1.2.3


From 4bda902f1b9dccb5603c2beebd71392cbfe34eb9 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 19:02:54 -0700
Subject: LX -> LP

---
 techlibs/ice40/synth_ice40.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 2f77c03db..a3890268a 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -240,7 +240,7 @@ struct SynthIce40Pass : public ScriptPass
 		{
 			std::string define;
 			if (device_opt == "lp")
-				define = "-D ICE40_LX";
+				define = "-D ICE40_LP";
 			else if (device_opt == "u")
 				define = "-D ICE40_U";
 			else
-- 
cgit v1.2.3


From efa4ee5c0e6201f357d7c02a7deeb1ba1c23c368 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 19:03:29 -0700
Subject: Add arrival times for U

---
 techlibs/ice40/cells_sim.v | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index f5fe800f7..116188acb 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -175,12 +175,14 @@ endmodule
 
 // Max delay from: https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
 //                 https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
+//                 https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
 
 // Positive Edge SiliconBlue FF Cells
 
 module SB_DFF (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, D
 );
@@ -191,6 +193,7 @@ endmodule
 module SB_DFFE (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, D
 );
@@ -202,6 +205,7 @@ endmodule
 module SB_DFFSR (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -215,6 +219,7 @@ endmodule
 module SB_DFFR (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -228,6 +233,7 @@ endmodule
 module SB_DFFSS (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -241,6 +247,7 @@ endmodule
 module SB_DFFS (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -254,6 +261,7 @@ endmodule
 module SB_DFFESR (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -269,6 +277,7 @@ endmodule
 module SB_DFFER (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -282,6 +291,7 @@ endmodule
 module SB_DFFESS (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -297,6 +307,7 @@ endmodule
 module SB_DFFES (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -312,6 +323,7 @@ endmodule
 module SB_DFFN (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, D
 );
@@ -322,6 +334,7 @@ endmodule
 module SB_DFFNE (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, D
 );
@@ -333,6 +346,7 @@ endmodule
 module SB_DFFNSR (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -346,6 +360,7 @@ endmodule
 module SB_DFFNR (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -359,6 +374,7 @@ endmodule
 module SB_DFFNSS (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -372,6 +388,7 @@ endmodule
 module SB_DFFNS (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -385,6 +402,7 @@ endmodule
 module SB_DFFNESR (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -400,6 +418,7 @@ endmodule
 module SB_DFFNER (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -413,6 +432,7 @@ endmodule
 module SB_DFFNESS (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -428,6 +448,7 @@ endmodule
 module SB_DFFNES (
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -443,6 +464,7 @@ endmodule
 module SB_RAM40_4K (
 	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
 	`ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
+	`ABC_ARRIVAL_U(1179)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
 	output [15:0] RDATA,
 	input         RCLK, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -613,6 +635,7 @@ endmodule
 module SB_RAM40_4KNR (
 	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
 	`ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
+	`ABC_ARRIVAL_U(1179)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
 	output [15:0] RDATA,
 	input         RCLKN, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -680,6 +703,7 @@ endmodule
 module SB_RAM40_4KNW (
 	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
 	`ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
+	`ABC_ARRIVAL_U(1179)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
 	output [15:0] RDATA,
 	input         RCLK, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -747,6 +771,7 @@ endmodule
 module SB_RAM40_4KNRNW (
 	`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
 	`ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
+	`ABC_ARRIVAL_U(1179)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
 	output [15:0] RDATA,
 	input         RCLKN, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -818,6 +843,7 @@ module ICESTORM_LC (
 	output LO,
 	`ABC_ARRIVAL_HX(540)
 	`ABC_ARRIVAL_LP(796)
+	`ABC_ARRIVAL_U(1391)
 	output O,
 	output COUT
 );
-- 
cgit v1.2.3


From 309684af16c763f7874beb605d0834c64975d004 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 19:07:28 -0700
Subject: Add arrival for SB_MAC16.O

---
 techlibs/ice40/cells_sim.v | 1 +
 1 file changed, 1 insertion(+)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 116188acb..f4cc342eb 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -1445,6 +1445,7 @@ module SB_MAC16 (
 	input ADDSUBTOP, ADDSUBBOT,
 	input OHOLDTOP, OHOLDBOT,
 	input CI, ACCUMCI, SIGNEXTIN,
+	`ABC_ARRIVAL_U(1984)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L587
 	output [31:0] O,
 	output CO, ACCUMCO, SIGNEXTOUT
 );
-- 
cgit v1.2.3


From e8e38308689a760b69bd2910a36701b19f64656d Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 19:09:29 -0700
Subject: Comment out SB_MAC16 arrival time for now, need to handle all its
 modes

---
 techlibs/ice40/cells_sim.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index f4cc342eb..8e5e0358e 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -1445,7 +1445,7 @@ module SB_MAC16 (
 	input ADDSUBTOP, ADDSUBBOT,
 	input OHOLDTOP, OHOLDBOT,
 	input CI, ACCUMCI, SIGNEXTIN,
-	`ABC_ARRIVAL_U(1984)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L587
+	//`ABC_ARRIVAL_U(1984)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
 	output [31:0] O,
 	output CO, ACCUMCO, SIGNEXTOUT
 );
-- 
cgit v1.2.3


From 25b1670a8425198abfcef4602a3d1ddcc0ca5d40 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 29 Aug 2019 07:03:32 -0700
Subject: Rename boxes too

---
 techlibs/ice40/abc_hx.box | 2 +-
 techlibs/ice40/abc_lp.box | 2 +-
 techlibs/ice40/abc_u.box  | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

(limited to 'techlibs/ice40')

diff --git a/techlibs/ice40/abc_hx.box b/techlibs/ice40/abc_hx.box
index 571152129..3ea70bc91 100644
--- a/techlibs/ice40/abc_hx.box
+++ b/techlibs/ice40/abc_hx.box
@@ -8,6 +8,6 @@
 #   (NB: carry chain input/output must be last
 #        input/output and have been moved there
 #        overriding the alphabetical ordering)
-$__ICE40_FULL_ADDER 1 1 5 2
+$__ICE40_CARRY_WRAPPER 1 1 5 2
 400 379 449 316 316
 259 231 -   -   126
diff --git a/techlibs/ice40/abc_lp.box b/techlibs/ice40/abc_lp.box
index a9f8699fc..473e92fe9 100644
--- a/techlibs/ice40/abc_lp.box
+++ b/techlibs/ice40/abc_lp.box
@@ -8,6 +8,6 @@
 #   (NB: carry chain input/output must be last
 #        input/output and have been moved there
 #        overriding the alphabetical ordering)
-$__ICE40_FULL_ADDER 1 1 5 2
+$__ICE40_CARRY_WRAPPER 1 1 5 2
 589 558 661 465 465
 675 609 -   -   186
diff --git a/techlibs/ice40/abc_u.box b/techlibs/ice40/abc_u.box
index bc8a8d9cd..f00e247b8 100644
--- a/techlibs/ice40/abc_u.box
+++ b/techlibs/ice40/abc_u.box
@@ -8,6 +8,6 @@
 #   (NB: carry chain input/output must be last
 #        input/output and have been moved there
 #        overriding the alphabetical ordering)
-$__ICE40_FULL_ADDER 1 1 5 2
+$__ICE40_CARRY_WRAPPER 1 1 5 2
 1231 1205 1285 874 874
 675  609  -    -   278
-- 
cgit v1.2.3