From a76520112d6a7ab894a3e85b7e32def6b4ff5491 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 13 Feb 2020 10:30:56 -0800 Subject: ice40: specify fixes --- techlibs/ice40/synth_ice40.cc | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'techlibs/ice40/synth_ice40.cc') diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 7466ef1c2..f9c5a750b 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -236,15 +236,15 @@ struct SynthIce40Pass : public ScriptPass void script() YS_OVERRIDE { + std::string define; + if (device_opt == "lp") + define = "-D ICE40_LP"; + else if (device_opt == "u") + define = "-D ICE40_U"; + else + define = "-D ICE40_HX"; if (check_label("begin")) { - std::string define; - if (device_opt == "lp") - define = "-D ICE40_LP"; - else if (device_opt == "u") - define = "-D ICE40_U"; - else - define = "-D ICE40_HX"; run("read_verilog " + define + " -lib -specify +/ice40/cells_sim.v"); run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt.c_str())); run("proc"); @@ -352,7 +352,7 @@ struct SynthIce40Pass : public ScriptPass } if (!noabc) { if (abc9) { - run("read_verilog -icells -lib -specify +/abc9_model.v +/ice40/abc9_model.v"); + run("read_verilog " + define + " -icells -lib -specify +/abc9_model.v +/ice40/abc9_model.v"); int wire_delay; if (device_opt == "lp") wire_delay = 400; @@ -360,7 +360,7 @@ struct SynthIce40Pass : public ScriptPass wire_delay = 750; else wire_delay = 250; - run(stringf("abc9 -W %d", wire_delay, device_opt.c_str(), device_opt.c_str())); + run(stringf("abc9 -W %d", wire_delay)); } else run("abc -dress -lut 4", "(skip if -noabc)"); -- cgit v1.2.3