From 7a1538cd36b45fd3c397dd0414de37af768ad89e Mon Sep 17 00:00:00 2001 From: David Shah Date: Tue, 1 Oct 2019 13:46:36 +0100 Subject: ecp5: Add support for mapping 36-bit wide PDP BRAMs Signed-off-by: David Shah --- techlibs/ecp5/.gitignore | 1 + techlibs/ecp5/Makefile.inc | 2 + techlibs/ecp5/bram.txt | 23 ++++++++++ techlibs/ecp5/brams_connect.py | 20 +++++++++ techlibs/ecp5/brams_map.v | 42 ++++++++++++++++++ techlibs/ecp5/cells_bb.v | 96 +++++++++++++++++++++++++++++++++++++++++- 6 files changed, 183 insertions(+), 1 deletion(-) (limited to 'techlibs/ecp5') diff --git a/techlibs/ecp5/.gitignore b/techlibs/ecp5/.gitignore index 54c329735..9d4723264 100644 --- a/techlibs/ecp5/.gitignore +++ b/techlibs/ecp5/.gitignore @@ -6,4 +6,5 @@ bram_conn_2.vh bram_conn_4.vh bram_conn_9.vh bram_conn_18.vh +bram_conn_36.vh brams_connect.mk diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc index 80eee5004..b03da164c 100644 --- a/techlibs/ecp5/Makefile.inc +++ b/techlibs/ecp5/Makefile.inc @@ -44,6 +44,7 @@ techlibs/ecp5/bram_conn_2.vh: techlibs/ecp5/brams_connect.mk techlibs/ecp5/bram_conn_4.vh: techlibs/ecp5/brams_connect.mk techlibs/ecp5/bram_conn_9.vh: techlibs/ecp5/brams_connect.mk techlibs/ecp5/bram_conn_18.vh: techlibs/ecp5/brams_connect.mk +techlibs/ecp5/bram_conn_36.vh: techlibs/ecp5/brams_connect.mk $(eval $(call add_gen_share_file,share/ecp5,techlibs/ecp5/bram_init_1_2_4.vh)) $(eval $(call add_gen_share_file,share/ecp5,techlibs/ecp5/bram_init_9_18_36.vh)) @@ -53,3 +54,4 @@ $(eval $(call add_gen_share_file,share/ecp5,techlibs/ecp5/bram_conn_2.vh)) $(eval $(call add_gen_share_file,share/ecp5,techlibs/ecp5/bram_conn_4.vh)) $(eval $(call add_gen_share_file,share/ecp5,techlibs/ecp5/bram_conn_9.vh)) $(eval $(call add_gen_share_file,share/ecp5,techlibs/ecp5/bram_conn_18.vh)) +$(eval $(call add_gen_share_file,share/ecp5,techlibs/ecp5/bram_conn_36.vh)) diff --git a/techlibs/ecp5/bram.txt b/techlibs/ecp5/bram.txt index f223a42b8..570960489 100644 --- a/techlibs/ecp5/bram.txt +++ b/techlibs/ecp5/bram.txt @@ -1,3 +1,18 @@ +bram $__ECP5_PDPW16KD + init 1 + + abits 9 + dbits 36 + + groups 2 + ports 1 1 + wrmode 1 0 + enable 4 1 + transp 0 0 + clocks 2 3 + clkpol 2 3 +endbram + bram $__ECP5_DP16KD init 1 @@ -22,6 +37,14 @@ bram $__ECP5_DP16KD clkpol 2 3 endbram +match $__ECP5_PDPW16KD + min bits 2048 + min efficiency 5 + shuffle_enable B + make_transp + or_next_if_better +endmatch + match $__ECP5_DP16KD min bits 2048 min efficiency 5 diff --git a/techlibs/ecp5/brams_connect.py b/techlibs/ecp5/brams_connect.py index f86dcfcf0..098607c59 100755 --- a/techlibs/ecp5/brams_connect.py +++ b/techlibs/ecp5/brams_connect.py @@ -10,6 +10,18 @@ def write_bus_ports(f, ada_bits, adb_bits, dia_bits, dob_bits): print(" %s," % ", ".join(dia_conn), file=f) print(" %s," % ", ".join(dob_conn), file=f) +def write_bus_ports_pdp(f, adw_bits, adr_bits, di_bits, do_bits, be_bits): + adw_conn = [".ADW%d(%s)" % (i, adw_bits[i]) for i in range(len(adw_bits))] + adr_conn = [".ADR%d(%s)" % (i, adr_bits[i]) for i in range(len(adr_bits))] + di_conn = [".DI%d(%s)" % (i, di_bits[i]) for i in range(len(di_bits))] + do_conn = [".DO%d(%s)" % (i, do_bits[i]) for i in range(len(do_bits))] + be_conn = [".BE%d(%s)" % (i, be_bits[i]) for i in range(len(be_bits))] + print(" %s," % ", ".join(adw_conn), file=f) + print(" %s," % ", ".join(adr_conn), file=f) + print(" %s," % ", ".join(di_conn), file=f) + print(" %s," % ", ".join(do_conn), file=f) + print(" %s," % ", ".join(be_conn), file=f) + with open("techlibs/ecp5/bram_conn_1.vh", "w") as f: ada_bits = ["A1ADDR[%d]" % i for i in range(14)] adb_bits = ["B1ADDR[%d]" % i for i in range(14)] @@ -44,3 +56,11 @@ with open("techlibs/ecp5/bram_conn_18.vh", "w") as f: dia_bits = ["A1DATA[%d]" % i for i in range(18)] dob_bits = ["B1DATA[%d]" % i for i in range(18)] write_bus_ports(f, ada_bits, adb_bits, dia_bits, dob_bits) + +with open("techlibs/ecp5/bram_conn_36.vh", "w") as f: + adw_bits = ["A1ADDR[%d]" % i for i in range(9)] + adr_bits = ["1'b0", "1'b0", "1'b0", "1'b0", "1'b0"] + ["B1ADDR[%d]" % i for i in range(9)] + di_bits = ["A1DATA[%d]" % i for i in range(36)] + do_bits = ["B1DATA[%d]" % (i + 18) for i in range(18)] + ["B1DATA[%d]" % i for i in range(18)] + be_bits = ["A1EN[%d]" % i for i in range(4)] + write_bus_ports_pdp(f, adw_bits, adr_bits, di_bits, do_bits, be_bits) diff --git a/techlibs/ecp5/brams_map.v b/techlibs/ecp5/brams_map.v index 0353cbadb..310aedaf2 100644 --- a/techlibs/ecp5/brams_map.v +++ b/techlibs/ecp5/brams_map.v @@ -113,3 +113,45 @@ module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); wire TECHMAP_FAIL = 1'b1; end endgenerate endmodule + +module \$__ECP5_PDPW16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); + parameter CFG_ABITS = 9; + parameter CFG_DBITS = 36; + parameter CFG_ENABLE_A = 4; + + parameter CLKPOL2 = 1; + parameter CLKPOL3 = 1; + parameter [18431:0] INIT = 18432'bx; + + input CLK2; + input CLK3; + + input [CFG_ABITS-1:0] A1ADDR; + input [CFG_DBITS-1:0] A1DATA; + input [CFG_ENABLE_A-1:0] A1EN; + + input [CFG_ABITS-1:0] B1ADDR; + output [CFG_DBITS-1:0] B1DATA; + input B1EN; + + localparam CLKWMUX = CLKPOL2 ? "CLKA" : "INV"; + localparam CLKRMUX = CLKPOL3 ? "CLKB" : "INV"; + + localparam WRITEMODE_A = TRANSP2 ? "WRITETHROUGH" : "READBEFOREWRITE"; + + PDPW16KD #( + `include "bram_init_9_18_36.vh" + .DATA_WIDTH_W(36), + .DATA_WIDTH_R(36), + .CLKWMUX(CLKWMUX), + .CLKRMUX(CLKRMUX), + .GSR("AUTO") + ) _TECHMAP_REPLACE_ ( + `include "bram_conn_36.vh" + .CLKW(CLK2), .CLKR(CLK3), + .CEW(1'b1), + .CER(B1EN), .OCER(1'b1), + .RST(1'b0) + ); + +endmodule diff --git a/techlibs/ecp5/cells_bb.v b/techlibs/ecp5/cells_bb.v index 8557053b6..0a5046db2 100644 --- a/techlibs/ecp5/cells_bb.v +++ b/techlibs/ecp5/cells_bb.v @@ -683,4 +683,98 @@ endmodule module SGSR ( input GSR, CLK ); -endmodule \ No newline at end of file +endmodule + + +(* blackbox *) +module PDPW16KD ( + input DI35, DI34, DI33, DI32, DI31, DI30, DI29, DI28, DI27, DI26, DI25, DI24, DI23, DI22, DI21, DI20, DI19, DI18, + input DI17, DI16, DI15, DI14, DI13, DI12, DI11, DI10, DI9, DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0, + input ADW8, ADW7, ADW6, ADW5, ADW4, ADW3, ADW2, ADW1, ADW0, + input BE3, BE2, BE1, BE0, CEW, CLKW, CSW2, CSW1, CSW0, + input ADR13, ADR12, ADR11, ADR10, ADR9, ADR8, ADR7, ADR6, ADR5, ADR4, ADR3, ADR2, ADR1, ADR0, + input CER, OCER, CLKR, CSR2, CSR1, CSR0, RST, + output DO35, DO34, DO33, DO32, DO31, DO30, DO29, DO28, DO27, DO26, DO25, DO24, DO23, DO22, DO21, DO20, DO19, DO18, + output DO17, DO16, DO15, DO14, DO13, DO12, DO11, DO10, DO9, DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0 +); + parameter DATA_WIDTH_W = 36; + parameter DATA_WIDTH_R = 36; + parameter GSR = "ENABLED"; + + parameter REGMODE = "NOREG"; + + parameter RESETMODE = "SYNC"; + parameter ASYNC_RESET_RELEASE = "SYNC"; + + parameter CSDECODE_W = "0b000"; + parameter CSDECODE_R = "0b000"; + + parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_DATA = "STATIC"; + parameter CLKWMUX = "CLKW"; + parameter CLKRMUX = "CLKR"; + +endmodule -- cgit v1.2.3 From b424d374db354141afe1f42eead3347e5cb86a04 Mon Sep 17 00:00:00 2001 From: David Shah Date: Tue, 1 Oct 2019 14:14:46 +0100 Subject: ecp5: Fix shuffle_enable port Signed-off-by: David Shah --- techlibs/ecp5/bram.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'techlibs/ecp5') diff --git a/techlibs/ecp5/bram.txt b/techlibs/ecp5/bram.txt index 570960489..777ccaa2e 100644 --- a/techlibs/ecp5/bram.txt +++ b/techlibs/ecp5/bram.txt @@ -40,7 +40,7 @@ endbram match $__ECP5_PDPW16KD min bits 2048 min efficiency 5 - shuffle_enable B + shuffle_enable A make_transp or_next_if_better endmatch @@ -48,5 +48,5 @@ endmatch match $__ECP5_DP16KD min bits 2048 min efficiency 5 - shuffle_enable B + shuffle_enable A endmatch -- cgit v1.2.3 From 9fef1df3c1431cff2e097a10a502f77f04986a60 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 4 Oct 2019 10:48:44 -0700 Subject: Panic over. Model was elsewhere. Re-arrange for consistency --- techlibs/ecp5/synth_ecp5.cc | 1 + 1 file changed, 1 insertion(+) (limited to 'techlibs/ecp5') diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index 1f5b1cb6b..67d2f483c 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -311,6 +311,7 @@ struct SynthEcp5Pass : public ScriptPass run("techmap " + techmap_args); if (abc9) { + run("read_verilog -icells -lib +/ecp5/abc_model.v"); if (nowidelut) run("abc9 -lut +/ecp5/abc_5g_nowide.lut -box +/ecp5/abc_5g.box -W 200"); else -- cgit v1.2.3 From aae2b9fd9c8dc915fadacc24962436dd7aedff36 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 4 Oct 2019 11:04:10 -0700 Subject: Rename abc_* names/attributes to more precisely be abc9_* --- techlibs/ecp5/Makefile.inc | 12 +++++------ techlibs/ecp5/abc9_5g.box | 43 ++++++++++++++++++++++++++++++++++++++++ techlibs/ecp5/abc9_5g.lut | 25 +++++++++++++++++++++++ techlibs/ecp5/abc9_5g_nowide.lut | 12 +++++++++++ techlibs/ecp5/abc9_map.v | 24 ++++++++++++++++++++++ techlibs/ecp5/abc9_model.v | 5 +++++ techlibs/ecp5/abc9_unmap.v | 5 +++++ techlibs/ecp5/abc_5g.box | 43 ---------------------------------------- techlibs/ecp5/abc_5g.lut | 25 ----------------------- techlibs/ecp5/abc_5g_nowide.lut | 12 ----------- techlibs/ecp5/abc_map.v | 24 ---------------------- techlibs/ecp5/abc_model.v | 5 ----- techlibs/ecp5/abc_unmap.v | 5 ----- techlibs/ecp5/cells_sim.v | 12 +++++------ techlibs/ecp5/synth_ecp5.cc | 10 +++++----- 15 files changed, 131 insertions(+), 131 deletions(-) create mode 100644 techlibs/ecp5/abc9_5g.box create mode 100644 techlibs/ecp5/abc9_5g.lut create mode 100644 techlibs/ecp5/abc9_5g_nowide.lut create mode 100644 techlibs/ecp5/abc9_map.v create mode 100644 techlibs/ecp5/abc9_model.v create mode 100644 techlibs/ecp5/abc9_unmap.v delete mode 100644 techlibs/ecp5/abc_5g.box delete mode 100644 techlibs/ecp5/abc_5g.lut delete mode 100644 techlibs/ecp5/abc_5g_nowide.lut delete mode 100644 techlibs/ecp5/abc_map.v delete mode 100644 techlibs/ecp5/abc_model.v delete mode 100644 techlibs/ecp5/abc_unmap.v (limited to 'techlibs/ecp5') diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc index b03da164c..5832d07ee 100644 --- a/techlibs/ecp5/Makefile.inc +++ b/techlibs/ecp5/Makefile.inc @@ -15,12 +15,12 @@ $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/arith_map.v)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/latches_map.v)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/dsp_map.v)) -$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_map.v)) -$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_unmap.v)) -$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_model.v)) -$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g.box)) -$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g.lut)) -$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g_nowide.lut)) +$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_map.v)) +$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_unmap.v)) +$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_model.v)) +$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_5g.box)) +$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_5g.lut)) +$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_5g_nowide.lut)) EXTRA_OBJS += techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk .SECONDARY: techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk diff --git a/techlibs/ecp5/abc9_5g.box b/techlibs/ecp5/abc9_5g.box new file mode 100644 index 000000000..2bc945a54 --- /dev/null +++ b/techlibs/ecp5/abc9_5g.box @@ -0,0 +1,43 @@ +# NB: Inputs/Outputs must be ordered alphabetically +# (with exceptions for carry in/out) + +# Box 1 : CCU2C (2xCARRY + 2xLUT4) +# Outputs: S0, S1, COUT +# (NB: carry chain input/output must be last +# input/output and bus has been moved +# there overriding the otherwise +# alphabetical ordering) +# name ID w/b ins outs +CCU2C 1 1 9 3 + +#A0 A1 B0 B1 C0 C1 D0 D1 CIN +379 - 379 - 275 - 141 - 257 +630 379 630 379 526 275 392 141 273 +516 516 516 516 412 412 278 278 43 + +# Box 2 : TRELLIS_DPR16X4_COMB (16x4 dist ram) +# Outputs: DO0, DO1, DO2, DO3 +# name ID w/b ins outs +$__ABC9_DPR16X4_COMB 2 0 8 4 + +#A0 A1 A2 A3 RAD0 RAD1 RAD2 RAD3 +0 0 0 0 141 379 275 379 +0 0 0 0 141 379 275 379 +0 0 0 0 141 379 275 379 +0 0 0 0 141 379 275 379 + +# Box 3 : PFUMX (MUX2) +# Outputs: Z +# name ID w/b ins outs +PFUMX 3 1 3 1 + +#ALUT BLUT C0 +98 98 151 + +# Box 4 : L6MUX21 (MUX2) +# Outputs: Z +# name ID w/b ins outs +L6MUX21 4 1 3 1 + +#D0 D1 SD +140 141 148 diff --git a/techlibs/ecp5/abc9_5g.lut b/techlibs/ecp5/abc9_5g.lut new file mode 100644 index 000000000..e8aa9b35d --- /dev/null +++ b/techlibs/ecp5/abc9_5g.lut @@ -0,0 +1,25 @@ +# ECP5-5G LUT library for ABC +# Note that ECP5 architecture assigns difference +# in LUT input delay to interconnect, so this is +# considered too + + +# Simple LUTs +# area D C B A +1 1 141 +2 1 141 275 +3 1 141 275 379 +4 1 141 275 379 379 + +# LUT5 = 2x LUT4 + PFUMX +# area M0 D C B A +5 2 151 239 373 477 477 + +# LUT6 = 2x LUT5 + MUX2 +# area M1 M0 D C B A +6 4 148 292 380 514 618 618 + +# LUT7 = 2x LUT6 + MUX2 +# area M2 M1 M0 D C B A +7 8 148 289 433 521 655 759 759 + diff --git a/techlibs/ecp5/abc9_5g_nowide.lut b/techlibs/ecp5/abc9_5g_nowide.lut new file mode 100644 index 000000000..60352d892 --- /dev/null +++ b/techlibs/ecp5/abc9_5g_nowide.lut @@ -0,0 +1,12 @@ +# ECP5-5G LUT library for ABC +# Note that ECP5 architecture assigns difference +# in LUT input delay to interconnect, so this is +# considered too + + +# Simple LUTs +# area D C B A +1 1 141 +2 1 141 275 +3 1 141 275 379 +4 1 141 275 379 379 diff --git a/techlibs/ecp5/abc9_map.v b/techlibs/ecp5/abc9_map.v new file mode 100644 index 000000000..d8d70f9f6 --- /dev/null +++ b/techlibs/ecp5/abc9_map.v @@ -0,0 +1,24 @@ +// --------------------------------------- + +module TRELLIS_DPR16X4 ( + input [3:0] DI, + input [3:0] WAD, + input WRE, + input WCK, + input [3:0] RAD, + output [3:0] DO +); + parameter WCKMUX = "WCK"; + parameter WREMUX = "WRE"; + parameter [63:0] INITVAL = 64'h0000000000000000; + wire [3:0] \$DO ; + + TRELLIS_DPR16X4 #( + .WCKMUX(WCKMUX), .WREMUX(WREMUX), .INITVAL(INITVAL) + ) _TECHMAP_REPLACE_ ( + .DI(DI), .WAD(WAD), .WRE(WRE), .WCK(WCK), + .RAD(RAD), .DO(\$DO ) + ); + + \$__ABC9_DPR16X4_COMB do (.A(\$DO ), .S(RAD), .Y(DO)); +endmodule diff --git a/techlibs/ecp5/abc9_model.v b/techlibs/ecp5/abc9_model.v new file mode 100644 index 000000000..1dc8b5617 --- /dev/null +++ b/techlibs/ecp5/abc9_model.v @@ -0,0 +1,5 @@ +// --------------------------------------- + +(* abc9_box_id=2 *) +module \$__ABC9_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y); +endmodule diff --git a/techlibs/ecp5/abc9_unmap.v b/techlibs/ecp5/abc9_unmap.v new file mode 100644 index 000000000..9ae143c46 --- /dev/null +++ b/techlibs/ecp5/abc9_unmap.v @@ -0,0 +1,5 @@ +// --------------------------------------- + +module \$__ABC9_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y); + assign Y = A; +endmodule diff --git a/techlibs/ecp5/abc_5g.box b/techlibs/ecp5/abc_5g.box deleted file mode 100644 index a336b4a85..000000000 --- a/techlibs/ecp5/abc_5g.box +++ /dev/null @@ -1,43 +0,0 @@ -# NB: Inputs/Outputs must be ordered alphabetically -# (with exceptions for carry in/out) - -# Box 1 : CCU2C (2xCARRY + 2xLUT4) -# Outputs: S0, S1, COUT -# (NB: carry chain input/output must be last -# input/output and bus has been moved -# there overriding the otherwise -# alphabetical ordering) -# name ID w/b ins outs -CCU2C 1 1 9 3 - -#A0 A1 B0 B1 C0 C1 D0 D1 CIN -379 - 379 - 275 - 141 - 257 -630 379 630 379 526 275 392 141 273 -516 516 516 516 412 412 278 278 43 - -# Box 2 : TRELLIS_DPR16X4_COMB (16x4 dist ram) -# Outputs: DO0, DO1, DO2, DO3 -# name ID w/b ins outs -$__ABC_DPR16X4_COMB 2 0 8 4 - -#A0 A1 A2 A3 RAD0 RAD1 RAD2 RAD3 -0 0 0 0 141 379 275 379 -0 0 0 0 141 379 275 379 -0 0 0 0 141 379 275 379 -0 0 0 0 141 379 275 379 - -# Box 3 : PFUMX (MUX2) -# Outputs: Z -# name ID w/b ins outs -PFUMX 3 1 3 1 - -#ALUT BLUT C0 -98 98 151 - -# Box 4 : L6MUX21 (MUX2) -# Outputs: Z -# name ID w/b ins outs -L6MUX21 4 1 3 1 - -#D0 D1 SD -140 141 148 diff --git a/techlibs/ecp5/abc_5g.lut b/techlibs/ecp5/abc_5g.lut deleted file mode 100644 index e8aa9b35d..000000000 --- a/techlibs/ecp5/abc_5g.lut +++ /dev/null @@ -1,25 +0,0 @@ -# ECP5-5G LUT library for ABC -# Note that ECP5 architecture assigns difference -# in LUT input delay to interconnect, so this is -# considered too - - -# Simple LUTs -# area D C B A -1 1 141 -2 1 141 275 -3 1 141 275 379 -4 1 141 275 379 379 - -# LUT5 = 2x LUT4 + PFUMX -# area M0 D C B A -5 2 151 239 373 477 477 - -# LUT6 = 2x LUT5 + MUX2 -# area M1 M0 D C B A -6 4 148 292 380 514 618 618 - -# LUT7 = 2x LUT6 + MUX2 -# area M2 M1 M0 D C B A -7 8 148 289 433 521 655 759 759 - diff --git a/techlibs/ecp5/abc_5g_nowide.lut b/techlibs/ecp5/abc_5g_nowide.lut deleted file mode 100644 index 60352d892..000000000 --- a/techlibs/ecp5/abc_5g_nowide.lut +++ /dev/null @@ -1,12 +0,0 @@ -# ECP5-5G LUT library for ABC -# Note that ECP5 architecture assigns difference -# in LUT input delay to interconnect, so this is -# considered too - - -# Simple LUTs -# area D C B A -1 1 141 -2 1 141 275 -3 1 141 275 379 -4 1 141 275 379 379 diff --git a/techlibs/ecp5/abc_map.v b/techlibs/ecp5/abc_map.v deleted file mode 100644 index ffd25f06d..000000000 --- a/techlibs/ecp5/abc_map.v +++ /dev/null @@ -1,24 +0,0 @@ -// --------------------------------------- - -module TRELLIS_DPR16X4 ( - input [3:0] DI, - input [3:0] WAD, - input WRE, - input WCK, - input [3:0] RAD, - output [3:0] DO -); - parameter WCKMUX = "WCK"; - parameter WREMUX = "WRE"; - parameter [63:0] INITVAL = 64'h0000000000000000; - wire [3:0] \$DO ; - - TRELLIS_DPR16X4 #( - .WCKMUX(WCKMUX), .WREMUX(WREMUX), .INITVAL(INITVAL) - ) _TECHMAP_REPLACE_ ( - .DI(DI), .WAD(WAD), .WRE(WRE), .WCK(WCK), - .RAD(RAD), .DO(\$DO ) - ); - - \$__ABC_DPR16X4_COMB do (.A(\$DO ), .S(RAD), .Y(DO)); -endmodule diff --git a/techlibs/ecp5/abc_model.v b/techlibs/ecp5/abc_model.v deleted file mode 100644 index 56a733b75..000000000 --- a/techlibs/ecp5/abc_model.v +++ /dev/null @@ -1,5 +0,0 @@ -// --------------------------------------- - -(* abc_box_id=2 *) -module \$__ABC_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y); -endmodule diff --git a/techlibs/ecp5/abc_unmap.v b/techlibs/ecp5/abc_unmap.v deleted file mode 100644 index d43cdd93f..000000000 --- a/techlibs/ecp5/abc_unmap.v +++ /dev/null @@ -1,5 +0,0 @@ -// --------------------------------------- - -module \$__ABC_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y); - assign Y = A; -endmodule diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index db77dc127..f467218cc 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -9,19 +9,19 @@ module LUT4(input A, B, C, D, output Z); endmodule // --------------------------------------- -(* abc_box_id=4, lib_whitebox *) +(* abc9_box_id=4, lib_whitebox *) module L6MUX21 (input D0, D1, SD, output Z); assign Z = SD ? D1 : D0; endmodule // --------------------------------------- -(* abc_box_id=1, lib_whitebox *) +(* abc9_box_id=1, lib_whitebox *) module CCU2C( - (* abc_carry *) + (* abc9_carry *) input CIN, input A0, B0, C0, D0, A1, B1, C1, D1, output S0, S1, - (* abc_carry *) + (* abc9_carry *) output COUT ); parameter [15:0] INIT0 = 16'h0000; @@ -103,7 +103,7 @@ module TRELLIS_RAM16X2 ( endmodule // --------------------------------------- -(* abc_box_id=3, lib_whitebox *) +(* abc9_box_id=3, lib_whitebox *) module PFUMX (input ALUT, BLUT, C0, output Z); assign Z = C0 ? ALUT : BLUT; endmodule @@ -115,7 +115,7 @@ module TRELLIS_DPR16X4 ( input WRE, input WCK, input [3:0] RAD, - /* (* abc_arrival= *) */ + /* (* abc9_arrival= *) */ output [3:0] DO ); parameter WCKMUX = "WCK"; diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index 67d2f483c..80aa1dbc5 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -307,16 +307,16 @@ struct SynthEcp5Pass : public ScriptPass } std::string techmap_args = "-map +/ecp5/latches_map.v"; if (abc9) - techmap_args += " -map +/ecp5/abc_map.v -max_iter 1"; + techmap_args += " -map +/ecp5/abc9_map.v -max_iter 1"; run("techmap " + techmap_args); if (abc9) { - run("read_verilog -icells -lib +/ecp5/abc_model.v"); + run("read_verilog -icells -lib +/ecp5/abc9_model.v"); if (nowidelut) - run("abc9 -lut +/ecp5/abc_5g_nowide.lut -box +/ecp5/abc_5g.box -W 200"); + run("abc9 -lut +/ecp5/abc9_5g_nowide.lut -box +/ecp5/abc9_5g.box -W 200"); else - run("abc9 -lut +/ecp5/abc_5g.lut -box +/ecp5/abc_5g.box -W 200"); - run("techmap -map +/ecp5/abc_unmap.v"); + run("abc9 -lut +/ecp5/abc9_5g.lut -box +/ecp5/abc9_5g.box -W 200"); + run("techmap -map +/ecp5/abc9_unmap.v"); } else { if (nowidelut) run("abc -lut 4 -dress"); -- cgit v1.2.3 From 3b44e80d4babb57f4b7c5325f666f0731a4d878b Mon Sep 17 00:00:00 2001 From: David Shah Date: Thu, 10 Oct 2019 15:55:16 +0100 Subject: ecp5: Set syn_useioff on IO FFs to enable packing Signed-off-by: David Shah --- techlibs/ecp5/cells_ff.vh | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'techlibs/ecp5') diff --git a/techlibs/ecp5/cells_ff.vh b/techlibs/ecp5/cells_ff.vh index 0c9689ebd..501c1b3b2 100644 --- a/techlibs/ecp5/cells_ff.vh +++ b/techlibs/ecp5/cells_ff.vh @@ -23,15 +23,15 @@ module FD1S3JX(input PD, D, CK, output Q); parameter GSR = "ENABLED"; TRELLI // module FL1S3AY(); endmodule // Diamond I/O registers -module IFS1P3BX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule -module IFS1P3DX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule -module IFS1P3IX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule -module IFS1P3JX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule +module IFS1P3BX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="input" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule +module IFS1P3DX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="input" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule +module IFS1P3IX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="input" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule +module IFS1P3JX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="input" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule -module OFS1P3BX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule -module OFS1P3DX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule -module OFS1P3IX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule -module OFS1P3JX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule +module OFS1P3BX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="output" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule +module OFS1P3DX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="output" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule +module OFS1P3IX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="output" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule +module OFS1P3JX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="output" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule // TODO: Diamond I/O latches // module IFS1S1B(input PD, D, SCLK, output Q); endmodule -- cgit v1.2.3 From 7b1a6706d801773ec44d00bda0fd292c50fe39b7 Mon Sep 17 00:00:00 2001 From: David Shah Date: Thu, 10 Oct 2019 15:58:31 +0100 Subject: ecp5: Add attrmvcp to copy syn_useioff to driving FF Signed-off-by: David Shah --- techlibs/ecp5/synth_ecp5.cc | 1 + 1 file changed, 1 insertion(+) (limited to 'techlibs/ecp5') diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index 80aa1dbc5..a79dee31f 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -297,6 +297,7 @@ struct SynthEcp5Pass : public ScriptPass run("simplemap"); run("ecp5_ffinit"); run("ecp5_gsr"); + run("attrmvcp -copy -attr syn_useioff"); run("opt_clean"); } -- cgit v1.2.3 From e1d4e683b42bb1b75acb4054a94610cdc9fec0e7 Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 11 Oct 2019 14:50:33 +0100 Subject: ecp5: Add ECLKBRIDGECS blackbox Signed-off-by: David Shah --- techlibs/ecp5/cells_bb.v | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'techlibs/ecp5') diff --git a/techlibs/ecp5/cells_bb.v b/techlibs/ecp5/cells_bb.v index 0a5046db2..ae124e7a3 100644 --- a/techlibs/ecp5/cells_bb.v +++ b/techlibs/ecp5/cells_bb.v @@ -333,6 +333,13 @@ module ECLKSYNCB( ); endmodule +(* blackbox *) +module ECLKBRIDGECS( + input CLK0, CLK1, SEL, + output ECSOUT +); +endmodule + (* blackbox *) module DCCA( input CLKI, CE, -- cgit v1.2.3