From 44b5bd4b631874e5ed083d5de75f5b87431f935f Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 8 Sep 2014 17:09:39 +0200 Subject: Fixed simlib $macc model for xilinx xsim --- techlibs/common/simlib.v | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) (limited to 'techlibs/common') diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index dd12bd39f..0ad8d14b2 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -806,9 +806,23 @@ input [A_WIDTH-1:0] A; input [B_WIDTH-1:0] B; output reg [Y_WIDTH-1:0] Y; +// Xilinx XSIM does not like $clog2() below.. +function integer my_clog2; + input integer v; + begin + if (v > 0) + v = v - 1; + my_clog2 = 0; + while (v) begin + v = v >> 1; + my_clog2 = my_clog2 + 1; + end + end +endfunction + localparam integer num_bits = CONFIG[3:0]; localparam integer num_ports = (CONFIG_WIDTH-4) / (2 + 2*num_bits); -localparam integer num_abits = $clog2(A_WIDTH) > 0 ? $clog2(A_WIDTH) : 1; +localparam integer num_abits = my_clog2(A_WIDTH) > 0 ? my_clog2(A_WIDTH) : 1; function [2*num_ports*num_abits-1:0] get_port_offsets; input [CONFIG_WIDTH-1:0] cfg; -- cgit v1.2.3