From fd7921776387a05edadcc90d1300670d49a73d68 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Thu, 27 May 2021 20:54:29 +0200
Subject: Add v2 memory cells.
---
passes/cmds/torder.cc | 2 +-
passes/opt/opt_clean.cc | 4 ++--
passes/opt/opt_expr.cc | 2 +-
passes/opt/opt_reduce.cc | 4 ++--
passes/opt/share.cc | 9 ++++++---
passes/opt/wreduce.cc | 2 +-
passes/techmap/extract.cc | 1 +
7 files changed, 14 insertions(+), 10 deletions(-)
(limited to 'passes')
diff --git a/passes/cmds/torder.cc b/passes/cmds/torder.cc
index 9fc7f2e9c..1620c0bca 100644
--- a/passes/cmds/torder.cc
+++ b/passes/cmds/torder.cc
@@ -83,7 +83,7 @@ struct TorderPass : public Pass {
if (!noautostop && yosys_celltypes.cell_known(cell->type)) {
if (conn.first.in(ID::Q, ID::CTRL_OUT, ID::RD_DATA))
continue;
- if (cell->type == ID($memrd) && conn.first == ID::DATA)
+ if (cell->type.in(ID($memrd), ID($memrd_v2)) && conn.first == ID::DATA)
continue;
}
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index c3a0928ef..08e9d6b79 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -117,7 +117,7 @@ void rmunused_module_cells(Module *module, bool verbose)
}
for (Cell *cell : module->cells()) {
- if (cell->type.in(ID($memwr), ID($meminit), ID($meminit_v2))) {
+ if (cell->type.in(ID($memwr), ID($memwr_v2), ID($meminit), ID($meminit_v2))) {
IdString mem_id = cell->getParam(ID::MEMID).decode_string();
mem2cells[mem_id].insert(cell);
}
@@ -167,7 +167,7 @@ void rmunused_module_cells(Module *module, bool verbose)
for (auto bit : sigmap(it.second))
bits.insert(bit);
- if (cell->type == ID($memrd)) {
+ if (cell->type.in(ID($memrd), ID($memrd_v2))) {
IdString mem_id = cell->getParam(ID::MEMID).decode_string();
if (mem_unused.count(mem_id)) {
mem_unused.erase(mem_id);
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index b7bbb2adf..cdd821c52 100644
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -441,7 +441,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (!noclkinv)
{
- if (cell->type.in(ID($dff), ID($dffe), ID($dffsr), ID($dffsre), ID($adff), ID($adffe), ID($sdff), ID($sdffe), ID($sdffce), ID($fsm), ID($memrd), ID($memwr)))
+ if (cell->type.in(ID($dff), ID($dffe), ID($dffsr), ID($dffsre), ID($adff), ID($adffe), ID($sdff), ID($sdffe), ID($sdffce), ID($fsm), ID($memrd), ID($memrd_v2), ID($memwr), ID($memwr_v2)))
handle_polarity_inv(cell, ID::CLK, ID::CLK_POLARITY, assign_map, invert_map);
if (cell->type.in(ID($sr), ID($dffsr), ID($dffsre), ID($dlatchsr))) {
diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc
index 15b2772c7..b558f547e 100644
--- a/passes/opt/opt_reduce.cc
+++ b/passes/opt/opt_reduce.cc
@@ -254,9 +254,9 @@ struct OptReduceWorker
SigPool mem_wren_sigs;
for (auto &cell_it : module->cells_) {
RTLIL::Cell *cell = cell_it.second;
- if (cell->type == ID($mem))
+ if (cell->type.in(ID($mem), ID($mem_v2)))
mem_wren_sigs.add(assign_map(cell->getPort(ID::WR_EN)));
- if (cell->type == ID($memwr))
+ if (cell->type.in(ID($memwr), ID($memwr_v2)))
mem_wren_sigs.add(assign_map(cell->getPort(ID::EN)));
}
for (auto &cell_it : module->cells_) {
diff --git a/passes/opt/share.cc b/passes/opt/share.cc
index ee1acfb7f..abef71937 100644
--- a/passes/opt/share.cc
+++ b/passes/opt/share.cc
@@ -366,7 +366,7 @@ struct ShareWorker
continue;
}
- if (cell->type == ID($memrd)) {
+ if (cell->type.in(ID($memrd), ID($memrd_v2))) {
if (cell->parameters.at(ID::CLK_ENABLE).as_bool())
continue;
if (config.opt_aggressive || !modwalker.sigmap(cell->getPort(ID::ADDR)).is_fully_const())
@@ -399,11 +399,14 @@ struct ShareWorker
if (c1->type != c2->type)
return false;
- if (c1->type == ID($memrd))
+ if (c1->type.in(ID($memrd), ID($memrd_v2)))
{
if (c1->parameters.at(ID::MEMID).decode_string() != c2->parameters.at(ID::MEMID).decode_string())
return false;
+ if (c1->parameters.at(ID::WIDTH) != c2->parameters.at(ID::WIDTH))
+ return false;
+
return true;
}
@@ -703,7 +706,7 @@ struct ShareWorker
return supercell;
}
- if (c1->type == ID($memrd))
+ if (c1->type.in(ID($memrd), ID($memrd_v2)))
{
RTLIL::Cell *supercell = module->addCell(NEW_ID, c1);
RTLIL::SigSpec addr1 = c1->getPort(ID::ADDR);
diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc
index f6bf8b51a..aaad28ef0 100644
--- a/passes/opt/wreduce.cc
+++ b/passes/opt/wreduce.cc
@@ -558,7 +558,7 @@ struct WreducePass : public Pass {
}
}
- if (!opt_memx && c->type.in(ID($memrd), ID($memwr), ID($meminit), ID($meminit_v2))) {
+ if (!opt_memx && c->type.in(ID($memrd), ID($memrd_v2), ID($memwr), ID($memwr_v2), ID($meminit), ID($meminit_v2))) {
IdString memid = c->getParam(ID::MEMID).decode_string();
RTLIL::Memory *mem = module->memories.at(memid);
if (mem->start_offset >= 0) {
diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc
index eb6b3b858..137d22170 100644
--- a/passes/techmap/extract.cc
+++ b/passes/techmap/extract.cc
@@ -74,6 +74,7 @@ public:
param_int(ID::CTRL_IN_WIDTH)
param_int(ID::CTRL_OUT_WIDTH)
param_int(ID::OFFSET)
+ param_int(ID::PORTID)
param_int(ID::PRIORITY)
param_int(ID::RD_PORTS)
param_int(ID::SIZE)
--
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