From 43081337fa4a85cd4a1a007576eaf945816bd576 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 6 Aug 2019 16:04:21 -0700 Subject: Cleanup opt_expr.cc --- passes/opt/opt_expr.cc | 65 +++++++++++++++++++++++--------------------------- 1 file changed, 30 insertions(+), 35 deletions(-) (limited to 'passes') diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 512ef0cbf..ef4b8b57a 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -367,10 +367,11 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons for (auto cell : module->cells()) if (design->selected(module, cell) && cell->type[0] == '$') { - if ((cell->type == "$_NOT_" || cell->type == "$not" || cell->type == "$logic_not") && + if (cell->type.in("$_NOT_", "$not", "$logic_not") && cell->getPort("\\A").size() == 1 && cell->getPort("\\Y").size() == 1) invert_map[assign_map(cell->getPort("\\Y"))] = assign_map(cell->getPort("\\A")); - if ((cell->type == "$mux" || cell->type == "$_MUX_") && cell->getPort("\\A") == SigSpec(State::S1) && cell->getPort("\\B") == SigSpec(State::S0)) + if (cell->type.in("$mux", "$_MUX_") && + cell->getPort("\\A") == SigSpec(State::S1) && cell->getPort("\\B") == SigSpec(State::S0)) invert_map[assign_map(cell->getPort("\\Y"))] = assign_map(cell->getPort("\\S")); if (ct_combinational.cell_known(cell->type)) for (auto &conn : cell->connections()) { @@ -512,13 +513,11 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons if (do_fine) { - if (cell->type == "$not" || cell->type == "$pos" || - cell->type == "$and" || cell->type == "$or" || cell->type == "$xor" || cell->type == "$xnor") + if (cell->type.in("$not", "$pos", "$and", "$or", "$xor", "$xnor")) if (group_cell_inputs(module, cell, true, assign_map)) goto next_cell; - if (cell->type == "$logic_not" || cell->type == "$logic_and" || cell->type == "$logic_or" || - cell->type == "$reduce_or" || cell->type == "$reduce_and" || cell->type == "$reduce_bool") + if (cell->type.in("$logic_not", "$logic_and", "$logic_or", "$reduce_or", "$reduce_and", "$reduce_bool")) { SigBit neutral_bit = cell->type == "$reduce_and" ? State::S1 : State::S0; @@ -541,7 +540,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons } } - if (cell->type == "$logic_and" || cell->type == "$logic_or") + if (cell->type.in("$logic_and", "$logic_or")) { SigBit neutral_bit = State::S0; @@ -590,7 +589,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons } } - if (cell->type == "$logic_not" || cell->type == "$logic_and" || cell->type == "$logic_or" || cell->type == "$reduce_or" || cell->type == "$reduce_bool") + if (cell->type.in("$logic_not", "$logic_and", "$logic_or", "$reduce_or", "$reduce_bool")) { RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A")); @@ -616,7 +615,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons } } - if (cell->type == "$logic_and" || cell->type == "$logic_or") + if (cell->type.in("$logic_and", "$logic_or")) { RTLIL::SigSpec sig_b = assign_map(cell->getPort("\\B")); @@ -643,16 +642,13 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons } } - if (cell->type == "$reduce_xor" || cell->type == "$reduce_xnor" || cell->type == "$shift" || cell->type == "$shiftx" || - cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr" || - cell->type == "$lt" || cell->type == "$le" || cell->type == "$ge" || cell->type == "$gt" || - cell->type == "$neg" || cell->type == "$add" || cell->type == "$sub" || - cell->type == "$mul" || cell->type == "$div" || cell->type == "$mod" || cell->type == "$pow") + if (cell->type.in("$reduce_xor", "$reduce_xnor", "$shift", "$shiftx", "$shl", "$shr", "$sshl", "$sshr", + "$lt", "$le", "$ge", "$gt", "$neg", "$add", "$sub", "$mul", "$div", "$mod", "$pow")) { RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A")); RTLIL::SigSpec sig_b = cell->hasPort("\\B") ? assign_map(cell->getPort("\\B")) : RTLIL::SigSpec(); - if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr" || cell->type == "$shift" || cell->type == "$shiftx") + if (cell->type.in("$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx")) sig_a = RTLIL::SigSpec(); for (auto &bit : sig_a.to_sigbit_vector()) @@ -667,8 +663,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons found_the_x_bit: cover_list("opt.opt_expr.xbit", "$reduce_xor", "$reduce_xnor", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", "$lt", "$le", "$ge", "$gt", "$neg", "$add", "$sub", "$mul", "$div", "$mod", "$pow", cell->type.str()); - if (cell->type == "$reduce_xor" || cell->type == "$reduce_xnor" || - cell->type == "$lt" || cell->type == "$le" || cell->type == "$ge" || cell->type == "$gt") + if (cell->type.in("$reduce_xor", "$reduce_xnor", "$lt", "$le", "$ge", "$gt")) replace_cell(assign_map, module, cell, "x-bit in input", "\\Y", RTLIL::State::Sx); else replace_cell(assign_map, module, cell, "x-bit in input", "\\Y", RTLIL::SigSpec(RTLIL::State::Sx, cell->getPort("\\Y").size())); @@ -676,14 +671,14 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons } } - if ((cell->type == "$_NOT_" || cell->type == "$not" || cell->type == "$logic_not") && cell->getPort("\\Y").size() == 1 && + if (cell->type.in("$_NOT_", "$not", "$logic_not") && cell->getPort("\\Y").size() == 1 && invert_map.count(assign_map(cell->getPort("\\A"))) != 0) { cover_list("opt.opt_expr.invert.double", "$_NOT_", "$not", "$logic_not", cell->type.str()); replace_cell(assign_map, module, cell, "double_invert", "\\Y", invert_map.at(assign_map(cell->getPort("\\A")))); goto next_cell; } - if ((cell->type == "$_MUX_" || cell->type == "$mux") && invert_map.count(assign_map(cell->getPort("\\S"))) != 0) { + if (cell->type.in("$_MUX_", "$mux") && invert_map.count(assign_map(cell->getPort("\\S"))) != 0) { cover_list("opt.opt_expr.invert.muxsel", "$_MUX_", "$mux", cell->type.str()); log_debug("Optimizing away select inverter for %s cell `%s' in module `%s'.\n", log_id(cell->type), log_id(cell), log_id(module)); RTLIL::SigSpec tmp = cell->getPort("\\A"); @@ -786,7 +781,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons } } - if (cell->type == "$_TBUF_" || cell->type == "$tribuf") { + if (cell->type.in("$_TBUF_", "$tribuf")) { RTLIL::SigSpec input = cell->getPort(cell->type == "$_TBUF_" ? "\\E" : "\\EN"); RTLIL::SigSpec a = cell->getPort("\\A"); assign_map.apply(input); @@ -803,7 +798,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons } } - if (cell->type == "$eq" || cell->type == "$ne" || cell->type == "$eqx" || cell->type == "$nex") + if (cell->type.in("$eq", "$ne", "$eqx", "$nex")) { RTLIL::SigSpec a = cell->getPort("\\A"); RTLIL::SigSpec b = cell->getPort("\\B"); @@ -820,7 +815,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons for (int i = 0; i < GetSize(a); i++) { if (a[i].wire == NULL && b[i].wire == NULL && a[i] != b[i] && a[i].data <= RTLIL::State::S1 && b[i].data <= RTLIL::State::S1) { cover_list("opt.opt_expr.eqneq.isneq", "$eq", "$ne", "$eqx", "$nex", cell->type.str()); - RTLIL::SigSpec new_y = RTLIL::SigSpec((cell->type == "$eq" || cell->type == "$eqx") ? RTLIL::State::S0 : RTLIL::State::S1); + RTLIL::SigSpec new_y = RTLIL::SigSpec(cell->type.in("$eq", "$eqx") ? RTLIL::State::S0 : RTLIL::State::S1); new_y.extend_u0(cell->parameters["\\Y_WIDTH"].as_int(), false); replace_cell(assign_map, module, cell, "isneq", "\\Y", new_y); goto next_cell; @@ -833,7 +828,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons if (new_a.size() == 0) { cover_list("opt.opt_expr.eqneq.empty", "$eq", "$ne", "$eqx", "$nex", cell->type.str()); - RTLIL::SigSpec new_y = RTLIL::SigSpec((cell->type == "$eq" || cell->type == "$eqx") ? RTLIL::State::S1 : RTLIL::State::S0); + RTLIL::SigSpec new_y = RTLIL::SigSpec(cell->type.in("$eq", "$eqx") ? RTLIL::State::S1 : RTLIL::State::S0); new_y.extend_u0(cell->parameters["\\Y_WIDTH"].as_int(), false); replace_cell(assign_map, module, cell, "empty", "\\Y", new_y); goto next_cell; @@ -848,7 +843,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons } } - if ((cell->type == "$eq" || cell->type == "$ne") && cell->parameters["\\Y_WIDTH"].as_int() == 1 && + if (cell->type.in("$eq", "$ne") && cell->parameters["\\Y_WIDTH"].as_int() == 1 && cell->parameters["\\A_WIDTH"].as_int() == 1 && cell->parameters["\\B_WIDTH"].as_int() == 1) { RTLIL::SigSpec a = assign_map(cell->getPort("\\A")); @@ -878,7 +873,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons } } - if ((cell->type == "$eq" || cell->type == "$ne") && + if (cell->type.in("$eq", "$ne") && (assign_map(cell->getPort("\\A")).is_fully_zero() || assign_map(cell->getPort("\\B")).is_fully_zero())) { cover_list("opt.opt_expr.eqneq.cmpzero", "$eq", "$ne", cell->type.str()); @@ -937,7 +932,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons bool identity_wrt_b = false; bool arith_inverse = false; - if (cell->type == "$add" || cell->type == "$sub" || cell->type == "$or" || cell->type == "$xor") + if (cell->type.in("$add", "$sub", "$or", "$xor")) { RTLIL::SigSpec a = assign_map(cell->getPort("\\A")); RTLIL::SigSpec b = assign_map(cell->getPort("\\B")); @@ -949,7 +944,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons identity_wrt_a = true; } - if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr" || cell->type == "$shift" || cell->type == "$shiftx") + if (cell->type.in("$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx")) { RTLIL::SigSpec b = assign_map(cell->getPort("\\B")); @@ -1004,15 +999,15 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons } } - if (mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && - cell->getPort("\\A") == RTLIL::SigSpec(0, 1) && cell->getPort("\\B") == RTLIL::SigSpec(1, 1)) { + if (mux_bool && cell->type.in("$mux", "$_MUX_") && + cell->getPort("\\A") == State::S0 && cell->getPort("\\B") == State::S1) { cover_list("opt.opt_expr.mux_bool", "$mux", "$_MUX_", cell->type.str()); replace_cell(assign_map, module, cell, "mux_bool", "\\Y", cell->getPort("\\S")); goto next_cell; } - if (mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && - cell->getPort("\\A") == RTLIL::SigSpec(1, 1) && cell->getPort("\\B") == RTLIL::SigSpec(0, 1)) { + if (mux_bool && cell->type.in("$mux", "$_MUX_") && + cell->getPort("\\A") == State::S1 && cell->getPort("\\B") == State::S0) { cover_list("opt.opt_expr.mux_invert", "$mux", "$_MUX_", cell->type.str()); log_debug("Replacing %s cell `%s' in module `%s' with inverter.\n", log_id(cell->type), log_id(cell), log_id(module)); cell->setPort("\\A", cell->getPort("\\S")); @@ -1031,7 +1026,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons goto next_cell; } - if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->getPort("\\A") == RTLIL::SigSpec(0, 1)) { + if (consume_x && mux_bool && cell->type.in("$mux", "$_MUX_") && cell->getPort("\\A") == State::S0) { cover_list("opt.opt_expr.mux_and", "$mux", "$_MUX_", cell->type.str()); log_debug("Replacing %s cell `%s' in module `%s' with and-gate.\n", log_id(cell->type), log_id(cell), log_id(module)); cell->setPort("\\A", cell->getPort("\\S")); @@ -1051,7 +1046,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons goto next_cell; } - if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->getPort("\\B") == RTLIL::SigSpec(1, 1)) { + if (consume_x && mux_bool && cell->type.in("$mux", "$_MUX_") && cell->getPort("\\B") == State::S1) { cover_list("opt.opt_expr.mux_or", "$mux", "$_MUX_", cell->type.str()); log_debug("Replacing %s cell `%s' in module `%s' with or-gate.\n", log_id(cell->type), log_id(cell), log_id(module)); cell->setPort("\\B", cell->getPort("\\S")); @@ -1071,7 +1066,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons goto next_cell; } - if (mux_undef && (cell->type == "$mux" || cell->type == "$pmux")) { + if (mux_undef && cell->type.in("$mux", "$pmux")) { RTLIL::SigSpec new_a, new_b, new_s; int width = cell->getPort("\\A").size(); if ((cell->getPort("\\A").is_fully_undef() && cell->getPort("\\B").is_fully_undef()) || @@ -1413,7 +1408,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons } // simplify comparisons - if (do_fine && (cell->type == "$lt" || cell->type == "$ge" || cell->type == "$gt" || cell->type == "$le")) + if (do_fine && cell->type.in("$lt", "$ge", "$gt", "$le")) { IdString cmp_type = cell->type; SigSpec var_sig = cell->getPort("\\A"); -- cgit v1.2.3 From 3486235338faa1377bb4e1a8981a45b4ee6edfa9 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 6 Aug 2019 16:18:18 -0700 Subject: Make liberal use of IdString.in() --- passes/fsm/fsm_expand.cc | 2 +- passes/memory/memory_dff.cc | 2 +- passes/memory/memory_share.cc | 6 +++--- passes/opt/opt_merge.cc | 8 ++++---- passes/opt/opt_muxtree.cc | 2 +- passes/opt/opt_rmdff.cc | 6 +++--- passes/opt/share.cc | 4 ++-- passes/proc/proc_arst.cc | 4 ++-- passes/techmap/abc.cc | 16 ++++++++-------- passes/techmap/abc9.cc | 8 ++++---- passes/techmap/aigmap.cc | 2 +- passes/techmap/deminout.cc | 2 +- passes/techmap/dff2dffe.cc | 4 ++-- passes/techmap/simplemap.cc | 2 +- 14 files changed, 34 insertions(+), 34 deletions(-) (limited to 'passes') diff --git a/passes/fsm/fsm_expand.cc b/passes/fsm/fsm_expand.cc index c34d0c15c..1610ec751 100644 --- a/passes/fsm/fsm_expand.cc +++ b/passes/fsm/fsm_expand.cc @@ -50,7 +50,7 @@ struct FsmExpand if (full_mode || cell->type == "$_MUX_") return true; - if (cell->type == "$mux" || cell->type == "$pmux") + if (cell->type.in("$mux", "$pmux")) if (cell->getPort("\\A").size() < 2) return true; diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index 32b97f27a..be4b3c100 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -262,7 +262,7 @@ struct MemoryDffWorker mux_cells_a[sigmap(cell->getPort("\\A"))] = cell; mux_cells_b[sigmap(cell->getPort("\\B"))] = cell; } - if (cell->type == "$not" || cell->type == "$_NOT_" || (cell->type == "$logic_not" && GetSize(cell->getPort("\\A")) == 1)) { + if (cell->type.in("$not", "$_NOT_") || (cell->type == "$logic_not" && GetSize(cell->getPort("\\A")) == 1)) { SigSpec sig_a = cell->getPort("\\A"); SigSpec sig_y = cell->getPort("\\Y"); if (cell->type == "$not") diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index 172afe0cb..eb912cfd4 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -155,7 +155,7 @@ struct MemoryShareWorker { bool ignore_data_port = false; - if (cell->type == "$mux" || cell->type == "$pmux") + if (cell->type.in("$mux", "$pmux")) { std::vector sig_a = sigmap(cell->getPort("\\A")); std::vector sig_b = sigmap(cell->getPort("\\B")); @@ -173,7 +173,7 @@ struct MemoryShareWorker continue; } - if ((cell->type == "$memwr" || cell->type == "$memrd") && + if (cell->type.in("$memwr", "$memrd") && cell->parameters.at("\\MEMID").decode_string() == memid) ignore_data_port = true; @@ -690,7 +690,7 @@ struct MemoryShareWorker sigmap_xmux.add(cell->getPort("\\Y"), sig_a); } - if (cell->type == "$mux" || cell->type == "$pmux") + if (cell->type.in("$mux", "$pmux")) { std::vector sig_y = sigmap(cell->getPort("\\Y")); for (int i = 0; i < int(sig_y.size()); i++) diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc index 7567d4657..8964171e6 100644 --- a/passes/opt/opt_merge.cc +++ b/passes/opt/opt_merge.cc @@ -94,8 +94,8 @@ struct OptMergeWorker const dict *conn = &cell->connections(); dict alt_conn; - if (cell->type == "$and" || cell->type == "$or" || cell->type == "$xor" || cell->type == "$xnor" || cell->type == "$add" || cell->type == "$mul" || - cell->type == "$logic_and" || cell->type == "$logic_or" || cell->type == "$_AND_" || cell->type == "$_OR_" || cell->type == "$_XOR_") { + if (cell->type.in("$and", "$or", "$xor", "$xnor", "$add", "$mul", + "$logic_and", "$logic_or", "$_AND_", "$_OR_", "$_XOR_")) { alt_conn = *conn; if (assign_map(alt_conn.at("\\A")) < assign_map(alt_conn.at("\\B"))) { alt_conn["\\A"] = conn->at("\\B"); @@ -103,13 +103,13 @@ struct OptMergeWorker } conn = &alt_conn; } else - if (cell->type == "$reduce_xor" || cell->type == "$reduce_xnor") { + if (cell->type.in("$reduce_xor", "$reduce_xnor")) { alt_conn = *conn; assign_map.apply(alt_conn.at("\\A")); alt_conn.at("\\A").sort(); conn = &alt_conn; } else - if (cell->type == "$reduce_and" || cell->type == "$reduce_or" || cell->type == "$reduce_bool") { + if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_bool")) { alt_conn = *conn; assign_map.apply(alt_conn.at("\\A")); alt_conn.at("\\A").sort_and_unify(); diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc index 6511e091b..4b96fe524 100644 --- a/passes/opt/opt_muxtree.cc +++ b/passes/opt/opt_muxtree.cc @@ -84,7 +84,7 @@ struct OptMuxtreeWorker // .const_deactivated for (auto cell : module->cells()) { - if (cell->type == "$mux" || cell->type == "$pmux") + if (cell->type.in("$mux", "$pmux")) { RTLIL::SigSpec sig_a = cell->getPort("\\A"); RTLIL::SigSpec sig_b = cell->getPort("\\B"); diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc index be6ac2d30..d712736c1 100644 --- a/passes/opt/opt_rmdff.cc +++ b/passes/opt/opt_rmdff.cc @@ -71,7 +71,7 @@ bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell) pol_set = cell->type[12] == 'P' ? State::S1 : State::S0; pol_clr = cell->type[13] == 'P' ? State::S1 : State::S0; } else - if (cell->type == "$dffsr" || cell->type == "$dlatchsr") { + if (cell->type.in("$dffsr", "$dlatchsr")) { pol_set = cell->parameters["\\SET_POLARITY"].as_bool() ? State::S1 : State::S0; pol_clr = cell->parameters["\\CLR_POLARITY"].as_bool() ? State::S1 : State::S0; } else @@ -137,7 +137,7 @@ bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell) return true; } - if (cell->type == "$dffsr" || cell->type == "$dlatchsr") + if (cell->type.in("$dffsr", "$dlatchsr")) { cell->setParam("\\WIDTH", GetSize(sig_d)); cell->setPort("\\SET", sig_set); @@ -624,7 +624,7 @@ struct OptRmdffPass : public Pass { } } - if (cell->type == "$mux" || cell->type == "$pmux") { + if (cell->type.in("$mux", "$pmux")) { if (cell->getPort("\\A").size() == cell->getPort("\\B").size()) mux_drivers.insert(assign_map(cell->getPort("\\Y")), cell); continue; diff --git a/passes/opt/share.cc b/passes/opt/share.cc index c85c27427..7f66f749f 100644 --- a/passes/opt/share.cc +++ b/passes/opt/share.cc @@ -376,13 +376,13 @@ struct ShareWorker continue; } - if (cell->type == "$mul" || cell->type == "$div" || cell->type == "$mod") { + if (cell->type.in("$mul", "$div", "$mod")) { if (config.opt_aggressive || cell->parameters.at("\\Y_WIDTH").as_int() >= 4) shareable_cells.insert(cell); continue; } - if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr") { + if (cell->type.in("$shl", "$shr", "$sshl", "$sshr")) { if (config.opt_aggressive || cell->parameters.at("\\Y_WIDTH").as_int() >= 8) shareable_cells.insert(cell); continue; diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc index d069f152a..c606deb88 100644 --- a/passes/proc/proc_arst.cc +++ b/passes/proc/proc_arst.cc @@ -55,7 +55,7 @@ bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSpec ref, return check_signal(mod, cell->getPort("\\A"), ref, polarity); } - if ((cell->type == "$eq" || cell->type == "$eqx") && cell->getPort("\\Y") == signal) { + if (cell->type.in("$eq", "$eqx") && cell->getPort("\\Y") == signal) { if (cell->getPort("\\A").is_fully_const()) { if (!cell->getPort("\\A").as_bool()) polarity = !polarity; @@ -68,7 +68,7 @@ bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSpec ref, } } - if ((cell->type == "$ne" || cell->type == "$nex") && cell->getPort("\\Y") == signal) { + if (cell->type.in("$ne", "$nex") && cell->getPort("\\Y") == signal) { if (cell->getPort("\\A").is_fully_const()) { if (cell->getPort("\\A").as_bool()) polarity = !polarity; diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index 41a05c619..73f63a4e1 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -166,7 +166,7 @@ void mark_port(RTLIL::SigSpec sig) void extract_cell(RTLIL::Cell *cell, bool keepff) { - if (cell->type == "$_DFF_N_" || cell->type == "$_DFF_P_") + if (cell->type.in("$_DFF_N_", "$_DFF_P_")) { if (clk_polarity != (cell->type == "$_DFF_P_")) return; @@ -177,11 +177,11 @@ void extract_cell(RTLIL::Cell *cell, bool keepff) goto matching_dff; } - if (cell->type == "$_DFFE_NN_" || cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_") + if (cell->type.in("$_DFFE_NN_", "$_DFFE_NP_", "$_DFFE_PN_", "$_DFFE_PP_")) { - if (clk_polarity != (cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_")) + if (clk_polarity != cell->type.in("$_DFFE_PN_", "$_DFFE_PP_")) return; - if (en_polarity != (cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PP_")) + if (en_polarity != cell->type.in("$_DFFE_NP_", "$_DFFE_PP_")) return; if (clk_sig != assign_map(cell->getPort("\\C"))) return; @@ -1824,15 +1824,15 @@ struct AbcPass : public Pass { } } - if (cell->type == "$_DFF_N_" || cell->type == "$_DFF_P_") + if (cell->type.in("$_DFF_N_", "$_DFF_P_")) { key = clkdomain_t(cell->type == "$_DFF_P_", assign_map(cell->getPort("\\C")), true, RTLIL::SigSpec()); } else - if (cell->type == "$_DFFE_NN_" || cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_") + if (cell->type.in("$_DFFE_NN_", "$_DFFE_NP_" "$_DFFE_PN_", "$_DFFE_PP_")) { - bool this_clk_pol = cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_"; - bool this_en_pol = cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PP_"; + bool this_clk_pol = cell->type.in("$_DFFE_PN_", "$_DFFE_PP_"); + bool this_en_pol = cell->type.in("$_DFFE_NP_", "$_DFFE_PP_"); key = clkdomain_t(this_clk_pol, assign_map(cell->getPort("\\C")), this_en_pol, assign_map(cell->getPort("\\E"))); } else diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 658bb1225..34919cf07 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -1137,15 +1137,15 @@ struct Abc9Pass : public Pass { } } - if (cell->type == "$_DFF_N_" || cell->type == "$_DFF_P_") + if (cell->type.in("$_DFF_N_", "$_DFF_P_")) { key = clkdomain_t(cell->type == "$_DFF_P_", assign_map(cell->getPort("\\C")), true, RTLIL::SigSpec()); } else - if (cell->type == "$_DFFE_NN_" || cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_") + if (cell->type.in("$_DFFE_NN_", "$_DFFE_NP_", "$_DFFE_PN_", "$_DFFE_PP_")) { - bool this_clk_pol = cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_"; - bool this_en_pol = cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PP_"; + bool this_clk_pol = cell->type.in("$_DFFE_PN_", "$_DFFE_PP_"); + bool this_en_pol = cell->type.in("$_DFFE_NP_", "$_DFFE_PP_"); key = clkdomain_t(this_clk_pol, assign_map(cell->getPort("\\C")), this_en_pol, assign_map(cell->getPort("\\E"))); } else diff --git a/passes/techmap/aigmap.cc b/passes/techmap/aigmap.cc index 35df2ff79..2423676cb 100644 --- a/passes/techmap/aigmap.cc +++ b/passes/techmap/aigmap.cc @@ -66,7 +66,7 @@ struct AigmapPass : public Pass { { Aig aig(cell); - if (cell->type == "$_AND_" || cell->type == "$_NOT_") + if (cell->type.in("$_AND_", "$_NOT_")) aig.name.clear(); if (nand_mode && cell->type == "$_NAND_") diff --git a/passes/techmap/deminout.cc b/passes/techmap/deminout.cc index 47d0ff416..142d12bdc 100644 --- a/passes/techmap/deminout.cc +++ b/passes/techmap/deminout.cc @@ -85,7 +85,7 @@ struct DeminoutPass : public Pass { if (conn.first == "\\Y" && cell->type.in("$mux", "$pmux", "$_MUX_", "$_TBUF_", "$tribuf")) { - bool tribuf = (cell->type == "$_TBUF_" || cell->type == "$tribuf"); + bool tribuf = cell->type.in("$_TBUF_", "$tribuf"); if (!tribuf) { for (auto &c : cell->connections()) { diff --git a/passes/techmap/dff2dffe.cc b/passes/techmap/dff2dffe.cc index 7e1040963..44bc14628 100644 --- a/passes/techmap/dff2dffe.cc +++ b/passes/techmap/dff2dffe.cc @@ -52,13 +52,13 @@ struct Dff2dffeWorker } for (auto cell : module->cells()) { - if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$_MUX_") { + if (cell->type.in("$mux", "$pmux", "$_MUX_")) { RTLIL::SigSpec sig_y = sigmap(cell->getPort("\\Y")); for (int i = 0; i < GetSize(sig_y); i++) bit2mux[sig_y[i]] = cell_int_t(cell, i); } if (direct_dict.empty()) { - if (cell->type == "$dff" || cell->type == "$_DFF_N_" || cell->type == "$_DFF_P_") + if (cell->type.in("$dff", "$_DFF_N_", "$_DFF_P_")) dff_cells.push_back(cell); } else { if (direct_dict.count(cell->type)) diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc index f3da80c66..6c70ffd4f 100644 --- a/passes/techmap/simplemap.cc +++ b/passes/techmap/simplemap.cc @@ -245,7 +245,7 @@ void simplemap_eqne(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::SigSpec sig_b = cell->getPort("\\B"); RTLIL::SigSpec sig_y = cell->getPort("\\Y"); bool is_signed = cell->parameters.at("\\A_SIGNED").as_bool(); - bool is_ne = cell->type == "$ne" || cell->type == "$nex"; + bool is_ne = cell->type.in("$ne", "$nex"); RTLIL::SigSpec xor_out = module->addWire(NEW_ID, max(GetSize(sig_a), GetSize(sig_b))); RTLIL::Cell *xor_cell = module->addXor(NEW_ID, sig_a, sig_b, xor_out, is_signed); -- cgit v1.2.3 From 046e1a52147dd4a0e1f23e4aa7cb71b0a4d1b497 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 6 Aug 2019 16:22:47 -0700 Subject: Use State::S{0,1} --- passes/fsm/fsm_map.cc | 4 ++-- passes/memory/memory_collect.cc | 10 +++++----- passes/memory/memory_map.cc | 2 +- passes/sat/eval.cc | 4 ++-- passes/sat/miter.cc | 2 +- passes/techmap/simplemap.cc | 2 +- 6 files changed, 12 insertions(+), 12 deletions(-) (limited to 'passes') diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc index 90c958912..80913fda8 100644 --- a/passes/fsm/fsm_map.cc +++ b/passes/fsm/fsm_map.cc @@ -133,7 +133,7 @@ static void implement_pattern_cache(RTLIL::Module *module, std::mapconnect(RTLIL::SigSig(output, cases_vector)); } else { - module->connect(RTLIL::SigSig(output, RTLIL::SigSpec(0, 1))); + module->connect(RTLIL::SigSig(output, State::S0)); } } diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc index 369fcc84e..6acbce62f 100644 --- a/passes/memory/memory_collect.cc +++ b/passes/memory/memory_collect.cc @@ -194,8 +194,8 @@ Cell *handle_memory(Module *module, RTLIL::Memory *memory) log_assert(sig_wr_en.size() == wr_ports * memory->width); mem->parameters["\\WR_PORTS"] = Const(wr_ports); - mem->parameters["\\WR_CLK_ENABLE"] = wr_ports ? sig_wr_clk_enable.as_const() : Const(0, 1); - mem->parameters["\\WR_CLK_POLARITY"] = wr_ports ? sig_wr_clk_polarity.as_const() : Const(0, 1); + mem->parameters["\\WR_CLK_ENABLE"] = wr_ports ? sig_wr_clk_enable.as_const() : State::S0; + mem->parameters["\\WR_CLK_POLARITY"] = wr_ports ? sig_wr_clk_polarity.as_const() : State::S0; mem->setPort("\\WR_CLK", sig_wr_clk); mem->setPort("\\WR_ADDR", sig_wr_addr); @@ -209,9 +209,9 @@ Cell *handle_memory(Module *module, RTLIL::Memory *memory) log_assert(sig_rd_data.size() == rd_ports * memory->width); mem->parameters["\\RD_PORTS"] = Const(rd_ports); - mem->parameters["\\RD_CLK_ENABLE"] = rd_ports ? sig_rd_clk_enable.as_const() : Const(0, 1); - mem->parameters["\\RD_CLK_POLARITY"] = rd_ports ? sig_rd_clk_polarity.as_const() : Const(0, 1); - mem->parameters["\\RD_TRANSPARENT"] = rd_ports ? sig_rd_transparent.as_const() : Const(0, 1); + mem->parameters["\\RD_CLK_ENABLE"] = rd_ports ? sig_rd_clk_enable.as_const() : State::S0; + mem->parameters["\\RD_CLK_POLARITY"] = rd_ports ? sig_rd_clk_polarity.as_const() : State::S0; + mem->parameters["\\RD_TRANSPARENT"] = rd_ports ? sig_rd_transparent.as_const() : State::S0; mem->setPort("\\RD_CLK", sig_rd_clk); mem->setPort("\\RD_ADDR", sig_rd_addr); diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index a0b808e56..65bccb5ef 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -301,7 +301,7 @@ struct MemoryMapWorker RTLIL::Wire *w = w_seladdr; - if (wr_bit != RTLIL::SigSpec(1, 1)) + if (wr_bit != State::S1) { RTLIL::Cell *c = module->addCell(genid(cell->name, "$wren", i, "", j, "", wr_offset), "$and"); c->parameters["\\A_SIGNED"] = RTLIL::Const(0); diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc index 008cd2dfa..e0bb439f4 100644 --- a/passes/sat/eval.cc +++ b/passes/sat/eval.cc @@ -47,8 +47,8 @@ struct BruteForceEquivChecker { if (inputs.size() < mod1_inputs.size()) { RTLIL::SigSpec inputs0 = inputs, inputs1 = inputs; - inputs0.append(RTLIL::Const(0, 1)); - inputs1.append(RTLIL::Const(1, 1)); + inputs0.append(State::S0); + inputs1.append(State::S1); run_checker(inputs0); run_checker(inputs1); return; diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index 1a886af70..e1da1a9e6 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -236,7 +236,7 @@ void create_miter_equiv(struct Pass *that, std::vector args, RTLIL: if (flag_make_assert) { RTLIL::Cell *assert_cell = miter_module->addCell(NEW_ID, "$assert"); assert_cell->setPort("\\A", all_conditions); - assert_cell->setPort("\\EN", RTLIL::SigSpec(1, 1)); + assert_cell->setPort("\\EN", State::S1); } RTLIL::Wire *w_trigger = miter_module->addWire("\\trigger"); diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc index 6c70ffd4f..2eaba1b09 100644 --- a/passes/techmap/simplemap.cc +++ b/passes/techmap/simplemap.cc @@ -185,7 +185,7 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::Cell } if (sig.size() == 0) - sig = RTLIL::SigSpec(0, 1); + sig = State::S0; } void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell) -- cgit v1.2.3 From e38f40af5b7cdd5c8b896ffba17069bd65f01f29 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 6 Aug 2019 16:42:25 -0700 Subject: Use IdString::begins_with() --- passes/hierarchy/hierarchy.cc | 20 +++++++++----------- passes/opt/opt_rmdff.cc | 16 ++++++++-------- 2 files changed, 17 insertions(+), 19 deletions(-) (limited to 'passes') diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 213437c01..19bf531cf 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -48,7 +48,7 @@ void generate(RTLIL::Design *design, const std::vector &celltypes, RTLIL::Cell *cell = i2.second; if (design->has(cell->type)) continue; - if (cell->type.substr(0, 1) == "$" && cell->type.substr(0, 3) != "$__") + if (cell->type.begins_with("$__")) continue; for (auto &pattern : celltypes) if (patmatch(pattern.c_str(), RTLIL::unescape_id(cell->type).c_str())) @@ -143,7 +143,7 @@ void generate(RTLIL::Design *design, const std::vector &celltypes, // Return the "basic" type for an array item. std::string basic_cell_type(const std::string celltype, int pos[3] = nullptr) { std::string basicType = celltype; - if (celltype.substr(0, 7) == "$array:") { + if (celltype.compare(0, strlen("$array:"), "$array:")) { int pos_idx = celltype.find_first_of(':'); int pos_num = celltype.find_first_of(':', pos_idx + 1); int pos_type = celltype.find_first_of(':', pos_num + 1); @@ -194,14 +194,14 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check std::vector connections_to_add_name; std::vector connections_to_add_signal; - if (cell->type.substr(0, 7) == "$array:") { + if (cell->type.begins_with("$array:")) { int pos[3]; basic_cell_type(cell->type.str(), pos); int pos_idx = pos[0]; int pos_num = pos[1]; int pos_type = pos[2]; - int idx = atoi(cell->type.str().substr(pos_idx + 1, pos_num).c_str()); - int num = atoi(cell->type.str().substr(pos_num + 1, pos_type).c_str()); + int idx = std::stoi(cell->type.str().substr(pos_idx + 1, pos_num)); + int num = std::stoi(cell->type.str().substr(pos_num + 1, pos_type)); array_cells[cell] = std::pair(idx, num); cell->type = cell->type.str().substr(pos_type + 1); } @@ -422,8 +422,8 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check for (auto &conn : cell->connections_) { int conn_size = conn.second.size(); RTLIL::IdString portname = conn.first; - if (portname.substr(0, 1) == "$") { - int port_id = atoi(portname.substr(1).c_str()); + if (portname.begins_with("$")) { + int port_id = std::stoi(portname.substr(1)); for (auto &wire_it : mod->wires_) if (wire_it.second->port_id == port_id) { portname = wire_it.first; @@ -457,9 +457,8 @@ void hierarchy_worker(RTLIL::Design *design, std::setcells()) { std::string celltype = cell->type.str(); - if (celltype.substr(0, 7) == "$array:") { + if (celltype.compare(0, strlen("$array:"), "$array:")) celltype = basic_cell_type(celltype); - } if (design->module(celltype)) hierarchy_worker(design, used, design->module(celltype), indent+4); } @@ -521,9 +520,8 @@ int find_top_mod_score(Design *design, Module *module, dict &db) for (auto cell : module->cells()) { std::string celltype = cell->type.str(); // Is this an array instance - if (celltype.substr(0, 7) == "$array:") { + if (celltype.compare(0, strlen("$array:"), "$array:")) celltype = basic_cell_type(celltype); - } // Is this cell a module instance? auto instModule = design->module(celltype); // If there is no instance for this, issue a warning. diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc index d712736c1..450626f4a 100644 --- a/passes/opt/opt_rmdff.cc +++ b/passes/opt/opt_rmdff.cc @@ -63,11 +63,11 @@ bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell) log_assert(GetSize(sig_set) == GetSize(sig_clr)); - if (cell->type.substr(0,8) == "$_DFFSR_") { + if (cell->type.begins_with("$_DFFSR_")) { pol_set = cell->type[9] == 'P' ? State::S1 : State::S0; pol_clr = cell->type[10] == 'P' ? State::S1 : State::S0; } else - if (cell->type.substr(0,11) == "$_DLATCHSR_") { + if (cell->type.begins_with("$_DLATCHSR_")) { pol_set = cell->type[12] == 'P' ? State::S1 : State::S0; pol_clr = cell->type[13] == 'P' ? State::S1 : State::S0; } else @@ -198,9 +198,9 @@ bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell) { IdString new_type; - if (cell->type.substr(0,8) == "$_DFFSR_") + if (cell->type.begins_with("$_DFFSR_")) new_type = stringf("$_DFF_%c_", cell->type[8]); - else if (cell->type.substr(0,11) == "$_DLATCHSR_") + else if (cell->type.begins_with("$_DLATCHSR_")) new_type = stringf("$_DLATCH_%c_", cell->type[11]); else log_abort(); @@ -278,7 +278,7 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) sig_c = dff->getPort("\\C"); val_cp = RTLIL::Const(dff->type == "$_DFF_P_", 1); } - else if (dff->type.substr(0,6) == "$_DFF_" && dff->type.substr(9) == "_" && + else if (dff->type.begins_with("$_DFF_") && dff->type.substr(9) == "_" && (dff->type[6] == 'N' || dff->type[6] == 'P') && (dff->type[7] == 'N' || dff->type[7] == 'P') && (dff->type[8] == '0' || dff->type[8] == '1')) { @@ -290,7 +290,7 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) val_rp = RTLIL::Const(dff->type[7] == 'P', 1); val_rv = RTLIL::Const(dff->type[8] == '1', 1); } - else if (dff->type.substr(0,7) == "$_DFFE_" && dff->type.substr(9) == "_" && + else if (dff->type.begins_with("$_DFFE_") && dff->type.substr(9) == "_" && (dff->type[7] == 'N' || dff->type[7] == 'P') && (dff->type[8] == 'N' || dff->type[8] == 'P')) { sig_d = dff->getPort("\\D"); @@ -428,7 +428,7 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) return true; } - log_assert(dff->type.substr(0,6) == "$_DFF_"); + log_assert(dff->type.begins_with("$_DFF_")); dff->type = stringf("$_DFF_%c_", + dff->type[6]); dff->unsetPort("\\R"); } @@ -452,7 +452,7 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) return true; } - log_assert(dff->type.substr(0,7) == "$_DFFE_"); + log_assert(dff->type.begins_with("$_DFFE_")); dff->type = stringf("$_DFF_%c_", + dff->type[7]); dff->unsetPort("\\E"); } -- cgit v1.2.3 From c11ad24fd7d961432cfdbca7497ba229d3b4f38d Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 6 Aug 2019 16:45:48 -0700 Subject: Use std::stoi instead of atoi(.c_str()) --- passes/cmds/add.cc | 2 +- passes/cmds/chformal.cc | 4 ++-- passes/cmds/qwp.cc | 2 +- passes/cmds/scc.cc | 4 ++-- passes/cmds/select.cc | 16 ++++++++-------- passes/cmds/setundef.cc | 2 +- passes/cmds/show.cc | 2 +- passes/cmds/tee.cc | 2 +- passes/equiv/equiv_induct.cc | 2 +- passes/equiv/equiv_simple.cc | 2 +- passes/equiv/equiv_struct.cc | 2 +- passes/memory/memory_bram.cc | 8 ++++---- passes/opt/opt_lut.cc | 4 ++-- passes/opt/pmux2shiftx.cc | 4 ++-- passes/opt/share.cc | 2 +- passes/sat/freduce.cc | 2 +- passes/sat/mutate.cc | 34 +++++++++++++++++----------------- passes/sat/sat.cc | 26 +++++++++++++------------- passes/sat/sim.cc | 4 ++-- passes/techmap/abc.cc | 12 ++++++------ passes/techmap/abc9.cc | 12 ++++++------ passes/techmap/extract.cc | 10 +++++----- passes/techmap/extract_counter.cc | 2 +- passes/techmap/extract_fa.cc | 4 ++-- passes/techmap/flowmap.cc | 12 ++++++------ passes/techmap/nlutmap.cc | 2 +- passes/techmap/shregmap.cc | 8 ++++---- passes/techmap/techmap.cc | 2 +- passes/tests/test_abcloop.cc | 4 ++-- passes/tests/test_autotb.cc | 4 ++-- passes/tests/test_cell.cc | 4 ++-- 31 files changed, 100 insertions(+), 100 deletions(-) (limited to 'passes') diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc index af6f7043d..971de1d00 100644 --- a/passes/cmds/add.cc +++ b/passes/cmds/add.cc @@ -130,7 +130,7 @@ struct AddPass : public Pass { if (arg == "-global_input") arg_flag_global = true; arg_name = args[++argidx]; - arg_width = atoi(args[++argidx].c_str()); + arg_width = std::stoi(args[++argidx]); continue; } break; diff --git a/passes/cmds/chformal.cc b/passes/cmds/chformal.cc index 7e32da65f..c97b204af 100644 --- a/passes/cmds/chformal.cc +++ b/passes/cmds/chformal.cc @@ -106,12 +106,12 @@ struct ChformalPass : public Pass { } if (mode == 0 && args[argidx] == "-delay" && argidx+1 < args.size()) { mode = 'd'; - mode_arg = atoi(args[++argidx].c_str()); + mode_arg = std::stoi(args[++argidx]); continue; } if (mode == 0 && args[argidx] == "-skip" && argidx+1 < args.size()) { mode = 's'; - mode_arg = atoi(args[++argidx].c_str()); + mode_arg = std::stoi(args[++argidx]); continue; } if ((mode == 0 || mode == 'c') && args[argidx] == "-assert2assume") { diff --git a/passes/cmds/qwp.cc b/passes/cmds/qwp.cc index adbe89e31..4d53b3995 100644 --- a/passes/cmds/qwp.cc +++ b/passes/cmds/qwp.cc @@ -830,7 +830,7 @@ struct QwpPass : public Pass { continue; } if (args[argidx] == "-grid" && argidx+1 < args.size()) { - config.grid = 1.0 / atoi(args[++argidx].c_str()); + config.grid = 1.0 / std::stoi(args[++argidx]); continue; } if (args[argidx] == "-dump" && argidx+1 < args.size()) { diff --git a/passes/cmds/scc.cc b/passes/cmds/scc.cc index 99f4fbae8..ad924e1bf 100644 --- a/passes/cmds/scc.cc +++ b/passes/cmds/scc.cc @@ -269,11 +269,11 @@ struct SccPass : public Pass { size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { if (args[argidx] == "-max_depth" && argidx+1 < args.size()) { - maxDepth = atoi(args[++argidx].c_str()); + maxDepth = std::stoi(args[++argidx]); continue; } if (args[argidx] == "-expect" && argidx+1 < args.size()) { - expect = atoi(args[++argidx].c_str()); + expect = std::stoi(args[++argidx]); continue; } if (args[argidx] == "-nofeedback") { diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index b5e8ef1af..e857e655f 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -517,7 +517,7 @@ static void select_op_expand(RTLIL::Design *design, std::string arg, char mode, size_t endpos = arg.find_first_not_of("0123456789", pos); if (endpos == std::string::npos) endpos = arg.size(); - levels = atoi(arg.substr(pos, endpos-pos).c_str()); + levels = std::stoi(arg.substr(pos, endpos-pos)); pos = endpos; } @@ -526,7 +526,7 @@ static void select_op_expand(RTLIL::Design *design, std::string arg, char mode, if (endpos == std::string::npos) endpos = arg.size(); if (int(endpos) > pos) - rem_objects = atoi(arg.substr(pos, endpos-pos).c_str()); + rem_objects = std::stoi(arg.substr(pos, endpos-pos)); pos = endpos; } @@ -823,15 +823,15 @@ static void select_stmt(RTLIL::Design *design, std::string arg) if (arg_memb.substr(0, 2) == "s:") { size_t delim = arg_memb.substr(2).find(':'); if (delim == std::string::npos) { - int width = atoi(arg_memb.substr(2).c_str()); + int width = std::stoi(arg_memb.substr(2)); for (auto &it : mod->wires_) if (it.second->width == width) sel.selected_members[mod->name].insert(it.first); } else { std::string min_str = arg_memb.substr(2, delim); std::string max_str = arg_memb.substr(2+delim+1); - int min_width = min_str.empty() ? 0 : atoi(min_str.c_str()); - int max_width = max_str.empty() ? -1 : atoi(max_str.c_str()); + int min_width = min_str.empty() ? 0 : std::stoi(min_str); + int max_width = max_str.empty() ? -1 : std::stoi(max_str); for (auto &it : mod->wires_) if (min_width <= it.second->width && (it.second->width <= max_width || max_width == -1)) sel.selected_members[mod->name].insert(it.first); @@ -1230,15 +1230,15 @@ struct SelectPass : public Pass { continue; } if (arg == "-assert-count" && argidx+1 < args.size()) { - assert_count = atoi(args[++argidx].c_str()); + assert_count = std::stoi(args[++argidx]); continue; } if (arg == "-assert-max" && argidx+1 < args.size()) { - assert_max = atoi(args[++argidx].c_str()); + assert_max = std::stoi(args[++argidx]); continue; } if (arg == "-assert-min" && argidx+1 < args.size()) { - assert_min = atoi(args[++argidx].c_str()); + assert_min = std::stoi(args[++argidx]); continue; } if (arg == "-clear") { diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index 3eedc86b8..0e3c0c853 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -210,7 +210,7 @@ struct SetundefPass : public Pass { if (args[argidx] == "-random" && !got_value && argidx+1 < args.size()) { got_value = true; worker.next_bit_mode = MODE_RANDOM; - worker.next_bit_state = atoi(args[++argidx].c_str()) + 1; + worker.next_bit_state = std::stoi(args[++argidx]) + 1; for (int i = 0; i < 10; i++) worker.next_bit(); continue; diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index cf729215f..3af477bd9 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -740,7 +740,7 @@ struct ShowPass : public Pass { continue; } if (arg == "-colors" && argidx+1 < args.size()) { - colorSeed = atoi(args[++argidx].c_str()); + colorSeed = std::stoi(args[++argidx]); for (int i = 0; i < 100; i++) colorSeed = ShowWorker::xorshift32(colorSeed); continue; diff --git a/passes/cmds/tee.cc b/passes/cmds/tee.cc index 1a44bdaec..e0a74099a 100644 --- a/passes/cmds/tee.cc +++ b/passes/cmds/tee.cc @@ -79,7 +79,7 @@ struct TeePass : public Pass { continue; } if (GetSize(args[argidx]) >= 2 && (args[argidx][0] == '-' || args[argidx][0] == '+') && args[argidx][1] >= '0' && args[argidx][1] <= '9') { - log_verbose_level += atoi(args[argidx].c_str()); + log_verbose_level += std::stoi(args[argidx]); continue; } break; diff --git a/passes/equiv/equiv_induct.cc b/passes/equiv/equiv_induct.cc index bcc68d6d2..e3af16e2d 100644 --- a/passes/equiv/equiv_induct.cc +++ b/passes/equiv/equiv_induct.cc @@ -207,7 +207,7 @@ struct EquivInductPass : public Pass { continue; } if (args[argidx] == "-seq" && argidx+1 < args.size()) { - max_seq = atoi(args[++argidx].c_str()); + max_seq = std::stoi(args[++argidx]); continue; } break; diff --git a/passes/equiv/equiv_simple.cc b/passes/equiv/equiv_simple.cc index c2fab26f2..1f80e117d 100644 --- a/passes/equiv/equiv_simple.cc +++ b/passes/equiv/equiv_simple.cc @@ -325,7 +325,7 @@ struct EquivSimplePass : public Pass { continue; } if (args[argidx] == "-seq" && argidx+1 < args.size()) { - max_seq = atoi(args[++argidx].c_str()); + max_seq = std::stoi(args[++argidx]); continue; } break; diff --git a/passes/equiv/equiv_struct.cc b/passes/equiv/equiv_struct.cc index a7973fd04..0bae55802 100644 --- a/passes/equiv/equiv_struct.cc +++ b/passes/equiv/equiv_struct.cc @@ -338,7 +338,7 @@ struct EquivStructPass : public Pass { continue; } if (args[argidx] == "-maxiter" && argidx+1 < args.size()) { - max_iter = atoi(args[++argidx].c_str()); + max_iter = std::stoi(args[++argidx]); continue; } break; diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc index aa8f94149..2913400c5 100644 --- a/passes/memory/memory_bram.cc +++ b/passes/memory/memory_bram.cc @@ -176,7 +176,7 @@ struct rules_t bool parse_single_int(const char *stmt, int &value) { if (GetSize(tokens) == 2 && tokens[0] == stmt) { - value = atoi(tokens[1].c_str()); + value = std::stoi(tokens[1]); return true; } return false; @@ -187,7 +187,7 @@ struct rules_t if (GetSize(tokens) >= 2 && tokens[0] == stmt) { value.resize(GetSize(tokens)-1); for (int i = 1; i < GetSize(tokens); i++) - value[i-1] = atoi(tokens[i].c_str()); + value[i-1] = std::stoi(tokens[i]); return true; } return false; @@ -297,12 +297,12 @@ struct rules_t } if (GetSize(tokens) == 3 && tokens[0] == "min") { - data.min_limits[tokens[1]] = atoi(tokens[2].c_str()); + data.min_limits[tokens[1]] = std::stoi(tokens[2]); continue; } if (GetSize(tokens) == 3 && tokens[0] == "max") { - data.max_limits[tokens[1]] = atoi(tokens[2].c_str()); + data.max_limits[tokens[1]] = std::stoi(tokens[2]); continue; } diff --git a/passes/opt/opt_lut.cc b/passes/opt/opt_lut.cc index 587ef878a..6d97c0bb4 100644 --- a/passes/opt/opt_lut.cc +++ b/passes/opt/opt_lut.cc @@ -555,14 +555,14 @@ struct OptLutPass : public Pass { if (conn_tokens.size() != 2) log_cmd_error("Invalid format of -dlogic signal mapping.\n"); IdString logic_port = "\\" + conn_tokens[0]; - int lut_input = atoi(conn_tokens[1].c_str()); + int lut_input = std::stoi(conn_tokens[1]); dlogic[type][lut_input] = logic_port; } continue; } if (args[argidx] == "-limit" && argidx + 1 < args.size()) { - limit = atoi(args[++argidx].c_str()); + limit = std::stoi(args[++argidx]); continue; } break; diff --git a/passes/opt/pmux2shiftx.cc b/passes/opt/pmux2shiftx.cc index 65d8b8f32..e571ed3c6 100644 --- a/passes/opt/pmux2shiftx.cc +++ b/passes/opt/pmux2shiftx.cc @@ -240,11 +240,11 @@ struct Pmux2ShiftxPass : public Pass { size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { if (args[argidx] == "-min_density" && argidx+1 < args.size()) { - min_density = atoi(args[++argidx].c_str()); + min_density = std::stoi(args[++argidx]); continue; } if (args[argidx] == "-min_choices" && argidx+1 < args.size()) { - min_choices = atoi(args[++argidx].c_str()); + min_choices = std::stoi(args[++argidx]); continue; } if (args[argidx] == "-onehot" && argidx+1 < args.size() && args[argidx+1] == "ignore") { diff --git a/passes/opt/share.cc b/passes/opt/share.cc index 7f66f749f..ea5bf8d33 100644 --- a/passes/opt/share.cc +++ b/passes/opt/share.cc @@ -1521,7 +1521,7 @@ struct SharePass : public Pass { continue; } if (args[argidx] == "-limit" && argidx+1 < args.size()) { - config.limit = atoi(args[++argidx].c_str()); + config.limit = std::stoi(args[++argidx]); continue; } break; diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index f29631639..781b5e3cc 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -816,7 +816,7 @@ struct FreducePass : public Pass { continue; } if (args[argidx] == "-stop" && argidx+1 < args.size()) { - reduce_stop_at = atoi(args[++argidx].c_str()); + reduce_stop_at = std::stoi(args[++argidx]); continue; } if (args[argidx] == "-dump" && argidx+1 < args.size()) { diff --git a/passes/sat/mutate.cc b/passes/sat/mutate.cc index b53bbfeb2..a4b2f5eb5 100644 --- a/passes/sat/mutate.cc +++ b/passes/sat/mutate.cc @@ -803,7 +803,7 @@ struct MutatePass : public Pass { for (argidx = 1; argidx < args.size(); argidx++) { if (args[argidx] == "-list" && argidx+1 < args.size()) { - N = atoi(args[++argidx].c_str()); + N = std::stoi(args[++argidx]); continue; } if (args[argidx] == "-o" && argidx+1 < args.size()) { @@ -815,7 +815,7 @@ struct MutatePass : public Pass { continue; } if (args[argidx] == "-seed" && argidx+1 < args.size()) { - opts.seed = atoi(args[++argidx].c_str()); + opts.seed = std::stoi(args[++argidx]); continue; } if (args[argidx] == "-none") { @@ -828,8 +828,8 @@ struct MutatePass : public Pass { } if (args[argidx] == "-ctrl" && argidx+3 < args.size()) { opts.ctrl_name = RTLIL::escape_id(args[++argidx]); - opts.ctrl_width = atoi(args[++argidx].c_str()); - opts.ctrl_value = atoi(args[++argidx].c_str()); + opts.ctrl_width = std::stoi(args[++argidx]); + opts.ctrl_value = std::stoi(args[++argidx]); continue; } if (args[argidx] == "-module" && argidx+1 < args.size()) { @@ -845,11 +845,11 @@ struct MutatePass : public Pass { continue; } if (args[argidx] == "-portbit" && argidx+1 < args.size()) { - opts.portbit = atoi(args[++argidx].c_str()); + opts.portbit = std::stoi(args[++argidx]); continue; } if (args[argidx] == "-ctrlbit" && argidx+1 < args.size()) { - opts.ctrlbit = atoi(args[++argidx].c_str()); + opts.ctrlbit = std::stoi(args[++argidx]); continue; } if (args[argidx] == "-wire" && argidx+1 < args.size()) { @@ -857,7 +857,7 @@ struct MutatePass : public Pass { continue; } if (args[argidx] == "-wirebit" && argidx+1 < args.size()) { - opts.wirebit = atoi(args[++argidx].c_str()); + opts.wirebit = std::stoi(args[++argidx]); continue; } if (args[argidx] == "-src" && argidx+1 < args.size()) { @@ -866,52 +866,52 @@ struct MutatePass : public Pass { } if (args[argidx] == "-cfg" && argidx+2 < args.size()) { if (args[argidx+1] == "pick_cover_prcnt") { - opts.pick_cover_prcnt = atoi(args[argidx+2].c_str()); + opts.pick_cover_prcnt = std::stoi(args[argidx+2]); argidx += 2; continue; } if (args[argidx+1] == "weight_cover") { - opts.weight_cover = atoi(args[argidx+2].c_str()); + opts.weight_cover = std::stoi(args[argidx+2]); argidx += 2; continue; } if (args[argidx+1] == "weight_pq_w") { - opts.weight_pq_w = atoi(args[argidx+2].c_str()); + opts.weight_pq_w = std::stoi(args[argidx+2]); argidx += 2; continue; } if (args[argidx+1] == "weight_pq_b") { - opts.weight_pq_b = atoi(args[argidx+2].c_str()); + opts.weight_pq_b = std::stoi(args[argidx+2]); argidx += 2; continue; } if (args[argidx+1] == "weight_pq_c") { - opts.weight_pq_c = atoi(args[argidx+2].c_str()); + opts.weight_pq_c = std::stoi(args[argidx+2]); argidx += 2; continue; } if (args[argidx+1] == "weight_pq_s") { - opts.weight_pq_s = atoi(args[argidx+2].c_str()); + opts.weight_pq_s = std::stoi(args[argidx+2]); argidx += 2; continue; } if (args[argidx+1] == "weight_pq_mw") { - opts.weight_pq_mw = atoi(args[argidx+2].c_str()); + opts.weight_pq_mw = std::stoi(args[argidx+2]); argidx += 2; continue; } if (args[argidx+1] == "weight_pq_mb") { - opts.weight_pq_mb = atoi(args[argidx+2].c_str()); + opts.weight_pq_mb = std::stoi(args[argidx+2]); argidx += 2; continue; } if (args[argidx+1] == "weight_pq_mc") { - opts.weight_pq_mc = atoi(args[argidx+2].c_str()); + opts.weight_pq_mc = std::stoi(args[argidx+2]); argidx += 2; continue; } if (args[argidx+1] == "weight_pq_ms") { - opts.weight_pq_ms = atoi(args[argidx+2].c_str()); + opts.weight_pq_ms = std::stoi(args[argidx+2]); argidx += 2; continue; } diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index e4654d835..847ca0e1d 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -1102,23 +1102,23 @@ struct SatPass : public Pass { continue; } if (args[argidx] == "-timeout" && argidx+1 < args.size()) { - timeout = atoi(args[++argidx].c_str()); + timeout = std::stoi(args[++argidx]); continue; } if (args[argidx] == "-max" && argidx+1 < args.size()) { - loopcount = atoi(args[++argidx].c_str()); + loopcount = std::stoi(args[++argidx]); continue; } if (args[argidx] == "-maxsteps" && argidx+1 < args.size()) { - maxsteps = atoi(args[++argidx].c_str()); + maxsteps = std::stoi(args[++argidx]); continue; } if (args[argidx] == "-initsteps" && argidx+1 < args.size()) { - initsteps = atoi(args[++argidx].c_str()); + initsteps = std::stoi(args[++argidx]); continue; } if (args[argidx] == "-stepsize" && argidx+1 < args.size()) { - stepsize = max(1, atoi(args[++argidx].c_str())); + stepsize = max(1, std::stoi(args[++argidx])); continue; } if (args[argidx] == "-ignore_div_by_zero") { @@ -1185,7 +1185,7 @@ struct SatPass : public Pass { continue; } if (args[argidx] == "-tempinduct-skip" && argidx+1 < args.size()) { - tempinduct_skip = atoi(args[++argidx].c_str()); + tempinduct_skip = std::stoi(args[++argidx]); continue; } if (args[argidx] == "-prove" && argidx+2 < args.size()) { @@ -1206,39 +1206,39 @@ struct SatPass : public Pass { continue; } if (args[argidx] == "-prove-skip" && argidx+1 < args.size()) { - prove_skip = atoi(args[++argidx].c_str()); + prove_skip = std::stoi(args[++argidx]); continue; } if (args[argidx] == "-seq" && argidx+1 < args.size()) { - seq_len = atoi(args[++argidx].c_str()); + seq_len = std::stoi(args[++argidx]); continue; } if (args[argidx] == "-set-at" && argidx+3 < args.size()) { - int timestep = atoi(args[++argidx].c_str()); + int timestep = std::stoi(args[++argidx]); std::string lhs = args[++argidx]; std::string rhs = args[++argidx]; sets_at[timestep].push_back(std::pair(lhs, rhs)); continue; } if (args[argidx] == "-unset-at" && argidx+2 < args.size()) { - int timestep = atoi(args[++argidx].c_str()); + int timestep = std::stoi(args[++argidx]); unsets_at[timestep].push_back(args[++argidx]); continue; } if (args[argidx] == "-set-def-at" && argidx+2 < args.size()) { - int timestep = atoi(args[++argidx].c_str()); + int timestep = std::stoi(args[++argidx]); sets_def_at[timestep].push_back(args[++argidx]); enable_undef = true; continue; } if (args[argidx] == "-set-any-undef-at" && argidx+2 < args.size()) { - int timestep = atoi(args[++argidx].c_str()); + int timestep = std::stoi(args[++argidx]); sets_any_undef_at[timestep].push_back(args[++argidx]); enable_undef = true; continue; } if (args[argidx] == "-set-all-undef-at" && argidx+2 < args.size()) { - int timestep = atoi(args[++argidx].c_str()); + int timestep = std::stoi(args[++argidx]); sets_all_undef_at[timestep].push_back(args[++argidx]); enable_undef = true; continue; diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index 4c3022c70..cb102e8bf 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -803,11 +803,11 @@ struct SimPass : public Pass { continue; } if (args[argidx] == "-n" && argidx+1 < args.size()) { - numcycles = atoi(args[++argidx].c_str()); + numcycles = std::stoi(args[++argidx]); continue; } if (args[argidx] == "-rstlen" && argidx+1 < args.size()) { - worker.rstlen = atoi(args[++argidx].c_str()); + worker.rstlen = std::stoi(args[++argidx]); continue; } if (args[argidx] == "-clock" && argidx+1 < args.size()) { diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index 73f63a4e1..5509c8c12 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -1564,10 +1564,10 @@ struct AbcPass : public Pass { size_t pos = arg.find_first_of(':'); int lut_mode = 0, lut_mode2 = 0; if (pos != string::npos) { - lut_mode = atoi(arg.substr(0, pos).c_str()); - lut_mode2 = atoi(arg.substr(pos+1).c_str()); + lut_mode = std::stoi(arg.substr(0, pos)); + lut_mode2 = std::stoi(arg.substr(pos+1)); } else { - lut_mode = atoi(arg.c_str()); + lut_mode = std::stoi(arg); lut_mode2 = lut_mode; } lut_costs.clear(); @@ -1584,10 +1584,10 @@ struct AbcPass : public Pass { if (GetSize(parts) == 0 && !lut_costs.empty()) lut_costs.push_back(lut_costs.back()); else if (GetSize(parts) == 1) - lut_costs.push_back(atoi(parts.at(0).c_str())); + lut_costs.push_back(std::stoi(parts.at(0))); else if (GetSize(parts) == 2) - while (GetSize(lut_costs) < atoi(parts.at(0).c_str())) - lut_costs.push_back(atoi(parts.at(1).c_str())); + while (GetSize(lut_costs) < std::stoi(parts.at(0))) + lut_costs.push_back(std::stoi(parts.at(1))); else log_cmd_error("Invalid -luts syntax.\n"); } diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 34919cf07..36e3b4e65 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -999,8 +999,8 @@ struct Abc9Pass : public Pass { size_t pos = arg.find_first_of(':'); int lut_mode = 0, lut_mode2 = 0; if (pos != string::npos) { - lut_mode = atoi(arg.substr(0, pos).c_str()); - lut_mode2 = atoi(arg.substr(pos+1).c_str()); + lut_mode = std::stoi(arg.substr(0, pos)); + lut_mode2 = std::stoi(arg.substr(pos+1)); } else { pos = arg.find_first_of('.'); if (pos != string::npos) { @@ -1010,7 +1010,7 @@ struct Abc9Pass : public Pass { lut_file = std::string(pwd) + "/" + lut_file; } else { - lut_mode = atoi(arg.c_str()); + lut_mode = std::stoi(arg); lut_mode2 = lut_mode; } } @@ -1028,10 +1028,10 @@ struct Abc9Pass : public Pass { if (GetSize(parts) == 0 && !lut_costs.empty()) lut_costs.push_back(lut_costs.back()); else if (GetSize(parts) == 1) - lut_costs.push_back(atoi(parts.at(0).c_str())); + lut_costs.push_back(std::stoi(parts.at(0))); else if (GetSize(parts) == 2) - while (GetSize(lut_costs) < atoi(parts.at(0).c_str())) - lut_costs.push_back(atoi(parts.at(1).c_str())); + while (GetSize(lut_costs) < std::stoi(parts.at(0))) + lut_costs.push_back(std::stoi(parts.at(1))); else log_cmd_error("Invalid -luts syntax.\n"); } diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index fff90f13c..cf9743806 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -476,16 +476,16 @@ struct ExtractPass : public Pass { continue; } if (args[argidx] == "-mine_cells_span" && argidx+2 < args.size()) { - mine_cells_min = atoi(args[++argidx].c_str()); - mine_cells_max = atoi(args[++argidx].c_str()); + mine_cells_min = std::stoi(args[++argidx]); + mine_cells_max = std::stoi(args[++argidx]); continue; } if (args[argidx] == "-mine_min_freq" && argidx+1 < args.size()) { - mine_min_freq = atoi(args[++argidx].c_str()); + mine_min_freq = std::stoi(args[++argidx]); continue; } if (args[argidx] == "-mine_limit_matches_per_module" && argidx+1 < args.size()) { - mine_limit_mod = atoi(args[++argidx].c_str()); + mine_limit_mod = std::stoi(args[++argidx]); continue; } if (args[argidx] == "-mine_split" && argidx+2 < args.size()) { @@ -494,7 +494,7 @@ struct ExtractPass : public Pass { continue; } if (args[argidx] == "-mine_max_fanout" && argidx+1 < args.size()) { - mine_max_fanout = atoi(args[++argidx].c_str()); + mine_max_fanout = std::stoi(args[++argidx]); continue; } if (args[argidx] == "-verbose") { diff --git a/passes/techmap/extract_counter.cc b/passes/techmap/extract_counter.cc index a8d0bc834..da56e087b 100644 --- a/passes/techmap/extract_counter.cc +++ b/passes/techmap/extract_counter.cc @@ -613,7 +613,7 @@ struct ExtractCounterPass : public Pass { if (args[argidx] == "-maxwidth" && argidx+1 < args.size()) { - maxwidth = atoi(args[++argidx].c_str()); + maxwidth = std::stoi(args[++argidx]); continue; } } diff --git a/passes/techmap/extract_fa.cc b/passes/techmap/extract_fa.cc index b541ceb6b..0b5b6a111 100644 --- a/passes/techmap/extract_fa.cc +++ b/passes/techmap/extract_fa.cc @@ -580,11 +580,11 @@ struct ExtractFaPass : public Pass { continue; } if (args[argidx] == "-d" && argidx+2 < args.size()) { - config.maxdepth = atoi(args[++argidx].c_str()); + config.maxdepth = std::stoi(args[++argidx]); continue; } if (args[argidx] == "-b" && argidx+2 < args.size()) { - config.maxbreadth = atoi(args[++argidx].c_str()); + config.maxbreadth = std::stoi(args[++argidx]); continue; } break; diff --git a/passes/techmap/flowmap.cc b/passes/techmap/flowmap.cc index 96d0df5f8..3e66fcacc 100644 --- a/passes/techmap/flowmap.cc +++ b/passes/techmap/flowmap.cc @@ -1525,12 +1525,12 @@ struct FlowmapPass : public Pass { { if (args[argidx] == "-maxlut" && argidx + 1 < args.size()) { - order = atoi(args[++argidx].c_str()); + order = std::stoi(args[++argidx]); continue; } if (args[argidx] == "-minlut" && argidx + 1 < args.size()) { - minlut = atoi(args[++argidx].c_str()); + minlut = std::stoi(args[++argidx]); continue; } if (args[argidx] == "-cells" && argidx + 1 < args.size()) @@ -1545,23 +1545,23 @@ struct FlowmapPass : public Pass { } if (args[argidx] == "-r-alpha" && argidx + 1 < args.size()) { - r_alpha = atoi(args[++argidx].c_str()); + r_alpha = std::stoi(args[++argidx]); continue; } if (args[argidx] == "-r-beta" && argidx + 1 < args.size()) { - r_beta = atoi(args[++argidx].c_str()); + r_beta = std::stoi(args[++argidx]); continue; } if (args[argidx] == "-r-gamma" && argidx + 1 < args.size()) { - r_gamma = atoi(args[++argidx].c_str()); + r_gamma = std::stoi(args[++argidx]); continue; } if (args[argidx] == "-optarea" && argidx + 1 < args.size()) { relax = true; - optarea = atoi(args[++argidx].c_str()); + optarea = std::stoi(args[++argidx]); continue; } if (args[argidx] == "-debug") diff --git a/passes/techmap/nlutmap.cc b/passes/techmap/nlutmap.cc index cc765d89c..9ac39ed05 100644 --- a/passes/techmap/nlutmap.cc +++ b/passes/techmap/nlutmap.cc @@ -163,7 +163,7 @@ struct NlutmapPass : public Pass { vector tokens = split_tokens(args[++argidx], ","); config.luts.clear(); for (auto &token : tokens) - config.luts.push_back(atoi(token.c_str())); + config.luts.push_back(std::stoi(token)); continue; } if (args[argidx] == "-assert") { diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index 004ab1eb9..06eb7b793 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -655,19 +655,19 @@ struct ShregmapPass : public Pass { continue; } if (args[argidx] == "-minlen" && argidx+1 < args.size()) { - opts.minlen = atoi(args[++argidx].c_str()); + opts.minlen = std::stoi(args[++argidx]); continue; } if (args[argidx] == "-maxlen" && argidx+1 < args.size()) { - opts.maxlen = atoi(args[++argidx].c_str()); + opts.maxlen = std::stoi(args[++argidx]); continue; } if (args[argidx] == "-keep_before" && argidx+1 < args.size()) { - opts.keep_before = atoi(args[++argidx].c_str()); + opts.keep_before = std::stoi(args[++argidx]); continue; } if (args[argidx] == "-keep_after" && argidx+1 < args.size()) { - opts.keep_after = atoi(args[++argidx].c_str()); + opts.keep_after = std::stoi(args[++argidx]); continue; } if (args[argidx] == "-tech" && argidx+1 < args.size() && opts.tech == nullptr) { diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index ceb053825..d10420ae8 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -1072,7 +1072,7 @@ struct TechmapPass : public Pass { continue; } if (args[argidx] == "-max_iter" && argidx+1 < args.size()) { - max_iter = atoi(args[++argidx].c_str()); + max_iter = std::stoi(args[++argidx]); continue; } if (args[argidx] == "-D" && argidx+1 < args.size()) { diff --git a/passes/tests/test_abcloop.cc b/passes/tests/test_abcloop.cc index 5d5466afe..d5a167db1 100644 --- a/passes/tests/test_abcloop.cc +++ b/passes/tests/test_abcloop.cc @@ -268,11 +268,11 @@ struct TestAbcloopPass : public Pass { for (argidx = 1; argidx < GetSize(args); argidx++) { if (args[argidx] == "-n" && argidx+1 < GetSize(args)) { - num_iter = atoi(args[++argidx].c_str()); + num_iter = std::stoi(args[++argidx]); continue; } if (args[argidx] == "-s" && argidx+1 < GetSize(args)) { - xorshift32_state = atoi(args[++argidx].c_str()); + xorshift32_state = std::stoi(args[++argidx]); continue; } break; diff --git a/passes/tests/test_autotb.cc b/passes/tests/test_autotb.cc index bfb1d6642..198007b87 100644 --- a/passes/tests/test_autotb.cc +++ b/passes/tests/test_autotb.cc @@ -360,11 +360,11 @@ struct TestAutotbBackend : public Backend { for (argidx = 1; argidx < GetSize(args); argidx++) { if (args[argidx] == "-n" && argidx+1 < GetSize(args)) { - num_iter = atoi(args[++argidx].c_str()); + num_iter = std::stoi(args[++argidx]); continue; } if (args[argidx] == "-seed" && argidx+1 < GetSize(args)) { - seed = atoi(args[++argidx].c_str()); + seed = std::stoi(args[++argidx]); continue; } break; diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index e360b5edb..7c58ec158 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -730,11 +730,11 @@ struct TestCellPass : public Pass { for (argidx = 1; argidx < GetSize(args); argidx++) { if (args[argidx] == "-n" && argidx+1 < GetSize(args)) { - num_iter = atoi(args[++argidx].c_str()); + num_iter = std::stoi(args[++argidx]); continue; } if (args[argidx] == "-s" && argidx+1 < GetSize(args)) { - xorshift32_state = atoi(args[++argidx].c_str()); + xorshift32_state = std::stoi(args[++argidx]); continue; } if (args[argidx] == "-map" && argidx+1 < GetSize(args)) { -- cgit v1.2.3 From 234fcf1724941b5c4fa77cc0359d339ddd36aeb3 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 6 Aug 2019 19:07:45 -0700 Subject: Fix typos --- passes/hierarchy/hierarchy.cc | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'passes') diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 19bf531cf..ff5c3b6a1 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -143,7 +143,7 @@ void generate(RTLIL::Design *design, const std::vector &celltypes, // Return the "basic" type for an array item. std::string basic_cell_type(const std::string celltype, int pos[3] = nullptr) { std::string basicType = celltype; - if (celltype.compare(0, strlen("$array:"), "$array:")) { + if (celltype.compare(0, strlen("$array:"), "$array:") == 0) { int pos_idx = celltype.find_first_of(':'); int pos_num = celltype.find_first_of(':', pos_idx + 1); int pos_type = celltype.find_first_of(':', pos_num + 1); @@ -200,8 +200,8 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check int pos_idx = pos[0]; int pos_num = pos[1]; int pos_type = pos[2]; - int idx = std::stoi(cell->type.str().substr(pos_idx + 1, pos_num)); - int num = std::stoi(cell->type.str().substr(pos_num + 1, pos_type)); + int idx = std::stoi(cell->type.substr(pos_idx + 1, pos_num)); + int num = std::stoi(cell->type.substr(pos_num + 1, pos_type)); array_cells[cell] = std::pair(idx, num); cell->type = cell->type.str().substr(pos_type + 1); } @@ -457,7 +457,7 @@ void hierarchy_worker(RTLIL::Design *design, std::setcells()) { std::string celltype = cell->type.str(); - if (celltype.compare(0, strlen("$array:"), "$array:")) + if (celltype.compare(0, strlen("$array:"), "$array:") == 0) celltype = basic_cell_type(celltype); if (design->module(celltype)) hierarchy_worker(design, used, design->module(celltype), indent+4); @@ -520,7 +520,7 @@ int find_top_mod_score(Design *design, Module *module, dict &db) for (auto cell : module->cells()) { std::string celltype = cell->type.str(); // Is this an array instance - if (celltype.compare(0, strlen("$array:"), "$array:")) + if (celltype.compare(0, strlen("$array:"), "$array:") == 0) celltype = basic_cell_type(celltype); // Is this cell a module instance? auto instModule = design->module(celltype); -- cgit v1.2.3 From ee7c970367c68fe1a02a237ed01f2845a03cf9b2 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 6 Aug 2019 19:08:33 -0700 Subject: IdString::str().substr() -> IdString::substr() --- passes/hierarchy/hierarchy.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index ff5c3b6a1..1319225ff 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -203,7 +203,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check int idx = std::stoi(cell->type.substr(pos_idx + 1, pos_num)); int num = std::stoi(cell->type.substr(pos_num + 1, pos_type)); array_cells[cell] = std::pair(idx, num); - cell->type = cell->type.str().substr(pos_type + 1); + cell->type = cell->type.substr(pos_type + 1); } dict interfaces_to_add_to_submodule; dict modports_used_in_submodule; -- cgit v1.2.3 From 48d0f994064557dc0832748e17133ee2eac88cbf Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 7 Aug 2019 11:09:17 -0700 Subject: stoi -> atoi --- passes/cmds/add.cc | 2 +- passes/cmds/chformal.cc | 4 ++-- passes/cmds/qwp.cc | 2 +- passes/cmds/scc.cc | 4 ++-- passes/cmds/select.cc | 16 ++++++++-------- passes/cmds/setundef.cc | 2 +- passes/cmds/show.cc | 2 +- passes/cmds/tee.cc | 2 +- passes/equiv/equiv_induct.cc | 2 +- passes/equiv/equiv_simple.cc | 2 +- passes/equiv/equiv_struct.cc | 2 +- passes/hierarchy/hierarchy.cc | 6 +++--- passes/memory/memory_bram.cc | 8 ++++---- passes/opt/opt_lut.cc | 4 ++-- passes/opt/pmux2shiftx.cc | 4 ++-- passes/opt/share.cc | 2 +- passes/sat/freduce.cc | 2 +- passes/sat/mutate.cc | 34 +++++++++++++++++----------------- passes/sat/sat.cc | 26 +++++++++++++------------- passes/sat/sim.cc | 4 ++-- passes/techmap/abc.cc | 14 +++++++------- passes/techmap/abc9.cc | 12 ++++++------ passes/techmap/dff2dffe.cc | 2 +- passes/techmap/extract.cc | 10 +++++----- passes/techmap/extract_counter.cc | 2 +- passes/techmap/extract_fa.cc | 4 ++-- passes/techmap/flowmap.cc | 12 ++++++------ passes/techmap/muxcover.cc | 10 +++++----- passes/techmap/nlutmap.cc | 2 +- passes/techmap/shregmap.cc | 8 ++++---- passes/techmap/techmap.cc | 2 +- passes/tests/test_abcloop.cc | 4 ++-- passes/tests/test_autotb.cc | 4 ++-- passes/tests/test_cell.cc | 4 ++-- 34 files changed, 110 insertions(+), 110 deletions(-) (limited to 'passes') diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc index 971de1d00..af6f7043d 100644 --- a/passes/cmds/add.cc +++ b/passes/cmds/add.cc @@ -130,7 +130,7 @@ struct AddPass : public Pass { if (arg == "-global_input") arg_flag_global = true; arg_name = args[++argidx]; - arg_width = std::stoi(args[++argidx]); + arg_width = atoi(args[++argidx].c_str()); continue; } break; diff --git a/passes/cmds/chformal.cc b/passes/cmds/chformal.cc index c97b204af..7e32da65f 100644 --- a/passes/cmds/chformal.cc +++ b/passes/cmds/chformal.cc @@ -106,12 +106,12 @@ struct ChformalPass : public Pass { } if (mode == 0 && args[argidx] == "-delay" && argidx+1 < args.size()) { mode = 'd'; - mode_arg = std::stoi(args[++argidx]); + mode_arg = atoi(args[++argidx].c_str()); continue; } if (mode == 0 && args[argidx] == "-skip" && argidx+1 < args.size()) { mode = 's'; - mode_arg = std::stoi(args[++argidx]); + mode_arg = atoi(args[++argidx].c_str()); continue; } if ((mode == 0 || mode == 'c') && args[argidx] == "-assert2assume") { diff --git a/passes/cmds/qwp.cc b/passes/cmds/qwp.cc index 4d53b3995..adbe89e31 100644 --- a/passes/cmds/qwp.cc +++ b/passes/cmds/qwp.cc @@ -830,7 +830,7 @@ struct QwpPass : public Pass { continue; } if (args[argidx] == "-grid" && argidx+1 < args.size()) { - config.grid = 1.0 / std::stoi(args[++argidx]); + config.grid = 1.0 / atoi(args[++argidx].c_str()); continue; } if (args[argidx] == "-dump" && argidx+1 < args.size()) { diff --git a/passes/cmds/scc.cc b/passes/cmds/scc.cc index ad924e1bf..99f4fbae8 100644 --- a/passes/cmds/scc.cc +++ b/passes/cmds/scc.cc @@ -269,11 +269,11 @@ struct SccPass : public Pass { size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { if (args[argidx] == "-max_depth" && argidx+1 < args.size()) { - maxDepth = std::stoi(args[++argidx]); + maxDepth = atoi(args[++argidx].c_str()); continue; } if (args[argidx] == "-expect" && argidx+1 < args.size()) { - expect = std::stoi(args[++argidx]); + expect = atoi(args[++argidx].c_str()); continue; } if (args[argidx] == "-nofeedback") { diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index e857e655f..b5e8ef1af 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -517,7 +517,7 @@ static void select_op_expand(RTLIL::Design *design, std::string arg, char mode, size_t endpos = arg.find_first_not_of("0123456789", pos); if (endpos == std::string::npos) endpos = arg.size(); - levels = std::stoi(arg.substr(pos, endpos-pos)); + levels = atoi(arg.substr(pos, endpos-pos).c_str()); pos = endpos; } @@ -526,7 +526,7 @@ static void select_op_expand(RTLIL::Design *design, std::string arg, char mode, if (endpos == std::string::npos) endpos = arg.size(); if (int(endpos) > pos) - rem_objects = std::stoi(arg.substr(pos, endpos-pos)); + rem_objects = atoi(arg.substr(pos, endpos-pos).c_str()); pos = endpos; } @@ -823,15 +823,15 @@ static void select_stmt(RTLIL::Design *design, std::string arg) if (arg_memb.substr(0, 2) == "s:") { size_t delim = arg_memb.substr(2).find(':'); if (delim == std::string::npos) { - int width = std::stoi(arg_memb.substr(2)); + int width = atoi(arg_memb.substr(2).c_str()); for (auto &it : mod->wires_) if (it.second->width == width) sel.selected_members[mod->name].insert(it.first); } else { std::string min_str = arg_memb.substr(2, delim); std::string max_str = arg_memb.substr(2+delim+1); - int min_width = min_str.empty() ? 0 : std::stoi(min_str); - int max_width = max_str.empty() ? -1 : std::stoi(max_str); + int min_width = min_str.empty() ? 0 : atoi(min_str.c_str()); + int max_width = max_str.empty() ? -1 : atoi(max_str.c_str()); for (auto &it : mod->wires_) if (min_width <= it.second->width && (it.second->width <= max_width || max_width == -1)) sel.selected_members[mod->name].insert(it.first); @@ -1230,15 +1230,15 @@ struct SelectPass : public Pass { continue; } if (arg == "-assert-count" && argidx+1 < args.size()) { - assert_count = std::stoi(args[++argidx]); + assert_count = atoi(args[++argidx].c_str()); continue; } if (arg == "-assert-max" && argidx+1 < args.size()) { - assert_max = std::stoi(args[++argidx]); + assert_max = atoi(args[++argidx].c_str()); continue; } if (arg == "-assert-min" && argidx+1 < args.size()) { - assert_min = std::stoi(args[++argidx]); + assert_min = atoi(args[++argidx].c_str()); continue; } if (arg == "-clear") { diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index 0e3c0c853..3eedc86b8 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -210,7 +210,7 @@ struct SetundefPass : public Pass { if (args[argidx] == "-random" && !got_value && argidx+1 < args.size()) { got_value = true; worker.next_bit_mode = MODE_RANDOM; - worker.next_bit_state = std::stoi(args[++argidx]) + 1; + worker.next_bit_state = atoi(args[++argidx].c_str()) + 1; for (int i = 0; i < 10; i++) worker.next_bit(); continue; diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index 3af477bd9..cf729215f 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -740,7 +740,7 @@ struct ShowPass : public Pass { continue; } if (arg == "-colors" && argidx+1 < args.size()) { - colorSeed = std::stoi(args[++argidx]); + colorSeed = atoi(args[++argidx].c_str()); for (int i = 0; i < 100; i++) colorSeed = ShowWorker::xorshift32(colorSeed); continue; diff --git a/passes/cmds/tee.cc b/passes/cmds/tee.cc index e0a74099a..1a44bdaec 100644 --- a/passes/cmds/tee.cc +++ b/passes/cmds/tee.cc @@ -79,7 +79,7 @@ struct TeePass : public Pass { continue; } if (GetSize(args[argidx]) >= 2 && (args[argidx][0] == '-' || args[argidx][0] == '+') && args[argidx][1] >= '0' && args[argidx][1] <= '9') { - log_verbose_level += std::stoi(args[argidx]); + log_verbose_level += atoi(args[argidx].c_str()); continue; } break; diff --git a/passes/equiv/equiv_induct.cc b/passes/equiv/equiv_induct.cc index e3af16e2d..bcc68d6d2 100644 --- a/passes/equiv/equiv_induct.cc +++ b/passes/equiv/equiv_induct.cc @@ -207,7 +207,7 @@ struct EquivInductPass : public Pass { continue; } if (args[argidx] == "-seq" && argidx+1 < args.size()) { - max_seq = std::stoi(args[++argidx]); + max_seq = atoi(args[++argidx].c_str()); continue; } break; diff --git a/passes/equiv/equiv_simple.cc b/passes/equiv/equiv_simple.cc index 1f80e117d..c2fab26f2 100644 --- a/passes/equiv/equiv_simple.cc +++ b/passes/equiv/equiv_simple.cc @@ -325,7 +325,7 @@ struct EquivSimplePass : public Pass { continue; } if (args[argidx] == "-seq" && argidx+1 < args.size()) { - max_seq = std::stoi(args[++argidx]); + max_seq = atoi(args[++argidx].c_str()); continue; } break; diff --git a/passes/equiv/equiv_struct.cc b/passes/equiv/equiv_struct.cc index 0bae55802..a7973fd04 100644 --- a/passes/equiv/equiv_struct.cc +++ b/passes/equiv/equiv_struct.cc @@ -338,7 +338,7 @@ struct EquivStructPass : public Pass { continue; } if (args[argidx] == "-maxiter" && argidx+1 < args.size()) { - max_iter = std::stoi(args[++argidx]); + max_iter = atoi(args[++argidx].c_str()); continue; } break; diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 1319225ff..fd95b94b2 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -200,8 +200,8 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check int pos_idx = pos[0]; int pos_num = pos[1]; int pos_type = pos[2]; - int idx = std::stoi(cell->type.substr(pos_idx + 1, pos_num)); - int num = std::stoi(cell->type.substr(pos_num + 1, pos_type)); + int idx = atoi(cell->type.substr(pos_idx + 1, pos_num).c_str()); + int num = atoi(cell->type.substr(pos_num + 1, pos_type).c_str()); array_cells[cell] = std::pair(idx, num); cell->type = cell->type.substr(pos_type + 1); } @@ -423,7 +423,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check int conn_size = conn.second.size(); RTLIL::IdString portname = conn.first; if (portname.begins_with("$")) { - int port_id = std::stoi(portname.substr(1)); + int port_id = atoi(portname.substr(1).c_str()); for (auto &wire_it : mod->wires_) if (wire_it.second->port_id == port_id) { portname = wire_it.first; diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc index 2913400c5..aa8f94149 100644 --- a/passes/memory/memory_bram.cc +++ b/passes/memory/memory_bram.cc @@ -176,7 +176,7 @@ struct rules_t bool parse_single_int(const char *stmt, int &value) { if (GetSize(tokens) == 2 && tokens[0] == stmt) { - value = std::stoi(tokens[1]); + value = atoi(tokens[1].c_str()); return true; } return false; @@ -187,7 +187,7 @@ struct rules_t if (GetSize(tokens) >= 2 && tokens[0] == stmt) { value.resize(GetSize(tokens)-1); for (int i = 1; i < GetSize(tokens); i++) - value[i-1] = std::stoi(tokens[i]); + value[i-1] = atoi(tokens[i].c_str()); return true; } return false; @@ -297,12 +297,12 @@ struct rules_t } if (GetSize(tokens) == 3 && tokens[0] == "min") { - data.min_limits[tokens[1]] = std::stoi(tokens[2]); + data.min_limits[tokens[1]] = atoi(tokens[2].c_str()); continue; } if (GetSize(tokens) == 3 && tokens[0] == "max") { - data.max_limits[tokens[1]] = std::stoi(tokens[2]); + data.max_limits[tokens[1]] = atoi(tokens[2].c_str()); continue; } diff --git a/passes/opt/opt_lut.cc b/passes/opt/opt_lut.cc index 6d97c0bb4..587ef878a 100644 --- a/passes/opt/opt_lut.cc +++ b/passes/opt/opt_lut.cc @@ -555,14 +555,14 @@ struct OptLutPass : public Pass { if (conn_tokens.size() != 2) log_cmd_error("Invalid format of -dlogic signal mapping.\n"); IdString logic_port = "\\" + conn_tokens[0]; - int lut_input = std::stoi(conn_tokens[1]); + int lut_input = atoi(conn_tokens[1].c_str()); dlogic[type][lut_input] = logic_port; } continue; } if (args[argidx] == "-limit" && argidx + 1 < args.size()) { - limit = std::stoi(args[++argidx]); + limit = atoi(args[++argidx].c_str()); continue; } break; diff --git a/passes/opt/pmux2shiftx.cc b/passes/opt/pmux2shiftx.cc index e571ed3c6..65d8b8f32 100644 --- a/passes/opt/pmux2shiftx.cc +++ b/passes/opt/pmux2shiftx.cc @@ -240,11 +240,11 @@ struct Pmux2ShiftxPass : public Pass { size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { if (args[argidx] == "-min_density" && argidx+1 < args.size()) { - min_density = std::stoi(args[++argidx]); + min_density = atoi(args[++argidx].c_str()); continue; } if (args[argidx] == "-min_choices" && argidx+1 < args.size()) { - min_choices = std::stoi(args[++argidx]); + min_choices = atoi(args[++argidx].c_str()); continue; } if (args[argidx] == "-onehot" && argidx+1 < args.size() && args[argidx+1] == "ignore") { diff --git a/passes/opt/share.cc b/passes/opt/share.cc index ea5bf8d33..7f66f749f 100644 --- a/passes/opt/share.cc +++ b/passes/opt/share.cc @@ -1521,7 +1521,7 @@ struct SharePass : public Pass { continue; } if (args[argidx] == "-limit" && argidx+1 < args.size()) { - config.limit = std::stoi(args[++argidx]); + config.limit = atoi(args[++argidx].c_str()); continue; } break; diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index 781b5e3cc..f29631639 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -816,7 +816,7 @@ struct FreducePass : public Pass { continue; } if (args[argidx] == "-stop" && argidx+1 < args.size()) { - reduce_stop_at = std::stoi(args[++argidx]); + reduce_stop_at = atoi(args[++argidx].c_str()); continue; } if (args[argidx] == "-dump" && argidx+1 < args.size()) { diff --git a/passes/sat/mutate.cc b/passes/sat/mutate.cc index a4b2f5eb5..b53bbfeb2 100644 --- a/passes/sat/mutate.cc +++ b/passes/sat/mutate.cc @@ -803,7 +803,7 @@ struct MutatePass : public Pass { for (argidx = 1; argidx < args.size(); argidx++) { if (args[argidx] == "-list" && argidx+1 < args.size()) { - N = std::stoi(args[++argidx]); + N = atoi(args[++argidx].c_str()); continue; } if (args[argidx] == "-o" && argidx+1 < args.size()) { @@ -815,7 +815,7 @@ struct MutatePass : public Pass { continue; } if (args[argidx] == "-seed" && argidx+1 < args.size()) { - opts.seed = std::stoi(args[++argidx]); + opts.seed = atoi(args[++argidx].c_str()); continue; } if (args[argidx] == "-none") { @@ -828,8 +828,8 @@ struct MutatePass : public Pass { } if (args[argidx] == "-ctrl" && argidx+3 < args.size()) { opts.ctrl_name = RTLIL::escape_id(args[++argidx]); - opts.ctrl_width = std::stoi(args[++argidx]); - opts.ctrl_value = std::stoi(args[++argidx]); + opts.ctrl_width = atoi(args[++argidx].c_str()); + opts.ctrl_value = atoi(args[++argidx].c_str()); continue; } if (args[argidx] == "-module" && argidx+1 < args.size()) { @@ -845,11 +845,11 @@ struct MutatePass : public Pass { continue; } if (args[argidx] == "-portbit" && argidx+1 < args.size()) { - opts.portbit = std::stoi(args[++argidx]); + opts.portbit = atoi(args[++argidx].c_str()); continue; } if (args[argidx] == "-ctrlbit" && argidx+1 < args.size()) { - opts.ctrlbit = std::stoi(args[++argidx]); + opts.ctrlbit = atoi(args[++argidx].c_str()); continue; } if (args[argidx] == "-wire" && argidx+1 < args.size()) { @@ -857,7 +857,7 @@ struct MutatePass : public Pass { continue; } if (args[argidx] == "-wirebit" && argidx+1 < args.size()) { - opts.wirebit = std::stoi(args[++argidx]); + opts.wirebit = atoi(args[++argidx].c_str()); continue; } if (args[argidx] == "-src" && argidx+1 < args.size()) { @@ -866,52 +866,52 @@ struct MutatePass : public Pass { } if (args[argidx] == "-cfg" && argidx+2 < args.size()) { if (args[argidx+1] == "pick_cover_prcnt") { - opts.pick_cover_prcnt = std::stoi(args[argidx+2]); + opts.pick_cover_prcnt = atoi(args[argidx+2].c_str()); argidx += 2; continue; } if (args[argidx+1] == "weight_cover") { - opts.weight_cover = std::stoi(args[argidx+2]); + opts.weight_cover = atoi(args[argidx+2].c_str()); argidx += 2; continue; } if (args[argidx+1] == "weight_pq_w") { - opts.weight_pq_w = std::stoi(args[argidx+2]); + opts.weight_pq_w = atoi(args[argidx+2].c_str()); argidx += 2; continue; } if (args[argidx+1] == "weight_pq_b") { - opts.weight_pq_b = std::stoi(args[argidx+2]); + opts.weight_pq_b = atoi(args[argidx+2].c_str()); argidx += 2; continue; } if (args[argidx+1] == "weight_pq_c") { - opts.weight_pq_c = std::stoi(args[argidx+2]); + opts.weight_pq_c = atoi(args[argidx+2].c_str()); argidx += 2; continue; } if (args[argidx+1] == "weight_pq_s") { - opts.weight_pq_s = std::stoi(args[argidx+2]); + opts.weight_pq_s = atoi(args[argidx+2].c_str()); argidx += 2; continue; } if (args[argidx+1] == "weight_pq_mw") { - opts.weight_pq_mw = std::stoi(args[argidx+2]); + opts.weight_pq_mw = atoi(args[argidx+2].c_str()); argidx += 2; continue; } if (args[argidx+1] == "weight_pq_mb") { - opts.weight_pq_mb = std::stoi(args[argidx+2]); + opts.weight_pq_mb = atoi(args[argidx+2].c_str()); argidx += 2; continue; } if (args[argidx+1] == "weight_pq_mc") { - opts.weight_pq_mc = std::stoi(args[argidx+2]); + opts.weight_pq_mc = atoi(args[argidx+2].c_str()); argidx += 2; continue; } if (args[argidx+1] == "weight_pq_ms") { - opts.weight_pq_ms = std::stoi(args[argidx+2]); + opts.weight_pq_ms = atoi(args[argidx+2].c_str()); argidx += 2; continue; } diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 847ca0e1d..80498f5b4 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -1102,23 +1102,23 @@ struct SatPass : public Pass { continue; } if (args[argidx] == "-timeout" && argidx+1 < args.size()) { - timeout = std::stoi(args[++argidx]); + timeout = std::atoi(args[++argidx].c_str()); continue; } if (args[argidx] == "-max" && argidx+1 < args.size()) { - loopcount = std::stoi(args[++argidx]); + loopcount = std::atoi(args[++argidx].c_str()); continue; } if (args[argidx] == "-maxsteps" && argidx+1 < args.size()) { - maxsteps = std::stoi(args[++argidx]); + maxsteps = std::atoi(args[++argidx].c_str()); continue; } if (args[argidx] == "-initsteps" && argidx+1 < args.size()) { - initsteps = std::stoi(args[++argidx]); + initsteps = std::atoi(args[++argidx].c_str()); continue; } if (args[argidx] == "-stepsize" && argidx+1 < args.size()) { - stepsize = max(1, std::stoi(args[++argidx])); + stepsize = max(1, std::atoi(args[++argidx].c_str())); continue; } if (args[argidx] == "-ignore_div_by_zero") { @@ -1185,7 +1185,7 @@ struct SatPass : public Pass { continue; } if (args[argidx] == "-tempinduct-skip" && argidx+1 < args.size()) { - tempinduct_skip = std::stoi(args[++argidx]); + tempinduct_skip = atoi(args[++argidx].c_str()); continue; } if (args[argidx] == "-prove" && argidx+2 < args.size()) { @@ -1206,39 +1206,39 @@ struct SatPass : public Pass { continue; } if (args[argidx] == "-prove-skip" && argidx+1 < args.size()) { - prove_skip = std::stoi(args[++argidx]); + prove_skip = atoi(args[++argidx].c_str()); continue; } if (args[argidx] == "-seq" && argidx+1 < args.size()) { - seq_len = std::stoi(args[++argidx]); + seq_len = atoi(args[++argidx].c_str()); continue; } if (args[argidx] == "-set-at" && argidx+3 < args.size()) { - int timestep = std::stoi(args[++argidx]); + int timestep = atoi(args[++argidx].c_str()); std::string lhs = args[++argidx]; std::string rhs = args[++argidx]; sets_at[timestep].push_back(std::pair(lhs, rhs)); continue; } if (args[argidx] == "-unset-at" && argidx+2 < args.size()) { - int timestep = std::stoi(args[++argidx]); + int timestep = atoi(args[++argidx].c_str()); unsets_at[timestep].push_back(args[++argidx]); continue; } if (args[argidx] == "-set-def-at" && argidx+2 < args.size()) { - int timestep = std::stoi(args[++argidx]); + int timestep = atoi(args[++argidx].c_str()); sets_def_at[timestep].push_back(args[++argidx]); enable_undef = true; continue; } if (args[argidx] == "-set-any-undef-at" && argidx+2 < args.size()) { - int timestep = std::stoi(args[++argidx]); + int timestep = atoi(args[++argidx].c_str()); sets_any_undef_at[timestep].push_back(args[++argidx]); enable_undef = true; continue; } if (args[argidx] == "-set-all-undef-at" && argidx+2 < args.size()) { - int timestep = std::stoi(args[++argidx]); + int timestep = atoi(args[++argidx].c_str()); sets_all_undef_at[timestep].push_back(args[++argidx]); enable_undef = true; continue; diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index cb102e8bf..4c3022c70 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -803,11 +803,11 @@ struct SimPass : public Pass { continue; } if (args[argidx] == "-n" && argidx+1 < args.size()) { - numcycles = std::stoi(args[++argidx]); + numcycles = atoi(args[++argidx].c_str()); continue; } if (args[argidx] == "-rstlen" && argidx+1 < args.size()) { - worker.rstlen = std::stoi(args[++argidx]); + worker.rstlen = atoi(args[++argidx].c_str()); continue; } if (args[argidx] == "-clock" && argidx+1 < args.size()) { diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index 5509c8c12..76634cb31 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -343,7 +343,7 @@ std::string remap_name(RTLIL::IdString abc_name, RTLIL::Wire **orig_wire = nullp abc_sname.erase(0, 5); if (std::isdigit(abc_sname.at(0))) { - int sid = std::stoi(abc_sname); + int sid = std::atoi(abc_sname.c_str()); size_t postfix_start = abc_sname.find_first_not_of("0123456789"); std::string postfix = postfix_start != std::string::npos ? abc_sname.substr(postfix_start) : ""; @@ -1564,10 +1564,10 @@ struct AbcPass : public Pass { size_t pos = arg.find_first_of(':'); int lut_mode = 0, lut_mode2 = 0; if (pos != string::npos) { - lut_mode = std::stoi(arg.substr(0, pos)); - lut_mode2 = std::stoi(arg.substr(pos+1)); + lut_mode = std::atoi(arg.substr(0, pos).c_str()); + lut_mode2 = std::atoi(arg.substr(pos+1).c_str()); } else { - lut_mode = std::stoi(arg); + lut_mode = std::atoi(arg.c_str()); lut_mode2 = lut_mode; } lut_costs.clear(); @@ -1584,10 +1584,10 @@ struct AbcPass : public Pass { if (GetSize(parts) == 0 && !lut_costs.empty()) lut_costs.push_back(lut_costs.back()); else if (GetSize(parts) == 1) - lut_costs.push_back(std::stoi(parts.at(0))); + lut_costs.push_back(atoi(parts.at(0).c_str())); else if (GetSize(parts) == 2) - while (GetSize(lut_costs) < std::stoi(parts.at(0))) - lut_costs.push_back(std::stoi(parts.at(1))); + while (GetSize(lut_costs) < std::atoi(parts.at(0).c_str())) + lut_costs.push_back(atoi(parts.at(1).c_str())); else log_cmd_error("Invalid -luts syntax.\n"); } diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 36e3b4e65..34919cf07 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -999,8 +999,8 @@ struct Abc9Pass : public Pass { size_t pos = arg.find_first_of(':'); int lut_mode = 0, lut_mode2 = 0; if (pos != string::npos) { - lut_mode = std::stoi(arg.substr(0, pos)); - lut_mode2 = std::stoi(arg.substr(pos+1)); + lut_mode = atoi(arg.substr(0, pos).c_str()); + lut_mode2 = atoi(arg.substr(pos+1).c_str()); } else { pos = arg.find_first_of('.'); if (pos != string::npos) { @@ -1010,7 +1010,7 @@ struct Abc9Pass : public Pass { lut_file = std::string(pwd) + "/" + lut_file; } else { - lut_mode = std::stoi(arg); + lut_mode = atoi(arg.c_str()); lut_mode2 = lut_mode; } } @@ -1028,10 +1028,10 @@ struct Abc9Pass : public Pass { if (GetSize(parts) == 0 && !lut_costs.empty()) lut_costs.push_back(lut_costs.back()); else if (GetSize(parts) == 1) - lut_costs.push_back(std::stoi(parts.at(0))); + lut_costs.push_back(atoi(parts.at(0).c_str())); else if (GetSize(parts) == 2) - while (GetSize(lut_costs) < std::stoi(parts.at(0))) - lut_costs.push_back(std::stoi(parts.at(1))); + while (GetSize(lut_costs) < atoi(parts.at(0).c_str())) + lut_costs.push_back(atoi(parts.at(1).c_str())); else log_cmd_error("Invalid -luts syntax.\n"); } diff --git a/passes/techmap/dff2dffe.cc b/passes/techmap/dff2dffe.cc index 44bc14628..8e947b4dc 100644 --- a/passes/techmap/dff2dffe.cc +++ b/passes/techmap/dff2dffe.cc @@ -304,7 +304,7 @@ struct Dff2dffePass : public Pass { } if (args[argidx] == "-unmap-mince" && argidx + 1 < args.size()) { unmap_mode = true; - min_ce_use = std::stoi(args[++argidx]); + min_ce_use = atoi(args[++argidx].c_str()); continue; } if (args[argidx] == "-direct" && argidx + 2 < args.size()) { diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index cf9743806..fff90f13c 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -476,16 +476,16 @@ struct ExtractPass : public Pass { continue; } if (args[argidx] == "-mine_cells_span" && argidx+2 < args.size()) { - mine_cells_min = std::stoi(args[++argidx]); - mine_cells_max = std::stoi(args[++argidx]); + mine_cells_min = atoi(args[++argidx].c_str()); + mine_cells_max = atoi(args[++argidx].c_str()); continue; } if (args[argidx] == "-mine_min_freq" && argidx+1 < args.size()) { - mine_min_freq = std::stoi(args[++argidx]); + mine_min_freq = atoi(args[++argidx].c_str()); continue; } if (args[argidx] == "-mine_limit_matches_per_module" && argidx+1 < args.size()) { - mine_limit_mod = std::stoi(args[++argidx]); + mine_limit_mod = atoi(args[++argidx].c_str()); continue; } if (args[argidx] == "-mine_split" && argidx+2 < args.size()) { @@ -494,7 +494,7 @@ struct ExtractPass : public Pass { continue; } if (args[argidx] == "-mine_max_fanout" && argidx+1 < args.size()) { - mine_max_fanout = std::stoi(args[++argidx]); + mine_max_fanout = atoi(args[++argidx].c_str()); continue; } if (args[argidx] == "-verbose") { diff --git a/passes/techmap/extract_counter.cc b/passes/techmap/extract_counter.cc index da56e087b..a8d0bc834 100644 --- a/passes/techmap/extract_counter.cc +++ b/passes/techmap/extract_counter.cc @@ -613,7 +613,7 @@ struct ExtractCounterPass : public Pass { if (args[argidx] == "-maxwidth" && argidx+1 < args.size()) { - maxwidth = std::stoi(args[++argidx]); + maxwidth = atoi(args[++argidx].c_str()); continue; } } diff --git a/passes/techmap/extract_fa.cc b/passes/techmap/extract_fa.cc index 0b5b6a111..b541ceb6b 100644 --- a/passes/techmap/extract_fa.cc +++ b/passes/techmap/extract_fa.cc @@ -580,11 +580,11 @@ struct ExtractFaPass : public Pass { continue; } if (args[argidx] == "-d" && argidx+2 < args.size()) { - config.maxdepth = std::stoi(args[++argidx]); + config.maxdepth = atoi(args[++argidx].c_str()); continue; } if (args[argidx] == "-b" && argidx+2 < args.size()) { - config.maxbreadth = std::stoi(args[++argidx]); + config.maxbreadth = atoi(args[++argidx].c_str()); continue; } break; diff --git a/passes/techmap/flowmap.cc b/passes/techmap/flowmap.cc index 3e66fcacc..96d0df5f8 100644 --- a/passes/techmap/flowmap.cc +++ b/passes/techmap/flowmap.cc @@ -1525,12 +1525,12 @@ struct FlowmapPass : public Pass { { if (args[argidx] == "-maxlut" && argidx + 1 < args.size()) { - order = std::stoi(args[++argidx]); + order = atoi(args[++argidx].c_str()); continue; } if (args[argidx] == "-minlut" && argidx + 1 < args.size()) { - minlut = std::stoi(args[++argidx]); + minlut = atoi(args[++argidx].c_str()); continue; } if (args[argidx] == "-cells" && argidx + 1 < args.size()) @@ -1545,23 +1545,23 @@ struct FlowmapPass : public Pass { } if (args[argidx] == "-r-alpha" && argidx + 1 < args.size()) { - r_alpha = std::stoi(args[++argidx]); + r_alpha = atoi(args[++argidx].c_str()); continue; } if (args[argidx] == "-r-beta" && argidx + 1 < args.size()) { - r_beta = std::stoi(args[++argidx]); + r_beta = atoi(args[++argidx].c_str()); continue; } if (args[argidx] == "-r-gamma" && argidx + 1 < args.size()) { - r_gamma = std::stoi(args[++argidx]); + r_gamma = atoi(args[++argidx].c_str()); continue; } if (args[argidx] == "-optarea" && argidx + 1 < args.size()) { relax = true; - optarea = std::stoi(args[++argidx]); + optarea = atoi(args[++argidx].c_str()); continue; } if (args[argidx] == "-debug") diff --git a/passes/techmap/muxcover.cc b/passes/techmap/muxcover.cc index d53378a29..45987392e 100644 --- a/passes/techmap/muxcover.cc +++ b/passes/techmap/muxcover.cc @@ -676,14 +676,14 @@ struct MuxcoverPass : public Pass { { const auto &arg = args[argidx]; if (arg.size() >= 6 && arg.substr(0,6) == "-mux2=") { - cost_mux2 = std::stoi(arg.substr(6)); + cost_mux2 = atoi(arg.substr(6).c_str()); continue; } if (arg.size() >= 5 && arg.substr(0,5) == "-mux4") { use_mux4 = true; if (arg.size() > 5) { if (arg[5] != '=') break; - cost_mux4 = std::stoi(arg.substr(6)); + cost_mux4 = atoi(arg.substr(6).c_str()); } continue; } @@ -691,7 +691,7 @@ struct MuxcoverPass : public Pass { use_mux8 = true; if (arg.size() > 5) { if (arg[5] != '=') break; - cost_mux8 = std::stoi(arg.substr(6)); + cost_mux8 = atoi(arg.substr(6).c_str()); } continue; } @@ -699,12 +699,12 @@ struct MuxcoverPass : public Pass { use_mux16 = true; if (arg.size() > 6) { if (arg[6] != '=') break; - cost_mux16 = std::stoi(arg.substr(7)); + cost_mux16 = atoi(arg.substr(7).c_str()); } continue; } if (arg.size() >= 6 && arg.substr(0,6) == "-dmux=") { - cost_dmux = std::stoi(arg.substr(6)); + cost_dmux = atoi(arg.substr(6).c_str()); continue; } if (arg == "-nodecode") { diff --git a/passes/techmap/nlutmap.cc b/passes/techmap/nlutmap.cc index 9ac39ed05..cc765d89c 100644 --- a/passes/techmap/nlutmap.cc +++ b/passes/techmap/nlutmap.cc @@ -163,7 +163,7 @@ struct NlutmapPass : public Pass { vector tokens = split_tokens(args[++argidx], ","); config.luts.clear(); for (auto &token : tokens) - config.luts.push_back(std::stoi(token)); + config.luts.push_back(atoi(token.c_str())); continue; } if (args[argidx] == "-assert") { diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index 06eb7b793..004ab1eb9 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -655,19 +655,19 @@ struct ShregmapPass : public Pass { continue; } if (args[argidx] == "-minlen" && argidx+1 < args.size()) { - opts.minlen = std::stoi(args[++argidx]); + opts.minlen = atoi(args[++argidx].c_str()); continue; } if (args[argidx] == "-maxlen" && argidx+1 < args.size()) { - opts.maxlen = std::stoi(args[++argidx]); + opts.maxlen = atoi(args[++argidx].c_str()); continue; } if (args[argidx] == "-keep_before" && argidx+1 < args.size()) { - opts.keep_before = std::stoi(args[++argidx]); + opts.keep_before = atoi(args[++argidx].c_str()); continue; } if (args[argidx] == "-keep_after" && argidx+1 < args.size()) { - opts.keep_after = std::stoi(args[++argidx]); + opts.keep_after = atoi(args[++argidx].c_str()); continue; } if (args[argidx] == "-tech" && argidx+1 < args.size() && opts.tech == nullptr) { diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index d10420ae8..ceb053825 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -1072,7 +1072,7 @@ struct TechmapPass : public Pass { continue; } if (args[argidx] == "-max_iter" && argidx+1 < args.size()) { - max_iter = std::stoi(args[++argidx]); + max_iter = atoi(args[++argidx].c_str()); continue; } if (args[argidx] == "-D" && argidx+1 < args.size()) { diff --git a/passes/tests/test_abcloop.cc b/passes/tests/test_abcloop.cc index d5a167db1..5d5466afe 100644 --- a/passes/tests/test_abcloop.cc +++ b/passes/tests/test_abcloop.cc @@ -268,11 +268,11 @@ struct TestAbcloopPass : public Pass { for (argidx = 1; argidx < GetSize(args); argidx++) { if (args[argidx] == "-n" && argidx+1 < GetSize(args)) { - num_iter = std::stoi(args[++argidx]); + num_iter = atoi(args[++argidx].c_str()); continue; } if (args[argidx] == "-s" && argidx+1 < GetSize(args)) { - xorshift32_state = std::stoi(args[++argidx]); + xorshift32_state = atoi(args[++argidx].c_str()); continue; } break; diff --git a/passes/tests/test_autotb.cc b/passes/tests/test_autotb.cc index 198007b87..bfb1d6642 100644 --- a/passes/tests/test_autotb.cc +++ b/passes/tests/test_autotb.cc @@ -360,11 +360,11 @@ struct TestAutotbBackend : public Backend { for (argidx = 1; argidx < GetSize(args); argidx++) { if (args[argidx] == "-n" && argidx+1 < GetSize(args)) { - num_iter = std::stoi(args[++argidx]); + num_iter = atoi(args[++argidx].c_str()); continue; } if (args[argidx] == "-seed" && argidx+1 < GetSize(args)) { - seed = std::stoi(args[++argidx]); + seed = atoi(args[++argidx].c_str()); continue; } break; diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index 7c58ec158..e360b5edb 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -730,11 +730,11 @@ struct TestCellPass : public Pass { for (argidx = 1; argidx < GetSize(args); argidx++) { if (args[argidx] == "-n" && argidx+1 < GetSize(args)) { - num_iter = std::stoi(args[++argidx]); + num_iter = atoi(args[++argidx].c_str()); continue; } if (args[argidx] == "-s" && argidx+1 < GetSize(args)) { - xorshift32_state = std::stoi(args[++argidx]); + xorshift32_state = atoi(args[++argidx].c_str()); continue; } if (args[argidx] == "-map" && argidx+1 < GetSize(args)) { -- cgit v1.2.3 From 0c78c62d6c043925293c0ff934c41f2df6932b85 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 7 Aug 2019 11:11:14 -0700 Subject: Remove std:: namespace --- passes/sat/sat.cc | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'passes') diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 80498f5b4..e4654d835 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -1102,23 +1102,23 @@ struct SatPass : public Pass { continue; } if (args[argidx] == "-timeout" && argidx+1 < args.size()) { - timeout = std::atoi(args[++argidx].c_str()); + timeout = atoi(args[++argidx].c_str()); continue; } if (args[argidx] == "-max" && argidx+1 < args.size()) { - loopcount = std::atoi(args[++argidx].c_str()); + loopcount = atoi(args[++argidx].c_str()); continue; } if (args[argidx] == "-maxsteps" && argidx+1 < args.size()) { - maxsteps = std::atoi(args[++argidx].c_str()); + maxsteps = atoi(args[++argidx].c_str()); continue; } if (args[argidx] == "-initsteps" && argidx+1 < args.size()) { - initsteps = std::atoi(args[++argidx].c_str()); + initsteps = atoi(args[++argidx].c_str()); continue; } if (args[argidx] == "-stepsize" && argidx+1 < args.size()) { - stepsize = max(1, std::atoi(args[++argidx].c_str())); + stepsize = max(1, atoi(args[++argidx].c_str())); continue; } if (args[argidx] == "-ignore_div_by_zero") { -- cgit v1.2.3 From 71649969213863b2695f1c51956886fc7879c3e6 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 7 Aug 2019 11:12:38 -0700 Subject: RTLIL::S{0,1} -> State::S{0,1} --- passes/fsm/fsm_extract.cc | 28 ++++++++++++++-------------- passes/opt/muxpack.cc | 2 +- passes/techmap/abc9.cc | 2 +- passes/techmap/alumacc.cc | 12 ++++++------ passes/techmap/dff2dffe.cc | 2 +- passes/techmap/maccmap.cc | 16 ++++++++-------- passes/tests/test_cell.cc | 34 +++++++++++++++++----------------- 7 files changed, 48 insertions(+), 48 deletions(-) (limited to 'passes') diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index 6095eaf30..a85c3bec0 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -168,7 +168,7 @@ undef_bit_in_next_state: ctrl_in_bit_indices[ctrl_in[i]] = i; for (auto &it : ctrl_in_bit_indices) - if (tr.ctrl_in.bits.at(it.second) == RTLIL::S1 && exclusive_ctrls.count(it.first) != 0) + if (tr.ctrl_in.bits.at(it.second) == State::S1 && exclusive_ctrls.count(it.first) != 0) for (auto &dc_bit : exclusive_ctrls.at(it.first)) if (ctrl_in_bit_indices.count(dc_bit)) tr.ctrl_in.bits.at(ctrl_in_bit_indices.at(dc_bit)) = RTLIL::State::Sa; @@ -216,13 +216,13 @@ undef_bit_in_next_state: ce.push(); dont_care.append(undef); ce.set(undef, constval.as_const()); - if (exclusive_ctrls.count(undef) && constval == RTLIL::S1) + if (exclusive_ctrls.count(undef) && constval == State::S1) for (auto &bit : exclusive_ctrls.at(undef)) { RTLIL::SigSpec bitval = bit; - if (ce.eval(bitval) && bitval != RTLIL::S0) + if (ce.eval(bitval) && bitval != State::S0) goto found_contradiction_1; else - ce.set(bit, RTLIL::S0); + ce.set(bit, State::S0); } find_transitions(ce, ce_nostop, fsm_data, states, state_in, ctrl_in, ctrl_out, dff_in, dont_care); found_contradiction_1: @@ -231,21 +231,21 @@ undef_bit_in_next_state: else { ce.push(), ce_nostop.push(); - ce.set(undef, RTLIL::S0); - ce_nostop.set(undef, RTLIL::S0); + ce.set(undef, State::S0); + ce_nostop.set(undef, State::S0); find_transitions(ce, ce_nostop, fsm_data, states, state_in, ctrl_in, ctrl_out, dff_in, dont_care); ce.pop(), ce_nostop.pop(); ce.push(), ce_nostop.push(); - ce.set(undef, RTLIL::S1); - ce_nostop.set(undef, RTLIL::S1); + ce.set(undef, State::S1); + ce_nostop.set(undef, State::S1); if (exclusive_ctrls.count(undef)) for (auto &bit : exclusive_ctrls.at(undef)) { RTLIL::SigSpec bitval = bit; - if ((ce.eval(bitval) || ce_nostop.eval(bitval)) && bitval != RTLIL::S0) + if ((ce.eval(bitval) || ce_nostop.eval(bitval)) && bitval != State::S0) goto found_contradiction_2; else - ce.set(bit, RTLIL::S0), ce_nostop.set(bit, RTLIL::S0); + ce.set(bit, State::S0), ce_nostop.set(bit, RTLIL::S0); } find_transitions(ce, ce_nostop, fsm_data, states, state_in, ctrl_in, ctrl_out, dff_in, dont_care); found_contradiction_2: @@ -263,8 +263,8 @@ static void extract_fsm(RTLIL::Wire *wire) RTLIL::SigSpec dff_in(RTLIL::State::Sm, wire->width); RTLIL::Const reset_state(RTLIL::State::Sx, wire->width); - RTLIL::SigSpec clk = RTLIL::S0; - RTLIL::SigSpec arst = RTLIL::S0; + RTLIL::SigSpec clk = State::S0; + RTLIL::SigSpec arst = State::S0; bool clk_polarity = true; bool arst_polarity = true; @@ -371,8 +371,8 @@ static void extract_fsm(RTLIL::Wire *wire) RTLIL::Cell *fsm_cell = module->addCell(stringf("$fsm$%s$%d", wire->name.c_str(), autoidx++), "$fsm"); fsm_cell->setPort("\\CLK", clk); fsm_cell->setPort("\\ARST", arst); - fsm_cell->parameters["\\CLK_POLARITY"] = clk_polarity ? RTLIL::S1 : RTLIL::S0; - fsm_cell->parameters["\\ARST_POLARITY"] = arst_polarity ? RTLIL::S1 : RTLIL::S0; + fsm_cell->parameters["\\CLK_POLARITY"] = clk_polarity ? State::S1 : State::S0; + fsm_cell->parameters["\\ARST_POLARITY"] = arst_polarity ? State::S1 : State::S0; fsm_cell->setPort("\\CTRL_IN", ctrl_in); fsm_cell->setPort("\\CTRL_OUT", ctrl_out); fsm_cell->parameters["\\NAME"] = RTLIL::Const(wire->name.str()); diff --git a/passes/opt/muxpack.cc b/passes/opt/muxpack.cc index 6697d6ca1..225c30d9a 100644 --- a/passes/opt/muxpack.cc +++ b/passes/opt/muxpack.cc @@ -49,7 +49,7 @@ struct ExclusiveDatabase } else if (cell->type == "$logic_not") { nonconst_sig = sigmap(cell->getPort("\\A")); - const_sig = Const(RTLIL::S0, GetSize(nonconst_sig)); + const_sig = Const(State::S0, GetSize(nonconst_sig)); y_port = sigmap(cell->getPort("\\Y")); } else if (cell->type == "$reduce_or") { diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 34919cf07..31c1d6f80 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -593,7 +593,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri c->setPort("\\Y", module->addWire(NEW_ID)); RTLIL::Wire *wire = module->wire(remap_name(y_bit.wire->name)); log_assert(wire); - module->connect(RTLIL::SigBit(wire, y_bit.offset), RTLIL::S1); + module->connect(RTLIL::SigBit(wire, y_bit.offset), State::S1); } else if (!lut_costs.empty() || !lut_file.empty()) { RTLIL::Cell* driver_lut = nullptr; diff --git a/passes/techmap/alumacc.cc b/passes/techmap/alumacc.cc index dc7d416b0..5c9e42fd4 100644 --- a/passes/techmap/alumacc.cc +++ b/passes/techmap/alumacc.cc @@ -315,7 +315,7 @@ struct AlumaccWorker } if (subtract_b) - C.append(RTLIL::S1); + C.append(State::S1); if (GetSize(C) > 1) goto next_macc; @@ -402,7 +402,7 @@ struct AlumaccWorker alunode_t *n = nullptr; for (auto node : sig_alu[RTLIL::SigSig(A, B)]) - if (node->is_signed == is_signed && node->invert_b && node->c == RTLIL::S1) { + if (node->is_signed == is_signed && node->invert_b && node->c == State::S1) { n = node; break; } @@ -411,7 +411,7 @@ struct AlumaccWorker n = new alunode_t; n->a = A; n->b = B; - n->c = RTLIL::S1; + n->c = State::S1; n->y = module->addWire(NEW_ID, max(GetSize(A), GetSize(B))); n->is_signed = is_signed; n->invert_b = true; @@ -440,7 +440,7 @@ struct AlumaccWorker alunode_t *n = nullptr; for (auto node : sig_alu[RTLIL::SigSig(A, B)]) - if (node->is_signed == is_signed && node->invert_b && node->c == RTLIL::S1) { + if (node->is_signed == is_signed && node->invert_b && node->c == State::S1) { n = node; break; } @@ -484,8 +484,8 @@ struct AlumaccWorker n->alu_cell->setPort("\\A", n->a); n->alu_cell->setPort("\\B", n->b); - n->alu_cell->setPort("\\CI", GetSize(n->c) ? n->c : RTLIL::S0); - n->alu_cell->setPort("\\BI", n->invert_b ? RTLIL::S1 : RTLIL::S0); + n->alu_cell->setPort("\\CI", GetSize(n->c) ? n->c : State::S0); + n->alu_cell->setPort("\\BI", n->invert_b ? State::S1 : State::S0); n->alu_cell->setPort("\\Y", n->y); n->alu_cell->setPort("\\X", module->addWire(NEW_ID, GetSize(n->y))); n->alu_cell->setPort("\\CO", module->addWire(NEW_ID, GetSize(n->y))); diff --git a/passes/techmap/dff2dffe.cc b/passes/techmap/dff2dffe.cc index 8e947b4dc..2dc577c73 100644 --- a/passes/techmap/dff2dffe.cc +++ b/passes/techmap/dff2dffe.cc @@ -167,7 +167,7 @@ struct Dff2dffeWorker } if (GetSize(or_input) == 0) - return RTLIL::S1; + return State::S1; if (GetSize(or_input) == 1) return or_input; diff --git a/passes/techmap/maccmap.cc b/passes/techmap/maccmap.cc index 3e8e59e6b..59e58e4db 100644 --- a/passes/techmap/maccmap.cc +++ b/passes/techmap/maccmap.cc @@ -36,7 +36,7 @@ struct MaccmapWorker void add(RTLIL::SigBit bit, int position) { - if (position >= width || bit == RTLIL::S0) + if (position >= width || bit == State::S0) return; if (bits.at(position).count(bit)) { @@ -53,7 +53,7 @@ struct MaccmapWorker if (do_subtract) { a = module->Not(NEW_ID, a); - add(RTLIL::S1, 0); + add(State::S1, 0); } for (int i = 0; i < width; i++) @@ -80,7 +80,7 @@ struct MaccmapWorker else { add(module->And(NEW_ID, a, RTLIL::SigSpec(b[i], width)), false, do_subtract); - a = {a.extract(0, width-1), RTLIL::S0}; + a = {a.extract(0, width-1), State::S0}; } } @@ -88,10 +88,10 @@ struct MaccmapWorker { int start_index = 0, stop_index = GetSize(in1); - while (start_index < stop_index && in1[start_index] == RTLIL::S0 && in2[start_index] == RTLIL::S0 && in3[start_index] == RTLIL::S0) + while (start_index < stop_index && in1[start_index] == State::S0 && in2[start_index] == RTLIL::S0 && in3[start_index] == RTLIL::S0) start_index++; - while (start_index < stop_index && in1[stop_index-1] == RTLIL::S0 && in2[stop_index-1] == RTLIL::S0 && in3[stop_index-1] == RTLIL::S0) + while (start_index < stop_index && in1[stop_index-1] == State::S0 && in2[stop_index-1] == RTLIL::S0 && in3[stop_index-1] == RTLIL::S0) stop_index--; if (start_index == stop_index) @@ -222,7 +222,7 @@ struct MaccmapWorker RTLIL::SigSpec in3 = summands[i+2]; RTLIL::SigSpec out1, out2; fulladd(in1, in2, in3, out1, out2); - RTLIL::SigBit extra_bit = RTLIL::S0; + RTLIL::SigBit extra_bit = State::S0; if (!tree_sum_bits.empty()) { extra_bit = tree_sum_bits.back(); tree_sum_bits.pop_back(); @@ -240,8 +240,8 @@ struct MaccmapWorker RTLIL::Cell *c = module->addCell(NEW_ID, "$alu"); c->setPort("\\A", summands.front()); c->setPort("\\B", summands.back()); - c->setPort("\\CI", RTLIL::S0); - c->setPort("\\BI", RTLIL::S0); + c->setPort("\\CI", State::S0); + c->setPort("\\BI", State::S0); c->setPort("\\Y", module->addWire(NEW_ID, width)); c->setPort("\\X", module->addWire(NEW_ID, width)); c->setPort("\\CO", module->addWire(NEW_ID, width)); diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index e360b5edb..cea247dc7 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -186,7 +186,7 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type, RTLIL::SigSpec config; for (int i = 0; i < (1 << width); i++) - config.append(xorshift32(2) ? RTLIL::S1 : RTLIL::S0); + config.append(xorshift32(2) ? State::S1 : State::S0); cell->setParam("\\LUT", config.as_const()); } @@ -209,16 +209,16 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type, for (int i = 0; i < width*depth; i++) switch (xorshift32(3)) { case 0: - config.append(RTLIL::S1); - config.append(RTLIL::S0); + config.append(State::S1); + config.append(State::S0); break; case 1: - config.append(RTLIL::S0); - config.append(RTLIL::S1); + config.append(State::S0); + config.append(State::S1); break; case 2: - config.append(RTLIL::S0); - config.append(RTLIL::S0); + config.append(State::S0); + config.append(State::S0); break; } @@ -308,18 +308,18 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type, case 0: n = xorshift32(GetSize(sig) + 1); for (int i = 0; i < n; i++) - sig[i] = xorshift32(2) == 1 ? RTLIL::S1 : RTLIL::S0; + sig[i] = xorshift32(2) == 1 ? State::S1 : State::S0; break; case 1: n = xorshift32(GetSize(sig) + 1); for (int i = n; i < GetSize(sig); i++) - sig[i] = xorshift32(2) == 1 ? RTLIL::S1 : RTLIL::S0; + sig[i] = xorshift32(2) == 1 ? State::S1 : State::S0; break; case 2: n = xorshift32(GetSize(sig)); m = xorshift32(GetSize(sig)); for (int i = min(n, m); i < max(n, m); i++) - sig[i] = xorshift32(2) == 1 ? RTLIL::S1 : RTLIL::S0; + sig[i] = xorshift32(2) == 1 ? State::S1 : State::S0; break; } @@ -491,7 +491,7 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std:: RTLIL::Const in_value; for (int i = 0; i < GetSize(gold_wire); i++) - in_value.bits.push_back(xorshift32(2) ? RTLIL::S1 : RTLIL::S0); + in_value.bits.push_back(xorshift32(2) ? State::S1 : State::S0); if (xorshift32(4) == 0) { int inv_chance = 1 + xorshift32(8); @@ -591,11 +591,11 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std:: } for (int i = 0; i < GetSize(out_sig); i++) { - if (out_val[i] != RTLIL::S0 && out_val[i] != RTLIL::S1) + if (out_val[i] != State::S0 && out_val[i] != State::S1) continue; - if (out_val[i] == RTLIL::S0 && sat1_model_value.at(i) == false) + if (out_val[i] == State::S0 && sat1_model_value.at(i) == false) continue; - if (out_val[i] == RTLIL::S1 && sat1_model_value.at(i) == true) + if (out_val[i] == State::S1 && sat1_model_value.at(i) == true) continue; log_error("Mismatch in sat model 1 (no undef modeling) output!\n"); } @@ -627,12 +627,12 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std:: for (int i = 0; i < GetSize(out_sig); i++) { if (sat2_model_value.at(GetSize(out_sig) + i)) { - if (out_val[i] != RTLIL::S0 && out_val[i] != RTLIL::S1) + if (out_val[i] != State::S0 && out_val[i] != State::S1) continue; } else { - if (out_val[i] == RTLIL::S0 && sat2_model_value.at(i) == false) + if (out_val[i] == State::S0 && sat2_model_value.at(i) == false) continue; - if (out_val[i] == RTLIL::S1 && sat2_model_value.at(i) == true) + if (out_val[i] == State::S1 && sat2_model_value.at(i) == true) continue; } log_error("Mismatch in sat model 2 (undef modeling) output!\n"); -- cgit v1.2.3 From 6d77236f3845cd8785e7bdd4da3c5ef966be6043 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 7 Aug 2019 12:20:08 -0700 Subject: substr() -> compare() --- passes/cmds/cover.cc | 2 +- passes/cmds/select.cc | 50 ++++++++++++++++++++++---------------------- passes/cmds/setattr.cc | 2 +- passes/cmds/show.cc | 6 +++--- passes/equiv/equiv_opt.cc | 2 +- passes/equiv/equiv_struct.cc | 4 ++-- passes/opt/opt_clean.cc | 6 +++--- passes/opt/opt_merge.cc | 2 +- passes/opt/opt_rmdff.cc | 4 ++-- passes/sat/expose.cc | 2 +- passes/sat/miter.cc | 4 ++-- passes/sat/sat.cc | 6 +++--- passes/techmap/abc.cc | 10 ++++----- passes/techmap/dff2dffe.cc | 6 +++--- passes/techmap/extract.cc | 10 ++++----- passes/techmap/muxcover.cc | 10 ++++----- passes/techmap/techmap.cc | 20 +++++++++--------- passes/tests/test_cell.cc | 2 +- 18 files changed, 74 insertions(+), 74 deletions(-) (limited to 'passes') diff --git a/passes/cmds/cover.cc b/passes/cmds/cover.cc index 1128116b4..628ac4c5e 100644 --- a/passes/cmds/cover.cc +++ b/passes/cmds/cover.cc @@ -121,7 +121,7 @@ struct CoverPass : public Pass { } break; } - while (argidx < args.size() && args[argidx].substr(0, 1) != "-") + while (argidx < args.size() && args[argidx].compare(0, 1, "-") != 0) patterns.push_back(args[argidx++]); extra_args(args, argidx, design); diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index b5e8ef1af..59d10a1b8 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -34,7 +34,7 @@ static bool match_ids(RTLIL::IdString id, std::string pattern) { if (id == pattern) return true; - if (id.size() > 0 && id[0] == '\\' && id.substr(1) == pattern) + if (id.size() > 0 && id[0] == '\\' && id.compare(1, std::string::npos, pattern.c_str()) == 0) return true; if (patmatch(pattern.c_str(), id.c_str())) return true; @@ -124,11 +124,11 @@ static bool match_attr(const dict &attributes, st size_t pos = match_expr.find_first_of(""); if (pos != std::string::npos) { - if (match_expr.substr(pos, 2) == "!=") + if (match_expr.compare(pos, 2, "!=") == 0) return match_attr(attributes, match_expr.substr(0, pos), match_expr.substr(pos+2), '!'); - if (match_expr.substr(pos, 2) == "<=") + if (match_expr.compare(pos, 2, "<=") == 0) return match_attr(attributes, match_expr.substr(0, pos), match_expr.substr(pos+2), '['); - if (match_expr.substr(pos, 2) == ">=") + if (match_expr.compare(pos, 2, ">=") == 0) return match_attr(attributes, match_expr.substr(0, pos), match_expr.substr(pos+2), ']'); return match_attr(attributes, match_expr.substr(0, pos), match_expr.substr(pos+1), match_expr[pos]); } @@ -711,32 +711,32 @@ static void select_stmt(RTLIL::Design *design, std::string arg) log_cmd_error("Must have at least one element on the stack for operator %%a.\n"); select_op_alias(design, work_stack[work_stack.size()-1]); } else - if (arg == "%x" || (arg.size() > 2 && arg.substr(0, 2) == "%x" && (arg[2] == ':' || arg[2] == '*' || arg[2] == '.' || ('0' <= arg[2] && arg[2] <= '9')))) { + if (arg == "%x" || (arg.size() > 2 && arg.compare(0, 2, "%x") == 0 && (arg[2] == ':' || arg[2] == '*' || arg[2] == '.' || ('0' <= arg[2] && arg[2] <= '9')))) { if (work_stack.size() < 1) log_cmd_error("Must have at least one element on the stack for operator %%x.\n"); select_op_expand(design, arg, 'x', false); } else - if (arg == "%ci" || (arg.size() > 3 && arg.substr(0, 3) == "%ci" && (arg[3] == ':' || arg[3] == '*' || arg[3] == '.' || ('0' <= arg[3] && arg[3] <= '9')))) { + if (arg == "%ci" || (arg.size() > 3 && arg.compare(0, 3, "%ci") == 0 && (arg[3] == ':' || arg[3] == '*' || arg[3] == '.' || ('0' <= arg[3] && arg[3] <= '9')))) { if (work_stack.size() < 1) log_cmd_error("Must have at least one element on the stack for operator %%ci.\n"); select_op_expand(design, arg, 'i', false); } else - if (arg == "%co" || (arg.size() > 3 && arg.substr(0, 3) == "%co" && (arg[3] == ':' || arg[3] == '*' || arg[3] == '.' || ('0' <= arg[3] && arg[3] <= '9')))) { + if (arg == "%co" || (arg.size() > 3 && arg.compare(0, 3, "%co") == 0 && (arg[3] == ':' || arg[3] == '*' || arg[3] == '.' || ('0' <= arg[3] && arg[3] <= '9')))) { if (work_stack.size() < 1) log_cmd_error("Must have at least one element on the stack for operator %%co.\n"); select_op_expand(design, arg, 'o', false); } else - if (arg == "%xe" || (arg.size() > 3 && arg.substr(0, 3) == "%xe" && (arg[3] == ':' || arg[3] == '*' || arg[3] == '.' || ('0' <= arg[3] && arg[3] <= '9')))) { + if (arg == "%xe" || (arg.size() > 3 && arg.compare(0, 3, "%xe") == 0 && (arg[3] == ':' || arg[3] == '*' || arg[3] == '.' || ('0' <= arg[3] && arg[3] <= '9')))) { if (work_stack.size() < 1) log_cmd_error("Must have at least one element on the stack for operator %%xe.\n"); select_op_expand(design, arg, 'x', true); } else - if (arg == "%cie" || (arg.size() > 4 && arg.substr(0, 4) == "%cie" && (arg[4] == ':' || arg[4] == '*' || arg[4] == '.' || ('0' <= arg[4] && arg[4] <= '9')))) { + if (arg == "%cie" || (arg.size() > 4 && arg.compare(0, 4, "%cie") == 0 && (arg[4] == ':' || arg[4] == '*' || arg[4] == '.' || ('0' <= arg[4] && arg[4] <= '9')))) { if (work_stack.size() < 1) log_cmd_error("Must have at least one element on the stack for operator %%cie.\n"); select_op_expand(design, arg, 'i', true); } else - if (arg == "%coe" || (arg.size() > 4 && arg.substr(0, 4) == "%coe" && (arg[4] == ':' || arg[4] == '*' || arg[4] == '.' || ('0' <= arg[4] && arg[4] <= '9')))) { + if (arg == "%coe" || (arg.size() > 4 && arg.compare(0, 4, "%coe") == 0 && (arg[4] == ':' || arg[4] == '*' || arg[4] == '.' || ('0' <= arg[4] && arg[4] <= '9')))) { if (work_stack.size() < 1) log_cmd_error("Must have at least one element on the stack for operator %%coe.\n"); select_op_expand(design, arg, 'o', true); @@ -766,7 +766,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg) } else { size_t pos = arg.find('/'); if (pos == std::string::npos) { - if (arg.find(':') == std::string::npos || arg.substr(0, 1) == "A") + if (arg.find(':') == std::string::npos || arg.compare(0, 1, "A") == 0) arg_mod = arg; else arg_mod = "*", arg_memb = arg; @@ -787,7 +787,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg) sel.full_selection = false; for (auto &mod_it : design->modules_) { - if (arg_mod.substr(0, 2) == "A:") { + if (arg_mod.compare(0, 2, "A:") == 0) { if (!match_attr(mod_it.second->attributes, arg_mod.substr(2))) continue; } else @@ -800,27 +800,27 @@ static void select_stmt(RTLIL::Design *design, std::string arg) } RTLIL::Module *mod = mod_it.second; - if (arg_memb.substr(0, 2) == "w:") { + if (arg_memb.compare(0, 2, "w:") == 0) { for (auto &it : mod->wires_) if (match_ids(it.first, arg_memb.substr(2))) sel.selected_members[mod->name].insert(it.first); } else - if (arg_memb.substr(0, 2) == "i:") { + if (arg_memb.compare(0, 2, "i:") == 0) { for (auto &it : mod->wires_) if (it.second->port_input && match_ids(it.first, arg_memb.substr(2))) sel.selected_members[mod->name].insert(it.first); } else - if (arg_memb.substr(0, 2) == "o:") { + if (arg_memb.compare(0, 2, "o:") == 0) { for (auto &it : mod->wires_) if (it.second->port_output && match_ids(it.first, arg_memb.substr(2))) sel.selected_members[mod->name].insert(it.first); } else - if (arg_memb.substr(0, 2) == "x:") { + if (arg_memb.compare(0, 2, "x:") == 0) { for (auto &it : mod->wires_) if ((it.second->port_input || it.second->port_output) && match_ids(it.first, arg_memb.substr(2))) sel.selected_members[mod->name].insert(it.first); } else - if (arg_memb.substr(0, 2) == "s:") { + if (arg_memb.compare(0, 2, "s:") == 0) { size_t delim = arg_memb.substr(2).find(':'); if (delim == std::string::npos) { int width = atoi(arg_memb.substr(2).c_str()); @@ -837,27 +837,27 @@ static void select_stmt(RTLIL::Design *design, std::string arg) sel.selected_members[mod->name].insert(it.first); } } else - if (arg_memb.substr(0, 2) == "m:") { + if (arg_memb.compare(0, 2, "m:") == 0) { for (auto &it : mod->memories) if (match_ids(it.first, arg_memb.substr(2))) sel.selected_members[mod->name].insert(it.first); } else - if (arg_memb.substr(0, 2) == "c:") { + if (arg_memb.compare(0, 2, "c:") ==0) { for (auto &it : mod->cells_) if (match_ids(it.first, arg_memb.substr(2))) sel.selected_members[mod->name].insert(it.first); } else - if (arg_memb.substr(0, 2) == "t:") { + if (arg_memb.compare(0, 2, "t:") == 0) { for (auto &it : mod->cells_) if (match_ids(it.second->type, arg_memb.substr(2))) sel.selected_members[mod->name].insert(it.first); } else - if (arg_memb.substr(0, 2) == "p:") { + if (arg_memb.compare(0, 2, "p:") == 0) { for (auto &it : mod->processes) if (match_ids(it.first, arg_memb.substr(2))) sel.selected_members[mod->name].insert(it.first); } else - if (arg_memb.substr(0, 2) == "a:") { + if (arg_memb.compare(0, 2, "a:") == 0) { for (auto &it : mod->wires_) if (match_attr(it.second->attributes, arg_memb.substr(2))) sel.selected_members[mod->name].insert(it.first); @@ -871,12 +871,12 @@ static void select_stmt(RTLIL::Design *design, std::string arg) if (match_attr(it.second->attributes, arg_memb.substr(2))) sel.selected_members[mod->name].insert(it.first); } else - if (arg_memb.substr(0, 2) == "r:") { + if (arg_memb.compare(0, 2, "r:") == 0) { for (auto &it : mod->cells_) if (match_attr(it.second->parameters, arg_memb.substr(2))) sel.selected_members[mod->name].insert(it.first); } else { - if (arg_memb.substr(0, 2) == "n:") + if (arg_memb.compare(0, 2, "n:") == 0) arg_memb = arg_memb.substr(2); for (auto &it : mod->wires_) if (match_ids(it.first, arg_memb)) @@ -927,7 +927,7 @@ void handle_extra_select_args(Pass *pass, vector args, size_t argidx, si { work_stack.clear(); for (; argidx < args_size; argidx++) { - if (args[argidx].substr(0, 1) == "-") { + if (args[argidx].compare(0, 1, "-") == 0) { if (pass != NULL) pass->cmd_error(args, argidx, "Unexpected option in selection arguments."); else diff --git a/passes/cmds/setattr.cc b/passes/cmds/setattr.cc index b9fcc3e7a..1ccfc2e86 100644 --- a/passes/cmds/setattr.cc +++ b/passes/cmds/setattr.cc @@ -34,7 +34,7 @@ struct setunset_t setunset_t(std::string set_name, std::string set_value) : name(RTLIL::escape_id(set_name)), value(), unset(false) { - if (set_value.substr(0, 1) == "\"" && set_value.substr(GetSize(set_value)-1) == "\"") { + if (set_value.compare(0, 1, "\"") == 0 && set_value.compare(GetSize(set_value)-1, std::string::npos, "\"") == 0) { value = RTLIL::Const(set_value.substr(1, GetSize(set_value)-2)); } else { RTLIL::SigSpec sig_value; diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index cf729215f..2e9fc72af 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -527,11 +527,11 @@ struct ShowWorker { currentColor = xorshift32(currentColor); if (wires_on_demand.count(it.first) > 0) { - if (it.second.in.size() == 1 && it.second.out.size() > 1 && it.second.in.begin()->substr(0, 1) == "p") + if (it.second.in.size() == 1 && it.second.out.size() > 1 && it.second.in.begin()->compare(0, 1, "p") == 0) it.second.out.erase(*it.second.in.begin()); if (it.second.in.size() == 1 && it.second.out.size() == 1) { std::string from = *it.second.in.begin(), to = *it.second.out.begin(); - if (from != to || from.substr(0, 1) != "p") + if (from != to || from.compare(0, 1, "p") != 0) fprintf(f, "%s:e -> %s:w [%s, %s];\n", from.c_str(), to.c_str(), nextColor(it.second.color).c_str(), widthLabel(it.second.bits).c_str()); continue; } @@ -808,7 +808,7 @@ struct ShowPass : public Pass { if (f.fail()) log_error("Can't open lib file `%s'.\n", filename.c_str()); RTLIL::Design *lib = new RTLIL::Design; - Frontend::frontend_call(lib, &f, filename, (filename.size() > 3 && filename.substr(filename.size()-3) == ".il") ? "ilang" : "verilog"); + Frontend::frontend_call(lib, &f, filename, (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".il") == 0 ? "ilang" : "verilog")); libs.push_back(lib); } diff --git a/passes/equiv/equiv_opt.cc b/passes/equiv/equiv_opt.cc index 3596dfd7b..19d1c25ac 100644 --- a/passes/equiv/equiv_opt.cc +++ b/passes/equiv/equiv_opt.cc @@ -97,7 +97,7 @@ struct EquivOptPass:public ScriptPass for (; argidx < args.size(); argidx++) { if (command.empty()) { - if (args[argidx].substr(0, 1) == "-") + if (args[argidx].compare(0, 1, "-") == 0) cmd_error(args, argidx, "Unknown option."); } else { command += " "; diff --git a/passes/equiv/equiv_struct.cc b/passes/equiv/equiv_struct.cc index a7973fd04..6672948b9 100644 --- a/passes/equiv/equiv_struct.cc +++ b/passes/equiv/equiv_struct.cc @@ -215,9 +215,9 @@ struct EquivStructWorker if (c != nullptr) { string n = cell_name.str(); cells_type = c->type; - if (GetSize(n) > 5 && n.substr(GetSize(n)-5) == "_gold") + if (GetSize(n) > 5 && n.compare(GetSize(n)-5, std::string::npos, "_gold") == 0) gold_cells.push_back(c); - else if (GetSize(n) > 5 && n.substr(GetSize(n)-5) == "_gate") + else if (GetSize(n) > 5 && n.compare(GetSize(n)-5, std::string::npos, "_gate") == 0) gate_cells.push_back(c); else other_cells.push_back(c); diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index a8a8e0bc7..905c95b6c 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -222,10 +222,10 @@ bool compare_signals(RTLIL::SigBit &s1, RTLIL::SigBit &s2, SigPool ®s, SigPoo bool check_public_name(RTLIL::IdString id) { - const std::string &id_str = id.str(); - if (id_str[0] == '$') + if (id.begins_with("$")) return false; - if (id_str.substr(0, 2) == "\\_" && (id_str[id_str.size()-1] == '_' || id_str.find("_[") != std::string::npos)) + const std::string &id_str = id.str(); + if (id.begins_with("\\_") && (id.ends_with("_") || id_str.find("_[") != std::string::npos)) return false; if (id_str.find(".$") != std::string::npos) return false; diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc index 8964171e6..cac7c0a6f 100644 --- a/passes/opt/opt_merge.cc +++ b/passes/opt/opt_merge.cc @@ -222,7 +222,7 @@ struct OptMergeWorker return true; } - if (cell1->type.substr(0, 1) == "$" && conn1.count("\\Q") != 0) { + if (cell1->type.begins_with("$") && conn1.count("\\Q") != 0) { std::vector q1 = dff_init_map(cell1->getPort("\\Q")).to_sigbit_vector(); std::vector q2 = dff_init_map(cell2->getPort("\\Q")).to_sigbit_vector(); for (size_t i = 0; i < q1.size(); i++) diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc index 450626f4a..8d42a37c3 100644 --- a/passes/opt/opt_rmdff.cc +++ b/passes/opt/opt_rmdff.cc @@ -278,7 +278,7 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) sig_c = dff->getPort("\\C"); val_cp = RTLIL::Const(dff->type == "$_DFF_P_", 1); } - else if (dff->type.begins_with("$_DFF_") && dff->type.substr(9) == "_" && + else if (dff->type.begins_with("$_DFF_") && dff->type.compare(9, 1, "_") == 0 && (dff->type[6] == 'N' || dff->type[6] == 'P') && (dff->type[7] == 'N' || dff->type[7] == 'P') && (dff->type[8] == '0' || dff->type[8] == '1')) { @@ -290,7 +290,7 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) val_rp = RTLIL::Const(dff->type[7] == 'P', 1); val_rv = RTLIL::Const(dff->type[8] == '1', 1); } - else if (dff->type.begins_with("$_DFFE_") && dff->type.substr(9) == "_" && + else if (dff->type.begins_with("$_DFFE_") && dff->type.compare(9, 1, "_") == 0 && (dff->type[7] == 'N' || dff->type[7] == 'P') && (dff->type[8] == 'N' || dff->type[8] == 'P')) { sig_d = dff->getPort("\\D"); diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc index 71ce1683d..7631d87e6 100644 --- a/passes/sat/expose.cc +++ b/passes/sat/expose.cc @@ -151,7 +151,7 @@ void create_dff_dq_map(std::map &map, RTLIL::De continue; } - if (info.cell->type.size() == 10 && info.cell->type.substr(0, 6) == "$_DFF_") { + if (info.cell->type.size() == 10 && info.cell->type.begins_with("$_DFF_")) { info.bit_clk = sigmap(info.cell->getPort("\\C")).as_bit(); info.bit_arst = sigmap(info.cell->getPort("\\R")).as_bit(); info.clk_polarity = info.cell->type[6] == 'P'; diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index e1da1a9e6..49ef40061 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -59,7 +59,7 @@ void create_miter_equiv(struct Pass *that, std::vector args, RTLIL: } break; } - if (argidx+3 != args.size() || args[argidx].substr(0, 1) == "-") + if (argidx+3 != args.size() || args[argidx].compare(0, 1, "-") == 0) that->cmd_error(args, argidx, "command argument error"); RTLIL::IdString gold_name = RTLIL::escape_id(args[argidx++]); @@ -279,7 +279,7 @@ void create_miter_assert(struct Pass *that, std::vector args, RTLIL } break; } - if ((argidx+1 != args.size() && argidx+2 != args.size()) || args[argidx].substr(0, 1) == "-") + if ((argidx+1 != args.size() && argidx+2 != args.size()) || args[argidx].compare(0, 1, "-") == 0) that->cmd_error(args, argidx, "command argument error"); IdString module_name = RTLIL::escape_id(args[argidx++]); diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index e4654d835..dd56d8c71 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -519,7 +519,7 @@ struct SatHelper for (auto &p : d->connections()) { if (d->type == "$dff" && p.first == "\\CLK") continue; - if (d->type.substr(0, 6) == "$_DFF_" && p.first == "\\C") + if (d->type.begins_with("$_DFF_") && p.first == "\\C") continue; queued_signals.add(handled_signals.remove(sigmap(p.second))); } @@ -797,7 +797,7 @@ struct SatHelper vector data; string name = wd.first.c_str(); - while (name.substr(0, 1) == "\\") + while (name.compare(0, 1, "\\") == 0) name = name.substr(1); fprintf(f, " { \"name\": \"%s\", \"wave\": \"", name.c_str()); @@ -1353,7 +1353,7 @@ struct SatPass : public Pass { if (show_regs) { pool reg_wires; for (auto cell : module->cells()) { - if (cell->type == "$dff" || cell->type.substr(0, 6) == "$_DFF_") + if (cell->type == "$dff" || cell->type.begins_with("$_DFF_")) for (auto bit : cell->getPort("\\Q")) if (bit.wire) reg_wires.insert(bit.wire); diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index 7cb784505..9db8aafa7 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -333,12 +333,12 @@ std::string remap_name(RTLIL::IdString abc_name, RTLIL::Wire **orig_wire = nullp { std::string abc_sname = abc_name.substr(1); bool isnew = false; - if (abc_sname.substr(0, 4) == "new_") + if (abc_sname.compare(0, 4, "new_") == 0) { abc_sname.erase(0, 4); isnew = true; } - if (abc_sname.substr(0, 5) == "ys__n") + if (abc_sname.compare(0, 5, "ys__n") == 0) { abc_sname.erase(0, 5); if (std::isdigit(abc_sname.at(0))) @@ -1562,10 +1562,10 @@ struct AbcPass : public Pass { size_t pos = arg.find_first_of(':'); int lut_mode = 0, lut_mode2 = 0; if (pos != string::npos) { - lut_mode = std::atoi(arg.substr(0, pos).c_str()); - lut_mode2 = std::atoi(arg.substr(pos+1).c_str()); + lut_mode = atoi(arg.substr(0, pos).c_str()); + lut_mode2 = atoi(arg.substr(pos+1).c_str()); } else { - lut_mode = std::atoi(arg.c_str()); + lut_mode = atoi(arg.c_str()); lut_mode2 = lut_mode; } lut_costs.clear(); diff --git a/passes/techmap/dff2dffe.cc b/passes/techmap/dff2dffe.cc index 2dc577c73..c0bf3a665 100644 --- a/passes/techmap/dff2dffe.cc +++ b/passes/techmap/dff2dffe.cc @@ -377,7 +377,7 @@ struct Dff2dffePass : public Pass { mod->remove(cell); continue; } - if (cell->type.substr(0, 7) == "$_DFFE_") { + if (cell->type.begins_with("$_DFFE_")) { if (min_ce_use >= 0) { int ce_use = 0; for (auto cell_other : mod->selected_cells()) { @@ -390,8 +390,8 @@ struct Dff2dffePass : public Pass { continue; } - bool clk_pol = cell->type.substr(7, 1) == "P"; - bool en_pol = cell->type.substr(8, 1) == "P"; + bool clk_pol = cell->type.compare(7, 1, "P") == 0; + bool en_pol = cell->type.compare(8, 1, "P") == 0; RTLIL::SigSpec tmp = mod->addWire(NEW_ID); mod->addDff(NEW_ID, cell->getPort("\\C"), tmp, cell->getPort("\\Q"), clk_pol); if (en_pol) diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index fff90f13c..e3b4faba1 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -54,7 +54,7 @@ public: RTLIL::Const unified_param(RTLIL::IdString cell_type, RTLIL::IdString param, RTLIL::Const value) { - if (cell_type.substr(0, 1) != "$" || cell_type.substr(0, 2) == "$_") + if (!cell_type.begins_with("$") || cell_type.begins_with("$_")) return value; #define param_bool(_n) if (param == _n) return value.as_bool(); @@ -203,7 +203,7 @@ bool module2graph(SubCircuit::Graph &graph, RTLIL::Module *mod, bool constports, continue; std::string type = cell->type.str(); - if (sel == NULL && type.substr(0, 2) == "\\$") + if (sel == NULL && type.compare(0, 2, "\\$") == 0) type = type.substr(1); graph.createNode(cell->name.str(), type, (void*)cell); @@ -594,7 +594,7 @@ struct ExtractPass : public Pass { map = new RTLIL::Design; for (auto &filename : map_filenames) { - if (filename.substr(0, 1) == "%") + if (filename.compare(0, 1, "%") == 0) { if (!saved_designs.count(filename.substr(1))) { delete map; @@ -613,10 +613,10 @@ struct ExtractPass : public Pass { delete map; log_cmd_error("Can't open map file `%s'.\n", filename.c_str()); } - Frontend::frontend_call(map, &f, filename, (filename.size() > 3 && filename.substr(filename.size()-3) == ".il") ? "ilang" : "verilog"); + Frontend::frontend_call(map, &f, filename, (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".il") == 0 ? "ilang" : "verilog")); f.close(); - if (filename.size() <= 3 || filename.substr(filename.size()-3) != ".il") { + if (filename.size() <= 3 || filename.compare(filename.size()-3, std::string::npos, ".il") != 0) { Pass::call(map, "proc"); Pass::call(map, "opt_clean"); } diff --git a/passes/techmap/muxcover.cc b/passes/techmap/muxcover.cc index 45987392e..81546249c 100644 --- a/passes/techmap/muxcover.cc +++ b/passes/techmap/muxcover.cc @@ -675,11 +675,11 @@ struct MuxcoverPass : public Pass { for (argidx = 1; argidx < args.size(); argidx++) { const auto &arg = args[argidx]; - if (arg.size() >= 6 && arg.substr(0,6) == "-mux2=") { + if (arg.size() >= 6 && arg.compare(0,6,"-mux2=") == 0) { cost_mux2 = atoi(arg.substr(6).c_str()); continue; } - if (arg.size() >= 5 && arg.substr(0,5) == "-mux4") { + if (arg.size() >= 5 && arg.compare(0,5,"-mux4") == 0) { use_mux4 = true; if (arg.size() > 5) { if (arg[5] != '=') break; @@ -687,7 +687,7 @@ struct MuxcoverPass : public Pass { } continue; } - if (arg.size() >= 5 && arg.substr(0,5) == "-mux8") { + if (arg.size() >= 5 && arg.compare(0,5,"-mux8") == 0) { use_mux8 = true; if (arg.size() > 5) { if (arg[5] != '=') break; @@ -695,7 +695,7 @@ struct MuxcoverPass : public Pass { } continue; } - if (arg.size() >= 6 && arg.substr(0,6) == "-mux16") { + if (arg.size() >= 6 && arg.compare(0,6,"-mux16") == 0) { use_mux16 = true; if (arg.size() > 6) { if (arg[6] != '=') break; @@ -703,7 +703,7 @@ struct MuxcoverPass : public Pass { } continue; } - if (arg.size() >= 6 && arg.substr(0,6) == "-dmux=") { + if (arg.size() >= 6 && arg.compare(0,6,"-dmux=") == 0) { cost_dmux = atoi(arg.substr(6).c_str()); continue; } diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index ceb053825..2708b08ae 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -243,7 +243,7 @@ struct TechmapWorker if (positional_ports.count(portname) > 0) portname = positional_ports.at(portname); if (tpl->wires_.count(portname) == 0 || tpl->wires_.at(portname)->port_id == 0) { - if (portname.substr(0, 1) == "$") + if (portname.begins_with("$")) log_error("Can't map port `%s' of cell `%s' to template `%s'!\n", portname.c_str(), cell->name.c_str(), tpl->name.c_str()); continue; } @@ -341,7 +341,7 @@ struct TechmapWorker RTLIL::Cell *c = module->addCell(c_name, it.second); design->select(module, c); - if (!flatten_mode && c->type.substr(0, 2) == "\\$") + if (!flatten_mode && c->type.begins_with("\\$")) c->type = c->type.substr(1); for (auto &it2 : c->connections_) { @@ -406,7 +406,7 @@ struct TechmapWorker continue; std::string cell_type = cell->type.str(); - if (in_recursion && cell_type.substr(0, 2) == "\\$") + if (in_recursion && cell->type.begins_with("\\$")) cell_type = cell_type.substr(1); if (celltypeMap.count(cell_type) == 0) { @@ -468,7 +468,7 @@ struct TechmapWorker std::string cell_type = cell->type.str(); - if (in_recursion && cell_type.substr(0, 2) == "\\$") + if (in_recursion && cell->type.begins_with("\\$")) cell_type = cell_type.substr(1); for (auto &tpl_name : celltypeMap.at(cell_type)) @@ -602,7 +602,7 @@ struct TechmapWorker } for (auto conn : cell->connections()) { - if (conn.first.substr(0, 1) == "$") + if (conn.first.begins_with("$")) continue; if (tpl->wires_.count(conn.first) > 0 && tpl->wires_.at(conn.first)->port_id > 0) continue; @@ -725,7 +725,7 @@ struct TechmapWorker for (auto &it : twd) { - if (it.first.substr(0, 12) != "_TECHMAP_DO_" || it.second.empty()) + if (it.first.compare(0, 12, "_TECHMAP_DO_") != 0 || it.second.empty()) continue; auto &data = it.second.front(); @@ -874,7 +874,7 @@ struct TechmapWorker tpl->cloneInto(m); for (auto cell : m->cells()) { - if (cell->type.substr(0, 2) == "\\$") + if (cell->type.begins_with("\\$")) cell->type = cell->type.substr(1); } @@ -1113,7 +1113,7 @@ struct TechmapPass : public Pass { Frontend::frontend_call(map, &f, "", verilog_frontend); } else { for (auto &fn : map_files) - if (fn.substr(0, 1) == "%") { + if (fn.compare(0, 1, "%") == 0) { if (!saved_designs.count(fn.substr(1))) { delete map; log_cmd_error("Can't saved design `%s'.\n", fn.c_str()+1); @@ -1128,7 +1128,7 @@ struct TechmapPass : public Pass { yosys_input_files.insert(fn); if (f.fail()) log_cmd_error("Can't open map file `%s'\n", fn.c_str()); - Frontend::frontend_call(map, &f, fn, (fn.size() > 3 && fn.substr(fn.size()-3) == ".il") ? "ilang" : verilog_frontend); + Frontend::frontend_call(map, &f, fn, (fn.size() > 3 && fn.compare(fn.size()-3, std::string::npos, ".il") == 0 ? "ilang" : verilog_frontend)); } } @@ -1143,7 +1143,7 @@ struct TechmapPass : public Pass { free(p); } else { string module_name = it.first.str(); - if (module_name.substr(0, 2) == "\\$") + if (it.first.begins_with("\\$")) module_name = module_name.substr(1); celltypeMap[module_name].insert(it.first); } diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index cea247dc7..319669955 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -872,7 +872,7 @@ struct TestCellPass : public Pass { continue; } - if (args[argidx].substr(0, 1) == "/") { + if (args[argidx].compare(0, 1, "/") == 0) { std::vector new_selected_cell_types; for (auto it : selected_cell_types) if (it != args[argidx].substr(1)) -- cgit v1.2.3