From ab71bd0746c39402aefaea85322fe36bdbaabb09 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 12 Feb 2014 08:35:42 +0100 Subject: Updated ABC to rev e97a6e1d59b9 --- passes/abc/abc.cc | 53 +++++++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 49 insertions(+), 4 deletions(-) (limited to 'passes') diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index 5aa13572e..e6b7a72d8 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -29,10 +29,10 @@ // Kahn, Arthur B. (1962), "Topological sorting of large networks", Communications of the ACM 5 (11): 558–562, doi:10.1145/368996.369025 // http://en.wikipedia.org/wiki/Topological_sorting -#define ABC_COMMAND_LIB "strash; retime; balance; dch; map; topo" -#define ABC_COMMAND_CTR "strash; retime; balance; dch; map; topo; buffer; upsize; dnsize; stime" -#define ABC_COMMAND_LUT "strash; retime; balance; dch; if" -#define ABC_COMMAND_DFL "strash; retime; balance; dch; map" +#define ABC_COMMAND_LIB "strash; ifraig -v; retime -v; balance -v; dch -vf; scorr -v; map -v;" +#define ABC_COMMAND_CTR "strash; ifraig -v; retime -v; balance -v; dch -vf; scorr -v; map -v; buffer -v; upsize -v; dnsize -v; stime -p" +#define ABC_COMMAND_LUT "strash; ifraig -v; retime -v; balance -v; dch -vf; scorr -v; if -v" +#define ABC_COMMAND_DFL "strash; ifraig -v; retime -v; balance -v; dch -vf; scorr -v; map -v" #include "kernel/register.h" #include "kernel/sigtools.h" @@ -359,6 +359,30 @@ static void handle_loops() fclose(dot_f); } +static std::string add_echos_to_abc_cmd(std::string str) +{ + std::string new_str, token; + for (size_t i = 0; i < str.size(); i++) { + token += str[i]; + if (str[i] == ';') { + while (i+1 < str.size() && str[i+1] == ' ') + i++; + if (!new_str.empty()) + new_str += "echo; "; + new_str += "echo + " + token + " " + token + " "; + token.clear(); + } + } + + if (!token.empty()) { + if (!new_str.empty()) + new_str += "echo; echo + " + token + "; "; + new_str += token; + } + + return new_str; +} + static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::string script_file, std::string exe_file, std::string liberty_file, std::string constr_file, bool cleanup, int lut_mode, bool dff_mode, std::string clk_str) { @@ -398,6 +422,17 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std abc_command = constr_file.empty() ? ABC_COMMAND_LIB : ABC_COMMAND_CTR; else abc_command = ABC_COMMAND_DFL; + abc_command = add_echos_to_abc_cmd(abc_command); + + if (abc_command.size() > 128) { + for (size_t i = 0; i+1 < abc_command.size(); i++) + if (abc_command[i] == ';' && abc_command[i+1] == ' ') + abc_command[i+1] = '\n'; + FILE *f = fopen(stringf("%s/abc.script", tempdir_name).c_str(), "wt"); + fprintf(f, "%s\n", abc_command.c_str()); + fclose(f); + abc_command = stringf("source %s/abc.script", tempdir_name); + } if (clk_str.empty()) { if (clk_str[0] == '!') { @@ -578,6 +613,8 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std exe_file.c_str(), tempdir_name, tempdir_name, abc_command.c_str()); buffer += stringf("write_blif %s/output.blif' 2>&1", tempdir_name); + log("%s\n", buffer.c_str()); + errno = ENOMEM; // popen does not set errno if memory allocation fails, therefore set it by hand f = popen(buffer.c_str(), "r"); if (f == NULL) @@ -838,6 +875,14 @@ struct AbcPass : public Pass { log(" -constr \n"); log(" pass this file with timing constraints to ABC. use with -liberty.\n"); log("\n"); + log(" a constr file contains two lines:\n"); + log(" set_driving_cell \n"); + log(" set_load \n"); + log("\n"); + log(" the set_driving_cell statement defines which cell type is assumed to\n"); + log(" drive the primary inputs and the set_load statement sets the number of\n"); + log(" flip-flops driven by each primary output.\n"); + log("\n"); log(" -lut \n"); log(" generate netlist using luts of (max) the specified width.\n"); log("\n"); -- cgit v1.2.3 From 7664f5d92b9fd78c7a858702544887d48c1d5aec Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 13 Feb 2014 08:07:08 +0100 Subject: Updated ABC and some related changes --- passes/abc/abc.cc | 41 +++++++++++++++++++++++++++++++---------- 1 file changed, 31 insertions(+), 10 deletions(-) (limited to 'passes') diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index e6b7a72d8..1115bdc7b 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -29,10 +29,10 @@ // Kahn, Arthur B. (1962), "Topological sorting of large networks", Communications of the ACM 5 (11): 558–562, doi:10.1145/368996.369025 // http://en.wikipedia.org/wiki/Topological_sorting -#define ABC_COMMAND_LIB "strash; ifraig -v; retime -v; balance -v; dch -vf; scorr -v; map -v;" -#define ABC_COMMAND_CTR "strash; ifraig -v; retime -v; balance -v; dch -vf; scorr -v; map -v; buffer -v; upsize -v; dnsize -v; stime -p" -#define ABC_COMMAND_LUT "strash; ifraig -v; retime -v; balance -v; dch -vf; scorr -v; if -v" -#define ABC_COMMAND_DFL "strash; ifraig -v; retime -v; balance -v; dch -vf; scorr -v; map -v" +#define ABC_COMMAND_LIB "strash; ifraig -v; retime -v; balance -v; scorr -v; dch -vf; map -v;" +#define ABC_COMMAND_CTR "strash; ifraig -v; retime -v; balance -v; scorr -v; dch -vf; map -v; buffer -v; upsize -v; dnsize -v; stime -p" +#define ABC_COMMAND_LUT "strash; ifraig -v; retime -v; balance -v; scorr -v; dch -vf; if -v" +#define ABC_COMMAND_DFL "strash; ifraig -v; retime -v; balance -v; scorr -v; dch -vf; map -v" #include "kernel/register.h" #include "kernel/sigtools.h" @@ -383,6 +383,25 @@ static std::string add_echos_to_abc_cmd(std::string str) return new_str; } +static std::string fold_abc_cmd(std::string str) +{ + std::string token, new_str = " "; + int char_counter = 10; + + for (size_t i = 0; i <= str.size(); i++) { + if (i < str.size()) + token += str[i]; + if (i == str.size() || str[i] == ';') { + if (char_counter + token.size() > 75) + new_str += "\n ", char_counter = 14; + new_str += token, char_counter += token.size(); + token.clear(); + } + } + + return new_str; +} + static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::string script_file, std::string exe_file, std::string liberty_file, std::string constr_file, bool cleanup, int lut_mode, bool dff_mode, std::string clk_str) { @@ -508,6 +527,8 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std fprintf(f, " n%d", si.id); count_input++; } + if (count_input == 0) + fprintf(f, " dummy_input\n"); fprintf(f, "\n"); int count_output = 0; @@ -857,16 +878,16 @@ struct AbcPass : public Pass { log(" if no -script parameter is given, the following scripts are used:\n"); log("\n"); log(" for -liberty without -constr:\n"); - log(" %s\n", ABC_COMMAND_LIB); + log("%s\n", fold_abc_cmd(ABC_COMMAND_LIB).c_str()); log("\n"); log(" for -liberty with -constr:\n"); - log(" %s\n", ABC_COMMAND_CTR); + log("%s\n", fold_abc_cmd(ABC_COMMAND_CTR).c_str()); log("\n"); log(" for -lut:\n"); - log(" %s\n", ABC_COMMAND_LUT); + log("%s\n", fold_abc_cmd(ABC_COMMAND_LUT).c_str()); log("\n"); log(" otherwise:\n"); - log(" %s\n", ABC_COMMAND_DFL); + log("%s\n", fold_abc_cmd(ABC_COMMAND_DFL).c_str()); log("\n"); log(" -liberty \n"); log(" generate netlists for the specified cell library (using the liberty\n"); @@ -880,8 +901,8 @@ struct AbcPass : public Pass { log(" set_load \n"); log("\n"); log(" the set_driving_cell statement defines which cell type is assumed to\n"); - log(" drive the primary inputs and the set_load statement sets the number of\n"); - log(" flip-flops driven by each primary output.\n"); + log(" drive the primary inputs and the set_load statement sets the load in\n"); + log(" femtofarads for each primary output.\n"); log("\n"); log(" -lut \n"); log(" generate netlist using luts of (max) the specified width.\n"); -- cgit v1.2.3 From b4639078903847469c2cfe211b3e5d7006a78cc8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 13 Feb 2014 08:12:52 +0100 Subject: Removed double blanks in ABC default command sequences --- passes/abc/abc.cc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'passes') diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index 1115bdc7b..dae3a22fc 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -29,10 +29,10 @@ // Kahn, Arthur B. (1962), "Topological sorting of large networks", Communications of the ACM 5 (11): 558–562, doi:10.1145/368996.369025 // http://en.wikipedia.org/wiki/Topological_sorting -#define ABC_COMMAND_LIB "strash; ifraig -v; retime -v; balance -v; scorr -v; dch -vf; map -v;" -#define ABC_COMMAND_CTR "strash; ifraig -v; retime -v; balance -v; scorr -v; dch -vf; map -v; buffer -v; upsize -v; dnsize -v; stime -p" -#define ABC_COMMAND_LUT "strash; ifraig -v; retime -v; balance -v; scorr -v; dch -vf; if -v" -#define ABC_COMMAND_DFL "strash; ifraig -v; retime -v; balance -v; scorr -v; dch -vf; map -v" +#define ABC_COMMAND_LIB "strash; ifraig -v; retime -v; balance -v; scorr -v; dch -vf; map -v;" +#define ABC_COMMAND_CTR "strash; ifraig -v; retime -v; balance -v; scorr -v; dch -vf; map -v; buffer -v; upsize -v; dnsize -v; stime -p" +#define ABC_COMMAND_LUT "strash; ifraig -v; retime -v; balance -v; scorr -v; dch -vf; if -v" +#define ABC_COMMAND_DFL "strash; ifraig -v; retime -v; balance -v; scorr -v; dch -vf; map -v" #include "kernel/register.h" #include "kernel/sigtools.h" -- cgit v1.2.3 From cd9e8741a71502c303c6f25d02bb2259a7dd7ff3 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 13 Feb 2014 13:59:13 +0100 Subject: Implemented read_verilog -defer --- passes/hierarchy/hierarchy.cc | 26 +++++++++++++++++++------- 1 file changed, 19 insertions(+), 7 deletions(-) (limited to 'passes') diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 50d0e6e47..526d17294 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -145,6 +145,14 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla if (design->modules.count(cell->type) == 0) { + if (design->modules.count("$abstract" + cell->type)) + { + cell->type = design->modules.at("$abstract" + cell->type)->derive(design, cell->parameters); + cell->parameters.clear(); + did_something = true; + continue; + } + if (cell->type[0] == '$') continue; @@ -210,7 +218,7 @@ static void hierarchy_worker(RTLIL::Design *design, std::set &us } } -static void hierarchy(RTLIL::Design *design, RTLIL::Module *top, bool purge_lib) +static void hierarchy(RTLIL::Design *design, RTLIL::Module *top, bool purge_lib, bool first_pass) { std::set used; hierarchy_worker(design, used, top, 0); @@ -221,6 +229,8 @@ static void hierarchy(RTLIL::Design *design, RTLIL::Module *top, bool purge_lib) del_modules.push_back(it.second); for (auto mod : del_modules) { + if (first_pass && mod->name.substr(0, 9) == "$abstract") + continue; if (!purge_lib && mod->get_bool_attribute("\\blackbox")) continue; log("Removing unused module `%s'.\n", mod->name.c_str()); @@ -362,10 +372,12 @@ struct HierarchyPass : public Pass { if (args[argidx] == "-top") { if (++argidx >= args.size()) log_cmd_error("Option -top requires an additional argument!\n"); - if (args[argidx][0] != '$' && args[argidx][0] != '\\') - top_mod = design->modules.count("\\" + args[argidx]) > 0 ? design->modules["\\" + args[argidx]] : NULL; - else - top_mod = design->modules.count(args[argidx]) > 0 ? design->modules[args[argidx]] : NULL; + top_mod = design->modules.count(RTLIL::escape_id(args[argidx])) ? design->modules.at(RTLIL::escape_id(args[argidx])) : NULL; + if (top_mod == NULL && design->modules.count("$abstract" + RTLIL::escape_id(args[argidx]))) { + std::map empty_parameters; + design->modules.at("$abstract" + RTLIL::escape_id(args[argidx]))->derive(design, empty_parameters); + top_mod = design->modules.count(RTLIL::escape_id(args[argidx])) ? design->modules.at(RTLIL::escape_id(args[argidx])) : NULL; + } if (top_mod == NULL) log_cmd_error("Module `%s' not found!\n", args[argidx].c_str()); continue; @@ -387,7 +399,7 @@ struct HierarchyPass : public Pass { top_mod = mod_it.second; if (top_mod != NULL) - hierarchy(design, top_mod, purge_lib); + hierarchy(design, top_mod, purge_lib, true); bool did_something = true; bool did_something_once = false; @@ -409,7 +421,7 @@ struct HierarchyPass : public Pass { if (top_mod != NULL && did_something_once) { log_header("Re-running hierarchy analysis..\n"); - hierarchy(design, top_mod, purge_lib); + hierarchy(design, top_mod, purge_lib, false); } if (top_mod != NULL) { -- cgit v1.2.3 From a1239416185aebca03d131dc3ebe3e3d45c5a9f3 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 13 Feb 2014 18:56:36 +0100 Subject: Updated ABC --- passes/abc/abc.cc | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) (limited to 'passes') diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index dae3a22fc..eaecb7910 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -640,9 +640,32 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std f = popen(buffer.c_str(), "r"); if (f == NULL) log_error("Opening pipe to `%s' for reading failed: %s\n", buffer.c_str(), strerror(errno)); +#if 0 char logbuf[1024]; while (fgets(logbuf, 1024, f) != NULL) log("ABC: %s", logbuf); +#else + bool got_cr = false; + std::string linebuf; + char logbuf[1024]; + while (fgets(logbuf, 1024, f) != NULL) + for (char *p = logbuf; *p; p++) { + if (*p == '\r') { + got_cr = true; + continue; + } + if (*p == '\n') { + log("ABC: %s\n", linebuf.c_str()); + got_cr = false, linebuf.clear(); + continue; + } + if (got_cr) + got_cr = false, linebuf.clear(); + linebuf += *p; + } + if (!linebuf.empty()) + log("ABC: %s\n", linebuf.c_str()); +#endif errno = 0; int ret = pclose(f); if (ret < 0) -- cgit v1.2.3 From de3ea9269a55b653b94651559bebc93e01e28afb Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 13 Feb 2014 19:14:15 +0100 Subject: updated default ABC command strings --- passes/abc/abc.cc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'passes') diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index eaecb7910..4add6452d 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -29,10 +29,10 @@ // Kahn, Arthur B. (1962), "Topological sorting of large networks", Communications of the ACM 5 (11): 558–562, doi:10.1145/368996.369025 // http://en.wikipedia.org/wiki/Topological_sorting -#define ABC_COMMAND_LIB "strash; ifraig -v; retime -v; balance -v; scorr -v; dch -vf; map -v;" -#define ABC_COMMAND_CTR "strash; ifraig -v; retime -v; balance -v; scorr -v; dch -vf; map -v; buffer -v; upsize -v; dnsize -v; stime -p" -#define ABC_COMMAND_LUT "strash; ifraig -v; retime -v; balance -v; scorr -v; dch -vf; if -v" -#define ABC_COMMAND_DFL "strash; ifraig -v; retime -v; balance -v; scorr -v; dch -vf; map -v" +#define ABC_COMMAND_LIB "strash; scorr -v; ifraig -v; retime -v; strash; dch -vf; map -v" +#define ABC_COMMAND_CTR "strash; scorr -v; ifraig -v; retime -v; strash; dch -vf; map -v; buffer -v; upsize -v; dnsize -v; stime -p" +#define ABC_COMMAND_LUT "strash; scorr -v; ifraig -v; retime -v; strash; dch -vf; if -v" +#define ABC_COMMAND_DFL "strash; scorr -v; ifraig -v; retime -v; strash; dch -vf; map -v" #include "kernel/register.h" #include "kernel/sigtools.h" -- cgit v1.2.3 From 3121d19d95ae916b96baa000197f3ec2aa5c5ad7 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 14 Feb 2014 11:28:42 +0100 Subject: Added abc -keepff option --- passes/abc/abc.cc | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) (limited to 'passes') diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index 4add6452d..bd0d983ac 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -109,7 +109,7 @@ static void mark_port(RTLIL::SigSpec sig) } } -static void extract_cell(RTLIL::Cell *cell) +static void extract_cell(RTLIL::Cell *cell, bool keepff) { if (cell->type == "$_DFF_N_" || cell->type == "$_DFF_P_") { @@ -121,6 +121,11 @@ static void extract_cell(RTLIL::Cell *cell) RTLIL::SigSpec sig_d = cell->connections["\\D"]; RTLIL::SigSpec sig_q = cell->connections["\\Q"]; + if (keepff) + for (auto &c : sig_q.chunks) + if (c.wire != NULL) + c.wire->attributes["\\keep"] = 1; + assign_map.apply(sig_d); assign_map.apply(sig_q); @@ -403,7 +408,7 @@ static std::string fold_abc_cmd(std::string str) } static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::string script_file, std::string exe_file, - std::string liberty_file, std::string constr_file, bool cleanup, int lut_mode, bool dff_mode, std::string clk_str) + std::string liberty_file, std::string constr_file, bool cleanup, int lut_mode, bool dff_mode, std::string clk_str, bool keepff) { module = current_module; map_autoidx = RTLIL::autoidx++; @@ -498,7 +503,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std if (design->selected(current_module, it.second)) cells.push_back(it.second); for (auto c : cells) - extract_cell(c); + extract_cell(c, keepff); for (auto &wire_it : module->wires) { if (wire_it.second->port_id > 0 || wire_it.second->get_bool_attribute("\\keep")) @@ -940,6 +945,10 @@ struct AbcPass : public Pass { log(" with -dff, then it falls back to the automatic dection of clock domain\n"); log(" if the specified clock is not found in a module.)\n"); log("\n"); + log(" -keepff\n"); + log(" set the \"keep\" attribute on flip-flop output wires. (and thus preserve\n"); + log(" them, for example for equivialence checking.)\n"); + log("\n"); log(" -nocleanup\n"); log(" when this option is used, the temporary files created by this pass\n"); log(" are not removed. this is useful for debugging.\n"); @@ -960,7 +969,7 @@ struct AbcPass : public Pass { std::string exe_file = rewrite_yosys_exe("yosys-abc"); std::string script_file, liberty_file, constr_file, clk_str; - bool dff_mode = false, cleanup = true; + bool dff_mode = false, keepff = false, cleanup = true; int lut_mode = 0; size_t argidx; @@ -1001,6 +1010,10 @@ struct AbcPass : public Pass { clk_str = args[++argidx]; continue; } + if (arg == "-keepff") { + keepff = true; + continue; + } if (arg == "-nocleanup") { cleanup = false; continue; @@ -1020,7 +1033,7 @@ struct AbcPass : public Pass { if (mod_it.second->processes.size() > 0) log("Skipping module %s as it contains processes.\n", mod_it.second->name.c_str()); else - abc_module(design, mod_it.second, script_file, exe_file, liberty_file, constr_file, cleanup, lut_mode, dff_mode, clk_str); + abc_module(design, mod_it.second, script_file, exe_file, liberty_file, constr_file, cleanup, lut_mode, dff_mode, clk_str, keepff); } assign_map.clear(); -- cgit v1.2.3 From 67effc9f5bc82b45ff163bfefea53c40d2c8819a Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 15 Feb 2014 13:16:08 +0100 Subject: Fixed opt_const handling of double invert with non-1 output width --- passes/opt/opt_const.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index 34d1a69c1..f611d7211 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -108,7 +108,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons #define ACTION_DO(_p_, _s_) do { replace_cell(module, cell, input.as_string(), _p_, _s_); goto next_cell; } while (0) #define ACTION_DO_Y(_v_) ACTION_DO("\\Y", RTLIL::SigSpec(RTLIL::State::S ## _v_)) - if ((cell->type == "$_INV_" || cell->type == "$not" || cell->type == "$logic_not") && + if ((cell->type == "$_INV_" || cell->type == "$not" || cell->type == "$logic_not") && cell->connections["\\Y"].width == 1 && invert_map.count(assign_map(cell->connections["\\A"])) != 0) { replace_cell(module, cell, "double_invert", "\\Y", invert_map.at(assign_map(cell->connections["\\A"]))); goto next_cell; -- cgit v1.2.3 From cdf0f10760d08b8349f392f1cbe41a6ca2b1f49e Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 15 Feb 2014 16:34:12 +0100 Subject: Fixed dfflibmap for cell libraries with no set-reset-ff --- passes/techmap/dfflibmap.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc index 23d93353f..fd5fa86e1 100644 --- a/passes/techmap/dfflibmap.cc +++ b/passes/techmap/dfflibmap.cc @@ -342,7 +342,7 @@ static bool expand_cellmap(std::string pattern, std::string inv) static void map_sr_to_arst(const char *from, const char *to) { - if (cell_mappings.count(to) > 0) + if (!cell_mappings.count(from) || cell_mappings.count(to) > 0) return; char from_clk_pol = from[8], from_set_pol = from[9], from_clr_pol = from[10]; -- cgit v1.2.3 From 623a68f5283331d96cded03bfd323266c88286f6 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 15 Feb 2014 21:59:26 +0100 Subject: Added iopadmap -bits --- passes/techmap/iopadmap.cc | 62 +++++++++++++++++++++++++++++++++++----------- 1 file changed, 48 insertions(+), 14 deletions(-) (limited to 'passes') diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc index b98214977..cc678516f 100644 --- a/passes/techmap/iopadmap.cc +++ b/passes/techmap/iopadmap.cc @@ -57,6 +57,11 @@ struct IopadmapPass : public Pass { log(" -nameparam \n"); log(" Use the specified parameter to set the port name.\n"); log("\n"); + log(" -bits\n"); + log(" create individual bit-wide buffers even for ports that\n"); + log(" are wider. (the default behavio is to create word-wide\n"); + log(" buffers use -widthparam to set the word size on the cell.)\n"); + log("\n"); } virtual void execute(std::vector args, RTLIL::Design *design) { @@ -66,6 +71,7 @@ struct IopadmapPass : public Pass { std::string outpad_celltype, outpad_portname, outpad_portname2; std::string inoutpad_celltype, inoutpad_portname, inoutpad_portname2; std::string widthparam, nameparam; + bool flag_bits = false; size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) @@ -97,6 +103,10 @@ struct IopadmapPass : public Pass { nameparam = args[++argidx]; continue; } + if (arg == "-bits") { + flag_bits = true; + continue; + } break; } extra_args(args, argidx, design); @@ -146,31 +156,55 @@ struct IopadmapPass : public Pass { } else log_abort(); - if (wire->width != 1 && widthparam.empty()) { - log("Don't map multi-bit port %s.%s: Missing option -widthparam.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name)); + if (!flag_bits && wire->width != 1 && widthparam.empty()) { + log("Don't map multi-bit port %s.%s: Missing option -widthparam or -bits.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name)); continue; } log("Mapping port %s.%s using %s.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name), celltype.c_str()); - RTLIL::Cell *cell = new RTLIL::Cell; - cell->name = NEW_ID; - cell->type = RTLIL::escape_id(celltype); - cell->connections[RTLIL::escape_id(portname)] = RTLIL::SigSpec(wire); + RTLIL::Wire *new_wire = NULL; if (!portname2.empty()) { - RTLIL::Wire *new_wire = new RTLIL::Wire; + new_wire = new RTLIL::Wire; *new_wire = *wire; wire->name = NEW_ID; module->wires[wire->name] = wire; module->wires[new_wire->name] = new_wire; - cell->connections[RTLIL::escape_id(portname2)] = RTLIL::SigSpec(new_wire); } - if (!widthparam.empty()) - cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(wire->width); - if (!nameparam.empty()) - cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(RTLIL::id2cstr(wire->name)); - cell->attributes["\\keep"] = RTLIL::Const(1); - module->add(cell); + + if (flag_bits) + { + for (int i = 0; i < wire->width; i++) + { + RTLIL::Cell *cell = new RTLIL::Cell; + cell->name = NEW_ID; + cell->type = RTLIL::escape_id(celltype); + cell->connections[RTLIL::escape_id(portname)] = RTLIL::SigSpec(wire, 1, i); + if (!portname2.empty()) + cell->connections[RTLIL::escape_id(portname2)] = RTLIL::SigSpec(new_wire, 1, i); + if (!widthparam.empty()) + cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(1); + if (!nameparam.empty()) + cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(stringf("%s[%d]", RTLIL::id2cstr(wire->name), i)); + cell->attributes["\\keep"] = RTLIL::Const(1); + module->add(cell); + } + } + else + { + RTLIL::Cell *cell = new RTLIL::Cell; + cell->name = NEW_ID; + cell->type = RTLIL::escape_id(celltype); + cell->connections[RTLIL::escape_id(portname)] = RTLIL::SigSpec(wire); + if (!portname2.empty()) + cell->connections[RTLIL::escape_id(portname2)] = RTLIL::SigSpec(new_wire); + if (!widthparam.empty()) + cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(wire->width); + if (!nameparam.empty()) + cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(RTLIL::id2cstr(wire->name)); + cell->attributes["\\keep"] = RTLIL::Const(1); + module->add(cell); + } wire->port_id = 0; wire->port_input = false; -- cgit v1.2.3 From 9a816b65a80a7a56b06ac5d0859be73b24008202 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 16 Feb 2014 00:16:54 +0100 Subject: Added != support for relational select pattern --- passes/cmds/select.cc | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index a1a64f145..3a886b1c8 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -63,6 +63,8 @@ static bool match_attr_val(const RTLIL::Const &value, std::string pattern, char if (match_op == '=') return value == pattern_value; + if (match_op == '!') + return value != pattern_value; if (match_op == '<') return value.as_int() < pattern_value.as_int(); if (match_op == '>') @@ -82,6 +84,8 @@ static bool match_attr_val(const RTLIL::Const &value, std::string pattern, char if (match_op == '=') return value_str == pattern; + if (match_op == '!') + return value_str != pattern; if (match_op == '<') return value_str < pattern; if (match_op == '>') @@ -115,9 +119,11 @@ static bool match_attr(const std::map &attributes static bool match_attr(const std::map &attributes, std::string match_expr) { - size_t pos = match_expr.find_first_of("<=>"); + size_t pos = match_expr.find_first_of(""); if (pos != std::string::npos) { + if (match_expr.substr(pos, 2) == "!=") + return match_attr(attributes, match_expr.substr(0, pos), match_expr.substr(pos+2), '!'); if (match_expr.substr(pos, 2) == "<=") return match_attr(attributes, match_expr.substr(0, pos), match_expr.substr(pos+2), '['); if (match_expr.substr(pos, 2) == ">=") -- cgit v1.2.3 From d3dc22a90f8b87ffe0109b0fa2074d887642e7cb Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 16 Feb 2014 17:16:44 +0100 Subject: Added recursion support to techmap --- passes/techmap/techmap.cc | 522 +++++++++++++++++++++++----------------------- 1 file changed, 262 insertions(+), 260 deletions(-) (limited to 'passes') diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index eeeebd111..eb044d6fe 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -50,317 +50,320 @@ static void apply_prefix(std::string prefix, RTLIL::SigSpec &sig, RTLIL::Module } } -std::map simplemap_mappers; -std::map>, RTLIL::Module*> techmap_cache; -std::map techmap_do_cache; +struct TechmapWorker +{ + std::map simplemap_mappers; + std::map>, RTLIL::Module*> techmap_cache; + std::map techmap_do_cache; -struct TechmapWireData { - RTLIL::Wire *wire; - RTLIL::SigSpec value; -}; + struct TechmapWireData { + RTLIL::Wire *wire; + RTLIL::SigSpec value; + }; -typedef std::map> TechmapWires; + typedef std::map> TechmapWires; -static TechmapWires techmap_find_special_wires(RTLIL::Module *module) -{ - TechmapWires result; + TechmapWires techmap_find_special_wires(RTLIL::Module *module) + { + TechmapWires result; - if (module == NULL) - return result; + if (module == NULL) + return result; - for (auto &it : module->wires) { - const char *p = it.first.c_str(); - if (*p == '$') - continue; + for (auto &it : module->wires) { + const char *p = it.first.c_str(); + if (*p == '$') + continue; - const char *q = strrchr(p+1, '.'); - p = q ? q : p+1; + const char *q = strrchr(p+1, '.'); + p = q ? q : p+1; - if (!strncmp(p, "_TECHMAP_", 9)) { - TechmapWireData record; - record.wire = it.second; - record.value = it.second; - result[p].push_back(record); - it.second->attributes["\\keep"] = RTLIL::Const(1); - it.second->attributes["\\_techmap_special_"] = RTLIL::Const(1); + if (!strncmp(p, "_TECHMAP_", 9)) { + TechmapWireData record; + record.wire = it.second; + record.value = it.second; + result[p].push_back(record); + it.second->attributes["\\keep"] = RTLIL::Const(1); + it.second->attributes["\\_techmap_special_"] = RTLIL::Const(1); + } } - } - if (!result.empty()) { - SigMap sigmap(module); - for (auto &it1 : result) - for (auto &it2 : it1.second) - sigmap.apply(it2.value); - } - - return result; -} + if (!result.empty()) { + SigMap sigmap(module); + for (auto &it1 : result) + for (auto &it2 : it1.second) + sigmap.apply(it2.value); + } -static void techmap_module_worker(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Cell *cell, RTLIL::Module *tpl, bool flatten_mode) -{ - log("Mapping `%s.%s' using `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(tpl->name)); - - if (tpl->memories.size() != 0) - log_error("Technology map yielded memories -> this is not supported.\n"); - - if (tpl->processes.size() != 0) - log_error("Technology map yielded processes -> this is not supported.\n"); - - std::map positional_ports; - - for (auto &it : tpl->wires) { - if (it.second->port_id > 0) - positional_ports[stringf("$%d", it.second->port_id)] = it.first; - RTLIL::Wire *w = new RTLIL::Wire(*it.second); - apply_prefix(cell->name, w->name); - w->port_input = false; - w->port_output = false; - w->port_id = 0; - if (it.second->get_bool_attribute("\\_techmap_special_")) - w->attributes.clear(); - module->wires[w->name] = w; - design->select(module, w); + return result; } - SigMap port_signal_map; - - for (auto &it : cell->connections) { - RTLIL::IdString portname = it.first; - if (positional_ports.count(portname) > 0) - portname = positional_ports.at(portname); - if (tpl->wires.count(portname) == 0 || tpl->wires.at(portname)->port_id == 0) { - if (portname.substr(0, 1) == "$") - log_error("Can't map port `%s' of cell `%s' to template `%s'!\n", portname.c_str(), cell->name.c_str(), tpl->name.c_str()); - continue; - } - RTLIL::Wire *w = tpl->wires.at(portname); - RTLIL::SigSig c; - if (w->port_output) { - c.first = it.second; - c.second = RTLIL::SigSpec(w); - apply_prefix(cell->name, c.second, module); - } else { - c.first = RTLIL::SigSpec(w); - c.second = it.second; - apply_prefix(cell->name, c.first, module); + void techmap_module_worker(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Cell *cell, RTLIL::Module *tpl, bool flatten_mode) + { + log("Mapping `%s.%s' using `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(tpl->name)); + + if (tpl->memories.size() != 0) + log_error("Technology map yielded memories -> this is not supported.\n"); + + if (tpl->processes.size() != 0) + log_error("Technology map yielded processes -> this is not supported.\n"); + + std::map positional_ports; + + for (auto &it : tpl->wires) { + if (it.second->port_id > 0) + positional_ports[stringf("$%d", it.second->port_id)] = it.first; + RTLIL::Wire *w = new RTLIL::Wire(*it.second); + apply_prefix(cell->name, w->name); + w->port_input = false; + w->port_output = false; + w->port_id = 0; + if (it.second->get_bool_attribute("\\_techmap_special_")) + w->attributes.clear(); + module->wires[w->name] = w; + design->select(module, w); } - if (c.second.width > c.first.width) - c.second.remove(c.first.width, c.second.width - c.first.width); - if (c.second.width < c.first.width) - c.second.append(RTLIL::SigSpec(RTLIL::State::S0, c.first.width - c.second.width)); - assert(c.first.width == c.second.width); + + SigMap port_signal_map; + + for (auto &it : cell->connections) { + RTLIL::IdString portname = it.first; + if (positional_ports.count(portname) > 0) + portname = positional_ports.at(portname); + if (tpl->wires.count(portname) == 0 || tpl->wires.at(portname)->port_id == 0) { + if (portname.substr(0, 1) == "$") + log_error("Can't map port `%s' of cell `%s' to template `%s'!\n", portname.c_str(), cell->name.c_str(), tpl->name.c_str()); + continue; + } + RTLIL::Wire *w = tpl->wires.at(portname); + RTLIL::SigSig c; + if (w->port_output) { + c.first = it.second; + c.second = RTLIL::SigSpec(w); + apply_prefix(cell->name, c.second, module); + } else { + c.first = RTLIL::SigSpec(w); + c.second = it.second; + apply_prefix(cell->name, c.first, module); + } + if (c.second.width > c.first.width) + c.second.remove(c.first.width, c.second.width - c.first.width); + if (c.second.width < c.first.width) + c.second.append(RTLIL::SigSpec(RTLIL::State::S0, c.first.width - c.second.width)); + assert(c.first.width == c.second.width); #if 0 - // more conservative approach: - // connect internal and external wires - module->connections.push_back(c); + // more conservative approach: + // connect internal and external wires + module->connections.push_back(c); #else - // approach that yields nicer outputs: - // replace internal wires that are connected to external wires - if (w->port_output) - port_signal_map.add(c.second, c.first); - else - port_signal_map.add(c.first, c.second); + // approach that yields nicer outputs: + // replace internal wires that are connected to external wires + if (w->port_output) + port_signal_map.add(c.second, c.first); + else + port_signal_map.add(c.first, c.second); #endif - } + } + + for (auto &it : tpl->cells) { + RTLIL::Cell *c = new RTLIL::Cell(*it.second); + if (!flatten_mode && c->type.substr(0, 2) == "\\$") + c->type = c->type.substr(1); + apply_prefix(cell->name, c->name); + for (auto &it2 : c->connections) { + apply_prefix(cell->name, it2.second, module); + port_signal_map.apply(it2.second); + } + module->cells[c->name] = c; + design->select(module, c); + } - for (auto &it : tpl->cells) { - RTLIL::Cell *c = new RTLIL::Cell(*it.second); - if (!flatten_mode && c->type.substr(0, 2) == "\\$") - c->type = c->type.substr(1); - apply_prefix(cell->name, c->name); - for (auto &it2 : c->connections) { - apply_prefix(cell->name, it2.second, module); - port_signal_map.apply(it2.second); + for (auto &it : tpl->connections) { + RTLIL::SigSig c = it; + apply_prefix(cell->name, c.first, module); + apply_prefix(cell->name, c.second, module); + port_signal_map.apply(c.first); + port_signal_map.apply(c.second); + module->connections.push_back(c); } - module->cells[c->name] = c; - design->select(module, c); - } - for (auto &it : tpl->connections) { - RTLIL::SigSig c = it; - apply_prefix(cell->name, c.first, module); - apply_prefix(cell->name, c.second, module); - port_signal_map.apply(c.first); - port_signal_map.apply(c.second); - module->connections.push_back(c); + module->cells.erase(cell->name); + delete cell; } - module->cells.erase(cell->name); - delete cell; -} + bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, std::set &handled_cells, + const std::map> &celltypeMap, bool flatten_mode) + { + if (!design->selected(module)) + return false; -static bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, std::set &handled_cells, - const std::map> &celltypeMap, bool flatten_mode) -{ - if (!design->selected(module)) - return false; + bool log_continue = false; + bool did_something = false; + std::vector cell_names; - bool log_continue = false; - bool did_something = false; - std::vector cell_names; + for (auto &cell_it : module->cells) + cell_names.push_back(cell_it.first); - for (auto &cell_it : module->cells) - cell_names.push_back(cell_it.first); + for (auto &cell_name : cell_names) + { + if (module->cells.count(cell_name) == 0) + continue; - for (auto &cell_name : cell_names) - { - if (module->cells.count(cell_name) == 0) - continue; + RTLIL::Cell *cell = module->cells[cell_name]; - RTLIL::Cell *cell = module->cells[cell_name]; + if (!design->selected(module, cell) || handled_cells.count(cell) > 0) + continue; - if (!design->selected(module, cell) || handled_cells.count(cell) > 0) - continue; + if (celltypeMap.count(cell->type) == 0) + continue; - if (celltypeMap.count(cell->type) == 0) - continue; + for (auto &tpl_name : celltypeMap.at(cell->type)) + { + std::string derived_name = tpl_name; + RTLIL::Module *tpl = map->modules[tpl_name]; + std::map parameters = cell->parameters; - for (auto &tpl_name : celltypeMap.at(cell->type)) - { - std::string derived_name = tpl_name; - RTLIL::Module *tpl = map->modules[tpl_name]; - std::map parameters = cell->parameters; + if (!flatten_mode) + { + if (tpl->get_bool_attribute("\\techmap_simplemap")) { + log("Mapping %s.%s (%s) with simplemap.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); + if (simplemap_mappers.count(cell->type) == 0) + log_error("No simplemap mapper for cell type %s found!\n", RTLIL::id2cstr(cell->type)); + simplemap_mappers.at(cell->type)(module, cell); + module->cells.erase(cell->name); + delete cell; + cell = NULL; + did_something = true; + break; + } - if (!flatten_mode) - { - if (tpl->get_bool_attribute("\\techmap_simplemap")) { - log("Mapping %s.%s (%s) with simplemap.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); - if (simplemap_mappers.count(cell->type) == 0) - log_error("No simplemap mapper for cell type %s found!\n", RTLIL::id2cstr(cell->type)); - simplemap_mappers.at(cell->type)(module, cell); - module->cells.erase(cell->name); - delete cell; - cell = NULL; - did_something = true; - break; - } + for (auto conn : cell->connections) { + if (conn.first.substr(0, 1) == "$") + continue; + if (tpl->wires.count(conn.first) > 0 && tpl->wires.at(conn.first)->port_id > 0) + continue; + if (!conn.second.is_fully_const() || parameters.count(conn.first) > 0 || tpl->avail_parameters.count(conn.first) == 0) + goto next_tpl; + parameters[conn.first] = conn.second.as_const(); + } - for (auto conn : cell->connections) { - if (conn.first.substr(0, 1) == "$") - continue; - if (tpl->wires.count(conn.first) > 0 && tpl->wires.at(conn.first)->port_id > 0) + if (0) { + next_tpl: continue; - if (!conn.second.is_fully_const() || parameters.count(conn.first) > 0 || tpl->avail_parameters.count(conn.first) == 0) - goto next_tpl; - parameters[conn.first] = conn.second.as_const(); - } + } - if (0) { - next_tpl: - continue; + if (tpl->avail_parameters.count("\\_TECHMAP_CELLTYPE_") != 0) + parameters["\\_TECHMAP_CELLTYPE_"] = RTLIL::unescape_id(cell->type); } - if (tpl->avail_parameters.count("\\_TECHMAP_CELLTYPE_") != 0) - parameters["\\_TECHMAP_CELLTYPE_"] = RTLIL::unescape_id(cell->type); - } - - std::pair> key(tpl_name, parameters); - if (techmap_cache.count(key) > 0) { - tpl = techmap_cache[key]; - } else { - if (cell->parameters.size() != 0) { - derived_name = tpl->derive(map, parameters); - tpl = map->modules[derived_name]; - log_continue = true; + std::pair> key(tpl_name, parameters); + if (techmap_cache.count(key) > 0) { + tpl = techmap_cache[key]; + } else { + if (cell->parameters.size() != 0) { + derived_name = tpl->derive(map, parameters); + tpl = map->modules[derived_name]; + log_continue = true; + } + techmap_cache[key] = tpl; } - techmap_cache[key] = tpl; - } - - if (flatten_mode) - techmap_do_cache[tpl] = true; - if (techmap_do_cache.count(tpl) == 0) - { - bool keep_running = true; - techmap_do_cache[tpl] = true; + if (flatten_mode) + techmap_do_cache[tpl] = true; - while (keep_running) + if (techmap_do_cache.count(tpl) == 0) { - TechmapWires twd = techmap_find_special_wires(tpl); - keep_running = false; - - for (auto &it : twd["_TECHMAP_FAIL_"]) { - RTLIL::SigSpec value = it.value; - if (value.is_fully_const() && value.as_bool()) { - log("Not using module `%s' from techmap as it contains a %s marker wire with non-zero value %s.\n", - derived_name.c_str(), RTLIL::id2cstr(it.wire->name), log_signal(value)); - techmap_do_cache[tpl] = false; + bool keep_running = true; + techmap_do_cache[tpl] = true; + + while (keep_running) + { + TechmapWires twd = techmap_find_special_wires(tpl); + keep_running = false; + + for (auto &it : twd["_TECHMAP_FAIL_"]) { + RTLIL::SigSpec value = it.value; + if (value.is_fully_const() && value.as_bool()) { + log("Not using module `%s' from techmap as it contains a %s marker wire with non-zero value %s.\n", + derived_name.c_str(), RTLIL::id2cstr(it.wire->name), log_signal(value)); + techmap_do_cache[tpl] = false; + } } - } - if (!techmap_do_cache[tpl]) - break; + if (!techmap_do_cache[tpl]) + break; - for (auto &it : twd) - { - if (it.first.substr(0, 12) != "_TECHMAP_DO_" || it.second.empty()) - continue; + for (auto &it : twd) + { + if (it.first.substr(0, 12) != "_TECHMAP_DO_" || it.second.empty()) + continue; - auto &data = it.second.front(); + auto &data = it.second.front(); - if (!data.value.is_fully_const()) - log_error("Techmap yielded config wire %s with non-const value %s.\n", RTLIL::id2cstr(data.wire->name), log_signal(data.value)); + if (!data.value.is_fully_const()) + log_error("Techmap yielded config wire %s with non-const value %s.\n", RTLIL::id2cstr(data.wire->name), log_signal(data.value)); - tpl->wires.erase(data.wire->name); - const char *p = data.wire->name.c_str(); - const char *q = strrchr(p+1, '.'); - q = q ? q : p+1; + tpl->wires.erase(data.wire->name); + const char *p = data.wire->name.c_str(); + const char *q = strrchr(p+1, '.'); + q = q ? q : p+1; - assert(!strncmp(q, "_TECHMAP_DO_", 12)); - std::string new_name = data.wire->name.substr(0, q-p) + "_TECHMAP_DONE_" + data.wire->name.substr(q-p+12); - while (tpl->wires.count(new_name)) - new_name += "_"; - data.wire->name = new_name; - tpl->add(data.wire); + assert(!strncmp(q, "_TECHMAP_DO_", 12)); + std::string new_name = data.wire->name.substr(0, q-p) + "_TECHMAP_DONE_" + data.wire->name.substr(q-p+12); + while (tpl->wires.count(new_name)) + new_name += "_"; + data.wire->name = new_name; + tpl->add(data.wire); - std::string cmd_string = data.value.as_const().decode_string(); + std::string cmd_string = data.value.as_const().decode_string(); - RTLIL::Selection tpl_mod_sel(false); - tpl_mod_sel.select(tpl); - map->selection_stack.push_back(tpl_mod_sel); - Pass::call(map, cmd_string); - map->selection_stack.pop_back(); + RTLIL::Selection tpl_mod_sel(false); + tpl_mod_sel.select(tpl); + map->selection_stack.push_back(tpl_mod_sel); + Pass::call(map, cmd_string); + map->selection_stack.pop_back(); - keep_running = true; - break; + keep_running = true; + break; + } } - } - TechmapWires twd = techmap_find_special_wires(tpl); - for (auto &it : twd) { - if (it.first != "_TECHMAP_FAIL_" && it.first.substr(0, 12) != "_TECHMAP_DO_" && it.first.substr(0, 14) != "_TECHMAP_DONE_") - log_error("Techmap yielded unknown config wire %s.\n", it.first.c_str()); - if (techmap_do_cache[tpl]) - for (auto &it2 : it.second) - if (!it2.value.is_fully_const()) - log_error("Techmap yielded config wire %s with non-const value %s.\n", RTLIL::id2cstr(it2.wire->name), log_signal(it2.value)); + TechmapWires twd = techmap_find_special_wires(tpl); + for (auto &it : twd) { + if (it.first != "_TECHMAP_FAIL_" && it.first.substr(0, 12) != "_TECHMAP_DO_" && it.first.substr(0, 14) != "_TECHMAP_DONE_") + log_error("Techmap yielded unknown config wire %s.\n", it.first.c_str()); + if (techmap_do_cache[tpl]) + for (auto &it2 : it.second) + if (!it2.value.is_fully_const()) + log_error("Techmap yielded config wire %s with non-const value %s.\n", RTLIL::id2cstr(it2.wire->name), log_signal(it2.value)); + } } - } - if (techmap_do_cache.at(tpl) == false) - continue; + if (techmap_do_cache.at(tpl) == false) + continue; + + if (log_continue) { + log_header("Continuing TECHMAP pass.\n"); + log_continue = false; + } - if (log_continue) { - log_header("Continuing TECHMAP pass.\n"); - log_continue = false; + techmap_module_worker(design, module, cell, tpl, flatten_mode); + did_something = true; + cell = NULL; + break; } - techmap_module_worker(design, module, cell, tpl, flatten_mode); - did_something = true; - cell = NULL; - break; + handled_cells.insert(cell); } - handled_cells.insert(cell); - } + if (log_continue) { + log_header("Continuing TECHMAP pass.\n"); + log_continue = false; + } - if (log_continue) { - log_header("Continuing TECHMAP pass.\n"); - log_continue = false; + return did_something; } - - return did_something; -} +}; struct TechmapPass : public Pass { TechmapPass() : Pass("techmap", "generic technology mapper") { } @@ -469,7 +472,8 @@ struct TechmapPass : public Pass { } extra_args(args, argidx, design); - simplemap_get_mappers(simplemap_mappers); + TechmapWorker worker; + simplemap_get_mappers(worker.simplemap_mappers); RTLIL::Design *map = new RTLIL::Design; if (map_files.empty()) { @@ -509,17 +513,15 @@ struct TechmapPass : public Pass { while (did_something) { did_something = false; for (auto &mod_it : design->modules) - if (techmap_module(design, mod_it.second, map, handled_cells, celltypeMap, false)) + if (worker.techmap_module(design, mod_it.second, map, handled_cells, celltypeMap, false)) did_something = true; if (did_something) design->check(); } log("No more expansions possible.\n"); - techmap_cache.clear(); - techmap_do_cache.clear(); - simplemap_mappers.clear(); delete map; + log_pop(); } } TechmapPass; @@ -544,6 +546,8 @@ struct FlattenPass : public Pass { extra_args(args, 1, design); + TechmapWorker worker; + std::map> celltypeMap; for (auto &it : design->modules) celltypeMap[it.first].insert(it.first); @@ -559,11 +563,11 @@ struct FlattenPass : public Pass { while (did_something) { did_something = false; if (top_mod != NULL) { - if (techmap_module(design, top_mod, design, handled_cells, celltypeMap, true)) + if (worker.techmap_module(design, top_mod, design, handled_cells, celltypeMap, true)) did_something = true; } else { for (auto &mod_it : design->modules) - if (techmap_module(design, mod_it.second, design, handled_cells, celltypeMap, true)) + if (worker.techmap_module(design, mod_it.second, design, handled_cells, celltypeMap, true)) did_something = true; } } @@ -582,8 +586,6 @@ struct FlattenPass : public Pass { design->modules.swap(new_modules); } - techmap_cache.clear(); - techmap_do_cache.clear(); log_pop(); } } FlattenPass; -- cgit v1.2.3 From 42ce3db983fdb512e181daab1817991a661066ff Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 16 Feb 2014 17:39:50 +0100 Subject: Fixed use of selection in splitnets command --- passes/cmds/splitnets.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc index da9ef43f9..7e043bcff 100644 --- a/passes/cmds/splitnets.cc +++ b/passes/cmds/splitnets.cc @@ -169,7 +169,7 @@ struct SplitnetsPass : public Pass { { for (auto &w : module->wires) { RTLIL::Wire *wire = w.second; - if (wire->width > 1 && (wire->port_id == 0 || flag_ports)) + if (wire->width > 1 && (wire->port_id == 0 || flag_ports) && design->selected(module, w.second)) worker.splitmap[wire] = std::vector(); } -- cgit v1.2.3 From 28e14ee50a3effcd5335ec06f5b1c2acda008a4e Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 16 Feb 2014 21:58:27 +0100 Subject: Fixed handling of "keep" attribute on wires in opt_clean --- passes/opt/opt_clean.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'passes') diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 733a1cbf1..d330fb7bd 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -227,10 +227,10 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool std::vector del_wires; for (auto &it : module->wires) { RTLIL::Wire *wire = it.second; - if ((!purge_mode && check_public_name(wire->name)) || wire->port_id != 0) { + if ((!purge_mode && check_public_name(wire->name)) || wire->port_id != 0 || wire->get_bool_attribute("\\keep")) { RTLIL::SigSpec s1 = RTLIL::SigSpec(wire), s2 = s1; assign_map.apply(s2); - if (!used_signals.check_any(s2) && wire->port_id == 0) { + if (!used_signals.check_any(s2) && wire->port_id == 0 && !wire->get_bool_attribute("\\keep")) { del_wires.push_back(wire); } else { s1.expand(); -- cgit v1.2.3 From a9b11d7c83a060e59185636711c3ffa4f1c76591 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 16 Feb 2014 21:58:59 +0100 Subject: Added CONSTMSK and CONSTVAL feature to techmap --- passes/techmap/techmap.cc | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) (limited to 'passes') diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index eb044d6fe..da87c3ab7 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -201,6 +201,7 @@ struct TechmapWorker bool did_something = false; std::vector cell_names; + SigMap sigmap(module); for (auto &cell_it : module->cells) cell_names.push_back(cell_it.first); @@ -254,6 +255,22 @@ struct TechmapWorker if (tpl->avail_parameters.count("\\_TECHMAP_CELLTYPE_") != 0) parameters["\\_TECHMAP_CELLTYPE_"] = RTLIL::unescape_id(cell->type); + + for (auto conn : cell->connections) { + if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", RTLIL::id2cstr(conn.first))) != 0) { + std::vector v = sigmap(conn.second).to_sigbit_vector(); + for (auto &bit : v) + bit = RTLIL::SigBit(bit.wire == NULL ? RTLIL::State::S1 : RTLIL::State::S0); + parameters[stringf("\\_TECHMAP_CONSTMSK_%s_", RTLIL::id2cstr(conn.first))] = RTLIL::SigSpec(v).as_const(); + } + if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTVAL_%s_", RTLIL::id2cstr(conn.first))) != 0) { + std::vector v = sigmap(conn.second).to_sigbit_vector(); + for (auto &bit : v) + if (bit.wire != NULL) + bit = RTLIL::SigBit(RTLIL::State::Sx); + parameters[stringf("\\_TECHMAP_CONSTVAL_%s_", RTLIL::id2cstr(conn.first))] = RTLIL::SigSpec(v).as_const(); + } + } } std::pair> key(tpl_name, parameters); @@ -431,6 +448,12 @@ struct TechmapPass : public Pass { log(" When a parameter with this name exists, it will be set to the type name\n"); log(" of the cell that matches the module.\n"); log("\n"); + log(" _TECHMAP_CONSTMSK__\n"); + log(" _TECHMAP_CONSTVAL__\n"); + log(" When this pair of parameters is available in a module for a port, then\n"); + log(" former has a 1-bit for each constant input bit and the latter has the\n"); + log(" value for this bit. The unused bits of the latter are set to undef (x).\n"); + log("\n"); log("When a module in the map file has a parameter where the according cell in the\n"); log("design has a port, the module from the map file is only used if the port in\n"); log("the design is connected to a constant value. The parameter is then set to the\n"); -- cgit v1.2.3 From 6d63f39eb6abbefd8a12f0fe081c33ef1638800c Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 16 Feb 2014 22:18:06 +0100 Subject: Added some additional checks to techmap --- passes/techmap/techmap.cc | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'passes') diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index da87c3ab7..f0d1e6da4 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -293,11 +293,16 @@ struct TechmapWorker bool keep_running = true; techmap_do_cache[tpl] = true; + std::set techmap_wire_names; + while (keep_running) { TechmapWires twd = techmap_find_special_wires(tpl); keep_running = false; + for (auto &it : twd) + techmap_wire_names.insert(it.first); + for (auto &it : twd["_TECHMAP_FAIL_"]) { RTLIL::SigSpec value = it.value; if (value.is_fully_const() && value.as_bool()) { @@ -320,7 +325,9 @@ struct TechmapWorker if (!data.value.is_fully_const()) log_error("Techmap yielded config wire %s with non-const value %s.\n", RTLIL::id2cstr(data.wire->name), log_signal(data.value)); + techmap_wire_names.erase(it.first); tpl->wires.erase(data.wire->name); + const char *p = data.wire->name.c_str(); const char *q = strrchr(p+1, '.'); q = q ? q : p+1; @@ -335,10 +342,13 @@ struct TechmapWorker std::string cmd_string = data.value.as_const().decode_string(); RTLIL::Selection tpl_mod_sel(false); + std::string backup_active_module = map->selected_active_module; + map->selected_active_module = tpl->name; tpl_mod_sel.select(tpl); map->selection_stack.push_back(tpl_mod_sel); Pass::call(map, cmd_string); map->selection_stack.pop_back(); + map->selected_active_module = backup_active_module; keep_running = true; break; @@ -353,7 +363,11 @@ struct TechmapWorker for (auto &it2 : it.second) if (!it2.value.is_fully_const()) log_error("Techmap yielded config wire %s with non-const value %s.\n", RTLIL::id2cstr(it2.wire->name), log_signal(it2.value)); + techmap_wire_names.erase(it.first); } + + for (auto &it : techmap_wire_names) + log_error("Techmap special wire %s disappeared. This is considered a fatal error.\n", RTLIL::id2cstr(it)); } if (techmap_do_cache.at(tpl) == false) -- cgit v1.2.3 From ca53ef50982d84917a4f6d293dd0d07805bb8eb6 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 17 Feb 2014 09:44:39 +0100 Subject: Better preserve wires when flattening (in comparison to techmap) --- passes/techmap/techmap.cc | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) (limited to 'passes') diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index f0d1e6da4..53164b58a 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -151,18 +151,18 @@ struct TechmapWorker if (c.second.width < c.first.width) c.second.append(RTLIL::SigSpec(RTLIL::State::S0, c.first.width - c.second.width)); assert(c.first.width == c.second.width); -#if 0 - // more conservative approach: - // connect internal and external wires - module->connections.push_back(c); -#else - // approach that yields nicer outputs: - // replace internal wires that are connected to external wires - if (w->port_output) - port_signal_map.add(c.second, c.first); - else - port_signal_map.add(c.first, c.second); -#endif + if (flatten_mode) { + // more conservative approach: + // connect internal and external wires + module->connections.push_back(c); + } else { + // approach that yields nicer outputs: + // replace internal wires that are connected to external wires + if (w->port_output) + port_signal_map.add(c.second, c.first); + else + port_signal_map.add(c.first, c.second); + } } for (auto &it : tpl->cells) { -- cgit v1.2.3 From 4a948d780a6dd7de73b4dd05aecabe3a12863f3f Mon Sep 17 00:00:00 2001 From: Andrew Zonenberg Date: Mon, 17 Feb 2014 06:06:04 -0500 Subject: Added "-dump_fail_to_vcd" argument to SAT solver --- passes/sat/sat.cc | 114 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 114 insertions(+) (limited to 'passes') diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index c08271590..1cf4f0841 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -30,6 +30,8 @@ #include #include #include +#include +#include namespace { @@ -630,6 +632,109 @@ struct SatHelper if (last_timestep == -2) log(" no model variables selected for display.\n"); } + + void dump_model_to_vcd(std::string vcd_file_name) + { + FILE* f = fopen(vcd_file_name.c_str(), "w"); + if(!f) + log_cmd_error("Can't open output file `%s' for writing: %s\n", vcd_file_name.c_str(), strerror(errno)); + + log("Dumping SAT model to VCD file %s\n", vcd_file_name.c_str()); + + time_t timestamp; + struct tm* now; + char stime[128] = {0}; + time(×tamp); + now = localtime(×tamp); + strftime(stime, sizeof(stime), "%c", now); + + std::string module_fname = "unknown"; + auto apos = module->attributes.find("\\src"); + if(apos != module->attributes.end()) + module_fname = module->attributes["\\src"].decode_string(); + + fprintf(f, "$date\n"); + fprintf(f, " %s\n", stime); + fprintf(f, "$end\n"); + fprintf(f, "$version\n"); + fprintf(f, " Generated by %s\n", yosys_version_str); + fprintf(f, "$end\n"); + fprintf(f, "$comment\n"); + fprintf(f, " Generated from SAT problem in module %s (declared at %s)\n", + module->name.c_str(), module_fname.c_str()); + fprintf(f, "$end\n"); + + //VCD has some limits on internal (non-display) identifier names, so make legal ones + std::map vcdnames; + + fprintf(f, "$timescale 1ns\n"); //arbitrary time scale since actual clock period is unknown/unimportant + fprintf(f, "$scope module %s $end\n", module->name.c_str()); + for (auto &info : modelInfo) { + if(vcdnames.find(info.description) != vcdnames.end()) + continue; + + char namebuf[16]; + snprintf(namebuf, sizeof(namebuf), "v%d", static_cast(vcdnames.size())); + vcdnames[info.description] = namebuf; + + //Even display identifiers can't use some special characters + std::string legal_desc = info.description.c_str(); + for (auto &c : legal_desc) { + if(c == '$') + c = '_'; + if(c == ':') + c = '_'; + } + + fprintf(f, "$var wire %d %s %s $end\n", info.width, namebuf, legal_desc.c_str()); + + //Need to look at first *two* cycles! + //We need to put a name on all variables but those without an initialization clause + //have no value at timestep 0 + if(info.timestep > 1) + break; + } + fprintf(f, "$upscope $end\n"); + fprintf(f, "$enddefinitions $end\n"); + fprintf(f, "$dumpvars\n"); + + static const char bitvals[] = "01xzxx"; + + int last_timestep = -2; + for (auto &info : modelInfo) + { + RTLIL::Const value; + + for (int i = 0; i < info.width; i++) { + value.bits.push_back(modelValues.at(info.offset+i) ? RTLIL::State::S1 : RTLIL::State::S0); + if (enable_undef && modelValues.at(modelExpressions.size()/2 + info.offset + i)) + value.bits.back() = RTLIL::State::Sx; + } + + if (info.timestep != last_timestep) { + if(last_timestep == 0) + fprintf(f, "$end\n"); + else + fprintf(f, "#%d\n", info.timestep); + + last_timestep = info.timestep; + } + + if(info.width == 1) + fprintf(f, "%c%s\n", bitvals[value.bits[0]], vcdnames[info.description].c_str()); + else { + fprintf(f, "b"); + for(int k=info.width-1; k >= 0; k --) //need to flip bit ordering for VCD + fprintf(f, "%c", bitvals[value.bits[k]]); + fprintf(f, " %s\n", vcdnames[info.description].c_str()); + } + } + + if (last_timestep == -2) + log(" no model variables selected for display.\n"); + + fclose(f); + } void invalidate_model(bool max_undef) { @@ -822,6 +927,8 @@ struct SatPass : public Pass { bool ignore_div_by_zero = false, set_init_undef = false, set_init_zero = false, max_undef = false; bool tempinduct = false, prove_asserts = false, show_inputs = false, show_outputs = false; bool ignore_unknown_cells = false, falsify = false, tempinduct_def = false, set_init_def = false; + bool dump_fail_to_vcd = false; + std::string vcd_file_name = ""; log_header("Executing SAT pass (solving SAT problems in the circuit).\n"); @@ -995,6 +1102,11 @@ struct SatPass : public Pass { ignore_unknown_cells = true; continue; } + if (args[argidx] == "-dump_fail_to_vcd" && argidx+1 < args.size()) { + dump_fail_to_vcd = true; + vcd_file_name = args[++argidx]; + continue; + } break; } extra_args(args, argidx, design); @@ -1107,6 +1219,8 @@ struct SatPass : public Pass { log("SAT temporal induction proof finished - model found for base case: FAIL!\n"); print_proof_failed(); basecase.print_model(); + if(dump_fail_to_vcd) + basecase.dump_model_to_vcd(vcd_file_name); goto tip_failed; } -- cgit v1.2.3 From 0851c2b6ea7044d9bce2014a2be2365a2bf7e1b0 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 17 Feb 2014 13:57:14 +0100 Subject: Renamed "sat -dump_fail_to_vcd" to "sat -dump_vcd" and some minor cleanups --- passes/sat/sat.cc | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) (limited to 'passes') diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 1cf4f0841..2cd15d01c 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -875,6 +875,9 @@ struct SatPass : public Pass { log(" -set-init-zero\n"); log(" set all initial states (not set using -set-init) to zero\n"); log("\n"); + log(" -dump_vcd \n"); + log(" dump SAT model (counter example in proof) to VCD file\n"); + log("\n"); log("The following additional options can be used to set up a proof. If also -seq\n"); log("is passed, a temporal induction proof is performed.\n"); log("\n"); @@ -927,8 +930,7 @@ struct SatPass : public Pass { bool ignore_div_by_zero = false, set_init_undef = false, set_init_zero = false, max_undef = false; bool tempinduct = false, prove_asserts = false, show_inputs = false, show_outputs = false; bool ignore_unknown_cells = false, falsify = false, tempinduct_def = false, set_init_def = false; - bool dump_fail_to_vcd = false; - std::string vcd_file_name = ""; + std::string vcd_file_name; log_header("Executing SAT pass (solving SAT problems in the circuit).\n"); @@ -1102,8 +1104,7 @@ struct SatPass : public Pass { ignore_unknown_cells = true; continue; } - if (args[argidx] == "-dump_fail_to_vcd" && argidx+1 < args.size()) { - dump_fail_to_vcd = true; + if (args[argidx] == "-dump_vcd" && argidx+1 < args.size()) { vcd_file_name = args[++argidx]; continue; } @@ -1219,7 +1220,7 @@ struct SatPass : public Pass { log("SAT temporal induction proof finished - model found for base case: FAIL!\n"); print_proof_failed(); basecase.print_model(); - if(dump_fail_to_vcd) + if(!vcd_file_name.empty()) basecase.dump_model_to_vcd(vcd_file_name); goto tip_failed; } @@ -1344,6 +1345,9 @@ struct SatPass : public Pass { sathelper.print_model(); + if(!vcd_file_name.empty()) + sathelper.dump_model_to_vcd(vcd_file_name); + if (loopcount != 0) { loopcount--, rerun_counter++; sathelper.invalidate_model(max_undef); -- cgit v1.2.3 From 13051e6acf6c1fd506a49d258c3d99c1334c78cc Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 18 Feb 2014 09:03:16 +0100 Subject: Added "sat -initsteps" --- passes/sat/sat.cc | 43 +++++++++++++++++++++++++++++-------------- 1 file changed, 29 insertions(+), 14 deletions(-) (limited to 'passes') diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 2cd15d01c..2dc7a16ba 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -903,6 +903,9 @@ struct SatPass : public Pass { log(" -maxsteps \n"); log(" Set a maximum length for the induction.\n"); log("\n"); + log(" -initsteps \n"); + log(" Set initial length for the induction.\n"); + log("\n"); log(" -timeout \n"); log(" Maximum number of seconds a single SAT instance may take.\n"); log("\n"); @@ -925,7 +928,7 @@ struct SatPass : public Pass { std::map>> sets_at; std::map> unsets_at, sets_def_at, sets_any_undef_at, sets_all_undef_at; std::vector shows, sets_def, sets_any_undef, sets_all_undef; - int loopcount = 0, seq_len = 0, maxsteps = 0, timeout = 0; + int loopcount = 0, seq_len = 0, maxsteps = 0, initsteps = 0, timeout = 0; bool verify = false, fail_on_timeout = false, enable_undef = false, set_def_inputs = false; bool ignore_div_by_zero = false, set_init_undef = false, set_init_zero = false, max_undef = false; bool tempinduct = false, prove_asserts = false, show_inputs = false, show_outputs = false; @@ -970,6 +973,10 @@ struct SatPass : public Pass { maxsteps = atoi(args[++argidx].c_str()); continue; } + if (args[argidx] == "-initsteps" && argidx+1 < args.size()) { + initsteps = atoi(args[++argidx].c_str()); + continue; + } if (args[argidx] == "-ignore_div_by_zero") { ignore_div_by_zero = true; continue; @@ -1240,21 +1247,29 @@ struct SatPass : public Pass { if (inductlen > 1) inductstep.force_unique_state(1, inductlen + 1); - log("\n[induction step] Solving problem with %d variables and %d clauses..\n", - inductstep.ez.numCnfVariables(), inductstep.ez.numCnfClauses()); - - if (!inductstep.solve(inductstep.ez.NOT(property))) { - if (inductstep.gotTimeout) - goto timeout; - log("Induction step proven: SUCCESS!\n"); - print_qed(); - goto tip_success; + if (inductlen < initsteps) + { + log("\n[induction step] Skipping problem with %d variables and %d clauses (below initsteps).\n", + inductstep.ez.numCnfVariables(), inductstep.ez.numCnfClauses()); + inductstep.ez.assume(property); } + else + { + log("\n[induction step] Solving problem with %d variables and %d clauses..\n", + inductstep.ez.numCnfVariables(), inductstep.ez.numCnfClauses()); + + if (!inductstep.solve(inductstep.ez.NOT(property))) { + if (inductstep.gotTimeout) + goto timeout; + log("Induction step proven: SUCCESS!\n"); + print_qed(); + goto tip_success; + } - log("Induction step failed. Incrementing induction length.\n"); - inductstep.ez.assume(property); - - inductstep.print_model(); + log("Induction step failed. Incrementing induction length.\n"); + inductstep.ez.assume(property); + inductstep.print_model(); + } } log("\nReached maximum number of time steps -> proof failed.\n"); -- cgit v1.2.3 From 32af10fa9b0fb8c86451a15f780288da13d4ab99 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 18 Feb 2014 09:28:05 +0100 Subject: Coding style corrections in SatHelper::dump_model_to_vcd() --- passes/sat/sat.cc | 62 +++++++++++++++++++++++++++---------------------------- 1 file changed, 31 insertions(+), 31 deletions(-) (limited to 'passes') diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 2dc7a16ba..3b4a394ec 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -632,27 +632,27 @@ struct SatHelper if (last_timestep == -2) log(" no model variables selected for display.\n"); } - + void dump_model_to_vcd(std::string vcd_file_name) { - FILE* f = fopen(vcd_file_name.c_str(), "w"); - if(!f) + FILE *f = fopen(vcd_file_name.c_str(), "w"); + if (!f) log_cmd_error("Can't open output file `%s' for writing: %s\n", vcd_file_name.c_str(), strerror(errno)); - + log("Dumping SAT model to VCD file %s\n", vcd_file_name.c_str()); - + time_t timestamp; struct tm* now; - char stime[128] = {0}; + char stime[128] = {}; time(×tamp); now = localtime(×tamp); strftime(stime, sizeof(stime), "%c", now); - + std::string module_fname = "unknown"; auto apos = module->attributes.find("\\src"); if(apos != module->attributes.end()) module_fname = module->attributes["\\src"].decode_string(); - + fprintf(f, "$date\n"); fprintf(f, " %s\n", stime); fprintf(f, "$end\n"); @@ -663,21 +663,22 @@ struct SatHelper fprintf(f, " Generated from SAT problem in module %s (declared at %s)\n", module->name.c_str(), module_fname.c_str()); fprintf(f, "$end\n"); - - //VCD has some limits on internal (non-display) identifier names, so make legal ones + + // VCD has some limits on internal (non-display) identifier names, so make legal ones std::map vcdnames; - - fprintf(f, "$timescale 1ns\n"); //arbitrary time scale since actual clock period is unknown/unimportant + + fprintf(f, "$timescale 1ns\n"); // arbitrary time scale since actual clock period is unknown/unimportant fprintf(f, "$scope module %s $end\n", module->name.c_str()); - for (auto &info : modelInfo) { - if(vcdnames.find(info.description) != vcdnames.end()) + for (auto &info : modelInfo) + { + if (vcdnames.find(info.description) != vcdnames.end()) continue; - + char namebuf[16]; snprintf(namebuf, sizeof(namebuf), "v%d", static_cast(vcdnames.size())); vcdnames[info.description] = namebuf; - - //Even display identifiers can't use some special characters + + // Even display identifiers can't use some special characters std::string legal_desc = info.description.c_str(); for (auto &c : legal_desc) { if(c == '$') @@ -685,21 +686,21 @@ struct SatHelper if(c == ':') c = '_'; } - + fprintf(f, "$var wire %d %s %s $end\n", info.width, namebuf, legal_desc.c_str()); - - //Need to look at first *two* cycles! - //We need to put a name on all variables but those without an initialization clause - //have no value at timestep 0 + + // Need to look at first *two* cycles! + // We need to put a name on all variables but those without an initialization clause + // have no value at timestep 0 if(info.timestep > 1) break; } fprintf(f, "$upscope $end\n"); fprintf(f, "$enddefinitions $end\n"); fprintf(f, "$dumpvars\n"); - + static const char bitvals[] = "01xzxx"; - + int last_timestep = -2; for (auto &info : modelInfo) { @@ -710,19 +711,18 @@ struct SatHelper if (enable_undef && modelValues.at(modelExpressions.size()/2 + info.offset + i)) value.bits.back() = RTLIL::State::Sx; } - - if (info.timestep != last_timestep) { + + if (info.timestep != last_timestep) { if(last_timestep == 0) fprintf(f, "$end\n"); else fprintf(f, "#%d\n", info.timestep); - last_timestep = info.timestep; } - - if(info.width == 1) + + if(info.width == 1) { fprintf(f, "%c%s\n", bitvals[value.bits[0]], vcdnames[info.description].c_str()); - else { + } else { fprintf(f, "b"); for(int k=info.width-1; k >= 0; k --) //need to flip bit ordering for VCD fprintf(f, "%c", bitvals[value.bits[k]]); @@ -732,7 +732,7 @@ struct SatHelper if (last_timestep == -2) log(" no model variables selected for display.\n"); - + fclose(f); } -- cgit v1.2.3 From a78bba1f5cf5b8c312c453e5c2c1a57b6946bebd Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 18 Feb 2014 09:29:08 +0100 Subject: Added "sat -dump_cnf" --- passes/sat/sat.cc | 39 ++++++++++++++++++++++++++++++++++----- 1 file changed, 34 insertions(+), 5 deletions(-) (limited to 'passes') diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 3b4a394ec..d18a220d3 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -878,6 +878,10 @@ struct SatPass : public Pass { log(" -dump_vcd \n"); log(" dump SAT model (counter example in proof) to VCD file\n"); log("\n"); + log(" -dump_cnf \n"); + log(" dump CNF of SAT problem (in DIMACS format). in temporal induction\n"); + log(" proofs this is the CNF of the first induction step.\n"); + log("\n"); log("The following additional options can be used to set up a proof. If also -seq\n"); log("is passed, a temporal induction proof is performed.\n"); log("\n"); @@ -933,7 +937,7 @@ struct SatPass : public Pass { bool ignore_div_by_zero = false, set_init_undef = false, set_init_zero = false, max_undef = false; bool tempinduct = false, prove_asserts = false, show_inputs = false, show_outputs = false; bool ignore_unknown_cells = false, falsify = false, tempinduct_def = false, set_init_def = false; - std::string vcd_file_name; + std::string vcd_file_name, cnf_file_name; log_header("Executing SAT pass (solving SAT problems in the circuit).\n"); @@ -1115,6 +1119,10 @@ struct SatPass : public Pass { vcd_file_name = args[++argidx]; continue; } + if (args[argidx] == "-dump_cnf" && argidx+1 < args.size()) { + cnf_file_name = args[++argidx]; + continue; + } break; } extra_args(args, argidx, design); @@ -1255,6 +1263,19 @@ struct SatPass : public Pass { } else { + if (!cnf_file_name.empty()) + { + FILE *f = fopen(cnf_file_name.c_str(), "w"); + if (!f) + log_cmd_error("Can't open output file `%s' for writing: %s\n", cnf_file_name.c_str(), strerror(errno)); + + log("Dumping CNF to file `%s'.\n", cnf_file_name.c_str()); + cnf_file_name.clear(); + + inductstep.ez.printDIMACS(f, false); + fclose(f); + } + log("\n[induction step] Solving problem with %d variables and %d clauses..\n", inductstep.ez.numCnfVariables(), inductstep.ez.numCnfClauses()); @@ -1333,10 +1354,18 @@ struct SatPass : public Pass { } sathelper.generate_model(); -#if 0 - // print CNF for debugging - sathelper.ez.printDIMACS(stdout, true); -#endif + if (!cnf_file_name.empty()) + { + FILE *f = fopen(cnf_file_name.c_str(), "w"); + if (!f) + log_cmd_error("Can't open output file `%s' for writing: %s\n", cnf_file_name.c_str(), strerror(errno)); + + log("Dumping CNF to file `%s'.\n", cnf_file_name.c_str()); + cnf_file_name.clear(); + + sathelper.ez.printDIMACS(f, false); + fclose(f); + } int rerun_counter = 0; -- cgit v1.2.3 From a71d09421d31b43b6bda6f6958373ec8a409e3c1 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 18 Feb 2014 19:23:32 +0100 Subject: Added techmap support for _TECHMAP_CONNMAP_*_ --- passes/techmap/techmap.cc | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) (limited to 'passes') diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 53164b58a..74621d3e5 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -271,6 +271,37 @@ struct TechmapWorker parameters[stringf("\\_TECHMAP_CONSTVAL_%s_", RTLIL::id2cstr(conn.first))] = RTLIL::SigSpec(v).as_const(); } } + + int unique_bit_id_counter = 0; + std::map unique_bit_id; + unique_bit_id[RTLIL::State::S0] = unique_bit_id_counter++; + unique_bit_id[RTLIL::State::S1] = unique_bit_id_counter++; + unique_bit_id[RTLIL::State::Sx] = unique_bit_id_counter++; + unique_bit_id[RTLIL::State::Sz] = unique_bit_id_counter++; + + for (auto conn : cell->connections) + if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))) != 0) { + for (auto &bit : sigmap(conn.second).to_sigbit_vector()) + if (unique_bit_id.count(bit) == 0) + unique_bit_id[bit] = unique_bit_id_counter++; + } + + int bits = 0; + for (int i = 0; i < 32; i++) + if (((unique_bit_id_counter-1) & (1 << i)) != 0) + bits = i; + if (tpl->avail_parameters.count("\\_TECHMAP_BITS_CONNMAP_")) + parameters["\\_TECHMAP_BITS_CONNMAP_"] = bits; + + for (auto conn : cell->connections) + if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))) != 0) { + RTLIL::Const value; + for (auto &bit : sigmap(conn.second).to_sigbit_vector()) { + RTLIL::Const chunk(unique_bit_id.at(bit), bits); + value.bits.insert(value.bits.end(), chunk.bits.begin(), chunk.bits.end()); + } + parameters[stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))] = value; + } } std::pair> key(tpl_name, parameters); @@ -468,6 +499,14 @@ struct TechmapPass : public Pass { log(" former has a 1-bit for each constant input bit and the latter has the\n"); log(" value for this bit. The unused bits of the latter are set to undef (x).\n"); log("\n"); + log(" _TECHMAP_BITS_CONNMAP_\n"); + log(" _TECHMAP_CONNMAP__\n"); + log(" For an N-bit port, the _TECHMAP_CONNMAP__ parameter, if it\n"); + log(" exists, will be set to an N*_TECHMAP_BITS_CONNMAP_ bit vector containing\n"); + log(" N words (of _TECHMAP_BITS_CONNMAP_ bits each) that assign each single\n"); + log(" bit driver a unique id. The values 0-3 are reserved for 0, 1, x, and z.\n"); + log(" This can be used to detect shorted inputs.\n"); + log("\n"); log("When a module in the map file has a parameter where the according cell in the\n"); log("design has a port, the module from the map file is only used if the port in\n"); log("the design is connected to a constant value. The parameter is then set to the\n"); -- cgit v1.2.3 From 0dadfed46d938282d7651c9a817f33b1d87397c7 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 20 Feb 2014 20:44:11 +0100 Subject: Added connwrappers command --- passes/cmds/Makefile.inc | 1 + passes/cmds/connwrappers.cc | 205 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 206 insertions(+) create mode 100644 passes/cmds/connwrappers.cc (limited to 'passes') diff --git a/passes/cmds/Makefile.inc b/passes/cmds/Makefile.inc index f01a1c4b5..77cac2b45 100644 --- a/passes/cmds/Makefile.inc +++ b/passes/cmds/Makefile.inc @@ -15,4 +15,5 @@ OBJS += passes/cmds/copy.o OBJS += passes/cmds/splice.o OBJS += passes/cmds/scc.o OBJS += passes/cmds/log.o +OBJS += passes/cmds/connwrappers.o diff --git a/passes/cmds/connwrappers.cc b/passes/cmds/connwrappers.cc new file mode 100644 index 000000000..dd8b4fede --- /dev/null +++ b/passes/cmds/connwrappers.cc @@ -0,0 +1,205 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/register.h" +#include "kernel/sigtools.h" +#include "kernel/rtlil.h" +#include "kernel/log.h" + +struct ConnwrappersWorker +{ + struct portdecl_t { + // key: celltype, portname; + std::string widthparam, signparam; + bool is_signed; + }; + + std::set decl_celltypes; + std::map, portdecl_t> decls; + + void add_port(std::string celltype, std::string portname, std::string widthparam, std::string signparam) + { + std::pair key(RTLIL::escape_id(celltype), RTLIL::escape_id(portname)); + decl_celltypes.insert(key.first); + + if (decls.count(key)) + log_cmd_error("Duplicate port decl: %s %s\n", celltype.c_str(), portname.c_str()); + + portdecl_t decl; + decl.widthparam = RTLIL::escape_id(widthparam); + decl.signparam = RTLIL::escape_id(signparam); + decl.is_signed = false; + decls[key] = decl; + } + + void add_port(std::string celltype, std::string portname, std::string widthparam, bool is_signed) + { + std::pair key(RTLIL::escape_id(celltype), RTLIL::escape_id(portname)); + decl_celltypes.insert(key.first); + + if (decls.count(key)) + log_cmd_error("Duplicate port decl: %s %s\n", celltype.c_str(), portname.c_str()); + + portdecl_t decl; + decl.widthparam = RTLIL::escape_id(widthparam); + decl.is_signed = is_signed; + decls[key] = decl; + } + + void work(RTLIL::Design *design, RTLIL::Module *module) + { + std::map> extend_map; + SigMap sigmap(module); + + for (auto &it : module->cells) + { + RTLIL::Cell *cell = it.second; + + if (!decl_celltypes.count(cell->type)) + continue; + + for (auto &conn : cell->connections) + { + std::pair key(cell->type, conn.first); + + if (!decls.count(key)) + continue; + + portdecl_t &decl = decls.at(key); + + if (!cell->parameters.count(decl.widthparam)) + continue; + + if (!decl.signparam.empty() && !cell->parameters.count(decl.signparam)) + continue; + + int inner_width = cell->parameters.at(decl.widthparam).as_int(); + int outer_width = conn.second.width; + bool is_signed = decl.signparam.empty() ? decl.is_signed : cell->parameters.at(decl.signparam).as_bool(); + + if (inner_width >= outer_width) + continue; + + RTLIL::SigSpec sig = sigmap(conn.second); + extend_map[sig.extract(inner_width - 1, 1)] = std::pair(is_signed, + sig.extract(inner_width, outer_width - inner_width)); + } + } + + for (auto &it : module->cells) + { + RTLIL::Cell *cell = it.second; + + if (!design->selected(module, cell)) + continue; + + for (auto &conn : cell->connections) + { + std::vector sigbits = sigmap(conn.second).to_sigbit_vector(); + RTLIL::SigSpec old_sig; + + for (size_t i = 0; i < sigbits.size(); i++) + { + if (!extend_map.count(sigbits[i])) + continue; + + bool is_signed = extend_map.at(sigbits[i]).first; + RTLIL::SigSpec extend_sig = extend_map.at(sigbits[i]).second; + + int extend_width = 0; + RTLIL::SigBit extend_bit = is_signed ? sigbits[i] : RTLIL::SigBit(RTLIL::State::S0); + while (extend_width < extend_sig.width && i + extend_width + 1 < sigbits.size() && + sigbits[i + extend_width + 1] == extend_bit) extend_width++; + + if (extend_width == 0) + continue; + + if (old_sig.width == 0) + old_sig = conn.second; + + conn.second.replace(i+1, extend_sig.extract(0, extend_width)); + i += extend_width; + } + + if (old_sig.width) + log("Connected extended bits of %s.%s:%s: %s -> %s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), + RTLIL::id2cstr(conn.first), log_signal(old_sig), log_signal(conn.second)); + } + } + } +}; + +struct ConnwrappersPass : public Pass { + ConnwrappersPass() : Pass("connwrappers", "replace undef values with defined constants") { } + virtual void help() + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" connwrappers [options] [selection]\n"); + log("\n"); + log("Wrappers are used in coarse-grain synthesis to wrap cells with smaller ports\n"); + log("in wrapper cells with a (larger) constant port size. I.e. the upper bits\n"); + log("of the wrapper outut are signed/unsigned bit extended. This command uses this\n"); + log("knowlege to rewire the inputs of the driven cells to match the output of\n"); + log("the driving cell.\n"); + log("\n"); + log(" -signed \n"); + log(" -unsigned \n"); + log(" consider the specified signed/unsigned wrapper output\n"); + log("\n"); + log(" -port \n"); + log(" use the specified parameter to decide if signed or unsigned\n"); + log("\n"); + log("The options -signed, -unsigned, and -port can be specified multiple times.\n"); + log("\n"); + } + virtual void execute(std::vector args, RTLIL::Design *design) + { + ConnwrappersWorker worker; + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) + { + if (args[argidx] == "-signed" && argidx+3 < args.size()) { + worker.add_port(args[argidx+1], args[argidx+2], args[argidx+3], true); + argidx += 3; + continue; + } + if (args[argidx] == "-unsigned" && argidx+3 < args.size()) { + worker.add_port(args[argidx+1], args[argidx+2], args[argidx+3], false); + argidx += 3; + continue; + } + if (args[argidx] == "-port" && argidx+4 < args.size()) { + worker.add_port(args[argidx+1], args[argidx+2], args[argidx+3], args[argidx+4]); + argidx += 4; + continue; + } + break; + } + extra_args(args, argidx, design); + + log_header("Executing CONNWRAPPERS pass (connect extended ports of wrapper cells).\n"); + + for (auto &mod_it : design->modules) + if (design->selected(mod_it.second)) + worker.work(design, mod_it.second); + } +} ConnwrappersPass; + -- cgit v1.2.3 From 483c99fe46d6b1cd35abddd38a629d30e13289b4 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 20 Feb 2014 23:28:59 +0100 Subject: Added "design -push" and "design -pop" --- passes/cmds/design.cc | 53 +++++++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 45 insertions(+), 8 deletions(-) (limited to 'passes') diff --git a/passes/cmds/design.cc b/passes/cmds/design.cc index 80a6c0731..7b8889d60 100644 --- a/passes/cmds/design.cc +++ b/passes/cmds/design.cc @@ -22,13 +22,18 @@ #include "kernel/rtlil.h" #include "kernel/log.h" +std::map saved_designs; +std::vector pushed_designs; + struct DesignPass : public Pass { DesignPass() : Pass("design", "save, restore and reset current design") { } - std::map saved_designs; virtual ~DesignPass() { for (auto &it : saved_designs) delete it.second; saved_designs.clear(); + for (auto &it : pushed_designs) + delete it; + pushed_designs.clear(); } virtual void help() { @@ -49,6 +54,16 @@ struct DesignPass : public Pass { log("Save the current design under the given name and then clear the current design.\n"); log("\n"); log("\n"); + log(" design -push\n"); + log("\n"); + log("Push the current design to the stack and then clear the current design.\n"); + log("\n"); + log("\n"); + log(" design -pop\n"); + log("\n"); + log("Reset the current design and pop the last design from the stack.\n"); + log("\n"); + log("\n"); log(" design -load \n"); log("\n"); log("Reset the current design and load the design previously saved under the given\n"); @@ -70,6 +85,8 @@ struct DesignPass : public Pass { { bool got_mode = false; bool reset_mode = false; + bool push_mode = false; + bool pop_mode = false; RTLIL::Design *copy_from_design = NULL, *copy_to_design = NULL; std::string save_name, load_name, as_name; std::vector copy_src_modules; @@ -83,6 +100,16 @@ struct DesignPass : public Pass { reset_mode = true; continue; } + if (!got_mode && args[argidx] == "-push") { + got_mode = true; + push_mode = true; + continue; + } + if (!got_mode && args[argidx] == "-pop") { + got_mode = true; + pop_mode = true; + continue; + } if (!got_mode && args[argidx] == "-save" && argidx+1 < args.size()) { got_mode = true; save_name = args[++argidx]; @@ -151,7 +178,10 @@ struct DesignPass : public Pass { extra_args(args, argidx, design, false); if (!got_mode) - cmd_error(args, argidx, "Missing mode argument (-reset, -save, -load, -copy-from, or -copy-to)."); + cmd_error(args, argidx, "Missing mode argument."); + + if (pop_mode && pushed_designs.empty()) + log_cmd_error("No pushed designs.\n"); if (copy_to_design != NULL) { @@ -169,7 +199,7 @@ struct DesignPass : public Pass { } } - if (!save_name.empty()) + if (!save_name.empty() || push_mode) { RTLIL::Design *design_copy = new RTLIL::Design; @@ -182,10 +212,14 @@ struct DesignPass : public Pass { if (saved_designs.count(save_name)) delete saved_designs.at(save_name); - saved_designs[save_name] = design_copy; + + if (push_mode) + pushed_designs.push_back(design_copy); + else + saved_designs[save_name] = design_copy; } - if (reset_mode || !load_name.empty()) + if (reset_mode || !load_name.empty() || push_mode || pop_mode) { for (auto &it : design->modules) delete it.second; @@ -198,9 +232,12 @@ struct DesignPass : public Pass { design->selection_stack.push_back(RTLIL::Selection()); } - if (!load_name.empty()) + if (!load_name.empty() || pop_mode) { - RTLIL::Design *saved_design = saved_designs.at(load_name); + RTLIL::Design *saved_design = pop_mode ? pushed_designs.back() : saved_designs.at(load_name); + + if (pop_mode) + pushed_designs.pop_back(); for (auto &it : saved_design->modules) design->modules[it.first] = it.second->clone(); @@ -211,4 +248,4 @@ struct DesignPass : public Pass { } } } DesignPass; - + -- cgit v1.2.3 From 236fc4209c17bf96b37e6f8a29a8aa3f24d5df45 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 20 Feb 2014 23:30:15 +0100 Subject: Added "extract -map %" --- passes/techmap/extract.cc | 40 ++++++++++++++++++++++++++++++---------- 1 file changed, 30 insertions(+), 10 deletions(-) (limited to 'passes') diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index eff14ff01..06b0df2de 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -315,6 +315,10 @@ struct ExtractPass : public Pass { log(" use the modules in this file as reference. This option can be used\n"); log(" multiple times.\n"); log("\n"); + log(" -map %%\n"); + log(" use the modules in this in-memory design as reference. This option can\n"); + log(" be used multiple times.\n"); + log("\n"); log(" -verbose\n"); log(" print debug output while analyzing\n"); log("\n"); @@ -524,16 +528,32 @@ struct ExtractPass : public Pass { if (!mine_mode) { map = new RTLIL::Design; - for (auto &filename : map_filenames) { - FILE *f = fopen(filename.c_str(), "rt"); - if (f == NULL) - log_cmd_error("Can't open map file `%s'.\n", filename.c_str()); - Frontend::frontend_call(map, f, filename, (filename.size() > 3 && filename.substr(filename.size()-3) == ".il") ? "ilang" : "verilog"); - fclose(f); - - if (filename.size() <= 3 || filename.substr(filename.size()-3) != ".il") { - Pass::call(map, "proc"); - Pass::call(map, "opt_clean"); + for (auto &filename : map_filenames) + { + if (filename.substr(0, 1) == "%") + { + if (!saved_designs.count(filename.substr(1))) { + delete map; + log_cmd_error("Can't saved design `%s'.\n", filename.c_str()+1); + } + for (auto &it : saved_designs.at(filename.substr(1))->modules) + if (!map->modules.count(it.first)) + map->modules[it.first] = it.second->clone(); + } + else + { + FILE *f = fopen(filename.c_str(), "rt"); + if (f == NULL) { + delete map; + log_cmd_error("Can't open map file `%s'.\n", filename.c_str()); + } + Frontend::frontend_call(map, f, filename, (filename.size() > 3 && filename.substr(filename.size()-3) == ".il") ? "ilang" : "verilog"); + fclose(f); + + if (filename.size() <= 3 || filename.substr(filename.size()-3) != ".il") { + Pass::call(map, "proc"); + Pass::call(map, "opt_clean"); + } } } } -- cgit v1.2.3 From 737b71c73576d67b707119805cb599644a43777d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 20 Feb 2014 23:31:13 +0100 Subject: Added "extract -ignore_parameters" and "extract -ignore_param ..." --- passes/techmap/extract.cc | 79 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) (limited to 'passes') diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index 06b0df2de..d2193c7b1 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -34,8 +34,14 @@ namespace class SubCircuitSolver : public SubCircuit::Solver { public: + bool ignore_parameters; + std::set> ignored_parameters; std::set cell_attr, wire_attr; + SubCircuitSolver() : ignore_parameters(false) + { + } + bool compareAttributes(const std::set &attr, const std::map &needleAttr, const std::map &haystackAttr) { for (auto &it : attr) { @@ -46,12 +52,70 @@ namespace return true; } + RTLIL::Const unified_param(RTLIL::IdString cell_type, RTLIL::IdString param, RTLIL::Const value) + { + if (cell_type.substr(0, 1) != "$" || cell_type.substr(0, 2) == "$_") + return value; + + #define param_bool(_n) if (param == _n) return value.as_bool(); + param_bool("\\ARST_POLARITY"); + param_bool("\\A_SIGNED"); + param_bool("\\B_SIGNED"); + param_bool("\\CLK_ENABLE"); + param_bool("\\CLK_POLARITY"); + param_bool("\\CLR_POLARITY"); + param_bool("\\EN_POLARITY"); + param_bool("\\SET_POLARITY"); + param_bool("\\TRANSPARENT"); + #undef param_bool + + #define param_int(_n) if (param == _n) return value.as_int(); + param_int("\\ABITS") + param_int("\\A_WIDTH") + param_int("\\B_WIDTH") + param_int("\\CTRL_IN_WIDTH") + param_int("\\CTRL_OUT_WIDTH") + param_int("\\OFFSET") + param_int("\\PRIORITY") + param_int("\\RD_PORTS") + param_int("\\SIZE") + param_int("\\STATE_BITS") + param_int("\\STATE_NUM") + param_int("\\STATE_NUM_LOG2") + param_int("\\STATE_RST") + param_int("\\S_WIDTH") + param_int("\\TRANS_NUM") + param_int("\\WIDTH") + param_int("\\WR_PORTS") + param_int("\\Y_WIDTH") + #undef param_int + + return value; + } + virtual bool userCompareNodes(const std::string &, const std::string &, void *needleUserData, const std::string &, const std::string &, void *haystackUserData, const std::map &portMapping) { RTLIL::Cell *needleCell = (RTLIL::Cell*) needleUserData; RTLIL::Cell *haystackCell = (RTLIL::Cell*) haystackUserData; + if (!needleCell || !haystackCell) { + assert(!needleCell && !haystackCell); + return true; + } + + if (!ignore_parameters) { + std::map needle_param, haystack_param; + for (auto &it : needleCell->parameters) + if (!ignored_parameters.count(std::pair(needleCell->type, it.first))) + needle_param[it.first] = unified_param(needleCell->type, it.first, it.second); + for (auto &it : haystackCell->parameters) + if (!ignored_parameters.count(std::pair(haystackCell->type, it.first))) + haystack_param[it.first] = unified_param(haystackCell->type, it.first, it.second); + if (needle_param != haystack_param) + return false; + } + if (cell_attr.size() > 0 && !compareAttributes(cell_attr, needleCell->attributes, haystackCell->attributes)) return false; @@ -351,6 +415,12 @@ struct ExtractPass : public Pass { log(" -wire_attr \n"); log(" Attributes on wires with the given name must match.\n"); log("\n"); + log(" -ignore_parameters\n"); + log(" Do not use parameters when matching cells.\n"); + log("\n"); + log(" -ignore_param \n"); + log(" Do not use this parameter when matching cells.\n"); + log("\n"); log("This pass does not operate on modules with uprocessed processes in it.\n"); log("(I.e. the 'proc' pass should be used first to convert processes to netlists.)\n"); log("\n"); @@ -498,6 +568,15 @@ struct ExtractPass : public Pass { solver.wire_attr.insert(RTLIL::escape_id(args[++argidx])); continue; } + if (args[argidx] == "-ignore_parameters") { + solver.ignore_parameters = true; + continue; + } + if (args[argidx] == "-ignore_param" && argidx+2 < args.size()) { + solver.ignored_parameters.insert(std::pair(RTLIL::escape_id(args[argidx+1]), RTLIL::escape_id(args[argidx+2]))); + argidx += 2; + continue; + } break; } extra_args(args, argidx, design); -- cgit v1.2.3 From 4e43cb731701679e6d584ba14163befcb846e87b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 20 Feb 2014 23:42:07 +0100 Subject: Added _TECHMAP_REPLACE_ feature to techmap --- passes/techmap/techmap.cc | 25 +++++++++++++++++++++---- 1 file changed, 21 insertions(+), 4 deletions(-) (limited to 'passes') diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 74621d3e5..f163c024e 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -108,6 +108,18 @@ struct TechmapWorker if (tpl->processes.size() != 0) log_error("Technology map yielded processes -> this is not supported.\n"); + // erase from namespace first for _TECHMAP_REPLACE_ to work + module->cells.erase(cell->name); + std::string orig_cell_name; + + if (!flatten_mode) + for (auto &it : tpl->cells) + if (it.first == "\\_TECHMAP_REPLACE_") { + orig_cell_name = cell->name; + cell->name = stringf("$techmap%d", RTLIL::autoidx++) + cell->name; + break; + } + std::map positional_ports; for (auto &it : tpl->wires) { @@ -120,7 +132,7 @@ struct TechmapWorker w->port_id = 0; if (it.second->get_bool_attribute("\\_techmap_special_")) w->attributes.clear(); - module->wires[w->name] = w; + module->add(w); design->select(module, w); } @@ -169,12 +181,15 @@ struct TechmapWorker RTLIL::Cell *c = new RTLIL::Cell(*it.second); if (!flatten_mode && c->type.substr(0, 2) == "\\$") c->type = c->type.substr(1); - apply_prefix(cell->name, c->name); + if (!flatten_mode && c->name == "\\_TECHMAP_REPLACE_") + c->name = orig_cell_name; + else + apply_prefix(cell->name, c->name); for (auto &it2 : c->connections) { apply_prefix(cell->name, it2.second, module); port_signal_map.apply(it2.second); } - module->cells[c->name] = c; + module->add(c); design->select(module, c); } @@ -187,7 +202,6 @@ struct TechmapWorker module->connections.push_back(c); } - module->cells.erase(cell->name); delete cell; } @@ -512,6 +526,9 @@ struct TechmapPass : public Pass { log("the design is connected to a constant value. The parameter is then set to the\n"); log("constant value.\n"); log("\n"); + log("A cell with the name _TECHMAP_REPLACE_ in the map file will inherit the name\n"); + log("of the cell that is beeing replaced.\n"); + log("\n"); log("See 'help extract' for a pass that does the opposite thing.\n"); log("\n"); log("See 'help flatten' for a pass that does flatten the design (which is\n"); -- cgit v1.2.3 From 8b508dc90b87c99e13f1fa9f8e79e48c7fa52e90 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 21 Feb 2014 23:34:45 +0100 Subject: Added workaround for vhdl-style edge triggers from vhdl2verilog to proc_arst --- passes/proc/proc_arst.cc | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'passes') diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc index 571946573..057378e7c 100644 --- a/passes/proc/proc_arst.cc +++ b/passes/proc/proc_arst.cc @@ -156,8 +156,12 @@ restart_proc_arst: if (sync->type == RTLIL::SyncType::STp || sync->type == RTLIL::SyncType::STn) { bool polarity = sync->type == RTLIL::SyncType::STp; if (check_signal(mod, root_sig, sync->signal, polarity)) { - log("Found async reset %s in `%s.%s'.\n", log_signal(sync->signal), mod->name.c_str(), proc->name.c_str()); - sync->type = sync->type == RTLIL::SyncType::STp ? RTLIL::SyncType::ST1 : RTLIL::SyncType::ST0; + if (proc->syncs.size() == 1) { + log("Found VHDL-style edge-trigger %s in `%s.%s'.\n", log_signal(sync->signal), mod->name.c_str(), proc->name.c_str()); + } else { + log("Found async reset %s in `%s.%s'.\n", log_signal(sync->signal), mod->name.c_str(), proc->name.c_str()); + sync->type = sync->type == RTLIL::SyncType::STp ? RTLIL::SyncType::ST1 : RTLIL::SyncType::ST0; + } for (auto &action : sync->actions) { RTLIL::SigSpec rspec = action.second; RTLIL::SigSpec rval = RTLIL::SigSpec(RTLIL::State::Sm, rspec.width); -- cgit v1.2.3 From 548519875bbffda02c5c7a891ce67fd3738d6e6f Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 22 Feb 2014 17:07:22 +0100 Subject: Fixed bug (typo) in passes/opt/opt_const.cc --- passes/opt/opt_const.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index f611d7211..ad9a71b15 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -342,7 +342,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons cell->parameters.erase("\\WIDTH"); cell->type = "$or"; } else - cell->type = "$_or_"; + cell->type = "$_OR_"; OPT_DID_SOMETHING = true; did_something = true; goto next_cell; -- cgit v1.2.3 From 9e9998433616f438cb0185519bb5b7f8e1a8f543 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 27 Feb 2014 04:09:32 +0100 Subject: Fixed const folding of $bu0 cells --- passes/opt/opt_const.cc | 1 + 1 file changed, 1 insertion(+) (limited to 'passes') diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index ad9a71b15..da71ec30e 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -463,6 +463,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons FOLD_2ARG_CELL(pow) FOLD_1ARG_CELL(pos) + FOLD_1ARG_CELL(bu0) FOLD_1ARG_CELL(neg) // be very conservative with optimizing $mux cells as we do not want to break mux trees -- cgit v1.2.3 From 96e753041dbd0abc86ff0a6404f13d29edcb985d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 3 Mar 2014 02:14:27 +0100 Subject: fixed freduce for Minisat::SimpSolver: use frozen_literal() --- passes/sat/freduce.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'passes') diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index 81250b000..746523f82 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -112,13 +112,13 @@ struct FindReducedInputs size_t idx_bits = get_bits(idx); if (sat_pi_uniq_bitvec.size() != idx_bits) { - sat_pi_uniq_bitvec.push_back(ez.literal(stringf("uniq_%d", int(idx_bits)-1))); + sat_pi_uniq_bitvec.push_back(ez.frozen_literal(stringf("uniq_%d", int(idx_bits)-1))); for (auto &it : sat_pi) ez.assume(ez.OR(ez.NOT(it.second), ez.NOT(sat_pi_uniq_bitvec.back()))); } log_assert(sat_pi_uniq_bitvec.size() == idx_bits); - sat_pi[bit] = ez.literal(stringf("pi_%s", log_signal(bit))); + sat_pi[bit] = ez.frozen_literal(stringf("p, falsei_%s", log_signal(bit))); ez.assume(ez.IFF(ez.XOR(sat_a, sat_b), sat_pi[bit])); for (size_t i = 0; i < idx_bits; i++) -- cgit v1.2.3 From 1ecaf1bb767834dc6a763549b63d9d4653c342d1 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 6 Mar 2014 12:15:17 +0100 Subject: Added techmap -max_iter option --- passes/techmap/techmap.cc | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'passes') diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index f163c024e..937f41315 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -464,6 +464,9 @@ struct TechmapPass : public Pass { log(" yosys data files are). this is mainly used internally when techmap\n"); log(" is called from other commands.\n"); log("\n"); + log(" -max_iter \n"); + log(" only run the specified number of iterations.\n"); + log("\n"); log(" -D , -I \n"); log(" this options are passed as-is to the verilog frontend for loading the\n"); log(" map file. Note that the verilog frontend is also called with the\n"); @@ -542,6 +545,7 @@ struct TechmapPass : public Pass { std::vector map_files; std::string verilog_frontend = "verilog -ignore_redef"; + int max_iter = -1; size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { @@ -553,6 +557,10 @@ struct TechmapPass : public Pass { map_files.push_back(get_share_file_name(args[++argidx])); continue; } + if (args[argidx] == "-max_iter" && argidx+1 < args.size()) { + max_iter = atoi(args[++argidx].c_str()); + continue; + } if (args[argidx] == "-D" && argidx+1 < args.size()) { verilog_frontend += " -D " + args[++argidx]; continue; @@ -610,6 +618,8 @@ struct TechmapPass : public Pass { did_something = true; if (did_something) design->check(); + if (max_iter > 0 && --max_iter == 0) + break; } log("No more expansions possible.\n"); -- cgit v1.2.3 From 9b9c3327ccf3a8e69f9af57333839f470df0ce66 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 6 Mar 2014 14:18:34 +0100 Subject: Fixed undef handling in opt_reduce --- passes/opt/opt_reduce.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'passes') diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc index dd1299810..fee8fb71b 100644 --- a/passes/opt/opt_reduce.cc +++ b/passes/opt/opt_reduce.cc @@ -65,8 +65,8 @@ struct OptReduceWorker continue; } if (chunk.wire == NULL) { - new_sig_a = RTLIL::SigSpec(RTLIL::State::Sx); - break; + new_sig_a.append(chunk); + continue; } bool imported_children = false; -- cgit v1.2.3 From da5859a6744943469d5165724fa79ce243e5d8e3 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 6 Mar 2014 18:14:26 +0100 Subject: Added freduce -stop --- passes/sat/freduce.cc | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) (limited to 'passes') diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index 746523f82..8d7ce5aaf 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -31,7 +31,7 @@ namespace { bool inv_mode; -int verbose_level; +int verbose_level, reduce_counter, reduce_stop_at; typedef std::map>> drivers_t; struct equiv_bit_t @@ -648,7 +648,7 @@ struct FreduceWorker int rewired_sigbits = 0; for (auto &grp : equiv) { - log(" Using as master for group: %s\n", log_signal(grp.front().bit)); + log(" [%d] Using as master for group: %s\n", ++reduce_counter, log_signal(grp.front().bit)); RTLIL::SigSpec inv_sig; for (size_t i = 1; i < grp.size(); i++) @@ -692,6 +692,11 @@ struct FreduceWorker rewired_sigbits++; } + + if (reduce_counter == reduce_stop_at) { + log(" Reached limit passed using -stop option. Skipping all further reductions.\n"); + break; + } } log(" Rewired a total of %d signal bits in module %s.\n", rewired_sigbits, RTLIL::id2cstr(module->name)); @@ -711,7 +716,7 @@ struct FreducePass : public Pass { log("\n"); log("This pass performs functional reduction in the circuit. I.e. if two nodes are\n"); log("equivialent, they are merged to one node and one of the redundant drivers is\n"); - log("unconnected. A subsequent call to 'clean' will remove the redundant drivers.\n"); + log("disconnected. A subsequent call to 'clean' will remove the redundant drivers.\n"); log("\n"); log(" -v, -vv\n"); log(" enable verbose or very verbose output\n"); @@ -719,6 +724,10 @@ struct FreducePass : public Pass { log(" -inv\n"); log(" enable explicit handling of inverted signals\n"); log("\n"); + log(" -stop \n"); + log(" stop after reduction operations. this is mostly used for\n"); + log(" debugging the freduce command itself.\n"); + log("\n"); log("This pass is undef-aware, i.e. it considers don't-care values for detecting\n"); log("equivialent nodes.\n"); log("\n"); @@ -728,6 +737,8 @@ struct FreducePass : public Pass { } virtual void execute(std::vector args, RTLIL::Design *design) { + reduce_counter = 0; + reduce_stop_at = 0; verbose_level = 0; inv_mode = false; @@ -747,6 +758,10 @@ struct FreducePass : public Pass { inv_mode = true; continue; } + if (args[argidx] == "-stop" && argidx+1 < args.size()) { + reduce_stop_at = atoi(args[++argidx].c_str()); + continue; + } break; } extra_args(args, argidx, design); -- cgit v1.2.3 From 54d74cf6165ebefc2cf7aee4fab43566362eedb1 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 6 Mar 2014 22:06:58 +0100 Subject: Added freduce -dump --- passes/sat/freduce.cc | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index 8d7ce5aaf..22af13454 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -33,6 +33,7 @@ namespace { bool inv_mode; int verbose_level, reduce_counter, reduce_stop_at; typedef std::map>> drivers_t; +std::string dump_prefix; struct equiv_bit_t { @@ -559,6 +560,13 @@ struct FreduceWorker { } + void dump() + { + std::string filename = stringf("%s_%s_%05d.il", dump_prefix.c_str(), RTLIL::id2cstr(module->name), reduce_counter); + log("%s Writing dump file `%s'.\n", reduce_counter ? " " : "", filename.c_str()); + Pass::call(design, stringf("dump -outfile %s %s", filename.c_str(), design->selected_active_module.empty() ? module->name.c_str() : "")); + } + int run() { log("Running functional reduction on module %s:\n", RTLIL::id2cstr(module->name)); @@ -644,11 +652,14 @@ struct FreduceWorker std::map bitusage; module->rewrite_sigspecs(CountBitUsage(sigmap, bitusage)); + if (!dump_prefix.empty()) + dump(); + log(" Rewiring %d equivialent groups:\n", int(equiv.size())); int rewired_sigbits = 0; for (auto &grp : equiv) { - log(" [%d] Using as master for group: %s\n", ++reduce_counter, log_signal(grp.front().bit)); + log(" [%05d] Using as master for group: %s\n", ++reduce_counter, log_signal(grp.front().bit)); RTLIL::SigSpec inv_sig; for (size_t i = 1; i < grp.size(); i++) @@ -693,6 +704,9 @@ struct FreduceWorker rewired_sigbits++; } + if (!dump_prefix.empty()) + dump(); + if (reduce_counter == reduce_stop_at) { log(" Reached limit passed using -stop option. Skipping all further reductions.\n"); break; @@ -728,6 +742,10 @@ struct FreducePass : public Pass { log(" stop after reduction operations. this is mostly used for\n"); log(" debugging the freduce command itself.\n"); log("\n"); + log(" -dump \n"); + log(" dump the design to __.il after each reduction\n"); + log(" operation. this is mostly used for debugging the freduce command.\n"); + log("\n"); log("This pass is undef-aware, i.e. it considers don't-care values for detecting\n"); log("equivialent nodes.\n"); log("\n"); @@ -741,6 +759,7 @@ struct FreducePass : public Pass { reduce_stop_at = 0; verbose_level = 0; inv_mode = false; + dump_prefix = std::string(); log_header("Executing FREDUCE pass (perform functional reduction).\n"); @@ -762,6 +781,10 @@ struct FreducePass : public Pass { reduce_stop_at = atoi(args[++argidx].c_str()); continue; } + if (args[argidx] == "-dump" && argidx+1 < args.size()) { + dump_prefix = args[++argidx]; + continue; + } break; } extra_args(args, argidx, design); -- cgit v1.2.3 From 6f8865d81ab6392bdd1413f0ae6f5a5774524d28 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 7 Mar 2014 18:29:04 +0100 Subject: Some minor code cleanups in freduce command --- passes/sat/freduce.cc | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'passes') diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index 22af13454..eb94cad28 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -244,7 +244,6 @@ struct PerformReduction return 0; if (sigdepth.count(out) != 0) return sigdepth.at(out); - sigdepth[out] = 0; if (drivers.count(out) != 0) { std::pair> &drv = drivers.at(out); @@ -253,17 +252,18 @@ struct PerformReduction log_error("Can't create SAT model for cell %s (%s)!\n", RTLIL::id2cstr(drv.first->name), RTLIL::id2cstr(drv.first->type)); celldone.insert(drv.first); } - int max_child_dept = 0; + int max_child_depth = 0; for (auto &bit : drv.second) - max_child_dept = std::max(register_cone_worker(celldone, sigdepth, bit), max_child_dept); - sigdepth[out] = max_child_dept + 1; + max_child_depth = std::max(register_cone_worker(celldone, sigdepth, bit), max_child_depth); + sigdepth[out] = max_child_depth + 1; } else { pi_bits.push_back(out); sat_pi.push_back(satgen.importSigSpec(out).front()); ez.assume(ez.NOT(satgen.importUndefSigSpec(out).front())); + sigdepth[out] = 0; } - return sigdepth[out]; + return sigdepth.at(out); } PerformReduction(SigMap &sigmap, drivers_t &drivers, std::set> &inv_pairs, std::vector &bits, int cone_size) : -- cgit v1.2.3 From e3b11ea2d64724102070f96e667c4dea07c0c3e5 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 7 Mar 2014 18:44:23 +0100 Subject: Fixed bug in freduce command --- passes/sat/freduce.cc | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) (limited to 'passes') diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index eb94cad28..d4b7b5c10 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -560,6 +560,31 @@ struct FreduceWorker { } + bool find_bit_in_cone(std::set &celldone, RTLIL::SigBit needle, RTLIL::SigBit haystack) + { + if (needle == haystack) + return true; + if (haystack.wire == NULL || needle.wire == NULL || drivers.count(haystack) == 0) + return false; + + std::pair> &drv = drivers.at(haystack); + + if (celldone.count(drv.first)) + return false; + celldone.insert(drv.first); + + for (auto &bit : drv.second) + if (find_bit_in_cone(celldone, needle, bit)) + return true; + return false; + } + + bool find_bit_in_cone(RTLIL::SigBit needle, RTLIL::SigBit haystack) + { + std::set celldone; + return find_bit_in_cone(celldone, needle, haystack); + } + void dump() { std::string filename = stringf("%s_%s_%05d.il", dump_prefix.c_str(), RTLIL::id2cstr(module->name), reduce_counter); @@ -674,6 +699,11 @@ struct FreduceWorker continue; } + if (find_bit_in_cone(grp[i].bit, grp.front().bit)) { + log(" Skipping dependency of master: %s\n", log_signal(grp[i].bit)); + continue; + } + log(" Connect slave%s: %s\n", grp[i].inverted ? " using inverter" : "", log_signal(grp[i].bit)); RTLIL::Cell *drv = drivers.at(grp[i].bit).first; -- cgit v1.2.3 From 22aabe05c9dcb7a7f5c16988fc98a43e55b52beb Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 9 Mar 2014 15:15:38 +0100 Subject: Verbose reading of liberty and constr files in ABC pass --- passes/abc/abc.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'passes') diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index bd0d983ac..2829e660f 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -625,10 +625,10 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std std::string buffer; if (!liberty_file.empty()) { - buffer += stringf("%s -s -c 'read_blif %s/input.blif; read_lib %s; ", + buffer += stringf("%s -s -c 'read_blif %s/input.blif; read_lib -w %s; ", exe_file.c_str(), tempdir_name, liberty_file.c_str()); if (!constr_file.empty()) - buffer += stringf("read_constr %s; ", constr_file.c_str()); + buffer += stringf("read_constr -v %s; ", constr_file.c_str()); buffer += abc_command + "; "; } else if (lut_mode) -- cgit v1.2.3 From fcae92868de81de87079c1415d3d0123dce8d84c Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 9 Mar 2014 15:16:07 +0100 Subject: Fixed dumping of timing() { .. } block in libparse --- passes/techmap/libparse.cc | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'passes') diff --git a/passes/techmap/libparse.cc b/passes/techmap/libparse.cc index 8cbb8e2be..2ff551537 100644 --- a/passes/techmap/libparse.cc +++ b/passes/techmap/libparse.cc @@ -63,9 +63,10 @@ void LibertyAst::dump(FILE *f, std::string indent, std::string path, bool path_o } fprintf(f, "%s%s", indent.c_str(), id.c_str()); - if (!args.empty()) { + if (!args.empty() || !children.empty()) { + fprintf(f, "("); for (size_t i = 0; i < args.size(); i++) - fprintf(f, "%s%s", i > 0 ? ", " : "(", args[i].c_str()); + fprintf(f, "%s%s", i > 0 ? ", " : "", args[i].c_str()); fprintf(f, ")"); } if (!value.empty()) -- cgit v1.2.3 From fa75c8286e066ba4b73da94068662834cb671640 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 11 Mar 2014 13:09:01 +0100 Subject: Fixed memory corruption in passes/abc/blifparse.cc --- passes/abc/blifparse.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/abc/blifparse.cc b/passes/abc/blifparse.cc index 2d46d1a8e..1d4da19ad 100644 --- a/passes/abc/blifparse.cc +++ b/passes/abc/blifparse.cc @@ -40,7 +40,7 @@ static bool read_next_line(char *&buffer, size_t &buffer_size, int &line_count, } if (buffer_len == 0 || buffer[buffer_len-1] == '\\') { - if (buffer[buffer_len-1] == '\\') + if (buffer_len > 0 && buffer[buffer_len-1] == '\\') buffer[--buffer_len] = 0; line_count++; if (fgets(buffer+buffer_len, buffer_size-buffer_len, f) == NULL) -- cgit v1.2.3 From 91704a78531bec2e3eea3ddf90eaedb28e1d696d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 11 Mar 2014 14:24:24 +0100 Subject: Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys (see https://github.com/cliffordwolf/yosys/pull/28) --- passes/abc/abc.cc | 9 +++++++-- passes/cmds/select.cc | 1 + passes/fsm/fsm_recode.cc | 3 ++- passes/techmap/dfflibmap.cc | 1 + 4 files changed, 11 insertions(+), 3 deletions(-) (limited to 'passes') diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index 2829e660f..286b750cc 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -43,7 +43,9 @@ #include #include #include +#include #include +#include #include "blifparse.h" @@ -973,7 +975,11 @@ struct AbcPass : public Pass { int lut_mode = 0; size_t argidx; - char *pwd = get_current_dir_name(); + char pwd [PATH_MAX]; + if (!getcwd(pwd, sizeof(pwd))) { + log_cmd_error("getcwd failed: %s\n", strerror(errno)); + log_abort(); + } for (argidx = 1; argidx < args.size(); argidx++) { std::string arg = args[argidx]; if (arg == "-exe" && argidx+1 < args.size()) { @@ -1020,7 +1026,6 @@ struct AbcPass : public Pass { } break; } - free(pwd); extra_args(args, argidx, design); if (lut_mode != 0 && !liberty_file.empty()) diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index 3a886b1c8..59f936b01 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -23,6 +23,7 @@ #include "kernel/log.h" #include #include +#include using RTLIL::id2cstr; diff --git a/passes/fsm/fsm_recode.cc b/passes/fsm/fsm_recode.cc index 5a4e091cf..b02287962 100644 --- a/passes/fsm/fsm_recode.cc +++ b/passes/fsm/fsm_recode.cc @@ -23,8 +23,9 @@ #include "kernel/consteval.h" #include "kernel/celltypes.h" #include "fsmdata.h" -#include "math.h" +#include #include +#include static void fm_set_fsm_print(RTLIL::Cell *cell, RTLIL::Module *module, FsmData &fsm_data, const char *prefix, FILE *f) { diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc index fd5fa86e1..4bf73358b 100644 --- a/passes/techmap/dfflibmap.cc +++ b/passes/techmap/dfflibmap.cc @@ -21,6 +21,7 @@ #include "kernel/log.h" #include "libparse.h" #include +#include using namespace PASS_DFFLIBMAP; -- cgit v1.2.3 From 9087ece97c20d76359fb23cfd7a0f13552c1f2fd Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 11 Mar 2014 14:52:37 +0100 Subject: OSX compatible creation of stdcells.inc, using code from github.com/Siesh1oo/yosys (see https://github.com/cliffordwolf/yosys/pull/28) --- passes/techmap/Makefile.inc | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'passes') diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc index ae1ebbb56..85d580ce8 100644 --- a/passes/techmap/Makefile.inc +++ b/passes/techmap/Makefile.inc @@ -11,8 +11,9 @@ GENFILES += passes/techmap/stdcells.inc passes/techmap/stdcells.inc: techlibs/common/stdcells.v echo "// autogenerated from $<" > $@.new - od -v -td1 -w1 $< | awk 'BEGIN { print "static char stdcells_code[] = {"; } $$2 != "" { print $$2 ","; } \ - END { print 0 "};"; }' | fmt >> $@.new + echo "static char stdcells_code[] = {" >> $@.new + od -v -td1 -An $< | $(SED) -e 's/[0-9][0-9]*/&,/g' >> $@.new + echo "0};" >> $@.new mv $@.new $@ passes/techmap/techmap.o: passes/techmap/stdcells.inc -- cgit v1.2.3 From 8127d5e8c35da6610dc9fd43cca66ff9ca41f078 Mon Sep 17 00:00:00 2001 From: Siesh1oo Date: Wed, 12 Mar 2014 18:33:37 +0100 Subject: - kernel/register.h, kernel/driver.cc: refactor rewrite_yosys_exe()/get_share_file_name() to portable proc_self_dirname()/proc_share_dirname(). This refactoring improves robustness and allows OSX support with only 7 new lines of code, and easy extension for other systems. - passes/abc/abc.cc, passes/cmds/show.cc, passes/techmap/techmap.cc: use new, refactored semantics. --- passes/abc/abc.cc | 2 +- passes/cmds/show.cc | 3 ++- passes/techmap/techmap.cc | 3 ++- 3 files changed, 5 insertions(+), 3 deletions(-) (limited to 'passes') diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index 286b750cc..30e78e588 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -969,7 +969,7 @@ struct AbcPass : public Pass { log_header("Executing ABC pass (technology mapping using ABC).\n"); log_push(); - std::string exe_file = rewrite_yosys_exe("yosys-abc"); + std::string exe_file = proc_self_dirname() + "yosys-abc"; std::string script_file, liberty_file, constr_file, clk_str; bool dff_mode = false, keepff = false, cleanup = true; int lut_mode = 0; diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index fdccb4bcc..bf37e5dae 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -751,7 +751,8 @@ struct ShowPass : public Pass { log_cmd_error("Shell command failed!\n"); } else if (format.empty()) { - std::string cmd = stringf("fuser -s '%s' || '%s' '%s' &", out_file.c_str(), rewrite_yosys_exe("yosys-svgviewer").c_str(), out_file.c_str()); + std::string svgviewer = proc_self_dirname() + "yosys-svgviewer"; + std::string cmd = stringf("fuser -s '%s' || '%s' '%s' &", out_file.c_str(), svgviewer.c_str(), out_file.c_str()); log("Exec: %s\n", cmd.c_str()); if (system(cmd.c_str()) != 0) log_cmd_error("Shell command failed!\n"); diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 937f41315..0ca601e3b 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -548,13 +548,14 @@ struct TechmapPass : public Pass { int max_iter = -1; size_t argidx; + std::string proc_share_path = proc_share_dirname(); for (argidx = 1; argidx < args.size(); argidx++) { if (args[argidx] == "-map" && argidx+1 < args.size()) { map_files.push_back(args[++argidx]); continue; } if (args[argidx] == "-share_map" && argidx+1 < args.size()) { - map_files.push_back(get_share_file_name(args[++argidx])); + map_files.push_back(proc_share_path + args[++argidx]); continue; } if (args[argidx] == "-max_iter" && argidx+1 < args.size()) { -- cgit v1.2.3 From fad8558eb5ecbd62e2032a48c537bfecfad3dfc4 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 13 Mar 2014 12:48:10 +0100 Subject: Merged OSX fixes from Siesh1oo with some modifications --- passes/techmap/techmap.cc | 1 + 1 file changed, 1 insertion(+) (limited to 'passes') diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 0ca601e3b..69ffb9230 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -17,6 +17,7 @@ * */ +#include "kernel/compatibility.h" #include "kernel/register.h" #include "kernel/sigtools.h" #include "kernel/log.h" -- cgit v1.2.3 From 34e54cda5b45fb96cd44597622c3cba00e410265 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 13 Mar 2014 13:12:49 +0100 Subject: Small improvement in SAT log messages --- passes/sat/sat.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'passes') diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index d18a220d3..87bff4c48 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -214,7 +214,7 @@ struct SatHelper log_cmd_error("Set expression with different lhs and rhs sizes: %s (%s, %d bits) vs. %s (%s, %d bits)\n", s.first.c_str(), log_signal(lhs), lhs.width, s.second.c_str(), log_signal(rhs), rhs.width); - log("Import set-constraint for timestep: %s = %s\n", log_signal(lhs), log_signal(rhs)); + log("Import set-constraint for this timestep: %s = %s\n", log_signal(lhs), log_signal(rhs)); big_lhs.remove2(lhs, &big_rhs); big_lhs.append(lhs); big_rhs.append(rhs); @@ -228,7 +228,7 @@ struct SatHelper log_cmd_error("Failed to parse lhs set expression `%s'.\n", s.c_str()); show_signal_pool.add(sigmap(lhs)); - log("Import unset-constraint for timestep: %s\n", log_signal(lhs)); + log("Import unset-constraint for this timestep: %s\n", log_signal(lhs)); big_lhs.remove2(lhs, &big_rhs); } @@ -291,7 +291,7 @@ struct SatHelper for (int t = 0; t < 3; t++) for (auto &sig : sets_def_undef[t]) { - log("Import %s constraint for timestep: %s\n", t == 0 ? "def" : t == 1 ? "any_undef" : "all_undef", log_signal(sig)); + log("Import %s constraint for this timestep: %s\n", t == 0 ? "def" : t == 1 ? "any_undef" : "all_undef", log_signal(sig)); std::vector undef_sig = satgen.importUndefSigSpec(sig, timestep); if (t == 0) ez.assume(ez.NOT(ez.expression(ezSAT::OpOr, undef_sig))); -- cgit v1.2.3 From 9a34486bfbc8780d9a3af3164e99977e44d2a65f Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 19 Mar 2014 10:05:01 +0100 Subject: Fixed performance problem in opt_mux with nets driven by many conflicting drivers --- passes/opt/opt_muxtree.cc | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc index 47100869c..3292a46c8 100644 --- a/passes/opt/opt_muxtree.cc +++ b/passes/opt/opt_muxtree.cc @@ -309,13 +309,17 @@ struct OptMuxtreeWorker if (port_idx < int(muxinfo.ports.size())-1 && !muxinfo.ports[port_idx].const_activated) knowledge.known_active.push_back(muxinfo.ports[port_idx].ctrl_sigs); + std::vector parent_muxes; for (int m : muxinfo.ports[port_idx].input_muxes) { if (knowledge.visited_muxes.count(m) > 0) continue; knowledge.visited_muxes.insert(m); + parent_muxes.push_back(m); + } + for (int m : parent_muxes) eval_mux(knowledge, m); + for (int m : parent_muxes) knowledge.visited_muxes.erase(m); - } if (port_idx < int(muxinfo.ports.size())-1 && !muxinfo.ports[port_idx].const_activated) knowledge.known_active.pop_back(); @@ -393,6 +397,7 @@ struct OptMuxtreeWorker void eval_root_mux(int mux_idx) { knowledge_t knowledge; + knowledge.visited_muxes.insert(mux_idx); eval_mux(knowledge, mux_idx); } }; -- cgit v1.2.3 From f69b5800c940557cafd20598b03d774dd6cf6f8d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 10 May 2014 16:22:56 +0200 Subject: fixed syntax error in dot file created by "show" command --- passes/cmds/show.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index bf37e5dae..92fc5bd55 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -487,7 +487,7 @@ struct ShowWorker fprintf(f, "%s:e -> %s:w [%s, %s];\n", it.first.c_str(), it2.c_str(), nextColor(it.second.color).c_str(), widthLabel(it.second.bits).c_str()); } - fprintf(f, "};\n"); + fprintf(f, "}\n"); } ShowWorker(FILE *f, RTLIL::Design *design, std::vector &libs, uint32_t colorSeed, -- cgit v1.2.3 From 68c059565a3b75808e74eb481f14cb7f0c907f37 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 12 May 2014 12:45:47 +0200 Subject: Fixed bug in opt_reduce (see vloghammer issue_044) --- passes/opt/opt_reduce.cc | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc index fee8fb71b..dfe214416 100644 --- a/passes/opt/opt_reduce.cc +++ b/passes/opt/opt_reduce.cc @@ -73,7 +73,10 @@ struct OptReduceWorker for (auto child_cell : drivers.find(chunk)) { if (child_cell->type == cell->type) { opt_reduce(cells, drivers, child_cell); - new_sig_a.append(child_cell->connections["\\A"]); + if (child_cell->connections["\\Y"].extract(0, 1) == chunk) + new_sig_a.append(child_cell->connections["\\A"]); + else + new_sig_a.append(RTLIL::State::S0); imported_children = true; } } -- cgit v1.2.3 From 684c85902d259a0db3ac5271b540549e98646306 Mon Sep 17 00:00:00 2001 From: Johann Glaser Date: Mon, 26 May 2014 17:13:41 +0200 Subject: be more verbose when techmap yielded processes --- passes/techmap/techmap.cc | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 69ffb9230..4c5a0febc 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -106,8 +106,12 @@ struct TechmapWorker if (tpl->memories.size() != 0) log_error("Technology map yielded memories -> this is not supported.\n"); - if (tpl->processes.size() != 0) + if (tpl->processes.size() != 0) { + log("Technology map yielded processes:\n"); + for (auto &it : tpl->processes) + log(" %s",RTLIL::id2cstr(it.first)); log_error("Technology map yielded processes -> this is not supported.\n"); + } // erase from namespace first for _TECHMAP_REPLACE_ to work module->cells.erase(cell->name); -- cgit v1.2.3 From 278085fa01a9013051fbec842314cb6b5642e9bb Mon Sep 17 00:00:00 2001 From: Johann Glaser Date: Wed, 28 May 2014 18:05:38 +0200 Subject: added log_header to miter and expose pass, show cell type for exposed ports --- passes/sat/expose.cc | 8 +++++--- passes/sat/miter.cc | 4 ++++ 2 files changed, 9 insertions(+), 3 deletions(-) (limited to 'passes') diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc index 2ac7b35f6..831a43aa5 100644 --- a/passes/sat/expose.cc +++ b/passes/sat/expose.cc @@ -259,6 +259,8 @@ struct ExposePass : public Pass { bool flag_evert_dff = false; std::string sep = "."; + log_header("Executing EXPOSE pass (exposing internal signals as outputs).\n"); + size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { @@ -629,7 +631,7 @@ struct ExposePass : public Pass { w->port_input = true; add_new_wire(module, w); - log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name)); + log("New module port: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name), RTLIL::id2cstr(cell->type)); RTLIL::SigSpec sig; if (cell->connections.count(p->name) != 0) @@ -654,7 +656,7 @@ struct ExposePass : public Pass { w->port_input = true; add_new_wire(module, w); - log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name)); + log("New module port: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name), RTLIL::id2cstr(cell->type)); if (w->port_input) module->connections.push_back(RTLIL::SigSig(it.second, w)); @@ -667,7 +669,7 @@ struct ExposePass : public Pass { } for (auto &it : delete_cells) { - log("Removing cell: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(it)); + log("Removing cell: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(it), RTLIL::id2cstr(module->cells.at(it)->type)); delete module->cells.at(it); module->cells.erase(it); } diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index db12cb57d..6c8e2ff48 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -28,6 +28,8 @@ static void create_miter_equiv(struct Pass *that, std::vector args, bool flag_make_outcmp = false; bool flag_make_assert = false; + log_header("Executing MITER pass (creating miter circuit).\n"); + size_t argidx; for (argidx = 2; argidx < args.size(); argidx++) { @@ -102,6 +104,8 @@ static void create_miter_equiv(struct Pass *that, std::vector args, log_cmd_error("No matching port in gold module was found for %s!\n", it.second->name.c_str()); } + log("Creating miter cell \"%s\" with gold cell \"%s\" and gate cell \"%s\".\n", RTLIL::id2cstr(miter_name), RTLIL::id2cstr(gold_name), RTLIL::id2cstr(gate_name)); + RTLIL::Module *miter_module = new RTLIL::Module; miter_module->name = miter_name; design->modules[miter_name] = miter_module; -- cgit v1.2.3 From 68c99bf7349cf56385ee803144dd7d8e219be8d5 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 1 Jun 2014 11:32:27 +0200 Subject: Fixed log messages in memory_dff --- passes/memory/memory_dff.cc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'passes') diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index 2502a8b61..e8da6d642 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -111,6 +111,8 @@ static void handle_wr_cell(RTLIL::Module *module, RTLIL::Cell *cell) cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity); log("merged $dff to cell.\n"); } + + log("no (compatible) $dff found.\n"); } static void disconnect_dff(RTLIL::Module *module, RTLIL::SigSpec sig) -- cgit v1.2.3 From 7020f7fc138ac9bad46f9f2b41150321f315f992 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 3 Jun 2014 09:23:31 +0200 Subject: added tee cmd --- passes/cmds/Makefile.inc | 1 + passes/cmds/tee.cc | 88 ++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 89 insertions(+) create mode 100644 passes/cmds/tee.cc (limited to 'passes') diff --git a/passes/cmds/Makefile.inc b/passes/cmds/Makefile.inc index 77cac2b45..3a4b2da71 100644 --- a/passes/cmds/Makefile.inc +++ b/passes/cmds/Makefile.inc @@ -15,5 +15,6 @@ OBJS += passes/cmds/copy.o OBJS += passes/cmds/splice.o OBJS += passes/cmds/scc.o OBJS += passes/cmds/log.o +OBJS += passes/cmds/tee.o OBJS += passes/cmds/connwrappers.o diff --git a/passes/cmds/tee.cc b/passes/cmds/tee.cc new file mode 100644 index 000000000..dd9591954 --- /dev/null +++ b/passes/cmds/tee.cc @@ -0,0 +1,88 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2014 Clifford Wolf + * Copyright (C) 2014 Johann Glaser + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/register.h" +#include "kernel/rtlil.h" +#include "kernel/log.h" + +struct TeePass : public Pass { + TeePass() : Pass("tee", "redirect command output to file") { } + virtual void help() + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" tee [-q] [-o logfile|-a logfile] cmd\n"); + log("\n"); + log("Execute the specified command, optionally writing the commands output to the\n"); + log("specified logfile(s).\n"); + log("\n"); + log(" -q\n"); + log(" Do not print output to the normal destination (console and/or log file)\n"); + log("\n"); + log(" -o logfile\n"); + log(" Write output to this file, truncate if exists.\n"); + log("\n"); + log(" -a logfile\n"); + log(" Write output to this file, append if exists.\n"); + log("\n"); + } + virtual void execute(std::vector args, RTLIL::Design *design) + { + std::vector backup_log_files, files_to_close; + backup_log_files = log_files; + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) + { + if (args[argidx] == "-q" && files_to_close.empty()) { + log_files.clear(); + continue; + } + if ((args[argidx] == "-o" || args[argidx] == "-a") && argidx+1 < args.size()) { + const char *open_mode = args[argidx] == "-o" ? "wt" : "at"; + FILE *f = fopen(args[++argidx].c_str(), open_mode); + if (f == NULL) { + for (auto cf : files_to_close) + fclose(cf); + log_cmd_error("Can't create file %s.\n", args[argidx].c_str()); + } + log_files.push_back(f); + files_to_close.push_back(f); + continue; + } + break; + } + + try { + std::vector new_args(args.begin() + argidx, args.end()); + Pass::call(design, new_args); + } catch (int ex) { + for (auto cf : files_to_close) + fclose(cf); + log_files = backup_log_files; + throw ex; + } + + for (auto cf : files_to_close) + fclose(cf); + log_files = backup_log_files; + } +} TeePass; + -- cgit v1.2.3 From e275e8eef9ae47670075bd73a671f3acd3c0ca52 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 7 Jun 2014 11:48:50 +0200 Subject: Add support for cell arrays --- passes/hierarchy/hierarchy.cc | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) (limited to 'passes') diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 526d17294..6890cb9ea 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -137,12 +137,23 @@ static void generate(RTLIL::Design *design, const std::vector &cell static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check, std::vector &libdirs) { bool did_something = false; + std::map> array_cells; std::string filename; for (auto &cell_it : module->cells) { RTLIL::Cell *cell = cell_it.second; + if (cell->type.substr(0, 7) == "$array:") { + int pos_idx = cell->type.find_first_of(':'); + int pos_num = cell->type.find_first_of(':', pos_idx + 1); + int pos_type = cell->type.find_first_of(':', pos_num + 1); + int idx = atoi(cell->type.substr(pos_idx + 1, pos_num).c_str()); + int num = atoi(cell->type.substr(pos_num + 1, pos_type).c_str()); + array_cells[cell] = std::pair(idx, num); + cell->type = cell->type.substr(pos_type + 1); + } + if (design->modules.count(cell->type) == 0) { if (design->modules.count("$abstract" + cell->type)) @@ -198,6 +209,29 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla did_something = true; } + for (auto &it : array_cells) + { + RTLIL::Cell *cell = it.first; + int idx = it.second.first, num = it.second.second; + + if (design->modules.count(cell->type) == 0) + log_error("Array cell `%s.%s' of unkown type `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); + + RTLIL::Module *mod = design->modules[cell->type]; + + for (auto &conn : cell->connections) { + int conn_size = conn.second.width; + if (mod->wires.count(conn.first) == 0) + log_error("Array cell `%s.%s' connects to unkown port `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(conn.first)); + int port_size = mod->wires.at(conn.first)->width; + if (conn_size == port_size) + continue; + if (conn_size != port_size*num) + log_error("Array cell `%s.%s' has invalid port vs. signal size for port `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(conn.first)); + conn.second = conn.second.extract(port_size*idx, port_size); + } + } + return did_something; } -- cgit v1.2.3 From 744e51846776a304828301914f5cd74fb7d0a5ca Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 7 Jun 2014 12:17:06 +0200 Subject: fixed cell array handling of positional arguments --- passes/hierarchy/hierarchy.cc | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) (limited to 'passes') diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 6890cb9ea..d8a23c727 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -221,9 +221,18 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla for (auto &conn : cell->connections) { int conn_size = conn.second.width; - if (mod->wires.count(conn.first) == 0) + std::string portname = conn.first; + if (portname.substr(0, 1) == "$") { + int port_id = atoi(portname.substr(1).c_str()); + for (auto &wire_it : mod->wires) + if (wire_it.second->port_id == port_id) { + portname = wire_it.first; + break; + } + } + if (mod->wires.count(portname) == 0) log_error("Array cell `%s.%s' connects to unkown port `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(conn.first)); - int port_size = mod->wires.at(conn.first)->width; + int port_size = mod->wires.at(portname)->width; if (conn_size == port_size) continue; if (conn_size != port_size*num) -- cgit v1.2.3 From 22a998903b14b93180b98fe71129160e27793e38 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 14 Jun 2014 16:19:32 +0200 Subject: Added %D and %c select commands --- passes/cmds/select.cc | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) (limited to 'passes') diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index 59f936b01..38d43f8df 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -595,6 +595,13 @@ static void select_stmt(RTLIL::Design *design, std::string arg) select_op_diff(design, work_stack[work_stack.size()-2], work_stack[work_stack.size()-1]); work_stack.pop_back(); } else + if (arg == "%D") { + if (work_stack.size() < 2) + log_cmd_error("Must have at least two elements on the stack for operator %%d.\n"); + select_op_diff(design, work_stack[work_stack.size()-1], work_stack[work_stack.size()-2]); + work_stack[work_stack.size()-2] = work_stack[work_stack.size()-1]; + work_stack.pop_back(); + } else if (arg == "%i") { if (work_stack.size() < 2) log_cmd_error("Must have at least two elements on the stack for operator %%i.\n"); @@ -606,14 +613,19 @@ static void select_stmt(RTLIL::Design *design, std::string arg) log_cmd_error("Must have at least one element on the stack for operator %%s.\n"); select_op_submod(design, work_stack[work_stack.size()-1]); } else + if (arg == "%c") { + if (work_stack.size() < 1) + log_cmd_error("Must have at least one element on the stack for operator %%c.\n"); + work_stack.push_back(work_stack.back()); + } else if (arg == "%m") { if (work_stack.size() < 1) - log_cmd_error("Must have at least one element on the stack for operator %%s.\n"); + log_cmd_error("Must have at least one element on the stack for operator %%m.\n"); select_op_fullmod(design, work_stack[work_stack.size()-1]); } else if (arg == "%a") { if (work_stack.size() < 1) - log_cmd_error("Must have at least one element on the stack for operator %%s.\n"); + log_cmd_error("Must have at least one element on the stack for operator %%a.\n"); select_op_alias(design, work_stack[work_stack.size()-1]); } else if (arg == "%x" || (arg.size() > 2 && arg.substr(0, 2) == "%x" && (arg[2] == ':' || arg[2] == '*' || arg[2] == '.' || ('0' <= arg[2] && arg[2] <= '9')))) { @@ -958,6 +970,12 @@ struct SelectPass : public Pass { log(" %%d\n"); log(" pop the top set from the stack and subtract it from the new top\n"); log("\n"); + log(" %%D\n"); + log(" like %%d but swap the roles of two top sets on the stack\n"); + log("\n"); + log(" %%c\n"); + log(" create a copy of the top set rom the stack and push it\n"); + log("\n"); log(" %%x[|*][.][:[:..]]\n"); log(" expand top set num times according to the specified rules.\n"); log(" (i.e. select all cells connected to selected wires and select all\n"); -- cgit v1.2.3 From 1c85584fe5843a43590de3927fe9bde74a04e72e Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 19 Jun 2014 12:29:29 +0200 Subject: Do not create $dffsr cells with no-op resets in proc_dff --- passes/proc/proc_dff.cc | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'passes') diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index 2ec498fb2..c18446512 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -356,6 +356,11 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) rstval.optimize(); sig.optimize(); + if (rstval == sig) { + rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.width); + sync_level = NULL; + } + if (sync_always) { if (sync_edge || sync_level || many_async_rules.size() > 0) log_error("Mixed always event with edge and/or level sensitive events!\n"); -- cgit v1.2.3 From 3b52121d328d45a5d4269fd0e8de9af948c0216e Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 5 Jul 2014 11:17:40 +0200 Subject: now ignore init attributes on non-register wires in sat command --- passes/sat/sat.cc | 28 ++++++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-) (limited to 'passes') diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 87bff4c48..a9a00d8a2 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -103,10 +103,30 @@ struct SatHelper RTLIL::SigSpec rhs = it.second->attributes.at("\\init"); log_assert(lhs.width == rhs.width); - log("Import set-constraint from init attribute: %s = %s\n", log_signal(lhs), log_signal(rhs)); - big_lhs.remove2(lhs, &big_rhs); - big_lhs.append(lhs); - big_rhs.append(rhs); + RTLIL::SigSpec removed_bits; + for (int i = 0; i < lhs.width; i++) { + RTLIL::SigSpec bit = lhs.extract(i, 1); + if (!satgen.initial_state.check_all(bit)) { + removed_bits.append(bit); + lhs.remove(i, 1); + rhs.remove(i, 1); + i--; + } + } + + lhs.optimize(); + rhs.optimize(); + removed_bits.optimize(); + + if (removed_bits.width) + log("Warning: ignoring initial value on non-register: %s\n", log_signal(removed_bits)); + + if (lhs.width) { + log("Import set-constraint from init attribute: %s = %s\n", log_signal(lhs), log_signal(rhs)); + big_lhs.remove2(lhs, &big_rhs); + big_lhs.append(lhs); + big_rhs.append(rhs); + } } for (auto &s : sets_init) -- cgit v1.2.3 From 765f172211c8d7d8f14b6010193d8b53f5ec5e8f Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 16 Jul 2014 12:13:13 +0200 Subject: Changes to "memory" pass for new $memwr/$mem WR_EN interface --- passes/memory/memory_collect.cc | 4 +- passes/memory/memory_map.cc | 88 +++++++++++++++++++++++++---------------- passes/memory/memory_unpack.cc | 2 +- 3 files changed, 56 insertions(+), 38 deletions(-) (limited to 'passes') diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc index 6fe5e162c..028841f60 100644 --- a/passes/memory/memory_collect.cc +++ b/passes/memory/memory_collect.cc @@ -88,7 +88,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) clk_polarity.extend(1, false); addr.extend(addr_bits, false); data.extend(memory->width, false); - en.extend(1, false); + en.extend(memory->width, false); sig_wr_clk.append(clk); sig_wr_clk_enable.append(clk_enable); @@ -147,7 +147,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) assert(sig_wr_clk_polarity.width == wr_ports && sig_wr_clk_polarity.is_fully_const()); assert(sig_wr_addr.width == wr_ports * addr_bits); assert(sig_wr_data.width == wr_ports * memory->width); - assert(sig_wr_en.width == wr_ports); + assert(sig_wr_en.width == wr_ports * memory->width); mem->parameters["\\WR_PORTS"] = RTLIL::Const(wr_ports); mem->parameters["\\WR_CLK_ENABLE"] = wr_ports ? sig_wr_clk_enable.chunks[0].data : RTLIL::Const(0, 0); diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index e0e3802d1..10ab6e2f4 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -69,8 +69,8 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::SigSpec refclock; RTLIL::State refclock_pol = RTLIL::State::Sx; for (int i = 0; i < clocks.width; i++) { - RTLIL::SigSpec wr_en = cell->connections["\\WR_EN"].extract(i, 1); - if (wr_en.is_fully_const() && wr_en.as_int() == 0) { + RTLIL::SigSpec wr_en = cell->connections["\\WR_EN"].extract(i * mem_width, mem_width); + if (wr_en.is_fully_const() && !wr_en.as_bool()) { static_ports.insert(i); continue; } @@ -256,7 +256,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) { RTLIL::SigSpec wr_addr = cell->connections["\\WR_ADDR"].extract(j*mem_abits, mem_abits); RTLIL::SigSpec wr_data = cell->connections["\\WR_DATA"].extract(j*mem_width, mem_width); - RTLIL::SigSpec wr_en = cell->connections["\\WR_EN"].extract(j, 1); + RTLIL::SigSpec wr_en = cell->connections["\\WR_EN"].extract(j*mem_width, mem_width); RTLIL::Cell *c = new RTLIL::Cell; c->name = genid(cell->name, "$wreq", i, "", j); @@ -271,46 +271,64 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) module->cells[c->name] = c; count_wrmux++; - RTLIL::Wire *w = new RTLIL::Wire; - w->name = genid(cell->name, "$wreq", i, "", j, "$y"); - module->wires[w->name] = w; - c->connections["\\Y"] = RTLIL::SigSpec(w); + RTLIL::Wire *w_seladdr = new RTLIL::Wire; + w_seladdr->name = genid(cell->name, "$wreq", i, "", j, "$y"); + module->wires[w_seladdr->name] = w_seladdr; + c->connections["\\Y"] = w_seladdr; - if (wr_en != RTLIL::SigSpec(1, 1)) + int wr_offset = 0; + while (wr_offset < wr_en.width) { + int wr_width = 1; + RTLIL::SigSpec wr_bit = wr_en.extract(wr_offset, 1); + + while (wr_offset + wr_width < wr_en.width) { + RTLIL::SigSpec next_wr_bit = wr_en.extract(wr_offset + wr_width, 1); + if (next_wr_bit != wr_bit) + break; + wr_width++; + } + + RTLIL::Wire *w = w_seladdr; + + if (wr_bit != RTLIL::SigSpec(1, 1)) + { + c = new RTLIL::Cell; + c->name = genid(cell->name, "$wren", i, "", j, "", wr_offset); + c->type = "$and"; + c->parameters["\\A_SIGNED"] = RTLIL::Const(0); + c->parameters["\\B_SIGNED"] = RTLIL::Const(0); + c->parameters["\\A_WIDTH"] = RTLIL::Const(1); + c->parameters["\\B_WIDTH"] = RTLIL::Const(1); + c->parameters["\\Y_WIDTH"] = RTLIL::Const(1); + c->connections["\\A"] = w; + c->connections["\\B"] = wr_bit; + module->cells[c->name] = c; + + w = new RTLIL::Wire; + w->name = genid(cell->name, "$wren", i, "", j, "", wr_offset, "$y"); + module->wires[w->name] = w; + c->connections["\\Y"] = RTLIL::SigSpec(w); + } + c = new RTLIL::Cell; - c->name = genid(cell->name, "$wren", i, "", j); - c->type = "$and"; - c->parameters["\\A_SIGNED"] = RTLIL::Const(0); - c->parameters["\\B_SIGNED"] = RTLIL::Const(0); - c->parameters["\\A_WIDTH"] = RTLIL::Const(1); - c->parameters["\\B_WIDTH"] = RTLIL::Const(1); - c->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - c->connections["\\A"] = RTLIL::SigSpec(w); - c->connections["\\B"] = wr_en; + c->name = genid(cell->name, "$wrmux", i, "", j, "", wr_offset); + c->type = "$mux"; + c->parameters["\\WIDTH"] = wr_width; + c->connections["\\A"] = sig.extract(wr_offset, wr_width); + c->connections["\\B"] = wr_data.extract(wr_offset, wr_width); + c->connections["\\S"] = RTLIL::SigSpec(w); module->cells[c->name] = c; w = new RTLIL::Wire; - w->name = genid(cell->name, "$wren", i, "", j, "$y"); + w->name = genid(cell->name, "$wrmux", i, "", j, "", wr_offset, "$y"); + w->width = wr_width; module->wires[w->name] = w; - c->connections["\\Y"] = RTLIL::SigSpec(w); - } + c->connections["\\Y"] = w; - c = new RTLIL::Cell; - c->name = genid(cell->name, "$wrmux", i, "", j); - c->type = "$mux"; - c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"]; - c->connections["\\A"] = sig; - c->connections["\\B"] = wr_data; - c->connections["\\S"] = RTLIL::SigSpec(w); - module->cells[c->name] = c; - - w = new RTLIL::Wire; - w->name = genid(cell->name, "$wrmux", i, "", j, "$y"); - w->width = mem_width; - module->wires[w->name] = w; - c->connections["\\Y"] = RTLIL::SigSpec(w); - sig = RTLIL::SigSpec(w); + sig.replace(wr_offset, w); + wr_offset += wr_width; + } } module->connections.push_back(RTLIL::SigSig(data_reg_in[i], sig)); diff --git a/passes/memory/memory_unpack.cc b/passes/memory/memory_unpack.cc index 782c0cd79..bbd015833 100644 --- a/passes/memory/memory_unpack.cc +++ b/passes/memory/memory_unpack.cc @@ -74,7 +74,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory) cell->parameters["\\CLK_POLARITY"] = RTLIL::SigSpec(memory->parameters.at("\\WR_CLK_POLARITY")).extract(i, 1).as_const(); cell->parameters["\\PRIORITY"] = i; cell->connections["\\CLK"] = memory->connections.at("\\WR_CLK").extract(i, 1); - cell->connections["\\EN"] = memory->connections.at("\\WR_EN").extract(i, 1); + cell->connections["\\EN"] = memory->connections.at("\\WR_EN").extract(i*mem->width, mem->width); cell->connections["\\ADDR"] = memory->connections.at("\\WR_ADDR").extract(i*abits, abits); cell->connections["\\DATA"] = memory->connections.at("\\WR_DATA").extract(i*mem->width, mem->width); module->add(cell); -- cgit v1.2.3 From d678b6533dfac431a36abd22c01e9df184b723a4 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 16 Jul 2014 13:37:41 +0200 Subject: improved opt_reduce for $mem/$memwr WR_EN multiplexers --- passes/opt/opt_reduce.cc | 80 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) (limited to 'passes') diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc index dfe214416..d5bcb7f00 100644 --- a/passes/opt/opt_reduce.cc +++ b/passes/opt/opt_reduce.cc @@ -171,6 +171,66 @@ struct OptReduceWorker } } + void opt_mux_bits(RTLIL::Cell *cell) + { + std::vector sig_a = assign_map(cell->connections["\\A"]).to_sigbit_vector(); + std::vector sig_b = assign_map(cell->connections["\\B"]).to_sigbit_vector(); + std::vector sig_y = assign_map(cell->connections["\\Y"]).to_sigbit_vector(); + + std::vector new_sig_y; + RTLIL::SigSig old_sig_conn; + + std::vector> consolidated_in_tuples; + std::map, RTLIL::SigBit> consolidated_in_tuples_map; + + for (int i = 0; i < int(sig_y.size()); i++) + { + std::vector in_tuple; + in_tuple.push_back(sig_a.at(i)); + for (int j = i; j < int(sig_b.size()); j += int(sig_a.size())) + in_tuple.push_back(sig_b.at(j)); + + if (consolidated_in_tuples_map.count(in_tuple)) + { + old_sig_conn.first.append_bit(sig_y.at(i)); + old_sig_conn.second.append_bit(consolidated_in_tuples_map.at(in_tuple)); + } + else + { + consolidated_in_tuples_map[in_tuple] = sig_y.at(i); + consolidated_in_tuples.push_back(in_tuple); + new_sig_y.push_back(sig_y.at(i)); + } + } + + if (new_sig_y.size() != sig_y.size()) + { + log(" Consolidated identical input bits for %s cell %s:\n", cell->type.c_str(), cell->name.c_str()); + log(" Old inputs: A=%s, B=%s\n", log_signal(cell->connections["\\A"]), log_signal(cell->connections["\\B"])); + + cell->connections["\\A"] = RTLIL::SigSpec(); + for (auto &in_tuple : consolidated_in_tuples) + cell->connections["\\A"].append(in_tuple.at(0)); + + cell->connections["\\B"] = RTLIL::SigSpec(); + for (int i = 1; i <= cell->connections["\\S"].width; i++) + for (auto &in_tuple : consolidated_in_tuples) + cell->connections["\\B"].append(in_tuple.at(i)); + + log(" New inputs: A=%s, B=%s\n", log_signal(cell->connections["\\A"]), log_signal(cell->connections["\\B"])); + + cell->parameters["\\WIDTH"] = RTLIL::Const(new_sig_y.size()); + cell->connections["\\Y"] = new_sig_y; + + module->connections.push_back(old_sig_conn); + module->check(); + + did_something = true; + OPT_DID_SOMETHING = true; + total_count++; + } + } + OptReduceWorker(RTLIL::Design *design, RTLIL::Module *module) : design(design), module(module), assign_map(module) { @@ -179,6 +239,20 @@ struct OptReduceWorker total_count = 0; did_something = true; + SigPool mem_wren_sigs; + for (auto &cell_it : module->cells) { + RTLIL::Cell *cell = cell_it.second; + if (cell->type == "$mem") + mem_wren_sigs.add(assign_map(cell->connections["\\WR_EN"])); + if (cell->type == "$memwr") + mem_wren_sigs.add(assign_map(cell->connections["\\EN"])); + } + for (auto &cell_it : module->cells) { + RTLIL::Cell *cell = cell_it.second; + if (cell->type == "$dff" && mem_wren_sigs.check_any(assign_map(cell->connections["\\Q"]))) + mem_wren_sigs.add(assign_map(cell->connections["\\D"])); + } + while (did_something) { did_something = false; @@ -213,6 +287,12 @@ struct OptReduceWorker RTLIL::Cell *cell = cell_it.second; if ((cell->type != "$mux" && cell->type != "$pmux" && cell->type != "$safe_pmux") || !design->selected(module, cell)) continue; + + // this optimization is to aggressive for most coarse-grain applications. + // but we always want it for multiplexers driving write enable ports. + if (mem_wren_sigs.check_any(assign_map(cell->connections.at("\\Y")))) + opt_mux_bits(cell); + opt_mux(cell); } } -- cgit v1.2.3 From 64a6906cc448b90777591006786e8bb3a85d2c49 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 17 Jul 2014 08:58:51 +0200 Subject: Added support for "blackbox" attribute to flatten/techmap --- passes/techmap/techmap.cc | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 4c5a0febc..cb36c9e1f 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -243,6 +243,9 @@ struct TechmapWorker RTLIL::Module *tpl = map->modules[tpl_name]; std::map parameters = cell->parameters; + if (tpl->get_bool_attribute("\\blackbox")) + continue; + if (!flatten_mode) { if (tpl->get_bool_attribute("\\techmap_simplemap")) { @@ -686,7 +689,7 @@ struct FlattenPass : public Pass { if (top_mod != NULL) { std::map new_modules; for (auto &mod_it : design->modules) - if (mod_it.second == top_mod) { + if (mod_it.second == top_mod || mod_it.second->get_bool_attribute("\\blackbox")) { new_modules[mod_it.first] = mod_it.second; } else { log("Deleting now unused module %s.\n", RTLIL::id2cstr(mod_it.first)); -- cgit v1.2.3 From b76bf05cda789219069c623d3f77cbc47c1eb57d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 17 Jul 2014 08:59:07 +0200 Subject: Added support for "blackbox" attribute to iopadmap --- passes/techmap/iopadmap.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc index cc678516f..eb2757f66 100644 --- a/passes/techmap/iopadmap.cc +++ b/passes/techmap/iopadmap.cc @@ -115,7 +115,7 @@ struct IopadmapPass : public Pass { { RTLIL::Module *module = it.second; - if (!design->selected(module)) + if (!design->selected(module) || module->get_bool_attribute("\\blackbox")) continue; for (auto &it2 : module->wires) -- cgit v1.2.3 From 1b00861d0a3bba0b609eecde504d8a4f2f9d973d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 17 Jul 2014 12:12:04 +0200 Subject: Improved opt_reduce handling of mem wr_en mux bits --- passes/opt/opt_reduce.cc | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) (limited to 'passes') diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc index d5bcb7f00..1e91d1601 100644 --- a/passes/opt/opt_reduce.cc +++ b/passes/opt/opt_reduce.cc @@ -186,11 +186,21 @@ struct OptReduceWorker for (int i = 0; i < int(sig_y.size()); i++) { std::vector in_tuple; + bool all_tuple_bits_same = true; + in_tuple.push_back(sig_a.at(i)); - for (int j = i; j < int(sig_b.size()); j += int(sig_a.size())) + for (int j = i; j < int(sig_b.size()); j += int(sig_a.size())) { + if (sig_b.at(j) != sig_a.at(i)) + all_tuple_bits_same = false; in_tuple.push_back(sig_b.at(j)); + } - if (consolidated_in_tuples_map.count(in_tuple)) + if (all_tuple_bits_same) + { + old_sig_conn.first.append_bit(sig_y.at(i)); + old_sig_conn.second.append_bit(sig_a.at(i)); + } + else if (consolidated_in_tuples_map.count(in_tuple)) { old_sig_conn.first.append_bit(sig_y.at(i)); old_sig_conn.second.append_bit(consolidated_in_tuples_map.at(in_tuple)); @@ -206,7 +216,8 @@ struct OptReduceWorker if (new_sig_y.size() != sig_y.size()) { log(" Consolidated identical input bits for %s cell %s:\n", cell->type.c_str(), cell->name.c_str()); - log(" Old inputs: A=%s, B=%s\n", log_signal(cell->connections["\\A"]), log_signal(cell->connections["\\B"])); + log(" Old ports: A=%s, B=%s, Y=%s\n", log_signal(cell->connections["\\A"]), + log_signal(cell->connections["\\B"]), log_signal(cell->connections["\\Y"])); cell->connections["\\A"] = RTLIL::SigSpec(); for (auto &in_tuple : consolidated_in_tuples) @@ -217,11 +228,13 @@ struct OptReduceWorker for (auto &in_tuple : consolidated_in_tuples) cell->connections["\\B"].append(in_tuple.at(i)); - log(" New inputs: A=%s, B=%s\n", log_signal(cell->connections["\\A"]), log_signal(cell->connections["\\B"])); - cell->parameters["\\WIDTH"] = RTLIL::Const(new_sig_y.size()); cell->connections["\\Y"] = new_sig_y; + log(" New ports: A=%s, B=%s, Y=%s\n", log_signal(cell->connections["\\A"]), + log_signal(cell->connections["\\B"]), log_signal(cell->connections["\\Y"])); + log(" New connections: %s = %s\n", log_signal(old_sig_conn.first), log_signal(old_sig_conn.second)); + module->connections.push_back(old_sig_conn); module->check(); -- cgit v1.2.3 From 309ae98246cf9ff115b7d95ae14991faf72a5a38 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 18 Jul 2014 10:28:45 +0200 Subject: Apply opt_reduce WR_EN opts to the whole mux tree driving the WR_EN port --- passes/opt/opt_reduce.cc | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'passes') diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc index 1e91d1601..a0c7a027f 100644 --- a/passes/opt/opt_reduce.cc +++ b/passes/opt/opt_reduce.cc @@ -266,6 +266,21 @@ struct OptReduceWorker mem_wren_sigs.add(assign_map(cell->connections["\\D"])); } + bool keep_expanding_mem_wren_sigs = true; + while (keep_expanding_mem_wren_sigs) { + keep_expanding_mem_wren_sigs = false; + for (auto &cell_it : module->cells) { + RTLIL::Cell *cell = cell_it.second; + if (cell->type == "$mux" && mem_wren_sigs.check_any(assign_map(cell->connections["\\Y"]))) { + if (!mem_wren_sigs.check_all(assign_map(cell->connections["\\A"])) || + !mem_wren_sigs.check_all(assign_map(cell->connections["\\B"]))) + keep_expanding_mem_wren_sigs = true; + mem_wren_sigs.add(assign_map(cell->connections["\\A"])); + mem_wren_sigs.add(assign_map(cell->connections["\\B"])); + } + } + } + while (did_something) { did_something = false; -- cgit v1.2.3 From ab4b26679ff4acdc5a86bc79faa5439c625c38f8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 18 Jul 2014 12:40:01 +0200 Subject: Added memory_share --- passes/memory/Makefile.inc | 1 + passes/memory/memory.cc | 2 + passes/memory/memory_share.cc | 263 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 266 insertions(+) create mode 100644 passes/memory/memory_share.cc (limited to 'passes') diff --git a/passes/memory/Makefile.inc b/passes/memory/Makefile.inc index 21f17db5b..026c5ff85 100644 --- a/passes/memory/Makefile.inc +++ b/passes/memory/Makefile.inc @@ -1,6 +1,7 @@ OBJS += passes/memory/memory.o OBJS += passes/memory/memory_dff.o +OBJS += passes/memory/memory_share.o OBJS += passes/memory/memory_collect.o OBJS += passes/memory/memory_unpack.o OBJS += passes/memory/memory_map.o diff --git a/passes/memory/memory.cc b/passes/memory/memory.cc index 680657a79..a0c89a4d6 100644 --- a/passes/memory/memory.cc +++ b/passes/memory/memory.cc @@ -33,6 +33,7 @@ struct MemoryPass : public Pass { log("This pass calls all the other memory_* passes in a useful order:\n"); log("\n"); log(" memory_dff\n"); + log(" memory_share\n"); log(" memory_collect\n"); log(" memory_map (skipped if called with -nomap)\n"); log("\n"); @@ -58,6 +59,7 @@ struct MemoryPass : public Pass { extra_args(args, argidx, design); Pass::call(design, "memory_dff"); + Pass::call(design, "memory_share"); Pass::call(design, "memory_collect"); if (!flag_nomap) diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc new file mode 100644 index 000000000..69f3e739c --- /dev/null +++ b/passes/memory/memory_share.cc @@ -0,0 +1,263 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/rtlil.h" +#include "kernel/sigtools.h" +#include "kernel/register.h" +#include "kernel/log.h" +#include + +static bool memcells_cmp(RTLIL::Cell *a, RTLIL::Cell *b) +{ + if (a->type == "$memrd" && b->type == "$memrd") + return a->name < b->name; + if (a->type == "$memrd" || b->type == "$memrd") + return (a->type == "$memrd") < (b->type == "$memrd"); + return a->parameters.at("\\PRIORITY").as_int() < b->parameters.at("\\PRIORITY").as_int(); +} + +struct MemoryShareWorker +{ + RTLIL::Design *design; + RTLIL::Module *module; + SigMap sigmap; + + RTLIL::SigSpec mask_en_naive(RTLIL::SigSpec do_mask, RTLIL::SigSpec bits, RTLIL::SigSpec mask_bits) + { + // this is the naive version of the function that does not care about grouping the EN bits. + + RTLIL::SigSpec inv_mask_bits = module->Not(NEW_ID, mask_bits); + RTLIL::SigSpec inv_mask_bits_filtered = module->Mux(NEW_ID, RTLIL::SigSpec(RTLIL::State::S1, bits.width), inv_mask_bits, do_mask); + RTLIL::SigSpec result = module->And(NEW_ID, inv_mask_bits_filtered, bits); + return result; + } + + RTLIL::SigSpec mask_en_grouped(RTLIL::SigSpec do_mask, RTLIL::SigSpec bits, RTLIL::SigSpec mask_bits) + { + // this version of the function preserves the bit grouping in the EN bits. + + std::vector v_bits = bits; + std::vector v_mask_bits = mask_bits; + + std::map, std::pair>> groups; + RTLIL::SigSpec grouped_bits, grouped_mask_bits; + + for (int i = 0; i < bits.width; i++) { + std::pair key(v_bits[i], v_mask_bits[i]); + if (groups.count(key) == 0) { + groups[key].first = grouped_bits.width; + grouped_bits.append_bit(v_bits[i]); + grouped_mask_bits.append_bit(v_mask_bits[i]); + } + groups[key].second.push_back(i); + } + + std::vector grouped_result = mask_en_naive(do_mask, grouped_bits, grouped_mask_bits); + RTLIL::SigSpec result; + + for (int i = 0; i < bits.width; i++) { + std::pair key(v_bits[i], v_mask_bits[i]); + result.append_bit(grouped_result.at(groups.at(key).first)); + } + + return result; + } + + void merge_en_data(RTLIL::SigSpec &merged_en, RTLIL::SigSpec &merged_data, RTLIL::SigSpec next_en, RTLIL::SigSpec next_data) + { + std::vector v_old_en = merged_en; + std::vector v_next_en = next_en; + + // The new merged_en signal is just the old merged_en signal and next_en OR'ed together. + // But of course we need to preserve the bit grouping.. + + std::map, int> groups; + std::vector grouped_old_en, grouped_next_en; + RTLIL::SigSpec new_merged_en; + + for (int i = 0; i < int(v_old_en.size()); i++) { + std::pair key(v_old_en[i], v_next_en[i]); + if (groups.count(key) == 0) { + groups[key] = grouped_old_en.size(); + grouped_old_en.push_back(key.first); + grouped_next_en.push_back(key.second); + } + } + + std::vector grouped_new_en = module->Or(NEW_ID, grouped_old_en, grouped_next_en); + + for (int i = 0; i < int(v_old_en.size()); i++) { + std::pair key(v_old_en[i], v_next_en[i]); + new_merged_en.append_bit(grouped_new_en.at(groups.at(key))); + } + + // Create the new merged_data signal. + + RTLIL::SigSpec new_merged_data(RTLIL::State::Sx, merged_data.width); + + RTLIL::SigSpec old_data_set = module->And(NEW_ID, merged_en, merged_data); + RTLIL::SigSpec old_data_unset = module->And(NEW_ID, merged_en, module->Not(NEW_ID, merged_data)); + + RTLIL::SigSpec new_data_set = module->And(NEW_ID, next_en, next_data); + RTLIL::SigSpec new_data_unset = module->And(NEW_ID, next_en, module->Not(NEW_ID, next_data)); + + new_merged_data = module->Or(NEW_ID, new_merged_data, old_data_set); + new_merged_data = module->And(NEW_ID, new_merged_data, module->Not(NEW_ID, old_data_unset)); + + new_merged_data = module->Or(NEW_ID, new_merged_data, new_data_set); + new_merged_data = module->And(NEW_ID, new_merged_data, module->Not(NEW_ID, new_data_unset)); + + // Update merged_* signals + + merged_en = new_merged_en; + merged_data = new_merged_data; + } + + void consolidate_wr_by_addr(std::string memid, std::vector &wr_ports) + { + log("Consolidating write ports of memory %s by address:\n", log_id(memid)); + + std::map last_port_by_addr; + + bool cache_clk_enable = false; + bool cache_clk_polarity = false; + RTLIL::SigSpec cache_clk; + + for (int i = 0; i < int(wr_ports.size()); i++) + { + RTLIL::Cell *cell = wr_ports.at(i); + RTLIL::SigSpec addr = sigmap(cell->connections.at("\\ADDR")); + + if (cell->parameters.at("\\CLK_ENABLE").as_bool() != cache_clk_enable || + (cache_clk_enable && (sigmap(cell->connections.at("\\CLK")) != cache_clk || + cell->parameters.at("\\CLK_POLARITY").as_bool() != cache_clk_polarity))) + { + cache_clk_enable = cell->parameters.at("\\CLK_ENABLE").as_bool(); + cache_clk_polarity = cell->parameters.at("\\CLK_POLARITY").as_bool(); + cache_clk = sigmap(cell->connections.at("\\CLK")); + last_port_by_addr.clear(); + + if (cache_clk_enable) + log(" New clock domain: %s %s\n", cache_clk_polarity ? "posedge" : "negedge", log_signal(cache_clk)); + else + log(" New clock domain: unclocked\n"); + } + + log(" Port %d (%s) has addr %s.\n", i, log_id(cell), log_signal(addr)); + + if (last_port_by_addr.count(addr)) + { + int last_i = last_port_by_addr.at(addr); + log(" Merging port %d into this one.\n", last_i); + + // Force this ports addr input to addr directly (skip don't care muxes) + + cell->connections.at("\\ADDR") = addr; + + // If any of the ports between `last_i' and `i' write to the same address, this + // will have priority over whatever `last_i` wrote. So we need to revisit those + // ports and mask the EN bits accordingly. + + RTLIL::SigSpec merged_en = sigmap(wr_ports[last_i]->connections.at("\\EN")); + + for (int j = last_i+1; j < i; j++) + { + if (wr_ports[j] == NULL) + continue; + + RTLIL::SigSpec is_same_addr = module->new_wire(1, NEW_ID); + module->addEq(NEW_ID, addr, wr_ports[j]->connections.at("\\ADDR"), is_same_addr); + merged_en = mask_en_grouped(is_same_addr, merged_en, sigmap(wr_ports[j]->connections.at("\\EN"))); + } + + // Then we need to merge the (masked) EN and the DATA signals. + // Note that we intentionally do not use sigmap() on the DATA ports. + + RTLIL::SigSpec merged_data = wr_ports[last_i]->connections.at("\\DATA"); + merge_en_data(merged_en, merged_data, sigmap(cell->connections.at("\\EN")), cell->connections.at("\\DATA")); + + // Connect the new EN and DATA signals and remove the old write port. + + cell->connections.at("\\EN") = merged_en; + cell->connections.at("\\DATA") = merged_data; + + module->cells.erase(wr_ports[last_i]->name); + delete wr_ports[last_i]; + wr_ports[last_i] = NULL; + } + + last_port_by_addr[addr] = i; + } + } + + MemoryShareWorker(RTLIL::Design *design, RTLIL::Module *module) : + design(design), module(module), sigmap(module) + { + std::map, std::vector>> memindex; + + for (auto &it : module->cells) + { + RTLIL::Cell *cell = it.second; + + if (cell->type == "$memrd") + memindex[cell->parameters.at("\\MEMID").decode_string()].first.push_back(cell); + + if (cell->type == "$memwr") + memindex[cell->parameters.at("\\MEMID").decode_string()].second.push_back(cell); + + if (cell->type == "$mux") + { + RTLIL::SigSpec sig_a = sigmap(cell->connections.at("\\A")); + RTLIL::SigSpec sig_b = sigmap(cell->connections.at("\\B")); + + if (sig_a.is_fully_undef()) + sigmap.add(cell->connections.at("\\Y"), sig_b); + else if (sig_b.is_fully_undef()) + sigmap.add(cell->connections.at("\\Y"), sig_a); + } + } + + for (auto &it : memindex) { + std::sort(it.second.first.begin(), it.second.first.end(), memcells_cmp); + std::sort(it.second.second.begin(), it.second.second.end(), memcells_cmp); + consolidate_wr_by_addr(it.first, it.second.second); + } + } +}; + +struct MemorySharePass : public Pass { + MemorySharePass() : Pass("memory_share", "consolidate memory ports") { } + virtual void help() + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" memory_share [selection]\n"); + log("\n"); + log("This pass merges share-able memory ports into single memory ports.\n"); + log("\n"); + } + virtual void execute(std::vector args, RTLIL::Design *design) { + log_header("Executing MEMORY_SHARE pass (consolidating $memrc/$memwr cells).\n"); + extra_args(args, 1, design); + for (auto &mod_it : design->modules) + if (design->selected(mod_it.second)) + MemoryShareWorker(design, mod_it.second); + } +} MemorySharePass; + -- cgit v1.2.3 From a3419319727ac1c2012602a702b62631570d7588 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 18 Jul 2014 14:32:40 +0200 Subject: Only create collision detect logic in memory_share if necessary --- passes/memory/memory_share.cc | 51 +++++++++++++++++++++++++++++++++++++++---- 1 file changed, 47 insertions(+), 4 deletions(-) (limited to 'passes') diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index 69f3e739c..140a41849 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -134,6 +134,7 @@ struct MemoryShareWorker log("Consolidating write ports of memory %s by address:\n", log_id(memid)); std::map last_port_by_addr; + std::vector> active_bits_on_port; bool cache_clk_enable = false; bool cache_clk_polarity = false; @@ -161,11 +162,27 @@ struct MemoryShareWorker log(" Port %d (%s) has addr %s.\n", i, log_id(cell), log_signal(addr)); + log(" Active bits: "); + std::vector en_bits = sigmap(cell->connections.at("\\EN")); + active_bits_on_port.push_back(std::vector(en_bits.size())); + for (int k = int(en_bits.size())-1; k >= 0; k--) { + active_bits_on_port[i][k] = en_bits[k].wire != NULL || en_bits[k].data != RTLIL::State::S0; + log("%c", active_bits_on_port[i][k] ? '1' : '0'); + } + log("\n"); + if (last_port_by_addr.count(addr)) { int last_i = last_port_by_addr.at(addr); log(" Merging port %d into this one.\n", last_i); + bool found_overlapping_bits = false; + for (int k = 0; k < int(en_bits.size()); k++) { + if (active_bits_on_port[i][k] && active_bits_on_port[last_i][k]) + found_overlapping_bits = true; + active_bits_on_port[i][k] = active_bits_on_port[i][k] || active_bits_on_port[last_i][k]; + } + // Force this ports addr input to addr directly (skip don't care muxes) cell->connections.at("\\ADDR") = addr; @@ -181,16 +198,35 @@ struct MemoryShareWorker if (wr_ports[j] == NULL) continue; - RTLIL::SigSpec is_same_addr = module->new_wire(1, NEW_ID); - module->addEq(NEW_ID, addr, wr_ports[j]->connections.at("\\ADDR"), is_same_addr); - merged_en = mask_en_grouped(is_same_addr, merged_en, sigmap(wr_ports[j]->connections.at("\\EN"))); + for (int k = 0; k < int(en_bits.size()); k++) + if (active_bits_on_port[i][k] && active_bits_on_port[j][k]) + goto found_overlapping_bits_i_j; + + if (0) { + found_overlapping_bits_i_j: + log(" Creating collosion-detect logic for port %d.\n", j); + RTLIL::SigSpec is_same_addr = module->new_wire(1, NEW_ID); + module->addEq(NEW_ID, addr, wr_ports[j]->connections.at("\\ADDR"), is_same_addr); + merged_en = mask_en_grouped(is_same_addr, merged_en, sigmap(wr_ports[j]->connections.at("\\EN"))); + } } // Then we need to merge the (masked) EN and the DATA signals. // Note that we intentionally do not use sigmap() on the DATA ports. RTLIL::SigSpec merged_data = wr_ports[last_i]->connections.at("\\DATA"); - merge_en_data(merged_en, merged_data, sigmap(cell->connections.at("\\EN")), cell->connections.at("\\DATA")); + if (found_overlapping_bits) { + log(" Creating logic for merging DATA and EN ports.\n"); + merge_en_data(merged_en, merged_data, sigmap(cell->connections.at("\\EN")), cell->connections.at("\\DATA")); + } else { + for (int k = 0; k < int(en_bits.size()); k++) + if (!active_bits_on_port[last_i][k]) { + merged_en.replace(k, cell->connections.at("\\EN").extract(k, 1)); + merged_data.replace(k, cell->connections.at("\\DATA").extract(k, 1)); + } + merged_en.optimize(); + merged_data.optimize(); + } // Connect the new EN and DATA signals and remove the old write port. @@ -200,6 +236,13 @@ struct MemoryShareWorker module->cells.erase(wr_ports[last_i]->name); delete wr_ports[last_i]; wr_ports[last_i] = NULL; + + log(" Active bits: "); + std::vector en_bits = sigmap(cell->connections.at("\\EN")); + active_bits_on_port.push_back(std::vector(en_bits.size())); + for (int k = int(en_bits.size())-1; k >= 0; k--) + log("%c", active_bits_on_port[i][k] ? '1' : '0'); + log("\n"); } last_port_by_addr[addr] = i; -- cgit v1.2.3 From 44f13aff92146592fd9399bf96dfcb1f81fde708 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 18 Jul 2014 16:44:45 +0200 Subject: Improved seeding of color rng in show command --- passes/cmds/show.cc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index 92fc5bd55..eab42e6ff 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -54,7 +54,7 @@ struct ShowWorker const std::vector> &color_selections; const std::vector> &label_selections; - uint32_t xorshift32(uint32_t x) { + static uint32_t xorshift32(uint32_t x) { x ^= x << 13; x ^= x >> 17; x ^= x << 5; @@ -655,6 +655,8 @@ struct ShowPass : public Pass { } if (arg == "-colors" && argidx+1 < args.size()) { colorSeed = atoi(args[++argidx].c_str()); + for (int i = 0; i < 100; i++) + colorSeed = ShowWorker::xorshift32(colorSeed); continue; } if (arg == "-format" && argidx+1 < args.size()) { -- cgit v1.2.3 From e441f07d895a673c0bf40dcdc76781b50834fe44 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 18 Jul 2014 16:46:40 +0200 Subject: Added translation from read-feedback to en-signals in memory_share --- passes/memory/memory.cc | 4 + passes/memory/memory_share.cc | 246 ++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 240 insertions(+), 10 deletions(-) (limited to 'passes') diff --git a/passes/memory/memory.cc b/passes/memory/memory.cc index a0c89a4d6..fc3095535 100644 --- a/passes/memory/memory.cc +++ b/passes/memory/memory.cc @@ -33,7 +33,9 @@ struct MemoryPass : public Pass { log("This pass calls all the other memory_* passes in a useful order:\n"); log("\n"); log(" memory_dff\n"); + log(" opt_clean\n"); log(" memory_share\n"); + log(" opt_clean\n"); log(" memory_collect\n"); log(" memory_map (skipped if called with -nomap)\n"); log("\n"); @@ -59,7 +61,9 @@ struct MemoryPass : public Pass { extra_args(args, argidx, design); Pass::call(design, "memory_dff"); + Pass::call(design, "opt_clean"); Pass::call(design, "memory_share"); + Pass::call(design, "opt_clean"); Pass::call(design, "memory_collect"); if (!flag_nomap) diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index 140a41849..e2fa168c3 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -36,7 +36,209 @@ struct MemoryShareWorker { RTLIL::Design *design; RTLIL::Module *module; - SigMap sigmap; + SigMap sigmap, sigmap_xmux; + + std::map> sig_to_mux; + std::map>, RTLIL::SigBit> conditions_logic_cache; + + + // ----------------------------------------------------------------- + // Converting feedbacks to async read ports to proper enable signals + // ----------------------------------------------------------------- + + bool find_data_feedback(const std::set &async_rd_bits, RTLIL::SigBit sig, + std::map &state, std::set> &conditions) + { + if (async_rd_bits.count(sig)) { + conditions.insert(state); + return true; + } + + if (sig_to_mux.count(sig) == 0) + return false; + + RTLIL::Cell *cell = sig_to_mux.at(sig).first; + int bit_idx = sig_to_mux.at(sig).second; + + std::vector sig_a = sigmap(cell->connections.at("\\A")); + std::vector sig_b = sigmap(cell->connections.at("\\B")); + std::vector sig_s = sigmap(cell->connections.at("\\S")); + std::vector sig_y = sigmap(cell->connections.at("\\Y")); + log_assert(sig_y.at(bit_idx) == sig); + + for (int i = 0; i < int(sig_s.size()); i++) + if (state.count(sig_s[i]) && state.at(sig_s[i]) == true) { + if (find_data_feedback(async_rd_bits, sig_b.at(bit_idx + i*sig_y.size()), state, conditions)) + cell->connections.at("\\B").replace(bit_idx + i*sig_y.size(), RTLIL::State::Sx); + return false; + } + + + for (int i = 0; i < int(sig_s.size()); i++) + { + if (state.count(sig_s[i]) && state.at(sig_s[i]) == false) + continue; + + std::map new_state = state; + new_state[sig_s[i]] = true; + + if (find_data_feedback(async_rd_bits, sig_b.at(bit_idx + i*sig_y.size()), new_state, conditions)) + cell->connections.at("\\B").replace(bit_idx + i*sig_y.size(), RTLIL::State::Sx); + } + + std::map new_state = state; + for (int i = 0; i < int(sig_s.size()); i++) + new_state[sig_s[i]] = false; + + if (find_data_feedback(async_rd_bits, sig_a.at(bit_idx), new_state, conditions)) + cell->connections.at("\\A").replace(bit_idx, RTLIL::State::Sx); + + return false; + } + + RTLIL::SigBit conditions_to_logic(std::set> &conditions, int &created_conditions) + { + if (conditions_logic_cache.count(conditions)) + return conditions_logic_cache.at(conditions); + + RTLIL::SigSpec terms; + for (auto &cond : conditions) { + RTLIL::SigSpec sig1, sig2; + for (auto &it : cond) { + sig1.append_bit(it.first); + sig2.append_bit(it.second ? RTLIL::State::S1 : RTLIL::State::S0); + } + terms.append(module->Ne(NEW_ID, sig1, sig2)); + created_conditions++; + } + + if (terms.width > 1) + terms = module->ReduceAnd(NEW_ID, terms); + + return conditions_logic_cache[conditions] = terms; + } + + void translate_rd_feedback_to_en(std::string memid, std::vector &rd_ports, std::vector &wr_ports) + { + std::vector> async_rd_bits; + std::map> muxtree_upstream_map; + std::set non_feedback_nets; + + for (auto wire_it : module->wires) + if (wire_it.second->port_output) { + std::vector bits = RTLIL::SigSpec(wire_it.second); + non_feedback_nets.insert(bits.begin(), bits.end()); + } + + for (auto cell_it : module->cells) + { + RTLIL::Cell *cell = cell_it.second; + bool ignore_data_port = false; + + if (cell->type == "$mux" || cell->type == "$pmux") + { + std::vector sig_a = sigmap(cell->connections.at("\\A")); + std::vector sig_b = sigmap(cell->connections.at("\\B")); + std::vector sig_s = sigmap(cell->connections.at("\\S")); + std::vector sig_y = sigmap(cell->connections.at("\\Y")); + + non_feedback_nets.insert(sig_s.begin(), sig_s.end()); + + for (int i = 0; i < int(sig_y.size()); i++) { + muxtree_upstream_map[sig_y[i]].insert(sig_a[i]); + for (int j = 0; j < int(sig_s.size()); j++) + muxtree_upstream_map[sig_y[i]].insert(sig_b[i + j*sig_y.size()]); + } + + continue; + } + + if ((cell->type == "$memwr" || cell->type == "$memrd") && + cell->parameters.at("\\MEMID").decode_string() == memid) + ignore_data_port = true; + + for (auto conn : cell_it.second->connections) + { + if (ignore_data_port && conn.first == "\\DATA") + continue; + std::vector bits = sigmap(conn.second); + non_feedback_nets.insert(bits.begin(), bits.end()); + } + } + + std::set expand_non_feedback_nets = non_feedback_nets; + while (!expand_non_feedback_nets.empty()) + { + std::set new_expand_non_feedback_nets; + + for (auto &bit : expand_non_feedback_nets) + if (muxtree_upstream_map.count(bit)) + for (auto &new_bit : muxtree_upstream_map.at(bit)) + if (!non_feedback_nets.count(new_bit)) { + non_feedback_nets.insert(new_bit); + new_expand_non_feedback_nets.insert(new_bit); + } + + expand_non_feedback_nets.swap(new_expand_non_feedback_nets); + } + + for (auto cell : rd_ports) + { + if (cell->parameters.at("\\CLK_ENABLE").as_bool()) + continue; + + std::vector sig_data = sigmap(cell->connections.at("\\DATA")); + + for (int i = 0; i < int(sig_data.size()); i++) + if (non_feedback_nets.count(sig_data[i])) + goto not_pure_feedback_port; + + async_rd_bits.resize(std::max(async_rd_bits.size(), sig_data.size())); + for (int i = 0; i < int(sig_data.size()); i++) + async_rd_bits[i].insert(sig_data[i]); + + not_pure_feedback_port:; + } + + if (async_rd_bits.empty()) + return; + + log("Populating enable bits on write ports of memory %s with aync read feedback:\n", log_id(memid)); + + for (auto cell : wr_ports) + { + log(" Analyzing write port %s.\n", log_id(cell)); + + std::vector cell_data = cell->connections.at("\\DATA"); + std::vector cell_en = cell->connections.at("\\EN"); + + int created_conditions = 0; + for (int i = 0; i < int(cell_data.size()); i++) + if (cell_en[i] != RTLIL::SigBit(RTLIL::State::S0)) + { + std::map state; + std::set> conditions; + + if (cell_en[i].wire != NULL) { + state[cell_en[i]] = false; + conditions.insert(state); + } + + find_data_feedback(async_rd_bits.at(i), cell_data[i], state, conditions); + cell_en[i] = conditions_to_logic(conditions, created_conditions); + } + + if (created_conditions) { + log(" Added enable logic for %d different cases.\n", created_conditions); + cell->connections.at("\\EN") = cell_en; + } + } + } + + + // ------------------------------------------------------ + // Consolidate write ports that write to the same address + // ------------------------------------------------------ RTLIL::SigSpec mask_en_naive(RTLIL::SigSpec do_mask, RTLIL::SigSpec bits, RTLIL::SigSpec mask_bits) { @@ -143,7 +345,7 @@ struct MemoryShareWorker for (int i = 0; i < int(wr_ports.size()); i++) { RTLIL::Cell *cell = wr_ports.at(i); - RTLIL::SigSpec addr = sigmap(cell->connections.at("\\ADDR")); + RTLIL::SigSpec addr = sigmap_xmux(cell->connections.at("\\ADDR")); if (cell->parameters.at("\\CLK_ENABLE").as_bool() != cache_clk_enable || (cache_clk_enable && (sigmap(cell->connections.at("\\CLK")) != cache_clk || @@ -212,17 +414,18 @@ struct MemoryShareWorker } // Then we need to merge the (masked) EN and the DATA signals. - // Note that we intentionally do not use sigmap() on the DATA ports. RTLIL::SigSpec merged_data = wr_ports[last_i]->connections.at("\\DATA"); if (found_overlapping_bits) { log(" Creating logic for merging DATA and EN ports.\n"); - merge_en_data(merged_en, merged_data, sigmap(cell->connections.at("\\EN")), cell->connections.at("\\DATA")); + merge_en_data(merged_en, merged_data, sigmap(cell->connections.at("\\EN")), sigmap(cell->connections.at("\\DATA"))); } else { + RTLIL::SigSpec cell_en = sigmap(cell->connections.at("\\EN")); + RTLIL::SigSpec cell_data = sigmap(cell->connections.at("\\DATA")); for (int k = 0; k < int(en_bits.size()); k++) if (!active_bits_on_port[last_i][k]) { - merged_en.replace(k, cell->connections.at("\\EN").extract(k, 1)); - merged_data.replace(k, cell->connections.at("\\DATA").extract(k, 1)); + merged_en.replace(k, cell_en.extract(k, 1)); + merged_data.replace(k, cell_data.extract(k, 1)); } merged_en.optimize(); merged_data.optimize(); @@ -247,13 +450,28 @@ struct MemoryShareWorker last_port_by_addr[addr] = i; } + + // Clean up `wr_ports': remove all NULL entries + + std::vector wr_ports_with_nulls; + wr_ports_with_nulls.swap(wr_ports); + + for (auto cell : wr_ports_with_nulls) + if (cell != NULL) + wr_ports.push_back(cell); } + + // ------------- + // Setup and run + // ------------- + MemoryShareWorker(RTLIL::Design *design, RTLIL::Module *module) : design(design), module(module), sigmap(module) { std::map, std::vector>> memindex; + sigmap_xmux = sigmap; for (auto &it : module->cells) { RTLIL::Cell *cell = it.second; @@ -266,19 +484,27 @@ struct MemoryShareWorker if (cell->type == "$mux") { - RTLIL::SigSpec sig_a = sigmap(cell->connections.at("\\A")); - RTLIL::SigSpec sig_b = sigmap(cell->connections.at("\\B")); + RTLIL::SigSpec sig_a = sigmap_xmux(cell->connections.at("\\A")); + RTLIL::SigSpec sig_b = sigmap_xmux(cell->connections.at("\\B")); if (sig_a.is_fully_undef()) - sigmap.add(cell->connections.at("\\Y"), sig_b); + sigmap_xmux.add(cell->connections.at("\\Y"), sig_b); else if (sig_b.is_fully_undef()) - sigmap.add(cell->connections.at("\\Y"), sig_a); + sigmap_xmux.add(cell->connections.at("\\Y"), sig_a); + } + + if (cell->type == "$mux" || cell->type == "$pmux") + { + std::vector sig_y = sigmap(cell->connections.at("\\Y")); + for (int i = 0; i < int(sig_y.size()); i++) + sig_to_mux[sig_y[i]] = std::pair(cell, i); } } for (auto &it : memindex) { std::sort(it.second.first.begin(), it.second.first.end(), memcells_cmp); std::sort(it.second.second.begin(), it.second.second.end(), memcells_cmp); + translate_rd_feedback_to_en(it.first, it.second.first, it.second.second); consolidate_wr_by_addr(it.first, it.second.second); } } -- cgit v1.2.3 From 26f982ac0b69deb3cb9eda69e5cf687a69de4606 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 19 Jul 2014 15:32:14 +0200 Subject: Fixed bug in memory_share feedback-to-en code --- passes/memory/memory_share.cc | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) (limited to 'passes') diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index e2fa168c3..4af0ebdca 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -120,7 +120,7 @@ struct MemoryShareWorker void translate_rd_feedback_to_en(std::string memid, std::vector &rd_ports, std::vector &wr_ports) { - std::vector> async_rd_bits; + std::map>> async_rd_bits; std::map> muxtree_upstream_map; std::set non_feedback_nets; @@ -187,15 +187,16 @@ struct MemoryShareWorker if (cell->parameters.at("\\CLK_ENABLE").as_bool()) continue; + RTLIL::SigSpec sig_addr = sigmap(cell->connections.at("\\ADDR")); std::vector sig_data = sigmap(cell->connections.at("\\DATA")); for (int i = 0; i < int(sig_data.size()); i++) if (non_feedback_nets.count(sig_data[i])) goto not_pure_feedback_port; - async_rd_bits.resize(std::max(async_rd_bits.size(), sig_data.size())); + async_rd_bits[sig_addr].resize(std::max(async_rd_bits.size(), sig_data.size())); for (int i = 0; i < int(sig_data.size()); i++) - async_rd_bits[i].insert(sig_data[i]); + async_rd_bits[sig_addr][i].insert(sig_data[i]); not_pure_feedback_port:; } @@ -207,6 +208,10 @@ struct MemoryShareWorker for (auto cell : wr_ports) { + RTLIL::SigSpec sig_addr = sigmap_xmux(cell->connections.at("\\ADDR")); + if (!async_rd_bits.count(sig_addr)) + continue; + log(" Analyzing write port %s.\n", log_id(cell)); std::vector cell_data = cell->connections.at("\\DATA"); @@ -224,7 +229,7 @@ struct MemoryShareWorker conditions.insert(state); } - find_data_feedback(async_rd_bits.at(i), cell_data[i], state, conditions); + find_data_feedback(async_rd_bits.at(sig_addr).at(i), cell_data[i], state, conditions); cell_en[i] = conditions_to_logic(conditions, created_conditions); } @@ -333,6 +338,9 @@ struct MemoryShareWorker void consolidate_wr_by_addr(std::string memid, std::vector &wr_ports) { + if (wr_ports.size() <= 1) + return; + log("Consolidating write ports of memory %s by address:\n", log_id(memid)); std::map last_port_by_addr; -- cgit v1.2.3 From 297a0962ea399fcfa80656af2bc887c5725f5b82 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 19 Jul 2014 15:33:55 +0200 Subject: Added SAT-based write-port sharing to memory_share --- passes/memory/memory_share.cc | 180 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 180 insertions(+) (limited to 'passes') diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index 4af0ebdca..20ff16dea 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -18,7 +18,9 @@ */ #include "kernel/rtlil.h" +#include "kernel/satgen.h" #include "kernel/sigtools.h" +#include "kernel/modwalker.h" #include "kernel/register.h" #include "kernel/log.h" #include @@ -37,6 +39,8 @@ struct MemoryShareWorker RTLIL::Design *design; RTLIL::Module *module; SigMap sigmap, sigmap_xmux; + ModWalker modwalker; + CellTypes cone_ct; std::map> sig_to_mux; std::map>, RTLIL::SigBit> conditions_logic_cache; @@ -470,6 +474,167 @@ struct MemoryShareWorker } + // -------------------------------------------------------- + // Consolidate write ports using sat-based resource sharing + // -------------------------------------------------------- + + void consolidate_wr_using_sat(std::string memid, std::vector &wr_ports) + { + if (wr_ports.size() <= 1) + return; + + ezDefaultSAT ez; + SatGen satgen(&ez, &modwalker.sigmap); + + // find list of considered ports and port pairs + + std::set considered_ports; + std::set considered_port_pairs; + + for (int i = 0; i < int(wr_ports.size()); i++) { + std::vector bits = modwalker.sigmap(wr_ports[i]->connections.at("\\EN")); + for (auto bit : bits) + if (bit == RTLIL::State::S1) + goto port_is_always_active; + if (modwalker.has_drivers(bits)) + considered_ports.insert(i); + port_is_always_active:; + } + + log("Consolidating write ports of memory %s using sat-based resource sharing:\n", log_id(memid)); + + bool cache_clk_enable = false; + bool cache_clk_polarity = false; + RTLIL::SigSpec cache_clk; + + for (int i = 0; i < int(wr_ports.size()); i++) + { + RTLIL::Cell *cell = wr_ports.at(i); + + if (cell->parameters.at("\\CLK_ENABLE").as_bool() != cache_clk_enable || + (cache_clk_enable && (sigmap(cell->connections.at("\\CLK")) != cache_clk || + cell->parameters.at("\\CLK_POLARITY").as_bool() != cache_clk_polarity))) + { + cache_clk_enable = cell->parameters.at("\\CLK_ENABLE").as_bool(); + cache_clk_polarity = cell->parameters.at("\\CLK_POLARITY").as_bool(); + cache_clk = sigmap(cell->connections.at("\\CLK")); + } + else if (i > 0 && considered_ports.count(i-1) && considered_ports.count(i)) + considered_port_pairs.insert(i); + + if (cache_clk_enable) + log(" Port %d (%s) on %s %s: %s\n", i, log_id(cell), + cache_clk_polarity ? "posedge" : "negedge", log_signal(cache_clk), + considered_ports.count(i) ? "considered" : "not considered"); + else + log(" Port %d (%s) unclocked: %s\n", i, log_id(cell), + considered_ports.count(i) ? "considered" : "not considered"); + } + + if (considered_port_pairs.size() < 1) { + log(" No two subsequent ports in same clock domain considered -> nothing to consolidate.\n"); + return; + } + + // create SAT representation of common input cone of all considered EN signals + + std::set sat_cells; + std::set bits_queue; + std::map port_to_sat_variable; + + for (int i = 0; i < int(wr_ports.size()); i++) + if (considered_port_pairs.count(i) || considered_port_pairs.count(i+1)) + { + RTLIL::SigSpec sig = modwalker.sigmap(wr_ports[i]->connections.at("\\EN")); + port_to_sat_variable[i] = ez.expression(ez.OpOr, satgen.importSigSpec(sig)); + + std::vector bits = sig; + bits_queue.insert(bits.begin(), bits.end()); + } + + while (!bits_queue.empty()) + { + std::set portbits; + modwalker.get_drivers(portbits, bits_queue); + bits_queue.clear(); + + for (auto &pbit : portbits) + if (sat_cells.count(pbit.cell) == 0 && cone_ct.cell_known(pbit.cell->type)) { + std::set &cell_inputs = modwalker.cell_inputs[pbit.cell]; + bits_queue.insert(cell_inputs.begin(), cell_inputs.end()); + sat_cells.insert(pbit.cell); + } + } + + log(" Common input cone for all EN signals: %d cells.\n", int(sat_cells.size())); + + for (auto cell : sat_cells) + satgen.importCell(cell); + + log(" Size of unconstrained SAT problem: %d variables, %d clauses\n", ez.numCnfVariables(), ez.numCnfClauses()); + + // merge subsequent ports if possible + + for (int i = 0; i < int(wr_ports.size()); i++) + { + if (!considered_port_pairs.count(i)) + continue; + + if (ez.solve(port_to_sat_variable.at(i-1), port_to_sat_variable.at(i))) { + log(" According to SAT solver sharing of port %d with port %d is not possible.\n", i-1, i); + continue; + } + + log(" Merging port %d into port %d.\n", i-1, i); + port_to_sat_variable.at(i) = ez.OR(port_to_sat_variable.at(i-1), port_to_sat_variable.at(i)); + + RTLIL::SigSpec last_addr = wr_ports[i-1]->connections.at("\\ADDR"); + RTLIL::SigSpec last_data = wr_ports[i-1]->connections.at("\\DATA"); + std::vector last_en = modwalker.sigmap(wr_ports[i-1]->connections.at("\\EN")); + + RTLIL::SigSpec this_addr = wr_ports[i]->connections.at("\\ADDR"); + RTLIL::SigSpec this_data = wr_ports[i]->connections.at("\\DATA"); + std::vector this_en = modwalker.sigmap(wr_ports[i]->connections.at("\\EN")); + + RTLIL::SigBit this_en_active = module->ReduceOr(NEW_ID, this_en); + + wr_ports[i]->connections.at("\\ADDR") = module->Mux(NEW_ID, last_addr, this_addr, this_en_active); + wr_ports[i]->connections.at("\\DATA") = module->Mux(NEW_ID, last_data, this_data, this_en_active); + + std::map, int> groups_en; + RTLIL::SigSpec grouped_last_en, grouped_this_en, en; + RTLIL::Wire *grouped_en = module->new_wire(0, NEW_ID); + + for (int j = 0; j < int(this_en.size()); j++) { + std::pair key(last_en[j], this_en[j]); + if (!groups_en.count(key)) { + grouped_last_en.append_bit(last_en[j]); + grouped_this_en.append_bit(this_en[j]); + groups_en[key] = grouped_en->width; + grouped_en->width++; + } + en.append(RTLIL::SigSpec(grouped_en, 1, groups_en[key])); + } + + module->addMux(NEW_ID, grouped_last_en, grouped_this_en, this_en_active, grouped_en); + wr_ports[i]->connections.at("\\EN") = en; + + module->cells.erase(wr_ports[i-1]->name); + delete wr_ports[i-1]; + wr_ports[i-1] = NULL; + } + + // Clean up `wr_ports': remove all NULL entries + + std::vector wr_ports_with_nulls; + wr_ports_with_nulls.swap(wr_ports); + + for (auto cell : wr_ports_with_nulls) + if (cell != NULL) + wr_ports.push_back(cell); + } + + // ------------- // Setup and run // ------------- @@ -515,6 +680,21 @@ struct MemoryShareWorker translate_rd_feedback_to_en(it.first, it.second.first, it.second.second); consolidate_wr_by_addr(it.first, it.second.second); } + + cone_ct.setup_internals(); + cone_ct.cell_types.erase("$mul"); + cone_ct.cell_types.erase("$mod"); + cone_ct.cell_types.erase("$div"); + cone_ct.cell_types.erase("$pow"); + cone_ct.cell_types.erase("$shl"); + cone_ct.cell_types.erase("$shr"); + cone_ct.cell_types.erase("$sshl"); + cone_ct.cell_types.erase("$sshr"); + + modwalker.setup(design, module, &cone_ct); + + for (auto &it : memindex) + consolidate_wr_using_sat(it.first, it.second.second); } }; -- cgit v1.2.3 From e0a819dbe507c90e201279db317c2251b3c691eb Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 19 Jul 2014 15:34:14 +0200 Subject: More verbose memory_share help message --- passes/memory/memory_share.cc | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'passes') diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index 20ff16dea..cde5f2183 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -708,6 +708,23 @@ struct MemorySharePass : public Pass { log("\n"); log("This pass merges share-able memory ports into single memory ports.\n"); log("\n"); + log("The following methods are used to consolidate the number of memory ports:\n"); + log("\n"); + log(" - When write ports are connected to async read ports accessing the same\n"); + log(" address, then this feedback path is converted to a write port with\n"); + log(" byte/part enable signals.\n"); + log("\n"); + log(" - When multiple write ports access the same adress then this is converted\n"); + log(" to a single write port with a more complex data and/or enable logic path.\n"); + log("\n"); + log(" - When multiple write ports are never accessed at the same time (a SAT\n"); + log(" solver is used to determine this), then the ports are merged into a single\n"); + log(" write port.\n"); + log("\n"); + log("Note that in addition to the algorithms implemented in this pass, the $memrd\n"); + log("and $memwr cells are also subject to generic resource sharing passes (and other\n"); + log("optimizations) such as opt_share.\n"); + log("\n"); } virtual void execute(std::vector args, RTLIL::Design *design) { log_header("Executing MEMORY_SHARE pass (consolidating $memrc/$memwr cells).\n"); -- cgit v1.2.3 From efd9604dfb92fda05c3efea67b7c32d812717fa8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 19 Jul 2014 15:46:11 +0200 Subject: Improved memory_share log messages --- passes/memory/memory_share.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'passes') diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index cde5f2183..dc015f969 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -208,7 +208,7 @@ struct MemoryShareWorker if (async_rd_bits.empty()) return; - log("Populating enable bits on write ports of memory %s with aync read feedback:\n", log_id(memid)); + log("Populating enable bits on write ports of memory %s.%s with aync read feedback:\n", log_id(module), log_id(memid)); for (auto cell : wr_ports) { @@ -345,7 +345,7 @@ struct MemoryShareWorker if (wr_ports.size() <= 1) return; - log("Consolidating write ports of memory %s by address:\n", log_id(memid)); + log("Consolidating write ports of memory %s.%s by address:\n", log_id(module), log_id(memid)); std::map last_port_by_addr; std::vector> active_bits_on_port; @@ -501,7 +501,7 @@ struct MemoryShareWorker port_is_always_active:; } - log("Consolidating write ports of memory %s using sat-based resource sharing:\n", log_id(memid)); + log("Consolidating write ports of memory %s.%s using sat-based resource sharing:\n", log_id(module), log_id(memid)); bool cache_clk_enable = false; bool cache_clk_polarity = false; -- cgit v1.2.3 From 2278995bd8097558396ffdd3a5d24e324f22faa7 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 19 Jul 2014 20:54:32 +0200 Subject: Started to implement real resource sharing --- passes/sat/Makefile.inc | 1 + passes/sat/share.cc | 443 ++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 444 insertions(+) create mode 100644 passes/sat/share.cc (limited to 'passes') diff --git a/passes/sat/Makefile.inc b/passes/sat/Makefile.inc index 4fa6bf0d4..9aa806429 100644 --- a/passes/sat/Makefile.inc +++ b/passes/sat/Makefile.inc @@ -4,4 +4,5 @@ OBJS += passes/sat/freduce.o OBJS += passes/sat/eval.o OBJS += passes/sat/miter.o OBJS += passes/sat/expose.o +OBJS += passes/sat/share.o diff --git a/passes/sat/share.cc b/passes/sat/share.cc new file mode 100644 index 000000000..c04be7c8d --- /dev/null +++ b/passes/sat/share.cc @@ -0,0 +1,443 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/rtlil.h" +#include "kernel/satgen.h" +#include "kernel/sigtools.h" +#include "kernel/modwalker.h" +#include "kernel/register.h" +#include "kernel/log.h" +#include + +struct ShareWorkerConfig +{ + bool opt_all; +}; + +struct ShareWorker +{ + ShareWorkerConfig config; + RTLIL::Design *design; + RTLIL::Module *module; + + CellTypes cone_ct; + ModWalker modwalker; + + // --------------------------------------------------- + // Find shareable cells and compatible groups of cells + // --------------------------------------------------- + + std::set shareable_cells; + + void find_shareable_cells() + { + std::vector candidates; + + for (auto &it : module->cells) + { + RTLIL::Cell *cell = it.second; + + if (!design->selected(module, cell) || !modwalker.ct.cell_known(cell->type)) + continue; + + if (config.opt_all) { + candidates.push_back(cell); + continue; + } + + if (cell->type == "$memrd") { + if (!cell->parameters.at("\\CLK_ENABLE").as_bool()) + candidates.push_back(cell); + continue; + } + + if (cell->type == "$mul" || cell->type == "$div" || cell->type == "$mod") { + if (cell->parameters.at("\\Y_WIDTH").as_int() > 4) + candidates.push_back(cell); + continue; + } + + if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr") { + if (cell->parameters.at("\\Y_WIDTH").as_int() > 8) + candidates.push_back(cell); + continue; + } + } + + for (auto cell : candidates) + { + std::set driven_bits; + modwalker.get_consumers(driven_bits, modwalker.cell_outputs[cell]); + for (auto bit : driven_bits) { + if (bit.cell->type != "$mux" && bit.cell->type != "$pmux") + goto skip_candidate; + if (bit.port != "\\A" && bit.port != "\\B") + goto skip_candidate; + } + if (!modwalker.has_outputs(modwalker.cell_outputs[cell])) + shareable_cells.insert(cell); + skip_candidate:; + } + } + + bool is_shareable_pair(RTLIL::Cell *c1, RTLIL::Cell *c2) + { + if (c1->type != c2->type) + return false; + + if (c1->type == "$memrd") + { + if (c1->parameters.at("\\MEMID").decode_string() != c2->parameters.at("\\MEMID").decode_string()) + return false; + + return true; + } + + if (c1->type == "$mul" || c1->type == "$div" || c1->type == "$mod" || + c1->type == "$shl" || c1->type == "$shr" || c1->type == "$sshl" || c1->type == "$sshr") + { + if (c1->parameters.at("\\A_SIGNED").as_bool() != c2->parameters.at("\\A_SIGNED").as_bool()) + return false; + + if (c1->parameters.at("\\B_SIGNED").as_bool() != c2->parameters.at("\\B_SIGNED").as_bool()) + return false; + + int a1_width = c1->parameters.at("\\A_WIDTH").as_int(); + int b1_width = c1->parameters.at("\\B_WIDTH").as_int(); + int y1_width = c1->parameters.at("\\Y_WIDTH").as_int(); + + int a2_width = c2->parameters.at("\\A_WIDTH").as_int(); + int b2_width = c2->parameters.at("\\B_WIDTH").as_int(); + int y2_width = c2->parameters.at("\\Y_WIDTH").as_int(); + + if (std::max(a1_width, a2_width) > 2 * std::min(a1_width, a2_width)) return false; + if (std::max(b1_width, b2_width) > 2 * std::min(b1_width, b2_width)) return false; + if (std::max(y1_width, y2_width) > 2 * std::min(y1_width, y2_width)) return false; + + return true; + } + + for (auto &it : c1->parameters) + if (c2->parameters.count(it.first) == 0 || c2->parameters.at(it.first) != it.second) + return false; + + for (auto &it : c2->parameters) + if (c1->parameters.count(it.first) == 0 || c1->parameters.at(it.first) != it.second) + return false; + + return true; + } + + void find_shareable_partners(std::vector &results, RTLIL::Cell *cell) + { + results.clear(); + for (auto c : shareable_cells) + if (c != cell && is_shareable_pair(c, cell)) + results.push_back(c); + } + + + // -------------------------------------------------------- + // Finding control inputs and activation pattern for a cell + // -------------------------------------------------------- + + std::map>> activation_patterns_cache; + + void follow_mux_data_cone(std::set> &patterns, + std::set> &state, RTLIL::SigSpec signal) + { + std::set consumers; + std::map> consumers_by_cell; + + if (modwalker.has_outputs(signal)) + goto signal_outside_mux_tree; + + modwalker.get_consumers(consumers, signal); + for (auto &bit : consumers) { + if ((bit.cell->type != "$mux" && bit.cell->type != "$pmux") || bit.port == "\\S") + goto signal_outside_mux_tree; + consumers_by_cell[bit.cell].insert(bit); + } + + if (0) { + signal_outside_mux_tree:; + RTLIL::SigSpec pattern_first, pattern_second; + for (auto &bit : state) { + pattern_first.append_bit(bit.first); + pattern_second.append_bit(bit.second); + } + patterns.insert(std::pair(pattern_first, pattern_second.as_const())); + return; + } + + for (auto &it : consumers_by_cell) + { + RTLIL::Cell *cell = it.first; + log_assert(cell->type == "$mux" || cell->type == "$pmux"); + + int width = cell->parameters.at("\\WIDTH").as_int(); + std::set used_in_b_parts; + bool used_in_a = false; + + for (auto &bit : it.second) { + if (bit.port == "\\A") + used_in_a = true; + else if (bit.port == "\\B") + used_in_b_parts.insert(bit.offset / width); + else + log_abort(); + } + + std::vector sig_s = modwalker.sigmap(cell->connections.at("\\S")).to_sigbit_vector(); + + if (used_in_a) { + std::set> new_state = state; + for (auto &bit : sig_s) { + std::pair this_state(bit, RTLIL::State::S0); + std::pair this_inv_state(bit, RTLIL::State::S1); + if (new_state.count(this_inv_state)) + goto conflict_in_a_port; + new_state.insert(this_state); + } + follow_mux_data_cone(patterns, new_state, modwalker.sigmap(cell->connections.at("\\Y"))); + conflict_in_a_port:; + } + + for (int part_idx : used_in_b_parts) { + std::set> new_state = state; + std::pair this_state(sig_s.at(part_idx), RTLIL::State::S1); + std::pair this_inv_state(sig_s.at(part_idx), RTLIL::State::S0); + if (new_state.count(this_inv_state)) + goto conflict_in_b_port; + new_state.insert(this_state); + follow_mux_data_cone(patterns, new_state, modwalker.sigmap(cell->connections.at("\\Y"))); + conflict_in_b_port:; + } + } + } + + const std::set> &find_cell_activation_patterns(RTLIL::Cell *cell) + { + if (activation_patterns_cache.count(cell)) + return activation_patterns_cache.at(cell); + + std::set> state; + RTLIL::SigSpec cell_output_signal; + + for (auto &bit : modwalker.cell_outputs[cell]) + cell_output_signal.append_bit(bit); + + follow_mux_data_cone(activation_patterns_cache[cell], state, cell_output_signal); + return activation_patterns_cache.at(cell); + } + + RTLIL::SigSpec bits_from_activation_patterns(const std::set> &activation_patterns) + { + std::set all_bits; + for (auto &it : activation_patterns) { + std::vector bits = it.first; + all_bits.insert(bits.begin(), bits.end()); + } + + RTLIL::SigSpec signal; + for (auto &bit : all_bits) + signal.append_bit(bit); + + return signal; + } + + + // ------------- + // Setup and run + // ------------- + + ShareWorker(ShareWorkerConfig config, RTLIL::Design *design, RTLIL::Module *module) : + config(config), design(design), module(module) + { + cone_ct.setup_internals(); + cone_ct.cell_types.erase("$mul"); + cone_ct.cell_types.erase("$mod"); + cone_ct.cell_types.erase("$div"); + cone_ct.cell_types.erase("$pow"); + cone_ct.cell_types.erase("$shl"); + cone_ct.cell_types.erase("$shr"); + cone_ct.cell_types.erase("$sshl"); + cone_ct.cell_types.erase("$sshr"); + + modwalker.setup(design, module); + find_shareable_cells(); + + if (shareable_cells.size() < 2) + return; + + log("Found %d cells in module %s that may be considered for resource sharing.\n", + int(shareable_cells.size()), log_id(module)); + + while (!shareable_cells.empty()) + { + RTLIL::Cell *cell = *shareable_cells.begin(); + shareable_cells.erase(cell); + + log(" Analyzing resource sharing options for %s:\n", log_id(cell)); + + std::vector candidates; + find_shareable_partners(candidates, cell); + + if (candidates.empty()) { + log(" No candidates found.\n"); + continue; + } + + log(" Found %d candidates:", int(candidates.size())); + for (auto c : candidates) + log(" %s", log_id(c)); + log("\n"); + + const std::set> &cell_activation_patterns = find_cell_activation_patterns(cell); + RTLIL::SigSpec cell_activation_signals = bits_from_activation_patterns(cell_activation_patterns); + + log(" Found %d activation_patterns using ctrl signal %s.\n", int(cell_activation_patterns.size()), log_signal(cell_activation_signals)); + + if (cell_activation_patterns.empty()) + continue; + + for (auto other_cell : candidates) + { + log(" Analyzing resource sharing with %s:\n", log_id(other_cell)); + + const std::set> &other_cell_activation_patterns = find_cell_activation_patterns(other_cell); + RTLIL::SigSpec other_cell_activation_signals = bits_from_activation_patterns(other_cell_activation_patterns); + + log(" Found %d activation_patterns using ctrl signal %s.\n", + int(other_cell_activation_patterns.size()), log_signal(other_cell_activation_signals)); + + if (other_cell_activation_patterns.empty()) + continue; + + ezDefaultSAT ez; + SatGen satgen(&ez, &modwalker.sigmap); + + std::set sat_cells; + std::set bits_queue; + + std::vector cell_active, other_cell_active; + RTLIL::SigSpec all_ctrl_signals; + + for (auto &p : cell_activation_patterns) { + log(" Activation pattern for cell %s: %s = %s\n", log_id(cell), log_signal(p.first), log_signal(p.second)); + cell_active.push_back(ez.vec_eq(satgen.importSigSpec(p.first), satgen.importSigSpec(p.second))); + all_ctrl_signals.append(p.first); + } + + for (auto &p : other_cell_activation_patterns) { + log(" Activation pattern for cell %s: %s = %s\n", log_id(other_cell), log_signal(p.first), log_signal(p.second)); + other_cell_active.push_back(ez.vec_eq(satgen.importSigSpec(p.first), satgen.importSigSpec(p.second))); + all_ctrl_signals.append(p.first); + } + + for (auto &bit : cell_activation_signals.to_sigbit_vector()) + bits_queue.insert(bit); + + for (auto &bit : other_cell_activation_signals.to_sigbit_vector()) + bits_queue.insert(bit); + + while (!bits_queue.empty()) + { + std::set portbits; + modwalker.get_drivers(portbits, bits_queue); + bits_queue.clear(); + + for (auto &pbit : portbits) + if (sat_cells.count(pbit.cell) == 0 && cone_ct.cell_known(pbit.cell->type)) { + // log(" Adding cell %s (%s) to SAT problem.\n", log_id(pbit.cell), log_id(pbit.cell->type)); + satgen.importCell(pbit.cell); + sat_cells.insert(pbit.cell); + } + } + + all_ctrl_signals.sort_and_unify(); + std::vector sat_model = satgen.importSigSpec(all_ctrl_signals); + std::vector sat_model_values; + + ez.assume(ez.AND(ez.expression(ez.OpOr, cell_active), ez.expression(ez.OpOr, other_cell_active))); + + log(" Size of SAT problem: %d cells, %d variables, %d clauses\n", + int(sat_cells.size()), ez.numCnfVariables(), ez.numCnfClauses()); + + if (ez.solve(sat_model, sat_model_values)) { + log(" According to the SAT solver this pair of cells can not be shared.\n"); + log(" Model from SAT solver: %s = %d'", log_signal(all_ctrl_signals), int(sat_model_values.size())); + for (int i = int(sat_model_values.size())-1; i >= 0; i--) + log("%c", sat_model_values[i] ? '1' : '0'); + log("\n"); + continue; + } + + log(" According to the SAT solver this pair of cells can be shared.\n"); + log(" WARNING: Actually sharing the cells is not implemented yet.\n"); + shareable_cells.erase(other_cell); + break; + } + } + } +}; + +struct SharePass : public Pass { + SharePass() : Pass("share", "perform sat-based resource sharing") { } + virtual void help() + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" share [options] [selection]\n"); + log("\n"); + log("This pass merges shareable resources into a single resource. A SAT solver\n"); + log("is used to determine if two resources are share-able.\n"); + log("\n"); + log(" -all\n"); + log(" Per default the selection of cells that is considered for sharing is\n"); + log(" narrowed using some built-in heuristics. With this option all selected\n"); + log(" cells are considered for resource sharing.\n"); + log("\n"); + log(" IMPORTANT NOTE: If the -all option is used then no cells with internal\n"); + log(" state must be selected!\n"); + log("\n"); + } + virtual void execute(std::vector args, RTLIL::Design *design) + { + ShareWorkerConfig config; + config.opt_all = false; + + log_header("Executing SHARE pass (SAT-based resource sharing).\n"); + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) { + if (args[argidx] == "-all") { + config.opt_all = true; + continue; + } + break; + } + extra_args(args, argidx, design); + + for (auto &mod_it : design->modules) + if (design->selected(mod_it.second)) + ShareWorker(config, design, mod_it.second); + } +} SharePass; + -- cgit v1.2.3 From 15fd615da5a119b4ee9cded9f44ae36fd66820f7 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 20 Jul 2014 03:03:04 +0200 Subject: Progress in "share" pass --- passes/sat/share.cc | 75 +++++++++++++++++++++++++++++++++++++++-------------- 1 file changed, 56 insertions(+), 19 deletions(-) (limited to 'passes') diff --git a/passes/sat/share.cc b/passes/sat/share.cc index c04be7c8d..aad53e13c 100644 --- a/passes/sat/share.cc +++ b/passes/sat/share.cc @@ -27,7 +27,9 @@ struct ShareWorkerConfig { - bool opt_all; + bool opt_force; + bool opt_aggressive; + bool opt_fast; }; struct ShareWorker @@ -56,7 +58,7 @@ struct ShareWorker if (!design->selected(module, cell) || !modwalker.ct.cell_known(cell->type)) continue; - if (config.opt_all) { + if (config.opt_force) { candidates.push_back(cell); continue; } @@ -68,13 +70,19 @@ struct ShareWorker } if (cell->type == "$mul" || cell->type == "$div" || cell->type == "$mod") { - if (cell->parameters.at("\\Y_WIDTH").as_int() > 4) + if (config.opt_aggressive || cell->parameters.at("\\Y_WIDTH").as_int() > 4) candidates.push_back(cell); continue; } if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr") { - if (cell->parameters.at("\\Y_WIDTH").as_int() > 8) + if (config.opt_aggressive || cell->parameters.at("\\Y_WIDTH").as_int() > 8) + candidates.push_back(cell); + continue; + } + + if (cell->type == "$add" || cell->type == "$sub") { + if (config.opt_aggressive || cell->parameters.at("\\Y_WIDTH").as_int() > 10) candidates.push_back(cell); continue; } @@ -109,7 +117,7 @@ struct ShareWorker return true; } - if (c1->type == "$mul" || c1->type == "$div" || c1->type == "$mod" || + if (c1->type == "$mul" || c1->type == "$div" || c1->type == "$mod" || c1->type == "$add" || c1->type == "$sub" || c1->type == "$shl" || c1->type == "$shr" || c1->type == "$sshl" || c1->type == "$sshr") { if (c1->parameters.at("\\A_SIGNED").as_bool() != c2->parameters.at("\\A_SIGNED").as_bool()) @@ -118,17 +126,20 @@ struct ShareWorker if (c1->parameters.at("\\B_SIGNED").as_bool() != c2->parameters.at("\\B_SIGNED").as_bool()) return false; - int a1_width = c1->parameters.at("\\A_WIDTH").as_int(); - int b1_width = c1->parameters.at("\\B_WIDTH").as_int(); - int y1_width = c1->parameters.at("\\Y_WIDTH").as_int(); + if (!config.opt_aggressive) + { + int a1_width = c1->parameters.at("\\A_WIDTH").as_int(); + int b1_width = c1->parameters.at("\\B_WIDTH").as_int(); + int y1_width = c1->parameters.at("\\Y_WIDTH").as_int(); - int a2_width = c2->parameters.at("\\A_WIDTH").as_int(); - int b2_width = c2->parameters.at("\\B_WIDTH").as_int(); - int y2_width = c2->parameters.at("\\Y_WIDTH").as_int(); + int a2_width = c2->parameters.at("\\A_WIDTH").as_int(); + int b2_width = c2->parameters.at("\\B_WIDTH").as_int(); + int y2_width = c2->parameters.at("\\Y_WIDTH").as_int(); - if (std::max(a1_width, a2_width) > 2 * std::min(a1_width, a2_width)) return false; - if (std::max(b1_width, b2_width) > 2 * std::min(b1_width, b2_width)) return false; - if (std::max(y1_width, y2_width) > 2 * std::min(y1_width, y2_width)) return false; + if (std::max(a1_width, a2_width) > 2 * std::min(a1_width, a2_width)) return false; + if (std::max(b1_width, b2_width) > 2 * std::min(b1_width, b2_width)) return false; + if (std::max(y1_width, y2_width) > 2 * std::min(y1_width, y2_width)) return false; + } return true; } @@ -365,10 +376,15 @@ struct ShareWorker for (auto &pbit : portbits) if (sat_cells.count(pbit.cell) == 0 && cone_ct.cell_known(pbit.cell->type)) { + if (config.opt_fast && modwalker.cell_outputs[pbit.cell].size() >= 4) + continue; // log(" Adding cell %s (%s) to SAT problem.\n", log_id(pbit.cell), log_id(pbit.cell->type)); satgen.importCell(pbit.cell); sat_cells.insert(pbit.cell); } + + if (config.opt_fast && sat_cells.size() > 100) + break; } all_ctrl_signals.sort_and_unify(); @@ -409,26 +425,47 @@ struct SharePass : public Pass { log("This pass merges shareable resources into a single resource. A SAT solver\n"); log("is used to determine if two resources are share-able.\n"); log("\n"); - log(" -all\n"); + log(" -force\n"); log(" Per default the selection of cells that is considered for sharing is\n"); - log(" narrowed using some built-in heuristics. With this option all selected\n"); + log(" narrowed using a list of cell types. With this option all selected\n"); log(" cells are considered for resource sharing.\n"); log("\n"); log(" IMPORTANT NOTE: If the -all option is used then no cells with internal\n"); log(" state must be selected!\n"); log("\n"); + log(" -aggressive\n"); + log(" Per default some heuristics are used to reduce the number of cells\n"); + log(" considered for resource sharing to only large resources. This options\n"); + log(" turns this heuristics off, resulting in much more cells being considered\n"); + log(" for resource sharing.\n"); + log("\n"); + log(" -fast\n"); + log(" Only consider comparable primitive control logic in SAT solving, resulting\n"); + log(" in much easier SAT problems at the cost of maybe missing some oportunities\n"); + log(" for resource sharing.\n"); + log("\n"); } virtual void execute(std::vector args, RTLIL::Design *design) { ShareWorkerConfig config; - config.opt_all = false; + config.opt_force = false; + config.opt_aggressive = false; + config.opt_fast = false; log_header("Executing SHARE pass (SAT-based resource sharing).\n"); size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { - if (args[argidx] == "-all") { - config.opt_all = true; + if (args[argidx] == "-force") { + config.opt_force = true; + continue; + } + if (args[argidx] == "-aggressive") { + config.opt_aggressive = true; + continue; + } + if (args[argidx] == "-fast") { + config.opt_fast = true; continue; } break; -- cgit v1.2.3 From 8819493db4e2a02cef5d0ee751ff56605db5995b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 20 Jul 2014 10:36:46 +0200 Subject: Progress in "share" pass --- passes/sat/share.cc | 297 ++++++++++++++++++++++++++++++++-------------------- 1 file changed, 185 insertions(+), 112 deletions(-) (limited to 'passes') diff --git a/passes/sat/share.cc b/passes/sat/share.cc index aad53e13c..a1510a599 100644 --- a/passes/sat/share.cc +++ b/passes/sat/share.cc @@ -38,9 +38,77 @@ struct ShareWorker RTLIL::Design *design; RTLIL::Module *module; - CellTypes cone_ct; + CellTypes fwd_ct, cone_ct; ModWalker modwalker; + + // ------------------------------------------------------------------------------ + // Find terminal bits -- i.e. bits that do not (exclusively) feed into a mux tree + // ------------------------------------------------------------------------------ + + std::set terminal_bits; + + void find_terminal_bits() + { + std::set queue_strong_bits, queue_weak_bits; + std::set visited_cells; + + queue_weak_bits.insert(modwalker.signal_outputs.begin(), modwalker.signal_outputs.end()); + + for (auto &it : module->cells) + { + RTLIL::Cell *cell = it.second; + + if (cell->type == "$mux" || cell->type == "$pmux") + { + std::vector bits = modwalker.sigmap(cell->connections.at("\\S")); + queue_strong_bits.insert(bits.begin(), bits.end()); + } + else if (!fwd_ct.cell_known(cell->type)) + { + std::set &bits = modwalker.cell_inputs[cell]; + queue_weak_bits.insert(bits.begin(), bits.end()); + } + } + + terminal_bits.insert(queue_strong_bits.begin(), queue_strong_bits.end()); + terminal_bits.insert(queue_weak_bits.begin(), queue_weak_bits.end()); + + while (!queue_strong_bits.empty()) + { + std::set portbits; + modwalker.get_drivers(portbits, queue_strong_bits); + queue_strong_bits.clear(); + + for (auto &pbit : portbits) + if (fwd_ct.cell_known(pbit.cell->type) && visited_cells.count(pbit.cell) == 0) { + std::set &bits = modwalker.cell_inputs[pbit.cell]; + terminal_bits.insert(bits.begin(), bits.end()); + queue_strong_bits.insert(bits.begin(), bits.end()); + visited_cells.insert(pbit.cell); + } + } + + while (!queue_weak_bits.empty()) + { + std::set portbits; + modwalker.get_drivers(portbits, queue_weak_bits); + queue_weak_bits.clear(); + + for (auto &pbit : portbits) { + if (pbit.cell->type == "$mux" || pbit.cell->type == "$pmux") + continue; + if (fwd_ct.cell_known(pbit.cell->type) && visited_cells.count(pbit.cell) == 0) { + std::set &bits = modwalker.cell_inputs[pbit.cell]; + terminal_bits.insert(bits.begin(), bits.end()); + queue_weak_bits.insert(bits.begin(), bits.end()); + visited_cells.insert(pbit.cell); + } + } + } + } + + // --------------------------------------------------- // Find shareable cells and compatible groups of cells // --------------------------------------------------- @@ -49,8 +117,6 @@ struct ShareWorker void find_shareable_cells() { - std::vector candidates; - for (auto &it : module->cells) { RTLIL::Cell *cell = it.second; @@ -58,50 +124,43 @@ struct ShareWorker if (!design->selected(module, cell) || !modwalker.ct.cell_known(cell->type)) continue; + for (auto &bit : modwalker.cell_outputs[cell]) + if (terminal_bits.count(bit)) + goto not_a_muxed_cell; + + if (0) + not_a_muxed_cell: + continue; + if (config.opt_force) { - candidates.push_back(cell); + shareable_cells.insert(cell); continue; } if (cell->type == "$memrd") { if (!cell->parameters.at("\\CLK_ENABLE").as_bool()) - candidates.push_back(cell); + shareable_cells.insert(cell); continue; } if (cell->type == "$mul" || cell->type == "$div" || cell->type == "$mod") { if (config.opt_aggressive || cell->parameters.at("\\Y_WIDTH").as_int() > 4) - candidates.push_back(cell); + shareable_cells.insert(cell); continue; } if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr") { if (config.opt_aggressive || cell->parameters.at("\\Y_WIDTH").as_int() > 8) - candidates.push_back(cell); + shareable_cells.insert(cell); continue; } if (cell->type == "$add" || cell->type == "$sub") { if (config.opt_aggressive || cell->parameters.at("\\Y_WIDTH").as_int() > 10) - candidates.push_back(cell); + shareable_cells.insert(cell); continue; } } - - for (auto cell : candidates) - { - std::set driven_bits; - modwalker.get_consumers(driven_bits, modwalker.cell_outputs[cell]); - for (auto bit : driven_bits) { - if (bit.cell->type != "$mux" && bit.cell->type != "$pmux") - goto skip_candidate; - if (bit.port != "\\A" && bit.port != "\\B") - goto skip_candidate; - } - if (!modwalker.has_outputs(modwalker.cell_outputs[cell])) - shareable_cells.insert(cell); - skip_candidate:; - } } bool is_shareable_pair(RTLIL::Cell *c1, RTLIL::Cell *c2) @@ -170,77 +229,28 @@ struct ShareWorker std::map>> activation_patterns_cache; - void follow_mux_data_cone(std::set> &patterns, - std::set> &state, RTLIL::SigSpec signal) + bool sort_check_pattern(std::pair &p) { - std::set consumers; - std::map> consumers_by_cell; - - if (modwalker.has_outputs(signal)) - goto signal_outside_mux_tree; + std::map p_bits; - modwalker.get_consumers(consumers, signal); - for (auto &bit : consumers) { - if ((bit.cell->type != "$mux" && bit.cell->type != "$pmux") || bit.port == "\\S") - goto signal_outside_mux_tree; - consumers_by_cell[bit.cell].insert(bit); - } - - if (0) { - signal_outside_mux_tree:; - RTLIL::SigSpec pattern_first, pattern_second; - for (auto &bit : state) { - pattern_first.append_bit(bit.first); - pattern_second.append_bit(bit.second); - } - patterns.insert(std::pair(pattern_first, pattern_second.as_const())); - return; + std::vector p_first_bits = p.first; + for (int i = 0; i < SIZE(p_first_bits); i++) { + RTLIL::SigBit b = p_first_bits[i]; + RTLIL::State v = p.second.bits[i]; + if (p_bits.count(b) && p_bits.at(b) != v) + return false; + p_bits[b] = v; } - for (auto &it : consumers_by_cell) - { - RTLIL::Cell *cell = it.first; - log_assert(cell->type == "$mux" || cell->type == "$pmux"); - - int width = cell->parameters.at("\\WIDTH").as_int(); - std::set used_in_b_parts; - bool used_in_a = false; - - for (auto &bit : it.second) { - if (bit.port == "\\A") - used_in_a = true; - else if (bit.port == "\\B") - used_in_b_parts.insert(bit.offset / width); - else - log_abort(); - } - - std::vector sig_s = modwalker.sigmap(cell->connections.at("\\S")).to_sigbit_vector(); + p.first = RTLIL::SigSpec(); + p.second.bits.clear(); - if (used_in_a) { - std::set> new_state = state; - for (auto &bit : sig_s) { - std::pair this_state(bit, RTLIL::State::S0); - std::pair this_inv_state(bit, RTLIL::State::S1); - if (new_state.count(this_inv_state)) - goto conflict_in_a_port; - new_state.insert(this_state); - } - follow_mux_data_cone(patterns, new_state, modwalker.sigmap(cell->connections.at("\\Y"))); - conflict_in_a_port:; - } - - for (int part_idx : used_in_b_parts) { - std::set> new_state = state; - std::pair this_state(sig_s.at(part_idx), RTLIL::State::S1); - std::pair this_inv_state(sig_s.at(part_idx), RTLIL::State::S0); - if (new_state.count(this_inv_state)) - goto conflict_in_b_port; - new_state.insert(this_state); - follow_mux_data_cone(patterns, new_state, modwalker.sigmap(cell->connections.at("\\Y"))); - conflict_in_b_port:; - } + for (auto &it : p_bits) { + p.first.append_bit(it.first); + p.second.bits.push_back(it.second); } + + return true; } const std::set> &find_cell_activation_patterns(RTLIL::Cell *cell) @@ -248,14 +258,68 @@ struct ShareWorker if (activation_patterns_cache.count(cell)) return activation_patterns_cache.at(cell); - std::set> state; - RTLIL::SigSpec cell_output_signal; + const std::set &cell_out_bits = modwalker.cell_outputs[cell]; + std::set driven_cells; - for (auto &bit : modwalker.cell_outputs[cell]) - cell_output_signal.append_bit(bit); + for (auto &bit : cell_out_bits) + { + if (terminal_bits.count(bit)) { + // Terminal cells are always active: unconditional activation pattern + activation_patterns_cache[cell].insert(std::pair()); + return activation_patterns_cache.at(cell); + } + for (auto &pbit : modwalker.signal_consumers[bit]) { + log_assert(fwd_ct.cell_known(pbit.cell->type)); + driven_cells.insert(pbit.cell); + } + } + + for (auto c : driven_cells) + { + const std::set> &c_patterns = find_cell_activation_patterns(c); - follow_mux_data_cone(activation_patterns_cache[cell], state, cell_output_signal); - return activation_patterns_cache.at(cell); + if (c->type == "$mux" || c->type == "$pmux") + { + bool used_in_a = false; + std::set used_in_b_parts; + + int width = c->parameters.at("\\WIDTH").as_int(); + std::vector sig_a = modwalker.sigmap(c->connections.at("\\A")); + std::vector sig_b = modwalker.sigmap(c->connections.at("\\B")); + std::vector sig_s = modwalker.sigmap(c->connections.at("\\S")); + + for (auto &bit : sig_a) + if (cell_out_bits.count(bit)) + used_in_a = true; + + for (int i = 0; i < SIZE(sig_b); i++) + if (cell_out_bits.count(sig_b[i])) + used_in_b_parts.insert(i / width); + + if (used_in_a) + for (auto p : c_patterns) { + for (int i = 0; i < SIZE(sig_s); i++) + p.first.append_bit(sig_s[i]), p.second.bits.push_back(RTLIL::State::S0); + if (sort_check_pattern(p)) + activation_patterns_cache[cell].insert(p); + } + + for (int idx : used_in_b_parts) + for (auto p : c_patterns) { + p.first.append_bit(sig_s[idx]), p.second.bits.push_back(RTLIL::State::S1); + if (sort_check_pattern(p)) + activation_patterns_cache[cell].insert(p); + } + } + else + { + // Not a mux: just copy the activation patterns + for (auto &p : c_patterns) + activation_patterns_cache[cell].insert(p); + } + } + + return activation_patterns_cache[cell]; } RTLIL::SigSpec bits_from_activation_patterns(const std::set> &activation_patterns) @@ -281,6 +345,8 @@ struct ShareWorker ShareWorker(ShareWorkerConfig config, RTLIL::Design *design, RTLIL::Module *module) : config(config), design(design), module(module) { + fwd_ct.setup_internals(); + cone_ct.setup_internals(); cone_ct.cell_types.erase("$mul"); cone_ct.cell_types.erase("$mod"); @@ -292,13 +358,15 @@ struct ShareWorker cone_ct.cell_types.erase("$sshr"); modwalker.setup(design, module); + + find_terminal_bits(); find_shareable_cells(); if (shareable_cells.size() < 2) return; log("Found %d cells in module %s that may be considered for resource sharing.\n", - int(shareable_cells.size()), log_id(module)); + SIZE(shareable_cells), log_id(module)); while (!shareable_cells.empty()) { @@ -307,6 +375,16 @@ struct ShareWorker log(" Analyzing resource sharing options for %s:\n", log_id(cell)); + const std::set> &cell_activation_patterns = find_cell_activation_patterns(cell); + RTLIL::SigSpec cell_activation_signals = bits_from_activation_patterns(cell_activation_patterns); + + if (cell_activation_patterns.count(std::pair())) { + log (" Cell is always active. Therefore no sharing is possible.\n"); + continue; + } + + log(" Found %d activation_patterns using ctrl signal %s.\n", SIZE(cell_activation_patterns), log_signal(cell_activation_signals)); + std::vector candidates; find_shareable_partners(candidates, cell); @@ -315,19 +393,11 @@ struct ShareWorker continue; } - log(" Found %d candidates:", int(candidates.size())); + log(" Found %d candidates:", SIZE(candidates)); for (auto c : candidates) log(" %s", log_id(c)); log("\n"); - const std::set> &cell_activation_patterns = find_cell_activation_patterns(cell); - RTLIL::SigSpec cell_activation_signals = bits_from_activation_patterns(cell_activation_patterns); - - log(" Found %d activation_patterns using ctrl signal %s.\n", int(cell_activation_patterns.size()), log_signal(cell_activation_signals)); - - if (cell_activation_patterns.empty()) - continue; - for (auto other_cell : candidates) { log(" Analyzing resource sharing with %s:\n", log_id(other_cell)); @@ -335,11 +405,13 @@ struct ShareWorker const std::set> &other_cell_activation_patterns = find_cell_activation_patterns(other_cell); RTLIL::SigSpec other_cell_activation_signals = bits_from_activation_patterns(other_cell_activation_patterns); - log(" Found %d activation_patterns using ctrl signal %s.\n", - int(other_cell_activation_patterns.size()), log_signal(other_cell_activation_signals)); - - if (other_cell_activation_patterns.empty()) + if (other_cell_activation_patterns.count(std::pair())) { + log (" Cell is always active. Therefore no sharing is possible.\n"); continue; + } + + log(" Found %d activation_patterns using ctrl signal %s.\n", + SIZE(other_cell_activation_patterns), log_signal(other_cell_activation_signals)); ezDefaultSAT ez; SatGen satgen(&ez, &modwalker.sigmap); @@ -379,6 +451,7 @@ struct ShareWorker if (config.opt_fast && modwalker.cell_outputs[pbit.cell].size() >= 4) continue; // log(" Adding cell %s (%s) to SAT problem.\n", log_id(pbit.cell), log_id(pbit.cell->type)); + bits_queue.insert(modwalker.cell_inputs[pbit.cell].begin(), modwalker.cell_inputs[pbit.cell].end()); satgen.importCell(pbit.cell); sat_cells.insert(pbit.cell); } @@ -394,12 +467,12 @@ struct ShareWorker ez.assume(ez.AND(ez.expression(ez.OpOr, cell_active), ez.expression(ez.OpOr, other_cell_active))); log(" Size of SAT problem: %d cells, %d variables, %d clauses\n", - int(sat_cells.size()), ez.numCnfVariables(), ez.numCnfClauses()); + SIZE(sat_cells), ez.numCnfVariables(), ez.numCnfClauses()); if (ez.solve(sat_model, sat_model_values)) { log(" According to the SAT solver this pair of cells can not be shared.\n"); - log(" Model from SAT solver: %s = %d'", log_signal(all_ctrl_signals), int(sat_model_values.size())); - for (int i = int(sat_model_values.size())-1; i >= 0; i--) + log(" Model from SAT solver: %s = %d'", log_signal(all_ctrl_signals), SIZE(sat_model_values)); + for (int i = SIZE(sat_model_values)-1; i >= 0; i--) log("%c", sat_model_values[i] ? '1' : '0'); log("\n"); continue; @@ -440,7 +513,7 @@ struct SharePass : public Pass { log(" for resource sharing.\n"); log("\n"); log(" -fast\n"); - log(" Only consider comparable primitive control logic in SAT solving, resulting\n"); + log(" Only consider the simple part of the control logic in SAT solving, resulting\n"); log(" in much easier SAT problems at the cost of maybe missing some oportunities\n"); log(" for resource sharing.\n"); log("\n"); -- cgit v1.2.3 From 7b98e46ac352e625be2d8da9b12e7252ed5179d5 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 20 Jul 2014 11:41:57 +0200 Subject: Added removing of always inactive cells to "share" pass --- passes/sat/share.cc | 50 ++++++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 42 insertions(+), 8 deletions(-) (limited to 'passes') diff --git a/passes/sat/share.cc b/passes/sat/share.cc index a1510a599..fd48b9012 100644 --- a/passes/sat/share.cc +++ b/passes/sat/share.cc @@ -41,6 +41,8 @@ struct ShareWorker CellTypes fwd_ct, cone_ct; ModWalker modwalker; + std::set cells_to_remove; + // ------------------------------------------------------------------------------ // Find terminal bits -- i.e. bits that do not (exclusively) feed into a mux tree @@ -229,7 +231,7 @@ struct ShareWorker std::map>> activation_patterns_cache; - bool sort_check_pattern(std::pair &p) + bool sort_check_activation_pattern(std::pair &p) { std::map p_bits; @@ -253,7 +255,13 @@ struct ShareWorker return true; } - const std::set> &find_cell_activation_patterns(RTLIL::Cell *cell) + void optimize_activation_patterns(std::set> & /* patterns */) + { + // TODO: Remove patterns that are contained in other patterns + // TODO: Consolidate pairs of patterns that only differ in the value for one signal bit + } + + const std::set> &find_cell_activation_patterns(RTLIL::Cell *cell, const char *indent) { if (activation_patterns_cache.count(cell)) return activation_patterns_cache.at(cell); @@ -276,7 +284,7 @@ struct ShareWorker for (auto c : driven_cells) { - const std::set> &c_patterns = find_cell_activation_patterns(c); + const std::set> &c_patterns = find_cell_activation_patterns(c, indent); if (c->type == "$mux" || c->type == "$pmux") { @@ -300,14 +308,14 @@ struct ShareWorker for (auto p : c_patterns) { for (int i = 0; i < SIZE(sig_s); i++) p.first.append_bit(sig_s[i]), p.second.bits.push_back(RTLIL::State::S0); - if (sort_check_pattern(p)) + if (sort_check_activation_pattern(p)) activation_patterns_cache[cell].insert(p); } for (int idx : used_in_b_parts) for (auto p : c_patterns) { p.first.append_bit(sig_s[idx]), p.second.bits.push_back(RTLIL::State::S1); - if (sort_check_pattern(p)) + if (sort_check_activation_pattern(p)) activation_patterns_cache[cell].insert(p); } } @@ -319,6 +327,12 @@ struct ShareWorker } } + optimize_activation_patterns(activation_patterns_cache[cell]); + if (activation_patterns_cache[cell].empty()) { + log("%sFound cell that is never activated: %s\n", indent, log_id(cell)); + cells_to_remove.insert(cell); + } + return activation_patterns_cache[cell]; } @@ -375,9 +389,14 @@ struct ShareWorker log(" Analyzing resource sharing options for %s:\n", log_id(cell)); - const std::set> &cell_activation_patterns = find_cell_activation_patterns(cell); + const std::set> &cell_activation_patterns = find_cell_activation_patterns(cell, " "); RTLIL::SigSpec cell_activation_signals = bits_from_activation_patterns(cell_activation_patterns); + if (cell_activation_patterns.empty()) { + log (" Cell is never active. Sharing is pointless, we simply remove it.\n"); + continue; + } + if (cell_activation_patterns.count(std::pair())) { log (" Cell is always active. Therefore no sharing is possible.\n"); continue; @@ -402,11 +421,17 @@ struct ShareWorker { log(" Analyzing resource sharing with %s:\n", log_id(other_cell)); - const std::set> &other_cell_activation_patterns = find_cell_activation_patterns(other_cell); + const std::set> &other_cell_activation_patterns = find_cell_activation_patterns(other_cell, " "); RTLIL::SigSpec other_cell_activation_signals = bits_from_activation_patterns(other_cell_activation_patterns); + if (other_cell_activation_patterns.empty()) { + log (" Cell is never active. Sharing is pointless, we simply remove it.\n"); + shareable_cells.erase(other_cell); + continue; + } + if (other_cell_activation_patterns.count(std::pair())) { - log (" Cell is always active. Therefore no sharing is possible.\n"); + log (" Cell is always active. Therefore no sharing is possible.\n"); continue; } @@ -484,6 +509,15 @@ struct ShareWorker break; } } + + if (!cells_to_remove.empty()) { + log("Removing %d cells in module %s:\n", SIZE(cells_to_remove), log_id(module)); + for (auto c : cells_to_remove) { + log(" Removing cell %s (%s).\n", log_id(c), log_id(c->type)); + module->cells.erase(c->name); + delete c; + } + } } }; -- cgit v1.2.3 From 5b3ee7a072ad0bd7fb1245a2fb3560a0ca034457 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 20 Jul 2014 15:00:18 +0200 Subject: Added "share" supercell creation --- passes/sat/share.cc | 116 +++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 115 insertions(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/sat/share.cc b/passes/sat/share.cc index fd48b9012..9ad1d621a 100644 --- a/passes/sat/share.cc +++ b/passes/sat/share.cc @@ -134,6 +134,10 @@ struct ShareWorker not_a_muxed_cell: continue; + // FIXME: Creation of super cells is broken for this cell types + if (cell->type == "$shr" || cell->type == "$mod") + continue; + if (config.opt_force) { shareable_cells.insert(cell); continue; @@ -225,6 +229,71 @@ struct ShareWorker } + // ----------------------- + // Create replacement cell + // ----------------------- + + RTLIL::Cell *make_supercell(RTLIL::Cell *c1, RTLIL::Cell *c2, RTLIL::SigSpec act) + { + if (c1->type == "$mul" || c1->type == "$div" || c1->type == "$mod" || c1->type == "$add" || c1->type == "$sub" || + c1->type == "$shl" || c1->type == "$shr" || c1->type == "$sshl" || c1->type == "$sshr") + { + log_assert(c1->type == c2->type); + + bool a_signed = c1->parameters.at("\\A_SIGNED").as_bool(); + bool b_signed = c1->parameters.at("\\B_SIGNED").as_bool(); + + log_assert(a_signed == c2->parameters.at("\\A_SIGNED").as_bool()); + log_assert(b_signed == c2->parameters.at("\\B_SIGNED").as_bool()); + + RTLIL::SigSpec a1 = c1->connections.at("\\A"); + RTLIL::SigSpec b1 = c1->connections.at("\\B"); + RTLIL::SigSpec y1 = c1->connections.at("\\Y"); + + RTLIL::SigSpec a2 = c2->connections.at("\\A"); + RTLIL::SigSpec b2 = c2->connections.at("\\B"); + RTLIL::SigSpec y2 = c2->connections.at("\\Y"); + + int a_width = std::max(a1.width, a2.width); + int b_width = std::max(b1.width, b2.width); + int y_width = std::max(y1.width, y2.width); + + if (a1.width != a_width) a1 = module->addPos(NEW_ID, a1, module->new_wire(a_width, NEW_ID), a_signed)->connections.at("\\Y"); + if (b1.width != b_width) b1 = module->addPos(NEW_ID, b1, module->new_wire(b_width, NEW_ID), b_signed)->connections.at("\\Y"); + + if (a2.width != a_width) a2 = module->addPos(NEW_ID, a2, module->new_wire(a_width, NEW_ID), a_signed)->connections.at("\\Y"); + if (b2.width != b_width) b2 = module->addPos(NEW_ID, b2, module->new_wire(b_width, NEW_ID), b_signed)->connections.at("\\Y"); + + RTLIL::SigSpec a = module->Mux(NEW_ID, a2, a1, act); + RTLIL::SigSpec b = module->Mux(NEW_ID, b2, b1, act); + RTLIL::Wire *y = module->new_wire(y_width, NEW_ID); + + RTLIL::Cell *supercell = new RTLIL::Cell; + supercell->name = NEW_ID; + supercell->type = c1->type; + supercell->parameters["\\A_SIGNED"] = a_signed; + supercell->parameters["\\B_SIGNED"] = b_signed; + supercell->parameters["\\A_WIDTH"] = a_width; + supercell->parameters["\\B_WIDTH"] = b_width; + supercell->parameters["\\Y_WIDTH"] = y_width; + supercell->connections["\\A"] = a; + supercell->connections["\\B"] = b; + supercell->connections["\\Y"] = y; + module->add(supercell); + + RTLIL::SigSpec new_y1(y, y1.width); + RTLIL::SigSpec new_y2(y, y2.width); + + module->connections.push_back(RTLIL::SigSig(y1, new_y1)); + module->connections.push_back(RTLIL::SigSig(y2, new_y2)); + + return supercell; + } + + log_abort(); + } + + // -------------------------------------------------------- // Finding control inputs and activation pattern for a cell // -------------------------------------------------------- @@ -330,6 +399,8 @@ struct ShareWorker optimize_activation_patterns(activation_patterns_cache[cell]); if (activation_patterns_cache[cell].empty()) { log("%sFound cell that is never activated: %s\n", indent, log_id(cell)); + RTLIL::SigSpec cell_outputs = modwalker.cell_outputs[cell]; + module->connections.push_back(RTLIL::SigSig(cell_outputs, RTLIL::SigSpec(RTLIL::State::Sx, cell_outputs.width))); cells_to_remove.insert(cell); } @@ -351,6 +422,18 @@ struct ShareWorker return signal; } + RTLIL::SigSpec make_cell_activation_logic(const std::set> &activation_patterns) + { + RTLIL::Wire *all_cases_wire = module->new_wire(0, NEW_ID); + for (auto &p : activation_patterns) { + all_cases_wire->width++; + module->addEq(NEW_ID, p.first, p.second, RTLIL::SigSpec(all_cases_wire, 1, all_cases_wire->width - 1)); + } + if (all_cases_wire->width == 1) + return all_cases_wire; + return module->ReduceOr(NEW_ID, all_cases_wire); + } + // ------------- // Setup and run @@ -504,8 +587,39 @@ struct ShareWorker } log(" According to the SAT solver this pair of cells can be shared.\n"); - log(" WARNING: Actually sharing the cells is not implemented yet.\n"); shareable_cells.erase(other_cell); + + int cell_select_score = 0; + int other_cell_select_score = 0; + + for (auto &p : cell_activation_patterns) + cell_select_score += p.first.width; + + for (auto &p : other_cell_activation_patterns) + other_cell_select_score += p.first.width; + + RTLIL::Cell *supercell; + if (cell_select_score <= other_cell_select_score) { + RTLIL::SigSpec act = make_cell_activation_logic(cell_activation_patterns); + supercell = make_supercell(cell, other_cell, act); + log(" Activation signal for %s: %s\n", log_id(cell), log_signal(act)); + } else { + RTLIL::SigSpec act = make_cell_activation_logic(other_cell_activation_patterns); + supercell = make_supercell(other_cell, cell, act); + log(" Activation signal for %s: %s\n", log_id(other_cell), log_signal(act)); + } + + log(" New cell: %s (%s)\n", log_id(supercell), log_id(supercell->type)); + + std::set> supercell_activation_patterns; + supercell_activation_patterns.insert(cell_activation_patterns.begin(), cell_activation_patterns.end()); + supercell_activation_patterns.insert(other_cell_activation_patterns.begin(), other_cell_activation_patterns.end()); + optimize_activation_patterns(supercell_activation_patterns); + activation_patterns_cache[supercell] = supercell_activation_patterns; + shareable_cells.insert(supercell); + + cells_to_remove.insert(cell); + cells_to_remove.insert(other_cell); break; } } -- cgit v1.2.3 From 8d04ca7d22e375fbe075dee1f189669046ee8906 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 20 Jul 2014 15:16:10 +0200 Subject: Added call_on_selection() and call_on_module() API --- passes/hierarchy/submod.cc | 2 +- passes/techmap/techmap.cc | 10 +--------- 2 files changed, 2 insertions(+), 10 deletions(-) (limited to 'passes') diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index 7d0811254..55f5f0485 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -338,7 +338,7 @@ struct SubmodPass : public Pass { if (module == NULL) log("Nothing selected -> do nothing.\n"); else { - Pass::call_newsel(design, stringf("opt_clean %s", module->name.c_str())); + Pass::call_on_module(design, module, "opt_clean"); log_header("Continuing SUBMOD pass.\n"); SubmodWorker worker(design, module, opt_name); } diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index cb36c9e1f..3ceff279b 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -393,15 +393,7 @@ struct TechmapWorker tpl->add(data.wire); std::string cmd_string = data.value.as_const().decode_string(); - - RTLIL::Selection tpl_mod_sel(false); - std::string backup_active_module = map->selected_active_module; - map->selected_active_module = tpl->name; - tpl_mod_sel.select(tpl); - map->selection_stack.push_back(tpl_mod_sel); - Pass::call(map, cmd_string); - map->selection_stack.pop_back(); - map->selected_active_module = backup_active_module; + Pass::call_on_module(map, tpl, cmd_string); keep_running = true; break; -- cgit v1.2.3 From 4c38ec1cc81c95b79fbd717dafd9f79708c123e8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 20 Jul 2014 15:23:08 +0200 Subject: Added "miter -equiv -flatten" --- passes/sat/miter.cc | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'passes') diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index 6c8e2ff48..0ef9e9aaa 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -27,6 +27,7 @@ static void create_miter_equiv(struct Pass *that, std::vector args, bool flag_make_outputs = false; bool flag_make_outcmp = false; bool flag_make_assert = false; + bool flag_flatten = false; log_header("Executing MITER pass (creating miter circuit).\n"); @@ -49,6 +50,10 @@ static void create_miter_equiv(struct Pass *that, std::vector args, flag_make_assert = true; continue; } + if (args[argidx] == "-flatten") { + flag_flatten = true; + continue; + } break; } if (argidx+3 != args.size() || args[argidx].substr(0, 1) == "-") @@ -287,6 +292,12 @@ static void create_miter_equiv(struct Pass *that, std::vector args, miter_module->add(not_cell); miter_module->fixup_ports(); + + if (flag_flatten) { + log_push(); + Pass::call_on_module(design, miter_module, "flatten; opt_const -undriven;;"); + log_pop(); + } } struct MiterPass : public Pass { @@ -317,6 +328,9 @@ struct MiterPass : public Pass { log(" -make_assert\n"); log(" also create an 'assert' cell that checks if trigger is always low.\n"); log("\n"); + log(" -flatten\n"); + log(" call 'flatten; opt_const -undriven;;' on the miter circuit.\n"); + log("\n"); } virtual void execute(std::vector args, RTLIL::Design *design) { -- cgit v1.2.3 From ff28029fdb4fe97dca0e93b175dd2d6411671cb0 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 20 Jul 2014 17:06:36 +0200 Subject: Fixed creation of shift supercells in "share" pass --- passes/sat/share.cc | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) (limited to 'passes') diff --git a/passes/sat/share.cc b/passes/sat/share.cc index 9ad1d621a..27b21207e 100644 --- a/passes/sat/share.cc +++ b/passes/sat/share.cc @@ -135,7 +135,7 @@ struct ShareWorker continue; // FIXME: Creation of super cells is broken for this cell types - if (cell->type == "$shr" || cell->type == "$mod") + if (cell->type == "$div" || cell->type == "$mod") continue; if (config.opt_force) { @@ -246,6 +246,9 @@ struct ShareWorker log_assert(a_signed == c2->parameters.at("\\A_SIGNED").as_bool()); log_assert(b_signed == c2->parameters.at("\\B_SIGNED").as_bool()); + if (c1->type == "$shl" || c1->type == "$shr" || c1->type == "$sshl" || c1->type == "$sshr") + b_signed = false; + RTLIL::SigSpec a1 = c1->connections.at("\\A"); RTLIL::SigSpec b1 = c1->connections.at("\\B"); RTLIL::SigSpec y1 = c1->connections.at("\\Y"); @@ -258,10 +261,23 @@ struct ShareWorker int b_width = std::max(b1.width, b2.width); int y_width = std::max(y1.width, y2.width); - if (a1.width != a_width) a1 = module->addPos(NEW_ID, a1, module->new_wire(a_width, NEW_ID), a_signed)->connections.at("\\Y"); - if (b1.width != b_width) b1 = module->addPos(NEW_ID, b1, module->new_wire(b_width, NEW_ID), b_signed)->connections.at("\\Y"); + if (c1->type == "$shr" && a_signed) + { + a_width = std::max(y_width, a_width); + + if (a1.width < y1.width) a1 = module->addPos(NEW_ID, a1, module->new_wire(y1.width, NEW_ID), true)->connections.at("\\Y"); + if (a2.width < y2.width) a2 = module->addPos(NEW_ID, a2, module->new_wire(y2.width, NEW_ID), true)->connections.at("\\Y"); + + if (a1.width != a_width) a1 = module->addPos(NEW_ID, a1, module->new_wire(a_width, NEW_ID), false)->connections.at("\\Y"); + if (a2.width != a_width) a2 = module->addPos(NEW_ID, a2, module->new_wire(a_width, NEW_ID), false)->connections.at("\\Y"); + } + else + { + if (a1.width != a_width) a1 = module->addPos(NEW_ID, a1, module->new_wire(a_width, NEW_ID), a_signed)->connections.at("\\Y"); + if (a2.width != a_width) a2 = module->addPos(NEW_ID, a2, module->new_wire(a_width, NEW_ID), a_signed)->connections.at("\\Y"); + } - if (a2.width != a_width) a2 = module->addPos(NEW_ID, a2, module->new_wire(a_width, NEW_ID), a_signed)->connections.at("\\Y"); + if (b1.width != b_width) b1 = module->addPos(NEW_ID, b1, module->new_wire(b_width, NEW_ID), b_signed)->connections.at("\\Y"); if (b2.width != b_width) b2 = module->addPos(NEW_ID, b2, module->new_wire(b_width, NEW_ID), b_signed)->connections.at("\\Y"); RTLIL::SigSpec a = module->Mux(NEW_ID, a2, a1, act); -- cgit v1.2.3 From e9506bb2da9640cebc325e33a678d352d36a909e Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 20 Jul 2014 18:54:06 +0200 Subject: Supercell creation for $div/$mod worked all along, fixed test benches --- passes/sat/share.cc | 4 ---- 1 file changed, 4 deletions(-) (limited to 'passes') diff --git a/passes/sat/share.cc b/passes/sat/share.cc index 27b21207e..065496710 100644 --- a/passes/sat/share.cc +++ b/passes/sat/share.cc @@ -134,10 +134,6 @@ struct ShareWorker not_a_muxed_cell: continue; - // FIXME: Creation of super cells is broken for this cell types - if (cell->type == "$div" || cell->type == "$mod") - continue; - if (config.opt_force) { shareable_cells.insert(cell); continue; -- cgit v1.2.3 From 1ce5e835553a99c3333af00ead1d8f3e40c5538a Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 20 Jul 2014 20:15:49 +0200 Subject: Added "select -assert-count" --- passes/cmds/select.cc | 49 +++++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 43 insertions(+), 6 deletions(-) (limited to 'passes') diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index 38d43f8df..9ef60a28f 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -857,6 +857,10 @@ struct SelectPass : public Pass { log(" selection is non-empty. i.e. produce an error if no object matching\n"); log(" the selection is found.\n"); log("\n"); + log(" -assert-count N\n"); + log(" do not modify the current selection. instead assert that the given\n"); + log(" selection contains exactly N objects.\n"); + log("\n"); log(" -list\n"); log(" list all objects in the current selection\n"); log("\n"); @@ -1021,6 +1025,7 @@ struct SelectPass : public Pass { bool got_module = false; bool assert_none = false; bool assert_any = false; + int assert_count = -1; std::string write_file; std::string set_name; std::string sel_str; @@ -1047,6 +1052,10 @@ struct SelectPass : public Pass { assert_any = true; continue; } + if (arg == "-assert-count" && argidx+1 < args.size()) { + assert_count = atoi(args[++argidx].c_str()); + continue; + } if (arg == "-clear") { clear_mode = true; continue; @@ -1091,14 +1100,14 @@ struct SelectPass : public Pass { if (none_mode && args.size() != 2) log_cmd_error("Option -none can not be combined with any other options.\n"); - if (add_mode + del_mode + assert_none + assert_any > 1) - log_cmd_error("Options -add, -del, -assert-none or -assert-any can not be combined.\n"); + if (add_mode + del_mode + assert_none + assert_any + (assert_count >= 0) > 1) + log_cmd_error("Options -add, -del, -assert-none, -assert-any or -assert-count can not be combined.\n"); - if ((list_mode || !write_file.empty() || count_mode) && (add_mode || del_mode || assert_none || assert_any)) - log_cmd_error("Options -list, -write and -count can not be combined with -add, -del, -assert-none or -assert-any.\n"); + if ((list_mode || !write_file.empty() || count_mode) && (add_mode || del_mode || assert_none || assert_any || assert_count >= 0)) + log_cmd_error("Options -list, -write and -count can not be combined with -add, -del, -assert-none, -assert-any or -assert-count.\n"); - if (!set_name.empty() && (list_mode || !write_file.empty() || count_mode || add_mode || del_mode || assert_none || assert_any)) - log_cmd_error("Option -set can not be combined with -list, -write, -count, -add, -del, -assert-none or -assert-any.\n"); + if (!set_name.empty() && (list_mode || !write_file.empty() || count_mode || add_mode || del_mode || assert_none || assert_any || assert_count >= 0)) + log_cmd_error("Option -set can not be combined with -list, -write, -count, -add, -del, -assert-none, -assert-any or -assert-count.\n"); if (work_stack.size() == 0 && got_module) { RTLIL::Selection sel; @@ -1201,6 +1210,34 @@ struct SelectPass : public Pass { return; } + if (assert_count >= 0) + { + int total_count = 0; + if (work_stack.size() == 0) + log_cmd_error("No selection to check.\n"); + RTLIL::Selection *sel = &work_stack.back(); + sel->optimize(design); + for (auto mod_it : design->modules) + if (sel->selected_module(mod_it.first)) { + for (auto &it : mod_it.second->wires) + if (sel->selected_member(mod_it.first, it.first)) + total_count++; + for (auto &it : mod_it.second->memories) + if (sel->selected_member(mod_it.first, it.first)) + total_count++; + for (auto &it : mod_it.second->cells) + if (sel->selected_member(mod_it.first, it.first)) + total_count++; + for (auto &it : mod_it.second->processes) + if (sel->selected_member(mod_it.first, it.first)) + total_count++; + } + if (assert_count != total_count) + log_error("Assertation failed: selection contains %d elements instead of the asserted %d:%s\n", + total_count, assert_count, sel_str.c_str()); + return; + } + if (!set_name.empty()) { if (work_stack.size() == 0) -- cgit v1.2.3 From 04fcb07213291f469d208ceca2a32fb8c2fe3215 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 20 Jul 2014 20:44:14 +0200 Subject: Added support for resource sharing in mux control logic --- passes/sat/share.cc | 241 +++++++++++++++++++++++++++++++++------------------- 1 file changed, 155 insertions(+), 86 deletions(-) (limited to 'passes') diff --git a/passes/sat/share.cc b/passes/sat/share.cc index 065496710..90daefc0a 100644 --- a/passes/sat/share.cc +++ b/passes/sat/share.cc @@ -42,6 +42,7 @@ struct ShareWorker ModWalker modwalker; std::set cells_to_remove; + std::set recursion_state; // ------------------------------------------------------------------------------ @@ -52,58 +53,36 @@ struct ShareWorker void find_terminal_bits() { - std::set queue_strong_bits, queue_weak_bits; + std::set queue_bits; std::set visited_cells; - queue_weak_bits.insert(modwalker.signal_outputs.begin(), modwalker.signal_outputs.end()); + queue_bits.insert(modwalker.signal_outputs.begin(), modwalker.signal_outputs.end()); for (auto &it : module->cells) - { - RTLIL::Cell *cell = it.second; - - if (cell->type == "$mux" || cell->type == "$pmux") - { - std::vector bits = modwalker.sigmap(cell->connections.at("\\S")); - queue_strong_bits.insert(bits.begin(), bits.end()); + if (!fwd_ct.cell_known(it.second->type)) { + std::set &bits = modwalker.cell_inputs[it.second]; + queue_bits.insert(bits.begin(), bits.end()); } - else if (!fwd_ct.cell_known(cell->type)) - { - std::set &bits = modwalker.cell_inputs[cell]; - queue_weak_bits.insert(bits.begin(), bits.end()); - } - } - terminal_bits.insert(queue_strong_bits.begin(), queue_strong_bits.end()); - terminal_bits.insert(queue_weak_bits.begin(), queue_weak_bits.end()); + terminal_bits.insert(queue_bits.begin(), queue_bits.end()); - while (!queue_strong_bits.empty()) + while (!queue_bits.empty()) { std::set portbits; - modwalker.get_drivers(portbits, queue_strong_bits); - queue_strong_bits.clear(); + modwalker.get_drivers(portbits, queue_bits); + queue_bits.clear(); - for (auto &pbit : portbits) - if (fwd_ct.cell_known(pbit.cell->type) && visited_cells.count(pbit.cell) == 0) { - std::set &bits = modwalker.cell_inputs[pbit.cell]; + for (auto &pbit : portbits) { + if (pbit.cell->type == "$mux" || pbit.cell->type == "$pmux") { + std::set bits = modwalker.sigmap(pbit.cell->connections.at("\\S")).to_sigbit_set(); terminal_bits.insert(bits.begin(), bits.end()); - queue_strong_bits.insert(bits.begin(), bits.end()); + queue_bits.insert(bits.begin(), bits.end()); visited_cells.insert(pbit.cell); } - } - - while (!queue_weak_bits.empty()) - { - std::set portbits; - modwalker.get_drivers(portbits, queue_weak_bits); - queue_weak_bits.clear(); - - for (auto &pbit : portbits) { - if (pbit.cell->type == "$mux" || pbit.cell->type == "$pmux") - continue; if (fwd_ct.cell_known(pbit.cell->type) && visited_cells.count(pbit.cell) == 0) { std::set &bits = modwalker.cell_inputs[pbit.cell]; terminal_bits.insert(bits.begin(), bits.end()); - queue_weak_bits.insert(bits.begin(), bits.end()); + queue_bits.insert(bits.begin(), bits.end()); visited_cells.insert(pbit.cell); } } @@ -306,6 +285,48 @@ struct ShareWorker } + // ------------------------------------------- + // Finding forbidden control inputs for a cell + // ------------------------------------------- + + std::map> forbidden_controls_cache; + + const std::set &find_forbidden_controls(RTLIL::Cell *cell) + { + if (recursion_state.count(cell)) { + static std::set empty_controls_set; + return empty_controls_set; + } + + if (forbidden_controls_cache.count(cell)) + return forbidden_controls_cache.at(cell); + + std::set pbits; + std::set consumer_cells; + + modwalker.get_consumers(pbits, modwalker.cell_outputs[cell]); + + for (auto &bit : pbits) { + if ((bit.cell->type == "$mux" || bit.cell->type == "$pmux") && bit.port == "\\S") + forbidden_controls_cache[cell].insert(bit.cell->connections.at("\\S").extract(bit.offset, 1)); + consumer_cells.insert(bit.cell); + } + + recursion_state.insert(cell); + + for (auto c : consumer_cells) + if (fwd_ct.cell_known(c->type)) { + const std::set &bits = find_forbidden_controls(c); + forbidden_controls_cache[cell].insert(bits.begin(), bits.end()); + } + + log_assert(recursion_state.count(cell)); + recursion_state.erase(cell); + + return forbidden_controls_cache[cell]; + } + + // -------------------------------------------------------- // Finding control inputs and activation pattern for a cell // -------------------------------------------------------- @@ -344,11 +365,16 @@ struct ShareWorker const std::set> &find_cell_activation_patterns(RTLIL::Cell *cell, const char *indent) { + if (recursion_state.count(cell)) { + static std::set> empty_patterns_set; + return empty_patterns_set; + } + if (activation_patterns_cache.count(cell)) return activation_patterns_cache.at(cell); const std::set &cell_out_bits = modwalker.cell_outputs[cell]; - std::set driven_cells; + std::set driven_cells, driven_data_muxes; for (auto &bit : cell_out_bits) { @@ -359,55 +385,59 @@ struct ShareWorker } for (auto &pbit : modwalker.signal_consumers[bit]) { log_assert(fwd_ct.cell_known(pbit.cell->type)); - driven_cells.insert(pbit.cell); + if ((pbit.cell->type == "$mux" || pbit.cell->type == "$pmux") && (pbit.port == "\\A" || pbit.port == "\\B")) + driven_data_muxes.insert(pbit.cell); + else + driven_cells.insert(pbit.cell); } } - for (auto c : driven_cells) + recursion_state.insert(cell); + + for (auto c : driven_data_muxes) { const std::set> &c_patterns = find_cell_activation_patterns(c, indent); - if (c->type == "$mux" || c->type == "$pmux") - { - bool used_in_a = false; - std::set used_in_b_parts; - - int width = c->parameters.at("\\WIDTH").as_int(); - std::vector sig_a = modwalker.sigmap(c->connections.at("\\A")); - std::vector sig_b = modwalker.sigmap(c->connections.at("\\B")); - std::vector sig_s = modwalker.sigmap(c->connections.at("\\S")); - - for (auto &bit : sig_a) - if (cell_out_bits.count(bit)) - used_in_a = true; - - for (int i = 0; i < SIZE(sig_b); i++) - if (cell_out_bits.count(sig_b[i])) - used_in_b_parts.insert(i / width); - - if (used_in_a) - for (auto p : c_patterns) { - for (int i = 0; i < SIZE(sig_s); i++) - p.first.append_bit(sig_s[i]), p.second.bits.push_back(RTLIL::State::S0); - if (sort_check_activation_pattern(p)) - activation_patterns_cache[cell].insert(p); - } - - for (int idx : used_in_b_parts) - for (auto p : c_patterns) { - p.first.append_bit(sig_s[idx]), p.second.bits.push_back(RTLIL::State::S1); - if (sort_check_activation_pattern(p)) - activation_patterns_cache[cell].insert(p); - } - } - else - { - // Not a mux: just copy the activation patterns - for (auto &p : c_patterns) - activation_patterns_cache[cell].insert(p); - } + bool used_in_a = false; + std::set used_in_b_parts; + + int width = c->parameters.at("\\WIDTH").as_int(); + std::vector sig_a = modwalker.sigmap(c->connections.at("\\A")); + std::vector sig_b = modwalker.sigmap(c->connections.at("\\B")); + std::vector sig_s = modwalker.sigmap(c->connections.at("\\S")); + + for (auto &bit : sig_a) + if (cell_out_bits.count(bit)) + used_in_a = true; + + for (int i = 0; i < SIZE(sig_b); i++) + if (cell_out_bits.count(sig_b[i])) + used_in_b_parts.insert(i / width); + + if (used_in_a) + for (auto p : c_patterns) { + for (int i = 0; i < SIZE(sig_s); i++) + p.first.append_bit(sig_s[i]), p.second.bits.push_back(RTLIL::State::S0); + if (sort_check_activation_pattern(p)) + activation_patterns_cache[cell].insert(p); + } + + for (int idx : used_in_b_parts) + for (auto p : c_patterns) { + p.first.append_bit(sig_s[idx]), p.second.bits.push_back(RTLIL::State::S1); + if (sort_check_activation_pattern(p)) + activation_patterns_cache[cell].insert(p); + } + } + + for (auto c : driven_cells) { + const std::set> &c_patterns = find_cell_activation_patterns(c, indent); + activation_patterns_cache[cell].insert(c_patterns.begin(), c_patterns.end()); } + log_assert(recursion_state.count(cell)); + recursion_state.erase(cell); + optimize_activation_patterns(activation_patterns_cache[cell]); if (activation_patterns_cache[cell].empty()) { log("%sFound cell that is never activated: %s\n", indent, log_id(cell)); @@ -434,6 +464,24 @@ struct ShareWorker return signal; } + void filter_activation_patterns(std::set> &out, + const std::set> &in, const std::set &filter_bits) + { + for (auto &p : in) + { + std::vector p_first = p.first; + std::pair new_p; + + for (int i = 0; i < SIZE(p_first); i++) + if (filter_bits.count(p_first[i]) == 0) { + new_p.first.append_bit(p_first[i]); + new_p.second.bits.push_back(p.second.bits.at(i)); + } + + out.insert(new_p); + } + } + RTLIL::SigSpec make_cell_activation_logic(const std::set> &activation_patterns) { RTLIL::Wire *all_cases_wire = module->new_wire(0, NEW_ID); @@ -533,6 +581,25 @@ struct ShareWorker log(" Found %d activation_patterns using ctrl signal %s.\n", SIZE(other_cell_activation_patterns), log_signal(other_cell_activation_signals)); + const std::set &cell_forbidden_controls = find_forbidden_controls(cell); + const std::set &other_cell_forbidden_controls = find_forbidden_controls(other_cell); + + std::set union_forbidden_controls; + union_forbidden_controls.insert(cell_forbidden_controls.begin(), cell_forbidden_controls.end()); + union_forbidden_controls.insert(other_cell_forbidden_controls.begin(), other_cell_forbidden_controls.end()); + + if (!union_forbidden_controls.empty()) + log(" Forbidden control signals for this pair of cells: %s\n", log_signal(union_forbidden_controls)); + + std::set> filtered_cell_activation_patterns; + std::set> filtered_other_cell_activation_patterns; + + filter_activation_patterns(filtered_cell_activation_patterns, cell_activation_patterns, union_forbidden_controls); + filter_activation_patterns(filtered_other_cell_activation_patterns, other_cell_activation_patterns, union_forbidden_controls); + + optimize_activation_patterns(filtered_cell_activation_patterns); + optimize_activation_patterns(filtered_other_cell_activation_patterns); + ezDefaultSAT ez; SatGen satgen(&ez, &modwalker.sigmap); @@ -542,13 +609,13 @@ struct ShareWorker std::vector cell_active, other_cell_active; RTLIL::SigSpec all_ctrl_signals; - for (auto &p : cell_activation_patterns) { + for (auto &p : filtered_cell_activation_patterns) { log(" Activation pattern for cell %s: %s = %s\n", log_id(cell), log_signal(p.first), log_signal(p.second)); cell_active.push_back(ez.vec_eq(satgen.importSigSpec(p.first), satgen.importSigSpec(p.second))); all_ctrl_signals.append(p.first); } - for (auto &p : other_cell_activation_patterns) { + for (auto &p : filtered_other_cell_activation_patterns) { log(" Activation pattern for cell %s: %s = %s\n", log_id(other_cell), log_signal(p.first), log_signal(p.second)); other_cell_active.push_back(ez.vec_eq(satgen.importSigSpec(p.first), satgen.importSigSpec(p.second))); all_ctrl_signals.append(p.first); @@ -604,19 +671,19 @@ struct ShareWorker int cell_select_score = 0; int other_cell_select_score = 0; - for (auto &p : cell_activation_patterns) + for (auto &p : filtered_cell_activation_patterns) cell_select_score += p.first.width; - for (auto &p : other_cell_activation_patterns) + for (auto &p : filtered_other_cell_activation_patterns) other_cell_select_score += p.first.width; RTLIL::Cell *supercell; if (cell_select_score <= other_cell_select_score) { - RTLIL::SigSpec act = make_cell_activation_logic(cell_activation_patterns); + RTLIL::SigSpec act = make_cell_activation_logic(filtered_cell_activation_patterns); supercell = make_supercell(cell, other_cell, act); log(" Activation signal for %s: %s\n", log_id(cell), log_signal(act)); } else { - RTLIL::SigSpec act = make_cell_activation_logic(other_cell_activation_patterns); + RTLIL::SigSpec act = make_cell_activation_logic(filtered_other_cell_activation_patterns); supercell = make_supercell(other_cell, cell, act); log(" Activation signal for %s: %s\n", log_id(other_cell), log_signal(act)); } @@ -624,8 +691,8 @@ struct ShareWorker log(" New cell: %s (%s)\n", log_id(supercell), log_id(supercell->type)); std::set> supercell_activation_patterns; - supercell_activation_patterns.insert(cell_activation_patterns.begin(), cell_activation_patterns.end()); - supercell_activation_patterns.insert(other_cell_activation_patterns.begin(), other_cell_activation_patterns.end()); + supercell_activation_patterns.insert(filtered_cell_activation_patterns.begin(), filtered_cell_activation_patterns.end()); + supercell_activation_patterns.insert(filtered_other_cell_activation_patterns.begin(), filtered_other_cell_activation_patterns.end()); optimize_activation_patterns(supercell_activation_patterns); activation_patterns_cache[supercell] = supercell_activation_patterns; shareable_cells.insert(supercell); @@ -644,6 +711,8 @@ struct ShareWorker delete c; } } + + log_assert(recursion_state.empty()); } }; -- cgit v1.2.3 From b49beab1f30d0a7567c2917a3387fa52c84350fd Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 21 Jul 2014 02:08:38 +0200 Subject: Use ezSAT::non_incremental() in "share" pass --- passes/sat/share.cc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'passes') diff --git a/passes/sat/share.cc b/passes/sat/share.cc index 90daefc0a..8ef3396e0 100644 --- a/passes/sat/share.cc +++ b/passes/sat/share.cc @@ -601,6 +601,8 @@ struct ShareWorker optimize_activation_patterns(filtered_other_cell_activation_patterns); ezDefaultSAT ez; + ez.non_incremental(); + SatGen satgen(&ez, &modwalker.sigmap); std::set sat_cells; -- cgit v1.2.3 From 3cb61d03f8722fddfa14877accae1b3ca51e3926 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 21 Jul 2014 12:04:56 +0200 Subject: Wider range of cell types supported in "share" pass --- passes/sat/share.cc | 214 +++++++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 197 insertions(+), 17 deletions(-) (limited to 'passes') diff --git a/passes/sat/share.cc b/passes/sat/share.cc index 8ef3396e0..852d80782 100644 --- a/passes/sat/share.cc +++ b/passes/sat/share.cc @@ -30,11 +30,14 @@ struct ShareWorkerConfig bool opt_force; bool opt_aggressive; bool opt_fast; + std::set generic_uni_ops, generic_bin_ops, generic_cbin_ops; }; struct ShareWorker { ShareWorkerConfig config; + std::set generic_ops; + RTLIL::Design *design; RTLIL::Module *module; @@ -125,19 +128,19 @@ struct ShareWorker } if (cell->type == "$mul" || cell->type == "$div" || cell->type == "$mod") { - if (config.opt_aggressive || cell->parameters.at("\\Y_WIDTH").as_int() > 4) + if (config.opt_aggressive || cell->parameters.at("\\Y_WIDTH").as_int() >= 4) shareable_cells.insert(cell); continue; } if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr") { - if (config.opt_aggressive || cell->parameters.at("\\Y_WIDTH").as_int() > 8) + if (config.opt_aggressive || cell->parameters.at("\\Y_WIDTH").as_int() >= 8) shareable_cells.insert(cell); continue; } - if (cell->type == "$add" || cell->type == "$sub") { - if (config.opt_aggressive || cell->parameters.at("\\Y_WIDTH").as_int() > 10) + if (generic_ops.count(cell->type)) { + if (config.opt_aggressive || cell->parameters.at("\\Y_WIDTH").as_int() >= 10) shareable_cells.insert(cell); continue; } @@ -157,15 +160,25 @@ struct ShareWorker return true; } - if (c1->type == "$mul" || c1->type == "$div" || c1->type == "$mod" || c1->type == "$add" || c1->type == "$sub" || - c1->type == "$shl" || c1->type == "$shr" || c1->type == "$sshl" || c1->type == "$sshr") + if (config.generic_uni_ops.count(c1->type)) { - if (c1->parameters.at("\\A_SIGNED").as_bool() != c2->parameters.at("\\A_SIGNED").as_bool()) - return false; + if (!config.opt_aggressive) + { + int a1_width = c1->parameters.at("\\A_WIDTH").as_int(); + int y1_width = c1->parameters.at("\\Y_WIDTH").as_int(); - if (c1->parameters.at("\\B_SIGNED").as_bool() != c2->parameters.at("\\B_SIGNED").as_bool()) - return false; + int a2_width = c2->parameters.at("\\A_WIDTH").as_int(); + int y2_width = c2->parameters.at("\\Y_WIDTH").as_int(); + if (std::max(a1_width, a2_width) > 2 * std::min(a1_width, a2_width)) return false; + if (std::max(y1_width, y2_width) > 2 * std::min(y1_width, y2_width)) return false; + } + + return true; + } + + if (config.generic_bin_ops.count(c1->type)) + { if (!config.opt_aggressive) { int a1_width = c1->parameters.at("\\A_WIDTH").as_int(); @@ -184,6 +197,32 @@ struct ShareWorker return true; } + if (config.generic_cbin_ops.count(c1->type)) + { + if (!config.opt_aggressive) + { + int a1_width = c1->parameters.at("\\A_WIDTH").as_int(); + int b1_width = c1->parameters.at("\\B_WIDTH").as_int(); + int y1_width = c1->parameters.at("\\Y_WIDTH").as_int(); + + int a2_width = c2->parameters.at("\\A_WIDTH").as_int(); + int b2_width = c2->parameters.at("\\B_WIDTH").as_int(); + int y2_width = c2->parameters.at("\\Y_WIDTH").as_int(); + + int min1_width = std::min(a1_width, b1_width); + int max1_width = std::max(a1_width, b1_width); + + int min2_width = std::min(a2_width, b2_width); + int max2_width = std::max(a2_width, b2_width); + + if (std::max(min1_width, min2_width) > 2 * std::min(min1_width, min2_width)) return false; + if (std::max(max1_width, max2_width) > 2 * std::min(max1_width, max2_width)) return false; + if (std::max(y1_width, y2_width) > 2 * std::min(y1_width, y2_width)) return false; + } + + return true; + } + for (auto &it : c1->parameters) if (c2->parameters.count(it.first) == 0 || c2->parameters.at(it.first) != it.second) return false; @@ -210,10 +249,106 @@ struct ShareWorker RTLIL::Cell *make_supercell(RTLIL::Cell *c1, RTLIL::Cell *c2, RTLIL::SigSpec act) { - if (c1->type == "$mul" || c1->type == "$div" || c1->type == "$mod" || c1->type == "$add" || c1->type == "$sub" || - c1->type == "$shl" || c1->type == "$shr" || c1->type == "$sshl" || c1->type == "$sshr") + log_assert(c1->type == c2->type); + + if (config.generic_uni_ops.count(c1->type)) { - log_assert(c1->type == c2->type); + if (c1->parameters.at("\\A_SIGNED").as_bool() != c2->parameters.at("\\A_SIGNED").as_bool()) + { + RTLIL::Cell *unsigned_cell = c1->parameters.at("\\A_SIGNED").as_bool() ? c2 : c1; + if (unsigned_cell->connections.at("\\A").to_sigbit_vector().back() != RTLIL::State::S0) { + unsigned_cell->parameters.at("\\A_WIDTH") = unsigned_cell->parameters.at("\\A_WIDTH").as_int() + 1; + unsigned_cell->connections.at("\\A").append_bit(RTLIL::State::S0); + } + unsigned_cell->parameters.at("\\A_SIGNED") = true; + unsigned_cell->check(); + } + + bool a_signed = c1->parameters.at("\\A_SIGNED").as_bool(); + log_assert(a_signed == c2->parameters.at("\\A_SIGNED").as_bool()); + + RTLIL::SigSpec a1 = c1->connections.at("\\A"); + RTLIL::SigSpec y1 = c1->connections.at("\\Y"); + + RTLIL::SigSpec a2 = c2->connections.at("\\A"); + RTLIL::SigSpec y2 = c2->connections.at("\\Y"); + + int a_width = std::max(a1.width, a2.width); + int y_width = std::max(y1.width, y2.width); + + if (a1.width != a_width) a1 = module->addPos(NEW_ID, a1, module->new_wire(a_width, NEW_ID), a_signed)->connections.at("\\Y"); + if (a2.width != a_width) a2 = module->addPos(NEW_ID, a2, module->new_wire(a_width, NEW_ID), a_signed)->connections.at("\\Y"); + + RTLIL::SigSpec a = module->Mux(NEW_ID, a2, a1, act); + RTLIL::Wire *y = module->new_wire(y_width, NEW_ID); + + RTLIL::Cell *supercell = new RTLIL::Cell; + supercell->name = NEW_ID; + supercell->type = c1->type; + supercell->parameters["\\A_SIGNED"] = a_signed; + supercell->parameters["\\A_WIDTH"] = a_width; + supercell->parameters["\\Y_WIDTH"] = y_width; + supercell->connections["\\A"] = a; + supercell->connections["\\Y"] = y; + module->add(supercell); + + RTLIL::SigSpec new_y1(y, y1.width); + RTLIL::SigSpec new_y2(y, y2.width); + + module->connections.push_back(RTLIL::SigSig(y1, new_y1)); + module->connections.push_back(RTLIL::SigSig(y2, new_y2)); + + return supercell; + } + + if (config.generic_bin_ops.count(c1->type) || config.generic_cbin_ops.count(c1->type)) + { + bool modified_src_cells = false; + + if (config.generic_cbin_ops.count(c1->type)) + { + int score_unflipped = std::max(c1->parameters.at("\\A_WIDTH").as_int(), c2->parameters.at("\\A_WIDTH").as_int()) + + std::max(c1->parameters.at("\\B_WIDTH").as_int(), c2->parameters.at("\\B_WIDTH").as_int()); + + int score_flipped = std::max(c1->parameters.at("\\A_WIDTH").as_int(), c2->parameters.at("\\B_WIDTH").as_int()) + + std::max(c1->parameters.at("\\B_WIDTH").as_int(), c2->parameters.at("\\A_WIDTH").as_int()); + + if (score_flipped < score_unflipped) + { + std::swap(c2->connections.at("\\A"), c2->connections.at("\\B")); + std::swap(c2->parameters.at("\\A_WIDTH"), c2->parameters.at("\\B_WIDTH")); + std::swap(c2->parameters.at("\\A_SIGNED"), c2->parameters.at("\\B_SIGNED")); + modified_src_cells = true; + } + } + + if (c1->parameters.at("\\A_SIGNED").as_bool() != c2->parameters.at("\\A_SIGNED").as_bool()) + + { + RTLIL::Cell *unsigned_cell = c1->parameters.at("\\A_SIGNED").as_bool() ? c2 : c1; + if (unsigned_cell->connections.at("\\A").to_sigbit_vector().back() != RTLIL::State::S0) { + unsigned_cell->parameters.at("\\A_WIDTH") = unsigned_cell->parameters.at("\\A_WIDTH").as_int() + 1; + unsigned_cell->connections.at("\\A").append_bit(RTLIL::State::S0); + } + unsigned_cell->parameters.at("\\A_SIGNED") = true; + modified_src_cells = true; + } + + if (c1->parameters.at("\\B_SIGNED").as_bool() != c2->parameters.at("\\B_SIGNED").as_bool()) + { + RTLIL::Cell *unsigned_cell = c1->parameters.at("\\B_SIGNED").as_bool() ? c2 : c1; + if (unsigned_cell->connections.at("\\B").to_sigbit_vector().back() != RTLIL::State::S0) { + unsigned_cell->parameters.at("\\B_WIDTH") = unsigned_cell->parameters.at("\\B_WIDTH").as_int() + 1; + unsigned_cell->connections.at("\\B").append_bit(RTLIL::State::S0); + } + unsigned_cell->parameters.at("\\B_SIGNED") = true; + modified_src_cells = true; + } + + if (modified_src_cells) { + c1->check(); + c2->check(); + } bool a_signed = c1->parameters.at("\\A_SIGNED").as_bool(); bool b_signed = c1->parameters.at("\\B_SIGNED").as_bool(); @@ -259,9 +394,7 @@ struct ShareWorker RTLIL::SigSpec b = module->Mux(NEW_ID, b2, b1, act); RTLIL::Wire *y = module->new_wire(y_width, NEW_ID); - RTLIL::Cell *supercell = new RTLIL::Cell; - supercell->name = NEW_ID; - supercell->type = c1->type; + RTLIL::Cell *supercell = module->addCell(NEW_ID, c1->type); supercell->parameters["\\A_SIGNED"] = a_signed; supercell->parameters["\\B_SIGNED"] = b_signed; supercell->parameters["\\A_WIDTH"] = a_width; @@ -270,7 +403,7 @@ struct ShareWorker supercell->connections["\\A"] = a; supercell->connections["\\B"] = b; supercell->connections["\\Y"] = y; - module->add(supercell); + supercell->check(); RTLIL::SigSpec new_y1(y, y1.width); RTLIL::SigSpec new_y2(y, y2.width); @@ -502,6 +635,10 @@ struct ShareWorker ShareWorker(ShareWorkerConfig config, RTLIL::Design *design, RTLIL::Module *module) : config(config), design(design), module(module) { + generic_ops.insert(config.generic_uni_ops.begin(), config.generic_uni_ops.end()); + generic_ops.insert(config.generic_bin_ops.begin(), config.generic_bin_ops.end()); + generic_ops.insert(config.generic_cbin_ops.begin(), config.generic_cbin_ops.end()); + fwd_ct.setup_internals(); cone_ct.setup_internals(); @@ -752,10 +889,53 @@ struct SharePass : public Pass { virtual void execute(std::vector args, RTLIL::Design *design) { ShareWorkerConfig config; + config.opt_force = false; config.opt_aggressive = false; config.opt_fast = false; + config.generic_uni_ops.insert("$not"); + // config.generic_uni_ops.insert("$pos"); + // config.generic_uni_ops.insert("$bu0"); + config.generic_uni_ops.insert("$neg"); + + config.generic_uni_ops.insert("$reduce_and"); + config.generic_uni_ops.insert("$reduce_or"); + config.generic_uni_ops.insert("$reduce_xor"); + config.generic_uni_ops.insert("$reduce_xnor"); + config.generic_uni_ops.insert("$reduce_bool"); + + config.generic_cbin_ops.insert("$and"); + config.generic_cbin_ops.insert("$or"); + config.generic_cbin_ops.insert("$xor"); + config.generic_cbin_ops.insert("$xnor"); + + config.generic_bin_ops.insert("$shl"); + config.generic_bin_ops.insert("$shr"); + config.generic_bin_ops.insert("$sshl"); + config.generic_bin_ops.insert("$sshr"); + + config.generic_bin_ops.insert("$lt"); + config.generic_bin_ops.insert("$le"); + config.generic_bin_ops.insert("$eq"); + config.generic_bin_ops.insert("$ne"); + config.generic_bin_ops.insert("$eqx"); + config.generic_bin_ops.insert("$nex"); + config.generic_bin_ops.insert("$ge"); + config.generic_bin_ops.insert("$gt"); + + config.generic_cbin_ops.insert("$add"); + config.generic_cbin_ops.insert("$mul"); + + config.generic_bin_ops.insert("$sub"); + config.generic_bin_ops.insert("$div"); + config.generic_bin_ops.insert("$mod"); + // config.generic_bin_ops.insert("$pow"); + + config.generic_uni_ops.insert("$logic_not"); + config.generic_cbin_ops.insert("$logic_and"); + config.generic_cbin_ops.insert("$logic_or"); + log_header("Executing SHARE pass (SAT-based resource sharing).\n"); size_t argidx; -- cgit v1.2.3 From 1d88f1cf9f2088de7825f5292db5b40d4f73d036 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 21 Jul 2014 12:35:06 +0200 Subject: Removed deprecated module->new_wire() --- passes/cmds/connect.cc | 2 +- passes/cmds/delete.cc | 2 +- passes/cmds/splice.cc | 4 ++-- passes/memory/memory_share.cc | 4 ++-- passes/sat/freduce.cc | 4 ++-- passes/sat/miter.cc | 12 ++++++------ passes/sat/share.cc | 26 +++++++++++++------------- passes/techmap/simplemap.cc | 8 ++++---- 8 files changed, 31 insertions(+), 31 deletions(-) (limited to 'passes') diff --git a/passes/cmds/connect.cc b/passes/cmds/connect.cc index 7da2b9517..f99cb9b50 100644 --- a/passes/cmds/connect.cc +++ b/passes/cmds/connect.cc @@ -27,7 +27,7 @@ static void unset_drivers(RTLIL::Design *design, RTLIL::Module *module, SigMap & { CellTypes ct(design); - RTLIL::Wire *dummy_wire = module->new_wire(sig.width, NEW_ID); + RTLIL::Wire *dummy_wire = module->addWire(NEW_ID, sig.width); for (auto &it : module->cells) for (auto &port : it.second->connections) diff --git a/passes/cmds/delete.cc b/passes/cmds/delete.cc index 1c02752c2..ce6ac4aff 100644 --- a/passes/cmds/delete.cc +++ b/passes/cmds/delete.cc @@ -30,7 +30,7 @@ struct DeleteWireWorker sig.optimize(); for (auto &c : sig.chunks) if (c.wire != NULL && delete_wires_p->count(c.wire->name)) { - c.wire = module->new_wire(c.width, NEW_ID); + c.wire = module->addWire(NEW_ID, c.width); c.offset = 0; } } diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc index 6d920dbc5..a48a54a12 100644 --- a/passes/cmds/splice.cc +++ b/passes/cmds/splice.cc @@ -77,7 +77,7 @@ struct SpliceWorker cell->parameters["\\A_WIDTH"] = sig_a.width; cell->parameters["\\Y_WIDTH"] = sig.width; cell->connections["\\A"] = sig_a; - cell->connections["\\Y"] = module->new_wire(sig.width, NEW_ID); + cell->connections["\\Y"] = module->addWire(NEW_ID, sig.width); new_sig = cell->connections["\\Y"]; module->add(cell); } @@ -138,7 +138,7 @@ struct SpliceWorker cell->parameters["\\B_WIDTH"] = sig2.width; cell->connections["\\A"] = new_sig; cell->connections["\\B"] = sig2; - cell->connections["\\Y"] = module->new_wire(new_sig.width + sig2.width, NEW_ID); + cell->connections["\\Y"] = module->addWire(NEW_ID, new_sig.width + sig2.width); new_sig = cell->connections["\\Y"]; module->add(cell); } diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index dc015f969..578007a01 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -419,7 +419,7 @@ struct MemoryShareWorker if (0) { found_overlapping_bits_i_j: log(" Creating collosion-detect logic for port %d.\n", j); - RTLIL::SigSpec is_same_addr = module->new_wire(1, NEW_ID); + RTLIL::SigSpec is_same_addr = module->addWire(NEW_ID); module->addEq(NEW_ID, addr, wr_ports[j]->connections.at("\\ADDR"), is_same_addr); merged_en = mask_en_grouped(is_same_addr, merged_en, sigmap(wr_ports[j]->connections.at("\\EN"))); } @@ -603,7 +603,7 @@ struct MemoryShareWorker std::map, int> groups_en; RTLIL::SigSpec grouped_last_en, grouped_this_en, en; - RTLIL::Wire *grouped_en = module->new_wire(0, NEW_ID); + RTLIL::Wire *grouped_en = module->addWire(NEW_ID, 0); for (int j = 0; j < int(this_en.size()); j++) { std::pair key(last_en[j], this_en[j]); diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index d4b7b5c10..ac0415644 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -707,7 +707,7 @@ struct FreduceWorker log(" Connect slave%s: %s\n", grp[i].inverted ? " using inverter" : "", log_signal(grp[i].bit)); RTLIL::Cell *drv = drivers.at(grp[i].bit).first; - RTLIL::Wire *dummy_wire = module->new_wire(1, NEW_ID); + RTLIL::Wire *dummy_wire = module->addWire(NEW_ID); for (auto &port : drv->connections) if (ct.cell_output(drv->type, port.first)) sigmap(port.second).replace(grp[i].bit, dummy_wire, &port.second); @@ -716,7 +716,7 @@ struct FreduceWorker { if (inv_sig.width == 0) { - inv_sig = module->new_wire(1, NEW_ID); + inv_sig = module->addWire(NEW_ID); RTLIL::Cell *inv_cell = new RTLIL::Cell; inv_cell->name = NEW_ID; diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index 0ef9e9aaa..6e57fceb1 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -164,7 +164,7 @@ static void create_miter_equiv(struct Pass *that, std::vector args, if (flag_ignore_gold_x) { - RTLIL::SigSpec gold_x = miter_module->new_wire(w2_gold->width, NEW_ID); + RTLIL::SigSpec gold_x = miter_module->addWire(NEW_ID, w2_gold->width); for (int i = 0; i < w2_gold->width; i++) { RTLIL::Cell *eqx_cell = new RTLIL::Cell; eqx_cell->name = NEW_ID; @@ -180,8 +180,8 @@ static void create_miter_equiv(struct Pass *that, std::vector args, miter_module->add(eqx_cell); } - RTLIL::SigSpec gold_masked = miter_module->new_wire(w2_gold->width, NEW_ID); - RTLIL::SigSpec gate_masked = miter_module->new_wire(w2_gate->width, NEW_ID); + RTLIL::SigSpec gold_masked = miter_module->addWire(NEW_ID, w2_gold->width); + RTLIL::SigSpec gate_masked = miter_module->addWire(NEW_ID, w2_gate->width); RTLIL::Cell *or_gold_cell = new RTLIL::Cell; or_gold_cell->name = NEW_ID; @@ -219,7 +219,7 @@ static void create_miter_equiv(struct Pass *that, std::vector args, eq_cell->parameters["\\B_SIGNED"] = 0; eq_cell->connections["\\A"] = gold_masked; eq_cell->connections["\\B"] = gate_masked; - eq_cell->connections["\\Y"] = miter_module->new_wire(1, NEW_ID); + eq_cell->connections["\\Y"] = miter_module->addWire(NEW_ID); this_condition = eq_cell->connections["\\Y"]; miter_module->add(eq_cell); } @@ -235,7 +235,7 @@ static void create_miter_equiv(struct Pass *that, std::vector args, eq_cell->parameters["\\B_SIGNED"] = 0; eq_cell->connections["\\A"] = w2_gold; eq_cell->connections["\\B"] = w2_gate; - eq_cell->connections["\\Y"] = miter_module->new_wire(1, NEW_ID); + eq_cell->connections["\\Y"] = miter_module->addWire(NEW_ID); this_condition = eq_cell->connections["\\Y"]; miter_module->add(eq_cell); } @@ -261,7 +261,7 @@ static void create_miter_equiv(struct Pass *that, std::vector args, reduce_cell->parameters["\\Y_WIDTH"] = 1; reduce_cell->parameters["\\A_SIGNED"] = 0; reduce_cell->connections["\\A"] = all_conditions; - reduce_cell->connections["\\Y"] = miter_module->new_wire(1, NEW_ID); + reduce_cell->connections["\\Y"] = miter_module->addWire(NEW_ID); all_conditions = reduce_cell->connections["\\Y"]; miter_module->add(reduce_cell); } diff --git a/passes/sat/share.cc b/passes/sat/share.cc index 852d80782..42e59c475 100644 --- a/passes/sat/share.cc +++ b/passes/sat/share.cc @@ -276,11 +276,11 @@ struct ShareWorker int a_width = std::max(a1.width, a2.width); int y_width = std::max(y1.width, y2.width); - if (a1.width != a_width) a1 = module->addPos(NEW_ID, a1, module->new_wire(a_width, NEW_ID), a_signed)->connections.at("\\Y"); - if (a2.width != a_width) a2 = module->addPos(NEW_ID, a2, module->new_wire(a_width, NEW_ID), a_signed)->connections.at("\\Y"); + if (a1.width != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y"); + if (a2.width != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y"); RTLIL::SigSpec a = module->Mux(NEW_ID, a2, a1, act); - RTLIL::Wire *y = module->new_wire(y_width, NEW_ID); + RTLIL::Wire *y = module->addWire(NEW_ID, y_width); RTLIL::Cell *supercell = new RTLIL::Cell; supercell->name = NEW_ID; @@ -375,24 +375,24 @@ struct ShareWorker { a_width = std::max(y_width, a_width); - if (a1.width < y1.width) a1 = module->addPos(NEW_ID, a1, module->new_wire(y1.width, NEW_ID), true)->connections.at("\\Y"); - if (a2.width < y2.width) a2 = module->addPos(NEW_ID, a2, module->new_wire(y2.width, NEW_ID), true)->connections.at("\\Y"); + if (a1.width < y1.width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, y1.width), true)->connections.at("\\Y"); + if (a2.width < y2.width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, y2.width), true)->connections.at("\\Y"); - if (a1.width != a_width) a1 = module->addPos(NEW_ID, a1, module->new_wire(a_width, NEW_ID), false)->connections.at("\\Y"); - if (a2.width != a_width) a2 = module->addPos(NEW_ID, a2, module->new_wire(a_width, NEW_ID), false)->connections.at("\\Y"); + if (a1.width != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), false)->connections.at("\\Y"); + if (a2.width != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), false)->connections.at("\\Y"); } else { - if (a1.width != a_width) a1 = module->addPos(NEW_ID, a1, module->new_wire(a_width, NEW_ID), a_signed)->connections.at("\\Y"); - if (a2.width != a_width) a2 = module->addPos(NEW_ID, a2, module->new_wire(a_width, NEW_ID), a_signed)->connections.at("\\Y"); + if (a1.width != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y"); + if (a2.width != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y"); } - if (b1.width != b_width) b1 = module->addPos(NEW_ID, b1, module->new_wire(b_width, NEW_ID), b_signed)->connections.at("\\Y"); - if (b2.width != b_width) b2 = module->addPos(NEW_ID, b2, module->new_wire(b_width, NEW_ID), b_signed)->connections.at("\\Y"); + if (b1.width != b_width) b1 = module->addPos(NEW_ID, b1, module->addWire(NEW_ID, b_width), b_signed)->connections.at("\\Y"); + if (b2.width != b_width) b2 = module->addPos(NEW_ID, b2, module->addWire(NEW_ID, b_width), b_signed)->connections.at("\\Y"); RTLIL::SigSpec a = module->Mux(NEW_ID, a2, a1, act); RTLIL::SigSpec b = module->Mux(NEW_ID, b2, b1, act); - RTLIL::Wire *y = module->new_wire(y_width, NEW_ID); + RTLIL::Wire *y = module->addWire(NEW_ID, y_width); RTLIL::Cell *supercell = module->addCell(NEW_ID, c1->type); supercell->parameters["\\A_SIGNED"] = a_signed; @@ -617,7 +617,7 @@ struct ShareWorker RTLIL::SigSpec make_cell_activation_logic(const std::set> &activation_patterns) { - RTLIL::Wire *all_cases_wire = module->new_wire(0, NEW_ID); + RTLIL::Wire *all_cases_wire = module->addWire(NEW_ID, 0); for (auto &p : activation_patterns) { all_cases_wire->width++; module->addEq(NEW_ID, p.first, p.second, RTLIL::SigSpec(all_cases_wire, 1, all_cases_wire->width - 1)); diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc index e67b1e055..91f3b6124 100644 --- a/passes/techmap/simplemap.cc +++ b/passes/techmap/simplemap.cc @@ -89,7 +89,7 @@ static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell) if (cell->type == "$xnor") { - RTLIL::SigSpec sig_t = module->new_wire(width, NEW_ID); + RTLIL::SigSpec sig_t = module->addWire(NEW_ID, width); sig_t.expand(); for (int i = 0; i < width; i++) { @@ -158,7 +158,7 @@ static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) while (sig_a.width > 1) { - RTLIL::SigSpec sig_t = module->new_wire(sig_a.width / 2, NEW_ID); + RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig_a.width / 2); sig_t.expand(); for (int i = 0; i < sig_a.width; i += 2) @@ -182,7 +182,7 @@ static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) } if (cell->type == "$reduce_xnor") { - RTLIL::SigSpec sig_t = module->new_wire(1, NEW_ID); + RTLIL::SigSpec sig_t = module->addWire(NEW_ID); RTLIL::Cell *gate = new RTLIL::Cell; gate->name = NEW_ID; gate->type = "$_INV_"; @@ -206,7 +206,7 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig) while (sig.width > 1) { - RTLIL::SigSpec sig_t = module->new_wire(sig.width / 2, NEW_ID); + RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig.width / 2); sig_t.expand(); for (int i = 0; i < sig.width; i += 2) -- cgit v1.2.3 From 361e0d62ffd90b87c94bfc98ed3cbee1a745cd8f Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 21 Jul 2014 12:41:29 +0200 Subject: Replaced depricated NEW_WIRE macro with module->addWire() calls --- passes/proc/proc_dff.cc | 20 ++++++++++---------- passes/techmap/hilomap.cc | 4 ++-- 2 files changed, 12 insertions(+), 12 deletions(-) (limited to 'passes') diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index c18446512..13e4e6606 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -80,7 +80,7 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.width); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); cell->connections["\\A"] = sync_low_signals; - cell->connections["\\Y"] = sync_low_signals = NEW_WIRE(mod, 1); + cell->connections["\\Y"] = sync_low_signals = mod->addWire(NEW_ID); mod->add(cell); } @@ -92,7 +92,7 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.width); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); cell->connections["\\A"] = sync_low_signals; - cell->connections["\\Y"] = NEW_WIRE(mod, 1); + cell->connections["\\Y"] = mod->addWire(NEW_ID); sync_high_signals.append(cell->connections["\\Y"]); mod->add(cell); } @@ -105,7 +105,7 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_high_signals.width); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); cell->connections["\\A"] = sync_high_signals; - cell->connections["\\Y"] = sync_high_signals = NEW_WIRE(mod, 1); + cell->connections["\\Y"] = sync_high_signals = mod->addWire(NEW_ID); mod->add(cell); } @@ -116,7 +116,7 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S inv_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_d.width); inv_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_d.width); inv_cell->connections["\\A"] = sync_value; - inv_cell->connections["\\Y"] = sync_value_inv = NEW_WIRE(mod, sig_d.width); + inv_cell->connections["\\Y"] = sync_value_inv = mod->addWire(NEW_ID, sig_d.width); mod->add(inv_cell); RTLIL::Cell *mux_set_cell = new RTLIL::Cell; @@ -126,7 +126,7 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S mux_set_cell->connections["\\A"] = sig_sr_set; mux_set_cell->connections["\\B"] = sync_value; mux_set_cell->connections["\\S"] = sync_high_signals; - mux_set_cell->connections["\\Y"] = sig_sr_set = NEW_WIRE(mod, sig_d.width); + mux_set_cell->connections["\\Y"] = sig_sr_set = mod->addWire(NEW_ID, sig_d.width); mod->add(mux_set_cell); RTLIL::Cell *mux_clr_cell = new RTLIL::Cell; @@ -136,7 +136,7 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S mux_clr_cell->connections["\\A"] = sig_sr_clr; mux_clr_cell->connections["\\B"] = sync_value_inv; mux_clr_cell->connections["\\S"] = sync_high_signals; - mux_clr_cell->connections["\\Y"] = sig_sr_clr = NEW_WIRE(mod, sig_d.width); + mux_clr_cell->connections["\\Y"] = sig_sr_clr = mod->addWire(NEW_ID, sig_d.width); mod->add(mux_clr_cell); } @@ -168,9 +168,9 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec std::stringstream sstr; sstr << "$procdff$" << (RTLIL::autoidx++); - RTLIL::SigSpec sig_set_inv = NEW_WIRE(mod, sig_in.width); - RTLIL::SigSpec sig_sr_set = NEW_WIRE(mod, sig_in.width); - RTLIL::SigSpec sig_sr_clr = NEW_WIRE(mod, sig_in.width); + RTLIL::SigSpec sig_set_inv = mod->addWire(NEW_ID, sig_in.width); + RTLIL::SigSpec sig_sr_set = mod->addWire(NEW_ID, sig_in.width); + RTLIL::SigSpec sig_sr_clr = mod->addWire(NEW_ID, sig_in.width); RTLIL::Cell *inv_set = new RTLIL::Cell; inv_set->name = NEW_ID; @@ -315,7 +315,7 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) { sync_level = new RTLIL::SyncRule; sync_level->type = RTLIL::SyncType::ST1; - sync_level->signal = NEW_WIRE(mod, 1); + sync_level->signal = mod->addWire(NEW_ID); sync_level->actions.push_back(RTLIL::SigSig(sig, rstval)); free_sync_level = true; diff --git a/passes/techmap/hilomap.cc b/passes/techmap/hilomap.cc index bc5caa38c..d24f557e2 100644 --- a/passes/techmap/hilomap.cc +++ b/passes/techmap/hilomap.cc @@ -34,7 +34,7 @@ void hilomap_worker(RTLIL::SigSpec &sig) for (auto &c : sig.chunks) { if (c.wire == NULL && (c.data.bits.at(0) == RTLIL::State::S1) && !hicell_celltype.empty()) { if (!singleton_mode || last_hi.width == 0) { - last_hi = RTLIL::SigChunk(NEW_WIRE(module, 1)); + last_hi = RTLIL::SigChunk(module->addWire(NEW_ID)); RTLIL::Cell *cell = new RTLIL::Cell; cell->name = NEW_ID; cell->type = RTLIL::escape_id(hicell_celltype); @@ -45,7 +45,7 @@ void hilomap_worker(RTLIL::SigSpec &sig) } if (c.wire == NULL && (c.data.bits.at(0) == RTLIL::State::S0) && !locell_celltype.empty()) { if (!singleton_mode || last_lo.width == 0) { - last_lo = RTLIL::SigChunk(NEW_WIRE(module, 1)); + last_lo = RTLIL::SigChunk(module->addWire(NEW_ID)); RTLIL::Cell *cell = new RTLIL::Cell; cell->name = NEW_ID; cell->type = RTLIL::escape_id(locell_celltype); -- cgit v1.2.3 From e035f1d886b30329c1c061894146a5c6f92b4f7a Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 21 Jul 2014 14:09:11 +0200 Subject: Added opt_const support for simple identities --- passes/opt/opt_const.cc | 69 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) (limited to 'passes') diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index da71ec30e..76948344e 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -288,6 +288,75 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons } } + // checking for simple identities + { + bool identity_bu0 = false; + bool identity_wrt_a = false; + bool identity_wrt_b = false; + + if (cell->type == "$add" || cell->type == "$sub" || cell->type == "$or" || cell->type == "$xor") + { + RTLIL::SigSpec a = assign_map(cell->connections["\\A"]); + RTLIL::SigSpec b = assign_map(cell->connections["\\B"]); + + if (cell->type != "$sub" && a.is_fully_const() && a.as_bool() == false) + identity_wrt_b = true; + + if (b.is_fully_const() && b.as_bool() == false) + identity_wrt_a = true; + } + + if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr") + { + RTLIL::SigSpec b = assign_map(cell->connections["\\B"]); + + if (b.is_fully_const() && b.as_bool() == false) + identity_wrt_a = true, identity_bu0 = true; + } + + if (cell->type == "$mul") + { + RTLIL::SigSpec a = assign_map(cell->connections["\\A"]); + RTLIL::SigSpec b = assign_map(cell->connections["\\B"]); + + if (a.is_fully_const() && a.width <= 32 && a.as_int() == 1) + identity_wrt_b = true; + + if (b.is_fully_const() && b.width <= 32 && b.as_int() == 1) + identity_wrt_a = true; + } + + if (cell->type == "$div") + { + RTLIL::SigSpec b = assign_map(cell->connections["\\B"]); + + if (b.is_fully_const() && b.width <= 32 && b.as_int() == 1) + identity_wrt_a = true; + } + + if (identity_wrt_a || identity_wrt_b) + { + log("Replacing %s cell `%s' in module `%s' with identity for port %c.\n", + cell->type.c_str(), cell->name.c_str(), module->name.c_str(), identity_wrt_a ? 'A' : 'B'); + + if (!identity_wrt_a) { + cell->connections.at("\\A") = cell->connections.at("\\B"); + cell->parameters.at("\\A_WIDTH") = cell->parameters.at("\\B_WIDTH"); + cell->parameters.at("\\A_SIGNED") = cell->parameters.at("\\B_SIGNED"); + } + + cell->type = identity_bu0 ? "$bu0" : "$pos"; + cell->connections.erase("\\B"); + cell->parameters.erase("\\B_WIDTH"); + cell->parameters.erase("\\B_SIGNED"); + cell->check(); + + OPT_DID_SOMETHING = true; + did_something = true; + goto next_cell; + } + } + if (mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->connections["\\A"] == RTLIL::SigSpec(0, 1) && cell->connections["\\B"] == RTLIL::SigSpec(1, 1)) { replace_cell(module, cell, "mux_bool", "\\Y", cell->connections["\\S"]); -- cgit v1.2.3 From 1241a9fd5073d327d49f1af47db37214a4628ed8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 21 Jul 2014 16:34:16 +0200 Subject: Added "opt_const -fine" and "opt_reduce -fine" --- passes/opt/opt.cc | 14 ++++-- passes/opt/opt_const.cc | 121 ++++++++++++++++++++++++++++++++++++++++++++--- passes/opt/opt_reduce.cc | 24 ++++++++-- 3 files changed, 144 insertions(+), 15 deletions(-) (limited to 'passes') diff --git a/passes/opt/opt.cc b/passes/opt/opt.cc index 8f4725e1c..62aa48bee 100644 --- a/passes/opt/opt.cc +++ b/passes/opt/opt.cc @@ -31,7 +31,7 @@ struct OptPass : public Pass { { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); - log(" opt [-purge] [-mux_undef] [-mux_bool] [-undriven] [selection]\n"); + log(" opt [-purge] [-mux_undef] [-mux_bool] [-undriven] [-fine] [selection]\n"); log("\n"); log("This pass calls all the other opt_* passes in a useful order. This performs\n"); log("a series of trivial optimizations and cleanups. This pass executes the other\n"); @@ -42,11 +42,11 @@ struct OptPass : public Pass { log("\n"); log(" do\n"); log(" opt_muxtree\n"); - log(" opt_reduce\n"); + log(" opt_reduce [-fine]\n"); log(" opt_share\n"); log(" opt_rmdff\n"); log(" opt_clean [-purge]\n"); - log(" opt_const [-mux_undef] [-mux_bool] [-undriven]\n"); + log(" opt_const [-mux_undef] [-mux_bool] [-undriven] [-fine]\n"); log(" while [changed design]\n"); log("\n"); } @@ -54,6 +54,7 @@ struct OptPass : public Pass { { std::string opt_clean_args; std::string opt_const_args; + std::string opt_reduce_args; log_header("Executing OPT pass (performing simple optimizations).\n"); log_push(); @@ -76,6 +77,11 @@ struct OptPass : public Pass { opt_const_args += " -undriven"; continue; } + if (args[argidx] == "-fine") { + opt_const_args += " -fine"; + opt_reduce_args += " -fine"; + continue; + } break; } extra_args(args, argidx, design); @@ -88,7 +94,7 @@ struct OptPass : public Pass { while (1) { OPT_DID_SOMETHING = false; Pass::call(design, "opt_muxtree"); - Pass::call(design, "opt_reduce"); + Pass::call(design, "opt_reduce" + opt_reduce_args); Pass::call(design, "opt_share"); Pass::call(design, "opt_rmdff"); Pass::call(design, "opt_clean" + opt_clean_args); diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index 76948344e..a17ca6792 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -25,11 +25,11 @@ #include #include #include -#include +#include static bool did_something; -void replace_undriven(RTLIL::Design *design, RTLIL::Module *module) +static void replace_undriven(RTLIL::Design *design, RTLIL::Module *module) { CellTypes ct(design); SigMap sigmap(module); @@ -71,7 +71,7 @@ void replace_undriven(RTLIL::Design *design, RTLIL::Module *module) } } -void replace_cell(RTLIL::Module *module, RTLIL::Cell *cell, std::string info, std::string out_port, RTLIL::SigSpec out_val) +static void replace_cell(RTLIL::Module *module, RTLIL::Cell *cell, std::string info, std::string out_port, RTLIL::SigSpec out_val) { RTLIL::SigSpec Y = cell->connections[out_port]; log("Replacing %s cell `%s' (%s) in module `%s' with constant driver `%s = %s'.\n", @@ -85,7 +85,103 @@ void replace_cell(RTLIL::Module *module, RTLIL::Cell *cell, std::string info, st did_something = true; } -void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool consume_x, bool mux_undef, bool mux_bool) +static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutative, bool extend_u0, SigMap &sigmap) +{ + std::string b_name = cell->connections.count("\\B") ? "\\B" : "\\A"; + + bool a_signed = cell->parameters.at("\\A_SIGNED").as_bool(); + bool b_signed = cell->parameters.at(b_name + "_SIGNED").as_bool(); + + RTLIL::SigSpec sig_a = sigmap(cell->connections.at("\\A")); + RTLIL::SigSpec sig_b = sigmap(cell->connections.at(b_name)); + RTLIL::SigSpec sig_y = sigmap(cell->connections.at("\\Y")); + + if (extend_u0) { + sig_a.extend_u0(sig_y.width, a_signed); + sig_b.extend_u0(sig_y.width, b_signed); + } else { + sig_a.extend(sig_y.width, a_signed); + sig_b.extend(sig_y.width, b_signed); + } + + std::vector bits_a = sig_a, bits_b = sig_b, bits_y = sig_y; + + enum { GRP_DYN, GRP_CONST_A, GRP_CONST_B, GRP_CONST_AB, GRP_N }; + std::map, std::set> grouped_bits[GRP_N]; + + for (int i = 0; i < SIZE(bits_y); i++) + { + int group_idx = GRP_DYN; + RTLIL::SigBit bit_a = bits_a[i], bit_b = bits_b[i]; + + if (bit_a.wire == NULL && bit_b.wire == NULL) + group_idx = GRP_CONST_AB; + else if (bit_a.wire == NULL) + group_idx = GRP_CONST_A; + else if (bit_b.wire == NULL && commutative) + group_idx = GRP_CONST_A, std::swap(bit_a, bit_b); + else if (bit_b.wire == NULL) + group_idx = GRP_CONST_B; + + grouped_bits[group_idx][std::pair(bit_a, bit_b)].insert(bits_y[i]); + } + + for (int i = 0; i < GRP_N; i++) + if (SIZE(grouped_bits[i]) == SIZE(bits_y)) + return false; + + log("Replacing %s cell `%s' in module `%s' with cells using grouped bits:\n", + log_id(cell->type), log_id(cell), log_id(module)); + + for (int i = 0; i < GRP_N; i++) + { + if (grouped_bits[i].empty()) + continue; + + RTLIL::Wire *new_y = module->addWire(NEW_ID, SIZE(grouped_bits[i])); + RTLIL::SigSpec new_a, new_b; + RTLIL::SigSig new_conn; + + for (auto &it : grouped_bits[i]) { + for (auto &bit : it.second) { + new_conn.first.append_bit(bit); + new_conn.second.append_bit(RTLIL::SigBit(new_y, new_a.width)); + } + new_a.append_bit(it.first.first); + new_b.append_bit(it.first.second); + } + + RTLIL::Cell *c = module->addCell(NEW_ID, cell->type); + + c->connections["\\A"] = new_a; + c->parameters["\\A_WIDTH"] = new_a.width; + c->parameters["\\A_SIGNED"] = false; + + if (b_name == "\\B") { + c->connections["\\B"] = new_b; + c->parameters["\\B_WIDTH"] = new_b.width; + c->parameters["\\B_SIGNED"] = false; + } + + c->connections["\\Y"] = new_y; + c->parameters["\\Y_WIDTH"] = new_y->width; + c->check(); + + module->connections.push_back(new_conn); + + log(" New cell `%s': A=%s", log_id(c), log_signal(new_a)); + if (b_name == "\\B") + log(", B=%s", log_signal(new_b)); + log("\n"); + } + + module->remove(cell); + OPT_DID_SOMETHING = true; + did_something = true; + return true; +} + +static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool consume_x, bool mux_undef, bool mux_bool, bool do_fine) { if (!design->selected(module)) return; @@ -108,6 +204,11 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons #define ACTION_DO(_p_, _s_) do { replace_cell(module, cell, input.as_string(), _p_, _s_); goto next_cell; } while (0) #define ACTION_DO_Y(_v_) ACTION_DO("\\Y", RTLIL::SigSpec(RTLIL::State::S ## _v_)) + if (do_fine && (cell->type == "$not" || cell->type == "$pos" || cell->type == "$bu0" || + cell->type == "$and" || cell->type == "$or" || cell->type == "$xor" || cell->type == "$xnor")) + if (group_cell_inputs(module, cell, true, cell->type != "$pos", assign_map)) + goto next_cell; + if ((cell->type == "$_INV_" || cell->type == "$not" || cell->type == "$logic_not") && cell->connections["\\Y"].width == 1 && invert_map.count(assign_map(cell->connections["\\A"])) != 0) { replace_cell(module, cell, "double_invert", "\\Y", invert_map.at(assign_map(cell->connections["\\A"]))); @@ -573,12 +674,16 @@ struct OptConstPass : public Pass { log(" -undriven\n"); log(" replace undriven nets with undef (x) constants\n"); log("\n"); + log(" -fine\n"); + log(" perform fine-grain optimizations\n"); + log("\n"); } virtual void execute(std::vector args, RTLIL::Design *design) { bool mux_undef = false; bool mux_bool = false; bool undriven = false; + bool do_fine = false; log_header("Executing OPT_CONST pass (perform const folding).\n"); log_push(); @@ -597,6 +702,10 @@ struct OptConstPass : public Pass { undriven = true; continue; } + if (args[argidx] == "-fine") { + do_fine = true; + continue; + } break; } extra_args(args, argidx, design); @@ -609,9 +718,9 @@ struct OptConstPass : public Pass { do { do { did_something = false; - replace_const_cells(design, mod_it.second, false, mux_undef, mux_bool); + replace_const_cells(design, mod_it.second, false, mux_undef, mux_bool, do_fine); } while (did_something); - replace_const_cells(design, mod_it.second, true, mux_undef, mux_bool); + replace_const_cells(design, mod_it.second, true, mux_undef, mux_bool, do_fine); } while (did_something); } diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc index a0c7a027f..93945e49a 100644 --- a/passes/opt/opt_reduce.cc +++ b/passes/opt/opt_reduce.cc @@ -244,7 +244,7 @@ struct OptReduceWorker } } - OptReduceWorker(RTLIL::Design *design, RTLIL::Module *module) : + OptReduceWorker(RTLIL::Design *design, RTLIL::Module *module, bool do_fine) : design(design), module(module), assign_map(module) { log(" Optimizing cells in module %s.\n", module->name.c_str()); @@ -318,7 +318,7 @@ struct OptReduceWorker // this optimization is to aggressive for most coarse-grain applications. // but we always want it for multiplexers driving write enable ports. - if (mem_wren_sigs.check_any(assign_map(cell->connections.at("\\Y")))) + if (do_fine || mem_wren_sigs.check_any(assign_map(cell->connections.at("\\Y")))) opt_mux_bits(cell); opt_mux(cell); @@ -333,7 +333,7 @@ struct OptReducePass : public Pass { { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); - log(" opt_reduce [selection]\n"); + log(" opt_reduce [options] [selection]\n"); log("\n"); log("This pass performs two interlinked optimizations:\n"); log("\n"); @@ -343,17 +343,31 @@ struct OptReducePass : public Pass { log("2. it identifies duplicated inputs to MUXes and replaces them with a single\n"); log("input with the original control signals OR'ed together.\n"); log("\n"); + log(" -fine\n"); + log(" perform fine-grain optimizations\n"); + log("\n"); } virtual void execute(std::vector args, RTLIL::Design *design) { + bool do_fine = false; + log_header("Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n"); - extra_args(args, 1, design); + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) { + if (args[argidx] == "-fine") { + do_fine = true; + continue; + } + break; + } + extra_args(args, argidx, design); int total_count = 0; for (auto &mod_it : design->modules) { if (!design->selected(mod_it.second)) continue; - OptReduceWorker worker(design, mod_it.second); + OptReduceWorker worker(design, mod_it.second, do_fine); total_count += worker.total_count; } -- cgit v1.2.3 From 1873480ca5f5ec9ec6aa1b80b91ae047a6982002 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 21 Jul 2014 17:19:50 +0200 Subject: Added mul to mux conversion to "opt_const -fine" --- passes/opt/opt_const.cc | 55 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) (limited to 'passes') diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index a17ca6792..4cfee59d2 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -647,6 +647,61 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo ACTION_DO("\\Y", cell->connections["\\A"]); } + if (do_fine && cell->type == "$mul") + { + bool a_signed = cell->parameters["\\A_SIGNED"].as_bool(); + bool b_signed = cell->parameters["\\B_SIGNED"].as_bool(); + bool swapped_ab = false; + + RTLIL::SigSpec sig_a = assign_map(cell->connections["\\A"]); + RTLIL::SigSpec sig_b = assign_map(cell->connections["\\B"]); + RTLIL::SigSpec sig_y = assign_map(cell->connections["\\Y"]); + + if (sig_b.is_fully_const() && sig_b.width <= 32) + std::swap(sig_a, sig_b), std::swap(a_signed, b_signed), swapped_ab = true; + + if (sig_a.is_fully_def() && sig_a.width <= 32) + { + int a_val = sig_a.as_int(); + + if (a_val == 0) + { + log("Replacing multiply-by-zero cell `%s' in module `%s' with zero-driver.\n", + cell->name.c_str(), module->name.c_str()); + + module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.width))); + module->remove(cell); + + OPT_DID_SOMETHING = true; + did_something = true; + goto next_cell; + } + + for (int i = 0; i < sig_a.width - (a_signed ? 1 : 0); i++) + if (a_val == (1 << i)) + { + log("Replacing multiply-by-%d cell `%s' in module `%s' with shift-by-%d.\n", + a_val, cell->name.c_str(), module->name.c_str(), i); + + if (swapped_ab) { + cell->connections["\\A"] = cell->connections["\\B"]; + cell->parameters["\\A_WIDTH"] = cell->parameters["\\B_WIDTH"]; + cell->parameters["\\A_SIGNED"] = cell->parameters["\\B_SIGNED"]; + } + + cell->type = "$shl"; + cell->parameters["\\B_WIDTH"] = 6; + cell->parameters["\\B_SIGNED"] = false; + cell->connections["\\B"] = RTLIL::SigSpec(i, 6); + cell->check(); + + OPT_DID_SOMETHING = true; + did_something = true; + goto next_cell; + } + } + } + next_cell:; #undef ACTION_DO #undef ACTION_DO_Y -- cgit v1.2.3 From 137dbf3cf7edbec8c31dfdb2c9c0bcc413c5786d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 21 Jul 2014 21:38:55 +0200 Subject: Added "opt_const -keepdc" --- passes/opt/opt.cc | 13 +++- passes/opt/opt_const.cc | 170 ++++++++++++++++++++++++++++++++++++++++++++---- 2 files changed, 168 insertions(+), 15 deletions(-) (limited to 'passes') diff --git a/passes/opt/opt.cc b/passes/opt/opt.cc index 62aa48bee..33e1507bc 100644 --- a/passes/opt/opt.cc +++ b/passes/opt/opt.cc @@ -31,7 +31,7 @@ struct OptPass : public Pass { { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); - log(" opt [-purge] [-mux_undef] [-mux_bool] [-undriven] [-fine] [selection]\n"); + log(" opt [options] [selection]\n"); log("\n"); log("This pass calls all the other opt_* passes in a useful order. This performs\n"); log("a series of trivial optimizations and cleanups. This pass executes the other\n"); @@ -46,8 +46,11 @@ struct OptPass : public Pass { log(" opt_share\n"); log(" opt_rmdff\n"); log(" opt_clean [-purge]\n"); - log(" opt_const [-mux_undef] [-mux_bool] [-undriven] [-fine]\n"); - log(" while [changed design]\n"); + log(" opt_const [-mux_undef] [-mux_bool] [-undriven] [-fine] [-keepdc]\n"); + log(" while \n"); + log("\n"); + log("Note: Options in square brackets (such as [-keepdc]) are passed through to\n"); + log("the opt_* commands when given to 'opt'.\n"); log("\n"); } virtual void execute(std::vector args, RTLIL::Design *design) @@ -82,6 +85,10 @@ struct OptPass : public Pass { opt_reduce_args += " -fine"; continue; } + if (args[argidx] == "-keepdc") { + opt_const_args += " -keepdc"; + continue; + } break; } extra_args(args, argidx, design); diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index 4cfee59d2..e855e45ee 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -74,6 +74,8 @@ static void replace_undriven(RTLIL::Design *design, RTLIL::Module *module) static void replace_cell(RTLIL::Module *module, RTLIL::Cell *cell, std::string info, std::string out_port, RTLIL::SigSpec out_val) { RTLIL::SigSpec Y = cell->connections[out_port]; + out_val.extend_u0(Y.width, false); + log("Replacing %s cell `%s' (%s) in module `%s' with constant driver `%s = %s'.\n", cell->type.c_str(), cell->name.c_str(), info.c_str(), module->name.c_str(), log_signal(Y), log_signal(out_val)); @@ -114,6 +116,12 @@ static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool com int group_idx = GRP_DYN; RTLIL::SigBit bit_a = bits_a[i], bit_b = bits_b[i]; + if (cell->type == "$or" && (bit_a == RTLIL::State::S1 || bit_b == RTLIL::State::S1)) + bit_a = bit_b = RTLIL::State::S1; + + if (cell->type == "$and" && (bit_a == RTLIL::State::S0 || bit_b == RTLIL::State::S0)) + bit_a = bit_b = RTLIL::State::S0; + if (bit_a.wire == NULL && bit_b.wire == NULL) group_idx = GRP_CONST_AB; else if (bit_a.wire == NULL) @@ -181,7 +189,7 @@ static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool com return true; } -static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool consume_x, bool mux_undef, bool mux_bool, bool do_fine) +static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool consume_x, bool mux_undef, bool mux_bool, bool do_fine, bool keepdc) { if (!design->selected(module)) return; @@ -204,10 +212,132 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo #define ACTION_DO(_p_, _s_) do { replace_cell(module, cell, input.as_string(), _p_, _s_); goto next_cell; } while (0) #define ACTION_DO_Y(_v_) ACTION_DO("\\Y", RTLIL::SigSpec(RTLIL::State::S ## _v_)) - if (do_fine && (cell->type == "$not" || cell->type == "$pos" || cell->type == "$bu0" || - cell->type == "$and" || cell->type == "$or" || cell->type == "$xor" || cell->type == "$xnor")) - if (group_cell_inputs(module, cell, true, cell->type != "$pos", assign_map)) + if (do_fine) + { + if (cell->type == "$not" || cell->type == "$pos" || cell->type == "$bu0" || + cell->type == "$and" || cell->type == "$or" || cell->type == "$xor" || cell->type == "$xnor") + if (group_cell_inputs(module, cell, true, cell->type != "$pos", assign_map)) + goto next_cell; + + if (cell->type == "$reduce_and") + { + RTLIL::SigSpec sig_a = assign_map(cell->connections.at("\\A")); + + RTLIL::State new_a = RTLIL::State::S1; + for (auto &bit : sig_a.to_sigbit_vector()) + if (bit == RTLIL::State::Sx) { + if (new_a == RTLIL::State::S1) + new_a = RTLIL::State::Sx; + } else if (bit == RTLIL::State::S0) { + new_a = RTLIL::State::S0; + break; + } else if (bit.wire != NULL) { + new_a = RTLIL::State::Sm; + } + + if (new_a != RTLIL::State::Sm && RTLIL::SigSpec(new_a) != sig_a) { + log("Replacing port A of %s cell `%s' in module `%s' with constant driver: %s -> %s\n", + cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a)); + cell->connections.at("\\A") = sig_a = new_a; + cell->parameters.at("\\A_WIDTH") = 1; + OPT_DID_SOMETHING = true; + did_something = true; + } + } + + if (cell->type == "$logic_not" || cell->type == "$logic_and" || cell->type == "$logic_or" || cell->type == "$reduce_or" || cell->type == "$reduce_bool") + { + RTLIL::SigSpec sig_a = assign_map(cell->connections.at("\\A")); + + RTLIL::State new_a = RTLIL::State::S0; + for (auto &bit : sig_a.to_sigbit_vector()) + if (bit == RTLIL::State::Sx) { + if (new_a == RTLIL::State::S0) + new_a = RTLIL::State::Sx; + } else if (bit == RTLIL::State::S1) { + new_a = RTLIL::State::S1; + break; + } else if (bit.wire != NULL) { + new_a = RTLIL::State::Sm; + } + + if (new_a != RTLIL::State::Sm && RTLIL::SigSpec(new_a) != sig_a) { + log("Replacing port A of %s cell `%s' in module `%s' with constant driver: %s -> %s\n", + cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a)); + cell->connections.at("\\A") = sig_a = new_a; + cell->parameters.at("\\A_WIDTH") = 1; + OPT_DID_SOMETHING = true; + did_something = true; + } + } + + if (cell->type == "$logic_and" || cell->type == "$logic_or") + { + RTLIL::SigSpec sig_b = assign_map(cell->connections.at("\\B")); + + RTLIL::State new_b = RTLIL::State::S0; + for (auto &bit : sig_b.to_sigbit_vector()) + if (bit == RTLIL::State::Sx) { + if (new_b == RTLIL::State::S0) + new_b = RTLIL::State::Sx; + } else if (bit == RTLIL::State::S1) { + new_b = RTLIL::State::S1; + break; + } else if (bit.wire != NULL) { + new_b = RTLIL::State::Sm; + } + + if (new_b != RTLIL::State::Sm && RTLIL::SigSpec(new_b) != sig_b) { + log("Replacing port B of %s cell `%s' in module `%s' with constant driver: %s -> %s\n", + cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_b), log_signal(new_b)); + cell->connections.at("\\B") = sig_b = new_b; + cell->parameters.at("\\B_WIDTH") = 1; + OPT_DID_SOMETHING = true; + did_something = true; + } + } + } + + if (cell->type == "$logic_or" && (assign_map(cell->connections.at("\\A")) == RTLIL::State::S1 || assign_map(cell->connections.at("\\B")) == RTLIL::State::S1)) { + replace_cell(module, cell, "one high", "\\Y", RTLIL::State::S1); + goto next_cell; + } + + if (cell->type == "$logic_and" && (assign_map(cell->connections.at("\\A")) == RTLIL::State::S0 || assign_map(cell->connections.at("\\B")) == RTLIL::State::S0)) { + replace_cell(module, cell, "one low", "\\Y", RTLIL::State::S0); + goto next_cell; + } + + if (cell->type == "$reduce_xor" || cell->type == "$reduce_xnor" || + cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr" || + cell->type == "$lt" || cell->type == "$le" || cell->type == "$ge" || cell->type == "$gt" || + cell->type == "$neg" || cell->type == "$add" || cell->type == "$sub" || + cell->type == "$mul" || cell->type == "$div" || cell->type == "$mod" || cell->type == "$pow") + { + RTLIL::SigSpec sig_a = assign_map(cell->connections.at("\\A")); + RTLIL::SigSpec sig_b = cell->connections.count("\\B") ? assign_map(cell->connections.at("\\B")) : RTLIL::SigSpec(); + + if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr") + sig_a = RTLIL::SigSpec(); + + for (auto &bit : sig_a.to_sigbit_vector()) + if (bit == RTLIL::State::Sx) + goto found_the_x_bit; + + for (auto &bit : sig_b.to_sigbit_vector()) + if (bit == RTLIL::State::Sx) + goto found_the_x_bit; + + if (0) { + found_the_x_bit: + if (cell->type == "$reduce_xor" || cell->type == "$reduce_xnor" || + cell->type == "$lt" || cell->type == "$le" || cell->type == "$ge" || cell->type == "$gt") + replace_cell(module, cell, "x-bit in input", "\\Y", RTLIL::State::Sx); + else + replace_cell(module, cell, "x-bit in input", "\\Y", RTLIL::SigSpec(RTLIL::State::Sx, cell->connections.at("\\Y").width)); goto next_cell; + } + } if ((cell->type == "$_INV_" || cell->type == "$not" || cell->type == "$logic_not") && cell->connections["\\Y"].width == 1 && invert_map.count(assign_map(cell->connections["\\A"])) != 0) { @@ -389,7 +519,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo } } - // checking for simple identities + if (!keepdc) { bool identity_bu0 = false; bool identity_wrt_a = false; @@ -647,7 +777,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo ACTION_DO("\\Y", cell->connections["\\A"]); } - if (do_fine && cell->type == "$mul") + if (!keepdc && cell->type == "$mul") { bool a_signed = cell->parameters["\\A_SIGNED"].as_bool(); bool b_signed = cell->parameters["\\B_SIGNED"].as_bool(); @@ -677,22 +807,27 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo goto next_cell; } - for (int i = 0; i < sig_a.width - (a_signed ? 1 : 0); i++) + for (int i = 1; i < (a_signed ? sig_a.width-1 : sig_a.width); i++) if (a_val == (1 << i)) { log("Replacing multiply-by-%d cell `%s' in module `%s' with shift-by-%d.\n", a_val, cell->name.c_str(), module->name.c_str(), i); - if (swapped_ab) { + if (!swapped_ab) { cell->connections["\\A"] = cell->connections["\\B"]; cell->parameters["\\A_WIDTH"] = cell->parameters["\\B_WIDTH"]; cell->parameters["\\A_SIGNED"] = cell->parameters["\\B_SIGNED"]; } + std::vector new_b = RTLIL::SigSpec(i, 6); + + while (SIZE(new_b) > 1 && new_b.back() == RTLIL::State::S0) + new_b.pop_back(); + cell->type = "$shl"; - cell->parameters["\\B_WIDTH"] = 6; + cell->parameters["\\B_WIDTH"] = SIZE(new_b); cell->parameters["\\B_SIGNED"] = false; - cell->connections["\\B"] = RTLIL::SigSpec(i, 6); + cell->connections["\\B"] = new_b; cell->check(); OPT_DID_SOMETHING = true; @@ -729,6 +864,12 @@ struct OptConstPass : public Pass { log(" -undriven\n"); log(" replace undriven nets with undef (x) constants\n"); log("\n"); + log(" -keepdc\n"); + log(" some optimizations change the behavior of the circuit with respect to\n"); + log(" don't-care bits. for example in 'a+0' a single x-bit in 'a' will cause\n"); + log(" all result bits to be set to x. this behavior changes when 'a+0' is\n"); + log(" replaced by 'a'. the -keepdc option disables all such optimizations.\n"); + log("\n"); log(" -fine\n"); log(" perform fine-grain optimizations\n"); log("\n"); @@ -739,6 +880,7 @@ struct OptConstPass : public Pass { bool mux_bool = false; bool undriven = false; bool do_fine = false; + bool keepdc = false; log_header("Executing OPT_CONST pass (perform const folding).\n"); log_push(); @@ -761,6 +903,10 @@ struct OptConstPass : public Pass { do_fine = true; continue; } + if (args[argidx] == "-keepdc") { + keepdc = true; + continue; + } break; } extra_args(args, argidx, design); @@ -773,9 +919,9 @@ struct OptConstPass : public Pass { do { do { did_something = false; - replace_const_cells(design, mod_it.second, false, mux_undef, mux_bool, do_fine); + replace_const_cells(design, mod_it.second, false, mux_undef, mux_bool, do_fine, keepdc); } while (did_something); - replace_const_cells(design, mod_it.second, true, mux_undef, mux_bool, do_fine); + replace_const_cells(design, mod_it.second, true, mux_undef, mux_bool, do_fine, keepdc); } while (did_something); } -- cgit v1.2.3 From a233762a815fc180b371f699e865a7d7aed77bca Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 22 Jul 2014 19:56:17 +0200 Subject: SigSpec refactoring: renamed chunks and width to __chunks and __width --- passes/abc/abc.cc | 68 ++++++++++++------------ passes/abc/blifparse.cc | 10 ++-- passes/cmds/connect.cc | 2 +- passes/cmds/connwrappers.cc | 8 +-- passes/cmds/delete.cc | 2 +- passes/cmds/scatter.cc | 2 +- passes/cmds/scc.cc | 2 +- passes/cmds/select.cc | 2 +- passes/cmds/setundef.cc | 4 +- passes/cmds/show.cc | 34 ++++++------ passes/cmds/splice.cc | 18 +++---- passes/cmds/splitnets.cc | 4 +- passes/fsm/fsm_detect.cc | 4 +- passes/fsm/fsm_expand.cc | 18 +++---- passes/fsm/fsm_extract.cc | 38 +++++++------- passes/fsm/fsm_map.cc | 30 +++++------ passes/fsm/fsm_opt.cc | 18 +++---- passes/fsm/fsmdata.h | 8 +-- passes/hierarchy/hierarchy.cc | 4 +- passes/hierarchy/submod.cc | 4 +- passes/memory/memory_collect.cc | 32 ++++++------ passes/memory/memory_dff.cc | 12 ++--- passes/memory/memory_map.cc | 8 +-- passes/memory/memory_share.cc | 12 ++--- passes/opt/opt_clean.cc | 28 +++++----- passes/opt/opt_const.cc | 92 ++++++++++++++++----------------- passes/opt/opt_muxtree.cc | 14 ++--- passes/opt/opt_reduce.cc | 28 +++++----- passes/opt/opt_rmdff.cc | 14 ++--- passes/opt/opt_share.cc | 2 +- passes/proc/proc_arst.cc | 18 +++---- passes/proc/proc_clean.cc | 8 +-- passes/proc/proc_dff.cc | 82 ++++++++++++++--------------- passes/proc/proc_init.cc | 12 ++--- passes/proc/proc_mux.cc | 44 ++++++++-------- passes/sat/eval.cc | 66 +++++++++++------------ passes/sat/expose.cc | 2 +- passes/sat/freduce.cc | 2 +- passes/sat/miter.cc | 8 +-- passes/sat/sat.cc | 46 ++++++++--------- passes/sat/share.cc | 44 ++++++++-------- passes/techmap/extract.cc | 24 ++++----- passes/techmap/hilomap.cc | 2 +- passes/techmap/simplemap.cc | 112 ++++++++++++++++++++-------------------- passes/techmap/techmap.cc | 18 +++---- 45 files changed, 505 insertions(+), 505 deletions(-) (limited to 'passes') diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index 30e78e588..e21be30b8 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -69,8 +69,8 @@ static RTLIL::SigSpec clk_sig; static int map_signal(RTLIL::SigSpec sig, char gate_type = -1, int in1 = -1, int in2 = -1, int in3 = -1) { - assert(sig.width == 1); - assert(sig.chunks.size() == 1); + assert(sig.__width == 1); + assert(sig.__chunks.size() == 1); assign_map.apply(sig); @@ -105,7 +105,7 @@ static void mark_port(RTLIL::SigSpec sig) { assign_map.apply(sig); sig.expand(); - for (auto &c : sig.chunks) { + for (auto &c : sig.__chunks) { if (c.wire != NULL && signal_map.count(c) > 0) signal_list[signal_map[c]].is_port = true; } @@ -124,7 +124,7 @@ static void extract_cell(RTLIL::Cell *cell, bool keepff) RTLIL::SigSpec sig_q = cell->connections["\\Q"]; if (keepff) - for (auto &c : sig_q.chunks) + for (auto &c : sig_q.__chunks) if (c.wire != NULL) c.wire->attributes["\\keep"] = 1; @@ -300,8 +300,8 @@ static void handle_loops() for (auto &edge_it : edges) { int id2 = edge_it.first; - RTLIL::Wire *w1 = signal_list[id1].sig.chunks[0].wire; - RTLIL::Wire *w2 = signal_list[id2].sig.chunks[0].wire; + RTLIL::Wire *w1 = signal_list[id1].sig.__chunks[0].wire; + RTLIL::Wire *w2 = signal_list[id2].sig.__chunks[0].wire; if (w1 != NULL) continue; else if (w2 == NULL) @@ -469,7 +469,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std clk_sig = assign_map(RTLIL::SigSpec(module->wires.at(RTLIL::escape_id(clk_str)), 1)); } - if (dff_mode && clk_sig.width == 0) + if (dff_mode && clk_sig.__width == 0) { int best_dff_counter = 0; std::map, int> dff_counters; @@ -490,13 +490,13 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std } if (dff_mode || !clk_str.empty()) { - if (clk_sig.width == 0) + if (clk_sig.__width == 0) log("No (matching) clock domain found. Not extracting any FF cells.\n"); else log("Found (matching) %s clock domain: %s\n", clk_polarity ? "posedge" : "negedge", log_signal(clk_sig)); } - if (clk_sig.width != 0) + if (clk_sig.__width != 0) mark_port(clk_sig); std::vector cells; @@ -552,10 +552,10 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std fprintf(f, "# n%-5d %s\n", si.id, log_signal(si.sig)); for (auto &si : signal_list) { - assert(si.sig.width == 1 && si.sig.chunks.size() == 1); - if (si.sig.chunks[0].wire == NULL) { + assert(si.sig.__width == 1 && si.sig.__chunks.size() == 1); + if (si.sig.__chunks[0].wire == NULL) { fprintf(f, ".names n%d\n", si.id); - if (si.sig.chunks[0].data.bits[0] == RTLIL::State::S1) + if (si.sig.__chunks[0].data.bits[0] == RTLIL::State::S1) fprintf(f, "1\n"); } } @@ -716,15 +716,15 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std cell_stats[RTLIL::unescape_id(c->type)]++; if (c->type == "\\ZERO" || c->type == "\\ONE") { RTLIL::SigSig conn; - conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].chunks[0].wire->name)]); + conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].__chunks[0].wire->name)]); conn.second = RTLIL::SigSpec(c->type == "\\ZERO" ? 0 : 1, 1); module->connections.push_back(conn); continue; } if (c->type == "\\BUF") { RTLIL::SigSig conn; - conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].chunks[0].wire->name)]); - conn.second = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].chunks[0].wire->name)]); + conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].__chunks[0].wire->name)]); + conn.second = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].__chunks[0].wire->name)]); module->connections.push_back(conn); continue; } @@ -732,8 +732,8 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std RTLIL::Cell *cell = new RTLIL::Cell; cell->type = "$_INV_"; cell->name = remap_name(c->name); - cell->connections["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].chunks[0].wire->name)]); - cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].chunks[0].wire->name)]); + cell->connections["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].__chunks[0].wire->name)]); + cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].__chunks[0].wire->name)]); module->cells[cell->name] = cell; design->select(module, cell); continue; @@ -742,9 +742,9 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std RTLIL::Cell *cell = new RTLIL::Cell; cell->type = "$_" + c->type.substr(1) + "_"; cell->name = remap_name(c->name); - cell->connections["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].chunks[0].wire->name)]); - cell->connections["\\B"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\B"].chunks[0].wire->name)]); - cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].chunks[0].wire->name)]); + cell->connections["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].__chunks[0].wire->name)]); + cell->connections["\\B"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\B"].__chunks[0].wire->name)]); + cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].__chunks[0].wire->name)]); module->cells[cell->name] = cell; design->select(module, cell); continue; @@ -753,21 +753,21 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std RTLIL::Cell *cell = new RTLIL::Cell; cell->type = "$_MUX_"; cell->name = remap_name(c->name); - cell->connections["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].chunks[0].wire->name)]); - cell->connections["\\B"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\B"].chunks[0].wire->name)]); - cell->connections["\\S"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\S"].chunks[0].wire->name)]); - cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].chunks[0].wire->name)]); + cell->connections["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].__chunks[0].wire->name)]); + cell->connections["\\B"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\B"].__chunks[0].wire->name)]); + cell->connections["\\S"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\S"].__chunks[0].wire->name)]); + cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].__chunks[0].wire->name)]); module->cells[cell->name] = cell; design->select(module, cell); continue; } if (c->type == "\\DFF") { - log_assert(clk_sig.width == 1); + log_assert(clk_sig.__width == 1); RTLIL::Cell *cell = new RTLIL::Cell; cell->type = clk_polarity ? "$_DFF_P_" : "$_DFF_N_"; cell->name = remap_name(c->name); - cell->connections["\\D"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\D"].chunks[0].wire->name)]); - cell->connections["\\Q"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Q"].chunks[0].wire->name)]); + cell->connections["\\D"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\D"].__chunks[0].wire->name)]); + cell->connections["\\Q"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Q"].__chunks[0].wire->name)]); cell->connections["\\C"] = clk_sig; module->cells[cell->name] = cell; design->select(module, cell); @@ -784,18 +784,18 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std cell_stats[RTLIL::unescape_id(c->type)]++; if (c->type == "\\_const0_" || c->type == "\\_const1_") { RTLIL::SigSig conn; - conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections.begin()->second.chunks[0].wire->name)]); + conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections.begin()->second.__chunks[0].wire->name)]); conn.second = RTLIL::SigSpec(c->type == "\\_const0_" ? 0 : 1, 1); module->connections.push_back(conn); continue; } if (c->type == "\\_dff_") { - log_assert(clk_sig.width == 1); + log_assert(clk_sig.__width == 1); RTLIL::Cell *cell = new RTLIL::Cell; cell->type = clk_polarity ? "$_DFF_P_" : "$_DFF_N_"; cell->name = remap_name(c->name); - cell->connections["\\D"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\D"].chunks[0].wire->name)]); - cell->connections["\\Q"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Q"].chunks[0].wire->name)]); + cell->connections["\\D"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\D"].__chunks[0].wire->name)]); + cell->connections["\\Q"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Q"].__chunks[0].wire->name)]); cell->connections["\\C"] = clk_sig; module->cells[cell->name] = cell; design->select(module, cell); @@ -807,7 +807,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std cell->name = remap_name(c->name); for (auto &conn : c->connections) { RTLIL::SigSpec newsig; - for (auto &c : conn.second.chunks) { + for (auto &c : conn.second.__chunks) { if (c.width == 0) continue; assert(c.width == 1); @@ -822,9 +822,9 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std for (auto conn : mapped_mod->connections) { if (!conn.first.is_fully_const()) - conn.first = RTLIL::SigSpec(module->wires[remap_name(conn.first.chunks[0].wire->name)]); + conn.first = RTLIL::SigSpec(module->wires[remap_name(conn.first.__chunks[0].wire->name)]); if (!conn.second.is_fully_const()) - conn.second = RTLIL::SigSpec(module->wires[remap_name(conn.second.chunks[0].wire->name)]); + conn.second = RTLIL::SigSpec(module->wires[remap_name(conn.second.__chunks[0].wire->name)]); module->connections.push_back(conn); } diff --git a/passes/abc/blifparse.cc b/passes/abc/blifparse.cc index 1d4da19ad..65ebe541d 100644 --- a/passes/abc/blifparse.cc +++ b/passes/abc/blifparse.cc @@ -177,10 +177,10 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name) } input_sig.append(wire); } - output_sig = input_sig.extract(input_sig.width-1, 1); - input_sig = input_sig.extract(0, input_sig.width-1); + output_sig = input_sig.extract(input_sig.__width-1, 1); + input_sig = input_sig.extract(0, input_sig.__width-1); - if (input_sig.width == 0) { + if (input_sig.__width == 0) { RTLIL::State state = RTLIL::State::Sa; while (1) { if (!read_next_line(buffer, buffer_size, line_count, f)) @@ -218,8 +218,8 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name) RTLIL::Cell *cell = new RTLIL::Cell; cell->name = NEW_ID; cell->type = "$lut"; - cell->parameters["\\WIDTH"] = RTLIL::Const(input_sig.width); - cell->parameters["\\LUT"] = RTLIL::Const(RTLIL::State::Sx, 1 << input_sig.width); + cell->parameters["\\WIDTH"] = RTLIL::Const(input_sig.__width); + cell->parameters["\\LUT"] = RTLIL::Const(RTLIL::State::Sx, 1 << input_sig.__width); cell->connections["\\I"] = input_sig; cell->connections["\\O"] = output_sig; lutptr = &cell->parameters.at("\\LUT"); diff --git a/passes/cmds/connect.cc b/passes/cmds/connect.cc index f99cb9b50..f8f9e0590 100644 --- a/passes/cmds/connect.cc +++ b/passes/cmds/connect.cc @@ -27,7 +27,7 @@ static void unset_drivers(RTLIL::Design *design, RTLIL::Module *module, SigMap & { CellTypes ct(design); - RTLIL::Wire *dummy_wire = module->addWire(NEW_ID, sig.width); + RTLIL::Wire *dummy_wire = module->addWire(NEW_ID, sig.__width); for (auto &it : module->cells) for (auto &port : it.second->connections) diff --git a/passes/cmds/connwrappers.cc b/passes/cmds/connwrappers.cc index dd8b4fede..426d2b624 100644 --- a/passes/cmds/connwrappers.cc +++ b/passes/cmds/connwrappers.cc @@ -90,7 +90,7 @@ struct ConnwrappersWorker continue; int inner_width = cell->parameters.at(decl.widthparam).as_int(); - int outer_width = conn.second.width; + int outer_width = conn.second.__width; bool is_signed = decl.signparam.empty() ? decl.is_signed : cell->parameters.at(decl.signparam).as_bool(); if (inner_width >= outer_width) @@ -124,20 +124,20 @@ struct ConnwrappersWorker int extend_width = 0; RTLIL::SigBit extend_bit = is_signed ? sigbits[i] : RTLIL::SigBit(RTLIL::State::S0); - while (extend_width < extend_sig.width && i + extend_width + 1 < sigbits.size() && + while (extend_width < extend_sig.__width && i + extend_width + 1 < sigbits.size() && sigbits[i + extend_width + 1] == extend_bit) extend_width++; if (extend_width == 0) continue; - if (old_sig.width == 0) + if (old_sig.__width == 0) old_sig = conn.second; conn.second.replace(i+1, extend_sig.extract(0, extend_width)); i += extend_width; } - if (old_sig.width) + if (old_sig.__width) log("Connected extended bits of %s.%s:%s: %s -> %s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(conn.first), log_signal(old_sig), log_signal(conn.second)); } diff --git a/passes/cmds/delete.cc b/passes/cmds/delete.cc index ce6ac4aff..16828e4fb 100644 --- a/passes/cmds/delete.cc +++ b/passes/cmds/delete.cc @@ -28,7 +28,7 @@ struct DeleteWireWorker void operator()(RTLIL::SigSpec &sig) { sig.optimize(); - for (auto &c : sig.chunks) + for (auto &c : sig.__chunks) if (c.wire != NULL && delete_wires_p->count(c.wire->name)) { c.wire = module->addWire(NEW_ID, c.width); c.offset = 0; diff --git a/passes/cmds/scatter.cc b/passes/cmds/scatter.cc index e5f78830e..da36c7821 100644 --- a/passes/cmds/scatter.cc +++ b/passes/cmds/scatter.cc @@ -53,7 +53,7 @@ struct ScatterPass : public Pass { { RTLIL::Wire *wire = new RTLIL::Wire; wire->name = NEW_ID; - wire->width = p.second.width; + wire->width = p.second.__width; mod_it.second->add(wire); if (ct.cell_output(c.second->type, p.first)) { diff --git a/passes/cmds/scc.cc b/passes/cmds/scc.cc index f8c351a43..d668bc3a4 100644 --- a/passes/cmds/scc.cc +++ b/passes/cmds/scc.cc @@ -191,7 +191,7 @@ struct SccWorker nextsig.sort_and_unify(); sig = prevsig.extract(nextsig); - for (auto &chunk : sig.chunks) + for (auto &chunk : sig.__chunks) if (chunk.wire != NULL) sel.selected_members[module->name].insert(chunk.wire->name); } diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index 9ef60a28f..068162eb1 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -415,7 +415,7 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v include_match: is_input = mode == 'x' || ct.cell_input(cell.second->type, conn.first); is_output = mode == 'x' || ct.cell_output(cell.second->type, conn.first); - for (auto &chunk : conn.second.chunks) + for (auto &chunk : conn.second.__chunks) if (chunk.wire != NULL) { if (max_objects != 0 && selected_wires.count(chunk.wire) > 0 && lhs.selected_members[mod->name].count(cell.first) == 0) if (mode == 'x' || (mode == 'i' && is_output) || (mode == 'o' && is_input)) diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index 9d59834c2..3a99c0cec 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -48,7 +48,7 @@ struct SetundefWorker void operator()(RTLIL::SigSpec &sig) { sig.expand(); - for (auto &c : sig.chunks) + for (auto &c : sig.__chunks) if (c.wire == NULL && c.data.bits.at(0) > RTLIL::State::S1) c.data.bits.at(0) = next_bit(); sig.optimize(); @@ -141,7 +141,7 @@ struct SetundefPass : public Pass { undriven_signals.del(sigmap(conn.second)); RTLIL::SigSpec sig = undriven_signals.export_all(); - for (auto &c : sig.chunks) { + for (auto &c : sig.__chunks) { RTLIL::SigSpec bits; for (int i = 0; i < c.width; i++) bits.append(next_bit()); diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index eab42e6ff..0006a3ff4 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -78,7 +78,7 @@ struct ShowWorker std::string nextColor(RTLIL::SigSpec sig, std::string defaultColor) { sig.sort_and_unify(); - for (auto &c : sig.chunks) { + for (auto &c : sig.__chunks) { if (c.wire != NULL) for (auto &s : color_selections) if (s.second.selected_members.count(module->name) > 0 && s.second.selected_members.at(module->name).count(c.wire->name) > 0) @@ -173,13 +173,13 @@ struct ShowWorker { sig.optimize(); - if (sig.chunks.size() == 0) { + if (sig.__chunks.size() == 0) { fprintf(f, "v%d [ label=\"\" ];\n", single_idx_count); return stringf("v%d", single_idx_count++); } - if (sig.chunks.size() == 1) { - RTLIL::SigChunk &c = sig.chunks[0]; + if (sig.__chunks.size() == 1) { + RTLIL::SigChunk &c = sig.__chunks[0]; if (c.wire != NULL && design->selected_member(module->name, c.wire->name)) { if (!range_check || c.wire->width == c.width) return stringf("n%d", id2num(c.wire->name)); @@ -200,10 +200,10 @@ struct ShowWorker { std::string label_string; sig.optimize(); - int pos = sig.width-1; + int pos = sig.__width-1; int idx = single_idx_count++; - for (int i = int(sig.chunks.size())-1; i >= 0; i--) { - RTLIL::SigChunk &c = sig.chunks[i]; + for (int i = int(sig.__chunks.size())-1; i >= 0; i--) { + RTLIL::SigChunk &c = sig.__chunks[i]; net = gen_signode_simple(c, false); assert(!net.empty()); if (driver) { @@ -225,9 +225,9 @@ struct ShowWorker if (!port.empty()) { currentColor = xorshift32(currentColor); if (driver) - code += stringf("%s:e -> x%d:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, %s, %s];\n", port.c_str(), idx, nextColor(sig).c_str(), widthLabel(sig.width).c_str()); + code += stringf("%s:e -> x%d:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, %s, %s];\n", port.c_str(), idx, nextColor(sig).c_str(), widthLabel(sig.__width).c_str()); else - code += stringf("x%d:e -> %s:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, %s, %s];\n", idx, port.c_str(), nextColor(sig).c_str(), widthLabel(sig.width).c_str()); + code += stringf("x%d:e -> %s:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, %s, %s];\n", idx, port.c_str(), nextColor(sig).c_str(), widthLabel(sig.__width).c_str()); } if (node != NULL) *node = stringf("x%d", idx); @@ -239,7 +239,7 @@ struct ShowWorker net_conn_map[net].in.insert(port); else net_conn_map[net].out.insert(port); - net_conn_map[net].bits = sig.width; + net_conn_map[net].bits = sig.__width; net_conn_map[net].color = nextColor(sig, net_conn_map[net].color); } if (node != NULL) @@ -405,7 +405,7 @@ struct ShowWorker code += gen_portbox("", sig, false, &node); fprintf(f, "%s", code.c_str()); net_conn_map[node].out.insert(stringf("p%d", pidx)); - net_conn_map[node].bits = sig.width; + net_conn_map[node].bits = sig.__width; net_conn_map[node].color = nextColor(sig, net_conn_map[node].color); } @@ -414,7 +414,7 @@ struct ShowWorker code += gen_portbox("", sig, true, &node); fprintf(f, "%s", code.c_str()); net_conn_map[node].in.insert(stringf("p%d", pidx)); - net_conn_map[node].bits = sig.width; + net_conn_map[node].bits = sig.__width; net_conn_map[node].color = nextColor(sig, net_conn_map[node].color); } @@ -427,12 +427,12 @@ struct ShowWorker for (auto &conn : module->connections) { bool found_lhs_wire = false; - for (auto &c : conn.first.chunks) { + for (auto &c : conn.first.__chunks) { if (c.wire == NULL || design->selected_member(module->name, c.wire->name)) found_lhs_wire = true; } bool found_rhs_wire = false; - for (auto &c : conn.second.chunks) { + for (auto &c : conn.second.__chunks) { if (c.wire == NULL || design->selected_member(module->name, c.wire->name)) found_rhs_wire = true; } @@ -446,11 +446,11 @@ struct ShowWorker if (left_node[0] == 'x' && right_node[0] == 'x') { currentColor = xorshift32(currentColor); - fprintf(f, "%s:e -> %s:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, %s, %s];\n", left_node.c_str(), right_node.c_str(), nextColor(conn).c_str(), widthLabel(conn.first.width).c_str()); + fprintf(f, "%s:e -> %s:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, %s, %s];\n", left_node.c_str(), right_node.c_str(), nextColor(conn).c_str(), widthLabel(conn.first.__width).c_str()); } else { - net_conn_map[right_node].bits = conn.first.width; + net_conn_map[right_node].bits = conn.first.__width; net_conn_map[right_node].color = nextColor(conn, net_conn_map[right_node].color); - net_conn_map[left_node].bits = conn.first.width; + net_conn_map[left_node].bits = conn.first.__width; net_conn_map[left_node].color = nextColor(conn, net_conn_map[left_node].color); if (left_node[0] == 'x') { net_conn_map[right_node].in.insert(left_node); diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc index a48a54a12..80a7f90c0 100644 --- a/passes/cmds/splice.cc +++ b/passes/cmds/splice.cc @@ -52,7 +52,7 @@ struct SpliceWorker RTLIL::SigSpec get_sliced_signal(RTLIL::SigSpec sig) { - if (sig.width == 0 || sig.is_fully_const()) + if (sig.__width == 0 || sig.is_fully_const()) return sig; if (sliced_signals_cache.count(sig)) @@ -69,15 +69,15 @@ struct SpliceWorker RTLIL::SigSpec new_sig = sig; - if (sig_a.width != sig.width) { + if (sig_a.__width != sig.__width) { RTLIL::Cell *cell = new RTLIL::Cell; cell->name = NEW_ID; cell->type = "$slice"; cell->parameters["\\OFFSET"] = offset; - cell->parameters["\\A_WIDTH"] = sig_a.width; - cell->parameters["\\Y_WIDTH"] = sig.width; + cell->parameters["\\A_WIDTH"] = sig_a.__width; + cell->parameters["\\Y_WIDTH"] = sig.__width; cell->connections["\\A"] = sig_a; - cell->connections["\\Y"] = module->addWire(NEW_ID, sig.width); + cell->connections["\\Y"] = module->addWire(NEW_ID, sig.__width); new_sig = cell->connections["\\Y"]; module->add(cell); } @@ -90,7 +90,7 @@ struct SpliceWorker RTLIL::SigSpec get_spliced_signal(RTLIL::SigSpec sig) { - if (sig.width == 0 || sig.is_fully_const()) + if (sig.__width == 0 || sig.is_fully_const()) return sig; if (spliced_signals_cache.count(sig)) @@ -134,11 +134,11 @@ struct SpliceWorker RTLIL::Cell *cell = new RTLIL::Cell; cell->name = NEW_ID; cell->type = "$concat"; - cell->parameters["\\A_WIDTH"] = new_sig.width; - cell->parameters["\\B_WIDTH"] = sig2.width; + cell->parameters["\\A_WIDTH"] = new_sig.__width; + cell->parameters["\\B_WIDTH"] = sig2.__width; cell->connections["\\A"] = new_sig; cell->connections["\\B"] = sig2; - cell->connections["\\Y"] = module->addWire(NEW_ID, new_sig.width + sig2.width); + cell->connections["\\Y"] = module->addWire(NEW_ID, new_sig.__width + sig2.__width); new_sig = cell->connections["\\Y"]; module->add(cell); } diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc index 7e043bcff..7572baa35 100644 --- a/passes/cmds/splitnets.cc +++ b/passes/cmds/splitnets.cc @@ -63,7 +63,7 @@ struct SplitnetsWorker void operator()(RTLIL::SigSpec &sig) { sig.expand(); - for (auto &c : sig.chunks) + for (auto &c : sig.__chunks) if (splitmap.count(c.wire) > 0) c = splitmap.at(c.wire).at(c.offset); sig.optimize(); @@ -144,7 +144,7 @@ struct SplitnetsPass : public Pass { continue; RTLIL::SigSpec sig = p.second.optimized(); - for (auto &chunk : sig.chunks) { + for (auto &chunk : sig.__chunks) { if (chunk.wire == NULL) continue; if (chunk.wire->port_id == 0 || flag_ports) { diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc index a8ec19126..523feae92 100644 --- a/passes/fsm/fsm_detect.cc +++ b/passes/fsm/fsm_detect.cc @@ -56,8 +56,8 @@ static bool check_state_mux_tree(RTLIL::SigSpec old_sig, RTLIL::SigSpec sig, Sig RTLIL::SigSpec sig_b = assign_map(cellport.first->connections["\\B"]); if (!check_state_mux_tree(old_sig, sig_a, recursion_monitor)) return false; - for (int i = 0; i < sig_b.width; i += sig_a.width) - if (!check_state_mux_tree(old_sig, sig_b.extract(i, sig_a.width), recursion_monitor)) + for (int i = 0; i < sig_b.__width; i += sig_a.__width) + if (!check_state_mux_tree(old_sig, sig_b.extract(i, sig_a.__width), recursion_monitor)) return false; muxtree_cells.insert(cellport.first); } diff --git a/passes/fsm/fsm_expand.cc b/passes/fsm/fsm_expand.cc index 5756b10c7..e4d20077c 100644 --- a/passes/fsm/fsm_expand.cc +++ b/passes/fsm/fsm_expand.cc @@ -43,7 +43,7 @@ struct FsmExpand bool is_cell_merge_candidate(RTLIL::Cell *cell) { if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux") - if (cell->connections.at("\\A").width < 2) + if (cell->connections.at("\\A").__width < 2) return true; RTLIL::SigSpec new_signals; @@ -62,7 +62,7 @@ struct FsmExpand new_signals.remove(assign_map(fsm_cell->connections["\\CTRL_IN"])); new_signals.remove(assign_map(fsm_cell->connections["\\CTRL_OUT"])); - if (new_signals.width > 3) + if (new_signals.__width > 3) return false; if (cell->connections.count("\\Y") > 0) { @@ -73,7 +73,7 @@ struct FsmExpand new_signals.remove(assign_map(fsm_cell->connections["\\CTRL_OUT"])); } - if (new_signals.width > 2) + if (new_signals.__width > 2) return false; return true; @@ -145,8 +145,8 @@ struct FsmExpand std::vector truth_tab; - for (int i = 0; i < (1 << input_sig.width); i++) { - RTLIL::Const in_val(i, input_sig.width); + for (int i = 0; i < (1 << input_sig.__width); i++) { + RTLIL::Const in_val(i, input_sig.__width); RTLIL::SigSpec A, B, S; if (cell->connections.count("\\A") > 0) A = assign_map(cell->connections["\\A"]); @@ -166,17 +166,17 @@ struct FsmExpand FsmData fsm_data; fsm_data.copy_from_cell(fsm_cell); - fsm_data.num_inputs += input_sig.width; + fsm_data.num_inputs += input_sig.__width; fsm_cell->connections["\\CTRL_IN"].append(input_sig); - fsm_data.num_outputs += output_sig.width; + fsm_data.num_outputs += output_sig.__width; fsm_cell->connections["\\CTRL_OUT"].append(output_sig); std::vector new_transition_table; for (auto &tr : fsm_data.transition_table) { - for (int i = 0; i < (1 << input_sig.width); i++) { + for (int i = 0; i < (1 << input_sig.__width); i++) { FsmData::transition_t new_tr = tr; - RTLIL::Const in_val(i, input_sig.width); + RTLIL::Const in_val(i, input_sig.__width); RTLIL::Const out_val = truth_tab[i]; RTLIL::SigSpec ctrl_in = new_tr.ctrl_in; RTLIL::SigSpec ctrl_out = new_tr.ctrl_out; diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index 9cba904a7..c0b5857f0 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -36,7 +36,7 @@ static SigSet sig2driver, sig2trigger; static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL::SigSpec &ctrl, std::map &states, RTLIL::Const *reset_state = NULL) { - sig.extend(dff_out.width, false); + sig.extend(dff_out.__width, false); if (sig == dff_out) return true; @@ -44,10 +44,10 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL assign_map.apply(sig); if (sig.is_fully_const()) { sig.optimize(); - assert(sig.chunks.size() == 1); - if (states.count(sig.chunks[0].data) == 0) { + assert(sig.__chunks.size() == 1); + if (states.count(sig.__chunks[0].data) == 0) { log(" found state code: %s\n", log_signal(sig)); - states[sig.chunks[0].data] = -1; + states[sig.__chunks[0].data] = -1; } return true; } @@ -73,14 +73,14 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL break; log(" found reset state: %s (guessed from mux tree)\n", log_signal(*reset_state)); } while (0); - if (ctrl.extract(sig_s).width == 0) { + if (ctrl.extract(sig_s).__width == 0) { log(" found ctrl input: %s\n", log_signal(sig_s)); ctrl.append(sig_s); } if (!find_states(sig_a, dff_out, ctrl, states)) return false; - for (int i = 0; i < sig_b.width/sig_a.width; i++) { - if (!find_states(sig_b.extract(i*sig_a.width, sig_a.width), dff_out, ctrl, states)) + for (int i = 0; i < sig_b.__width/sig_a.__width; i++) { + if (!find_states(sig_b.extract(i*sig_a.__width, sig_a.__width), dff_out, ctrl, states)) return false; } } @@ -90,11 +90,11 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL static RTLIL::Const sig2const(ConstEval &ce, RTLIL::SigSpec sig, RTLIL::State noconst_state, RTLIL::SigSpec dont_care = RTLIL::SigSpec()) { - if (dont_care.width > 0) { + if (dont_care.__width > 0) { sig.expand(); - for (auto &chunk : sig.chunks) { + for (auto &chunk : sig.__chunks) { assert(chunk.width == 1); - if (dont_care.extract(chunk).width > 0) + if (dont_care.extract(chunk).__width > 0) chunk.wire = NULL, chunk.data = RTLIL::Const(noconst_state); } sig.optimize(); @@ -104,17 +104,17 @@ static RTLIL::Const sig2const(ConstEval &ce, RTLIL::SigSpec sig, RTLIL::State no ce.values_map.apply(sig); sig.expand(); - for (auto &chunk : sig.chunks) { + for (auto &chunk : sig.__chunks) { assert(chunk.width == 1); if (chunk.wire != NULL) chunk.wire = NULL, chunk.data = RTLIL::Const(noconst_state); } sig.optimize(); - if (sig.width == 0) + if (sig.__width == 0) return RTLIL::Const(); - assert(sig.chunks.size() == 1 && sig.chunks[0].wire == NULL); - return sig.chunks[0].data; + assert(sig.__chunks.size() == 1 && sig.__chunks[0].wire == NULL); + return sig.__chunks[0].data; } static void find_transitions(ConstEval &ce, ConstEval &ce_nostop, FsmData &fsm_data, std::map &states, int state_in, RTLIL::SigSpec ctrl_in, RTLIL::SigSpec ctrl_out, RTLIL::SigSpec dff_in, RTLIL::SigSpec dont_care) @@ -144,7 +144,7 @@ static void find_transitions(ConstEval &ce, ConstEval &ce_nostop, FsmData &fsm_d return; } - log_assert(undef.width > 0); + log_assert(undef.__width > 0); log_assert(ce.stop_signals.check_all(undef)); undef = undef.extract(0, 1); @@ -258,8 +258,8 @@ static void extract_fsm(RTLIL::Wire *wire) // Initialize fsm data struct FsmData fsm_data; - fsm_data.num_inputs = ctrl_in.width; - fsm_data.num_outputs = ctrl_out.width; + fsm_data.num_inputs = ctrl_in.__width; + fsm_data.num_outputs = ctrl_out.__width; fsm_data.state_bits = wire->width; fsm_data.reset_state = -1; for (auto &it : states) { @@ -314,7 +314,7 @@ static void extract_fsm(RTLIL::Wire *wire) RTLIL::SigSpec unconn_sig = port_sig.extract(ctrl_out); RTLIL::Wire *unconn_wire = new RTLIL::Wire; unconn_wire->name = stringf("$fsm_unconnect$%s$%d", log_signal(unconn_sig), RTLIL::autoidx++); - unconn_wire->width = unconn_sig.width; + unconn_wire->width = unconn_sig.__width; module->wires[unconn_wire->name] = unconn_wire; port_sig.replace(unconn_sig, RTLIL::SigSpec(unconn_wire), &cell->connections[cellport.second]); } @@ -367,7 +367,7 @@ struct FsmExtractPass : public Pass { sig2driver.insert(sig, sig2driver_entry_t(cell_it.first, conn_it.first)); } if (ct.cell_input(cell_it.second->type, conn_it.first) && cell_it.second->connections.count("\\Y") > 0 && - cell_it.second->connections["\\Y"].width == 1 && (conn_it.first == "\\A" || conn_it.first == "\\B")) { + cell_it.second->connections["\\Y"].__width == 1 && (conn_it.first == "\\A" || conn_it.first == "\\B")) { RTLIL::SigSpec sig = conn_it.second; assign_map.apply(sig); sig2trigger.insert(sig, sig2driver_entry_t(cell_it.first, conn_it.first)); diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc index c30cf1fe7..f11d78b39 100644 --- a/passes/fsm/fsm_map.cc +++ b/passes/fsm/fsm_map.cc @@ -50,12 +50,12 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map 0) + if (eq_sig_a.__width > 0) { RTLIL::Wire *eq_wire = new RTLIL::Wire; eq_wire->name = NEW_ID; @@ -69,17 +69,17 @@ static void implement_pattern_cache(RTLIL::Module *module, std::mapconnections["\\Y"] = RTLIL::SigSpec(eq_wire); eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false); eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false); - eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(eq_sig_a.width); - eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(eq_sig_b.width); + eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(eq_sig_a.__width); + eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(eq_sig_b.__width); eq_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); module->add(eq_cell); and_sig.append(RTLIL::SigSpec(eq_wire)); } - if (or_sig.width < num_states-int(fullstate_cache.size())) + if (or_sig.__width < num_states-int(fullstate_cache.size())) { - if (or_sig.width == 1) + if (or_sig.__width == 1) { and_sig.append(or_sig); } @@ -95,7 +95,7 @@ static void implement_pattern_cache(RTLIL::Module *module, std::mapconnections["\\A"] = or_sig; or_cell->connections["\\Y"] = RTLIL::SigSpec(or_wire); or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false); - or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(or_sig.width); + or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(or_sig.__width); or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); module->add(or_cell); @@ -103,7 +103,7 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map 1) { + if (cases_vector.__width > 1) { RTLIL::Cell *or_cell = new RTLIL::Cell; or_cell->name = NEW_ID; or_cell->type = "$reduce_or"; or_cell->connections["\\A"] = cases_vector; or_cell->connections["\\Y"] = output; or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false); - or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cases_vector.width); + or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cases_vector.__width); or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); module->add(or_cell); - } else if (cases_vector.width == 1) { + } else if (cases_vector.__width == 1) { module->connections.push_back(RTLIL::SigSig(output, cases_vector)); } else { module->connections.push_back(RTLIL::SigSig(output, RTLIL::SigSpec(0, 1))); @@ -237,8 +237,8 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) eq_cell->connections["\\Y"] = RTLIL::SigSpec(state_onehot, 1, i); eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false); eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false); - eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_a.width); - eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(sig_b.width); + eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_a.__width); + eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(sig_b.__width); eq_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); module->add(eq_cell); } @@ -308,8 +308,8 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) mux_cell->connections["\\B"] = sig_b; mux_cell->connections["\\S"] = sig_s; mux_cell->connections["\\Y"] = RTLIL::SigSpec(next_state_wire); - mux_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_a.width); - mux_cell->parameters["\\S_WIDTH"] = RTLIL::Const(sig_s.width); + mux_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_a.__width); + mux_cell->parameters["\\S_WIDTH"] = RTLIL::Const(sig_s.__width); module->add(mux_cell); } diff --git a/passes/fsm/fsm_opt.cc b/passes/fsm/fsm_opt.cc index 242a505e9..6732d2abd 100644 --- a/passes/fsm/fsm_opt.cc +++ b/passes/fsm/fsm_opt.cc @@ -33,11 +33,11 @@ struct FsmOpt bool signal_is_unused(RTLIL::SigSpec sig) { - assert(sig.width == 1); + assert(sig.__width == 1); sig.optimize(); - RTLIL::Wire *wire = sig.chunks[0].wire; - int bit = sig.chunks[0].offset; + RTLIL::Wire *wire = sig.__chunks[0].wire; + int bit = sig.__chunks[0].offset; if (!wire || wire->attributes.count("\\unused_bits") == 0) return false; @@ -55,11 +55,11 @@ struct FsmOpt void opt_const_and_unused_inputs() { RTLIL::SigSpec ctrl_in = cell->connections["\\CTRL_IN"]; - std::vector ctrl_in_used(ctrl_in.width); + std::vector ctrl_in_used(ctrl_in.__width); std::vector new_transition_table; for (auto &tr : fsm_data.transition_table) { - for (int i = 0; i < ctrl_in.width; i++) { + for (int i = 0; i < ctrl_in.__width; i++) { RTLIL::SigSpec ctrl_bit = ctrl_in.extract(i, 1); if (ctrl_bit.is_fully_const()) { if (tr.ctrl_in.bits[i] <= RTLIL::State::S1 && RTLIL::SigSpec(tr.ctrl_in.bits[i]) != ctrl_bit) @@ -112,8 +112,8 @@ struct FsmOpt { RTLIL::SigSpec &ctrl_in = cell->connections["\\CTRL_IN"]; - for (int i = 0; i < ctrl_in.width; i++) - for (int j = i+1; j < ctrl_in.width; j++) + for (int i = 0; i < ctrl_in.__width; i++) + for (int j = i+1; j < ctrl_in.__width; j++) if (ctrl_in.extract(i, 1) == ctrl_in.extract(j, 1)) { log(" Optimize handling of signal %s that is connected to inputs %d and %d.\n", log_signal(ctrl_in.extract(i, 1)), i, j); @@ -150,8 +150,8 @@ struct FsmOpt RTLIL::SigSpec &ctrl_in = cell->connections["\\CTRL_IN"]; RTLIL::SigSpec &ctrl_out = cell->connections["\\CTRL_OUT"]; - for (int j = 0; j < ctrl_out.width; j++) - for (int i = 0; i < ctrl_in.width; i++) + for (int j = 0; j < ctrl_out.__width; j++) + for (int i = 0; i < ctrl_in.__width; i++) if (ctrl_in.extract(i, 1) == ctrl_out.extract(j, 1)) { log(" Optimize handling of signal %s that is connected to input %d and output %d.\n", log_signal(ctrl_in.extract(i, 1)), i, j); diff --git a/passes/fsm/fsmdata.h b/passes/fsm/fsmdata.h index 225f34a9d..6b1753060 100644 --- a/passes/fsm/fsmdata.h +++ b/passes/fsm/fsmdata.h @@ -143,15 +143,15 @@ struct FsmData log(" Input signals:\n"); RTLIL::SigSpec sig_in = cell->connections["\\CTRL_IN"]; sig_in.expand(); - for (size_t i = 0; i < sig_in.chunks.size(); i++) - log(" %3zd: %s\n", i, log_signal(sig_in.chunks[i])); + for (size_t i = 0; i < sig_in.__chunks.size(); i++) + log(" %3zd: %s\n", i, log_signal(sig_in.__chunks[i])); log("\n"); log(" Output signals:\n"); RTLIL::SigSpec sig_out = cell->connections["\\CTRL_OUT"]; sig_out.expand(); - for (size_t i = 0; i < sig_out.chunks.size(); i++) - log(" %3zd: %s\n", i, log_signal(sig_out.chunks[i])); + for (size_t i = 0; i < sig_out.__chunks.size(); i++) + log(" %3zd: %s\n", i, log_signal(sig_out.__chunks[i])); log("\n"); log(" State encoding:\n"); diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index d8a23c727..5d9dc18a4 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -61,7 +61,7 @@ static void generate(RTLIL::Design *design, const std::vector &cell for (auto &conn : i2.second->connections) { if (conn.first[0] != '$') portnames.insert(conn.first); - portwidths[conn.first] = std::max(portwidths[conn.first], conn.second.width); + portwidths[conn.first] = std::max(portwidths[conn.first], conn.second.__width); } for (auto ¶ : i2.second->parameters) parameters.insert(para.first); @@ -220,7 +220,7 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla RTLIL::Module *mod = design->modules[cell->type]; for (auto &conn : cell->connections) { - int conn_size = conn.second.width; + int conn_size = conn.second.__width; std::string portname = conn.first; if (portname.substr(0, 1) == "$") { int port_id = atoi(portname.substr(1).c_str()); diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index 55f5f0485..f8f2b596b 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -67,7 +67,7 @@ struct SubmodWorker void flag_signal(RTLIL::SigSpec &sig, bool create, bool set_int_driven, bool set_int_used, bool set_ext_driven, bool set_ext_used) { - for (auto &c : sig.chunks) + for (auto &c : sig.__chunks) if (c.wire != NULL) flag_wire(c.wire, create, set_int_driven, set_int_used, set_ext_driven, set_ext_used); } @@ -164,7 +164,7 @@ struct SubmodWorker for (RTLIL::Cell *cell : submod.cells) { RTLIL::Cell *new_cell = new RTLIL::Cell(*cell); for (auto &conn : new_cell->connections) - for (auto &c : conn.second.chunks) + for (auto &c : conn.second.__chunks) if (c.wire != NULL) { assert(wire_flags.count(c.wire) > 0); c.wire = wire_flags[c.wire].new_wire; diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc index 028841f60..6c9e1b773 100644 --- a/passes/memory/memory_collect.cc +++ b/passes/memory/memory_collect.cc @@ -142,16 +142,16 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) sig_wr_clk_enable.optimize(); sig_wr_clk_polarity.optimize(); - assert(sig_wr_clk.width == wr_ports); - assert(sig_wr_clk_enable.width == wr_ports && sig_wr_clk_enable.is_fully_const()); - assert(sig_wr_clk_polarity.width == wr_ports && sig_wr_clk_polarity.is_fully_const()); - assert(sig_wr_addr.width == wr_ports * addr_bits); - assert(sig_wr_data.width == wr_ports * memory->width); - assert(sig_wr_en.width == wr_ports * memory->width); + assert(sig_wr_clk.__width == wr_ports); + assert(sig_wr_clk_enable.__width == wr_ports && sig_wr_clk_enable.is_fully_const()); + assert(sig_wr_clk_polarity.__width == wr_ports && sig_wr_clk_polarity.is_fully_const()); + assert(sig_wr_addr.__width == wr_ports * addr_bits); + assert(sig_wr_data.__width == wr_ports * memory->width); + assert(sig_wr_en.__width == wr_ports * memory->width); mem->parameters["\\WR_PORTS"] = RTLIL::Const(wr_ports); - mem->parameters["\\WR_CLK_ENABLE"] = wr_ports ? sig_wr_clk_enable.chunks[0].data : RTLIL::Const(0, 0); - mem->parameters["\\WR_CLK_POLARITY"] = wr_ports ? sig_wr_clk_polarity.chunks[0].data : RTLIL::Const(0, 0); + mem->parameters["\\WR_CLK_ENABLE"] = wr_ports ? sig_wr_clk_enable.__chunks[0].data : RTLIL::Const(0, 0); + mem->parameters["\\WR_CLK_POLARITY"] = wr_ports ? sig_wr_clk_polarity.__chunks[0].data : RTLIL::Const(0, 0); mem->connections["\\WR_CLK"] = sig_wr_clk; mem->connections["\\WR_ADDR"] = sig_wr_addr; @@ -162,16 +162,16 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) sig_rd_clk_polarity.optimize(); sig_rd_transparent.optimize(); - assert(sig_rd_clk.width == rd_ports); - assert(sig_rd_clk_enable.width == rd_ports && sig_rd_clk_enable.is_fully_const()); - assert(sig_rd_clk_polarity.width == rd_ports && sig_rd_clk_polarity.is_fully_const()); - assert(sig_rd_addr.width == rd_ports * addr_bits); - assert(sig_rd_data.width == rd_ports * memory->width); + assert(sig_rd_clk.__width == rd_ports); + assert(sig_rd_clk_enable.__width == rd_ports && sig_rd_clk_enable.is_fully_const()); + assert(sig_rd_clk_polarity.__width == rd_ports && sig_rd_clk_polarity.is_fully_const()); + assert(sig_rd_addr.__width == rd_ports * addr_bits); + assert(sig_rd_data.__width == rd_ports * memory->width); mem->parameters["\\RD_PORTS"] = RTLIL::Const(rd_ports); - mem->parameters["\\RD_CLK_ENABLE"] = rd_ports ? sig_rd_clk_enable.chunks[0].data : RTLIL::Const(0, 0); - mem->parameters["\\RD_CLK_POLARITY"] = rd_ports ? sig_rd_clk_polarity.chunks[0].data : RTLIL::Const(0, 0); - mem->parameters["\\RD_TRANSPARENT"] = rd_ports ? sig_rd_transparent.chunks[0].data : RTLIL::Const(0, 0); + mem->parameters["\\RD_CLK_ENABLE"] = rd_ports ? sig_rd_clk_enable.__chunks[0].data : RTLIL::Const(0, 0); + mem->parameters["\\RD_CLK_POLARITY"] = rd_ports ? sig_rd_clk_polarity.__chunks[0].data : RTLIL::Const(0, 0); + mem->parameters["\\RD_TRANSPARENT"] = rd_ports ? sig_rd_transparent.__chunks[0].data : RTLIL::Const(0, 0); mem->connections["\\RD_CLK"] = sig_rd_clk; mem->connections["\\RD_ADDR"] = sig_rd_addr; diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index e8da6d642..174417bd6 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -34,9 +34,9 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI normalize_sig(module, sig); sig.expand(); - for (size_t i = 0; i < sig.chunks.size(); i++) + for (size_t i = 0; i < sig.__chunks.size(); i++) { - RTLIL::SigChunk &chunk = sig.chunks[i]; + RTLIL::SigChunk &chunk = sig.__chunks[i]; if (chunk.wire == NULL) continue; @@ -59,11 +59,11 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI normalize_sig(module, q_norm); RTLIL::SigSpec d = q_norm.extract(chunk, &cell->connections[after ? "\\Q" : "\\D"]); - if (d.width != 1) + if (d.__width != 1) continue; - assert(d.chunks.size() == 1); - chunk = d.chunks[0]; + assert(d.__chunks.size() == 1); + chunk = d.__chunks[0]; clk = cell->connections["\\CLK"]; clk_polarity = cell->parameters["\\CLK_POLARITY"].as_bool(); goto replaced_this_bit; @@ -125,7 +125,7 @@ static void disconnect_dff(RTLIL::Module *module, RTLIL::SigSpec sig) RTLIL::Wire *wire = new RTLIL::Wire; wire->name = sstr.str(); - wire->width = sig.width; + wire->width = sig.__width; module->wires[wire->name] = wire; RTLIL::SigSpec newsig(wire); diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index 10ab6e2f4..b848e09e4 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -68,7 +68,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::Const clocks_en = cell->parameters["\\WR_CLK_ENABLE"]; RTLIL::SigSpec refclock; RTLIL::State refclock_pol = RTLIL::State::Sx; - for (int i = 0; i < clocks.width; i++) { + for (int i = 0; i < clocks.__width; i++) { RTLIL::SigSpec wr_en = cell->connections["\\WR_EN"].extract(i * mem_width, mem_width); if (wr_en.is_fully_const() && !wr_en.as_bool()) { static_ports.insert(i); @@ -89,7 +89,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) cell->name.c_str(), module->name.c_str(), i); return; } - if (refclock.width == 0) { + if (refclock.__width == 0) { refclock = clocks.extract(i, 1); refclock_pol = clocks_pol.bits[i]; } @@ -277,12 +277,12 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) c->connections["\\Y"] = w_seladdr; int wr_offset = 0; - while (wr_offset < wr_en.width) + while (wr_offset < wr_en.__width) { int wr_width = 1; RTLIL::SigSpec wr_bit = wr_en.extract(wr_offset, 1); - while (wr_offset + wr_width < wr_en.width) { + while (wr_offset + wr_width < wr_en.__width) { RTLIL::SigSpec next_wr_bit = wr_en.extract(wr_offset + wr_width, 1); if (next_wr_bit != wr_bit) break; diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index 578007a01..e56d14b68 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -116,7 +116,7 @@ struct MemoryShareWorker created_conditions++; } - if (terms.width > 1) + if (terms.__width > 1) terms = module->ReduceAnd(NEW_ID, terms); return conditions_logic_cache[conditions] = terms; @@ -254,7 +254,7 @@ struct MemoryShareWorker // this is the naive version of the function that does not care about grouping the EN bits. RTLIL::SigSpec inv_mask_bits = module->Not(NEW_ID, mask_bits); - RTLIL::SigSpec inv_mask_bits_filtered = module->Mux(NEW_ID, RTLIL::SigSpec(RTLIL::State::S1, bits.width), inv_mask_bits, do_mask); + RTLIL::SigSpec inv_mask_bits_filtered = module->Mux(NEW_ID, RTLIL::SigSpec(RTLIL::State::S1, bits.__width), inv_mask_bits, do_mask); RTLIL::SigSpec result = module->And(NEW_ID, inv_mask_bits_filtered, bits); return result; } @@ -269,10 +269,10 @@ struct MemoryShareWorker std::map, std::pair>> groups; RTLIL::SigSpec grouped_bits, grouped_mask_bits; - for (int i = 0; i < bits.width; i++) { + for (int i = 0; i < bits.__width; i++) { std::pair key(v_bits[i], v_mask_bits[i]); if (groups.count(key) == 0) { - groups[key].first = grouped_bits.width; + groups[key].first = grouped_bits.__width; grouped_bits.append_bit(v_bits[i]); grouped_mask_bits.append_bit(v_mask_bits[i]); } @@ -282,7 +282,7 @@ struct MemoryShareWorker std::vector grouped_result = mask_en_naive(do_mask, grouped_bits, grouped_mask_bits); RTLIL::SigSpec result; - for (int i = 0; i < bits.width; i++) { + for (int i = 0; i < bits.__width; i++) { std::pair key(v_bits[i], v_mask_bits[i]); result.append_bit(grouped_result.at(groups.at(key).first)); } @@ -320,7 +320,7 @@ struct MemoryShareWorker // Create the new merged_data signal. - RTLIL::SigSpec new_merged_data(RTLIL::State::Sx, merged_data.width); + RTLIL::SigSpec new_merged_data(RTLIL::State::Sx, merged_data.__width); RTLIL::SigSpec old_data_set = module->And(NEW_ID, merged_en, merged_data); RTLIL::SigSpec old_data_unset = module->And(NEW_ID, merged_en, module->Not(NEW_ID, merged_data)); diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index d330fb7bd..8a097916d 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -106,13 +106,13 @@ static int count_nontrivial_wire_attrs(RTLIL::Wire *w) static bool compare_signals(RTLIL::SigSpec &s1, RTLIL::SigSpec &s2, SigPool ®s, SigPool &conns, std::set &direct_wires) { - assert(s1.width == 1); - assert(s2.width == 1); - assert(s1.chunks.size() == 1); - assert(s2.chunks.size() == 1); + assert(s1.__width == 1); + assert(s2.__width == 1); + assert(s1.__chunks.size() == 1); + assert(s2.__chunks.size() == 1); - RTLIL::Wire *w1 = s1.chunks[0].wire; - RTLIL::Wire *w2 = s2.chunks[0].wire; + RTLIL::Wire *w1 = s1.__chunks[0].wire; + RTLIL::Wire *w2 = s2.__chunks[0].wire; if (w1 == NULL || w2 == NULL) return w2 == NULL; @@ -235,14 +235,14 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool } else { s1.expand(); s2.expand(); - assert(s1.chunks.size() == s2.chunks.size()); + assert(s1.__chunks.size() == s2.__chunks.size()); RTLIL::SigSig new_conn; - for (size_t i = 0; i < s1.chunks.size(); i++) - if (s1.chunks[i] != s2.chunks[i]) { - new_conn.first.append(s1.chunks[i]); - new_conn.second.append(s2.chunks[i]); + for (size_t i = 0; i < s1.__chunks.size(); i++) + if (s1.__chunks[i] != s2.__chunks[i]) { + new_conn.first.append(s1.__chunks[i]); + new_conn.second.append(s2.__chunks[i]); } - if (new_conn.first.width > 0) { + if (new_conn.first.__width > 0) { new_conn.first.optimize(); new_conn.second.optimize(); used_signals.add(new_conn.first); @@ -258,8 +258,8 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool if (!used_signals_nodrivers.check_any(sig)) { std::string unused_bits; sig.expand(); - for (size_t i = 0; i < sig.chunks.size(); i++) { - if (sig.chunks[i].wire == NULL) + for (size_t i = 0; i < sig.__chunks.size(); i++) { + if (sig.__chunks[i].wire == NULL) continue; if (!used_signals_nodrivers.check_any(sig)) { if (!unused_bits.empty()) diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index e855e45ee..bee86771c 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -56,13 +56,13 @@ static void replace_undriven(RTLIL::Design *design, RTLIL::Module *module) all_signals.del(driven_signals); RTLIL::SigSpec undriven_signals = all_signals.export_all(); - for (auto &c : undriven_signals.chunks) + for (auto &c : undriven_signals.__chunks) { RTLIL::SigSpec sig = c; if (c.wire->name[0] == '$') sig = used_signals.extract(sig); - if (sig.width == 0) + if (sig.__width == 0) continue; log("Setting undriven signal in %s to undef: %s\n", RTLIL::id2cstr(module->name), log_signal(c)); @@ -74,7 +74,7 @@ static void replace_undriven(RTLIL::Design *design, RTLIL::Module *module) static void replace_cell(RTLIL::Module *module, RTLIL::Cell *cell, std::string info, std::string out_port, RTLIL::SigSpec out_val) { RTLIL::SigSpec Y = cell->connections[out_port]; - out_val.extend_u0(Y.width, false); + out_val.extend_u0(Y.__width, false); log("Replacing %s cell `%s' (%s) in module `%s' with constant driver `%s = %s'.\n", cell->type.c_str(), cell->name.c_str(), info.c_str(), @@ -99,11 +99,11 @@ static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool com RTLIL::SigSpec sig_y = sigmap(cell->connections.at("\\Y")); if (extend_u0) { - sig_a.extend_u0(sig_y.width, a_signed); - sig_b.extend_u0(sig_y.width, b_signed); + sig_a.extend_u0(sig_y.__width, a_signed); + sig_b.extend_u0(sig_y.__width, b_signed); } else { - sig_a.extend(sig_y.width, a_signed); - sig_b.extend(sig_y.width, b_signed); + sig_a.extend(sig_y.__width, a_signed); + sig_b.extend(sig_y.__width, b_signed); } std::vector bits_a = sig_a, bits_b = sig_b, bits_y = sig_y; @@ -153,7 +153,7 @@ static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool com for (auto &it : grouped_bits[i]) { for (auto &bit : it.second) { new_conn.first.append_bit(bit); - new_conn.second.append_bit(RTLIL::SigBit(new_y, new_a.width)); + new_conn.second.append_bit(RTLIL::SigBit(new_y, new_a.__width)); } new_a.append_bit(it.first.first); new_b.append_bit(it.first.second); @@ -162,12 +162,12 @@ static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool com RTLIL::Cell *c = module->addCell(NEW_ID, cell->type); c->connections["\\A"] = new_a; - c->parameters["\\A_WIDTH"] = new_a.width; + c->parameters["\\A_WIDTH"] = new_a.__width; c->parameters["\\A_SIGNED"] = false; if (b_name == "\\B") { c->connections["\\B"] = new_b; - c->parameters["\\B_WIDTH"] = new_b.width; + c->parameters["\\B_WIDTH"] = new_b.__width; c->parameters["\\B_SIGNED"] = false; } @@ -202,7 +202,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo for (auto &cell_it : module->cells) if (design->selected(module, cell_it.second)) { if ((cell_it.second->type == "$_INV_" || cell_it.second->type == "$not" || cell_it.second->type == "$logic_not") && - cell_it.second->connections["\\A"].width == 1 && cell_it.second->connections["\\Y"].width == 1) + cell_it.second->connections["\\A"].__width == 1 && cell_it.second->connections["\\Y"].__width == 1) invert_map[assign_map(cell_it.second->connections["\\Y"])] = assign_map(cell_it.second->connections["\\A"]); cells.push_back(cell_it.second); } @@ -334,12 +334,12 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cell->type == "$lt" || cell->type == "$le" || cell->type == "$ge" || cell->type == "$gt") replace_cell(module, cell, "x-bit in input", "\\Y", RTLIL::State::Sx); else - replace_cell(module, cell, "x-bit in input", "\\Y", RTLIL::SigSpec(RTLIL::State::Sx, cell->connections.at("\\Y").width)); + replace_cell(module, cell, "x-bit in input", "\\Y", RTLIL::SigSpec(RTLIL::State::Sx, cell->connections.at("\\Y").__width)); goto next_cell; } } - if ((cell->type == "$_INV_" || cell->type == "$not" || cell->type == "$logic_not") && cell->connections["\\Y"].width == 1 && + if ((cell->type == "$_INV_" || cell->type == "$not" || cell->type == "$logic_not") && cell->connections["\\Y"].__width == 1 && invert_map.count(assign_map(cell->connections["\\A"])) != 0) { replace_cell(module, cell, "double_invert", "\\Y", invert_map.at(assign_map(cell->connections["\\A"]))); goto next_cell; @@ -460,35 +460,35 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo RTLIL::SigSpec new_a, new_b; a.expand(), b.expand(); - assert(a.chunks.size() == b.chunks.size()); - for (size_t i = 0; i < a.chunks.size(); i++) { - if (a.chunks[i].wire == NULL && b.chunks[i].wire == NULL && a.chunks[i].data.bits[0] != b.chunks[i].data.bits[0] && - a.chunks[i].data.bits[0] <= RTLIL::State::S1 && b.chunks[i].data.bits[0] <= RTLIL::State::S1) { + assert(a.__chunks.size() == b.__chunks.size()); + for (size_t i = 0; i < a.__chunks.size(); i++) { + if (a.__chunks[i].wire == NULL && b.__chunks[i].wire == NULL && a.__chunks[i].data.bits[0] != b.__chunks[i].data.bits[0] && + a.__chunks[i].data.bits[0] <= RTLIL::State::S1 && b.__chunks[i].data.bits[0] <= RTLIL::State::S1) { RTLIL::SigSpec new_y = RTLIL::SigSpec((cell->type == "$eq" || cell->type == "$eqx") ? RTLIL::State::S0 : RTLIL::State::S1); new_y.extend(cell->parameters["\\Y_WIDTH"].as_int(), false); replace_cell(module, cell, "empty", "\\Y", new_y); goto next_cell; } - if (a.chunks[i] == b.chunks[i]) + if (a.__chunks[i] == b.__chunks[i]) continue; - new_a.append(a.chunks[i]); - new_b.append(b.chunks[i]); + new_a.append(a.__chunks[i]); + new_b.append(b.__chunks[i]); } - if (new_a.width == 0) { + if (new_a.__width == 0) { RTLIL::SigSpec new_y = RTLIL::SigSpec((cell->type == "$eq" || cell->type == "$eqx") ? RTLIL::State::S1 : RTLIL::State::S0); new_y.extend(cell->parameters["\\Y_WIDTH"].as_int(), false); replace_cell(module, cell, "empty", "\\Y", new_y); goto next_cell; } - if (new_a.width < a.width || new_b.width < b.width) { + if (new_a.__width < a.__width || new_b.__width < b.__width) { new_a.optimize(); new_b.optimize(); cell->connections["\\A"] = new_a; cell->connections["\\B"] = new_b; - cell->parameters["\\A_WIDTH"] = new_a.width; - cell->parameters["\\B_WIDTH"] = new_b.width; + cell->parameters["\\A_WIDTH"] = new_a.__width; + cell->parameters["\\B_WIDTH"] = new_b.__width; } } @@ -550,10 +550,10 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo RTLIL::SigSpec a = assign_map(cell->connections["\\A"]); RTLIL::SigSpec b = assign_map(cell->connections["\\B"]); - if (a.is_fully_const() && a.width <= 32 && a.as_int() == 1) + if (a.is_fully_const() && a.__width <= 32 && a.as_int() == 1) identity_wrt_b = true; - if (b.is_fully_const() && b.width <= 32 && b.as_int() == 1) + if (b.is_fully_const() && b.__width <= 32 && b.as_int() == 1) identity_wrt_a = true; } @@ -561,7 +561,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo { RTLIL::SigSpec b = assign_map(cell->connections["\\B"]); - if (b.is_fully_const() && b.width <= 32 && b.as_int() == 1) + if (b.is_fully_const() && b.__width <= 32 && b.as_int() == 1) identity_wrt_a = true; } @@ -650,13 +650,13 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (mux_undef && (cell->type == "$mux" || cell->type == "$pmux")) { RTLIL::SigSpec new_a, new_b, new_s; - int width = cell->connections.at("\\A").width; + int width = cell->connections.at("\\A").__width; if ((cell->connections.at("\\A").is_fully_undef() && cell->connections.at("\\B").is_fully_undef()) || cell->connections.at("\\S").is_fully_undef()) { replace_cell(module, cell, "mux undef", "\\Y", cell->connections.at("\\A")); goto next_cell; } - for (int i = 0; i < cell->connections.at("\\S").width; i++) { + for (int i = 0; i < cell->connections.at("\\S").__width; i++) { RTLIL::SigSpec old_b = cell->connections.at("\\B").extract(i*width, width); RTLIL::SigSpec old_s = cell->connections.at("\\S").extract(i, 1); if (old_b.is_fully_undef() || old_s.is_fully_undef()) @@ -665,12 +665,12 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo new_s.append(old_s); } new_a = cell->connections.at("\\A"); - if (new_a.is_fully_undef() && new_s.width > 0) { - new_a = new_b.extract((new_s.width-1)*width, width); - new_b = new_b.extract(0, (new_s.width-1)*width); - new_s = new_s.extract(0, new_s.width-1); + if (new_a.is_fully_undef() && new_s.__width > 0) { + new_a = new_b.extract((new_s.__width-1)*width, width); + new_b = new_b.extract(0, (new_s.__width-1)*width); + new_s = new_s.extract(0, new_s.__width-1); } - if (new_s.width == 0) { + if (new_s.__width == 0) { replace_cell(module, cell, "mux undef", "\\Y", new_a); goto next_cell; } @@ -678,13 +678,13 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo replace_cell(module, cell, "mux undef", "\\Y", new_s); goto next_cell; } - if (cell->connections.at("\\S").width != new_s.width) { + if (cell->connections.at("\\S").__width != new_s.__width) { cell->connections.at("\\A") = new_a; cell->connections.at("\\B") = new_b; cell->connections.at("\\S") = new_s; - if (new_s.width > 1) { + if (new_s.__width > 1) { cell->type = "$pmux"; - cell->parameters["\\S_WIDTH"] = new_s.width; + cell->parameters["\\S_WIDTH"] = new_s.__width; } else { cell->type = "$mux"; cell->parameters.erase("\\S_WIDTH"); @@ -700,9 +700,9 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo assign_map.apply(a); \ if (a.is_fully_const()) { \ a.optimize(); \ - if (a.chunks.empty()) a.chunks.push_back(RTLIL::SigChunk()); \ + if (a.__chunks.empty()) a.__chunks.push_back(RTLIL::SigChunk()); \ RTLIL::Const dummy_arg(RTLIL::State::S0, 1); \ - RTLIL::SigSpec y(RTLIL::const_ ## _t(a.chunks[0].data, dummy_arg, \ + RTLIL::SigSpec y(RTLIL::const_ ## _t(a.__chunks[0].data, dummy_arg, \ cell->parameters["\\A_SIGNED"].as_bool(), false, \ cell->parameters["\\Y_WIDTH"].as_int())); \ replace_cell(module, cell, stringf("%s", log_signal(a)), "\\Y", y); \ @@ -716,9 +716,9 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo assign_map.apply(a), assign_map.apply(b); \ if (a.is_fully_const() && b.is_fully_const()) { \ a.optimize(), b.optimize(); \ - if (a.chunks.empty()) a.chunks.push_back(RTLIL::SigChunk()); \ - if (b.chunks.empty()) b.chunks.push_back(RTLIL::SigChunk()); \ - RTLIL::SigSpec y(RTLIL::const_ ## _t(a.chunks[0].data, b.chunks[0].data, \ + if (a.__chunks.empty()) a.__chunks.push_back(RTLIL::SigChunk()); \ + if (b.__chunks.empty()) b.__chunks.push_back(RTLIL::SigChunk()); \ + RTLIL::SigSpec y(RTLIL::const_ ## _t(a.__chunks[0].data, b.__chunks[0].data, \ cell->parameters["\\A_SIGNED"].as_bool(), \ cell->parameters["\\B_SIGNED"].as_bool(), \ cell->parameters["\\Y_WIDTH"].as_int())); \ @@ -787,10 +787,10 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo RTLIL::SigSpec sig_b = assign_map(cell->connections["\\B"]); RTLIL::SigSpec sig_y = assign_map(cell->connections["\\Y"]); - if (sig_b.is_fully_const() && sig_b.width <= 32) + if (sig_b.is_fully_const() && sig_b.__width <= 32) std::swap(sig_a, sig_b), std::swap(a_signed, b_signed), swapped_ab = true; - if (sig_a.is_fully_def() && sig_a.width <= 32) + if (sig_a.is_fully_def() && sig_a.__width <= 32) { int a_val = sig_a.as_int(); @@ -799,7 +799,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo log("Replacing multiply-by-zero cell `%s' in module `%s' with zero-driver.\n", cell->name.c_str(), module->name.c_str()); - module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.width))); + module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.__width))); module->remove(cell); OPT_DID_SOMETHING = true; @@ -807,7 +807,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo goto next_cell; } - for (int i = 1; i < (a_signed ? sig_a.width-1 : sig_a.width); i++) + for (int i = 1; i < (a_signed ? sig_a.__width-1 : sig_a.__width); i++) if (a_val == (1 << i)) { log("Replacing multiply-by-%d cell `%s' in module `%s' with shift-by-%d.\n", diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc index 3292a46c8..e844a4209 100644 --- a/passes/opt/opt_muxtree.cc +++ b/passes/opt/opt_muxtree.cc @@ -92,8 +92,8 @@ struct OptMuxtreeWorker muxinfo_t muxinfo; muxinfo.cell = cell; - for (int i = 0; i < sig_s.width; i++) { - RTLIL::SigSpec sig = sig_b.extract(i*sig_a.width, sig_a.width); + for (int i = 0; i < sig_s.__width; i++) { + RTLIL::SigSpec sig = sig_b.extract(i*sig_a.__width, sig_a.__width); RTLIL::SigSpec ctrl_sig = assign_map(sig_s.extract(i, 1)); portinfo_t portinfo; for (int idx : sig2bits(sig)) { @@ -201,7 +201,7 @@ struct OptMuxtreeWorker if (live_ports.size() == 1) { - RTLIL::SigSpec sig_in = sig_ports.extract(live_ports[0]*sig_a.width, sig_a.width); + RTLIL::SigSpec sig_in = sig_ports.extract(live_ports[0]*sig_a.__width, sig_a.__width); module->connections.push_back(RTLIL::SigSig(sig_y, sig_in)); module->cells.erase(mi.cell->name); delete mi.cell; @@ -211,7 +211,7 @@ struct OptMuxtreeWorker RTLIL::SigSpec new_sig_a, new_sig_b, new_sig_s; for (size_t i = 0; i < live_ports.size(); i++) { - RTLIL::SigSpec sig_in = sig_ports.extract(live_ports[i]*sig_a.width, sig_a.width); + RTLIL::SigSpec sig_in = sig_ports.extract(live_ports[i]*sig_a.__width, sig_a.__width); if (i == live_ports.size()-1) { new_sig_a = sig_in; } else { @@ -223,11 +223,11 @@ struct OptMuxtreeWorker mi.cell->connections["\\A"] = new_sig_a; mi.cell->connections["\\B"] = new_sig_b; mi.cell->connections["\\S"] = new_sig_s; - if (new_sig_s.width == 1) { + if (new_sig_s.__width == 1) { mi.cell->type = "$mux"; mi.cell->parameters.erase("\\S_WIDTH"); } else { - mi.cell->parameters["\\S_WIDTH"] = RTLIL::Const(new_sig_s.width); + mi.cell->parameters["\\S_WIDTH"] = RTLIL::Const(new_sig_s.__width); } } } @@ -260,7 +260,7 @@ struct OptMuxtreeWorker std::vector results; assign_map.apply(sig); sig.expand(); - for (auto &c : sig.chunks) + for (auto &c : sig.__chunks) if (c.wire != NULL) { bitDef_t bit(c.wire, c.offset); if (bit2num.count(bit) == 0) { diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc index 93945e49a..4f1176d97 100644 --- a/passes/opt/opt_reduce.cc +++ b/passes/opt/opt_reduce.cc @@ -48,7 +48,7 @@ struct OptReduceWorker sig_a.expand(); RTLIL::SigSpec new_sig_a; - for (auto &chunk : sig_a.chunks) + for (auto &chunk : sig_a.__chunks) { if (chunk.wire == NULL && chunk.data.bits[0] == RTLIL::State::S0) { if (cell->type == "$reduce_and") { @@ -85,7 +85,7 @@ struct OptReduceWorker } new_sig_a.sort_and_unify(); - if (new_sig_a != sig_a || sig_a.width != cell->connections["\\A"].width) { + if (new_sig_a != sig_a || sig_a.__width != cell->connections["\\A"].__width) { log(" New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a)); did_something = true; OPT_DID_SOMETHING = true; @@ -93,7 +93,7 @@ struct OptReduceWorker } cell->connections["\\A"] = new_sig_a; - cell->parameters["\\A_WIDTH"] = RTLIL::Const(new_sig_a.width); + cell->parameters["\\A_WIDTH"] = RTLIL::Const(new_sig_a.__width); return; } @@ -107,20 +107,20 @@ struct OptReduceWorker std::set handled_sig; handled_sig.insert(sig_a); - for (int i = 0; i < sig_s.width; i++) + for (int i = 0; i < sig_s.__width; i++) { - RTLIL::SigSpec this_b = sig_b.extract(i*sig_a.width, sig_a.width); + RTLIL::SigSpec this_b = sig_b.extract(i*sig_a.__width, sig_a.__width); if (handled_sig.count(this_b) > 0) continue; RTLIL::SigSpec this_s = sig_s.extract(i, 1); - for (int j = i+1; j < sig_s.width; j++) { - RTLIL::SigSpec that_b = sig_b.extract(j*sig_a.width, sig_a.width); + for (int j = i+1; j < sig_s.__width; j++) { + RTLIL::SigSpec that_b = sig_b.extract(j*sig_a.__width, sig_a.__width); if (this_b == that_b) this_s.append(sig_s.extract(j, 1)); } - if (this_s.width > 1) + if (this_s.__width > 1) { RTLIL::Wire *reduce_or_wire = new RTLIL::Wire; reduce_or_wire->name = NEW_ID; @@ -131,7 +131,7 @@ struct OptReduceWorker reduce_or_cell->type = "$reduce_or"; reduce_or_cell->connections["\\A"] = this_s; reduce_or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); - reduce_or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(this_s.width); + reduce_or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(this_s.__width); reduce_or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); module->cells[reduce_or_cell->name] = reduce_or_cell; @@ -144,14 +144,14 @@ struct OptReduceWorker handled_sig.insert(this_b); } - if (new_sig_s.width != sig_s.width) { + if (new_sig_s.__width != sig_s.__width) { log(" New ctrl vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_s)); did_something = true; OPT_DID_SOMETHING = true; total_count++; } - if (new_sig_s.width == 0) + if (new_sig_s.__width == 0) { module->connections.push_back(RTLIL::SigSig(cell->connections["\\Y"], cell->connections["\\A"])); assign_map.add(cell->connections["\\Y"], cell->connections["\\A"]); @@ -162,8 +162,8 @@ struct OptReduceWorker { cell->connections["\\B"] = new_sig_b; cell->connections["\\S"] = new_sig_s; - if (new_sig_s.width > 1) { - cell->parameters["\\S_WIDTH"] = RTLIL::Const(new_sig_s.width); + if (new_sig_s.__width > 1) { + cell->parameters["\\S_WIDTH"] = RTLIL::Const(new_sig_s.__width); } else { cell->type = "$mux"; cell->parameters.erase("\\S_WIDTH"); @@ -224,7 +224,7 @@ struct OptReduceWorker cell->connections["\\A"].append(in_tuple.at(0)); cell->connections["\\B"] = RTLIL::SigSpec(); - for (int i = 1; i <= cell->connections["\\S"].width; i++) + for (int i = 1; i <= cell->connections["\\S"].__width; i++) for (auto &in_tuple : consolidated_in_tuples) cell->connections["\\B"].append(in_tuple.at(i)); diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc index 9a438537c..879f7ddc6 100644 --- a/passes/opt/opt_rmdff.cc +++ b/passes/opt/opt_rmdff.cc @@ -100,7 +100,7 @@ static bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) } } - if (sig_c.is_fully_const() && (!sig_r.width || !has_init)) { + if (sig_c.is_fully_const() && (!sig_r.__width || !has_init)) { if (val_rv.bits.size() == 0) val_rv = val_init; RTLIL::SigSig conn(sig_q, val_rv); @@ -108,26 +108,26 @@ static bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) goto delete_dff; } - if (sig_d.is_fully_undef() && sig_r.width && !has_init) { + if (sig_d.is_fully_undef() && sig_r.__width && !has_init) { RTLIL::SigSig conn(sig_q, val_rv); mod->connections.push_back(conn); goto delete_dff; } - if (sig_d.is_fully_undef() && !sig_r.width && has_init) { + if (sig_d.is_fully_undef() && !sig_r.__width && has_init) { RTLIL::SigSig conn(sig_q, val_init); mod->connections.push_back(conn); goto delete_dff; } - if (sig_d.is_fully_const() && !sig_r.width && !has_init) { + if (sig_d.is_fully_const() && !sig_r.__width && !has_init) { RTLIL::SigSig conn(sig_q, sig_d); mod->connections.push_back(conn); goto delete_dff; } - if (sig_d == sig_q && !(sig_r.width && has_init)) { - if (sig_r.width) { + if (sig_d == sig_q && !(sig_r.__width && has_init)) { + if (sig_r.__width) { RTLIL::SigSig conn(sig_q, val_rv); mod->connections.push_back(conn); } @@ -182,7 +182,7 @@ struct OptRmdffPass : public Pass { std::vector dff_list; for (auto &it : mod_it.second->cells) { if (it.second->type == "$mux" || it.second->type == "$pmux") { - if (it.second->connections.at("\\A").width == it.second->connections.at("\\B").width) + if (it.second->connections.at("\\A").__width == it.second->connections.at("\\B").__width) mux_drivers.insert(assign_map(it.second->connections.at("\\Y")), it.second); continue; } diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc index eb639d8ab..07e512cba 100644 --- a/passes/opt/opt_share.cc +++ b/passes/opt/opt_share.cc @@ -97,7 +97,7 @@ struct OptShareWorker RTLIL::SigSpec sig = it.second; assign_map.apply(sig); hash_string += "C " + it.first + "="; - for (auto &chunk : sig.chunks) { + for (auto &chunk : sig.__chunks) { if (chunk.wire) hash_string += "{" + chunk.wire->name + " " + int_to_hash_string(chunk.offset) + " " + diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc index 057378e7c..a773e5e72 100644 --- a/passes/proc/proc_arst.cc +++ b/passes/proc/proc_arst.cc @@ -28,7 +28,7 @@ extern void proc_clean_case(RTLIL::CaseRule *cs, bool &did_something, int &count static bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSpec ref, bool &polarity) { - if (signal.width != 1) + if (signal.__width != 1) return false; if (signal == ref) return true; @@ -80,13 +80,13 @@ static void apply_const(RTLIL::Module *mod, const RTLIL::SigSpec rspec, RTLIL::S { for (auto &action : cs->actions) { if (unknown) - rspec.replace(action.first, RTLIL::SigSpec(RTLIL::State::Sm, action.second.width), &rval); + rspec.replace(action.first, RTLIL::SigSpec(RTLIL::State::Sm, action.second.__width), &rval); else rspec.replace(action.first, action.second, &rval); } for (auto sw : cs->switches) { - if (sw->signal.width == 0) { + if (sw->signal.__width == 0) { for (auto cs2 : sw->cases) apply_const(mod, rspec, rval, cs2, const_sig, polarity, unknown); } @@ -164,11 +164,11 @@ restart_proc_arst: } for (auto &action : sync->actions) { RTLIL::SigSpec rspec = action.second; - RTLIL::SigSpec rval = RTLIL::SigSpec(RTLIL::State::Sm, rspec.width); + RTLIL::SigSpec rval = RTLIL::SigSpec(RTLIL::State::Sm, rspec.__width); rspec.expand(), rval.expand(); - for (int i = 0; i < int(rspec.chunks.size()); i++) - if (rspec.chunks[i].wire == NULL) - rval.chunks[i] = rspec.chunks[i]; + for (int i = 0; i < int(rspec.__chunks.size()); i++) + if (rspec.__chunks[i].wire == NULL) + rval.__chunks[i] = rspec.__chunks[i]; rspec.optimize(), rval.optimize(); RTLIL::SigSpec last_rval; for (int count = 0; rval != last_rval; count++) { @@ -252,14 +252,14 @@ struct ProcArstPass : public Pass { if (sync->type == RTLIL::SyncType::STp || sync->type == RTLIL::SyncType::STn) for (auto &act : sync->actions) { RTLIL::SigSpec arst_sig, arst_val; - for (auto &chunk : act.first.chunks) + for (auto &chunk : act.first.__chunks) if (chunk.wire && chunk.wire->attributes.count("\\init")) { RTLIL::SigSpec value = chunk.wire->attributes.at("\\init"); value.extend(chunk.wire->width, false); arst_sig.append(chunk); arst_val.append(value.extract(chunk.offset, chunk.width)); } - if (arst_sig.width) { + if (arst_sig.__width) { log("Added global reset to process %s: %s <- %s\n", proc_it.first.c_str(), log_signal(arst_sig), log_signal(arst_val)); arst_actions.push_back(RTLIL::SigSig(arst_sig, arst_val)); diff --git a/passes/proc/proc_clean.cc b/passes/proc/proc_clean.cc index 83554df90..768660686 100644 --- a/passes/proc/proc_clean.cc +++ b/passes/proc/proc_clean.cc @@ -27,7 +27,7 @@ extern void proc_clean_case(RTLIL::CaseRule *cs, bool &did_something, int &count void proc_clean_switch(RTLIL::SwitchRule *sw, RTLIL::CaseRule *parent, bool &did_something, int &count, int max_depth) { - if (sw->signal.width > 0 && sw->signal.is_fully_const()) + if (sw->signal.__width > 0 && sw->signal.is_fully_const()) { int found_matching_case_idx = -1; for (int i = 0; i < int(sw->cases.size()) && found_matching_case_idx < 0; i++) @@ -59,7 +59,7 @@ void proc_clean_switch(RTLIL::SwitchRule *sw, RTLIL::CaseRule *parent, bool &did sw->signal = RTLIL::SigSpec(); } - if (sw->cases.size() == 1 && (sw->signal.width == 0 || sw->cases[0]->compare.empty())) + if (sw->cases.size() == 1 && (sw->signal.__width == 0 || sw->cases[0]->compare.empty())) { did_something = true; for (auto &action : sw->cases[0]->actions) @@ -91,7 +91,7 @@ void proc_clean_switch(RTLIL::SwitchRule *sw, RTLIL::CaseRule *parent, bool &did void proc_clean_case(RTLIL::CaseRule *cs, bool &did_something, int &count, int max_depth) { for (size_t i = 0; i < cs->actions.size(); i++) { - if (cs->actions[i].first.width == 0) { + if (cs->actions[i].first.__width == 0) { did_something = true; cs->actions.erase(cs->actions.begin() + (i--)); } @@ -114,7 +114,7 @@ static void proc_clean(RTLIL::Module *mod, RTLIL::Process *proc, int &total_coun bool did_something = true; for (size_t i = 0; i < proc->syncs.size(); i++) { for (size_t j = 0; j < proc->syncs[i]->actions.size(); j++) - if (proc->syncs[i]->actions[j].first.width == 0) + if (proc->syncs[i]->actions[j].first.__width == 0) proc->syncs[i]->actions.erase(proc->syncs[i]->actions.begin() + (j--)); if (proc->syncs[i]->actions.size() == 0) { delete proc->syncs[i]; diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index 13e4e6606..d3dff8efc 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -32,7 +32,7 @@ static RTLIL::SigSpec find_any_lvalue(const RTLIL::Process *proc) for (auto sync : proc->syncs) for (auto &action : sync->actions) - if (action.first.width > 0) { + if (action.first.__width > 0) { lvalue = action.first; lvalue.sort_and_unify(); break; @@ -44,7 +44,7 @@ static RTLIL::SigSpec find_any_lvalue(const RTLIL::Process *proc) this_lvalue.append(action.first); this_lvalue.sort_and_unify(); RTLIL::SigSpec common_sig = this_lvalue.extract(lvalue); - if (common_sig.width > 0) + if (common_sig.__width > 0) lvalue = common_sig; } @@ -54,8 +54,8 @@ static RTLIL::SigSpec find_any_lvalue(const RTLIL::Process *proc) static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, RTLIL::SigSpec clk, bool clk_polarity, std::map> &async_rules, RTLIL::Process *proc) { - RTLIL::SigSpec sig_sr_set = RTLIL::SigSpec(0, sig_d.width); - RTLIL::SigSpec sig_sr_clr = RTLIL::SigSpec(0, sig_d.width); + RTLIL::SigSpec sig_sr_set = RTLIL::SigSpec(0, sig_d.__width); + RTLIL::SigSpec sig_sr_clr = RTLIL::SigSpec(0, sig_d.__width); for (auto &it : async_rules) { @@ -72,24 +72,24 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S else log_abort(); - if (sync_low_signals.width > 1) { + if (sync_low_signals.__width > 1) { RTLIL::Cell *cell = new RTLIL::Cell; cell->name = NEW_ID; cell->type = "$reduce_or"; cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); - cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.width); + cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.__width); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); cell->connections["\\A"] = sync_low_signals; cell->connections["\\Y"] = sync_low_signals = mod->addWire(NEW_ID); mod->add(cell); } - if (sync_low_signals.width > 0) { + if (sync_low_signals.__width > 0) { RTLIL::Cell *cell = new RTLIL::Cell; cell->name = NEW_ID; cell->type = "$not"; cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); - cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.width); + cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.__width); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); cell->connections["\\A"] = sync_low_signals; cell->connections["\\Y"] = mod->addWire(NEW_ID); @@ -97,12 +97,12 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S mod->add(cell); } - if (sync_high_signals.width > 1) { + if (sync_high_signals.__width > 1) { RTLIL::Cell *cell = new RTLIL::Cell; cell->name = NEW_ID; cell->type = "$reduce_or"; cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); - cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_high_signals.width); + cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_high_signals.__width); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); cell->connections["\\A"] = sync_high_signals; cell->connections["\\Y"] = sync_high_signals = mod->addWire(NEW_ID); @@ -113,30 +113,30 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S inv_cell->name = NEW_ID; inv_cell->type = "$not"; inv_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); - inv_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_d.width); - inv_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_d.width); + inv_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_d.__width); + inv_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_d.__width); inv_cell->connections["\\A"] = sync_value; - inv_cell->connections["\\Y"] = sync_value_inv = mod->addWire(NEW_ID, sig_d.width); + inv_cell->connections["\\Y"] = sync_value_inv = mod->addWire(NEW_ID, sig_d.__width); mod->add(inv_cell); RTLIL::Cell *mux_set_cell = new RTLIL::Cell; mux_set_cell->name = NEW_ID; mux_set_cell->type = "$mux"; - mux_set_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.width); + mux_set_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.__width); mux_set_cell->connections["\\A"] = sig_sr_set; mux_set_cell->connections["\\B"] = sync_value; mux_set_cell->connections["\\S"] = sync_high_signals; - mux_set_cell->connections["\\Y"] = sig_sr_set = mod->addWire(NEW_ID, sig_d.width); + mux_set_cell->connections["\\Y"] = sig_sr_set = mod->addWire(NEW_ID, sig_d.__width); mod->add(mux_set_cell); RTLIL::Cell *mux_clr_cell = new RTLIL::Cell; mux_clr_cell->name = NEW_ID; mux_clr_cell->type = "$mux"; - mux_clr_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.width); + mux_clr_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.__width); mux_clr_cell->connections["\\A"] = sig_sr_clr; mux_clr_cell->connections["\\B"] = sync_value_inv; mux_clr_cell->connections["\\S"] = sync_high_signals; - mux_clr_cell->connections["\\Y"] = sig_sr_clr = mod->addWire(NEW_ID, sig_d.width); + mux_clr_cell->connections["\\Y"] = sig_sr_clr = mod->addWire(NEW_ID, sig_d.__width); mod->add(mux_clr_cell); } @@ -147,7 +147,7 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S cell->name = sstr.str(); cell->type = "$dffsr"; cell->attributes = proc->attributes; - cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.width); + cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.__width); cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1); cell->parameters["\\SET_POLARITY"] = RTLIL::Const(true, 1); cell->parameters["\\CLR_POLARITY"] = RTLIL::Const(true, 1); @@ -168,16 +168,16 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec std::stringstream sstr; sstr << "$procdff$" << (RTLIL::autoidx++); - RTLIL::SigSpec sig_set_inv = mod->addWire(NEW_ID, sig_in.width); - RTLIL::SigSpec sig_sr_set = mod->addWire(NEW_ID, sig_in.width); - RTLIL::SigSpec sig_sr_clr = mod->addWire(NEW_ID, sig_in.width); + RTLIL::SigSpec sig_set_inv = mod->addWire(NEW_ID, sig_in.__width); + RTLIL::SigSpec sig_sr_set = mod->addWire(NEW_ID, sig_in.__width); + RTLIL::SigSpec sig_sr_clr = mod->addWire(NEW_ID, sig_in.__width); RTLIL::Cell *inv_set = new RTLIL::Cell; inv_set->name = NEW_ID; inv_set->type = "$not"; inv_set->parameters["\\A_SIGNED"] = RTLIL::Const(0); - inv_set->parameters["\\A_WIDTH"] = RTLIL::Const(sig_in.width); - inv_set->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_in.width); + inv_set->parameters["\\A_WIDTH"] = RTLIL::Const(sig_in.__width); + inv_set->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_in.__width); inv_set->connections["\\A"] = sig_set; inv_set->connections["\\Y"] = sig_set_inv; mod->add(inv_set); @@ -185,8 +185,8 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec RTLIL::Cell *mux_sr_set = new RTLIL::Cell; mux_sr_set->name = NEW_ID; mux_sr_set->type = "$mux"; - mux_sr_set->parameters["\\WIDTH"] = RTLIL::Const(sig_in.width); - mux_sr_set->connections[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.width); + mux_sr_set->parameters["\\WIDTH"] = RTLIL::Const(sig_in.__width); + mux_sr_set->connections[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.__width); mux_sr_set->connections[set_polarity ? "\\B" : "\\A"] = sig_set; mux_sr_set->connections["\\Y"] = sig_sr_set; mux_sr_set->connections["\\S"] = set; @@ -195,8 +195,8 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec RTLIL::Cell *mux_sr_clr = new RTLIL::Cell; mux_sr_clr->name = NEW_ID; mux_sr_clr->type = "$mux"; - mux_sr_clr->parameters["\\WIDTH"] = RTLIL::Const(sig_in.width); - mux_sr_clr->connections[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.width); + mux_sr_clr->parameters["\\WIDTH"] = RTLIL::Const(sig_in.__width); + mux_sr_clr->connections[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.__width); mux_sr_clr->connections[set_polarity ? "\\B" : "\\A"] = sig_set_inv; mux_sr_clr->connections["\\Y"] = sig_sr_clr; mux_sr_clr->connections["\\S"] = set; @@ -206,7 +206,7 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec cell->name = sstr.str(); cell->type = "$dffsr"; cell->attributes = proc->attributes; - cell->parameters["\\WIDTH"] = RTLIL::Const(sig_in.width); + cell->parameters["\\WIDTH"] = RTLIL::Const(sig_in.__width); cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1); cell->parameters["\\SET_POLARITY"] = RTLIL::Const(true, 1); cell->parameters["\\CLR_POLARITY"] = RTLIL::Const(true, 1); @@ -233,7 +233,7 @@ static void gen_dff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::Const val_ cell->attributes = proc->attributes; mod->cells[cell->name] = cell; - cell->parameters["\\WIDTH"] = RTLIL::Const(sig_in.width); + cell->parameters["\\WIDTH"] = RTLIL::Const(sig_in.__width); if (arst) { cell->parameters["\\ARST_POLARITY"] = RTLIL::Const(arst_polarity, 1); cell->parameters["\\ARST_VALUE"] = val_rst; @@ -259,14 +259,14 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) RTLIL::SigSpec sig = find_any_lvalue(proc); bool free_sync_level = false; - if (sig.width == 0) + if (sig.__width == 0) break; log("Creating register for signal `%s.%s' using process `%s.%s'.\n", mod->name.c_str(), log_signal(sig), mod->name.c_str(), proc->name.c_str()); - RTLIL::SigSpec insig = RTLIL::SigSpec(RTLIL::State::Sz, sig.width); - RTLIL::SigSpec rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.width); + RTLIL::SigSpec insig = RTLIL::SigSpec(RTLIL::State::Sz, sig.__width); + RTLIL::SigSpec rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.__width); RTLIL::SyncRule *sync_level = NULL; RTLIL::SyncRule *sync_edge = NULL; RTLIL::SyncRule *sync_always = NULL; @@ -276,16 +276,16 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) for (auto sync : proc->syncs) for (auto &action : sync->actions) { - if (action.first.extract(sig).width == 0) + if (action.first.extract(sig).__width == 0) continue; if (sync->type == RTLIL::SyncType::ST0 || sync->type == RTLIL::SyncType::ST1) { if (sync_level != NULL && sync_level != sync) { // log_error("Multiple level sensitive events found for this signal!\n"); many_async_rules[rstval].insert(sync_level); - rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.width); + rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.__width); } - rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.width); + rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.__width); sig.replace(action.first, action.second, &rstval); sync_level = sync; } @@ -324,15 +324,15 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) inputs.append(it->signal); compare.append(it->type == RTLIL::SyncType::ST0 ? RTLIL::State::S1 : RTLIL::State::S0); } - assert(inputs.width == compare.width); + assert(inputs.__width == compare.__width); RTLIL::Cell *cell = new RTLIL::Cell; cell->name = NEW_ID; cell->type = "$ne"; cell->parameters["\\A_SIGNED"] = RTLIL::Const(false, 1); cell->parameters["\\B_SIGNED"] = RTLIL::Const(false, 1); - cell->parameters["\\A_WIDTH"] = RTLIL::Const(inputs.width); - cell->parameters["\\B_WIDTH"] = RTLIL::Const(inputs.width); + cell->parameters["\\A_WIDTH"] = RTLIL::Const(inputs.__width); + cell->parameters["\\B_WIDTH"] = RTLIL::Const(inputs.__width); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); cell->connections["\\A"] = inputs; cell->connections["\\B"] = compare; @@ -343,7 +343,7 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) } else { - rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.width); + rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.__width); sync_level = NULL; } } @@ -357,7 +357,7 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) sig.optimize(); if (rstval == sig) { - rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.width); + rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.__width); sync_level = NULL; } @@ -386,7 +386,7 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) sync_edge->signal, sync_level->signal, proc); } else - gen_dff(mod, insig, rstval.chunks[0].data, sig, + gen_dff(mod, insig, rstval.__chunks[0].data, sig, sync_edge->type == RTLIL::SyncType::STp, sync_level && sync_level->type == RTLIL::SyncType::ST1, sync_edge->signal, sync_level ? &sync_level->signal : NULL, proc); diff --git a/passes/proc/proc_init.cc b/passes/proc/proc_init.cc index fca20fda2..0ef17b22d 100644 --- a/passes/proc/proc_init.cc +++ b/passes/proc/proc_init.cc @@ -60,13 +60,13 @@ static void proc_init(RTLIL::Module *mod, RTLIL::Process *proc) log_cmd_error("Failed to get a constant init value for %s: %s\n", log_signal(lhs), log_signal(rhs)); int offset = 0; - for (size_t i = 0; i < lhs.chunks.size(); i++) { - if (lhs.chunks[i].wire == NULL) + for (size_t i = 0; i < lhs.__chunks.size(); i++) { + if (lhs.__chunks[i].wire == NULL) continue; - RTLIL::Wire *wire = lhs.chunks[i].wire; - RTLIL::SigSpec value = rhs.extract(offset, lhs.chunks[i].width); - if (value.width != wire->width) - log_cmd_error("Init value is not for the entire wire: %s = %s\n", log_signal(lhs.chunks[i]), log_signal(value)); + RTLIL::Wire *wire = lhs.__chunks[i].wire; + RTLIL::SigSpec value = rhs.extract(offset, lhs.__chunks[i].width); + if (value.__width != wire->width) + log_cmd_error("Init value is not for the entire wire: %s = %s\n", log_signal(lhs.__chunks[i]), log_signal(value)); log(" Setting init value: %s = %s\n", log_signal(wire), log_signal(value)); wire->attributes["\\init"] = value.as_const(); offset += wire->width; diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc index 9b2f83885..2e24e786b 100644 --- a/passes/proc/proc_mux.cc +++ b/passes/proc/proc_mux.cc @@ -28,14 +28,14 @@ static RTLIL::SigSpec find_any_lvalue(const RTLIL::CaseRule *cs) { for (auto &action : cs->actions) { - if (action.first.width) + if (action.first.__width) return action.first; } for (auto sw : cs->switches) for (auto cs2 : sw->cases) { RTLIL::SigSpec sig = find_any_lvalue(cs2); - if (sig.width) + if (sig.__width) return sig; } @@ -46,7 +46,7 @@ static void extract_core_signal(const RTLIL::CaseRule *cs, RTLIL::SigSpec &sig) { for (auto &action : cs->actions) { RTLIL::SigSpec lvalue = action.first.extract(sig); - if (lvalue.width) + if (lvalue.__width) sig = lvalue; } @@ -72,18 +72,18 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, comp.expand(); // get rid of don't-care bits - assert(sig.width == comp.width); - for (int i = 0; i < comp.width; i++) - if (comp.chunks[i].wire == NULL && comp.chunks[i].data.bits[0] == RTLIL::State::Sa) { + assert(sig.__width == comp.__width); + for (int i = 0; i < comp.__width; i++) + if (comp.__chunks[i].wire == NULL && comp.__chunks[i].data.bits[0] == RTLIL::State::Sa) { sig.remove(i, 1); comp.remove(i--, 1); } - if (comp.width == 0) + if (comp.__width == 0) return RTLIL::SigSpec(); sig.optimize(); comp.optimize(); - if (sig.width == 1 && comp == RTLIL::SigSpec(1,1)) + if (sig.__width == 1 && comp == RTLIL::SigSpec(1,1)) { mod->connections.push_back(RTLIL::SigSig(RTLIL::SigSpec(cmp_wire, 1, cmp_wire->width++), sig)); } @@ -101,8 +101,8 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(0); - eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig.width); - eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(comp.width); + eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig.__width); + eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(comp.__width); eq_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); eq_cell->connections["\\A"] = sig; @@ -143,7 +143,7 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector &compare, RTLIL::SigSpec when_signal, RTLIL::SigSpec else_signal, RTLIL::Cell *&last_mux_cell, RTLIL::SwitchRule *sw) { - assert(when_signal.width == else_signal.width); + assert(when_signal.__width == else_signal.__width); std::stringstream sstr; sstr << "$procmux$" << (RTLIL::autoidx++); @@ -154,14 +154,14 @@ static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, // compare results RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw); - if (ctrl_sig.width == 0) + if (ctrl_sig.__width == 0) return when_signal; - assert(ctrl_sig.width == 1); + assert(ctrl_sig.__width == 1); // prepare multiplexer output signal RTLIL::Wire *result_wire = new RTLIL::Wire; result_wire->name = sstr.str() + "_Y"; - result_wire->width = when_signal.width; + result_wire->width = when_signal.__width; mod->wires[result_wire->name] = result_wire; // create the multiplexer itself @@ -171,7 +171,7 @@ static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, mux_cell->attributes = sw->attributes; mod->cells[mux_cell->name] = mux_cell; - mux_cell->parameters["\\WIDTH"] = RTLIL::Const(when_signal.width); + mux_cell->parameters["\\WIDTH"] = RTLIL::Const(when_signal.__width); mux_cell->connections["\\A"] = else_signal; mux_cell->connections["\\B"] = when_signal; mux_cell->connections["\\S"] = ctrl_sig; @@ -184,14 +184,14 @@ static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, static void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector &compare, RTLIL::SigSpec when_signal, RTLIL::Cell *last_mux_cell, RTLIL::SwitchRule *sw) { assert(last_mux_cell != NULL); - assert(when_signal.width == last_mux_cell->connections["\\A"].width); + assert(when_signal.__width == last_mux_cell->connections["\\A"].__width); RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw); - assert(ctrl_sig.width == 1); + assert(ctrl_sig.__width == 1); last_mux_cell->type = "$pmux"; last_mux_cell->connections["\\S"].append(ctrl_sig); last_mux_cell->connections["\\B"].append(when_signal); - last_mux_cell->parameters["\\S_WIDTH"] = last_mux_cell->connections["\\S"].width; + last_mux_cell->parameters["\\S_WIDTH"] = last_mux_cell->connections["\\S"].__width; } static RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, RTLIL::CaseRule *cs, const RTLIL::SigSpec &sig, const RTLIL::SigSpec &defval) @@ -208,7 +208,7 @@ static RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, RTLIL::CaseRule *cs // detect groups of parallel cases std::vector pgroups(sw->cases.size()); if (!sw->get_bool_attribute("\\parallel_case")) { - BitPatternPool pool(sw->signal.width); + BitPatternPool pool(sw->signal.__width); bool extra_group_for_next_case = false; for (size_t i = 0; i < sw->cases.size(); i++) { RTLIL::CaseRule *cs2 = sw->cases[i]; @@ -224,7 +224,7 @@ static RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, RTLIL::CaseRule *cs if (cs2->compare.empty()) pgroups[i] = pgroups[i-1]+1; if (pgroups[i] != pgroups[i-1]) - pool = BitPatternPool(sw->signal.width); + pool = BitPatternPool(sw->signal.__width); } for (auto pat : cs2->compare) if (!pat.is_fully_const()) @@ -258,7 +258,7 @@ static void proc_mux(RTLIL::Module *mod, RTLIL::Process *proc) { RTLIL::SigSpec sig = find_any_lvalue(&proc->root_case); - if (sig.width == 0) + if (sig.__width == 0) break; if (first) { @@ -270,7 +270,7 @@ static void proc_mux(RTLIL::Module *mod, RTLIL::Process *proc) log(" creating decoder for signal `%s'.\n", log_signal(sig)); - RTLIL::SigSpec value = signal_to_mux_tree(mod, &proc->root_case, sig, RTLIL::SigSpec(RTLIL::State::Sx, sig.width)); + RTLIL::SigSpec value = signal_to_mux_tree(mod, &proc->root_case, sig, RTLIL::SigSpec(RTLIL::State::Sx, sig.__width)); mod->connections.push_back(RTLIL::SigSig(sig, value)); } } diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc index 5c38cc2cf..5369617be 100644 --- a/passes/sat/eval.cc +++ b/passes/sat/eval.cc @@ -44,7 +44,7 @@ struct BruteForceEquivChecker void run_checker(RTLIL::SigSpec &inputs) { - if (inputs.width < mod1_inputs.width) { + if (inputs.__width < mod1_inputs.__width) { RTLIL::SigSpec inputs0 = inputs, inputs1 = inputs; inputs0.append(RTLIL::Const(0, 1)); inputs1.append(RTLIL::Const(1, 1)); @@ -71,9 +71,9 @@ struct BruteForceEquivChecker if (ignore_x_mod1) { sig1.expand(), sig2.expand(); - for (size_t i = 0; i < sig1.chunks.size(); i++) - if (sig1.chunks.at(i) == RTLIL::SigChunk(RTLIL::State::Sx)) - sig2.chunks.at(i) = RTLIL::SigChunk(RTLIL::State::Sx); + for (size_t i = 0; i < sig1.__chunks.size(); i++) + if (sig1.__chunks.at(i) == RTLIL::SigChunk(RTLIL::State::Sx)) + sig2.__chunks.at(i) = RTLIL::SigChunk(RTLIL::State::Sx); sig1.optimize(), sig2.optimize(); } @@ -172,11 +172,11 @@ struct VlogHammerReporter log_error("Failed to find solution to SAT problem.\n"); expected_y.expand(); - for (int i = 0; i < expected_y.width; i++) { + for (int i = 0; i < expected_y.__width; i++) { RTLIL::State solution_bit = y_values.at(i) ? RTLIL::State::S1 : RTLIL::State::S0; - RTLIL::State expected_bit = expected_y.chunks.at(i).data.bits.at(0); + RTLIL::State expected_bit = expected_y.__chunks.at(i).data.bits.at(0); if (model_undef) { - if (y_values.at(expected_y.width+i)) + if (y_values.at(expected_y.__width+i)) solution_bit = RTLIL::State::Sx; } else { if (expected_bit == RTLIL::State::Sx) @@ -184,17 +184,17 @@ struct VlogHammerReporter } if (solution_bit != expected_bit) { std::string sat_bits, rtl_bits; - for (int k = expected_y.width-1; k >= 0; k--) { - if (model_undef && y_values.at(expected_y.width+k)) + for (int k = expected_y.__width-1; k >= 0; k--) { + if (model_undef && y_values.at(expected_y.__width+k)) sat_bits += "x"; else sat_bits += y_values.at(k) ? "1" : "0"; - rtl_bits += expected_y.chunks.at(k).data.bits.at(0) == RTLIL::State::Sx ? "x" : - expected_y.chunks.at(k).data.bits.at(0) == RTLIL::State::S1 ? "1" : "0"; + rtl_bits += expected_y.__chunks.at(k).data.bits.at(0) == RTLIL::State::Sx ? "x" : + expected_y.__chunks.at(k).data.bits.at(0) == RTLIL::State::S1 ? "1" : "0"; } log_error("Found error in SAT model: y[%d] = %s, should be %s:\n SAT: %s\n RTL: %s\n %*s^\n", int(i), log_signal(solution_bit), log_signal(expected_bit), - sat_bits.c_str(), rtl_bits.c_str(), expected_y.width-i-1, ""); + sat_bits.c_str(), rtl_bits.c_str(), expected_y.__width-i-1, ""); } } @@ -203,16 +203,16 @@ struct VlogHammerReporter std::vector cmp_vars; std::vector cmp_vals; - std::vector y_undef(y_values.begin() + expected_y.width, y_values.end()); + std::vector y_undef(y_values.begin() + expected_y.__width, y_values.end()); - for (int i = 0; i < expected_y.width; i++) + for (int i = 0; i < expected_y.__width; i++) if (y_undef.at(i)) { log(" Toggling undef bit %d to test undef gating.\n", i); if (!ez.solve(y_vec, y_values, ez.IFF(y_vec.at(i), y_values.at(i) ? ez.FALSE : ez.TRUE))) log_error("Failed to find solution with toggled bit!\n"); - cmp_vars.push_back(y_vec.at(expected_y.width + i)); + cmp_vars.push_back(y_vec.at(expected_y.__width + i)); cmp_vals.push_back(true); } else @@ -220,7 +220,7 @@ struct VlogHammerReporter cmp_vars.push_back(y_vec.at(i)); cmp_vals.push_back(y_values.at(i)); - cmp_vars.push_back(y_vec.at(expected_y.width + i)); + cmp_vars.push_back(y_vec.at(expected_y.__width + i)); cmp_vals.push_back(false); } @@ -283,7 +283,7 @@ struct VlogHammerReporter while (!ce.eval(sig, undef)) { // log_error("Evaluation of y in module %s failed: sig=%s, undef=%s\n", RTLIL::id2cstr(module->name), log_signal(sig), log_signal(undef)); log("Warning: Setting signal %s in module %s to undef.\n", log_signal(undef), RTLIL::id2cstr(module->name)); - ce.set(undef, RTLIL::Const(RTLIL::State::Sx, undef.width)); + ce.set(undef, RTLIL::Const(RTLIL::State::Sx, undef.__width)); } log("++VAL++ %d %s %s #\n", idx, module_name.c_str(), sig.as_const().as_string().c_str()); @@ -293,13 +293,13 @@ struct VlogHammerReporter rtl_sig.expand(); sat_check(module, recorded_set_vars, recorded_set_vals, sig, false); sat_check(module, recorded_set_vars, recorded_set_vals, sig, true); - } else if (rtl_sig.width > 0) { + } else if (rtl_sig.__width > 0) { sig.expand(); - if (rtl_sig.width != sig.width) + if (rtl_sig.__width != sig.__width) log_error("Output (y) has a different width in module %s compared to rtl!\n", RTLIL::id2cstr(module->name)); - for (int i = 0; i < sig.width; i++) - if (rtl_sig.chunks.at(i).data.bits.at(0) == RTLIL::State::Sx) - sig.chunks.at(i).data.bits.at(0) = RTLIL::State::Sx; + for (int i = 0; i < sig.__width; i++) + if (rtl_sig.__chunks.at(i).data.bits.at(0) == RTLIL::State::Sx) + sig.__chunks.at(i).data.bits.at(0) = RTLIL::State::Sx; } log("++RPT++ %d%s %s %s\n", idx, input_pattern_list.c_str(), sig.as_const().as_string().c_str(), module_name.c_str()); @@ -350,7 +350,7 @@ struct VlogHammerReporter } if (!RTLIL::SigSpec::parse(sig, NULL, pattern) || !sig.is_fully_const()) log_error("Failed to parse pattern %s!\n", pattern.c_str()); - if (sig.width < total_input_width) + if (sig.__width < total_input_width) log_error("Pattern %s is to short!\n", pattern.c_str()); patterns.push_back(sig.as_const()); if (invert_pattern) { @@ -470,9 +470,9 @@ struct EvalPass : public Pass { log_cmd_error("Failed to parse rhs set expression `%s'.\n", it.second.c_str()); if (!rhs.is_fully_const()) log_cmd_error("Right-hand-side set expression `%s' is not constant.\n", it.second.c_str()); - if (lhs.width != rhs.width) + if (lhs.__width != rhs.__width) log_cmd_error("Set expression with different lhs and rhs sizes: %s (%s, %d bits) vs. %s (%s, %d bits)\n", - it.first.c_str(), log_signal(lhs), lhs.width, it.second.c_str(), log_signal(rhs), rhs.width); + it.first.c_str(), log_signal(lhs), lhs.__width, it.second.c_str(), log_signal(rhs), rhs.__width); ce.set(lhs, rhs.as_const()); } @@ -493,7 +493,7 @@ struct EvalPass : public Pass { if (set_undef) { while (!ce.eval(value, undef)) { log("Failed to evaluate signal %s: Missing value for %s. -> setting to undef\n", log_signal(signal), log_signal(undef)); - ce.set(undef, RTLIL::Const(RTLIL::State::Sx, undef.width)); + ce.set(undef, RTLIL::Const(RTLIL::State::Sx, undef.__width)); undef = RTLIL::SigSpec(); } log("Eval result: %s = %s.\n", log_signal(signal), log_signal(value)); @@ -526,15 +526,15 @@ struct EvalPass : public Pass { } std::vector tab_line; - for (auto &c : tabsigs.chunks) + for (auto &c : tabsigs.__chunks) tab_line.push_back(log_signal(c)); tab_sep_colidx = tab_line.size(); - for (auto &c : signal.chunks) + for (auto &c : signal.__chunks) tab_line.push_back(log_signal(c)); tab.push_back(tab_line); tab_line.clear(); - RTLIL::Const tabvals(0, tabsigs.width); + RTLIL::Const tabvals(0, tabsigs.__width); do { ce.push(); @@ -548,19 +548,19 @@ struct EvalPass : public Pass { log_signal(tabsigs), log_signal(tabvals), log_signal(this_undef)); return; } - ce.set(this_undef, RTLIL::Const(RTLIL::State::Sx, this_undef.width)); + ce.set(this_undef, RTLIL::Const(RTLIL::State::Sx, this_undef.__width)); undef.append(this_undef); this_undef = RTLIL::SigSpec(); } int pos = 0; - for (auto &c : tabsigs.chunks) { + for (auto &c : tabsigs.__chunks) { tab_line.push_back(log_signal(RTLIL::SigSpec(tabvals).extract(pos, c.width))); pos += c.width; } pos = 0; - for (auto &c : signal.chunks) { + for (auto &c : signal.__chunks) { tab_line.push_back(log_signal(value.extract(pos, c.width))); pos += c.width; } @@ -602,7 +602,7 @@ struct EvalPass : public Pass { } log("\n"); - if (undef.width > 0) { + if (undef.__width > 0) { undef.sort_and_unify(); log("Assumend undef (x) value for the following singals: %s\n\n", log_signal(undef)); } diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc index 831a43aa5..4308e7364 100644 --- a/passes/sat/expose.cc +++ b/passes/sat/expose.cc @@ -649,7 +649,7 @@ struct ExposePass : public Pass { { RTLIL::Wire *w = new RTLIL::Wire; w->name = cell->name + sep + RTLIL::unescape_id(it.first); - w->width = it.second.width; + w->width = it.second.__width; if (ct.cell_input(cell->type, it.first)) w->port_output = true; if (ct.cell_output(cell->type, it.first)) diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index ac0415644..8cc59b291 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -714,7 +714,7 @@ struct FreduceWorker if (grp[i].inverted) { - if (inv_sig.width == 0) + if (inv_sig.__width == 0) { inv_sig = module->addWire(NEW_ID); diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index 6e57fceb1..1cd794b56 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -253,11 +253,11 @@ static void create_miter_equiv(struct Pass *that, std::vector args, } } - if (all_conditions.width != 1) { + if (all_conditions.__width != 1) { RTLIL::Cell *reduce_cell = new RTLIL::Cell; reduce_cell->name = NEW_ID; reduce_cell->type = "$reduce_and"; - reduce_cell->parameters["\\A_WIDTH"] = all_conditions.width; + reduce_cell->parameters["\\A_WIDTH"] = all_conditions.__width; reduce_cell->parameters["\\Y_WIDTH"] = 1; reduce_cell->parameters["\\A_SIGNED"] = 0; reduce_cell->connections["\\A"] = all_conditions; @@ -283,8 +283,8 @@ static void create_miter_equiv(struct Pass *that, std::vector args, RTLIL::Cell *not_cell = new RTLIL::Cell; not_cell->name = NEW_ID; not_cell->type = "$not"; - not_cell->parameters["\\A_WIDTH"] = all_conditions.width; - not_cell->parameters["\\A_WIDTH"] = all_conditions.width; + not_cell->parameters["\\A_WIDTH"] = all_conditions.__width; + not_cell->parameters["\\A_WIDTH"] = all_conditions.__width; not_cell->parameters["\\Y_WIDTH"] = w_trigger->width; not_cell->parameters["\\A_SIGNED"] = 0; not_cell->connections["\\A"] = all_conditions; diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index a9a00d8a2..161449324 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -101,10 +101,10 @@ struct SatHelper RTLIL::SigSpec lhs = sigmap(it.second); RTLIL::SigSpec rhs = it.second->attributes.at("\\init"); - log_assert(lhs.width == rhs.width); + log_assert(lhs.__width == rhs.__width); RTLIL::SigSpec removed_bits; - for (int i = 0; i < lhs.width; i++) { + for (int i = 0; i < lhs.__width; i++) { RTLIL::SigSpec bit = lhs.extract(i, 1); if (!satgen.initial_state.check_all(bit)) { removed_bits.append(bit); @@ -118,10 +118,10 @@ struct SatHelper rhs.optimize(); removed_bits.optimize(); - if (removed_bits.width) + if (removed_bits.__width) log("Warning: ignoring initial value on non-register: %s\n", log_signal(removed_bits)); - if (lhs.width) { + if (lhs.__width) { log("Import set-constraint from init attribute: %s = %s\n", log_signal(lhs), log_signal(rhs)); big_lhs.remove2(lhs, &big_rhs); big_lhs.append(lhs); @@ -140,9 +140,9 @@ struct SatHelper show_signal_pool.add(sigmap(lhs)); show_signal_pool.add(sigmap(rhs)); - if (lhs.width != rhs.width) + if (lhs.__width != rhs.__width) log_cmd_error("Set expression with different lhs and rhs sizes: %s (%s, %d bits) vs. %s (%s, %d bits)\n", - s.first.c_str(), log_signal(lhs), lhs.width, s.second.c_str(), log_signal(rhs), rhs.width); + s.first.c_str(), log_signal(lhs), lhs.__width, s.second.c_str(), log_signal(rhs), rhs.__width); log("Import set-constraint: %s = %s\n", log_signal(lhs), log_signal(rhs)); big_lhs.remove2(lhs, &big_rhs); @@ -166,17 +166,17 @@ struct SatHelper RTLIL::SigSpec rem = satgen.initial_state.export_all(); rem.remove(big_lhs); big_lhs.append(rem); - big_rhs.append(RTLIL::SigSpec(RTLIL::State::Sx, rem.width)); + big_rhs.append(RTLIL::SigSpec(RTLIL::State::Sx, rem.__width)); } if (set_init_zero) { RTLIL::SigSpec rem = satgen.initial_state.export_all(); rem.remove(big_lhs); big_lhs.append(rem); - big_rhs.append(RTLIL::SigSpec(RTLIL::State::S0, rem.width)); + big_rhs.append(RTLIL::SigSpec(RTLIL::State::S0, rem.__width)); } - if (big_lhs.width == 0) { + if (big_lhs.__width == 0) { log("No constraints for initial state found.\n\n"); return; } @@ -209,9 +209,9 @@ struct SatHelper show_signal_pool.add(sigmap(lhs)); show_signal_pool.add(sigmap(rhs)); - if (lhs.width != rhs.width) + if (lhs.__width != rhs.__width) log_cmd_error("Set expression with different lhs and rhs sizes: %s (%s, %d bits) vs. %s (%s, %d bits)\n", - s.first.c_str(), log_signal(lhs), lhs.width, s.second.c_str(), log_signal(rhs), rhs.width); + s.first.c_str(), log_signal(lhs), lhs.__width, s.second.c_str(), log_signal(rhs), rhs.__width); log("Import set-constraint: %s = %s\n", log_signal(lhs), log_signal(rhs)); big_lhs.remove2(lhs, &big_rhs); @@ -230,9 +230,9 @@ struct SatHelper show_signal_pool.add(sigmap(lhs)); show_signal_pool.add(sigmap(rhs)); - if (lhs.width != rhs.width) + if (lhs.__width != rhs.__width) log_cmd_error("Set expression with different lhs and rhs sizes: %s (%s, %d bits) vs. %s (%s, %d bits)\n", - s.first.c_str(), log_signal(lhs), lhs.width, s.second.c_str(), log_signal(rhs), rhs.width); + s.first.c_str(), log_signal(lhs), lhs.__width, s.second.c_str(), log_signal(rhs), rhs.__width); log("Import set-constraint for this timestep: %s = %s\n", log_signal(lhs), log_signal(rhs)); big_lhs.remove2(lhs, &big_rhs); @@ -358,9 +358,9 @@ struct SatHelper show_signal_pool.add(sigmap(lhs)); show_signal_pool.add(sigmap(rhs)); - if (lhs.width != rhs.width) + if (lhs.__width != rhs.__width) log_cmd_error("Proof expression with different lhs and rhs sizes: %s (%s, %d bits) vs. %s (%s, %d bits)\n", - s.first.c_str(), log_signal(lhs), lhs.width, s.second.c_str(), log_signal(rhs), rhs.width); + s.first.c_str(), log_signal(lhs), lhs.__width, s.second.c_str(), log_signal(rhs), rhs.__width); log("Import proof-constraint: %s = %s\n", log_signal(lhs), log_signal(rhs)); big_lhs.remove2(lhs, &big_rhs); @@ -386,9 +386,9 @@ struct SatHelper show_signal_pool.add(sigmap(lhs)); show_signal_pool.add(sigmap(rhs)); - if (lhs.width != rhs.width) + if (lhs.__width != rhs.__width) log_cmd_error("Proof-x expression with different lhs and rhs sizes: %s (%s, %d bits) vs. %s (%s, %d bits)\n", - s.first.c_str(), log_signal(lhs), lhs.width, s.second.c_str(), log_signal(rhs), rhs.width); + s.first.c_str(), log_signal(lhs), lhs.__width, s.second.c_str(), log_signal(rhs), rhs.__width); log("Import proof-x-constraint: %s = %s\n", log_signal(lhs), log_signal(rhs)); big_lhs.remove2(lhs, &big_rhs); @@ -413,8 +413,8 @@ struct SatHelper satgen.getAsserts(asserts_a, asserts_en, timestep); asserts_a.expand(); asserts_en.expand(); - for (size_t i = 0; i < asserts_a.chunks.size(); i++) - log("Import proof for assert: %s when %s.\n", log_signal(asserts_a.chunks[i]), log_signal(asserts_en.chunks[i])); + for (size_t i = 0; i < asserts_a.__chunks.size(); i++) + log("Import proof for assert: %s when %s.\n", log_signal(asserts_a.__chunks[i]), log_signal(asserts_en.__chunks[i])); prove_bits.push_back(satgen.importAsserts(timestep)); } @@ -543,12 +543,12 @@ struct SatHelper std::vector modelUndefExpressions; - for (auto &c : modelSig.chunks) + for (auto &c : modelSig.__chunks) if (c.wire != NULL) { ModelBlockInfo info; RTLIL::SigSpec chunksig = c; - info.width = chunksig.width; + info.width = chunksig.__width; info.description = log_signal(chunksig); for (int timestep = -1; timestep <= max_timestep; timestep++) @@ -573,7 +573,7 @@ struct SatHelper // Add initial state signals as collected by satgen // modelSig = satgen.initial_state.export_all(); - for (auto &c : modelSig.chunks) + for (auto &c : modelSig.__chunks) if (c.wire != NULL) { ModelBlockInfo info; @@ -581,7 +581,7 @@ struct SatHelper info.timestep = 0; info.offset = modelExpressions.size(); - info.width = chunksig.width; + info.width = chunksig.__width; info.description = log_signal(chunksig); modelInfo.insert(info); diff --git a/passes/sat/share.cc b/passes/sat/share.cc index 42e59c475..95f35bb3e 100644 --- a/passes/sat/share.cc +++ b/passes/sat/share.cc @@ -273,11 +273,11 @@ struct ShareWorker RTLIL::SigSpec a2 = c2->connections.at("\\A"); RTLIL::SigSpec y2 = c2->connections.at("\\Y"); - int a_width = std::max(a1.width, a2.width); - int y_width = std::max(y1.width, y2.width); + int a_width = std::max(a1.__width, a2.__width); + int y_width = std::max(y1.__width, y2.__width); - if (a1.width != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y"); - if (a2.width != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y"); + if (a1.__width != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y"); + if (a2.__width != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y"); RTLIL::SigSpec a = module->Mux(NEW_ID, a2, a1, act); RTLIL::Wire *y = module->addWire(NEW_ID, y_width); @@ -292,8 +292,8 @@ struct ShareWorker supercell->connections["\\Y"] = y; module->add(supercell); - RTLIL::SigSpec new_y1(y, y1.width); - RTLIL::SigSpec new_y2(y, y2.width); + RTLIL::SigSpec new_y1(y, y1.__width); + RTLIL::SigSpec new_y2(y, y2.__width); module->connections.push_back(RTLIL::SigSig(y1, new_y1)); module->connections.push_back(RTLIL::SigSig(y2, new_y2)); @@ -367,28 +367,28 @@ struct ShareWorker RTLIL::SigSpec b2 = c2->connections.at("\\B"); RTLIL::SigSpec y2 = c2->connections.at("\\Y"); - int a_width = std::max(a1.width, a2.width); - int b_width = std::max(b1.width, b2.width); - int y_width = std::max(y1.width, y2.width); + int a_width = std::max(a1.__width, a2.__width); + int b_width = std::max(b1.__width, b2.__width); + int y_width = std::max(y1.__width, y2.__width); if (c1->type == "$shr" && a_signed) { a_width = std::max(y_width, a_width); - if (a1.width < y1.width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, y1.width), true)->connections.at("\\Y"); - if (a2.width < y2.width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, y2.width), true)->connections.at("\\Y"); + if (a1.__width < y1.__width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, y1.__width), true)->connections.at("\\Y"); + if (a2.__width < y2.__width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, y2.__width), true)->connections.at("\\Y"); - if (a1.width != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), false)->connections.at("\\Y"); - if (a2.width != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), false)->connections.at("\\Y"); + if (a1.__width != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), false)->connections.at("\\Y"); + if (a2.__width != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), false)->connections.at("\\Y"); } else { - if (a1.width != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y"); - if (a2.width != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y"); + if (a1.__width != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y"); + if (a2.__width != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y"); } - if (b1.width != b_width) b1 = module->addPos(NEW_ID, b1, module->addWire(NEW_ID, b_width), b_signed)->connections.at("\\Y"); - if (b2.width != b_width) b2 = module->addPos(NEW_ID, b2, module->addWire(NEW_ID, b_width), b_signed)->connections.at("\\Y"); + if (b1.__width != b_width) b1 = module->addPos(NEW_ID, b1, module->addWire(NEW_ID, b_width), b_signed)->connections.at("\\Y"); + if (b2.__width != b_width) b2 = module->addPos(NEW_ID, b2, module->addWire(NEW_ID, b_width), b_signed)->connections.at("\\Y"); RTLIL::SigSpec a = module->Mux(NEW_ID, a2, a1, act); RTLIL::SigSpec b = module->Mux(NEW_ID, b2, b1, act); @@ -405,8 +405,8 @@ struct ShareWorker supercell->connections["\\Y"] = y; supercell->check(); - RTLIL::SigSpec new_y1(y, y1.width); - RTLIL::SigSpec new_y2(y, y2.width); + RTLIL::SigSpec new_y1(y, y1.__width); + RTLIL::SigSpec new_y2(y, y2.__width); module->connections.push_back(RTLIL::SigSig(y1, new_y1)); module->connections.push_back(RTLIL::SigSig(y2, new_y2)); @@ -575,7 +575,7 @@ struct ShareWorker if (activation_patterns_cache[cell].empty()) { log("%sFound cell that is never activated: %s\n", indent, log_id(cell)); RTLIL::SigSpec cell_outputs = modwalker.cell_outputs[cell]; - module->connections.push_back(RTLIL::SigSig(cell_outputs, RTLIL::SigSpec(RTLIL::State::Sx, cell_outputs.width))); + module->connections.push_back(RTLIL::SigSig(cell_outputs, RTLIL::SigSpec(RTLIL::State::Sx, cell_outputs.__width))); cells_to_remove.insert(cell); } @@ -811,10 +811,10 @@ struct ShareWorker int other_cell_select_score = 0; for (auto &p : filtered_cell_activation_patterns) - cell_select_score += p.first.width; + cell_select_score += p.first.__width; for (auto &p : filtered_other_cell_activation_patterns) - other_cell_select_score += p.first.width; + other_cell_select_score += p.first.__width; RTLIL::Cell *supercell; if (cell_select_score <= other_cell_select_score) { diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index d2193c7b1..7e57aa0f5 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -133,8 +133,8 @@ namespace needleSig.expand(); haystackSig.expand(); - for (int i = 0; i < std::min(needleSig.width, haystackSig.width); i++) { - RTLIL::Wire *needleWire = needleSig.chunks.at(i).wire, *haystackWire = haystackSig.chunks.at(i).wire; + for (int i = 0; i < std::min(needleSig.__width, haystackSig.__width); i++) { + RTLIL::Wire *needleWire = needleSig.__chunks.at(i).wire, *haystackWire = haystackSig.__chunks.at(i).wire; if (needleWire != lastNeedleWire || haystackWire != lastHaystackWire) if (!compareAttributes(wire_attr, needleWire ? needleWire->attributes : emptyAttr, haystackWire ? haystackWire->attributes : emptyAttr)) return false; @@ -193,7 +193,7 @@ namespace RTLIL::SigSpec conn_sig = conn.second; sigmap.apply(conn_sig); conn_sig.expand(); - for (auto &chunk : conn_sig.chunks) + for (auto &chunk : conn_sig.__chunks) if (chunk.wire != NULL) sig_use_count[std::pair(chunk.wire, chunk.offset)]++; } @@ -213,7 +213,7 @@ namespace for (auto &conn : cell->connections) { - graph.createPort(cell->name, conn.first, conn.second.width); + graph.createPort(cell->name, conn.first, conn.second.__width); if (split && split->count(std::pair(cell->type, conn.first)) > 0) continue; @@ -222,9 +222,9 @@ namespace sigmap.apply(conn_sig); conn_sig.expand(); - for (size_t i = 0; i < conn_sig.chunks.size(); i++) + for (size_t i = 0; i < conn_sig.__chunks.size(); i++) { - auto &chunk = conn_sig.chunks[i]; + auto &chunk = conn_sig.__chunks[i]; assert(chunk.width == 1); if (chunk.wire == NULL) { @@ -269,7 +269,7 @@ namespace sigmap.apply(conn_sig); conn_sig.expand(); - for (auto &chunk : conn_sig.chunks) + for (auto &chunk : conn_sig.__chunks) if (sig_bit_ref.count(chunk) != 0) { bit_ref_t &bit_ref = sig_bit_ref[chunk]; graph.markExtern(bit_ref.cell, bit_ref.port, bit_ref.bit); @@ -287,7 +287,7 @@ namespace sigmap.apply(conn_sig); conn_sig.expand(); - for (auto &chunk : conn_sig.chunks) + for (auto &chunk : conn_sig.__chunks) if (sig_bit_ref.count(chunk) != 0) { bit_ref_t &bit_ref = sig_bit_ref[chunk]; graph.markExtern(bit_ref.cell, bit_ref.port, bit_ref.bit); @@ -334,8 +334,8 @@ namespace RTLIL::SigSpec sig = sigmap(conn.second); if (mapping.portMapping.count(conn.first) > 0 && sig2port.has(sigmap(sig))) { sig.expand(); - for (int i = 0; i < sig.width; i++) - for (auto &port : sig2port.find(sig.chunks[i])) { + for (int i = 0; i < sig.__width; i++) + for (auto &port : sig2port.find(sig.__chunks[i])) { RTLIL::SigSpec bitsig = haystack_cell->connections.at(mapping.portMapping[conn.first]).extract(i, 1); cell->connections.at(port.first).replace(port.second, bitsig); } @@ -729,7 +729,7 @@ struct ExtractPass : public Pass { for (auto cell : cells) for (auto &conn : cell->connections) { RTLIL::SigSpec sig = sigmap(conn.second); - for (auto &chunk : sig.chunks) + for (auto &chunk : sig.__chunks) if (chunk.wire != NULL) wires.insert(chunk.wire); } @@ -756,7 +756,7 @@ struct ExtractPass : public Pass { newCell->parameters = cell->parameters; for (auto &conn : cell->connections) { RTLIL::SigSpec sig = sigmap(conn.second); - for (auto &chunk : sig.chunks) + for (auto &chunk : sig.__chunks) if (chunk.wire != NULL) chunk.wire = newMod->wires.at(chunk.wire->name); newCell->connections[conn.first] = sig; diff --git a/passes/techmap/hilomap.cc b/passes/techmap/hilomap.cc index d24f557e2..22f4c7d1d 100644 --- a/passes/techmap/hilomap.cc +++ b/passes/techmap/hilomap.cc @@ -31,7 +31,7 @@ static RTLIL::SigChunk last_hi, last_lo; void hilomap_worker(RTLIL::SigSpec &sig) { sig.expand(); - for (auto &c : sig.chunks) { + for (auto &c : sig.__chunks) { if (c.wire == NULL && (c.data.bits.at(0) == RTLIL::State::S1) && !hicell_celltype.empty()) { if (!singleton_mode || last_hi.width == 0) { last_hi = RTLIL::SigChunk(module->addWire(NEW_ID)); diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc index 91f3b6124..cef5cc89e 100644 --- a/passes/techmap/simplemap.cc +++ b/passes/techmap/simplemap.cc @@ -42,8 +42,8 @@ static void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::Cell *gate = new RTLIL::Cell; gate->name = NEW_ID; gate->type = "$_INV_"; - gate->connections["\\A"] = sig_a.chunks.at(i); - gate->connections["\\Y"] = sig_y.chunks.at(i); + gate->connections["\\A"] = sig_a.__chunks.at(i); + gate->connections["\\Y"] = sig_y.__chunks.at(i); module->add(gate); } } @@ -96,8 +96,8 @@ static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::Cell *gate = new RTLIL::Cell; gate->name = NEW_ID; gate->type = "$_INV_"; - gate->connections["\\A"] = sig_t.chunks.at(i); - gate->connections["\\Y"] = sig_y.chunks.at(i); + gate->connections["\\A"] = sig_t.__chunks.at(i); + gate->connections["\\Y"] = sig_y.__chunks.at(i); module->add(gate); } @@ -115,9 +115,9 @@ static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::Cell *gate = new RTLIL::Cell; gate->name = NEW_ID; gate->type = gate_type; - gate->connections["\\A"] = sig_a.chunks.at(i); - gate->connections["\\B"] = sig_b.chunks.at(i); - gate->connections["\\Y"] = sig_y.chunks.at(i); + gate->connections["\\A"] = sig_a.__chunks.at(i); + gate->connections["\\B"] = sig_b.__chunks.at(i); + gate->connections["\\Y"] = sig_y.__chunks.at(i); module->add(gate); } } @@ -129,20 +129,20 @@ static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::SigSpec sig_y = cell->connections.at("\\Y"); - if (sig_y.width == 0) + if (sig_y.__width == 0) return; - if (sig_a.width == 0) { - if (cell->type == "$reduce_and") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.width))); - if (cell->type == "$reduce_or") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.width))); - if (cell->type == "$reduce_xor") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.width))); - if (cell->type == "$reduce_xnor") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.width))); - if (cell->type == "$reduce_bool") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.width))); + if (sig_a.__width == 0) { + if (cell->type == "$reduce_and") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.__width))); + if (cell->type == "$reduce_or") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.__width))); + if (cell->type == "$reduce_xor") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.__width))); + if (cell->type == "$reduce_xnor") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.__width))); + if (cell->type == "$reduce_bool") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.__width))); return; } - if (sig_y.width > 1) { - module->connections.push_back(RTLIL::SigSig(sig_y.extract(1, sig_y.width-1), RTLIL::SigSpec(0, sig_y.width-1))); + if (sig_y.__width > 1) { + module->connections.push_back(RTLIL::SigSig(sig_y.extract(1, sig_y.__width-1), RTLIL::SigSpec(0, sig_y.__width-1))); sig_y = sig_y.extract(0, 1); } @@ -156,24 +156,24 @@ static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::SigSpec *last_output = NULL; - while (sig_a.width > 1) + while (sig_a.__width > 1) { - RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig_a.width / 2); + RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig_a.__width / 2); sig_t.expand(); - for (int i = 0; i < sig_a.width; i += 2) + for (int i = 0; i < sig_a.__width; i += 2) { - if (i+1 == sig_a.width) { - sig_t.append(sig_a.chunks.at(i)); + if (i+1 == sig_a.__width) { + sig_t.append(sig_a.__chunks.at(i)); continue; } RTLIL::Cell *gate = new RTLIL::Cell; gate->name = NEW_ID; gate->type = gate_type; - gate->connections["\\A"] = sig_a.chunks.at(i); - gate->connections["\\B"] = sig_a.chunks.at(i+1); - gate->connections["\\Y"] = sig_t.chunks.at(i/2); + gate->connections["\\A"] = sig_a.__chunks.at(i); + gate->connections["\\B"] = sig_a.__chunks.at(i+1); + gate->connections["\\Y"] = sig_t.__chunks.at(i/2); last_output = &gate->connections["\\Y"]; module->add(gate); } @@ -204,31 +204,31 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig) { sig.expand(); - while (sig.width > 1) + while (sig.__width > 1) { - RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig.width / 2); + RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig.__width / 2); sig_t.expand(); - for (int i = 0; i < sig.width; i += 2) + for (int i = 0; i < sig.__width; i += 2) { - if (i+1 == sig.width) { - sig_t.append(sig.chunks.at(i)); + if (i+1 == sig.__width) { + sig_t.append(sig.__chunks.at(i)); continue; } RTLIL::Cell *gate = new RTLIL::Cell; gate->name = NEW_ID; gate->type = "$_OR_"; - gate->connections["\\A"] = sig.chunks.at(i); - gate->connections["\\B"] = sig.chunks.at(i+1); - gate->connections["\\Y"] = sig_t.chunks.at(i/2); + gate->connections["\\A"] = sig.__chunks.at(i); + gate->connections["\\B"] = sig.__chunks.at(i+1); + gate->connections["\\Y"] = sig_t.__chunks.at(i/2); module->add(gate); } sig = sig_t; } - if (sig.width == 0) + if (sig.__width == 0) sig = RTLIL::SigSpec(0, 1); } @@ -239,11 +239,11 @@ static void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::SigSpec sig_y = cell->connections.at("\\Y"); - if (sig_y.width == 0) + if (sig_y.__width == 0) return; - if (sig_y.width > 1) { - module->connections.push_back(RTLIL::SigSig(sig_y.extract(1, sig_y.width-1), RTLIL::SigSpec(0, sig_y.width-1))); + if (sig_y.__width > 1) { + module->connections.push_back(RTLIL::SigSig(sig_y.extract(1, sig_y.__width-1), RTLIL::SigSpec(0, sig_y.__width-1))); sig_y = sig_y.extract(0, 1); } @@ -265,11 +265,11 @@ static void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::SigSpec sig_y = cell->connections.at("\\Y"); - if (sig_y.width == 0) + if (sig_y.__width == 0) return; - if (sig_y.width > 1) { - module->connections.push_back(RTLIL::SigSig(sig_y.extract(1, sig_y.width-1), RTLIL::SigSpec(0, sig_y.width-1))); + if (sig_y.__width > 1) { + module->connections.push_back(RTLIL::SigSig(sig_y.extract(1, sig_y.__width-1), RTLIL::SigSpec(0, sig_y.__width-1))); sig_y = sig_y.extract(0, 1); } @@ -304,10 +304,10 @@ static void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::Cell *gate = new RTLIL::Cell; gate->name = NEW_ID; gate->type = "$_MUX_"; - gate->connections["\\A"] = sig_a.chunks.at(i); - gate->connections["\\B"] = sig_b.chunks.at(i); + gate->connections["\\A"] = sig_a.__chunks.at(i); + gate->connections["\\B"] = sig_b.__chunks.at(i); gate->connections["\\S"] = cell->connections.at("\\S"); - gate->connections["\\Y"] = sig_y.chunks.at(i); + gate->connections["\\Y"] = sig_y.__chunks.at(i); module->add(gate); } } @@ -317,7 +317,7 @@ static void simplemap_slice(RTLIL::Module *module, RTLIL::Cell *cell) int offset = cell->parameters.at("\\OFFSET").as_int(); RTLIL::SigSpec sig_a = cell->connections.at("\\A"); RTLIL::SigSpec sig_y = cell->connections.at("\\Y"); - module->connections.push_back(RTLIL::SigSig(sig_y, sig_a.extract(offset, sig_y.width))); + module->connections.push_back(RTLIL::SigSig(sig_y, sig_a.extract(offset, sig_y.__width))); } static void simplemap_concat(RTLIL::Module *module, RTLIL::Cell *cell) @@ -349,9 +349,9 @@ static void simplemap_sr(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::Cell *gate = new RTLIL::Cell; gate->name = NEW_ID; gate->type = gate_type; - gate->connections["\\S"] = sig_s.chunks.at(i); - gate->connections["\\R"] = sig_r.chunks.at(i); - gate->connections["\\Q"] = sig_q.chunks.at(i); + gate->connections["\\S"] = sig_s.__chunks.at(i); + gate->connections["\\R"] = sig_r.__chunks.at(i); + gate->connections["\\Q"] = sig_q.__chunks.at(i); module->add(gate); } } @@ -376,8 +376,8 @@ static void simplemap_dff(RTLIL::Module *module, RTLIL::Cell *cell) gate->name = NEW_ID; gate->type = gate_type; gate->connections["\\C"] = sig_clk; - gate->connections["\\D"] = sig_d.chunks.at(i); - gate->connections["\\Q"] = sig_q.chunks.at(i); + gate->connections["\\D"] = sig_d.__chunks.at(i); + gate->connections["\\Q"] = sig_q.__chunks.at(i); module->add(gate); } } @@ -410,10 +410,10 @@ static void simplemap_dffsr(RTLIL::Module *module, RTLIL::Cell *cell) gate->name = NEW_ID; gate->type = gate_type; gate->connections["\\C"] = sig_clk; - gate->connections["\\S"] = sig_s.chunks.at(i); - gate->connections["\\R"] = sig_r.chunks.at(i); - gate->connections["\\D"] = sig_d.chunks.at(i); - gate->connections["\\Q"] = sig_q.chunks.at(i); + gate->connections["\\S"] = sig_s.__chunks.at(i); + gate->connections["\\R"] = sig_r.__chunks.at(i); + gate->connections["\\D"] = sig_d.__chunks.at(i); + gate->connections["\\Q"] = sig_q.__chunks.at(i); module->add(gate); } } @@ -446,8 +446,8 @@ static void simplemap_adff(RTLIL::Module *module, RTLIL::Cell *cell) gate->type = rst_val.at(i) == RTLIL::State::S1 ? gate_type_1 : gate_type_0; gate->connections["\\C"] = sig_clk; gate->connections["\\R"] = sig_rst; - gate->connections["\\D"] = sig_d.chunks.at(i); - gate->connections["\\Q"] = sig_q.chunks.at(i); + gate->connections["\\D"] = sig_d.__chunks.at(i); + gate->connections["\\Q"] = sig_q.__chunks.at(i); module->add(gate); } } @@ -472,8 +472,8 @@ static void simplemap_dlatch(RTLIL::Module *module, RTLIL::Cell *cell) gate->name = NEW_ID; gate->type = gate_type; gate->connections["\\E"] = sig_en; - gate->connections["\\D"] = sig_d.chunks.at(i); - gate->connections["\\Q"] = sig_q.chunks.at(i); + gate->connections["\\D"] = sig_d.__chunks.at(i); + gate->connections["\\Q"] = sig_q.__chunks.at(i); module->add(gate); } } diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 3ceff279b..f7d5efa0a 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -41,13 +41,13 @@ static void apply_prefix(std::string prefix, std::string &id) static void apply_prefix(std::string prefix, RTLIL::SigSpec &sig, RTLIL::Module *module) { - for (size_t i = 0; i < sig.chunks.size(); i++) { - if (sig.chunks[i].wire == NULL) + for (size_t i = 0; i < sig.__chunks.size(); i++) { + if (sig.__chunks[i].wire == NULL) continue; - std::string wire_name = sig.chunks[i].wire->name; + std::string wire_name = sig.__chunks[i].wire->name; apply_prefix(prefix, wire_name); assert(module->wires.count(wire_name) > 0); - sig.chunks[i].wire = module->wires[wire_name]; + sig.__chunks[i].wire = module->wires[wire_name]; } } @@ -163,11 +163,11 @@ struct TechmapWorker c.second = it.second; apply_prefix(cell->name, c.first, module); } - if (c.second.width > c.first.width) - c.second.remove(c.first.width, c.second.width - c.first.width); - if (c.second.width < c.first.width) - c.second.append(RTLIL::SigSpec(RTLIL::State::S0, c.first.width - c.second.width)); - assert(c.first.width == c.second.width); + if (c.second.__width > c.first.__width) + c.second.remove(c.first.__width, c.second.__width - c.first.__width); + if (c.second.__width < c.first.__width) + c.second.append(RTLIL::SigSpec(RTLIL::State::S0, c.first.__width - c.second.__width)); + assert(c.first.__width == c.second.__width); if (flatten_mode) { // more conservative approach: // connect internal and external wires -- cgit v1.2.3 From 4b4048bc5feba1ab05c7a63f12c0a17879cb7e04 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 22 Jul 2014 20:15:14 +0200 Subject: SigSpec refactoring: using the accessor functions everywhere --- passes/abc/abc.cc | 68 ++++++++++++------------ passes/abc/blifparse.cc | 10 ++-- passes/cmds/connect.cc | 2 +- passes/cmds/connwrappers.cc | 8 +-- passes/cmds/delete.cc | 2 +- passes/cmds/scatter.cc | 2 +- passes/cmds/scc.cc | 2 +- passes/cmds/select.cc | 2 +- passes/cmds/setundef.cc | 4 +- passes/cmds/show.cc | 34 ++++++------ passes/cmds/splice.cc | 18 +++---- passes/cmds/splitnets.cc | 4 +- passes/fsm/fsm_detect.cc | 4 +- passes/fsm/fsm_expand.cc | 18 +++---- passes/fsm/fsm_extract.cc | 38 +++++++------- passes/fsm/fsm_map.cc | 30 +++++------ passes/fsm/fsm_opt.cc | 18 +++---- passes/fsm/fsmdata.h | 8 +-- passes/hierarchy/hierarchy.cc | 4 +- passes/hierarchy/submod.cc | 4 +- passes/memory/memory_collect.cc | 32 ++++++------ passes/memory/memory_dff.cc | 12 ++--- passes/memory/memory_map.cc | 8 +-- passes/memory/memory_share.cc | 12 ++--- passes/opt/opt_clean.cc | 28 +++++----- passes/opt/opt_const.cc | 92 ++++++++++++++++----------------- passes/opt/opt_muxtree.cc | 14 ++--- passes/opt/opt_reduce.cc | 28 +++++----- passes/opt/opt_rmdff.cc | 14 ++--- passes/opt/opt_share.cc | 2 +- passes/proc/proc_arst.cc | 18 +++---- passes/proc/proc_clean.cc | 8 +-- passes/proc/proc_dff.cc | 82 ++++++++++++++--------------- passes/proc/proc_init.cc | 12 ++--- passes/proc/proc_mux.cc | 44 ++++++++-------- passes/sat/eval.cc | 66 +++++++++++------------ passes/sat/expose.cc | 2 +- passes/sat/freduce.cc | 2 +- passes/sat/miter.cc | 8 +-- passes/sat/sat.cc | 46 ++++++++--------- passes/sat/share.cc | 44 ++++++++-------- passes/techmap/extract.cc | 24 ++++----- passes/techmap/hilomap.cc | 2 +- passes/techmap/simplemap.cc | 112 ++++++++++++++++++++-------------------- passes/techmap/techmap.cc | 18 +++---- 45 files changed, 505 insertions(+), 505 deletions(-) (limited to 'passes') diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index e21be30b8..2d921b7be 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -69,8 +69,8 @@ static RTLIL::SigSpec clk_sig; static int map_signal(RTLIL::SigSpec sig, char gate_type = -1, int in1 = -1, int in2 = -1, int in3 = -1) { - assert(sig.__width == 1); - assert(sig.__chunks.size() == 1); + assert(sig.size() == 1); + assert(sig.chunks().size() == 1); assign_map.apply(sig); @@ -105,7 +105,7 @@ static void mark_port(RTLIL::SigSpec sig) { assign_map.apply(sig); sig.expand(); - for (auto &c : sig.__chunks) { + for (auto &c : sig.chunks()) { if (c.wire != NULL && signal_map.count(c) > 0) signal_list[signal_map[c]].is_port = true; } @@ -124,7 +124,7 @@ static void extract_cell(RTLIL::Cell *cell, bool keepff) RTLIL::SigSpec sig_q = cell->connections["\\Q"]; if (keepff) - for (auto &c : sig_q.__chunks) + for (auto &c : sig_q.chunks()) if (c.wire != NULL) c.wire->attributes["\\keep"] = 1; @@ -300,8 +300,8 @@ static void handle_loops() for (auto &edge_it : edges) { int id2 = edge_it.first; - RTLIL::Wire *w1 = signal_list[id1].sig.__chunks[0].wire; - RTLIL::Wire *w2 = signal_list[id2].sig.__chunks[0].wire; + RTLIL::Wire *w1 = signal_list[id1].sig.chunks()[0].wire; + RTLIL::Wire *w2 = signal_list[id2].sig.chunks()[0].wire; if (w1 != NULL) continue; else if (w2 == NULL) @@ -469,7 +469,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std clk_sig = assign_map(RTLIL::SigSpec(module->wires.at(RTLIL::escape_id(clk_str)), 1)); } - if (dff_mode && clk_sig.__width == 0) + if (dff_mode && clk_sig.size() == 0) { int best_dff_counter = 0; std::map, int> dff_counters; @@ -490,13 +490,13 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std } if (dff_mode || !clk_str.empty()) { - if (clk_sig.__width == 0) + if (clk_sig.size() == 0) log("No (matching) clock domain found. Not extracting any FF cells.\n"); else log("Found (matching) %s clock domain: %s\n", clk_polarity ? "posedge" : "negedge", log_signal(clk_sig)); } - if (clk_sig.__width != 0) + if (clk_sig.size() != 0) mark_port(clk_sig); std::vector cells; @@ -552,10 +552,10 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std fprintf(f, "# n%-5d %s\n", si.id, log_signal(si.sig)); for (auto &si : signal_list) { - assert(si.sig.__width == 1 && si.sig.__chunks.size() == 1); - if (si.sig.__chunks[0].wire == NULL) { + assert(si.sig.size() == 1 && si.sig.chunks().size() == 1); + if (si.sig.chunks()[0].wire == NULL) { fprintf(f, ".names n%d\n", si.id); - if (si.sig.__chunks[0].data.bits[0] == RTLIL::State::S1) + if (si.sig.chunks()[0].data.bits[0] == RTLIL::State::S1) fprintf(f, "1\n"); } } @@ -716,15 +716,15 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std cell_stats[RTLIL::unescape_id(c->type)]++; if (c->type == "\\ZERO" || c->type == "\\ONE") { RTLIL::SigSig conn; - conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].__chunks[0].wire->name)]); + conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].chunks()[0].wire->name)]); conn.second = RTLIL::SigSpec(c->type == "\\ZERO" ? 0 : 1, 1); module->connections.push_back(conn); continue; } if (c->type == "\\BUF") { RTLIL::SigSig conn; - conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].__chunks[0].wire->name)]); - conn.second = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].__chunks[0].wire->name)]); + conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].chunks()[0].wire->name)]); + conn.second = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].chunks()[0].wire->name)]); module->connections.push_back(conn); continue; } @@ -732,8 +732,8 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std RTLIL::Cell *cell = new RTLIL::Cell; cell->type = "$_INV_"; cell->name = remap_name(c->name); - cell->connections["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].__chunks[0].wire->name)]); - cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].__chunks[0].wire->name)]); + cell->connections["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].chunks()[0].wire->name)]); + cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].chunks()[0].wire->name)]); module->cells[cell->name] = cell; design->select(module, cell); continue; @@ -742,9 +742,9 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std RTLIL::Cell *cell = new RTLIL::Cell; cell->type = "$_" + c->type.substr(1) + "_"; cell->name = remap_name(c->name); - cell->connections["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].__chunks[0].wire->name)]); - cell->connections["\\B"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\B"].__chunks[0].wire->name)]); - cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].__chunks[0].wire->name)]); + cell->connections["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].chunks()[0].wire->name)]); + cell->connections["\\B"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\B"].chunks()[0].wire->name)]); + cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].chunks()[0].wire->name)]); module->cells[cell->name] = cell; design->select(module, cell); continue; @@ -753,21 +753,21 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std RTLIL::Cell *cell = new RTLIL::Cell; cell->type = "$_MUX_"; cell->name = remap_name(c->name); - cell->connections["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].__chunks[0].wire->name)]); - cell->connections["\\B"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\B"].__chunks[0].wire->name)]); - cell->connections["\\S"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\S"].__chunks[0].wire->name)]); - cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].__chunks[0].wire->name)]); + cell->connections["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].chunks()[0].wire->name)]); + cell->connections["\\B"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\B"].chunks()[0].wire->name)]); + cell->connections["\\S"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\S"].chunks()[0].wire->name)]); + cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].chunks()[0].wire->name)]); module->cells[cell->name] = cell; design->select(module, cell); continue; } if (c->type == "\\DFF") { - log_assert(clk_sig.__width == 1); + log_assert(clk_sig.size() == 1); RTLIL::Cell *cell = new RTLIL::Cell; cell->type = clk_polarity ? "$_DFF_P_" : "$_DFF_N_"; cell->name = remap_name(c->name); - cell->connections["\\D"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\D"].__chunks[0].wire->name)]); - cell->connections["\\Q"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Q"].__chunks[0].wire->name)]); + cell->connections["\\D"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\D"].chunks()[0].wire->name)]); + cell->connections["\\Q"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Q"].chunks()[0].wire->name)]); cell->connections["\\C"] = clk_sig; module->cells[cell->name] = cell; design->select(module, cell); @@ -784,18 +784,18 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std cell_stats[RTLIL::unescape_id(c->type)]++; if (c->type == "\\_const0_" || c->type == "\\_const1_") { RTLIL::SigSig conn; - conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections.begin()->second.__chunks[0].wire->name)]); + conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections.begin()->second.chunks()[0].wire->name)]); conn.second = RTLIL::SigSpec(c->type == "\\_const0_" ? 0 : 1, 1); module->connections.push_back(conn); continue; } if (c->type == "\\_dff_") { - log_assert(clk_sig.__width == 1); + log_assert(clk_sig.size() == 1); RTLIL::Cell *cell = new RTLIL::Cell; cell->type = clk_polarity ? "$_DFF_P_" : "$_DFF_N_"; cell->name = remap_name(c->name); - cell->connections["\\D"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\D"].__chunks[0].wire->name)]); - cell->connections["\\Q"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Q"].__chunks[0].wire->name)]); + cell->connections["\\D"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\D"].chunks()[0].wire->name)]); + cell->connections["\\Q"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Q"].chunks()[0].wire->name)]); cell->connections["\\C"] = clk_sig; module->cells[cell->name] = cell; design->select(module, cell); @@ -807,7 +807,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std cell->name = remap_name(c->name); for (auto &conn : c->connections) { RTLIL::SigSpec newsig; - for (auto &c : conn.second.__chunks) { + for (auto &c : conn.second.chunks()) { if (c.width == 0) continue; assert(c.width == 1); @@ -822,9 +822,9 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std for (auto conn : mapped_mod->connections) { if (!conn.first.is_fully_const()) - conn.first = RTLIL::SigSpec(module->wires[remap_name(conn.first.__chunks[0].wire->name)]); + conn.first = RTLIL::SigSpec(module->wires[remap_name(conn.first.chunks()[0].wire->name)]); if (!conn.second.is_fully_const()) - conn.second = RTLIL::SigSpec(module->wires[remap_name(conn.second.__chunks[0].wire->name)]); + conn.second = RTLIL::SigSpec(module->wires[remap_name(conn.second.chunks()[0].wire->name)]); module->connections.push_back(conn); } diff --git a/passes/abc/blifparse.cc b/passes/abc/blifparse.cc index 65ebe541d..47fa0f821 100644 --- a/passes/abc/blifparse.cc +++ b/passes/abc/blifparse.cc @@ -177,10 +177,10 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name) } input_sig.append(wire); } - output_sig = input_sig.extract(input_sig.__width-1, 1); - input_sig = input_sig.extract(0, input_sig.__width-1); + output_sig = input_sig.extract(input_sig.size()-1, 1); + input_sig = input_sig.extract(0, input_sig.size()-1); - if (input_sig.__width == 0) { + if (input_sig.size() == 0) { RTLIL::State state = RTLIL::State::Sa; while (1) { if (!read_next_line(buffer, buffer_size, line_count, f)) @@ -218,8 +218,8 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name) RTLIL::Cell *cell = new RTLIL::Cell; cell->name = NEW_ID; cell->type = "$lut"; - cell->parameters["\\WIDTH"] = RTLIL::Const(input_sig.__width); - cell->parameters["\\LUT"] = RTLIL::Const(RTLIL::State::Sx, 1 << input_sig.__width); + cell->parameters["\\WIDTH"] = RTLIL::Const(input_sig.size()); + cell->parameters["\\LUT"] = RTLIL::Const(RTLIL::State::Sx, 1 << input_sig.size()); cell->connections["\\I"] = input_sig; cell->connections["\\O"] = output_sig; lutptr = &cell->parameters.at("\\LUT"); diff --git a/passes/cmds/connect.cc b/passes/cmds/connect.cc index f8f9e0590..dcd5fc96b 100644 --- a/passes/cmds/connect.cc +++ b/passes/cmds/connect.cc @@ -27,7 +27,7 @@ static void unset_drivers(RTLIL::Design *design, RTLIL::Module *module, SigMap & { CellTypes ct(design); - RTLIL::Wire *dummy_wire = module->addWire(NEW_ID, sig.__width); + RTLIL::Wire *dummy_wire = module->addWire(NEW_ID, sig.size()); for (auto &it : module->cells) for (auto &port : it.second->connections) diff --git a/passes/cmds/connwrappers.cc b/passes/cmds/connwrappers.cc index 426d2b624..6cb2a892c 100644 --- a/passes/cmds/connwrappers.cc +++ b/passes/cmds/connwrappers.cc @@ -90,7 +90,7 @@ struct ConnwrappersWorker continue; int inner_width = cell->parameters.at(decl.widthparam).as_int(); - int outer_width = conn.second.__width; + int outer_width = conn.second.size(); bool is_signed = decl.signparam.empty() ? decl.is_signed : cell->parameters.at(decl.signparam).as_bool(); if (inner_width >= outer_width) @@ -124,20 +124,20 @@ struct ConnwrappersWorker int extend_width = 0; RTLIL::SigBit extend_bit = is_signed ? sigbits[i] : RTLIL::SigBit(RTLIL::State::S0); - while (extend_width < extend_sig.__width && i + extend_width + 1 < sigbits.size() && + while (extend_width < extend_sig.size() && i + extend_width + 1 < sigbits.size() && sigbits[i + extend_width + 1] == extend_bit) extend_width++; if (extend_width == 0) continue; - if (old_sig.__width == 0) + if (old_sig.size() == 0) old_sig = conn.second; conn.second.replace(i+1, extend_sig.extract(0, extend_width)); i += extend_width; } - if (old_sig.__width) + if (old_sig.size()) log("Connected extended bits of %s.%s:%s: %s -> %s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(conn.first), log_signal(old_sig), log_signal(conn.second)); } diff --git a/passes/cmds/delete.cc b/passes/cmds/delete.cc index 16828e4fb..c5aa196c6 100644 --- a/passes/cmds/delete.cc +++ b/passes/cmds/delete.cc @@ -28,7 +28,7 @@ struct DeleteWireWorker void operator()(RTLIL::SigSpec &sig) { sig.optimize(); - for (auto &c : sig.__chunks) + for (auto &c : sig.chunks()) if (c.wire != NULL && delete_wires_p->count(c.wire->name)) { c.wire = module->addWire(NEW_ID, c.width); c.offset = 0; diff --git a/passes/cmds/scatter.cc b/passes/cmds/scatter.cc index da36c7821..d5976dcb0 100644 --- a/passes/cmds/scatter.cc +++ b/passes/cmds/scatter.cc @@ -53,7 +53,7 @@ struct ScatterPass : public Pass { { RTLIL::Wire *wire = new RTLIL::Wire; wire->name = NEW_ID; - wire->width = p.second.__width; + wire->width = p.second.size(); mod_it.second->add(wire); if (ct.cell_output(c.second->type, p.first)) { diff --git a/passes/cmds/scc.cc b/passes/cmds/scc.cc index d668bc3a4..49e79bd4d 100644 --- a/passes/cmds/scc.cc +++ b/passes/cmds/scc.cc @@ -191,7 +191,7 @@ struct SccWorker nextsig.sort_and_unify(); sig = prevsig.extract(nextsig); - for (auto &chunk : sig.__chunks) + for (auto &chunk : sig.chunks()) if (chunk.wire != NULL) sel.selected_members[module->name].insert(chunk.wire->name); } diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index 068162eb1..123483a3a 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -415,7 +415,7 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v include_match: is_input = mode == 'x' || ct.cell_input(cell.second->type, conn.first); is_output = mode == 'x' || ct.cell_output(cell.second->type, conn.first); - for (auto &chunk : conn.second.__chunks) + for (auto &chunk : conn.second.chunks()) if (chunk.wire != NULL) { if (max_objects != 0 && selected_wires.count(chunk.wire) > 0 && lhs.selected_members[mod->name].count(cell.first) == 0) if (mode == 'x' || (mode == 'i' && is_output) || (mode == 'o' && is_input)) diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index 3a99c0cec..7558a4e9a 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -48,7 +48,7 @@ struct SetundefWorker void operator()(RTLIL::SigSpec &sig) { sig.expand(); - for (auto &c : sig.__chunks) + for (auto &c : sig.chunks()) if (c.wire == NULL && c.data.bits.at(0) > RTLIL::State::S1) c.data.bits.at(0) = next_bit(); sig.optimize(); @@ -141,7 +141,7 @@ struct SetundefPass : public Pass { undriven_signals.del(sigmap(conn.second)); RTLIL::SigSpec sig = undriven_signals.export_all(); - for (auto &c : sig.__chunks) { + for (auto &c : sig.chunks()) { RTLIL::SigSpec bits; for (int i = 0; i < c.width; i++) bits.append(next_bit()); diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index 0006a3ff4..fde96d537 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -78,7 +78,7 @@ struct ShowWorker std::string nextColor(RTLIL::SigSpec sig, std::string defaultColor) { sig.sort_and_unify(); - for (auto &c : sig.__chunks) { + for (auto &c : sig.chunks()) { if (c.wire != NULL) for (auto &s : color_selections) if (s.second.selected_members.count(module->name) > 0 && s.second.selected_members.at(module->name).count(c.wire->name) > 0) @@ -173,13 +173,13 @@ struct ShowWorker { sig.optimize(); - if (sig.__chunks.size() == 0) { + if (sig.chunks().size() == 0) { fprintf(f, "v%d [ label=\"\" ];\n", single_idx_count); return stringf("v%d", single_idx_count++); } - if (sig.__chunks.size() == 1) { - RTLIL::SigChunk &c = sig.__chunks[0]; + if (sig.chunks().size() == 1) { + RTLIL::SigChunk &c = sig.chunks()[0]; if (c.wire != NULL && design->selected_member(module->name, c.wire->name)) { if (!range_check || c.wire->width == c.width) return stringf("n%d", id2num(c.wire->name)); @@ -200,10 +200,10 @@ struct ShowWorker { std::string label_string; sig.optimize(); - int pos = sig.__width-1; + int pos = sig.size()-1; int idx = single_idx_count++; - for (int i = int(sig.__chunks.size())-1; i >= 0; i--) { - RTLIL::SigChunk &c = sig.__chunks[i]; + for (int i = int(sig.chunks().size())-1; i >= 0; i--) { + RTLIL::SigChunk &c = sig.chunks()[i]; net = gen_signode_simple(c, false); assert(!net.empty()); if (driver) { @@ -225,9 +225,9 @@ struct ShowWorker if (!port.empty()) { currentColor = xorshift32(currentColor); if (driver) - code += stringf("%s:e -> x%d:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, %s, %s];\n", port.c_str(), idx, nextColor(sig).c_str(), widthLabel(sig.__width).c_str()); + code += stringf("%s:e -> x%d:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, %s, %s];\n", port.c_str(), idx, nextColor(sig).c_str(), widthLabel(sig.size()).c_str()); else - code += stringf("x%d:e -> %s:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, %s, %s];\n", idx, port.c_str(), nextColor(sig).c_str(), widthLabel(sig.__width).c_str()); + code += stringf("x%d:e -> %s:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, %s, %s];\n", idx, port.c_str(), nextColor(sig).c_str(), widthLabel(sig.size()).c_str()); } if (node != NULL) *node = stringf("x%d", idx); @@ -239,7 +239,7 @@ struct ShowWorker net_conn_map[net].in.insert(port); else net_conn_map[net].out.insert(port); - net_conn_map[net].bits = sig.__width; + net_conn_map[net].bits = sig.size(); net_conn_map[net].color = nextColor(sig, net_conn_map[net].color); } if (node != NULL) @@ -405,7 +405,7 @@ struct ShowWorker code += gen_portbox("", sig, false, &node); fprintf(f, "%s", code.c_str()); net_conn_map[node].out.insert(stringf("p%d", pidx)); - net_conn_map[node].bits = sig.__width; + net_conn_map[node].bits = sig.size(); net_conn_map[node].color = nextColor(sig, net_conn_map[node].color); } @@ -414,7 +414,7 @@ struct ShowWorker code += gen_portbox("", sig, true, &node); fprintf(f, "%s", code.c_str()); net_conn_map[node].in.insert(stringf("p%d", pidx)); - net_conn_map[node].bits = sig.__width; + net_conn_map[node].bits = sig.size(); net_conn_map[node].color = nextColor(sig, net_conn_map[node].color); } @@ -427,12 +427,12 @@ struct ShowWorker for (auto &conn : module->connections) { bool found_lhs_wire = false; - for (auto &c : conn.first.__chunks) { + for (auto &c : conn.first.chunks()) { if (c.wire == NULL || design->selected_member(module->name, c.wire->name)) found_lhs_wire = true; } bool found_rhs_wire = false; - for (auto &c : conn.second.__chunks) { + for (auto &c : conn.second.chunks()) { if (c.wire == NULL || design->selected_member(module->name, c.wire->name)) found_rhs_wire = true; } @@ -446,11 +446,11 @@ struct ShowWorker if (left_node[0] == 'x' && right_node[0] == 'x') { currentColor = xorshift32(currentColor); - fprintf(f, "%s:e -> %s:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, %s, %s];\n", left_node.c_str(), right_node.c_str(), nextColor(conn).c_str(), widthLabel(conn.first.__width).c_str()); + fprintf(f, "%s:e -> %s:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, %s, %s];\n", left_node.c_str(), right_node.c_str(), nextColor(conn).c_str(), widthLabel(conn.first.size()).c_str()); } else { - net_conn_map[right_node].bits = conn.first.__width; + net_conn_map[right_node].bits = conn.first.size(); net_conn_map[right_node].color = nextColor(conn, net_conn_map[right_node].color); - net_conn_map[left_node].bits = conn.first.__width; + net_conn_map[left_node].bits = conn.first.size(); net_conn_map[left_node].color = nextColor(conn, net_conn_map[left_node].color); if (left_node[0] == 'x') { net_conn_map[right_node].in.insert(left_node); diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc index 80a7f90c0..aed9c076e 100644 --- a/passes/cmds/splice.cc +++ b/passes/cmds/splice.cc @@ -52,7 +52,7 @@ struct SpliceWorker RTLIL::SigSpec get_sliced_signal(RTLIL::SigSpec sig) { - if (sig.__width == 0 || sig.is_fully_const()) + if (sig.size() == 0 || sig.is_fully_const()) return sig; if (sliced_signals_cache.count(sig)) @@ -69,15 +69,15 @@ struct SpliceWorker RTLIL::SigSpec new_sig = sig; - if (sig_a.__width != sig.__width) { + if (sig_a.size() != sig.size()) { RTLIL::Cell *cell = new RTLIL::Cell; cell->name = NEW_ID; cell->type = "$slice"; cell->parameters["\\OFFSET"] = offset; - cell->parameters["\\A_WIDTH"] = sig_a.__width; - cell->parameters["\\Y_WIDTH"] = sig.__width; + cell->parameters["\\A_WIDTH"] = sig_a.size(); + cell->parameters["\\Y_WIDTH"] = sig.size(); cell->connections["\\A"] = sig_a; - cell->connections["\\Y"] = module->addWire(NEW_ID, sig.__width); + cell->connections["\\Y"] = module->addWire(NEW_ID, sig.size()); new_sig = cell->connections["\\Y"]; module->add(cell); } @@ -90,7 +90,7 @@ struct SpliceWorker RTLIL::SigSpec get_spliced_signal(RTLIL::SigSpec sig) { - if (sig.__width == 0 || sig.is_fully_const()) + if (sig.size() == 0 || sig.is_fully_const()) return sig; if (spliced_signals_cache.count(sig)) @@ -134,11 +134,11 @@ struct SpliceWorker RTLIL::Cell *cell = new RTLIL::Cell; cell->name = NEW_ID; cell->type = "$concat"; - cell->parameters["\\A_WIDTH"] = new_sig.__width; - cell->parameters["\\B_WIDTH"] = sig2.__width; + cell->parameters["\\A_WIDTH"] = new_sig.size(); + cell->parameters["\\B_WIDTH"] = sig2.size(); cell->connections["\\A"] = new_sig; cell->connections["\\B"] = sig2; - cell->connections["\\Y"] = module->addWire(NEW_ID, new_sig.__width + sig2.__width); + cell->connections["\\Y"] = module->addWire(NEW_ID, new_sig.size() + sig2.size()); new_sig = cell->connections["\\Y"]; module->add(cell); } diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc index 7572baa35..8cc6a5152 100644 --- a/passes/cmds/splitnets.cc +++ b/passes/cmds/splitnets.cc @@ -63,7 +63,7 @@ struct SplitnetsWorker void operator()(RTLIL::SigSpec &sig) { sig.expand(); - for (auto &c : sig.__chunks) + for (auto &c : sig.chunks()) if (splitmap.count(c.wire) > 0) c = splitmap.at(c.wire).at(c.offset); sig.optimize(); @@ -144,7 +144,7 @@ struct SplitnetsPass : public Pass { continue; RTLIL::SigSpec sig = p.second.optimized(); - for (auto &chunk : sig.__chunks) { + for (auto &chunk : sig.chunks()) { if (chunk.wire == NULL) continue; if (chunk.wire->port_id == 0 || flag_ports) { diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc index 523feae92..2ba4c72b8 100644 --- a/passes/fsm/fsm_detect.cc +++ b/passes/fsm/fsm_detect.cc @@ -56,8 +56,8 @@ static bool check_state_mux_tree(RTLIL::SigSpec old_sig, RTLIL::SigSpec sig, Sig RTLIL::SigSpec sig_b = assign_map(cellport.first->connections["\\B"]); if (!check_state_mux_tree(old_sig, sig_a, recursion_monitor)) return false; - for (int i = 0; i < sig_b.__width; i += sig_a.__width) - if (!check_state_mux_tree(old_sig, sig_b.extract(i, sig_a.__width), recursion_monitor)) + for (int i = 0; i < sig_b.size(); i += sig_a.size()) + if (!check_state_mux_tree(old_sig, sig_b.extract(i, sig_a.size()), recursion_monitor)) return false; muxtree_cells.insert(cellport.first); } diff --git a/passes/fsm/fsm_expand.cc b/passes/fsm/fsm_expand.cc index e4d20077c..0dd328db3 100644 --- a/passes/fsm/fsm_expand.cc +++ b/passes/fsm/fsm_expand.cc @@ -43,7 +43,7 @@ struct FsmExpand bool is_cell_merge_candidate(RTLIL::Cell *cell) { if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux") - if (cell->connections.at("\\A").__width < 2) + if (cell->connections.at("\\A").size() < 2) return true; RTLIL::SigSpec new_signals; @@ -62,7 +62,7 @@ struct FsmExpand new_signals.remove(assign_map(fsm_cell->connections["\\CTRL_IN"])); new_signals.remove(assign_map(fsm_cell->connections["\\CTRL_OUT"])); - if (new_signals.__width > 3) + if (new_signals.size() > 3) return false; if (cell->connections.count("\\Y") > 0) { @@ -73,7 +73,7 @@ struct FsmExpand new_signals.remove(assign_map(fsm_cell->connections["\\CTRL_OUT"])); } - if (new_signals.__width > 2) + if (new_signals.size() > 2) return false; return true; @@ -145,8 +145,8 @@ struct FsmExpand std::vector truth_tab; - for (int i = 0; i < (1 << input_sig.__width); i++) { - RTLIL::Const in_val(i, input_sig.__width); + for (int i = 0; i < (1 << input_sig.size()); i++) { + RTLIL::Const in_val(i, input_sig.size()); RTLIL::SigSpec A, B, S; if (cell->connections.count("\\A") > 0) A = assign_map(cell->connections["\\A"]); @@ -166,17 +166,17 @@ struct FsmExpand FsmData fsm_data; fsm_data.copy_from_cell(fsm_cell); - fsm_data.num_inputs += input_sig.__width; + fsm_data.num_inputs += input_sig.size(); fsm_cell->connections["\\CTRL_IN"].append(input_sig); - fsm_data.num_outputs += output_sig.__width; + fsm_data.num_outputs += output_sig.size(); fsm_cell->connections["\\CTRL_OUT"].append(output_sig); std::vector new_transition_table; for (auto &tr : fsm_data.transition_table) { - for (int i = 0; i < (1 << input_sig.__width); i++) { + for (int i = 0; i < (1 << input_sig.size()); i++) { FsmData::transition_t new_tr = tr; - RTLIL::Const in_val(i, input_sig.__width); + RTLIL::Const in_val(i, input_sig.size()); RTLIL::Const out_val = truth_tab[i]; RTLIL::SigSpec ctrl_in = new_tr.ctrl_in; RTLIL::SigSpec ctrl_out = new_tr.ctrl_out; diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index c0b5857f0..701b09bd8 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -36,7 +36,7 @@ static SigSet sig2driver, sig2trigger; static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL::SigSpec &ctrl, std::map &states, RTLIL::Const *reset_state = NULL) { - sig.extend(dff_out.__width, false); + sig.extend(dff_out.size(), false); if (sig == dff_out) return true; @@ -44,10 +44,10 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL assign_map.apply(sig); if (sig.is_fully_const()) { sig.optimize(); - assert(sig.__chunks.size() == 1); - if (states.count(sig.__chunks[0].data) == 0) { + assert(sig.chunks().size() == 1); + if (states.count(sig.chunks()[0].data) == 0) { log(" found state code: %s\n", log_signal(sig)); - states[sig.__chunks[0].data] = -1; + states[sig.chunks()[0].data] = -1; } return true; } @@ -73,14 +73,14 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL break; log(" found reset state: %s (guessed from mux tree)\n", log_signal(*reset_state)); } while (0); - if (ctrl.extract(sig_s).__width == 0) { + if (ctrl.extract(sig_s).size() == 0) { log(" found ctrl input: %s\n", log_signal(sig_s)); ctrl.append(sig_s); } if (!find_states(sig_a, dff_out, ctrl, states)) return false; - for (int i = 0; i < sig_b.__width/sig_a.__width; i++) { - if (!find_states(sig_b.extract(i*sig_a.__width, sig_a.__width), dff_out, ctrl, states)) + for (int i = 0; i < sig_b.size()/sig_a.size(); i++) { + if (!find_states(sig_b.extract(i*sig_a.size(), sig_a.size()), dff_out, ctrl, states)) return false; } } @@ -90,11 +90,11 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL static RTLIL::Const sig2const(ConstEval &ce, RTLIL::SigSpec sig, RTLIL::State noconst_state, RTLIL::SigSpec dont_care = RTLIL::SigSpec()) { - if (dont_care.__width > 0) { + if (dont_care.size() > 0) { sig.expand(); - for (auto &chunk : sig.__chunks) { + for (auto &chunk : sig.chunks()) { assert(chunk.width == 1); - if (dont_care.extract(chunk).__width > 0) + if (dont_care.extract(chunk).size() > 0) chunk.wire = NULL, chunk.data = RTLIL::Const(noconst_state); } sig.optimize(); @@ -104,17 +104,17 @@ static RTLIL::Const sig2const(ConstEval &ce, RTLIL::SigSpec sig, RTLIL::State no ce.values_map.apply(sig); sig.expand(); - for (auto &chunk : sig.__chunks) { + for (auto &chunk : sig.chunks()) { assert(chunk.width == 1); if (chunk.wire != NULL) chunk.wire = NULL, chunk.data = RTLIL::Const(noconst_state); } sig.optimize(); - if (sig.__width == 0) + if (sig.size() == 0) return RTLIL::Const(); - assert(sig.__chunks.size() == 1 && sig.__chunks[0].wire == NULL); - return sig.__chunks[0].data; + assert(sig.chunks().size() == 1 && sig.chunks()[0].wire == NULL); + return sig.chunks()[0].data; } static void find_transitions(ConstEval &ce, ConstEval &ce_nostop, FsmData &fsm_data, std::map &states, int state_in, RTLIL::SigSpec ctrl_in, RTLIL::SigSpec ctrl_out, RTLIL::SigSpec dff_in, RTLIL::SigSpec dont_care) @@ -144,7 +144,7 @@ static void find_transitions(ConstEval &ce, ConstEval &ce_nostop, FsmData &fsm_d return; } - log_assert(undef.__width > 0); + log_assert(undef.size() > 0); log_assert(ce.stop_signals.check_all(undef)); undef = undef.extract(0, 1); @@ -258,8 +258,8 @@ static void extract_fsm(RTLIL::Wire *wire) // Initialize fsm data struct FsmData fsm_data; - fsm_data.num_inputs = ctrl_in.__width; - fsm_data.num_outputs = ctrl_out.__width; + fsm_data.num_inputs = ctrl_in.size(); + fsm_data.num_outputs = ctrl_out.size(); fsm_data.state_bits = wire->width; fsm_data.reset_state = -1; for (auto &it : states) { @@ -314,7 +314,7 @@ static void extract_fsm(RTLIL::Wire *wire) RTLIL::SigSpec unconn_sig = port_sig.extract(ctrl_out); RTLIL::Wire *unconn_wire = new RTLIL::Wire; unconn_wire->name = stringf("$fsm_unconnect$%s$%d", log_signal(unconn_sig), RTLIL::autoidx++); - unconn_wire->width = unconn_sig.__width; + unconn_wire->width = unconn_sig.size(); module->wires[unconn_wire->name] = unconn_wire; port_sig.replace(unconn_sig, RTLIL::SigSpec(unconn_wire), &cell->connections[cellport.second]); } @@ -367,7 +367,7 @@ struct FsmExtractPass : public Pass { sig2driver.insert(sig, sig2driver_entry_t(cell_it.first, conn_it.first)); } if (ct.cell_input(cell_it.second->type, conn_it.first) && cell_it.second->connections.count("\\Y") > 0 && - cell_it.second->connections["\\Y"].__width == 1 && (conn_it.first == "\\A" || conn_it.first == "\\B")) { + cell_it.second->connections["\\Y"].size() == 1 && (conn_it.first == "\\A" || conn_it.first == "\\B")) { RTLIL::SigSpec sig = conn_it.second; assign_map.apply(sig); sig2trigger.insert(sig, sig2driver_entry_t(cell_it.first, conn_it.first)); diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc index f11d78b39..f8ffee523 100644 --- a/passes/fsm/fsm_map.cc +++ b/passes/fsm/fsm_map.cc @@ -50,12 +50,12 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map 0) + if (eq_sig_a.size() > 0) { RTLIL::Wire *eq_wire = new RTLIL::Wire; eq_wire->name = NEW_ID; @@ -69,17 +69,17 @@ static void implement_pattern_cache(RTLIL::Module *module, std::mapconnections["\\Y"] = RTLIL::SigSpec(eq_wire); eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false); eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false); - eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(eq_sig_a.__width); - eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(eq_sig_b.__width); + eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(eq_sig_a.size()); + eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(eq_sig_b.size()); eq_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); module->add(eq_cell); and_sig.append(RTLIL::SigSpec(eq_wire)); } - if (or_sig.__width < num_states-int(fullstate_cache.size())) + if (or_sig.size() < num_states-int(fullstate_cache.size())) { - if (or_sig.__width == 1) + if (or_sig.size() == 1) { and_sig.append(or_sig); } @@ -95,7 +95,7 @@ static void implement_pattern_cache(RTLIL::Module *module, std::mapconnections["\\A"] = or_sig; or_cell->connections["\\Y"] = RTLIL::SigSpec(or_wire); or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false); - or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(or_sig.__width); + or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(or_sig.size()); or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); module->add(or_cell); @@ -103,7 +103,7 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map 1) { + if (cases_vector.size() > 1) { RTLIL::Cell *or_cell = new RTLIL::Cell; or_cell->name = NEW_ID; or_cell->type = "$reduce_or"; or_cell->connections["\\A"] = cases_vector; or_cell->connections["\\Y"] = output; or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false); - or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cases_vector.__width); + or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cases_vector.size()); or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); module->add(or_cell); - } else if (cases_vector.__width == 1) { + } else if (cases_vector.size() == 1) { module->connections.push_back(RTLIL::SigSig(output, cases_vector)); } else { module->connections.push_back(RTLIL::SigSig(output, RTLIL::SigSpec(0, 1))); @@ -237,8 +237,8 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) eq_cell->connections["\\Y"] = RTLIL::SigSpec(state_onehot, 1, i); eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false); eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false); - eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_a.__width); - eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(sig_b.__width); + eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_a.size()); + eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(sig_b.size()); eq_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); module->add(eq_cell); } @@ -308,8 +308,8 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) mux_cell->connections["\\B"] = sig_b; mux_cell->connections["\\S"] = sig_s; mux_cell->connections["\\Y"] = RTLIL::SigSpec(next_state_wire); - mux_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_a.__width); - mux_cell->parameters["\\S_WIDTH"] = RTLIL::Const(sig_s.__width); + mux_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_a.size()); + mux_cell->parameters["\\S_WIDTH"] = RTLIL::Const(sig_s.size()); module->add(mux_cell); } diff --git a/passes/fsm/fsm_opt.cc b/passes/fsm/fsm_opt.cc index 6732d2abd..367b38eb1 100644 --- a/passes/fsm/fsm_opt.cc +++ b/passes/fsm/fsm_opt.cc @@ -33,11 +33,11 @@ struct FsmOpt bool signal_is_unused(RTLIL::SigSpec sig) { - assert(sig.__width == 1); + assert(sig.size() == 1); sig.optimize(); - RTLIL::Wire *wire = sig.__chunks[0].wire; - int bit = sig.__chunks[0].offset; + RTLIL::Wire *wire = sig.chunks()[0].wire; + int bit = sig.chunks()[0].offset; if (!wire || wire->attributes.count("\\unused_bits") == 0) return false; @@ -55,11 +55,11 @@ struct FsmOpt void opt_const_and_unused_inputs() { RTLIL::SigSpec ctrl_in = cell->connections["\\CTRL_IN"]; - std::vector ctrl_in_used(ctrl_in.__width); + std::vector ctrl_in_used(ctrl_in.size()); std::vector new_transition_table; for (auto &tr : fsm_data.transition_table) { - for (int i = 0; i < ctrl_in.__width; i++) { + for (int i = 0; i < ctrl_in.size(); i++) { RTLIL::SigSpec ctrl_bit = ctrl_in.extract(i, 1); if (ctrl_bit.is_fully_const()) { if (tr.ctrl_in.bits[i] <= RTLIL::State::S1 && RTLIL::SigSpec(tr.ctrl_in.bits[i]) != ctrl_bit) @@ -112,8 +112,8 @@ struct FsmOpt { RTLIL::SigSpec &ctrl_in = cell->connections["\\CTRL_IN"]; - for (int i = 0; i < ctrl_in.__width; i++) - for (int j = i+1; j < ctrl_in.__width; j++) + for (int i = 0; i < ctrl_in.size(); i++) + for (int j = i+1; j < ctrl_in.size(); j++) if (ctrl_in.extract(i, 1) == ctrl_in.extract(j, 1)) { log(" Optimize handling of signal %s that is connected to inputs %d and %d.\n", log_signal(ctrl_in.extract(i, 1)), i, j); @@ -150,8 +150,8 @@ struct FsmOpt RTLIL::SigSpec &ctrl_in = cell->connections["\\CTRL_IN"]; RTLIL::SigSpec &ctrl_out = cell->connections["\\CTRL_OUT"]; - for (int j = 0; j < ctrl_out.__width; j++) - for (int i = 0; i < ctrl_in.__width; i++) + for (int j = 0; j < ctrl_out.size(); j++) + for (int i = 0; i < ctrl_in.size(); i++) if (ctrl_in.extract(i, 1) == ctrl_out.extract(j, 1)) { log(" Optimize handling of signal %s that is connected to input %d and output %d.\n", log_signal(ctrl_in.extract(i, 1)), i, j); diff --git a/passes/fsm/fsmdata.h b/passes/fsm/fsmdata.h index 6b1753060..718b97043 100644 --- a/passes/fsm/fsmdata.h +++ b/passes/fsm/fsmdata.h @@ -143,15 +143,15 @@ struct FsmData log(" Input signals:\n"); RTLIL::SigSpec sig_in = cell->connections["\\CTRL_IN"]; sig_in.expand(); - for (size_t i = 0; i < sig_in.__chunks.size(); i++) - log(" %3zd: %s\n", i, log_signal(sig_in.__chunks[i])); + for (size_t i = 0; i < sig_in.chunks().size(); i++) + log(" %3zd: %s\n", i, log_signal(sig_in.chunks()[i])); log("\n"); log(" Output signals:\n"); RTLIL::SigSpec sig_out = cell->connections["\\CTRL_OUT"]; sig_out.expand(); - for (size_t i = 0; i < sig_out.__chunks.size(); i++) - log(" %3zd: %s\n", i, log_signal(sig_out.__chunks[i])); + for (size_t i = 0; i < sig_out.chunks().size(); i++) + log(" %3zd: %s\n", i, log_signal(sig_out.chunks()[i])); log("\n"); log(" State encoding:\n"); diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 5d9dc18a4..90f377e0d 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -61,7 +61,7 @@ static void generate(RTLIL::Design *design, const std::vector &cell for (auto &conn : i2.second->connections) { if (conn.first[0] != '$') portnames.insert(conn.first); - portwidths[conn.first] = std::max(portwidths[conn.first], conn.second.__width); + portwidths[conn.first] = std::max(portwidths[conn.first], conn.second.size()); } for (auto ¶ : i2.second->parameters) parameters.insert(para.first); @@ -220,7 +220,7 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla RTLIL::Module *mod = design->modules[cell->type]; for (auto &conn : cell->connections) { - int conn_size = conn.second.__width; + int conn_size = conn.second.size(); std::string portname = conn.first; if (portname.substr(0, 1) == "$") { int port_id = atoi(portname.substr(1).c_str()); diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index f8f2b596b..fa8043c89 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -67,7 +67,7 @@ struct SubmodWorker void flag_signal(RTLIL::SigSpec &sig, bool create, bool set_int_driven, bool set_int_used, bool set_ext_driven, bool set_ext_used) { - for (auto &c : sig.__chunks) + for (auto &c : sig.chunks()) if (c.wire != NULL) flag_wire(c.wire, create, set_int_driven, set_int_used, set_ext_driven, set_ext_used); } @@ -164,7 +164,7 @@ struct SubmodWorker for (RTLIL::Cell *cell : submod.cells) { RTLIL::Cell *new_cell = new RTLIL::Cell(*cell); for (auto &conn : new_cell->connections) - for (auto &c : conn.second.__chunks) + for (auto &c : conn.second.chunks()) if (c.wire != NULL) { assert(wire_flags.count(c.wire) > 0); c.wire = wire_flags[c.wire].new_wire; diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc index 6c9e1b773..5f06438f0 100644 --- a/passes/memory/memory_collect.cc +++ b/passes/memory/memory_collect.cc @@ -142,16 +142,16 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) sig_wr_clk_enable.optimize(); sig_wr_clk_polarity.optimize(); - assert(sig_wr_clk.__width == wr_ports); - assert(sig_wr_clk_enable.__width == wr_ports && sig_wr_clk_enable.is_fully_const()); - assert(sig_wr_clk_polarity.__width == wr_ports && sig_wr_clk_polarity.is_fully_const()); - assert(sig_wr_addr.__width == wr_ports * addr_bits); - assert(sig_wr_data.__width == wr_ports * memory->width); - assert(sig_wr_en.__width == wr_ports * memory->width); + assert(sig_wr_clk.size() == wr_ports); + assert(sig_wr_clk_enable.size() == wr_ports && sig_wr_clk_enable.is_fully_const()); + assert(sig_wr_clk_polarity.size() == wr_ports && sig_wr_clk_polarity.is_fully_const()); + assert(sig_wr_addr.size() == wr_ports * addr_bits); + assert(sig_wr_data.size() == wr_ports * memory->width); + assert(sig_wr_en.size() == wr_ports * memory->width); mem->parameters["\\WR_PORTS"] = RTLIL::Const(wr_ports); - mem->parameters["\\WR_CLK_ENABLE"] = wr_ports ? sig_wr_clk_enable.__chunks[0].data : RTLIL::Const(0, 0); - mem->parameters["\\WR_CLK_POLARITY"] = wr_ports ? sig_wr_clk_polarity.__chunks[0].data : RTLIL::Const(0, 0); + mem->parameters["\\WR_CLK_ENABLE"] = wr_ports ? sig_wr_clk_enable.chunks()[0].data : RTLIL::Const(0, 0); + mem->parameters["\\WR_CLK_POLARITY"] = wr_ports ? sig_wr_clk_polarity.chunks()[0].data : RTLIL::Const(0, 0); mem->connections["\\WR_CLK"] = sig_wr_clk; mem->connections["\\WR_ADDR"] = sig_wr_addr; @@ -162,16 +162,16 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) sig_rd_clk_polarity.optimize(); sig_rd_transparent.optimize(); - assert(sig_rd_clk.__width == rd_ports); - assert(sig_rd_clk_enable.__width == rd_ports && sig_rd_clk_enable.is_fully_const()); - assert(sig_rd_clk_polarity.__width == rd_ports && sig_rd_clk_polarity.is_fully_const()); - assert(sig_rd_addr.__width == rd_ports * addr_bits); - assert(sig_rd_data.__width == rd_ports * memory->width); + assert(sig_rd_clk.size() == rd_ports); + assert(sig_rd_clk_enable.size() == rd_ports && sig_rd_clk_enable.is_fully_const()); + assert(sig_rd_clk_polarity.size() == rd_ports && sig_rd_clk_polarity.is_fully_const()); + assert(sig_rd_addr.size() == rd_ports * addr_bits); + assert(sig_rd_data.size() == rd_ports * memory->width); mem->parameters["\\RD_PORTS"] = RTLIL::Const(rd_ports); - mem->parameters["\\RD_CLK_ENABLE"] = rd_ports ? sig_rd_clk_enable.__chunks[0].data : RTLIL::Const(0, 0); - mem->parameters["\\RD_CLK_POLARITY"] = rd_ports ? sig_rd_clk_polarity.__chunks[0].data : RTLIL::Const(0, 0); - mem->parameters["\\RD_TRANSPARENT"] = rd_ports ? sig_rd_transparent.__chunks[0].data : RTLIL::Const(0, 0); + mem->parameters["\\RD_CLK_ENABLE"] = rd_ports ? sig_rd_clk_enable.chunks()[0].data : RTLIL::Const(0, 0); + mem->parameters["\\RD_CLK_POLARITY"] = rd_ports ? sig_rd_clk_polarity.chunks()[0].data : RTLIL::Const(0, 0); + mem->parameters["\\RD_TRANSPARENT"] = rd_ports ? sig_rd_transparent.chunks()[0].data : RTLIL::Const(0, 0); mem->connections["\\RD_CLK"] = sig_rd_clk; mem->connections["\\RD_ADDR"] = sig_rd_addr; diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index 174417bd6..8bae24cff 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -34,9 +34,9 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI normalize_sig(module, sig); sig.expand(); - for (size_t i = 0; i < sig.__chunks.size(); i++) + for (size_t i = 0; i < sig.chunks().size(); i++) { - RTLIL::SigChunk &chunk = sig.__chunks[i]; + RTLIL::SigChunk &chunk = sig.chunks()[i]; if (chunk.wire == NULL) continue; @@ -59,11 +59,11 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI normalize_sig(module, q_norm); RTLIL::SigSpec d = q_norm.extract(chunk, &cell->connections[after ? "\\Q" : "\\D"]); - if (d.__width != 1) + if (d.size() != 1) continue; - assert(d.__chunks.size() == 1); - chunk = d.__chunks[0]; + assert(d.chunks().size() == 1); + chunk = d.chunks()[0]; clk = cell->connections["\\CLK"]; clk_polarity = cell->parameters["\\CLK_POLARITY"].as_bool(); goto replaced_this_bit; @@ -125,7 +125,7 @@ static void disconnect_dff(RTLIL::Module *module, RTLIL::SigSpec sig) RTLIL::Wire *wire = new RTLIL::Wire; wire->name = sstr.str(); - wire->width = sig.__width; + wire->width = sig.size(); module->wires[wire->name] = wire; RTLIL::SigSpec newsig(wire); diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index b848e09e4..e605e6e51 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -68,7 +68,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::Const clocks_en = cell->parameters["\\WR_CLK_ENABLE"]; RTLIL::SigSpec refclock; RTLIL::State refclock_pol = RTLIL::State::Sx; - for (int i = 0; i < clocks.__width; i++) { + for (int i = 0; i < clocks.size(); i++) { RTLIL::SigSpec wr_en = cell->connections["\\WR_EN"].extract(i * mem_width, mem_width); if (wr_en.is_fully_const() && !wr_en.as_bool()) { static_ports.insert(i); @@ -89,7 +89,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) cell->name.c_str(), module->name.c_str(), i); return; } - if (refclock.__width == 0) { + if (refclock.size() == 0) { refclock = clocks.extract(i, 1); refclock_pol = clocks_pol.bits[i]; } @@ -277,12 +277,12 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) c->connections["\\Y"] = w_seladdr; int wr_offset = 0; - while (wr_offset < wr_en.__width) + while (wr_offset < wr_en.size()) { int wr_width = 1; RTLIL::SigSpec wr_bit = wr_en.extract(wr_offset, 1); - while (wr_offset + wr_width < wr_en.__width) { + while (wr_offset + wr_width < wr_en.size()) { RTLIL::SigSpec next_wr_bit = wr_en.extract(wr_offset + wr_width, 1); if (next_wr_bit != wr_bit) break; diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index e56d14b68..5c349f702 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -116,7 +116,7 @@ struct MemoryShareWorker created_conditions++; } - if (terms.__width > 1) + if (terms.size() > 1) terms = module->ReduceAnd(NEW_ID, terms); return conditions_logic_cache[conditions] = terms; @@ -254,7 +254,7 @@ struct MemoryShareWorker // this is the naive version of the function that does not care about grouping the EN bits. RTLIL::SigSpec inv_mask_bits = module->Not(NEW_ID, mask_bits); - RTLIL::SigSpec inv_mask_bits_filtered = module->Mux(NEW_ID, RTLIL::SigSpec(RTLIL::State::S1, bits.__width), inv_mask_bits, do_mask); + RTLIL::SigSpec inv_mask_bits_filtered = module->Mux(NEW_ID, RTLIL::SigSpec(RTLIL::State::S1, bits.size()), inv_mask_bits, do_mask); RTLIL::SigSpec result = module->And(NEW_ID, inv_mask_bits_filtered, bits); return result; } @@ -269,10 +269,10 @@ struct MemoryShareWorker std::map, std::pair>> groups; RTLIL::SigSpec grouped_bits, grouped_mask_bits; - for (int i = 0; i < bits.__width; i++) { + for (int i = 0; i < bits.size(); i++) { std::pair key(v_bits[i], v_mask_bits[i]); if (groups.count(key) == 0) { - groups[key].first = grouped_bits.__width; + groups[key].first = grouped_bits.size(); grouped_bits.append_bit(v_bits[i]); grouped_mask_bits.append_bit(v_mask_bits[i]); } @@ -282,7 +282,7 @@ struct MemoryShareWorker std::vector grouped_result = mask_en_naive(do_mask, grouped_bits, grouped_mask_bits); RTLIL::SigSpec result; - for (int i = 0; i < bits.__width; i++) { + for (int i = 0; i < bits.size(); i++) { std::pair key(v_bits[i], v_mask_bits[i]); result.append_bit(grouped_result.at(groups.at(key).first)); } @@ -320,7 +320,7 @@ struct MemoryShareWorker // Create the new merged_data signal. - RTLIL::SigSpec new_merged_data(RTLIL::State::Sx, merged_data.__width); + RTLIL::SigSpec new_merged_data(RTLIL::State::Sx, merged_data.size()); RTLIL::SigSpec old_data_set = module->And(NEW_ID, merged_en, merged_data); RTLIL::SigSpec old_data_unset = module->And(NEW_ID, merged_en, module->Not(NEW_ID, merged_data)); diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 8a097916d..68fb2e72c 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -106,13 +106,13 @@ static int count_nontrivial_wire_attrs(RTLIL::Wire *w) static bool compare_signals(RTLIL::SigSpec &s1, RTLIL::SigSpec &s2, SigPool ®s, SigPool &conns, std::set &direct_wires) { - assert(s1.__width == 1); - assert(s2.__width == 1); - assert(s1.__chunks.size() == 1); - assert(s2.__chunks.size() == 1); + assert(s1.size() == 1); + assert(s2.size() == 1); + assert(s1.chunks().size() == 1); + assert(s2.chunks().size() == 1); - RTLIL::Wire *w1 = s1.__chunks[0].wire; - RTLIL::Wire *w2 = s2.__chunks[0].wire; + RTLIL::Wire *w1 = s1.chunks()[0].wire; + RTLIL::Wire *w2 = s2.chunks()[0].wire; if (w1 == NULL || w2 == NULL) return w2 == NULL; @@ -235,14 +235,14 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool } else { s1.expand(); s2.expand(); - assert(s1.__chunks.size() == s2.__chunks.size()); + assert(s1.chunks().size() == s2.chunks().size()); RTLIL::SigSig new_conn; - for (size_t i = 0; i < s1.__chunks.size(); i++) - if (s1.__chunks[i] != s2.__chunks[i]) { - new_conn.first.append(s1.__chunks[i]); - new_conn.second.append(s2.__chunks[i]); + for (size_t i = 0; i < s1.chunks().size(); i++) + if (s1.chunks()[i] != s2.chunks()[i]) { + new_conn.first.append(s1.chunks()[i]); + new_conn.second.append(s2.chunks()[i]); } - if (new_conn.first.__width > 0) { + if (new_conn.first.size() > 0) { new_conn.first.optimize(); new_conn.second.optimize(); used_signals.add(new_conn.first); @@ -258,8 +258,8 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool if (!used_signals_nodrivers.check_any(sig)) { std::string unused_bits; sig.expand(); - for (size_t i = 0; i < sig.__chunks.size(); i++) { - if (sig.__chunks[i].wire == NULL) + for (size_t i = 0; i < sig.chunks().size(); i++) { + if (sig.chunks()[i].wire == NULL) continue; if (!used_signals_nodrivers.check_any(sig)) { if (!unused_bits.empty()) diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index bee86771c..1a1f0fe42 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -56,13 +56,13 @@ static void replace_undriven(RTLIL::Design *design, RTLIL::Module *module) all_signals.del(driven_signals); RTLIL::SigSpec undriven_signals = all_signals.export_all(); - for (auto &c : undriven_signals.__chunks) + for (auto &c : undriven_signals.chunks()) { RTLIL::SigSpec sig = c; if (c.wire->name[0] == '$') sig = used_signals.extract(sig); - if (sig.__width == 0) + if (sig.size() == 0) continue; log("Setting undriven signal in %s to undef: %s\n", RTLIL::id2cstr(module->name), log_signal(c)); @@ -74,7 +74,7 @@ static void replace_undriven(RTLIL::Design *design, RTLIL::Module *module) static void replace_cell(RTLIL::Module *module, RTLIL::Cell *cell, std::string info, std::string out_port, RTLIL::SigSpec out_val) { RTLIL::SigSpec Y = cell->connections[out_port]; - out_val.extend_u0(Y.__width, false); + out_val.extend_u0(Y.size(), false); log("Replacing %s cell `%s' (%s) in module `%s' with constant driver `%s = %s'.\n", cell->type.c_str(), cell->name.c_str(), info.c_str(), @@ -99,11 +99,11 @@ static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool com RTLIL::SigSpec sig_y = sigmap(cell->connections.at("\\Y")); if (extend_u0) { - sig_a.extend_u0(sig_y.__width, a_signed); - sig_b.extend_u0(sig_y.__width, b_signed); + sig_a.extend_u0(sig_y.size(), a_signed); + sig_b.extend_u0(sig_y.size(), b_signed); } else { - sig_a.extend(sig_y.__width, a_signed); - sig_b.extend(sig_y.__width, b_signed); + sig_a.extend(sig_y.size(), a_signed); + sig_b.extend(sig_y.size(), b_signed); } std::vector bits_a = sig_a, bits_b = sig_b, bits_y = sig_y; @@ -153,7 +153,7 @@ static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool com for (auto &it : grouped_bits[i]) { for (auto &bit : it.second) { new_conn.first.append_bit(bit); - new_conn.second.append_bit(RTLIL::SigBit(new_y, new_a.__width)); + new_conn.second.append_bit(RTLIL::SigBit(new_y, new_a.size())); } new_a.append_bit(it.first.first); new_b.append_bit(it.first.second); @@ -162,12 +162,12 @@ static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool com RTLIL::Cell *c = module->addCell(NEW_ID, cell->type); c->connections["\\A"] = new_a; - c->parameters["\\A_WIDTH"] = new_a.__width; + c->parameters["\\A_WIDTH"] = new_a.size(); c->parameters["\\A_SIGNED"] = false; if (b_name == "\\B") { c->connections["\\B"] = new_b; - c->parameters["\\B_WIDTH"] = new_b.__width; + c->parameters["\\B_WIDTH"] = new_b.size(); c->parameters["\\B_SIGNED"] = false; } @@ -202,7 +202,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo for (auto &cell_it : module->cells) if (design->selected(module, cell_it.second)) { if ((cell_it.second->type == "$_INV_" || cell_it.second->type == "$not" || cell_it.second->type == "$logic_not") && - cell_it.second->connections["\\A"].__width == 1 && cell_it.second->connections["\\Y"].__width == 1) + cell_it.second->connections["\\A"].size() == 1 && cell_it.second->connections["\\Y"].size() == 1) invert_map[assign_map(cell_it.second->connections["\\Y"])] = assign_map(cell_it.second->connections["\\A"]); cells.push_back(cell_it.second); } @@ -334,12 +334,12 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cell->type == "$lt" || cell->type == "$le" || cell->type == "$ge" || cell->type == "$gt") replace_cell(module, cell, "x-bit in input", "\\Y", RTLIL::State::Sx); else - replace_cell(module, cell, "x-bit in input", "\\Y", RTLIL::SigSpec(RTLIL::State::Sx, cell->connections.at("\\Y").__width)); + replace_cell(module, cell, "x-bit in input", "\\Y", RTLIL::SigSpec(RTLIL::State::Sx, cell->connections.at("\\Y").size())); goto next_cell; } } - if ((cell->type == "$_INV_" || cell->type == "$not" || cell->type == "$logic_not") && cell->connections["\\Y"].__width == 1 && + if ((cell->type == "$_INV_" || cell->type == "$not" || cell->type == "$logic_not") && cell->connections["\\Y"].size() == 1 && invert_map.count(assign_map(cell->connections["\\A"])) != 0) { replace_cell(module, cell, "double_invert", "\\Y", invert_map.at(assign_map(cell->connections["\\A"]))); goto next_cell; @@ -460,35 +460,35 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo RTLIL::SigSpec new_a, new_b; a.expand(), b.expand(); - assert(a.__chunks.size() == b.__chunks.size()); - for (size_t i = 0; i < a.__chunks.size(); i++) { - if (a.__chunks[i].wire == NULL && b.__chunks[i].wire == NULL && a.__chunks[i].data.bits[0] != b.__chunks[i].data.bits[0] && - a.__chunks[i].data.bits[0] <= RTLIL::State::S1 && b.__chunks[i].data.bits[0] <= RTLIL::State::S1) { + assert(a.chunks().size() == b.chunks().size()); + for (size_t i = 0; i < a.chunks().size(); i++) { + if (a.chunks()[i].wire == NULL && b.chunks()[i].wire == NULL && a.chunks()[i].data.bits[0] != b.chunks()[i].data.bits[0] && + a.chunks()[i].data.bits[0] <= RTLIL::State::S1 && b.chunks()[i].data.bits[0] <= RTLIL::State::S1) { RTLIL::SigSpec new_y = RTLIL::SigSpec((cell->type == "$eq" || cell->type == "$eqx") ? RTLIL::State::S0 : RTLIL::State::S1); new_y.extend(cell->parameters["\\Y_WIDTH"].as_int(), false); replace_cell(module, cell, "empty", "\\Y", new_y); goto next_cell; } - if (a.__chunks[i] == b.__chunks[i]) + if (a.chunks()[i] == b.chunks()[i]) continue; - new_a.append(a.__chunks[i]); - new_b.append(b.__chunks[i]); + new_a.append(a.chunks()[i]); + new_b.append(b.chunks()[i]); } - if (new_a.__width == 0) { + if (new_a.size() == 0) { RTLIL::SigSpec new_y = RTLIL::SigSpec((cell->type == "$eq" || cell->type == "$eqx") ? RTLIL::State::S1 : RTLIL::State::S0); new_y.extend(cell->parameters["\\Y_WIDTH"].as_int(), false); replace_cell(module, cell, "empty", "\\Y", new_y); goto next_cell; } - if (new_a.__width < a.__width || new_b.__width < b.__width) { + if (new_a.size() < a.size() || new_b.size() < b.size()) { new_a.optimize(); new_b.optimize(); cell->connections["\\A"] = new_a; cell->connections["\\B"] = new_b; - cell->parameters["\\A_WIDTH"] = new_a.__width; - cell->parameters["\\B_WIDTH"] = new_b.__width; + cell->parameters["\\A_WIDTH"] = new_a.size(); + cell->parameters["\\B_WIDTH"] = new_b.size(); } } @@ -550,10 +550,10 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo RTLIL::SigSpec a = assign_map(cell->connections["\\A"]); RTLIL::SigSpec b = assign_map(cell->connections["\\B"]); - if (a.is_fully_const() && a.__width <= 32 && a.as_int() == 1) + if (a.is_fully_const() && a.size() <= 32 && a.as_int() == 1) identity_wrt_b = true; - if (b.is_fully_const() && b.__width <= 32 && b.as_int() == 1) + if (b.is_fully_const() && b.size() <= 32 && b.as_int() == 1) identity_wrt_a = true; } @@ -561,7 +561,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo { RTLIL::SigSpec b = assign_map(cell->connections["\\B"]); - if (b.is_fully_const() && b.__width <= 32 && b.as_int() == 1) + if (b.is_fully_const() && b.size() <= 32 && b.as_int() == 1) identity_wrt_a = true; } @@ -650,13 +650,13 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (mux_undef && (cell->type == "$mux" || cell->type == "$pmux")) { RTLIL::SigSpec new_a, new_b, new_s; - int width = cell->connections.at("\\A").__width; + int width = cell->connections.at("\\A").size(); if ((cell->connections.at("\\A").is_fully_undef() && cell->connections.at("\\B").is_fully_undef()) || cell->connections.at("\\S").is_fully_undef()) { replace_cell(module, cell, "mux undef", "\\Y", cell->connections.at("\\A")); goto next_cell; } - for (int i = 0; i < cell->connections.at("\\S").__width; i++) { + for (int i = 0; i < cell->connections.at("\\S").size(); i++) { RTLIL::SigSpec old_b = cell->connections.at("\\B").extract(i*width, width); RTLIL::SigSpec old_s = cell->connections.at("\\S").extract(i, 1); if (old_b.is_fully_undef() || old_s.is_fully_undef()) @@ -665,12 +665,12 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo new_s.append(old_s); } new_a = cell->connections.at("\\A"); - if (new_a.is_fully_undef() && new_s.__width > 0) { - new_a = new_b.extract((new_s.__width-1)*width, width); - new_b = new_b.extract(0, (new_s.__width-1)*width); - new_s = new_s.extract(0, new_s.__width-1); + if (new_a.is_fully_undef() && new_s.size() > 0) { + new_a = new_b.extract((new_s.size()-1)*width, width); + new_b = new_b.extract(0, (new_s.size()-1)*width); + new_s = new_s.extract(0, new_s.size()-1); } - if (new_s.__width == 0) { + if (new_s.size() == 0) { replace_cell(module, cell, "mux undef", "\\Y", new_a); goto next_cell; } @@ -678,13 +678,13 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo replace_cell(module, cell, "mux undef", "\\Y", new_s); goto next_cell; } - if (cell->connections.at("\\S").__width != new_s.__width) { + if (cell->connections.at("\\S").size() != new_s.size()) { cell->connections.at("\\A") = new_a; cell->connections.at("\\B") = new_b; cell->connections.at("\\S") = new_s; - if (new_s.__width > 1) { + if (new_s.size() > 1) { cell->type = "$pmux"; - cell->parameters["\\S_WIDTH"] = new_s.__width; + cell->parameters["\\S_WIDTH"] = new_s.size(); } else { cell->type = "$mux"; cell->parameters.erase("\\S_WIDTH"); @@ -700,9 +700,9 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo assign_map.apply(a); \ if (a.is_fully_const()) { \ a.optimize(); \ - if (a.__chunks.empty()) a.__chunks.push_back(RTLIL::SigChunk()); \ + if (a.chunks().empty()) a.chunks().push_back(RTLIL::SigChunk()); \ RTLIL::Const dummy_arg(RTLIL::State::S0, 1); \ - RTLIL::SigSpec y(RTLIL::const_ ## _t(a.__chunks[0].data, dummy_arg, \ + RTLIL::SigSpec y(RTLIL::const_ ## _t(a.chunks()[0].data, dummy_arg, \ cell->parameters["\\A_SIGNED"].as_bool(), false, \ cell->parameters["\\Y_WIDTH"].as_int())); \ replace_cell(module, cell, stringf("%s", log_signal(a)), "\\Y", y); \ @@ -716,9 +716,9 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo assign_map.apply(a), assign_map.apply(b); \ if (a.is_fully_const() && b.is_fully_const()) { \ a.optimize(), b.optimize(); \ - if (a.__chunks.empty()) a.__chunks.push_back(RTLIL::SigChunk()); \ - if (b.__chunks.empty()) b.__chunks.push_back(RTLIL::SigChunk()); \ - RTLIL::SigSpec y(RTLIL::const_ ## _t(a.__chunks[0].data, b.__chunks[0].data, \ + if (a.chunks().empty()) a.chunks().push_back(RTLIL::SigChunk()); \ + if (b.chunks().empty()) b.chunks().push_back(RTLIL::SigChunk()); \ + RTLIL::SigSpec y(RTLIL::const_ ## _t(a.chunks()[0].data, b.chunks()[0].data, \ cell->parameters["\\A_SIGNED"].as_bool(), \ cell->parameters["\\B_SIGNED"].as_bool(), \ cell->parameters["\\Y_WIDTH"].as_int())); \ @@ -787,10 +787,10 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo RTLIL::SigSpec sig_b = assign_map(cell->connections["\\B"]); RTLIL::SigSpec sig_y = assign_map(cell->connections["\\Y"]); - if (sig_b.is_fully_const() && sig_b.__width <= 32) + if (sig_b.is_fully_const() && sig_b.size() <= 32) std::swap(sig_a, sig_b), std::swap(a_signed, b_signed), swapped_ab = true; - if (sig_a.is_fully_def() && sig_a.__width <= 32) + if (sig_a.is_fully_def() && sig_a.size() <= 32) { int a_val = sig_a.as_int(); @@ -799,7 +799,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo log("Replacing multiply-by-zero cell `%s' in module `%s' with zero-driver.\n", cell->name.c_str(), module->name.c_str()); - module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.__width))); + module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size()))); module->remove(cell); OPT_DID_SOMETHING = true; @@ -807,7 +807,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo goto next_cell; } - for (int i = 1; i < (a_signed ? sig_a.__width-1 : sig_a.__width); i++) + for (int i = 1; i < (a_signed ? sig_a.size()-1 : sig_a.size()); i++) if (a_val == (1 << i)) { log("Replacing multiply-by-%d cell `%s' in module `%s' with shift-by-%d.\n", diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc index e844a4209..61147f67a 100644 --- a/passes/opt/opt_muxtree.cc +++ b/passes/opt/opt_muxtree.cc @@ -92,8 +92,8 @@ struct OptMuxtreeWorker muxinfo_t muxinfo; muxinfo.cell = cell; - for (int i = 0; i < sig_s.__width; i++) { - RTLIL::SigSpec sig = sig_b.extract(i*sig_a.__width, sig_a.__width); + for (int i = 0; i < sig_s.size(); i++) { + RTLIL::SigSpec sig = sig_b.extract(i*sig_a.size(), sig_a.size()); RTLIL::SigSpec ctrl_sig = assign_map(sig_s.extract(i, 1)); portinfo_t portinfo; for (int idx : sig2bits(sig)) { @@ -201,7 +201,7 @@ struct OptMuxtreeWorker if (live_ports.size() == 1) { - RTLIL::SigSpec sig_in = sig_ports.extract(live_ports[0]*sig_a.__width, sig_a.__width); + RTLIL::SigSpec sig_in = sig_ports.extract(live_ports[0]*sig_a.size(), sig_a.size()); module->connections.push_back(RTLIL::SigSig(sig_y, sig_in)); module->cells.erase(mi.cell->name); delete mi.cell; @@ -211,7 +211,7 @@ struct OptMuxtreeWorker RTLIL::SigSpec new_sig_a, new_sig_b, new_sig_s; for (size_t i = 0; i < live_ports.size(); i++) { - RTLIL::SigSpec sig_in = sig_ports.extract(live_ports[i]*sig_a.__width, sig_a.__width); + RTLIL::SigSpec sig_in = sig_ports.extract(live_ports[i]*sig_a.size(), sig_a.size()); if (i == live_ports.size()-1) { new_sig_a = sig_in; } else { @@ -223,11 +223,11 @@ struct OptMuxtreeWorker mi.cell->connections["\\A"] = new_sig_a; mi.cell->connections["\\B"] = new_sig_b; mi.cell->connections["\\S"] = new_sig_s; - if (new_sig_s.__width == 1) { + if (new_sig_s.size() == 1) { mi.cell->type = "$mux"; mi.cell->parameters.erase("\\S_WIDTH"); } else { - mi.cell->parameters["\\S_WIDTH"] = RTLIL::Const(new_sig_s.__width); + mi.cell->parameters["\\S_WIDTH"] = RTLIL::Const(new_sig_s.size()); } } } @@ -260,7 +260,7 @@ struct OptMuxtreeWorker std::vector results; assign_map.apply(sig); sig.expand(); - for (auto &c : sig.__chunks) + for (auto &c : sig.chunks()) if (c.wire != NULL) { bitDef_t bit(c.wire, c.offset); if (bit2num.count(bit) == 0) { diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc index 4f1176d97..7ab7233c6 100644 --- a/passes/opt/opt_reduce.cc +++ b/passes/opt/opt_reduce.cc @@ -48,7 +48,7 @@ struct OptReduceWorker sig_a.expand(); RTLIL::SigSpec new_sig_a; - for (auto &chunk : sig_a.__chunks) + for (auto &chunk : sig_a.chunks()) { if (chunk.wire == NULL && chunk.data.bits[0] == RTLIL::State::S0) { if (cell->type == "$reduce_and") { @@ -85,7 +85,7 @@ struct OptReduceWorker } new_sig_a.sort_and_unify(); - if (new_sig_a != sig_a || sig_a.__width != cell->connections["\\A"].__width) { + if (new_sig_a != sig_a || sig_a.size() != cell->connections["\\A"].size()) { log(" New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a)); did_something = true; OPT_DID_SOMETHING = true; @@ -93,7 +93,7 @@ struct OptReduceWorker } cell->connections["\\A"] = new_sig_a; - cell->parameters["\\A_WIDTH"] = RTLIL::Const(new_sig_a.__width); + cell->parameters["\\A_WIDTH"] = RTLIL::Const(new_sig_a.size()); return; } @@ -107,20 +107,20 @@ struct OptReduceWorker std::set handled_sig; handled_sig.insert(sig_a); - for (int i = 0; i < sig_s.__width; i++) + for (int i = 0; i < sig_s.size(); i++) { - RTLIL::SigSpec this_b = sig_b.extract(i*sig_a.__width, sig_a.__width); + RTLIL::SigSpec this_b = sig_b.extract(i*sig_a.size(), sig_a.size()); if (handled_sig.count(this_b) > 0) continue; RTLIL::SigSpec this_s = sig_s.extract(i, 1); - for (int j = i+1; j < sig_s.__width; j++) { - RTLIL::SigSpec that_b = sig_b.extract(j*sig_a.__width, sig_a.__width); + for (int j = i+1; j < sig_s.size(); j++) { + RTLIL::SigSpec that_b = sig_b.extract(j*sig_a.size(), sig_a.size()); if (this_b == that_b) this_s.append(sig_s.extract(j, 1)); } - if (this_s.__width > 1) + if (this_s.size() > 1) { RTLIL::Wire *reduce_or_wire = new RTLIL::Wire; reduce_or_wire->name = NEW_ID; @@ -131,7 +131,7 @@ struct OptReduceWorker reduce_or_cell->type = "$reduce_or"; reduce_or_cell->connections["\\A"] = this_s; reduce_or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); - reduce_or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(this_s.__width); + reduce_or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(this_s.size()); reduce_or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); module->cells[reduce_or_cell->name] = reduce_or_cell; @@ -144,14 +144,14 @@ struct OptReduceWorker handled_sig.insert(this_b); } - if (new_sig_s.__width != sig_s.__width) { + if (new_sig_s.size() != sig_s.size()) { log(" New ctrl vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_s)); did_something = true; OPT_DID_SOMETHING = true; total_count++; } - if (new_sig_s.__width == 0) + if (new_sig_s.size() == 0) { module->connections.push_back(RTLIL::SigSig(cell->connections["\\Y"], cell->connections["\\A"])); assign_map.add(cell->connections["\\Y"], cell->connections["\\A"]); @@ -162,8 +162,8 @@ struct OptReduceWorker { cell->connections["\\B"] = new_sig_b; cell->connections["\\S"] = new_sig_s; - if (new_sig_s.__width > 1) { - cell->parameters["\\S_WIDTH"] = RTLIL::Const(new_sig_s.__width); + if (new_sig_s.size() > 1) { + cell->parameters["\\S_WIDTH"] = RTLIL::Const(new_sig_s.size()); } else { cell->type = "$mux"; cell->parameters.erase("\\S_WIDTH"); @@ -224,7 +224,7 @@ struct OptReduceWorker cell->connections["\\A"].append(in_tuple.at(0)); cell->connections["\\B"] = RTLIL::SigSpec(); - for (int i = 1; i <= cell->connections["\\S"].__width; i++) + for (int i = 1; i <= cell->connections["\\S"].size(); i++) for (auto &in_tuple : consolidated_in_tuples) cell->connections["\\B"].append(in_tuple.at(i)); diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc index 879f7ddc6..4215a7b54 100644 --- a/passes/opt/opt_rmdff.cc +++ b/passes/opt/opt_rmdff.cc @@ -100,7 +100,7 @@ static bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) } } - if (sig_c.is_fully_const() && (!sig_r.__width || !has_init)) { + if (sig_c.is_fully_const() && (!sig_r.size() || !has_init)) { if (val_rv.bits.size() == 0) val_rv = val_init; RTLIL::SigSig conn(sig_q, val_rv); @@ -108,26 +108,26 @@ static bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) goto delete_dff; } - if (sig_d.is_fully_undef() && sig_r.__width && !has_init) { + if (sig_d.is_fully_undef() && sig_r.size() && !has_init) { RTLIL::SigSig conn(sig_q, val_rv); mod->connections.push_back(conn); goto delete_dff; } - if (sig_d.is_fully_undef() && !sig_r.__width && has_init) { + if (sig_d.is_fully_undef() && !sig_r.size() && has_init) { RTLIL::SigSig conn(sig_q, val_init); mod->connections.push_back(conn); goto delete_dff; } - if (sig_d.is_fully_const() && !sig_r.__width && !has_init) { + if (sig_d.is_fully_const() && !sig_r.size() && !has_init) { RTLIL::SigSig conn(sig_q, sig_d); mod->connections.push_back(conn); goto delete_dff; } - if (sig_d == sig_q && !(sig_r.__width && has_init)) { - if (sig_r.__width) { + if (sig_d == sig_q && !(sig_r.size() && has_init)) { + if (sig_r.size()) { RTLIL::SigSig conn(sig_q, val_rv); mod->connections.push_back(conn); } @@ -182,7 +182,7 @@ struct OptRmdffPass : public Pass { std::vector dff_list; for (auto &it : mod_it.second->cells) { if (it.second->type == "$mux" || it.second->type == "$pmux") { - if (it.second->connections.at("\\A").__width == it.second->connections.at("\\B").__width) + if (it.second->connections.at("\\A").size() == it.second->connections.at("\\B").size()) mux_drivers.insert(assign_map(it.second->connections.at("\\Y")), it.second); continue; } diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc index 07e512cba..819a0e460 100644 --- a/passes/opt/opt_share.cc +++ b/passes/opt/opt_share.cc @@ -97,7 +97,7 @@ struct OptShareWorker RTLIL::SigSpec sig = it.second; assign_map.apply(sig); hash_string += "C " + it.first + "="; - for (auto &chunk : sig.__chunks) { + for (auto &chunk : sig.chunks()) { if (chunk.wire) hash_string += "{" + chunk.wire->name + " " + int_to_hash_string(chunk.offset) + " " + diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc index a773e5e72..b5763508a 100644 --- a/passes/proc/proc_arst.cc +++ b/passes/proc/proc_arst.cc @@ -28,7 +28,7 @@ extern void proc_clean_case(RTLIL::CaseRule *cs, bool &did_something, int &count static bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSpec ref, bool &polarity) { - if (signal.__width != 1) + if (signal.size() != 1) return false; if (signal == ref) return true; @@ -80,13 +80,13 @@ static void apply_const(RTLIL::Module *mod, const RTLIL::SigSpec rspec, RTLIL::S { for (auto &action : cs->actions) { if (unknown) - rspec.replace(action.first, RTLIL::SigSpec(RTLIL::State::Sm, action.second.__width), &rval); + rspec.replace(action.first, RTLIL::SigSpec(RTLIL::State::Sm, action.second.size()), &rval); else rspec.replace(action.first, action.second, &rval); } for (auto sw : cs->switches) { - if (sw->signal.__width == 0) { + if (sw->signal.size() == 0) { for (auto cs2 : sw->cases) apply_const(mod, rspec, rval, cs2, const_sig, polarity, unknown); } @@ -164,11 +164,11 @@ restart_proc_arst: } for (auto &action : sync->actions) { RTLIL::SigSpec rspec = action.second; - RTLIL::SigSpec rval = RTLIL::SigSpec(RTLIL::State::Sm, rspec.__width); + RTLIL::SigSpec rval = RTLIL::SigSpec(RTLIL::State::Sm, rspec.size()); rspec.expand(), rval.expand(); - for (int i = 0; i < int(rspec.__chunks.size()); i++) - if (rspec.__chunks[i].wire == NULL) - rval.__chunks[i] = rspec.__chunks[i]; + for (int i = 0; i < int(rspec.chunks().size()); i++) + if (rspec.chunks()[i].wire == NULL) + rval.chunks()[i] = rspec.chunks()[i]; rspec.optimize(), rval.optimize(); RTLIL::SigSpec last_rval; for (int count = 0; rval != last_rval; count++) { @@ -252,14 +252,14 @@ struct ProcArstPass : public Pass { if (sync->type == RTLIL::SyncType::STp || sync->type == RTLIL::SyncType::STn) for (auto &act : sync->actions) { RTLIL::SigSpec arst_sig, arst_val; - for (auto &chunk : act.first.__chunks) + for (auto &chunk : act.first.chunks()) if (chunk.wire && chunk.wire->attributes.count("\\init")) { RTLIL::SigSpec value = chunk.wire->attributes.at("\\init"); value.extend(chunk.wire->width, false); arst_sig.append(chunk); arst_val.append(value.extract(chunk.offset, chunk.width)); } - if (arst_sig.__width) { + if (arst_sig.size()) { log("Added global reset to process %s: %s <- %s\n", proc_it.first.c_str(), log_signal(arst_sig), log_signal(arst_val)); arst_actions.push_back(RTLIL::SigSig(arst_sig, arst_val)); diff --git a/passes/proc/proc_clean.cc b/passes/proc/proc_clean.cc index 768660686..682515c5e 100644 --- a/passes/proc/proc_clean.cc +++ b/passes/proc/proc_clean.cc @@ -27,7 +27,7 @@ extern void proc_clean_case(RTLIL::CaseRule *cs, bool &did_something, int &count void proc_clean_switch(RTLIL::SwitchRule *sw, RTLIL::CaseRule *parent, bool &did_something, int &count, int max_depth) { - if (sw->signal.__width > 0 && sw->signal.is_fully_const()) + if (sw->signal.size() > 0 && sw->signal.is_fully_const()) { int found_matching_case_idx = -1; for (int i = 0; i < int(sw->cases.size()) && found_matching_case_idx < 0; i++) @@ -59,7 +59,7 @@ void proc_clean_switch(RTLIL::SwitchRule *sw, RTLIL::CaseRule *parent, bool &did sw->signal = RTLIL::SigSpec(); } - if (sw->cases.size() == 1 && (sw->signal.__width == 0 || sw->cases[0]->compare.empty())) + if (sw->cases.size() == 1 && (sw->signal.size() == 0 || sw->cases[0]->compare.empty())) { did_something = true; for (auto &action : sw->cases[0]->actions) @@ -91,7 +91,7 @@ void proc_clean_switch(RTLIL::SwitchRule *sw, RTLIL::CaseRule *parent, bool &did void proc_clean_case(RTLIL::CaseRule *cs, bool &did_something, int &count, int max_depth) { for (size_t i = 0; i < cs->actions.size(); i++) { - if (cs->actions[i].first.__width == 0) { + if (cs->actions[i].first.size() == 0) { did_something = true; cs->actions.erase(cs->actions.begin() + (i--)); } @@ -114,7 +114,7 @@ static void proc_clean(RTLIL::Module *mod, RTLIL::Process *proc, int &total_coun bool did_something = true; for (size_t i = 0; i < proc->syncs.size(); i++) { for (size_t j = 0; j < proc->syncs[i]->actions.size(); j++) - if (proc->syncs[i]->actions[j].first.__width == 0) + if (proc->syncs[i]->actions[j].first.size() == 0) proc->syncs[i]->actions.erase(proc->syncs[i]->actions.begin() + (j--)); if (proc->syncs[i]->actions.size() == 0) { delete proc->syncs[i]; diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index d3dff8efc..8e5fbe8f4 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -32,7 +32,7 @@ static RTLIL::SigSpec find_any_lvalue(const RTLIL::Process *proc) for (auto sync : proc->syncs) for (auto &action : sync->actions) - if (action.first.__width > 0) { + if (action.first.size() > 0) { lvalue = action.first; lvalue.sort_and_unify(); break; @@ -44,7 +44,7 @@ static RTLIL::SigSpec find_any_lvalue(const RTLIL::Process *proc) this_lvalue.append(action.first); this_lvalue.sort_and_unify(); RTLIL::SigSpec common_sig = this_lvalue.extract(lvalue); - if (common_sig.__width > 0) + if (common_sig.size() > 0) lvalue = common_sig; } @@ -54,8 +54,8 @@ static RTLIL::SigSpec find_any_lvalue(const RTLIL::Process *proc) static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, RTLIL::SigSpec clk, bool clk_polarity, std::map> &async_rules, RTLIL::Process *proc) { - RTLIL::SigSpec sig_sr_set = RTLIL::SigSpec(0, sig_d.__width); - RTLIL::SigSpec sig_sr_clr = RTLIL::SigSpec(0, sig_d.__width); + RTLIL::SigSpec sig_sr_set = RTLIL::SigSpec(0, sig_d.size()); + RTLIL::SigSpec sig_sr_clr = RTLIL::SigSpec(0, sig_d.size()); for (auto &it : async_rules) { @@ -72,24 +72,24 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S else log_abort(); - if (sync_low_signals.__width > 1) { + if (sync_low_signals.size() > 1) { RTLIL::Cell *cell = new RTLIL::Cell; cell->name = NEW_ID; cell->type = "$reduce_or"; cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); - cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.__width); + cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.size()); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); cell->connections["\\A"] = sync_low_signals; cell->connections["\\Y"] = sync_low_signals = mod->addWire(NEW_ID); mod->add(cell); } - if (sync_low_signals.__width > 0) { + if (sync_low_signals.size() > 0) { RTLIL::Cell *cell = new RTLIL::Cell; cell->name = NEW_ID; cell->type = "$not"; cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); - cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.__width); + cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.size()); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); cell->connections["\\A"] = sync_low_signals; cell->connections["\\Y"] = mod->addWire(NEW_ID); @@ -97,12 +97,12 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S mod->add(cell); } - if (sync_high_signals.__width > 1) { + if (sync_high_signals.size() > 1) { RTLIL::Cell *cell = new RTLIL::Cell; cell->name = NEW_ID; cell->type = "$reduce_or"; cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); - cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_high_signals.__width); + cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_high_signals.size()); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); cell->connections["\\A"] = sync_high_signals; cell->connections["\\Y"] = sync_high_signals = mod->addWire(NEW_ID); @@ -113,30 +113,30 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S inv_cell->name = NEW_ID; inv_cell->type = "$not"; inv_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); - inv_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_d.__width); - inv_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_d.__width); + inv_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_d.size()); + inv_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_d.size()); inv_cell->connections["\\A"] = sync_value; - inv_cell->connections["\\Y"] = sync_value_inv = mod->addWire(NEW_ID, sig_d.__width); + inv_cell->connections["\\Y"] = sync_value_inv = mod->addWire(NEW_ID, sig_d.size()); mod->add(inv_cell); RTLIL::Cell *mux_set_cell = new RTLIL::Cell; mux_set_cell->name = NEW_ID; mux_set_cell->type = "$mux"; - mux_set_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.__width); + mux_set_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size()); mux_set_cell->connections["\\A"] = sig_sr_set; mux_set_cell->connections["\\B"] = sync_value; mux_set_cell->connections["\\S"] = sync_high_signals; - mux_set_cell->connections["\\Y"] = sig_sr_set = mod->addWire(NEW_ID, sig_d.__width); + mux_set_cell->connections["\\Y"] = sig_sr_set = mod->addWire(NEW_ID, sig_d.size()); mod->add(mux_set_cell); RTLIL::Cell *mux_clr_cell = new RTLIL::Cell; mux_clr_cell->name = NEW_ID; mux_clr_cell->type = "$mux"; - mux_clr_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.__width); + mux_clr_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size()); mux_clr_cell->connections["\\A"] = sig_sr_clr; mux_clr_cell->connections["\\B"] = sync_value_inv; mux_clr_cell->connections["\\S"] = sync_high_signals; - mux_clr_cell->connections["\\Y"] = sig_sr_clr = mod->addWire(NEW_ID, sig_d.__width); + mux_clr_cell->connections["\\Y"] = sig_sr_clr = mod->addWire(NEW_ID, sig_d.size()); mod->add(mux_clr_cell); } @@ -147,7 +147,7 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S cell->name = sstr.str(); cell->type = "$dffsr"; cell->attributes = proc->attributes; - cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.__width); + cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size()); cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1); cell->parameters["\\SET_POLARITY"] = RTLIL::Const(true, 1); cell->parameters["\\CLR_POLARITY"] = RTLIL::Const(true, 1); @@ -168,16 +168,16 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec std::stringstream sstr; sstr << "$procdff$" << (RTLIL::autoidx++); - RTLIL::SigSpec sig_set_inv = mod->addWire(NEW_ID, sig_in.__width); - RTLIL::SigSpec sig_sr_set = mod->addWire(NEW_ID, sig_in.__width); - RTLIL::SigSpec sig_sr_clr = mod->addWire(NEW_ID, sig_in.__width); + RTLIL::SigSpec sig_set_inv = mod->addWire(NEW_ID, sig_in.size()); + RTLIL::SigSpec sig_sr_set = mod->addWire(NEW_ID, sig_in.size()); + RTLIL::SigSpec sig_sr_clr = mod->addWire(NEW_ID, sig_in.size()); RTLIL::Cell *inv_set = new RTLIL::Cell; inv_set->name = NEW_ID; inv_set->type = "$not"; inv_set->parameters["\\A_SIGNED"] = RTLIL::Const(0); - inv_set->parameters["\\A_WIDTH"] = RTLIL::Const(sig_in.__width); - inv_set->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_in.__width); + inv_set->parameters["\\A_WIDTH"] = RTLIL::Const(sig_in.size()); + inv_set->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_in.size()); inv_set->connections["\\A"] = sig_set; inv_set->connections["\\Y"] = sig_set_inv; mod->add(inv_set); @@ -185,8 +185,8 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec RTLIL::Cell *mux_sr_set = new RTLIL::Cell; mux_sr_set->name = NEW_ID; mux_sr_set->type = "$mux"; - mux_sr_set->parameters["\\WIDTH"] = RTLIL::Const(sig_in.__width); - mux_sr_set->connections[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.__width); + mux_sr_set->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size()); + mux_sr_set->connections[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.size()); mux_sr_set->connections[set_polarity ? "\\B" : "\\A"] = sig_set; mux_sr_set->connections["\\Y"] = sig_sr_set; mux_sr_set->connections["\\S"] = set; @@ -195,8 +195,8 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec RTLIL::Cell *mux_sr_clr = new RTLIL::Cell; mux_sr_clr->name = NEW_ID; mux_sr_clr->type = "$mux"; - mux_sr_clr->parameters["\\WIDTH"] = RTLIL::Const(sig_in.__width); - mux_sr_clr->connections[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.__width); + mux_sr_clr->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size()); + mux_sr_clr->connections[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.size()); mux_sr_clr->connections[set_polarity ? "\\B" : "\\A"] = sig_set_inv; mux_sr_clr->connections["\\Y"] = sig_sr_clr; mux_sr_clr->connections["\\S"] = set; @@ -206,7 +206,7 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec cell->name = sstr.str(); cell->type = "$dffsr"; cell->attributes = proc->attributes; - cell->parameters["\\WIDTH"] = RTLIL::Const(sig_in.__width); + cell->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size()); cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1); cell->parameters["\\SET_POLARITY"] = RTLIL::Const(true, 1); cell->parameters["\\CLR_POLARITY"] = RTLIL::Const(true, 1); @@ -233,7 +233,7 @@ static void gen_dff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::Const val_ cell->attributes = proc->attributes; mod->cells[cell->name] = cell; - cell->parameters["\\WIDTH"] = RTLIL::Const(sig_in.__width); + cell->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size()); if (arst) { cell->parameters["\\ARST_POLARITY"] = RTLIL::Const(arst_polarity, 1); cell->parameters["\\ARST_VALUE"] = val_rst; @@ -259,14 +259,14 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) RTLIL::SigSpec sig = find_any_lvalue(proc); bool free_sync_level = false; - if (sig.__width == 0) + if (sig.size() == 0) break; log("Creating register for signal `%s.%s' using process `%s.%s'.\n", mod->name.c_str(), log_signal(sig), mod->name.c_str(), proc->name.c_str()); - RTLIL::SigSpec insig = RTLIL::SigSpec(RTLIL::State::Sz, sig.__width); - RTLIL::SigSpec rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.__width); + RTLIL::SigSpec insig = RTLIL::SigSpec(RTLIL::State::Sz, sig.size()); + RTLIL::SigSpec rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size()); RTLIL::SyncRule *sync_level = NULL; RTLIL::SyncRule *sync_edge = NULL; RTLIL::SyncRule *sync_always = NULL; @@ -276,16 +276,16 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) for (auto sync : proc->syncs) for (auto &action : sync->actions) { - if (action.first.extract(sig).__width == 0) + if (action.first.extract(sig).size() == 0) continue; if (sync->type == RTLIL::SyncType::ST0 || sync->type == RTLIL::SyncType::ST1) { if (sync_level != NULL && sync_level != sync) { // log_error("Multiple level sensitive events found for this signal!\n"); many_async_rules[rstval].insert(sync_level); - rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.__width); + rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size()); } - rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.__width); + rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size()); sig.replace(action.first, action.second, &rstval); sync_level = sync; } @@ -324,15 +324,15 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) inputs.append(it->signal); compare.append(it->type == RTLIL::SyncType::ST0 ? RTLIL::State::S1 : RTLIL::State::S0); } - assert(inputs.__width == compare.__width); + assert(inputs.size() == compare.size()); RTLIL::Cell *cell = new RTLIL::Cell; cell->name = NEW_ID; cell->type = "$ne"; cell->parameters["\\A_SIGNED"] = RTLIL::Const(false, 1); cell->parameters["\\B_SIGNED"] = RTLIL::Const(false, 1); - cell->parameters["\\A_WIDTH"] = RTLIL::Const(inputs.__width); - cell->parameters["\\B_WIDTH"] = RTLIL::Const(inputs.__width); + cell->parameters["\\A_WIDTH"] = RTLIL::Const(inputs.size()); + cell->parameters["\\B_WIDTH"] = RTLIL::Const(inputs.size()); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); cell->connections["\\A"] = inputs; cell->connections["\\B"] = compare; @@ -343,7 +343,7 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) } else { - rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.__width); + rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size()); sync_level = NULL; } } @@ -357,7 +357,7 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) sig.optimize(); if (rstval == sig) { - rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.__width); + rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size()); sync_level = NULL; } @@ -386,7 +386,7 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) sync_edge->signal, sync_level->signal, proc); } else - gen_dff(mod, insig, rstval.__chunks[0].data, sig, + gen_dff(mod, insig, rstval.chunks()[0].data, sig, sync_edge->type == RTLIL::SyncType::STp, sync_level && sync_level->type == RTLIL::SyncType::ST1, sync_edge->signal, sync_level ? &sync_level->signal : NULL, proc); diff --git a/passes/proc/proc_init.cc b/passes/proc/proc_init.cc index 0ef17b22d..ba1fb5ab9 100644 --- a/passes/proc/proc_init.cc +++ b/passes/proc/proc_init.cc @@ -60,13 +60,13 @@ static void proc_init(RTLIL::Module *mod, RTLIL::Process *proc) log_cmd_error("Failed to get a constant init value for %s: %s\n", log_signal(lhs), log_signal(rhs)); int offset = 0; - for (size_t i = 0; i < lhs.__chunks.size(); i++) { - if (lhs.__chunks[i].wire == NULL) + for (size_t i = 0; i < lhs.chunks().size(); i++) { + if (lhs.chunks()[i].wire == NULL) continue; - RTLIL::Wire *wire = lhs.__chunks[i].wire; - RTLIL::SigSpec value = rhs.extract(offset, lhs.__chunks[i].width); - if (value.__width != wire->width) - log_cmd_error("Init value is not for the entire wire: %s = %s\n", log_signal(lhs.__chunks[i]), log_signal(value)); + RTLIL::Wire *wire = lhs.chunks()[i].wire; + RTLIL::SigSpec value = rhs.extract(offset, lhs.chunks()[i].width); + if (value.size() != wire->width) + log_cmd_error("Init value is not for the entire wire: %s = %s\n", log_signal(lhs.chunks()[i]), log_signal(value)); log(" Setting init value: %s = %s\n", log_signal(wire), log_signal(value)); wire->attributes["\\init"] = value.as_const(); offset += wire->width; diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc index 2e24e786b..cd459d949 100644 --- a/passes/proc/proc_mux.cc +++ b/passes/proc/proc_mux.cc @@ -28,14 +28,14 @@ static RTLIL::SigSpec find_any_lvalue(const RTLIL::CaseRule *cs) { for (auto &action : cs->actions) { - if (action.first.__width) + if (action.first.size()) return action.first; } for (auto sw : cs->switches) for (auto cs2 : sw->cases) { RTLIL::SigSpec sig = find_any_lvalue(cs2); - if (sig.__width) + if (sig.size()) return sig; } @@ -46,7 +46,7 @@ static void extract_core_signal(const RTLIL::CaseRule *cs, RTLIL::SigSpec &sig) { for (auto &action : cs->actions) { RTLIL::SigSpec lvalue = action.first.extract(sig); - if (lvalue.__width) + if (lvalue.size()) sig = lvalue; } @@ -72,18 +72,18 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, comp.expand(); // get rid of don't-care bits - assert(sig.__width == comp.__width); - for (int i = 0; i < comp.__width; i++) - if (comp.__chunks[i].wire == NULL && comp.__chunks[i].data.bits[0] == RTLIL::State::Sa) { + assert(sig.size() == comp.size()); + for (int i = 0; i < comp.size(); i++) + if (comp.chunks()[i].wire == NULL && comp.chunks()[i].data.bits[0] == RTLIL::State::Sa) { sig.remove(i, 1); comp.remove(i--, 1); } - if (comp.__width == 0) + if (comp.size() == 0) return RTLIL::SigSpec(); sig.optimize(); comp.optimize(); - if (sig.__width == 1 && comp == RTLIL::SigSpec(1,1)) + if (sig.size() == 1 && comp == RTLIL::SigSpec(1,1)) { mod->connections.push_back(RTLIL::SigSig(RTLIL::SigSpec(cmp_wire, 1, cmp_wire->width++), sig)); } @@ -101,8 +101,8 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(0); - eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig.__width); - eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(comp.__width); + eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig.size()); + eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(comp.size()); eq_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); eq_cell->connections["\\A"] = sig; @@ -143,7 +143,7 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector &compare, RTLIL::SigSpec when_signal, RTLIL::SigSpec else_signal, RTLIL::Cell *&last_mux_cell, RTLIL::SwitchRule *sw) { - assert(when_signal.__width == else_signal.__width); + assert(when_signal.size() == else_signal.size()); std::stringstream sstr; sstr << "$procmux$" << (RTLIL::autoidx++); @@ -154,14 +154,14 @@ static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, // compare results RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw); - if (ctrl_sig.__width == 0) + if (ctrl_sig.size() == 0) return when_signal; - assert(ctrl_sig.__width == 1); + assert(ctrl_sig.size() == 1); // prepare multiplexer output signal RTLIL::Wire *result_wire = new RTLIL::Wire; result_wire->name = sstr.str() + "_Y"; - result_wire->width = when_signal.__width; + result_wire->width = when_signal.size(); mod->wires[result_wire->name] = result_wire; // create the multiplexer itself @@ -171,7 +171,7 @@ static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, mux_cell->attributes = sw->attributes; mod->cells[mux_cell->name] = mux_cell; - mux_cell->parameters["\\WIDTH"] = RTLIL::Const(when_signal.__width); + mux_cell->parameters["\\WIDTH"] = RTLIL::Const(when_signal.size()); mux_cell->connections["\\A"] = else_signal; mux_cell->connections["\\B"] = when_signal; mux_cell->connections["\\S"] = ctrl_sig; @@ -184,14 +184,14 @@ static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, static void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector &compare, RTLIL::SigSpec when_signal, RTLIL::Cell *last_mux_cell, RTLIL::SwitchRule *sw) { assert(last_mux_cell != NULL); - assert(when_signal.__width == last_mux_cell->connections["\\A"].__width); + assert(when_signal.size() == last_mux_cell->connections["\\A"].size()); RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw); - assert(ctrl_sig.__width == 1); + assert(ctrl_sig.size() == 1); last_mux_cell->type = "$pmux"; last_mux_cell->connections["\\S"].append(ctrl_sig); last_mux_cell->connections["\\B"].append(when_signal); - last_mux_cell->parameters["\\S_WIDTH"] = last_mux_cell->connections["\\S"].__width; + last_mux_cell->parameters["\\S_WIDTH"] = last_mux_cell->connections["\\S"].size(); } static RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, RTLIL::CaseRule *cs, const RTLIL::SigSpec &sig, const RTLIL::SigSpec &defval) @@ -208,7 +208,7 @@ static RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, RTLIL::CaseRule *cs // detect groups of parallel cases std::vector pgroups(sw->cases.size()); if (!sw->get_bool_attribute("\\parallel_case")) { - BitPatternPool pool(sw->signal.__width); + BitPatternPool pool(sw->signal.size()); bool extra_group_for_next_case = false; for (size_t i = 0; i < sw->cases.size(); i++) { RTLIL::CaseRule *cs2 = sw->cases[i]; @@ -224,7 +224,7 @@ static RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, RTLIL::CaseRule *cs if (cs2->compare.empty()) pgroups[i] = pgroups[i-1]+1; if (pgroups[i] != pgroups[i-1]) - pool = BitPatternPool(sw->signal.__width); + pool = BitPatternPool(sw->signal.size()); } for (auto pat : cs2->compare) if (!pat.is_fully_const()) @@ -258,7 +258,7 @@ static void proc_mux(RTLIL::Module *mod, RTLIL::Process *proc) { RTLIL::SigSpec sig = find_any_lvalue(&proc->root_case); - if (sig.__width == 0) + if (sig.size() == 0) break; if (first) { @@ -270,7 +270,7 @@ static void proc_mux(RTLIL::Module *mod, RTLIL::Process *proc) log(" creating decoder for signal `%s'.\n", log_signal(sig)); - RTLIL::SigSpec value = signal_to_mux_tree(mod, &proc->root_case, sig, RTLIL::SigSpec(RTLIL::State::Sx, sig.__width)); + RTLIL::SigSpec value = signal_to_mux_tree(mod, &proc->root_case, sig, RTLIL::SigSpec(RTLIL::State::Sx, sig.size())); mod->connections.push_back(RTLIL::SigSig(sig, value)); } } diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc index 5369617be..03a86246c 100644 --- a/passes/sat/eval.cc +++ b/passes/sat/eval.cc @@ -44,7 +44,7 @@ struct BruteForceEquivChecker void run_checker(RTLIL::SigSpec &inputs) { - if (inputs.__width < mod1_inputs.__width) { + if (inputs.size() < mod1_inputs.size()) { RTLIL::SigSpec inputs0 = inputs, inputs1 = inputs; inputs0.append(RTLIL::Const(0, 1)); inputs1.append(RTLIL::Const(1, 1)); @@ -71,9 +71,9 @@ struct BruteForceEquivChecker if (ignore_x_mod1) { sig1.expand(), sig2.expand(); - for (size_t i = 0; i < sig1.__chunks.size(); i++) - if (sig1.__chunks.at(i) == RTLIL::SigChunk(RTLIL::State::Sx)) - sig2.__chunks.at(i) = RTLIL::SigChunk(RTLIL::State::Sx); + for (size_t i = 0; i < sig1.chunks().size(); i++) + if (sig1.chunks().at(i) == RTLIL::SigChunk(RTLIL::State::Sx)) + sig2.chunks().at(i) = RTLIL::SigChunk(RTLIL::State::Sx); sig1.optimize(), sig2.optimize(); } @@ -172,11 +172,11 @@ struct VlogHammerReporter log_error("Failed to find solution to SAT problem.\n"); expected_y.expand(); - for (int i = 0; i < expected_y.__width; i++) { + for (int i = 0; i < expected_y.size(); i++) { RTLIL::State solution_bit = y_values.at(i) ? RTLIL::State::S1 : RTLIL::State::S0; - RTLIL::State expected_bit = expected_y.__chunks.at(i).data.bits.at(0); + RTLIL::State expected_bit = expected_y.chunks().at(i).data.bits.at(0); if (model_undef) { - if (y_values.at(expected_y.__width+i)) + if (y_values.at(expected_y.size()+i)) solution_bit = RTLIL::State::Sx; } else { if (expected_bit == RTLIL::State::Sx) @@ -184,17 +184,17 @@ struct VlogHammerReporter } if (solution_bit != expected_bit) { std::string sat_bits, rtl_bits; - for (int k = expected_y.__width-1; k >= 0; k--) { - if (model_undef && y_values.at(expected_y.__width+k)) + for (int k = expected_y.size()-1; k >= 0; k--) { + if (model_undef && y_values.at(expected_y.size()+k)) sat_bits += "x"; else sat_bits += y_values.at(k) ? "1" : "0"; - rtl_bits += expected_y.__chunks.at(k).data.bits.at(0) == RTLIL::State::Sx ? "x" : - expected_y.__chunks.at(k).data.bits.at(0) == RTLIL::State::S1 ? "1" : "0"; + rtl_bits += expected_y.chunks().at(k).data.bits.at(0) == RTLIL::State::Sx ? "x" : + expected_y.chunks().at(k).data.bits.at(0) == RTLIL::State::S1 ? "1" : "0"; } log_error("Found error in SAT model: y[%d] = %s, should be %s:\n SAT: %s\n RTL: %s\n %*s^\n", int(i), log_signal(solution_bit), log_signal(expected_bit), - sat_bits.c_str(), rtl_bits.c_str(), expected_y.__width-i-1, ""); + sat_bits.c_str(), rtl_bits.c_str(), expected_y.size()-i-1, ""); } } @@ -203,16 +203,16 @@ struct VlogHammerReporter std::vector cmp_vars; std::vector cmp_vals; - std::vector y_undef(y_values.begin() + expected_y.__width, y_values.end()); + std::vector y_undef(y_values.begin() + expected_y.size(), y_values.end()); - for (int i = 0; i < expected_y.__width; i++) + for (int i = 0; i < expected_y.size(); i++) if (y_undef.at(i)) { log(" Toggling undef bit %d to test undef gating.\n", i); if (!ez.solve(y_vec, y_values, ez.IFF(y_vec.at(i), y_values.at(i) ? ez.FALSE : ez.TRUE))) log_error("Failed to find solution with toggled bit!\n"); - cmp_vars.push_back(y_vec.at(expected_y.__width + i)); + cmp_vars.push_back(y_vec.at(expected_y.size() + i)); cmp_vals.push_back(true); } else @@ -220,7 +220,7 @@ struct VlogHammerReporter cmp_vars.push_back(y_vec.at(i)); cmp_vals.push_back(y_values.at(i)); - cmp_vars.push_back(y_vec.at(expected_y.__width + i)); + cmp_vars.push_back(y_vec.at(expected_y.size() + i)); cmp_vals.push_back(false); } @@ -283,7 +283,7 @@ struct VlogHammerReporter while (!ce.eval(sig, undef)) { // log_error("Evaluation of y in module %s failed: sig=%s, undef=%s\n", RTLIL::id2cstr(module->name), log_signal(sig), log_signal(undef)); log("Warning: Setting signal %s in module %s to undef.\n", log_signal(undef), RTLIL::id2cstr(module->name)); - ce.set(undef, RTLIL::Const(RTLIL::State::Sx, undef.__width)); + ce.set(undef, RTLIL::Const(RTLIL::State::Sx, undef.size())); } log("++VAL++ %d %s %s #\n", idx, module_name.c_str(), sig.as_const().as_string().c_str()); @@ -293,13 +293,13 @@ struct VlogHammerReporter rtl_sig.expand(); sat_check(module, recorded_set_vars, recorded_set_vals, sig, false); sat_check(module, recorded_set_vars, recorded_set_vals, sig, true); - } else if (rtl_sig.__width > 0) { + } else if (rtl_sig.size() > 0) { sig.expand(); - if (rtl_sig.__width != sig.__width) + if (rtl_sig.size() != sig.size()) log_error("Output (y) has a different width in module %s compared to rtl!\n", RTLIL::id2cstr(module->name)); - for (int i = 0; i < sig.__width; i++) - if (rtl_sig.__chunks.at(i).data.bits.at(0) == RTLIL::State::Sx) - sig.__chunks.at(i).data.bits.at(0) = RTLIL::State::Sx; + for (int i = 0; i < sig.size(); i++) + if (rtl_sig.chunks().at(i).data.bits.at(0) == RTLIL::State::Sx) + sig.chunks().at(i).data.bits.at(0) = RTLIL::State::Sx; } log("++RPT++ %d%s %s %s\n", idx, input_pattern_list.c_str(), sig.as_const().as_string().c_str(), module_name.c_str()); @@ -350,7 +350,7 @@ struct VlogHammerReporter } if (!RTLIL::SigSpec::parse(sig, NULL, pattern) || !sig.is_fully_const()) log_error("Failed to parse pattern %s!\n", pattern.c_str()); - if (sig.__width < total_input_width) + if (sig.size() < total_input_width) log_error("Pattern %s is to short!\n", pattern.c_str()); patterns.push_back(sig.as_const()); if (invert_pattern) { @@ -470,9 +470,9 @@ struct EvalPass : public Pass { log_cmd_error("Failed to parse rhs set expression `%s'.\n", it.second.c_str()); if (!rhs.is_fully_const()) log_cmd_error("Right-hand-side set expression `%s' is not constant.\n", it.second.c_str()); - if (lhs.__width != rhs.__width) + if (lhs.size() != rhs.size()) log_cmd_error("Set expression with different lhs and rhs sizes: %s (%s, %d bits) vs. %s (%s, %d bits)\n", - it.first.c_str(), log_signal(lhs), lhs.__width, it.second.c_str(), log_signal(rhs), rhs.__width); + it.first.c_str(), log_signal(lhs), lhs.size(), it.second.c_str(), log_signal(rhs), rhs.size()); ce.set(lhs, rhs.as_const()); } @@ -493,7 +493,7 @@ struct EvalPass : public Pass { if (set_undef) { while (!ce.eval(value, undef)) { log("Failed to evaluate signal %s: Missing value for %s. -> setting to undef\n", log_signal(signal), log_signal(undef)); - ce.set(undef, RTLIL::Const(RTLIL::State::Sx, undef.__width)); + ce.set(undef, RTLIL::Const(RTLIL::State::Sx, undef.size())); undef = RTLIL::SigSpec(); } log("Eval result: %s = %s.\n", log_signal(signal), log_signal(value)); @@ -526,15 +526,15 @@ struct EvalPass : public Pass { } std::vector tab_line; - for (auto &c : tabsigs.__chunks) + for (auto &c : tabsigs.chunks()) tab_line.push_back(log_signal(c)); tab_sep_colidx = tab_line.size(); - for (auto &c : signal.__chunks) + for (auto &c : signal.chunks()) tab_line.push_back(log_signal(c)); tab.push_back(tab_line); tab_line.clear(); - RTLIL::Const tabvals(0, tabsigs.__width); + RTLIL::Const tabvals(0, tabsigs.size()); do { ce.push(); @@ -548,19 +548,19 @@ struct EvalPass : public Pass { log_signal(tabsigs), log_signal(tabvals), log_signal(this_undef)); return; } - ce.set(this_undef, RTLIL::Const(RTLIL::State::Sx, this_undef.__width)); + ce.set(this_undef, RTLIL::Const(RTLIL::State::Sx, this_undef.size())); undef.append(this_undef); this_undef = RTLIL::SigSpec(); } int pos = 0; - for (auto &c : tabsigs.__chunks) { + for (auto &c : tabsigs.chunks()) { tab_line.push_back(log_signal(RTLIL::SigSpec(tabvals).extract(pos, c.width))); pos += c.width; } pos = 0; - for (auto &c : signal.__chunks) { + for (auto &c : signal.chunks()) { tab_line.push_back(log_signal(value.extract(pos, c.width))); pos += c.width; } @@ -602,7 +602,7 @@ struct EvalPass : public Pass { } log("\n"); - if (undef.__width > 0) { + if (undef.size() > 0) { undef.sort_and_unify(); log("Assumend undef (x) value for the following singals: %s\n\n", log_signal(undef)); } diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc index 4308e7364..c9363f4bf 100644 --- a/passes/sat/expose.cc +++ b/passes/sat/expose.cc @@ -649,7 +649,7 @@ struct ExposePass : public Pass { { RTLIL::Wire *w = new RTLIL::Wire; w->name = cell->name + sep + RTLIL::unescape_id(it.first); - w->width = it.second.__width; + w->width = it.second.size(); if (ct.cell_input(cell->type, it.first)) w->port_output = true; if (ct.cell_output(cell->type, it.first)) diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index 8cc59b291..1e47e7de2 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -714,7 +714,7 @@ struct FreduceWorker if (grp[i].inverted) { - if (inv_sig.__width == 0) + if (inv_sig.size() == 0) { inv_sig = module->addWire(NEW_ID); diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index 1cd794b56..79857c5ea 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -253,11 +253,11 @@ static void create_miter_equiv(struct Pass *that, std::vector args, } } - if (all_conditions.__width != 1) { + if (all_conditions.size() != 1) { RTLIL::Cell *reduce_cell = new RTLIL::Cell; reduce_cell->name = NEW_ID; reduce_cell->type = "$reduce_and"; - reduce_cell->parameters["\\A_WIDTH"] = all_conditions.__width; + reduce_cell->parameters["\\A_WIDTH"] = all_conditions.size(); reduce_cell->parameters["\\Y_WIDTH"] = 1; reduce_cell->parameters["\\A_SIGNED"] = 0; reduce_cell->connections["\\A"] = all_conditions; @@ -283,8 +283,8 @@ static void create_miter_equiv(struct Pass *that, std::vector args, RTLIL::Cell *not_cell = new RTLIL::Cell; not_cell->name = NEW_ID; not_cell->type = "$not"; - not_cell->parameters["\\A_WIDTH"] = all_conditions.__width; - not_cell->parameters["\\A_WIDTH"] = all_conditions.__width; + not_cell->parameters["\\A_WIDTH"] = all_conditions.size(); + not_cell->parameters["\\A_WIDTH"] = all_conditions.size(); not_cell->parameters["\\Y_WIDTH"] = w_trigger->width; not_cell->parameters["\\A_SIGNED"] = 0; not_cell->connections["\\A"] = all_conditions; diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 161449324..24968aa2c 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -101,10 +101,10 @@ struct SatHelper RTLIL::SigSpec lhs = sigmap(it.second); RTLIL::SigSpec rhs = it.second->attributes.at("\\init"); - log_assert(lhs.__width == rhs.__width); + log_assert(lhs.size() == rhs.size()); RTLIL::SigSpec removed_bits; - for (int i = 0; i < lhs.__width; i++) { + for (int i = 0; i < lhs.size(); i++) { RTLIL::SigSpec bit = lhs.extract(i, 1); if (!satgen.initial_state.check_all(bit)) { removed_bits.append(bit); @@ -118,10 +118,10 @@ struct SatHelper rhs.optimize(); removed_bits.optimize(); - if (removed_bits.__width) + if (removed_bits.size()) log("Warning: ignoring initial value on non-register: %s\n", log_signal(removed_bits)); - if (lhs.__width) { + if (lhs.size()) { log("Import set-constraint from init attribute: %s = %s\n", log_signal(lhs), log_signal(rhs)); big_lhs.remove2(lhs, &big_rhs); big_lhs.append(lhs); @@ -140,9 +140,9 @@ struct SatHelper show_signal_pool.add(sigmap(lhs)); show_signal_pool.add(sigmap(rhs)); - if (lhs.__width != rhs.__width) + if (lhs.size() != rhs.size()) log_cmd_error("Set expression with different lhs and rhs sizes: %s (%s, %d bits) vs. %s (%s, %d bits)\n", - s.first.c_str(), log_signal(lhs), lhs.__width, s.second.c_str(), log_signal(rhs), rhs.__width); + s.first.c_str(), log_signal(lhs), lhs.size(), s.second.c_str(), log_signal(rhs), rhs.size()); log("Import set-constraint: %s = %s\n", log_signal(lhs), log_signal(rhs)); big_lhs.remove2(lhs, &big_rhs); @@ -166,17 +166,17 @@ struct SatHelper RTLIL::SigSpec rem = satgen.initial_state.export_all(); rem.remove(big_lhs); big_lhs.append(rem); - big_rhs.append(RTLIL::SigSpec(RTLIL::State::Sx, rem.__width)); + big_rhs.append(RTLIL::SigSpec(RTLIL::State::Sx, rem.size())); } if (set_init_zero) { RTLIL::SigSpec rem = satgen.initial_state.export_all(); rem.remove(big_lhs); big_lhs.append(rem); - big_rhs.append(RTLIL::SigSpec(RTLIL::State::S0, rem.__width)); + big_rhs.append(RTLIL::SigSpec(RTLIL::State::S0, rem.size())); } - if (big_lhs.__width == 0) { + if (big_lhs.size() == 0) { log("No constraints for initial state found.\n\n"); return; } @@ -209,9 +209,9 @@ struct SatHelper show_signal_pool.add(sigmap(lhs)); show_signal_pool.add(sigmap(rhs)); - if (lhs.__width != rhs.__width) + if (lhs.size() != rhs.size()) log_cmd_error("Set expression with different lhs and rhs sizes: %s (%s, %d bits) vs. %s (%s, %d bits)\n", - s.first.c_str(), log_signal(lhs), lhs.__width, s.second.c_str(), log_signal(rhs), rhs.__width); + s.first.c_str(), log_signal(lhs), lhs.size(), s.second.c_str(), log_signal(rhs), rhs.size()); log("Import set-constraint: %s = %s\n", log_signal(lhs), log_signal(rhs)); big_lhs.remove2(lhs, &big_rhs); @@ -230,9 +230,9 @@ struct SatHelper show_signal_pool.add(sigmap(lhs)); show_signal_pool.add(sigmap(rhs)); - if (lhs.__width != rhs.__width) + if (lhs.size() != rhs.size()) log_cmd_error("Set expression with different lhs and rhs sizes: %s (%s, %d bits) vs. %s (%s, %d bits)\n", - s.first.c_str(), log_signal(lhs), lhs.__width, s.second.c_str(), log_signal(rhs), rhs.__width); + s.first.c_str(), log_signal(lhs), lhs.size(), s.second.c_str(), log_signal(rhs), rhs.size()); log("Import set-constraint for this timestep: %s = %s\n", log_signal(lhs), log_signal(rhs)); big_lhs.remove2(lhs, &big_rhs); @@ -358,9 +358,9 @@ struct SatHelper show_signal_pool.add(sigmap(lhs)); show_signal_pool.add(sigmap(rhs)); - if (lhs.__width != rhs.__width) + if (lhs.size() != rhs.size()) log_cmd_error("Proof expression with different lhs and rhs sizes: %s (%s, %d bits) vs. %s (%s, %d bits)\n", - s.first.c_str(), log_signal(lhs), lhs.__width, s.second.c_str(), log_signal(rhs), rhs.__width); + s.first.c_str(), log_signal(lhs), lhs.size(), s.second.c_str(), log_signal(rhs), rhs.size()); log("Import proof-constraint: %s = %s\n", log_signal(lhs), log_signal(rhs)); big_lhs.remove2(lhs, &big_rhs); @@ -386,9 +386,9 @@ struct SatHelper show_signal_pool.add(sigmap(lhs)); show_signal_pool.add(sigmap(rhs)); - if (lhs.__width != rhs.__width) + if (lhs.size() != rhs.size()) log_cmd_error("Proof-x expression with different lhs and rhs sizes: %s (%s, %d bits) vs. %s (%s, %d bits)\n", - s.first.c_str(), log_signal(lhs), lhs.__width, s.second.c_str(), log_signal(rhs), rhs.__width); + s.first.c_str(), log_signal(lhs), lhs.size(), s.second.c_str(), log_signal(rhs), rhs.size()); log("Import proof-x-constraint: %s = %s\n", log_signal(lhs), log_signal(rhs)); big_lhs.remove2(lhs, &big_rhs); @@ -413,8 +413,8 @@ struct SatHelper satgen.getAsserts(asserts_a, asserts_en, timestep); asserts_a.expand(); asserts_en.expand(); - for (size_t i = 0; i < asserts_a.__chunks.size(); i++) - log("Import proof for assert: %s when %s.\n", log_signal(asserts_a.__chunks[i]), log_signal(asserts_en.__chunks[i])); + for (size_t i = 0; i < asserts_a.chunks().size(); i++) + log("Import proof for assert: %s when %s.\n", log_signal(asserts_a.chunks()[i]), log_signal(asserts_en.chunks()[i])); prove_bits.push_back(satgen.importAsserts(timestep)); } @@ -543,12 +543,12 @@ struct SatHelper std::vector modelUndefExpressions; - for (auto &c : modelSig.__chunks) + for (auto &c : modelSig.chunks()) if (c.wire != NULL) { ModelBlockInfo info; RTLIL::SigSpec chunksig = c; - info.width = chunksig.__width; + info.width = chunksig.size(); info.description = log_signal(chunksig); for (int timestep = -1; timestep <= max_timestep; timestep++) @@ -573,7 +573,7 @@ struct SatHelper // Add initial state signals as collected by satgen // modelSig = satgen.initial_state.export_all(); - for (auto &c : modelSig.__chunks) + for (auto &c : modelSig.chunks()) if (c.wire != NULL) { ModelBlockInfo info; @@ -581,7 +581,7 @@ struct SatHelper info.timestep = 0; info.offset = modelExpressions.size(); - info.width = chunksig.__width; + info.width = chunksig.size(); info.description = log_signal(chunksig); modelInfo.insert(info); diff --git a/passes/sat/share.cc b/passes/sat/share.cc index 95f35bb3e..738b0bd6d 100644 --- a/passes/sat/share.cc +++ b/passes/sat/share.cc @@ -273,11 +273,11 @@ struct ShareWorker RTLIL::SigSpec a2 = c2->connections.at("\\A"); RTLIL::SigSpec y2 = c2->connections.at("\\Y"); - int a_width = std::max(a1.__width, a2.__width); - int y_width = std::max(y1.__width, y2.__width); + int a_width = std::max(a1.size(), a2.size()); + int y_width = std::max(y1.size(), y2.size()); - if (a1.__width != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y"); - if (a2.__width != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y"); + if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y"); + if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y"); RTLIL::SigSpec a = module->Mux(NEW_ID, a2, a1, act); RTLIL::Wire *y = module->addWire(NEW_ID, y_width); @@ -292,8 +292,8 @@ struct ShareWorker supercell->connections["\\Y"] = y; module->add(supercell); - RTLIL::SigSpec new_y1(y, y1.__width); - RTLIL::SigSpec new_y2(y, y2.__width); + RTLIL::SigSpec new_y1(y, y1.size()); + RTLIL::SigSpec new_y2(y, y2.size()); module->connections.push_back(RTLIL::SigSig(y1, new_y1)); module->connections.push_back(RTLIL::SigSig(y2, new_y2)); @@ -367,28 +367,28 @@ struct ShareWorker RTLIL::SigSpec b2 = c2->connections.at("\\B"); RTLIL::SigSpec y2 = c2->connections.at("\\Y"); - int a_width = std::max(a1.__width, a2.__width); - int b_width = std::max(b1.__width, b2.__width); - int y_width = std::max(y1.__width, y2.__width); + int a_width = std::max(a1.size(), a2.size()); + int b_width = std::max(b1.size(), b2.size()); + int y_width = std::max(y1.size(), y2.size()); if (c1->type == "$shr" && a_signed) { a_width = std::max(y_width, a_width); - if (a1.__width < y1.__width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, y1.__width), true)->connections.at("\\Y"); - if (a2.__width < y2.__width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, y2.__width), true)->connections.at("\\Y"); + if (a1.size() < y1.size()) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, y1.size()), true)->connections.at("\\Y"); + if (a2.size() < y2.size()) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, y2.size()), true)->connections.at("\\Y"); - if (a1.__width != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), false)->connections.at("\\Y"); - if (a2.__width != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), false)->connections.at("\\Y"); + if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), false)->connections.at("\\Y"); + if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), false)->connections.at("\\Y"); } else { - if (a1.__width != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y"); - if (a2.__width != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y"); + if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y"); + if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y"); } - if (b1.__width != b_width) b1 = module->addPos(NEW_ID, b1, module->addWire(NEW_ID, b_width), b_signed)->connections.at("\\Y"); - if (b2.__width != b_width) b2 = module->addPos(NEW_ID, b2, module->addWire(NEW_ID, b_width), b_signed)->connections.at("\\Y"); + if (b1.size() != b_width) b1 = module->addPos(NEW_ID, b1, module->addWire(NEW_ID, b_width), b_signed)->connections.at("\\Y"); + if (b2.size() != b_width) b2 = module->addPos(NEW_ID, b2, module->addWire(NEW_ID, b_width), b_signed)->connections.at("\\Y"); RTLIL::SigSpec a = module->Mux(NEW_ID, a2, a1, act); RTLIL::SigSpec b = module->Mux(NEW_ID, b2, b1, act); @@ -405,8 +405,8 @@ struct ShareWorker supercell->connections["\\Y"] = y; supercell->check(); - RTLIL::SigSpec new_y1(y, y1.__width); - RTLIL::SigSpec new_y2(y, y2.__width); + RTLIL::SigSpec new_y1(y, y1.size()); + RTLIL::SigSpec new_y2(y, y2.size()); module->connections.push_back(RTLIL::SigSig(y1, new_y1)); module->connections.push_back(RTLIL::SigSig(y2, new_y2)); @@ -575,7 +575,7 @@ struct ShareWorker if (activation_patterns_cache[cell].empty()) { log("%sFound cell that is never activated: %s\n", indent, log_id(cell)); RTLIL::SigSpec cell_outputs = modwalker.cell_outputs[cell]; - module->connections.push_back(RTLIL::SigSig(cell_outputs, RTLIL::SigSpec(RTLIL::State::Sx, cell_outputs.__width))); + module->connections.push_back(RTLIL::SigSig(cell_outputs, RTLIL::SigSpec(RTLIL::State::Sx, cell_outputs.size()))); cells_to_remove.insert(cell); } @@ -811,10 +811,10 @@ struct ShareWorker int other_cell_select_score = 0; for (auto &p : filtered_cell_activation_patterns) - cell_select_score += p.first.__width; + cell_select_score += p.first.size(); for (auto &p : filtered_other_cell_activation_patterns) - other_cell_select_score += p.first.__width; + other_cell_select_score += p.first.size(); RTLIL::Cell *supercell; if (cell_select_score <= other_cell_select_score) { diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index 7e57aa0f5..a960f2bae 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -133,8 +133,8 @@ namespace needleSig.expand(); haystackSig.expand(); - for (int i = 0; i < std::min(needleSig.__width, haystackSig.__width); i++) { - RTLIL::Wire *needleWire = needleSig.__chunks.at(i).wire, *haystackWire = haystackSig.__chunks.at(i).wire; + for (int i = 0; i < std::min(needleSig.size(), haystackSig.size()); i++) { + RTLIL::Wire *needleWire = needleSig.chunks().at(i).wire, *haystackWire = haystackSig.chunks().at(i).wire; if (needleWire != lastNeedleWire || haystackWire != lastHaystackWire) if (!compareAttributes(wire_attr, needleWire ? needleWire->attributes : emptyAttr, haystackWire ? haystackWire->attributes : emptyAttr)) return false; @@ -193,7 +193,7 @@ namespace RTLIL::SigSpec conn_sig = conn.second; sigmap.apply(conn_sig); conn_sig.expand(); - for (auto &chunk : conn_sig.__chunks) + for (auto &chunk : conn_sig.chunks()) if (chunk.wire != NULL) sig_use_count[std::pair(chunk.wire, chunk.offset)]++; } @@ -213,7 +213,7 @@ namespace for (auto &conn : cell->connections) { - graph.createPort(cell->name, conn.first, conn.second.__width); + graph.createPort(cell->name, conn.first, conn.second.size()); if (split && split->count(std::pair(cell->type, conn.first)) > 0) continue; @@ -222,9 +222,9 @@ namespace sigmap.apply(conn_sig); conn_sig.expand(); - for (size_t i = 0; i < conn_sig.__chunks.size(); i++) + for (size_t i = 0; i < conn_sig.chunks().size(); i++) { - auto &chunk = conn_sig.__chunks[i]; + auto &chunk = conn_sig.chunks()[i]; assert(chunk.width == 1); if (chunk.wire == NULL) { @@ -269,7 +269,7 @@ namespace sigmap.apply(conn_sig); conn_sig.expand(); - for (auto &chunk : conn_sig.__chunks) + for (auto &chunk : conn_sig.chunks()) if (sig_bit_ref.count(chunk) != 0) { bit_ref_t &bit_ref = sig_bit_ref[chunk]; graph.markExtern(bit_ref.cell, bit_ref.port, bit_ref.bit); @@ -287,7 +287,7 @@ namespace sigmap.apply(conn_sig); conn_sig.expand(); - for (auto &chunk : conn_sig.__chunks) + for (auto &chunk : conn_sig.chunks()) if (sig_bit_ref.count(chunk) != 0) { bit_ref_t &bit_ref = sig_bit_ref[chunk]; graph.markExtern(bit_ref.cell, bit_ref.port, bit_ref.bit); @@ -334,8 +334,8 @@ namespace RTLIL::SigSpec sig = sigmap(conn.second); if (mapping.portMapping.count(conn.first) > 0 && sig2port.has(sigmap(sig))) { sig.expand(); - for (int i = 0; i < sig.__width; i++) - for (auto &port : sig2port.find(sig.__chunks[i])) { + for (int i = 0; i < sig.size(); i++) + for (auto &port : sig2port.find(sig.chunks()[i])) { RTLIL::SigSpec bitsig = haystack_cell->connections.at(mapping.portMapping[conn.first]).extract(i, 1); cell->connections.at(port.first).replace(port.second, bitsig); } @@ -729,7 +729,7 @@ struct ExtractPass : public Pass { for (auto cell : cells) for (auto &conn : cell->connections) { RTLIL::SigSpec sig = sigmap(conn.second); - for (auto &chunk : sig.__chunks) + for (auto &chunk : sig.chunks()) if (chunk.wire != NULL) wires.insert(chunk.wire); } @@ -756,7 +756,7 @@ struct ExtractPass : public Pass { newCell->parameters = cell->parameters; for (auto &conn : cell->connections) { RTLIL::SigSpec sig = sigmap(conn.second); - for (auto &chunk : sig.__chunks) + for (auto &chunk : sig.chunks()) if (chunk.wire != NULL) chunk.wire = newMod->wires.at(chunk.wire->name); newCell->connections[conn.first] = sig; diff --git a/passes/techmap/hilomap.cc b/passes/techmap/hilomap.cc index 22f4c7d1d..ac41e47ca 100644 --- a/passes/techmap/hilomap.cc +++ b/passes/techmap/hilomap.cc @@ -31,7 +31,7 @@ static RTLIL::SigChunk last_hi, last_lo; void hilomap_worker(RTLIL::SigSpec &sig) { sig.expand(); - for (auto &c : sig.__chunks) { + for (auto &c : sig.chunks()) { if (c.wire == NULL && (c.data.bits.at(0) == RTLIL::State::S1) && !hicell_celltype.empty()) { if (!singleton_mode || last_hi.width == 0) { last_hi = RTLIL::SigChunk(module->addWire(NEW_ID)); diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc index cef5cc89e..1eb5c063b 100644 --- a/passes/techmap/simplemap.cc +++ b/passes/techmap/simplemap.cc @@ -42,8 +42,8 @@ static void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::Cell *gate = new RTLIL::Cell; gate->name = NEW_ID; gate->type = "$_INV_"; - gate->connections["\\A"] = sig_a.__chunks.at(i); - gate->connections["\\Y"] = sig_y.__chunks.at(i); + gate->connections["\\A"] = sig_a.chunks().at(i); + gate->connections["\\Y"] = sig_y.chunks().at(i); module->add(gate); } } @@ -96,8 +96,8 @@ static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::Cell *gate = new RTLIL::Cell; gate->name = NEW_ID; gate->type = "$_INV_"; - gate->connections["\\A"] = sig_t.__chunks.at(i); - gate->connections["\\Y"] = sig_y.__chunks.at(i); + gate->connections["\\A"] = sig_t.chunks().at(i); + gate->connections["\\Y"] = sig_y.chunks().at(i); module->add(gate); } @@ -115,9 +115,9 @@ static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::Cell *gate = new RTLIL::Cell; gate->name = NEW_ID; gate->type = gate_type; - gate->connections["\\A"] = sig_a.__chunks.at(i); - gate->connections["\\B"] = sig_b.__chunks.at(i); - gate->connections["\\Y"] = sig_y.__chunks.at(i); + gate->connections["\\A"] = sig_a.chunks().at(i); + gate->connections["\\B"] = sig_b.chunks().at(i); + gate->connections["\\Y"] = sig_y.chunks().at(i); module->add(gate); } } @@ -129,20 +129,20 @@ static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::SigSpec sig_y = cell->connections.at("\\Y"); - if (sig_y.__width == 0) + if (sig_y.size() == 0) return; - if (sig_a.__width == 0) { - if (cell->type == "$reduce_and") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.__width))); - if (cell->type == "$reduce_or") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.__width))); - if (cell->type == "$reduce_xor") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.__width))); - if (cell->type == "$reduce_xnor") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.__width))); - if (cell->type == "$reduce_bool") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.__width))); + if (sig_a.size() == 0) { + if (cell->type == "$reduce_and") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size()))); + if (cell->type == "$reduce_or") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size()))); + if (cell->type == "$reduce_xor") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size()))); + if (cell->type == "$reduce_xnor") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size()))); + if (cell->type == "$reduce_bool") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size()))); return; } - if (sig_y.__width > 1) { - module->connections.push_back(RTLIL::SigSig(sig_y.extract(1, sig_y.__width-1), RTLIL::SigSpec(0, sig_y.__width-1))); + if (sig_y.size() > 1) { + module->connections.push_back(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1))); sig_y = sig_y.extract(0, 1); } @@ -156,24 +156,24 @@ static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::SigSpec *last_output = NULL; - while (sig_a.__width > 1) + while (sig_a.size() > 1) { - RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig_a.__width / 2); + RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig_a.size() / 2); sig_t.expand(); - for (int i = 0; i < sig_a.__width; i += 2) + for (int i = 0; i < sig_a.size(); i += 2) { - if (i+1 == sig_a.__width) { - sig_t.append(sig_a.__chunks.at(i)); + if (i+1 == sig_a.size()) { + sig_t.append(sig_a.chunks().at(i)); continue; } RTLIL::Cell *gate = new RTLIL::Cell; gate->name = NEW_ID; gate->type = gate_type; - gate->connections["\\A"] = sig_a.__chunks.at(i); - gate->connections["\\B"] = sig_a.__chunks.at(i+1); - gate->connections["\\Y"] = sig_t.__chunks.at(i/2); + gate->connections["\\A"] = sig_a.chunks().at(i); + gate->connections["\\B"] = sig_a.chunks().at(i+1); + gate->connections["\\Y"] = sig_t.chunks().at(i/2); last_output = &gate->connections["\\Y"]; module->add(gate); } @@ -204,31 +204,31 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig) { sig.expand(); - while (sig.__width > 1) + while (sig.size() > 1) { - RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig.__width / 2); + RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig.size() / 2); sig_t.expand(); - for (int i = 0; i < sig.__width; i += 2) + for (int i = 0; i < sig.size(); i += 2) { - if (i+1 == sig.__width) { - sig_t.append(sig.__chunks.at(i)); + if (i+1 == sig.size()) { + sig_t.append(sig.chunks().at(i)); continue; } RTLIL::Cell *gate = new RTLIL::Cell; gate->name = NEW_ID; gate->type = "$_OR_"; - gate->connections["\\A"] = sig.__chunks.at(i); - gate->connections["\\B"] = sig.__chunks.at(i+1); - gate->connections["\\Y"] = sig_t.__chunks.at(i/2); + gate->connections["\\A"] = sig.chunks().at(i); + gate->connections["\\B"] = sig.chunks().at(i+1); + gate->connections["\\Y"] = sig_t.chunks().at(i/2); module->add(gate); } sig = sig_t; } - if (sig.__width == 0) + if (sig.size() == 0) sig = RTLIL::SigSpec(0, 1); } @@ -239,11 +239,11 @@ static void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::SigSpec sig_y = cell->connections.at("\\Y"); - if (sig_y.__width == 0) + if (sig_y.size() == 0) return; - if (sig_y.__width > 1) { - module->connections.push_back(RTLIL::SigSig(sig_y.extract(1, sig_y.__width-1), RTLIL::SigSpec(0, sig_y.__width-1))); + if (sig_y.size() > 1) { + module->connections.push_back(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1))); sig_y = sig_y.extract(0, 1); } @@ -265,11 +265,11 @@ static void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::SigSpec sig_y = cell->connections.at("\\Y"); - if (sig_y.__width == 0) + if (sig_y.size() == 0) return; - if (sig_y.__width > 1) { - module->connections.push_back(RTLIL::SigSig(sig_y.extract(1, sig_y.__width-1), RTLIL::SigSpec(0, sig_y.__width-1))); + if (sig_y.size() > 1) { + module->connections.push_back(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1))); sig_y = sig_y.extract(0, 1); } @@ -304,10 +304,10 @@ static void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::Cell *gate = new RTLIL::Cell; gate->name = NEW_ID; gate->type = "$_MUX_"; - gate->connections["\\A"] = sig_a.__chunks.at(i); - gate->connections["\\B"] = sig_b.__chunks.at(i); + gate->connections["\\A"] = sig_a.chunks().at(i); + gate->connections["\\B"] = sig_b.chunks().at(i); gate->connections["\\S"] = cell->connections.at("\\S"); - gate->connections["\\Y"] = sig_y.__chunks.at(i); + gate->connections["\\Y"] = sig_y.chunks().at(i); module->add(gate); } } @@ -317,7 +317,7 @@ static void simplemap_slice(RTLIL::Module *module, RTLIL::Cell *cell) int offset = cell->parameters.at("\\OFFSET").as_int(); RTLIL::SigSpec sig_a = cell->connections.at("\\A"); RTLIL::SigSpec sig_y = cell->connections.at("\\Y"); - module->connections.push_back(RTLIL::SigSig(sig_y, sig_a.extract(offset, sig_y.__width))); + module->connections.push_back(RTLIL::SigSig(sig_y, sig_a.extract(offset, sig_y.size()))); } static void simplemap_concat(RTLIL::Module *module, RTLIL::Cell *cell) @@ -349,9 +349,9 @@ static void simplemap_sr(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::Cell *gate = new RTLIL::Cell; gate->name = NEW_ID; gate->type = gate_type; - gate->connections["\\S"] = sig_s.__chunks.at(i); - gate->connections["\\R"] = sig_r.__chunks.at(i); - gate->connections["\\Q"] = sig_q.__chunks.at(i); + gate->connections["\\S"] = sig_s.chunks().at(i); + gate->connections["\\R"] = sig_r.chunks().at(i); + gate->connections["\\Q"] = sig_q.chunks().at(i); module->add(gate); } } @@ -376,8 +376,8 @@ static void simplemap_dff(RTLIL::Module *module, RTLIL::Cell *cell) gate->name = NEW_ID; gate->type = gate_type; gate->connections["\\C"] = sig_clk; - gate->connections["\\D"] = sig_d.__chunks.at(i); - gate->connections["\\Q"] = sig_q.__chunks.at(i); + gate->connections["\\D"] = sig_d.chunks().at(i); + gate->connections["\\Q"] = sig_q.chunks().at(i); module->add(gate); } } @@ -410,10 +410,10 @@ static void simplemap_dffsr(RTLIL::Module *module, RTLIL::Cell *cell) gate->name = NEW_ID; gate->type = gate_type; gate->connections["\\C"] = sig_clk; - gate->connections["\\S"] = sig_s.__chunks.at(i); - gate->connections["\\R"] = sig_r.__chunks.at(i); - gate->connections["\\D"] = sig_d.__chunks.at(i); - gate->connections["\\Q"] = sig_q.__chunks.at(i); + gate->connections["\\S"] = sig_s.chunks().at(i); + gate->connections["\\R"] = sig_r.chunks().at(i); + gate->connections["\\D"] = sig_d.chunks().at(i); + gate->connections["\\Q"] = sig_q.chunks().at(i); module->add(gate); } } @@ -446,8 +446,8 @@ static void simplemap_adff(RTLIL::Module *module, RTLIL::Cell *cell) gate->type = rst_val.at(i) == RTLIL::State::S1 ? gate_type_1 : gate_type_0; gate->connections["\\C"] = sig_clk; gate->connections["\\R"] = sig_rst; - gate->connections["\\D"] = sig_d.__chunks.at(i); - gate->connections["\\Q"] = sig_q.__chunks.at(i); + gate->connections["\\D"] = sig_d.chunks().at(i); + gate->connections["\\Q"] = sig_q.chunks().at(i); module->add(gate); } } @@ -472,8 +472,8 @@ static void simplemap_dlatch(RTLIL::Module *module, RTLIL::Cell *cell) gate->name = NEW_ID; gate->type = gate_type; gate->connections["\\E"] = sig_en; - gate->connections["\\D"] = sig_d.__chunks.at(i); - gate->connections["\\Q"] = sig_q.__chunks.at(i); + gate->connections["\\D"] = sig_d.chunks().at(i); + gate->connections["\\Q"] = sig_q.chunks().at(i); module->add(gate); } } diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index f7d5efa0a..d3e7e20fc 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -41,13 +41,13 @@ static void apply_prefix(std::string prefix, std::string &id) static void apply_prefix(std::string prefix, RTLIL::SigSpec &sig, RTLIL::Module *module) { - for (size_t i = 0; i < sig.__chunks.size(); i++) { - if (sig.__chunks[i].wire == NULL) + for (size_t i = 0; i < sig.chunks().size(); i++) { + if (sig.chunks()[i].wire == NULL) continue; - std::string wire_name = sig.__chunks[i].wire->name; + std::string wire_name = sig.chunks()[i].wire->name; apply_prefix(prefix, wire_name); assert(module->wires.count(wire_name) > 0); - sig.__chunks[i].wire = module->wires[wire_name]; + sig.chunks()[i].wire = module->wires[wire_name]; } } @@ -163,11 +163,11 @@ struct TechmapWorker c.second = it.second; apply_prefix(cell->name, c.first, module); } - if (c.second.__width > c.first.__width) - c.second.remove(c.first.__width, c.second.__width - c.first.__width); - if (c.second.__width < c.first.__width) - c.second.append(RTLIL::SigSpec(RTLIL::State::S0, c.first.__width - c.second.__width)); - assert(c.first.__width == c.second.__width); + if (c.second.size() > c.first.size()) + c.second.remove(c.first.size(), c.second.size() - c.first.size()); + if (c.second.size() < c.first.size()) + c.second.append(RTLIL::SigSpec(RTLIL::State::S0, c.first.size() - c.second.size())); + assert(c.first.size() == c.second.size()); if (flatten_mode) { // more conservative approach: // connect internal and external wires -- cgit v1.2.3 From 28b3fd05fa9cf6d469fdec95e247a7ffe5bc001d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 22 Jul 2014 20:58:44 +0200 Subject: SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw() --- passes/cmds/delete.cc | 2 +- passes/cmds/setundef.cc | 2 +- passes/cmds/show.cc | 4 ++-- passes/cmds/splitnets.cc | 2 +- passes/fsm/fsm_extract.cc | 4 ++-- passes/hierarchy/submod.cc | 2 +- passes/memory/memory_dff.cc | 2 +- passes/opt/opt_const.cc | 9 ++------- passes/proc/proc_arst.cc | 2 +- passes/sat/eval.cc | 4 ++-- passes/techmap/extract.cc | 2 +- passes/techmap/hilomap.cc | 2 +- passes/techmap/techmap.cc | 2 +- 13 files changed, 17 insertions(+), 22 deletions(-) (limited to 'passes') diff --git a/passes/cmds/delete.cc b/passes/cmds/delete.cc index c5aa196c6..f433c4b4a 100644 --- a/passes/cmds/delete.cc +++ b/passes/cmds/delete.cc @@ -28,7 +28,7 @@ struct DeleteWireWorker void operator()(RTLIL::SigSpec &sig) { sig.optimize(); - for (auto &c : sig.chunks()) + for (auto &c : sig.chunks_rw()) if (c.wire != NULL && delete_wires_p->count(c.wire->name)) { c.wire = module->addWire(NEW_ID, c.width); c.offset = 0; diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index 7558a4e9a..619930b3a 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -48,7 +48,7 @@ struct SetundefWorker void operator()(RTLIL::SigSpec &sig) { sig.expand(); - for (auto &c : sig.chunks()) + for (auto &c : sig.chunks_rw()) if (c.wire == NULL && c.data.bits.at(0) > RTLIL::State::S1) c.data.bits.at(0) = next_bit(); sig.optimize(); diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index fde96d537..37fe44047 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -179,7 +179,7 @@ struct ShowWorker } if (sig.chunks().size() == 1) { - RTLIL::SigChunk &c = sig.chunks()[0]; + const RTLIL::SigChunk &c = sig.chunks()[0]; if (c.wire != NULL && design->selected_member(module->name, c.wire->name)) { if (!range_check || c.wire->width == c.width) return stringf("n%d", id2num(c.wire->name)); @@ -203,7 +203,7 @@ struct ShowWorker int pos = sig.size()-1; int idx = single_idx_count++; for (int i = int(sig.chunks().size())-1; i >= 0; i--) { - RTLIL::SigChunk &c = sig.chunks()[i]; + const RTLIL::SigChunk &c = sig.chunks()[i]; net = gen_signode_simple(c, false); assert(!net.empty()); if (driver) { diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc index 8cc6a5152..d71e9727c 100644 --- a/passes/cmds/splitnets.cc +++ b/passes/cmds/splitnets.cc @@ -63,7 +63,7 @@ struct SplitnetsWorker void operator()(RTLIL::SigSpec &sig) { sig.expand(); - for (auto &c : sig.chunks()) + for (auto &c : sig.chunks_rw()) if (splitmap.count(c.wire) > 0) c = splitmap.at(c.wire).at(c.offset); sig.optimize(); diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index 701b09bd8..c3bb1933a 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -92,7 +92,7 @@ static RTLIL::Const sig2const(ConstEval &ce, RTLIL::SigSpec sig, RTLIL::State no { if (dont_care.size() > 0) { sig.expand(); - for (auto &chunk : sig.chunks()) { + for (auto &chunk : sig.chunks_rw()) { assert(chunk.width == 1); if (dont_care.extract(chunk).size() > 0) chunk.wire = NULL, chunk.data = RTLIL::Const(noconst_state); @@ -104,7 +104,7 @@ static RTLIL::Const sig2const(ConstEval &ce, RTLIL::SigSpec sig, RTLIL::State no ce.values_map.apply(sig); sig.expand(); - for (auto &chunk : sig.chunks()) { + for (auto &chunk : sig.chunks_rw()) { assert(chunk.width == 1); if (chunk.wire != NULL) chunk.wire = NULL, chunk.data = RTLIL::Const(noconst_state); diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index fa8043c89..b983a840e 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -164,7 +164,7 @@ struct SubmodWorker for (RTLIL::Cell *cell : submod.cells) { RTLIL::Cell *new_cell = new RTLIL::Cell(*cell); for (auto &conn : new_cell->connections) - for (auto &c : conn.second.chunks()) + for (auto &c : conn.second.chunks_rw()) if (c.wire != NULL) { assert(wire_flags.count(c.wire) > 0); c.wire = wire_flags[c.wire].new_wire; diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index 8bae24cff..dee48597f 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -36,7 +36,7 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI for (size_t i = 0; i < sig.chunks().size(); i++) { - RTLIL::SigChunk &chunk = sig.chunks()[i]; + RTLIL::SigChunk &chunk = sig.chunks_rw()[i]; if (chunk.wire == NULL) continue; diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index 1a1f0fe42..9b89291b1 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -699,10 +699,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo RTLIL::SigSpec a = cell->connections["\\A"]; \ assign_map.apply(a); \ if (a.is_fully_const()) { \ - a.optimize(); \ - if (a.chunks().empty()) a.chunks().push_back(RTLIL::SigChunk()); \ RTLIL::Const dummy_arg(RTLIL::State::S0, 1); \ - RTLIL::SigSpec y(RTLIL::const_ ## _t(a.chunks()[0].data, dummy_arg, \ + RTLIL::SigSpec y(RTLIL::const_ ## _t(a.as_const(), dummy_arg, \ cell->parameters["\\A_SIGNED"].as_bool(), false, \ cell->parameters["\\Y_WIDTH"].as_int())); \ replace_cell(module, cell, stringf("%s", log_signal(a)), "\\Y", y); \ @@ -715,10 +713,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo RTLIL::SigSpec b = cell->connections["\\B"]; \ assign_map.apply(a), assign_map.apply(b); \ if (a.is_fully_const() && b.is_fully_const()) { \ - a.optimize(), b.optimize(); \ - if (a.chunks().empty()) a.chunks().push_back(RTLIL::SigChunk()); \ - if (b.chunks().empty()) b.chunks().push_back(RTLIL::SigChunk()); \ - RTLIL::SigSpec y(RTLIL::const_ ## _t(a.chunks()[0].data, b.chunks()[0].data, \ + RTLIL::SigSpec y(RTLIL::const_ ## _t(a.as_const(), b.as_const(), \ cell->parameters["\\A_SIGNED"].as_bool(), \ cell->parameters["\\B_SIGNED"].as_bool(), \ cell->parameters["\\Y_WIDTH"].as_int())); \ diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc index b5763508a..6cb560f5c 100644 --- a/passes/proc/proc_arst.cc +++ b/passes/proc/proc_arst.cc @@ -168,7 +168,7 @@ restart_proc_arst: rspec.expand(), rval.expand(); for (int i = 0; i < int(rspec.chunks().size()); i++) if (rspec.chunks()[i].wire == NULL) - rval.chunks()[i] = rspec.chunks()[i]; + rval.chunks_rw()[i] = rspec.chunks()[i]; rspec.optimize(), rval.optimize(); RTLIL::SigSpec last_rval; for (int count = 0; rval != last_rval; count++) { diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc index 03a86246c..73235e930 100644 --- a/passes/sat/eval.cc +++ b/passes/sat/eval.cc @@ -73,7 +73,7 @@ struct BruteForceEquivChecker sig1.expand(), sig2.expand(); for (size_t i = 0; i < sig1.chunks().size(); i++) if (sig1.chunks().at(i) == RTLIL::SigChunk(RTLIL::State::Sx)) - sig2.chunks().at(i) = RTLIL::SigChunk(RTLIL::State::Sx); + sig2.chunks_rw().at(i) = RTLIL::SigChunk(RTLIL::State::Sx); sig1.optimize(), sig2.optimize(); } @@ -299,7 +299,7 @@ struct VlogHammerReporter log_error("Output (y) has a different width in module %s compared to rtl!\n", RTLIL::id2cstr(module->name)); for (int i = 0; i < sig.size(); i++) if (rtl_sig.chunks().at(i).data.bits.at(0) == RTLIL::State::Sx) - sig.chunks().at(i).data.bits.at(0) = RTLIL::State::Sx; + sig.chunks_rw().at(i).data.bits.at(0) = RTLIL::State::Sx; } log("++RPT++ %d%s %s %s\n", idx, input_pattern_list.c_str(), sig.as_const().as_string().c_str(), module_name.c_str()); diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index a960f2bae..5a7298087 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -756,7 +756,7 @@ struct ExtractPass : public Pass { newCell->parameters = cell->parameters; for (auto &conn : cell->connections) { RTLIL::SigSpec sig = sigmap(conn.second); - for (auto &chunk : sig.chunks()) + for (auto &chunk : sig.chunks_rw()) if (chunk.wire != NULL) chunk.wire = newMod->wires.at(chunk.wire->name); newCell->connections[conn.first] = sig; diff --git a/passes/techmap/hilomap.cc b/passes/techmap/hilomap.cc index ac41e47ca..53c5d1044 100644 --- a/passes/techmap/hilomap.cc +++ b/passes/techmap/hilomap.cc @@ -31,7 +31,7 @@ static RTLIL::SigChunk last_hi, last_lo; void hilomap_worker(RTLIL::SigSpec &sig) { sig.expand(); - for (auto &c : sig.chunks()) { + for (auto &c : sig.chunks_rw()) { if (c.wire == NULL && (c.data.bits.at(0) == RTLIL::State::S1) && !hicell_celltype.empty()) { if (!singleton_mode || last_hi.width == 0) { last_hi = RTLIL::SigChunk(module->addWire(NEW_ID)); diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index d3e7e20fc..f3b1a0ef7 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -47,7 +47,7 @@ static void apply_prefix(std::string prefix, RTLIL::SigSpec &sig, RTLIL::Module std::string wire_name = sig.chunks()[i].wire->name; apply_prefix(prefix, wire_name); assert(module->wires.count(wire_name) > 0); - sig.chunks()[i].wire = module->wires[wire_name]; + sig.chunks_rw()[i].wire = module->wires[wire_name]; } } -- cgit v1.2.3 From e7e30f1c86d978131a5f4c6e62b5b8d822696cd1 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 22 Jul 2014 22:52:57 +0200 Subject: fixed memory leak in fsm_opt --- passes/fsm/fsm_opt.cc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/fsm/fsm_opt.cc b/passes/fsm/fsm_opt.cc index 367b38eb1..d5a9b71fa 100644 --- a/passes/fsm/fsm_opt.cc +++ b/passes/fsm/fsm_opt.cc @@ -44,8 +44,10 @@ struct FsmOpt char *str = strdup(wire->attributes["\\unused_bits"].decode_string().c_str()); for (char *tok = strtok(str, " "); tok != NULL; tok = strtok(NULL, " ")) { - if (tok[0] && bit == atoi(tok)) + if (tok[0] && bit == atoi(tok)) { + free(str); return true; + } } free(str); -- cgit v1.2.3 From 65a939cb2767623b95adcd2ec5e783b828c1f9eb Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 22 Jul 2014 22:54:39 +0200 Subject: Fixed memory corruption with new SigSpec API in proc_mux --- passes/proc/proc_mux.cc | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) (limited to 'passes') diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc index cd459d949..50ba8fa1e 100644 --- a/passes/proc/proc_mux.cc +++ b/passes/proc/proc_mux.cc @@ -68,20 +68,16 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, for (auto comp : compare) { RTLIL::SigSpec sig = signal; - sig.expand(); - comp.expand(); // get rid of don't-care bits assert(sig.size() == comp.size()); for (int i = 0; i < comp.size(); i++) - if (comp.chunks()[i].wire == NULL && comp.chunks()[i].data.bits[0] == RTLIL::State::Sa) { - sig.remove(i, 1); - comp.remove(i--, 1); + if (comp[i] == RTLIL::State::Sa) { + sig.remove(i); + comp.remove(i--); } if (comp.size() == 0) return RTLIL::SigSpec(); - sig.optimize(); - comp.optimize(); if (sig.size() == 1 && comp == RTLIL::SigSpec(1,1)) { -- cgit v1.2.3 From 4a6d234ec7acff085e3c923d3872d0863c766ad1 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 22 Jul 2014 23:07:42 +0200 Subject: SigSpec refactoring: cleanup of old SigSpec usage in fsm_* commands --- passes/fsm/fsm_extract.cc | 31 +++++++++---------------------- passes/fsm/fsm_opt.cc | 12 ++++-------- passes/fsm/fsmdata.h | 14 ++++++-------- 3 files changed, 19 insertions(+), 38 deletions(-) (limited to 'passes') diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index c3bb1933a..dfd025a51 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -43,11 +43,9 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL assign_map.apply(sig); if (sig.is_fully_const()) { - sig.optimize(); - assert(sig.chunks().size() == 1); - if (states.count(sig.chunks()[0].data) == 0) { + if (states.count(sig.as_const()) == 0) { log(" found state code: %s\n", log_signal(sig)); - states[sig.chunks()[0].data] = -1; + states[sig.as_const()] = -1; } return true; } @@ -91,30 +89,19 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL static RTLIL::Const sig2const(ConstEval &ce, RTLIL::SigSpec sig, RTLIL::State noconst_state, RTLIL::SigSpec dont_care = RTLIL::SigSpec()) { if (dont_care.size() > 0) { - sig.expand(); - for (auto &chunk : sig.chunks_rw()) { - assert(chunk.width == 1); - if (dont_care.extract(chunk).size() > 0) - chunk.wire = NULL, chunk.data = RTLIL::Const(noconst_state); - } - sig.optimize(); + for (int i = 0; i < SIZE(sig); i++) + if (dont_care.extract(sig[i]).size() > 0) + sig[i] = noconst_state; } ce.assign_map.apply(sig); ce.values_map.apply(sig); - sig.expand(); - for (auto &chunk : sig.chunks_rw()) { - assert(chunk.width == 1); - if (chunk.wire != NULL) - chunk.wire = NULL, chunk.data = RTLIL::Const(noconst_state); - } - sig.optimize(); + for (int i = 0; i < SIZE(sig); i++) + if (sig[i].wire != NULL) + sig[i] = noconst_state; - if (sig.size() == 0) - return RTLIL::Const(); - assert(sig.chunks().size() == 1 && sig.chunks()[0].wire == NULL); - return sig.chunks()[0].data; + return sig.as_const(); } static void find_transitions(ConstEval &ce, ConstEval &ce_nostop, FsmData &fsm_data, std::map &states, int state_in, RTLIL::SigSpec ctrl_in, RTLIL::SigSpec ctrl_out, RTLIL::SigSpec dff_in, RTLIL::SigSpec dont_care) diff --git a/passes/fsm/fsm_opt.cc b/passes/fsm/fsm_opt.cc index d5a9b71fa..efa61245a 100644 --- a/passes/fsm/fsm_opt.cc +++ b/passes/fsm/fsm_opt.cc @@ -33,18 +33,14 @@ struct FsmOpt bool signal_is_unused(RTLIL::SigSpec sig) { - assert(sig.size() == 1); - sig.optimize(); + RTLIL::SigBit bit = sig.to_single_sigbit(); - RTLIL::Wire *wire = sig.chunks()[0].wire; - int bit = sig.chunks()[0].offset; - - if (!wire || wire->attributes.count("\\unused_bits") == 0) + if (bit.wire == NULL || bit.wire->attributes.count("\\unused_bits") == 0) return false; - char *str = strdup(wire->attributes["\\unused_bits"].decode_string().c_str()); + char *str = strdup(bit.wire->attributes["\\unused_bits"].decode_string().c_str()); for (char *tok = strtok(str, " "); tok != NULL; tok = strtok(NULL, " ")) { - if (tok[0] && bit == atoi(tok)) { + if (tok[0] && bit.offset == atoi(tok)) { free(str); return true; } diff --git a/passes/fsm/fsmdata.h b/passes/fsm/fsmdata.h index 718b97043..d0be71c5b 100644 --- a/passes/fsm/fsmdata.h +++ b/passes/fsm/fsmdata.h @@ -142,26 +142,24 @@ struct FsmData log("\n"); log(" Input signals:\n"); RTLIL::SigSpec sig_in = cell->connections["\\CTRL_IN"]; - sig_in.expand(); - for (size_t i = 0; i < sig_in.chunks().size(); i++) - log(" %3zd: %s\n", i, log_signal(sig_in.chunks()[i])); + for (int i = 0; i < SIZE(sig_in); i++) + log(" %3zd: %s\n", i, log_signal(sig_in[i])); log("\n"); log(" Output signals:\n"); RTLIL::SigSpec sig_out = cell->connections["\\CTRL_OUT"]; - sig_out.expand(); - for (size_t i = 0; i < sig_out.chunks().size(); i++) - log(" %3zd: %s\n", i, log_signal(sig_out.chunks()[i])); + for (int i = 0; i < SIZE(sig_out); i++) + log(" %3zd: %s\n", i, log_signal(sig_out[i])); log("\n"); log(" State encoding:\n"); - for (size_t i = 0; i < state_table.size(); i++) + for (int i = 0; i < SIZE(state_table); i++) log(" %3zd: %10s%s\n", i, log_signal(state_table[i], false), int(i) == reset_state ? " " : ""); log("\n"); log(" Transition Table (state_in, ctrl_in, state_out, ctrl_out):\n"); - for (size_t i = 0; i < transition_table.size(); i++) { + for (int i = 0; i < SIZE(transition_table); i++) { transition_t &tr = transition_table[i]; log(" %5zd: %5d %s -> %5d %s\n", i, tr.state_in, log_signal(tr.ctrl_in), tr.state_out, log_signal(tr.ctrl_out)); } -- cgit v1.2.3 From 260c19ec5a3adb292158658dd69a352b9325ab64 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 23 Jul 2014 09:00:16 +0200 Subject: Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3 --- passes/abc/abc.cc | 2 +- passes/sat/share.cc | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) (limited to 'passes') diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index 2d921b7be..e7371ec52 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -466,7 +466,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std clk_str = clk_str.substr(1); } if (module->wires.count(RTLIL::escape_id(clk_str)) != 0) - clk_sig = assign_map(RTLIL::SigSpec(module->wires.at(RTLIL::escape_id(clk_str)), 1)); + clk_sig = assign_map(RTLIL::SigSpec(module->wires.at(RTLIL::escape_id(clk_str)), 1, 0)); } if (dff_mode && clk_sig.size() == 0) diff --git a/passes/sat/share.cc b/passes/sat/share.cc index 738b0bd6d..724bc3f98 100644 --- a/passes/sat/share.cc +++ b/passes/sat/share.cc @@ -292,8 +292,8 @@ struct ShareWorker supercell->connections["\\Y"] = y; module->add(supercell); - RTLIL::SigSpec new_y1(y, y1.size()); - RTLIL::SigSpec new_y2(y, y2.size()); + RTLIL::SigSpec new_y1(y, y1.size(), 0); + RTLIL::SigSpec new_y2(y, y2.size(), 0); module->connections.push_back(RTLIL::SigSig(y1, new_y1)); module->connections.push_back(RTLIL::SigSig(y2, new_y2)); @@ -405,8 +405,8 @@ struct ShareWorker supercell->connections["\\Y"] = y; supercell->check(); - RTLIL::SigSpec new_y1(y, y1.size()); - RTLIL::SigSpec new_y2(y, y2.size()); + RTLIL::SigSpec new_y1(y, y1.size(), 0); + RTLIL::SigSpec new_y2(y, y2.size(), 0); module->connections.push_back(RTLIL::SigSig(y1, new_y1)); module->connections.push_back(RTLIL::SigSig(y2, new_y2)); -- cgit v1.2.3 From a8d3a68971ccc4e47c54a906aae374a9a54b1415 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 23 Jul 2014 08:40:31 +0200 Subject: Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3 --- passes/abc/abc.cc | 2 +- passes/fsm/fsm_map.cc | 16 ++++++++-------- passes/memory/memory_share.cc | 2 +- passes/opt/opt_clean.cc | 2 +- passes/proc/proc_mux.cc | 4 ++-- passes/sat/eval.cc | 4 ++-- passes/sat/miter.cc | 2 +- passes/sat/share.cc | 10 +++++----- passes/techmap/extract.cc | 2 +- passes/techmap/iopadmap.cc | 4 ++-- 10 files changed, 24 insertions(+), 24 deletions(-) (limited to 'passes') diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index e7371ec52..fa2c49604 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -466,7 +466,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std clk_str = clk_str.substr(1); } if (module->wires.count(RTLIL::escape_id(clk_str)) != 0) - clk_sig = assign_map(RTLIL::SigSpec(module->wires.at(RTLIL::escape_id(clk_str)), 1, 0)); + clk_sig = assign_map(RTLIL::SigSpec::grml(module->wires.at(RTLIL::escape_id(clk_str)), 0)); } if (dff_mode && clk_sig.size() == 0) diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc index f8ffee523..1ac9664ad 100644 --- a/passes/fsm/fsm_map.cc +++ b/passes/fsm/fsm_map.cc @@ -30,7 +30,7 @@ static void implement_pattern_cache(RTLIL::Module *module, std::mapconnections.push_back(RTLIL::SigSig(RTLIL::SigSpec(state_onehot, 1, i), sig_a)); + module->connections.push_back(RTLIL::SigSig(RTLIL::SigSpec::grml(state_onehot, i), sig_a)); } else { @@ -234,7 +234,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) eq_cell->type = "$eq"; eq_cell->connections["\\A"] = sig_a; eq_cell->connections["\\B"] = sig_b; - eq_cell->connections["\\Y"] = RTLIL::SigSpec(state_onehot, 1, i); + eq_cell->connections["\\Y"] = RTLIL::SigSpec::grml(state_onehot, i); eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false); eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false); eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_a.size()); @@ -266,7 +266,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) fullstate_cache.erase(tr.state_in); } - implement_pattern_cache(module, pattern_cache, fullstate_cache, fsm_data.state_table.size(), state_onehot, ctrl_in, RTLIL::SigSpec(next_state_onehot, 1, i)); + implement_pattern_cache(module, pattern_cache, fullstate_cache, fsm_data.state_table.size(), state_onehot, ctrl_in, RTLIL::SigSpec::grml(next_state_onehot, i)); } if (encoding_is_onehot) @@ -279,7 +279,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) if (state.bits[j] == RTLIL::State::S1) bit_idx = j; if (bit_idx >= 0) - next_state_sig.replace(bit_idx, RTLIL::SigSpec(next_state_onehot, 1, i)); + next_state_sig.replace(bit_idx, RTLIL::SigSpec::grml(next_state_onehot, i)); } log_assert(!next_state_sig.has_marked_bits()); module->connections.push_back(RTLIL::SigSig(next_state_wire, next_state_sig)); @@ -297,7 +297,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) sig_a = RTLIL::SigSpec(state); } else { sig_b.append(RTLIL::SigSpec(state)); - sig_s.append(RTLIL::SigSpec(next_state_onehot, 1, i)); + sig_s.append(RTLIL::SigSpec::grml(next_state_onehot, i)); } } diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index 5c349f702..45c01f74a 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -613,7 +613,7 @@ struct MemoryShareWorker groups_en[key] = grouped_en->width; grouped_en->width++; } - en.append(RTLIL::SigSpec(grouped_en, 1, groups_en[key])); + en.append(RTLIL::SigSpec::grml(grouped_en, groups_en[key])); } module->addMux(NEW_ID, grouped_last_en, grouped_this_en, this_en_active, grouped_en); diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 68fb2e72c..165bb25c9 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -189,7 +189,7 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool for (auto &it : module->wires) { RTLIL::Wire *wire = it.second; for (int i = 0; i < wire->width; i++) { - RTLIL::SigSpec s1 = RTLIL::SigSpec(wire, 1, i), s2 = assign_map(s1); + RTLIL::SigSpec s1 = RTLIL::SigSpec::grml(wire, i), s2 = assign_map(s1); if (!compare_signals(s1, s2, register_signals, connected_signals, direct_wires)) assign_map.add(s1); } diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc index 50ba8fa1e..0fe765732 100644 --- a/passes/proc/proc_mux.cc +++ b/passes/proc/proc_mux.cc @@ -81,7 +81,7 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, if (sig.size() == 1 && comp == RTLIL::SigSpec(1,1)) { - mod->connections.push_back(RTLIL::SigSig(RTLIL::SigSpec(cmp_wire, 1, cmp_wire->width++), sig)); + mod->connections.push_back(RTLIL::SigSig(RTLIL::SigSpec::grml(cmp_wire, cmp_wire->width++), sig)); } else { @@ -103,7 +103,7 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, eq_cell->connections["\\A"] = sig; eq_cell->connections["\\B"] = comp; - eq_cell->connections["\\Y"] = RTLIL::SigSpec(cmp_wire, 1, cmp_wire->width++); + eq_cell->connections["\\Y"] = RTLIL::SigSpec::grml(cmp_wire, cmp_wire->width++); } } diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc index 73235e930..91b428126 100644 --- a/passes/sat/eval.cc +++ b/passes/sat/eval.cc @@ -260,8 +260,8 @@ struct VlogHammerReporter for (int i = 0; i < int(inputs.size()); i++) { RTLIL::Wire *wire = module->wires.at(inputs[i]); for (int j = input_widths[i]-1; j >= 0; j--) { - ce.set(RTLIL::SigSpec(wire, 1, j), bits.back()); - recorded_set_vars.append(RTLIL::SigSpec(wire, 1, j)); + ce.set(RTLIL::SigSpec::grml(wire, j), bits.back()); + recorded_set_vars.append(RTLIL::SigSpec::grml(wire, j)); recorded_set_vals.bits.push_back(bits.back()); bits.pop_back(); } diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index 79857c5ea..51cf3ae0d 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -174,7 +174,7 @@ static void create_miter_equiv(struct Pass *that, std::vector args, eqx_cell->parameters["\\Y_WIDTH"] = 1; eqx_cell->parameters["\\A_SIGNED"] = 0; eqx_cell->parameters["\\B_SIGNED"] = 0; - eqx_cell->connections["\\A"] = RTLIL::SigSpec(w2_gold, 1, i); + eqx_cell->connections["\\A"] = RTLIL::SigSpec::grml(w2_gold, i); eqx_cell->connections["\\B"] = RTLIL::State::Sx; eqx_cell->connections["\\Y"] = gold_x.extract(i, 1); miter_module->add(eqx_cell); diff --git a/passes/sat/share.cc b/passes/sat/share.cc index 724bc3f98..c209e8ed7 100644 --- a/passes/sat/share.cc +++ b/passes/sat/share.cc @@ -292,8 +292,8 @@ struct ShareWorker supercell->connections["\\Y"] = y; module->add(supercell); - RTLIL::SigSpec new_y1(y, y1.size(), 0); - RTLIL::SigSpec new_y2(y, y2.size(), 0); + RTLIL::SigSpec new_y1 = RTLIL::SigSpec::grml(y, 0, y1.size()); + RTLIL::SigSpec new_y2 = RTLIL::SigSpec::grml(y, 0, y2.size()); module->connections.push_back(RTLIL::SigSig(y1, new_y1)); module->connections.push_back(RTLIL::SigSig(y2, new_y2)); @@ -405,8 +405,8 @@ struct ShareWorker supercell->connections["\\Y"] = y; supercell->check(); - RTLIL::SigSpec new_y1(y, y1.size(), 0); - RTLIL::SigSpec new_y2(y, y2.size(), 0); + RTLIL::SigSpec new_y1 = RTLIL::SigSpec::grml(y, 0, y1.size()); + RTLIL::SigSpec new_y2 = RTLIL::SigSpec::grml(y, 0, y2.size()); module->connections.push_back(RTLIL::SigSig(y1, new_y1)); module->connections.push_back(RTLIL::SigSig(y2, new_y2)); @@ -620,7 +620,7 @@ struct ShareWorker RTLIL::Wire *all_cases_wire = module->addWire(NEW_ID, 0); for (auto &p : activation_patterns) { all_cases_wire->width++; - module->addEq(NEW_ID, p.first, p.second, RTLIL::SigSpec(all_cases_wire, 1, all_cases_wire->width - 1)); + module->addEq(NEW_ID, p.first, p.second, RTLIL::SigSpec::grml(all_cases_wire, all_cases_wire->width - 1)); } if (all_cases_wire->width == 1) return all_cases_wire; diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index 5a7298087..988917b17 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -315,7 +315,7 @@ namespace RTLIL::Wire *wire = it.second; if (wire->port_id > 0) { for (int i = 0; i < wire->width; i++) - sig2port.insert(sigmap(RTLIL::SigSpec(wire, 1, i)), std::pair(wire->name, i)); + sig2port.insert(sigmap(RTLIL::SigSpec::grml(wire, i)), std::pair(wire->name, i)); cell->connections[wire->name] = RTLIL::SigSpec(RTLIL::State::Sz, wire->width); } } diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc index eb2757f66..2cb76014c 100644 --- a/passes/techmap/iopadmap.cc +++ b/passes/techmap/iopadmap.cc @@ -179,9 +179,9 @@ struct IopadmapPass : public Pass { RTLIL::Cell *cell = new RTLIL::Cell; cell->name = NEW_ID; cell->type = RTLIL::escape_id(celltype); - cell->connections[RTLIL::escape_id(portname)] = RTLIL::SigSpec(wire, 1, i); + cell->connections[RTLIL::escape_id(portname)] = RTLIL::SigSpec::grml(wire, i); if (!portname2.empty()) - cell->connections[RTLIL::escape_id(portname2)] = RTLIL::SigSpec(new_wire, 1, i); + cell->connections[RTLIL::escape_id(portname2)] = RTLIL::SigSpec::grml(new_wire, i); if (!widthparam.empty()) cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(1); if (!nameparam.empty()) -- cgit v1.2.3 From ec923652e2eb721aa16657e54a67666f855c3d65 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 23 Jul 2014 09:48:26 +0200 Subject: Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3 --- passes/abc/abc.cc | 2 +- passes/fsm/fsm_map.cc | 16 ++++++++-------- passes/memory/memory_share.cc | 2 +- passes/opt/opt_clean.cc | 2 +- passes/proc/proc_mux.cc | 4 ++-- passes/sat/eval.cc | 4 ++-- passes/sat/miter.cc | 2 +- passes/sat/share.cc | 10 +++++----- passes/techmap/extract.cc | 2 +- passes/techmap/iopadmap.cc | 4 ++-- 10 files changed, 24 insertions(+), 24 deletions(-) (limited to 'passes') diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index fa2c49604..8cdd39b7a 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -466,7 +466,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std clk_str = clk_str.substr(1); } if (module->wires.count(RTLIL::escape_id(clk_str)) != 0) - clk_sig = assign_map(RTLIL::SigSpec::grml(module->wires.at(RTLIL::escape_id(clk_str)), 0)); + clk_sig = assign_map(RTLIL::SigSpec(module->wires.at(RTLIL::escape_id(clk_str)), 0)); } if (dff_mode && clk_sig.size() == 0) diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc index 1ac9664ad..9dda2ba89 100644 --- a/passes/fsm/fsm_map.cc +++ b/passes/fsm/fsm_map.cc @@ -30,7 +30,7 @@ static void implement_pattern_cache(RTLIL::Module *module, std::mapconnections.push_back(RTLIL::SigSig(RTLIL::SigSpec::grml(state_onehot, i), sig_a)); + module->connections.push_back(RTLIL::SigSig(RTLIL::SigSpec(state_onehot, i), sig_a)); } else { @@ -234,7 +234,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) eq_cell->type = "$eq"; eq_cell->connections["\\A"] = sig_a; eq_cell->connections["\\B"] = sig_b; - eq_cell->connections["\\Y"] = RTLIL::SigSpec::grml(state_onehot, i); + eq_cell->connections["\\Y"] = RTLIL::SigSpec(state_onehot, i); eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false); eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false); eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_a.size()); @@ -266,7 +266,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) fullstate_cache.erase(tr.state_in); } - implement_pattern_cache(module, pattern_cache, fullstate_cache, fsm_data.state_table.size(), state_onehot, ctrl_in, RTLIL::SigSpec::grml(next_state_onehot, i)); + implement_pattern_cache(module, pattern_cache, fullstate_cache, fsm_data.state_table.size(), state_onehot, ctrl_in, RTLIL::SigSpec(next_state_onehot, i)); } if (encoding_is_onehot) @@ -279,7 +279,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) if (state.bits[j] == RTLIL::State::S1) bit_idx = j; if (bit_idx >= 0) - next_state_sig.replace(bit_idx, RTLIL::SigSpec::grml(next_state_onehot, i)); + next_state_sig.replace(bit_idx, RTLIL::SigSpec(next_state_onehot, i)); } log_assert(!next_state_sig.has_marked_bits()); module->connections.push_back(RTLIL::SigSig(next_state_wire, next_state_sig)); @@ -297,7 +297,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) sig_a = RTLIL::SigSpec(state); } else { sig_b.append(RTLIL::SigSpec(state)); - sig_s.append(RTLIL::SigSpec::grml(next_state_onehot, i)); + sig_s.append(RTLIL::SigSpec(next_state_onehot, i)); } } diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index 45c01f74a..38eff9961 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -613,7 +613,7 @@ struct MemoryShareWorker groups_en[key] = grouped_en->width; grouped_en->width++; } - en.append(RTLIL::SigSpec::grml(grouped_en, groups_en[key])); + en.append(RTLIL::SigSpec(grouped_en, groups_en[key])); } module->addMux(NEW_ID, grouped_last_en, grouped_this_en, this_en_active, grouped_en); diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 165bb25c9..23fc48d5d 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -189,7 +189,7 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool for (auto &it : module->wires) { RTLIL::Wire *wire = it.second; for (int i = 0; i < wire->width; i++) { - RTLIL::SigSpec s1 = RTLIL::SigSpec::grml(wire, i), s2 = assign_map(s1); + RTLIL::SigSpec s1 = RTLIL::SigSpec(wire, i), s2 = assign_map(s1); if (!compare_signals(s1, s2, register_signals, connected_signals, direct_wires)) assign_map.add(s1); } diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc index 0fe765732..804c51fd3 100644 --- a/passes/proc/proc_mux.cc +++ b/passes/proc/proc_mux.cc @@ -81,7 +81,7 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, if (sig.size() == 1 && comp == RTLIL::SigSpec(1,1)) { - mod->connections.push_back(RTLIL::SigSig(RTLIL::SigSpec::grml(cmp_wire, cmp_wire->width++), sig)); + mod->connections.push_back(RTLIL::SigSig(RTLIL::SigSpec(cmp_wire, cmp_wire->width++), sig)); } else { @@ -103,7 +103,7 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, eq_cell->connections["\\A"] = sig; eq_cell->connections["\\B"] = comp; - eq_cell->connections["\\Y"] = RTLIL::SigSpec::grml(cmp_wire, cmp_wire->width++); + eq_cell->connections["\\Y"] = RTLIL::SigSpec(cmp_wire, cmp_wire->width++); } } diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc index 91b428126..902dedb62 100644 --- a/passes/sat/eval.cc +++ b/passes/sat/eval.cc @@ -260,8 +260,8 @@ struct VlogHammerReporter for (int i = 0; i < int(inputs.size()); i++) { RTLIL::Wire *wire = module->wires.at(inputs[i]); for (int j = input_widths[i]-1; j >= 0; j--) { - ce.set(RTLIL::SigSpec::grml(wire, j), bits.back()); - recorded_set_vars.append(RTLIL::SigSpec::grml(wire, j)); + ce.set(RTLIL::SigSpec(wire, j), bits.back()); + recorded_set_vars.append(RTLIL::SigSpec(wire, j)); recorded_set_vals.bits.push_back(bits.back()); bits.pop_back(); } diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index 51cf3ae0d..12384e2cc 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -174,7 +174,7 @@ static void create_miter_equiv(struct Pass *that, std::vector args, eqx_cell->parameters["\\Y_WIDTH"] = 1; eqx_cell->parameters["\\A_SIGNED"] = 0; eqx_cell->parameters["\\B_SIGNED"] = 0; - eqx_cell->connections["\\A"] = RTLIL::SigSpec::grml(w2_gold, i); + eqx_cell->connections["\\A"] = RTLIL::SigSpec(w2_gold, i); eqx_cell->connections["\\B"] = RTLIL::State::Sx; eqx_cell->connections["\\Y"] = gold_x.extract(i, 1); miter_module->add(eqx_cell); diff --git a/passes/sat/share.cc b/passes/sat/share.cc index c209e8ed7..ede2fa88c 100644 --- a/passes/sat/share.cc +++ b/passes/sat/share.cc @@ -292,8 +292,8 @@ struct ShareWorker supercell->connections["\\Y"] = y; module->add(supercell); - RTLIL::SigSpec new_y1 = RTLIL::SigSpec::grml(y, 0, y1.size()); - RTLIL::SigSpec new_y2 = RTLIL::SigSpec::grml(y, 0, y2.size()); + RTLIL::SigSpec new_y1(y, 0, y1.size()); + RTLIL::SigSpec new_y2(y, 0, y2.size()); module->connections.push_back(RTLIL::SigSig(y1, new_y1)); module->connections.push_back(RTLIL::SigSig(y2, new_y2)); @@ -405,8 +405,8 @@ struct ShareWorker supercell->connections["\\Y"] = y; supercell->check(); - RTLIL::SigSpec new_y1 = RTLIL::SigSpec::grml(y, 0, y1.size()); - RTLIL::SigSpec new_y2 = RTLIL::SigSpec::grml(y, 0, y2.size()); + RTLIL::SigSpec new_y1(y, 0, y1.size()); + RTLIL::SigSpec new_y2(y, 0, y2.size()); module->connections.push_back(RTLIL::SigSig(y1, new_y1)); module->connections.push_back(RTLIL::SigSig(y2, new_y2)); @@ -620,7 +620,7 @@ struct ShareWorker RTLIL::Wire *all_cases_wire = module->addWire(NEW_ID, 0); for (auto &p : activation_patterns) { all_cases_wire->width++; - module->addEq(NEW_ID, p.first, p.second, RTLIL::SigSpec::grml(all_cases_wire, all_cases_wire->width - 1)); + module->addEq(NEW_ID, p.first, p.second, RTLIL::SigSpec(all_cases_wire, all_cases_wire->width - 1)); } if (all_cases_wire->width == 1) return all_cases_wire; diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index 988917b17..1687a1ffb 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -315,7 +315,7 @@ namespace RTLIL::Wire *wire = it.second; if (wire->port_id > 0) { for (int i = 0; i < wire->width; i++) - sig2port.insert(sigmap(RTLIL::SigSpec::grml(wire, i)), std::pair(wire->name, i)); + sig2port.insert(sigmap(RTLIL::SigSpec(wire, i)), std::pair(wire->name, i)); cell->connections[wire->name] = RTLIL::SigSpec(RTLIL::State::Sz, wire->width); } } diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc index 2cb76014c..09147383a 100644 --- a/passes/techmap/iopadmap.cc +++ b/passes/techmap/iopadmap.cc @@ -179,9 +179,9 @@ struct IopadmapPass : public Pass { RTLIL::Cell *cell = new RTLIL::Cell; cell->name = NEW_ID; cell->type = RTLIL::escape_id(celltype); - cell->connections[RTLIL::escape_id(portname)] = RTLIL::SigSpec::grml(wire, i); + cell->connections[RTLIL::escape_id(portname)] = RTLIL::SigSpec(wire, i); if (!portname2.empty()) - cell->connections[RTLIL::escape_id(portname2)] = RTLIL::SigSpec::grml(new_wire, i); + cell->connections[RTLIL::escape_id(portname2)] = RTLIL::SigSpec(new_wire, i); if (!widthparam.empty()) cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(1); if (!nameparam.empty()) -- cgit v1.2.3 From 4e802eb7f6fe5858f8657be7cd3e6638cc0f2ece Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 23 Jul 2014 15:36:09 +0200 Subject: Fixed all users of SigSpec::chunks_rw() and removed it --- passes/cmds/delete.cc | 5 ++-- passes/cmds/setundef.cc | 57 ++++++++++++++++++++++----------------------- passes/cmds/splitnets.cc | 8 +++---- passes/hierarchy/submod.cc | 8 +++---- passes/memory/memory_dff.cc | 12 ++++------ passes/proc/proc_arst.cc | 8 +++---- passes/sat/eval.cc | 14 +++++------ passes/techmap/extract.cc | 6 ++--- passes/techmap/hilomap.cc | 26 ++++++++++----------- passes/techmap/techmap.cc | 17 +++++++------- 10 files changed, 75 insertions(+), 86 deletions(-) (limited to 'passes') diff --git a/passes/cmds/delete.cc b/passes/cmds/delete.cc index f433c4b4a..7fe95b0a9 100644 --- a/passes/cmds/delete.cc +++ b/passes/cmds/delete.cc @@ -27,12 +27,13 @@ struct DeleteWireWorker std::set *delete_wires_p; void operator()(RTLIL::SigSpec &sig) { - sig.optimize(); - for (auto &c : sig.chunks_rw()) + std::vector chunks = sig; + for (auto &c : chunks) if (c.wire != NULL && delete_wires_p->count(c.wire->name)) { c.wire = module->addWire(NEW_ID, c.width); c.offset = 0; } + sig = chunks; } }; diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index 619930b3a..63d5bb9af 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -23,35 +23,33 @@ #include "kernel/rtlil.h" #include "kernel/log.h" -static int next_bit_mode; -static uint32_t next_bit_state; - -static RTLIL::State next_bit() +struct SetundefWorker { - if (next_bit_mode == 0) - return RTLIL::State::S0; + int next_bit_mode; + uint32_t next_bit_state; - if (next_bit_mode == 1) - return RTLIL::State::S1; + RTLIL::State next_bit() + { + if (next_bit_mode == 0) + return RTLIL::State::S0; - // xorshift32 - next_bit_state ^= next_bit_state << 13; - next_bit_state ^= next_bit_state >> 17; - next_bit_state ^= next_bit_state << 5; - log_assert(next_bit_state != 0); + if (next_bit_mode == 1) + return RTLIL::State::S1; - return ((next_bit_state >> (next_bit_state & 15)) & 16) ? RTLIL::State::S0 : RTLIL::State::S1; -} + // xorshift32 + next_bit_state ^= next_bit_state << 13; + next_bit_state ^= next_bit_state >> 17; + next_bit_state ^= next_bit_state << 5; + log_assert(next_bit_state != 0); + + return ((next_bit_state >> (next_bit_state & 15)) & 16) ? RTLIL::State::S0 : RTLIL::State::S1; + } -struct SetundefWorker -{ void operator()(RTLIL::SigSpec &sig) { - sig.expand(); - for (auto &c : sig.chunks_rw()) - if (c.wire == NULL && c.data.bits.at(0) > RTLIL::State::S1) - c.data.bits.at(0) = next_bit(); - sig.optimize(); + for (auto &bit : sig) + if (bit.wire == NULL && bit.data > RTLIL::State::S1) + bit = next_bit(); } }; @@ -83,6 +81,7 @@ struct SetundefPass : public Pass { { bool got_value = false; bool undriven_mode = false; + SetundefWorker worker; size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) @@ -93,20 +92,20 @@ struct SetundefPass : public Pass { } if (args[argidx] == "-zero") { got_value = true; - next_bit_mode = 0; + worker.next_bit_mode = 0; continue; } if (args[argidx] == "-one") { got_value = true; - next_bit_mode = 1; + worker.next_bit_mode = 1; continue; } if (args[argidx] == "-random" && !got_value && argidx+1 < args.size()) { got_value = true; - next_bit_mode = 2; - next_bit_state = atoi(args[++argidx].c_str()) + 1; + worker.next_bit_mode = 2; + worker.next_bit_state = atoi(args[++argidx].c_str()) + 1; for (int i = 0; i < 10; i++) - next_bit(); + worker.next_bit(); continue; } break; @@ -144,13 +143,13 @@ struct SetundefPass : public Pass { for (auto &c : sig.chunks()) { RTLIL::SigSpec bits; for (int i = 0; i < c.width; i++) - bits.append(next_bit()); + bits.append(worker.next_bit()); bits.optimize(); module->connections.push_back(RTLIL::SigSig(c, bits)); } } - module->rewrite_sigspecs(SetundefWorker()); + module->rewrite_sigspecs(worker); } } } SetundefPass; diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc index d71e9727c..c40ff2c4a 100644 --- a/passes/cmds/splitnets.cc +++ b/passes/cmds/splitnets.cc @@ -62,11 +62,9 @@ struct SplitnetsWorker void operator()(RTLIL::SigSpec &sig) { - sig.expand(); - for (auto &c : sig.chunks_rw()) - if (splitmap.count(c.wire) > 0) - c = splitmap.at(c.wire).at(c.offset); - sig.optimize(); + for (auto &bit : sig) + if (splitmap.count(bit.wire) > 0) + bit = splitmap.at(bit.wire).at(bit.offset); } }; diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index b983a840e..257301880 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -164,10 +164,10 @@ struct SubmodWorker for (RTLIL::Cell *cell : submod.cells) { RTLIL::Cell *new_cell = new RTLIL::Cell(*cell); for (auto &conn : new_cell->connections) - for (auto &c : conn.second.chunks_rw()) - if (c.wire != NULL) { - assert(wire_flags.count(c.wire) > 0); - c.wire = wire_flags[c.wire].new_wire; + for (auto &bit : conn.second) + if (bit.wire != NULL) { + assert(wire_flags.count(bit.wire) > 0); + bit.wire = wire_flags[bit.wire].new_wire; } log(" cell %s (%s)\n", new_cell->name.c_str(), new_cell->type.c_str()); new_mod->cells[new_cell->name] = new_cell; diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index dee48597f..b1f1e22b5 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -32,13 +32,10 @@ static void normalize_sig(RTLIL::Module *module, RTLIL::SigSpec &sig) static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::SigSpec &clk, bool &clk_polarity, bool after = false) { normalize_sig(module, sig); - sig.expand(); - for (size_t i = 0; i < sig.chunks().size(); i++) + for (auto &bit : sig) { - RTLIL::SigChunk &chunk = sig.chunks_rw()[i]; - - if (chunk.wire == NULL) + if (bit.wire == NULL) continue; for (auto &cell_it : module->cells) @@ -58,12 +55,11 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI RTLIL::SigSpec q_norm = cell->connections[after ? "\\D" : "\\Q"]; normalize_sig(module, q_norm); - RTLIL::SigSpec d = q_norm.extract(chunk, &cell->connections[after ? "\\Q" : "\\D"]); + RTLIL::SigSpec d = q_norm.extract(bit, &cell->connections[after ? "\\Q" : "\\D"]); if (d.size() != 1) continue; - assert(d.chunks().size() == 1); - chunk = d.chunks()[0]; + bit = d; clk = cell->connections["\\CLK"]; clk_polarity = cell->parameters["\\CLK_POLARITY"].as_bool(); goto replaced_this_bit; diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc index 6cb560f5c..145abfa43 100644 --- a/passes/proc/proc_arst.cc +++ b/passes/proc/proc_arst.cc @@ -165,11 +165,9 @@ restart_proc_arst: for (auto &action : sync->actions) { RTLIL::SigSpec rspec = action.second; RTLIL::SigSpec rval = RTLIL::SigSpec(RTLIL::State::Sm, rspec.size()); - rspec.expand(), rval.expand(); - for (int i = 0; i < int(rspec.chunks().size()); i++) - if (rspec.chunks()[i].wire == NULL) - rval.chunks_rw()[i] = rspec.chunks()[i]; - rspec.optimize(), rval.optimize(); + for (int i = 0; i < SIZE(rspec); i++) + if (rspec[i].wire == NULL) + rval[i] = rspec[i]; RTLIL::SigSpec last_rval; for (int count = 0; rval != last_rval; count++) { last_rval = rval; diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc index 902dedb62..090f7463a 100644 --- a/passes/sat/eval.cc +++ b/passes/sat/eval.cc @@ -70,11 +70,9 @@ struct BruteForceEquivChecker log_signal(undef2), log_signal(mod1_inputs), log_signal(inputs)); if (ignore_x_mod1) { - sig1.expand(), sig2.expand(); - for (size_t i = 0; i < sig1.chunks().size(); i++) - if (sig1.chunks().at(i) == RTLIL::SigChunk(RTLIL::State::Sx)) - sig2.chunks_rw().at(i) = RTLIL::SigChunk(RTLIL::State::Sx); - sig1.optimize(), sig2.optimize(); + for (int i = 0; i < SIZE(sig1); i++) + if (sig1[i] == RTLIL::State::Sx) + sig2[i] = RTLIL::State::Sx; } if (sig1 != sig2) { @@ -297,9 +295,9 @@ struct VlogHammerReporter sig.expand(); if (rtl_sig.size() != sig.size()) log_error("Output (y) has a different width in module %s compared to rtl!\n", RTLIL::id2cstr(module->name)); - for (int i = 0; i < sig.size(); i++) - if (rtl_sig.chunks().at(i).data.bits.at(0) == RTLIL::State::Sx) - sig.chunks_rw().at(i).data.bits.at(0) = RTLIL::State::Sx; + for (int i = 0; i < SIZE(sig); i++) + if (rtl_sig[i] == RTLIL::State::Sx) + sig[i] = RTLIL::State::Sx; } log("++RPT++ %d%s %s %s\n", idx, input_pattern_list.c_str(), sig.as_const().as_string().c_str(), module_name.c_str()); diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index 1687a1ffb..e5055c9c4 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -755,11 +755,11 @@ struct ExtractPass : public Pass { newCell->type = cell->type; newCell->parameters = cell->parameters; for (auto &conn : cell->connections) { - RTLIL::SigSpec sig = sigmap(conn.second); - for (auto &chunk : sig.chunks_rw()) + std::vector chunks = sigmap(conn.second); + for (auto &chunk : chunks) if (chunk.wire != NULL) chunk.wire = newMod->wires.at(chunk.wire->name); - newCell->connections[conn.first] = sig; + newCell->connections[conn.first] = chunks; } newMod->add(newCell); } diff --git a/passes/techmap/hilomap.cc b/passes/techmap/hilomap.cc index 53c5d1044..51b8802c4 100644 --- a/passes/techmap/hilomap.cc +++ b/passes/techmap/hilomap.cc @@ -26,36 +26,34 @@ static std::string locell_celltype, locell_portname; static bool singleton_mode; static RTLIL::Module *module; -static RTLIL::SigChunk last_hi, last_lo; +static RTLIL::SigBit last_hi, last_lo; void hilomap_worker(RTLIL::SigSpec &sig) { - sig.expand(); - for (auto &c : sig.chunks_rw()) { - if (c.wire == NULL && (c.data.bits.at(0) == RTLIL::State::S1) && !hicell_celltype.empty()) { - if (!singleton_mode || last_hi.width == 0) { - last_hi = RTLIL::SigChunk(module->addWire(NEW_ID)); + for (auto &bit : sig) { + if (bit == RTLIL::State::S1 && !hicell_celltype.empty()) { + if (!singleton_mode || last_hi == RTLIL::State::Sm) { + last_hi = module->addWire(NEW_ID); RTLIL::Cell *cell = new RTLIL::Cell; cell->name = NEW_ID; cell->type = RTLIL::escape_id(hicell_celltype); cell->connections[RTLIL::escape_id(hicell_portname)] = last_hi; module->add(cell); } - c = last_hi; + bit = last_hi; } - if (c.wire == NULL && (c.data.bits.at(0) == RTLIL::State::S0) && !locell_celltype.empty()) { - if (!singleton_mode || last_lo.width == 0) { - last_lo = RTLIL::SigChunk(module->addWire(NEW_ID)); + if (bit == RTLIL::State::S0 && !locell_celltype.empty()) { + if (!singleton_mode || last_lo == RTLIL::State::Sm) { + last_lo = module->addWire(NEW_ID); RTLIL::Cell *cell = new RTLIL::Cell; cell->name = NEW_ID; cell->type = RTLIL::escape_id(locell_celltype); cell->connections[RTLIL::escape_id(locell_portname)] = last_lo; module->add(cell); } - c = last_lo; + bit = last_lo; } } - sig.optimize(); } struct HilomapPass : public Pass { @@ -119,8 +117,8 @@ struct HilomapPass : public Pass { if (!design->selected(module)) continue; - last_hi = RTLIL::SigChunk(); - last_lo = RTLIL::SigChunk(); + last_hi = RTLIL::State::Sm; + last_lo = RTLIL::State::Sm; module->rewrite_sigspecs(hilomap_worker); } diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index f3b1a0ef7..8d7b21e0f 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -41,14 +41,15 @@ static void apply_prefix(std::string prefix, std::string &id) static void apply_prefix(std::string prefix, RTLIL::SigSpec &sig, RTLIL::Module *module) { - for (size_t i = 0; i < sig.chunks().size(); i++) { - if (sig.chunks()[i].wire == NULL) - continue; - std::string wire_name = sig.chunks()[i].wire->name; - apply_prefix(prefix, wire_name); - assert(module->wires.count(wire_name) > 0); - sig.chunks_rw()[i].wire = module->wires[wire_name]; - } + std::vector chunks = sig; + for (auto &chunk : chunks) + if (chunk.wire != NULL) { + std::string wire_name = chunk.wire->name; + apply_prefix(prefix, wire_name); + assert(module->wires.count(wire_name) > 0); + chunk.wire = module->wires[wire_name]; + } + sig = chunks; } struct TechmapWorker -- cgit v1.2.3 From a62c21c9c64ad5b3e0dae5d4ee4857425f73068e Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 23 Jul 2014 16:09:27 +0200 Subject: Removed RTLIL::SigSpec::expand() method --- passes/abc/abc.cc | 53 +++++++--------- passes/opt/opt_clean.cc | 17 +++--- passes/opt/opt_const.cc | 14 ++--- passes/opt/opt_muxtree.cc | 12 ++-- passes/opt/opt_reduce.cc | 36 +++++------ passes/sat/eval.cc | 8 +-- passes/sat/sat.cc | 6 +- passes/techmap/extract.cc | 57 ++++++++---------- passes/techmap/simplemap.cc | 143 ++++++++++++++------------------------------ 9 files changed, 135 insertions(+), 211 deletions(-) (limited to 'passes') diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index 8cdd39b7a..ba27a3fc6 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -55,26 +55,23 @@ struct gate_t char type; int in1, in2, in3; bool is_port; - RTLIL::SigSpec sig; + RTLIL::SigBit bit; }; static int map_autoidx; static SigMap assign_map; static RTLIL::Module *module; static std::vector signal_list; -static std::map signal_map; +static std::map signal_map; static bool clk_polarity; static RTLIL::SigSpec clk_sig; -static int map_signal(RTLIL::SigSpec sig, char gate_type = -1, int in1 = -1, int in2 = -1, int in3 = -1) +static int map_signal(RTLIL::SigBit bit, char gate_type = -1, int in1 = -1, int in2 = -1, int in3 = -1) { - assert(sig.size() == 1); - assert(sig.chunks().size() == 1); + assign_map.apply(bit); - assign_map.apply(sig); - - if (signal_map.count(sig) == 0) { + if (signal_map.count(bit) == 0) { gate_t gate; gate.id = signal_list.size(); gate.type = -1; @@ -82,12 +79,12 @@ static int map_signal(RTLIL::SigSpec sig, char gate_type = -1, int in1 = -1, int gate.in2 = -1; gate.in3 = -1; gate.is_port = false; - gate.sig = sig; + gate.bit = bit; signal_list.push_back(gate); - signal_map[sig] = gate.id; + signal_map[bit] = gate.id; } - gate_t &gate = signal_list[signal_map[sig]]; + gate_t &gate = signal_list[signal_map[bit]]; if (gate_type >= 0) gate.type = gate_type; @@ -103,12 +100,9 @@ static int map_signal(RTLIL::SigSpec sig, char gate_type = -1, int in1 = -1, int static void mark_port(RTLIL::SigSpec sig) { - assign_map.apply(sig); - sig.expand(); - for (auto &c : sig.chunks()) { - if (c.wire != NULL && signal_map.count(c) > 0) - signal_list[signal_map[c]].is_port = true; - } + for (auto &bit : assign_map(sig)) + if (bit.wire != NULL && signal_map.count(bit) > 0) + signal_list[signal_map[bit]].is_port = true; } static void extract_cell(RTLIL::Cell *cell, bool keepff) @@ -229,7 +223,7 @@ static void dump_loop_graph(FILE *f, int &nr, std::map> &edge } for (auto n : nodes) - fprintf(f, " n%d [label=\"%s\\nid=%d, count=%d\"%s];\n", n, log_signal(signal_list[n].sig), + fprintf(f, " n%d [label=\"%s\\nid=%d, count=%d\"%s];\n", n, log_signal(signal_list[n].bit), n, in_counts[n], workpool.count(n) ? ", shape=box" : ""); for (auto &e : edges) @@ -280,7 +274,7 @@ static void handle_loops() int id = *workpool.begin(); workpool.erase(id); - // log("Removing non-loop node %d from graph: %s\n", id, log_signal(signal_list[id].sig)); + // log("Removing non-loop node %d from graph: %s\n", id, log_signal(signal_list[id].bit)); for (int id2 : edges[id]) { assert(in_edges_count[id2] > 0); @@ -300,8 +294,8 @@ static void handle_loops() for (auto &edge_it : edges) { int id2 = edge_it.first; - RTLIL::Wire *w1 = signal_list[id1].sig.chunks()[0].wire; - RTLIL::Wire *w2 = signal_list[id2].sig.chunks()[0].wire; + RTLIL::Wire *w1 = signal_list[id1].bit.wire; + RTLIL::Wire *w2 = signal_list[id2].bit.wire; if (w1 != NULL) continue; else if (w2 == NULL) @@ -333,10 +327,10 @@ static void handle_loops() for (int id2 : edges[id1]) { if (first_line) log("Breaking loop using new signal %s: %s -> %s\n", log_signal(RTLIL::SigSpec(wire)), - log_signal(signal_list[id1].sig), log_signal(signal_list[id2].sig)); + log_signal(signal_list[id1].bit), log_signal(signal_list[id2].bit)); else log(" %*s %s -> %s\n", int(strlen(log_signal(RTLIL::SigSpec(wire)))), "", - log_signal(signal_list[id1].sig), log_signal(signal_list[id2].sig)); + log_signal(signal_list[id1].bit), log_signal(signal_list[id2].bit)); first_line = false; } @@ -357,7 +351,7 @@ static void handle_loops() } edges[id1].swap(edges[id3]); - module->connections.push_back(RTLIL::SigSig(signal_list[id3].sig, signal_list[id1].sig)); + module->connections.push_back(RTLIL::SigSig(signal_list[id3].bit, signal_list[id1].bit)); dump_loop_graph(dot_f, dot_nr, edges, workpool, in_edges_count); } } @@ -549,13 +543,12 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std fprintf(f, "\n"); for (auto &si : signal_list) - fprintf(f, "# n%-5d %s\n", si.id, log_signal(si.sig)); + fprintf(f, "# n%-5d %s\n", si.id, log_signal(si.bit)); for (auto &si : signal_list) { - assert(si.sig.size() == 1 && si.sig.chunks().size() == 1); - if (si.sig.chunks()[0].wire == NULL) { + if (si.bit.wire == NULL) { fprintf(f, ".names n%d\n", si.id); - if (si.sig.chunks()[0].data.bits[0] == RTLIL::State::S1) + if (si.bit == RTLIL::State::S1) fprintf(f, "1\n"); } } @@ -837,12 +830,12 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std snprintf(buffer, 100, "\\n%d", si.id); RTLIL::SigSig conn; if (si.type >= 0) { - conn.first = si.sig; + conn.first = si.bit; conn.second = RTLIL::SigSpec(module->wires[remap_name(buffer)]); out_wires++; } else { conn.first = RTLIL::SigSpec(module->wires[remap_name(buffer)]); - conn.second = si.sig; + conn.second = si.bit; in_wires++; } module->connections.push_back(conn); diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 23fc48d5d..0be36606d 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -233,14 +233,12 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool if (!used_signals.check_any(s2) && wire->port_id == 0 && !wire->get_bool_attribute("\\keep")) { del_wires.push_back(wire); } else { - s1.expand(); - s2.expand(); - assert(s1.chunks().size() == s2.chunks().size()); + assert(SIZE(s1) == SIZE(s2)); RTLIL::SigSig new_conn; - for (size_t i = 0; i < s1.chunks().size(); i++) - if (s1.chunks()[i] != s2.chunks()[i]) { - new_conn.first.append(s1.chunks()[i]); - new_conn.second.append(s2.chunks()[i]); + for (int i = 0; i < SIZE(s1); i++) + if (s1[i] != s2[i]) { + new_conn.first.append_bit(s1[i]); + new_conn.second.append_bit(s2[i]); } if (new_conn.first.size() > 0) { new_conn.first.optimize(); @@ -257,9 +255,8 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool RTLIL::SigSpec sig = assign_map(RTLIL::SigSpec(wire)); if (!used_signals_nodrivers.check_any(sig)) { std::string unused_bits; - sig.expand(); - for (size_t i = 0; i < sig.chunks().size(); i++) { - if (sig.chunks()[i].wire == NULL) + for (int i = 0; i < SIZE(sig); i++) { + if (sig[i].wire == NULL) continue; if (!used_signals_nodrivers.check_any(sig)) { if (!unused_bits.empty()) diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index 9b89291b1..ff139854f 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -458,21 +458,19 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo } RTLIL::SigSpec new_a, new_b; - a.expand(), b.expand(); - assert(a.chunks().size() == b.chunks().size()); - for (size_t i = 0; i < a.chunks().size(); i++) { - if (a.chunks()[i].wire == NULL && b.chunks()[i].wire == NULL && a.chunks()[i].data.bits[0] != b.chunks()[i].data.bits[0] && - a.chunks()[i].data.bits[0] <= RTLIL::State::S1 && b.chunks()[i].data.bits[0] <= RTLIL::State::S1) { + assert(SIZE(a) == SIZE(b)); + for (int i = 0; i < SIZE(a); i++) { + if (a[i].wire == NULL && b[i].wire == NULL && a[i] != b[i] && a[i].data <= RTLIL::State::S1 && b[i].data <= RTLIL::State::S1) { RTLIL::SigSpec new_y = RTLIL::SigSpec((cell->type == "$eq" || cell->type == "$eqx") ? RTLIL::State::S0 : RTLIL::State::S1); new_y.extend(cell->parameters["\\Y_WIDTH"].as_int(), false); replace_cell(module, cell, "empty", "\\Y", new_y); goto next_cell; } - if (a.chunks()[i] == b.chunks()[i]) + if (a[i] == b[i]) continue; - new_a.append(a.chunks()[i]); - new_b.append(b.chunks()[i]); + new_a.append(a[i]); + new_b.append(b[i]); } if (new_a.size() == 0) { diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc index 61147f67a..dfcd55126 100644 --- a/passes/opt/opt_muxtree.cc +++ b/passes/opt/opt_muxtree.cc @@ -36,7 +36,11 @@ struct OptMuxtreeWorker SigMap assign_map; int removed_count; - typedef std::pair bitDef_t; + struct bitDef_t : public std::pair { + bitDef_t() : std::pair(NULL, 0) { } + bitDef_t(const RTLIL::SigBit &bit) : std::pair(bit.wire, bit.offset) { } + }; + struct bitinfo_t { int num; @@ -259,10 +263,8 @@ struct OptMuxtreeWorker { std::vector results; assign_map.apply(sig); - sig.expand(); - for (auto &c : sig.chunks()) - if (c.wire != NULL) { - bitDef_t bit(c.wire, c.offset); + for (auto &bit : sig) + if (bit.wire != NULL) { if (bit2num.count(bit) == 0) { bitinfo_t info; info.num = bit2info.size(); diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc index 7ab7233c6..913855f48 100644 --- a/passes/opt/opt_reduce.cc +++ b/passes/opt/opt_reduce.cc @@ -44,46 +44,48 @@ struct OptReduceWorker cells.erase(cell); RTLIL::SigSpec sig_a = assign_map(cell->connections["\\A"]); - sig_a.sort_and_unify(); - sig_a.expand(); + std::set new_sig_a_bits; - RTLIL::SigSpec new_sig_a; - for (auto &chunk : sig_a.chunks()) + for (auto &bit : sig_a.to_sigbit_set()) { - if (chunk.wire == NULL && chunk.data.bits[0] == RTLIL::State::S0) { + if (bit == RTLIL::State::S0) { if (cell->type == "$reduce_and") { - new_sig_a = RTLIL::SigSpec(RTLIL::State::S0); + new_sig_a_bits.clear(); + new_sig_a_bits.insert(RTLIL::State::S0); break; } continue; } - if (chunk.wire == NULL && chunk.data.bits[0] == RTLIL::State::S1) { + if (bit == RTLIL::State::S1) { if (cell->type == "$reduce_or") { - new_sig_a = RTLIL::SigSpec(RTLIL::State::S1); + new_sig_a_bits.clear(); + new_sig_a_bits.insert(RTLIL::State::S1); break; } continue; } - if (chunk.wire == NULL) { - new_sig_a.append(chunk); + if (bit.wire == NULL) { + new_sig_a_bits.insert(bit); continue; } bool imported_children = false; - for (auto child_cell : drivers.find(chunk)) { + for (auto child_cell : drivers.find(bit)) { if (child_cell->type == cell->type) { opt_reduce(cells, drivers, child_cell); - if (child_cell->connections["\\Y"].extract(0, 1) == chunk) - new_sig_a.append(child_cell->connections["\\A"]); - else - new_sig_a.append(RTLIL::State::S0); + if (child_cell->connections["\\Y"][0] == bit) { + std::set child_sig_a_bits = assign_map(child_cell->connections["\\A"]).to_sigbit_set(); + new_sig_a_bits.insert(child_sig_a_bits.begin(), child_sig_a_bits.end()); + } else + new_sig_a_bits.insert(RTLIL::State::S0); imported_children = true; } } if (!imported_children) - new_sig_a.append(chunk); + new_sig_a_bits.insert(bit); } - new_sig_a.sort_and_unify(); + + RTLIL::SigSpec new_sig_a(new_sig_a_bits); if (new_sig_a != sig_a || sig_a.size() != cell->connections["\\A"].size()) { log(" New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a)); diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc index 090f7463a..9b8c35361 100644 --- a/passes/sat/eval.cc +++ b/passes/sat/eval.cc @@ -169,10 +169,9 @@ struct VlogHammerReporter if (!ez.solve(y_vec, y_values)) log_error("Failed to find solution to SAT problem.\n"); - expected_y.expand(); for (int i = 0; i < expected_y.size(); i++) { RTLIL::State solution_bit = y_values.at(i) ? RTLIL::State::S1 : RTLIL::State::S0; - RTLIL::State expected_bit = expected_y.chunks().at(i).data.bits.at(0); + RTLIL::State expected_bit = expected_y[i].data; if (model_undef) { if (y_values.at(expected_y.size()+i)) solution_bit = RTLIL::State::Sx; @@ -187,8 +186,7 @@ struct VlogHammerReporter sat_bits += "x"; else sat_bits += y_values.at(k) ? "1" : "0"; - rtl_bits += expected_y.chunks().at(k).data.bits.at(0) == RTLIL::State::Sx ? "x" : - expected_y.chunks().at(k).data.bits.at(0) == RTLIL::State::S1 ? "1" : "0"; + rtl_bits += expected_y[k] == RTLIL::State::Sx ? "x" : expected_y[k] == RTLIL::State::S1 ? "1" : "0"; } log_error("Found error in SAT model: y[%d] = %s, should be %s:\n SAT: %s\n RTL: %s\n %*s^\n", int(i), log_signal(solution_bit), log_signal(expected_bit), @@ -288,11 +286,9 @@ struct VlogHammerReporter if (module_name == "rtl") { rtl_sig = sig; - rtl_sig.expand(); sat_check(module, recorded_set_vars, recorded_set_vals, sig, false); sat_check(module, recorded_set_vars, recorded_set_vals, sig, true); } else if (rtl_sig.size() > 0) { - sig.expand(); if (rtl_sig.size() != sig.size()) log_error("Output (y) has a different width in module %s compared to rtl!\n", RTLIL::id2cstr(module->name)); for (int i = 0; i < SIZE(sig); i++) diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 24968aa2c..34becaee8 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -411,10 +411,8 @@ struct SatHelper if (prove_asserts) { RTLIL::SigSpec asserts_a, asserts_en; satgen.getAsserts(asserts_a, asserts_en, timestep); - asserts_a.expand(); - asserts_en.expand(); - for (size_t i = 0; i < asserts_a.chunks().size(); i++) - log("Import proof for assert: %s when %s.\n", log_signal(asserts_a.chunks()[i]), log_signal(asserts_en.chunks()[i])); + for (int i = 0; i < SIZE(asserts_a); i++) + log("Import proof for assert: %s when %s.\n", log_signal(asserts_a[i]), log_signal(asserts_en[i])); prove_bits.push_back(satgen.importAsserts(timestep)); } diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index e5055c9c4..4c3aec31d 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -130,11 +130,8 @@ namespace RTLIL::SigSpec needleSig = conn.second; RTLIL::SigSpec haystackSig = haystackCell->connections.at(portMapping.at(conn.first)); - needleSig.expand(); - haystackSig.expand(); - for (int i = 0; i < std::min(needleSig.size(), haystackSig.size()); i++) { - RTLIL::Wire *needleWire = needleSig.chunks().at(i).wire, *haystackWire = haystackSig.chunks().at(i).wire; + RTLIL::Wire *needleWire = needleSig[i].wire, *haystackWire = haystackSig[i].wire; if (needleWire != lastNeedleWire || haystackWire != lastHaystackWire) if (!compareAttributes(wire_attr, needleWire ? needleWire->attributes : emptyAttr, haystackWire ? haystackWire->attributes : emptyAttr)) return false; @@ -156,7 +153,7 @@ namespace int max_fanout = -1, std::set> *split = NULL) { SigMap sigmap(mod); - std::map sig_bit_ref; + std::map sig_bit_ref; if (sel && !sel->selected(mod)) { log(" Skipping module %s as it is not selected.\n", id2cstr(mod->name)); @@ -192,10 +189,9 @@ namespace for (auto &conn : cell->connections) { RTLIL::SigSpec conn_sig = conn.second; sigmap.apply(conn_sig); - conn_sig.expand(); - for (auto &chunk : conn_sig.chunks()) - if (chunk.wire != NULL) - sig_use_count[std::pair(chunk.wire, chunk.offset)]++; + for (auto &bit : conn_sig) + if (bit.wire != NULL) + sig_use_count[std::pair(bit.wire, bit.offset)]++; } } @@ -220,39 +216,37 @@ namespace RTLIL::SigSpec conn_sig = conn.second; sigmap.apply(conn_sig); - conn_sig.expand(); - for (size_t i = 0; i < conn_sig.chunks().size(); i++) + for (int i = 0; i < conn_sig.size(); i++) { - auto &chunk = conn_sig.chunks()[i]; - assert(chunk.width == 1); + auto &bit = conn_sig[i]; - if (chunk.wire == NULL) { + if (bit.wire == NULL) { if (constports) { std::string node = "$const$x"; - if (chunk.data.bits[0] == RTLIL::State::S0) node = "$const$0"; - if (chunk.data.bits[0] == RTLIL::State::S1) node = "$const$1"; - if (chunk.data.bits[0] == RTLIL::State::Sz) node = "$const$z"; + if (bit == RTLIL::State::S0) node = "$const$0"; + if (bit == RTLIL::State::S1) node = "$const$1"; + if (bit == RTLIL::State::Sz) node = "$const$z"; graph.createConnection(cell->name, conn.first, i, node, "\\Y", 0); } else - graph.createConstant(cell->name, conn.first, i, int(chunk.data.bits[0])); + graph.createConstant(cell->name, conn.first, i, int(bit.data)); continue; } - if (max_fanout > 0 && sig_use_count[std::pair(chunk.wire, chunk.offset)] > max_fanout) + if (max_fanout > 0 && sig_use_count[std::pair(bit.wire, bit.offset)] > max_fanout) continue; - if (sel && !sel->selected(mod, chunk.wire)) + if (sel && !sel->selected(mod, bit.wire)) continue; - if (sig_bit_ref.count(chunk) == 0) { - bit_ref_t &bit_ref = sig_bit_ref[chunk]; + if (sig_bit_ref.count(bit) == 0) { + bit_ref_t &bit_ref = sig_bit_ref[bit]; bit_ref.cell = cell->name; bit_ref.port = conn.first; bit_ref.bit = i; } - bit_ref_t &bit_ref = sig_bit_ref[chunk]; + bit_ref_t &bit_ref = sig_bit_ref[bit]; graph.createConnection(bit_ref.cell, bit_ref.port, bit_ref.bit, cell->name, conn.first, i); } } @@ -267,11 +261,10 @@ namespace { RTLIL::SigSpec conn_sig = conn.second; sigmap.apply(conn_sig); - conn_sig.expand(); - for (auto &chunk : conn_sig.chunks()) - if (sig_bit_ref.count(chunk) != 0) { - bit_ref_t &bit_ref = sig_bit_ref[chunk]; + for (auto &bit : conn_sig) + if (sig_bit_ref.count(bit) != 0) { + bit_ref_t &bit_ref = sig_bit_ref[bit]; graph.markExtern(bit_ref.cell, bit_ref.port, bit_ref.bit); } } @@ -285,11 +278,10 @@ namespace { RTLIL::SigSpec conn_sig(wire); sigmap.apply(conn_sig); - conn_sig.expand(); - for (auto &chunk : conn_sig.chunks()) - if (sig_bit_ref.count(chunk) != 0) { - bit_ref_t &bit_ref = sig_bit_ref[chunk]; + for (auto &bit : conn_sig) + if (sig_bit_ref.count(bit) != 0) { + bit_ref_t &bit_ref = sig_bit_ref[bit]; graph.markExtern(bit_ref.cell, bit_ref.port, bit_ref.bit); } } @@ -333,9 +325,8 @@ namespace for (auto &conn : needle_cell->connections) { RTLIL::SigSpec sig = sigmap(conn.second); if (mapping.portMapping.count(conn.first) > 0 && sig2port.has(sigmap(sig))) { - sig.expand(); for (int i = 0; i < sig.size(); i++) - for (auto &port : sig2port.find(sig.chunks()[i])) { + for (auto &port : sig2port.find(sig[i])) { RTLIL::SigSpec bitsig = haystack_cell->connections.at(mapping.portMapping[conn.first]).extract(i, 1); cell->connections.at(port.first).replace(port.second, bitsig); } diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc index 1eb5c063b..034677d3b 100644 --- a/passes/techmap/simplemap.cc +++ b/passes/techmap/simplemap.cc @@ -29,75 +29,60 @@ extern void simplemap_get_mappers(std::mapparameters.at("\\Y_WIDTH").as_int(); - RTLIL::SigSpec sig_a = cell->connections.at("\\A"); - sig_a.extend(width, cell->parameters.at("\\A_SIGNED").as_bool()); - sig_a.expand(); - RTLIL::SigSpec sig_y = cell->connections.at("\\Y"); - sig_y.expand(); - for (int i = 0; i < width; i++) { + sig_a.extend(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool()); + + for (int i = 0; i < SIZE(sig_y); i++) { RTLIL::Cell *gate = new RTLIL::Cell; gate->name = NEW_ID; gate->type = "$_INV_"; - gate->connections["\\A"] = sig_a.chunks().at(i); - gate->connections["\\Y"] = sig_y.chunks().at(i); + gate->connections["\\A"] = sig_a[i]; + gate->connections["\\Y"] = sig_y[i]; module->add(gate); } } static void simplemap_pos(RTLIL::Module *module, RTLIL::Cell *cell) { - int width = cell->parameters.at("\\Y_WIDTH").as_int(); - RTLIL::SigSpec sig_a = cell->connections.at("\\A"); - sig_a.extend(width, cell->parameters.at("\\A_SIGNED").as_bool()); - RTLIL::SigSpec sig_y = cell->connections.at("\\Y"); + sig_a.extend(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool()); + module->connections.push_back(RTLIL::SigSig(sig_y, sig_a)); } static void simplemap_bu0(RTLIL::Module *module, RTLIL::Cell *cell) { - int width = cell->parameters.at("\\Y_WIDTH").as_int(); - RTLIL::SigSpec sig_a = cell->connections.at("\\A"); - sig_a.extend_u0(width, cell->parameters.at("\\A_SIGNED").as_bool()); - RTLIL::SigSpec sig_y = cell->connections.at("\\Y"); + sig_a.extend_u0(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool()); + module->connections.push_back(RTLIL::SigSig(sig_y, sig_a)); } static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell) { - int width = cell->parameters.at("\\Y_WIDTH").as_int(); - RTLIL::SigSpec sig_a = cell->connections.at("\\A"); - sig_a.extend_u0(width, cell->parameters.at("\\A_SIGNED").as_bool()); - sig_a.expand(); - RTLIL::SigSpec sig_b = cell->connections.at("\\B"); - sig_b.extend_u0(width, cell->parameters.at("\\B_SIGNED").as_bool()); - sig_b.expand(); - RTLIL::SigSpec sig_y = cell->connections.at("\\Y"); - sig_y.expand(); + + sig_a.extend_u0(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool()); + sig_b.extend_u0(SIZE(sig_y), cell->parameters.at("\\B_SIGNED").as_bool()); if (cell->type == "$xnor") { - RTLIL::SigSpec sig_t = module->addWire(NEW_ID, width); - sig_t.expand(); + RTLIL::SigSpec sig_t = module->addWire(NEW_ID, SIZE(sig_y)); - for (int i = 0; i < width; i++) { + for (int i = 0; i < SIZE(sig_y); i++) { RTLIL::Cell *gate = new RTLIL::Cell; gate->name = NEW_ID; gate->type = "$_INV_"; - gate->connections["\\A"] = sig_t.chunks().at(i); - gate->connections["\\Y"] = sig_y.chunks().at(i); + gate->connections["\\A"] = sig_t[i]; + gate->connections["\\Y"] = sig_y[i]; module->add(gate); } @@ -111,13 +96,13 @@ static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell) if (cell->type == "$xnor") gate_type = "$_XOR_"; log_assert(!gate_type.empty()); - for (int i = 0; i < width; i++) { + for (int i = 0; i < SIZE(sig_y); i++) { RTLIL::Cell *gate = new RTLIL::Cell; gate->name = NEW_ID; gate->type = gate_type; - gate->connections["\\A"] = sig_a.chunks().at(i); - gate->connections["\\B"] = sig_b.chunks().at(i); - gate->connections["\\Y"] = sig_y.chunks().at(i); + gate->connections["\\A"] = sig_a[i]; + gate->connections["\\B"] = sig_b[i]; + gate->connections["\\Y"] = sig_y[i]; module->add(gate); } } @@ -125,8 +110,6 @@ static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell) static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) { RTLIL::SigSpec sig_a = cell->connections.at("\\A"); - sig_a.expand(); - RTLIL::SigSpec sig_y = cell->connections.at("\\Y"); if (sig_y.size() == 0) @@ -159,21 +142,20 @@ static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) while (sig_a.size() > 1) { RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig_a.size() / 2); - sig_t.expand(); for (int i = 0; i < sig_a.size(); i += 2) { if (i+1 == sig_a.size()) { - sig_t.append(sig_a.chunks().at(i)); + sig_t.append(sig_a[i]); continue; } RTLIL::Cell *gate = new RTLIL::Cell; gate->name = NEW_ID; gate->type = gate_type; - gate->connections["\\A"] = sig_a.chunks().at(i); - gate->connections["\\B"] = sig_a.chunks().at(i+1); - gate->connections["\\Y"] = sig_t.chunks().at(i/2); + gate->connections["\\A"] = sig_a[i]; + gate->connections["\\B"] = sig_a[i+1]; + gate->connections["\\Y"] = sig_t[i/2]; last_output = &gate->connections["\\Y"]; module->add(gate); } @@ -202,26 +184,23 @@ static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig) { - sig.expand(); - while (sig.size() > 1) { RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig.size() / 2); - sig_t.expand(); for (int i = 0; i < sig.size(); i += 2) { if (i+1 == sig.size()) { - sig_t.append(sig.chunks().at(i)); + sig_t.append(sig[i]); continue; } RTLIL::Cell *gate = new RTLIL::Cell; gate->name = NEW_ID; gate->type = "$_OR_"; - gate->connections["\\A"] = sig.chunks().at(i); - gate->connections["\\B"] = sig.chunks().at(i+1); - gate->connections["\\Y"] = sig_t.chunks().at(i/2); + gate->connections["\\A"] = sig[i]; + gate->connections["\\B"] = sig[i+1]; + gate->connections["\\Y"] = sig_t[i/2]; module->add(gate); } @@ -289,25 +268,18 @@ static void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell) static void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell) { - int width = cell->parameters.at("\\WIDTH").as_int(); - RTLIL::SigSpec sig_a = cell->connections.at("\\A"); - sig_a.expand(); - RTLIL::SigSpec sig_b = cell->connections.at("\\B"); - sig_b.expand(); - RTLIL::SigSpec sig_y = cell->connections.at("\\Y"); - sig_y.expand(); - for (int i = 0; i < width; i++) { + for (int i = 0; i < SIZE(sig_y); i++) { RTLIL::Cell *gate = new RTLIL::Cell; gate->name = NEW_ID; gate->type = "$_MUX_"; - gate->connections["\\A"] = sig_a.chunks().at(i); - gate->connections["\\B"] = sig_b.chunks().at(i); + gate->connections["\\A"] = sig_a[i]; + gate->connections["\\B"] = sig_b[i]; gate->connections["\\S"] = cell->connections.at("\\S"); - gate->connections["\\Y"] = sig_y.chunks().at(i); + gate->connections["\\Y"] = sig_y[i]; module->add(gate); } } @@ -335,13 +307,8 @@ static void simplemap_sr(RTLIL::Module *module, RTLIL::Cell *cell) char clr_pol = cell->parameters.at("\\CLR_POLARITY").as_bool() ? 'P' : 'N'; RTLIL::SigSpec sig_s = cell->connections.at("\\SET"); - sig_s.expand(); - RTLIL::SigSpec sig_r = cell->connections.at("\\CLR"); - sig_r.expand(); - RTLIL::SigSpec sig_q = cell->connections.at("\\Q"); - sig_q.expand(); std::string gate_type = stringf("$_SR_%c%c_", set_pol, clr_pol); @@ -349,9 +316,9 @@ static void simplemap_sr(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::Cell *gate = new RTLIL::Cell; gate->name = NEW_ID; gate->type = gate_type; - gate->connections["\\S"] = sig_s.chunks().at(i); - gate->connections["\\R"] = sig_r.chunks().at(i); - gate->connections["\\Q"] = sig_q.chunks().at(i); + gate->connections["\\S"] = sig_s[i]; + gate->connections["\\R"] = sig_r[i]; + gate->connections["\\Q"] = sig_q[i]; module->add(gate); } } @@ -362,12 +329,8 @@ static void simplemap_dff(RTLIL::Module *module, RTLIL::Cell *cell) char clk_pol = cell->parameters.at("\\CLK_POLARITY").as_bool() ? 'P' : 'N'; RTLIL::SigSpec sig_clk = cell->connections.at("\\CLK"); - RTLIL::SigSpec sig_d = cell->connections.at("\\D"); - sig_d.expand(); - RTLIL::SigSpec sig_q = cell->connections.at("\\Q"); - sig_q.expand(); std::string gate_type = stringf("$_DFF_%c_", clk_pol); @@ -376,8 +339,8 @@ static void simplemap_dff(RTLIL::Module *module, RTLIL::Cell *cell) gate->name = NEW_ID; gate->type = gate_type; gate->connections["\\C"] = sig_clk; - gate->connections["\\D"] = sig_d.chunks().at(i); - gate->connections["\\Q"] = sig_q.chunks().at(i); + gate->connections["\\D"] = sig_d[i]; + gate->connections["\\Q"] = sig_q[i]; module->add(gate); } } @@ -390,18 +353,10 @@ static void simplemap_dffsr(RTLIL::Module *module, RTLIL::Cell *cell) char clr_pol = cell->parameters.at("\\CLR_POLARITY").as_bool() ? 'P' : 'N'; RTLIL::SigSpec sig_clk = cell->connections.at("\\CLK"); - RTLIL::SigSpec sig_s = cell->connections.at("\\SET"); - sig_s.expand(); - RTLIL::SigSpec sig_r = cell->connections.at("\\CLR"); - sig_r.expand(); - RTLIL::SigSpec sig_d = cell->connections.at("\\D"); - sig_d.expand(); - RTLIL::SigSpec sig_q = cell->connections.at("\\Q"); - sig_q.expand(); std::string gate_type = stringf("$_DFFSR_%c%c%c_", clk_pol, set_pol, clr_pol); @@ -410,10 +365,10 @@ static void simplemap_dffsr(RTLIL::Module *module, RTLIL::Cell *cell) gate->name = NEW_ID; gate->type = gate_type; gate->connections["\\C"] = sig_clk; - gate->connections["\\S"] = sig_s.chunks().at(i); - gate->connections["\\R"] = sig_r.chunks().at(i); - gate->connections["\\D"] = sig_d.chunks().at(i); - gate->connections["\\Q"] = sig_q.chunks().at(i); + gate->connections["\\S"] = sig_s[i]; + gate->connections["\\R"] = sig_r[i]; + gate->connections["\\D"] = sig_d[i]; + gate->connections["\\Q"] = sig_q[i]; module->add(gate); } } @@ -430,12 +385,8 @@ static void simplemap_adff(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::SigSpec sig_clk = cell->connections.at("\\CLK"); RTLIL::SigSpec sig_rst = cell->connections.at("\\ARST"); - RTLIL::SigSpec sig_d = cell->connections.at("\\D"); - sig_d.expand(); - RTLIL::SigSpec sig_q = cell->connections.at("\\Q"); - sig_q.expand(); std::string gate_type_0 = stringf("$_DFF_%c%c0_", clk_pol, rst_pol); std::string gate_type_1 = stringf("$_DFF_%c%c1_", clk_pol, rst_pol); @@ -446,8 +397,8 @@ static void simplemap_adff(RTLIL::Module *module, RTLIL::Cell *cell) gate->type = rst_val.at(i) == RTLIL::State::S1 ? gate_type_1 : gate_type_0; gate->connections["\\C"] = sig_clk; gate->connections["\\R"] = sig_rst; - gate->connections["\\D"] = sig_d.chunks().at(i); - gate->connections["\\Q"] = sig_q.chunks().at(i); + gate->connections["\\D"] = sig_d[i]; + gate->connections["\\Q"] = sig_q[i]; module->add(gate); } } @@ -458,12 +409,8 @@ static void simplemap_dlatch(RTLIL::Module *module, RTLIL::Cell *cell) char en_pol = cell->parameters.at("\\EN_POLARITY").as_bool() ? 'P' : 'N'; RTLIL::SigSpec sig_en = cell->connections.at("\\EN"); - RTLIL::SigSpec sig_d = cell->connections.at("\\D"); - sig_d.expand(); - RTLIL::SigSpec sig_q = cell->connections.at("\\Q"); - sig_q.expand(); std::string gate_type = stringf("$_DLATCH_%c_", en_pol); @@ -472,8 +419,8 @@ static void simplemap_dlatch(RTLIL::Module *module, RTLIL::Cell *cell) gate->name = NEW_ID; gate->type = gate_type; gate->connections["\\E"] = sig_en; - gate->connections["\\D"] = sig_d.chunks().at(i); - gate->connections["\\Q"] = sig_q.chunks().at(i); + gate->connections["\\D"] = sig_d[i]; + gate->connections["\\Q"] = sig_q[i]; module->add(gate); } } -- cgit v1.2.3 From c094c53de83707a5bf1b268640283f1dde235873 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 23 Jul 2014 20:32:28 +0200 Subject: Removed RTLIL::SigSpec::optimize() --- passes/abc/blifparse.cc | 3 --- passes/cmds/setundef.cc | 1 - passes/cmds/show.cc | 3 --- passes/cmds/splice.cc | 2 -- passes/cmds/splitnets.cc | 2 +- passes/fsm/fsm_map.cc | 5 ----- passes/memory/memory_collect.cc | 7 ------- passes/memory/memory_dff.cc | 1 - passes/memory/memory_share.cc | 2 -- passes/opt/opt_clean.cc | 2 -- passes/opt/opt_const.cc | 2 -- passes/proc/proc_dff.cc | 4 ---- passes/proc/proc_init.cc | 2 -- passes/sat/eval.cc | 3 --- passes/sat/freduce.cc | 10 +++++----- passes/sat/sat.cc | 5 ----- 16 files changed, 6 insertions(+), 48 deletions(-) (limited to 'passes') diff --git a/passes/abc/blifparse.cc b/passes/abc/blifparse.cc index 47fa0f821..04977b369 100644 --- a/passes/abc/blifparse.cc +++ b/passes/abc/blifparse.cc @@ -212,9 +212,6 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name) goto continue_without_read; } - input_sig.optimize(); - output_sig.optimize(); - RTLIL::Cell *cell = new RTLIL::Cell; cell->name = NEW_ID; cell->type = "$lut"; diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index 63d5bb9af..6c4bb16c0 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -144,7 +144,6 @@ struct SetundefPass : public Pass { RTLIL::SigSpec bits; for (int i = 0; i < c.width; i++) bits.append(worker.next_bit()); - bits.optimize(); module->connections.push_back(RTLIL::SigSig(c, bits)); } } diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index 37fe44047..6b37b7bb1 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -171,8 +171,6 @@ struct ShowWorker std::string gen_signode_simple(RTLIL::SigSpec sig, bool range_check = true) { - sig.optimize(); - if (sig.chunks().size() == 0) { fprintf(f, "v%d [ label=\"\" ];\n", single_idx_count); return stringf("v%d", single_idx_count++); @@ -199,7 +197,6 @@ struct ShowWorker if (net.empty()) { std::string label_string; - sig.optimize(); int pos = sig.size()-1; int idx = single_idx_count++; for (int i = int(sig.chunks().size())-1; i >= 0; i--) { diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc index aed9c076e..68e8951ff 100644 --- a/passes/cmds/splice.cc +++ b/passes/cmds/splice.cc @@ -82,7 +82,6 @@ struct SpliceWorker module->add(cell); } - new_sig.optimize(); sliced_signals_cache[sig] = new_sig; return new_sig; @@ -143,7 +142,6 @@ struct SpliceWorker module->add(cell); } - new_sig.optimize(); spliced_signals_cache[sig] = new_sig; log(" Created spliced signal: %s -> %s\n", log_signal(sig), log_signal(new_sig)); diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc index c40ff2c4a..c65b6a5f8 100644 --- a/passes/cmds/splitnets.cc +++ b/passes/cmds/splitnets.cc @@ -141,7 +141,7 @@ struct SplitnetsPass : public Pass { if (!ct.cell_output(c.second->type, p.first)) continue; - RTLIL::SigSpec sig = p.second.optimized(); + RTLIL::SigSpec sig = p.second; for (auto &chunk : sig.chunks()) { if (chunk.wire == NULL) continue; diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc index 9dda2ba89..cee267629 100644 --- a/passes/fsm/fsm_map.cc +++ b/passes/fsm/fsm_map.cc @@ -42,13 +42,10 @@ static void implement_pattern_cache(RTLIL::Module *module, std::mapparameters["\\SIZE"] = RTLIL::Const(memory->size); mem->parameters["\\ABITS"] = RTLIL::Const(addr_bits); - sig_wr_clk_enable.optimize(); - sig_wr_clk_polarity.optimize(); - assert(sig_wr_clk.size() == wr_ports); assert(sig_wr_clk_enable.size() == wr_ports && sig_wr_clk_enable.is_fully_const()); assert(sig_wr_clk_polarity.size() == wr_ports && sig_wr_clk_polarity.is_fully_const()); @@ -158,10 +155,6 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) mem->connections["\\WR_DATA"] = sig_wr_data; mem->connections["\\WR_EN"] = sig_wr_en; - sig_rd_clk_enable.optimize(); - sig_rd_clk_polarity.optimize(); - sig_rd_transparent.optimize(); - assert(sig_rd_clk.size() == rd_ports); assert(sig_rd_clk_enable.size() == rd_ports && sig_rd_clk_enable.is_fully_const()); assert(sig_rd_clk_polarity.size() == rd_ports && sig_rd_clk_polarity.is_fully_const()); diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index b1f1e22b5..56915776e 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -69,7 +69,6 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI replaced_this_bit:; } - sig.optimize(); return true; } diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index 38eff9961..dd2a32cad 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -439,8 +439,6 @@ struct MemoryShareWorker merged_en.replace(k, cell_en.extract(k, 1)); merged_data.replace(k, cell_data.extract(k, 1)); } - merged_en.optimize(); - merged_data.optimize(); } // Connect the new EN and DATA signals and remove the old write port. diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 0be36606d..ba0aadc6b 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -241,8 +241,6 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool new_conn.second.append_bit(s2[i]); } if (new_conn.first.size() > 0) { - new_conn.first.optimize(); - new_conn.second.optimize(); used_signals.add(new_conn.first); used_signals.add(new_conn.second); module->connections.push_back(new_conn); diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index ff139854f..800fbf109 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -481,8 +481,6 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo } if (new_a.size() < a.size() || new_b.size() < b.size()) { - new_a.optimize(); - new_b.optimize(); cell->connections["\\A"] = new_a; cell->connections["\\B"] = new_b; cell->parameters["\\A_WIDTH"] = new_a.size(); diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index 8e5fbe8f4..a8aba903a 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -352,10 +352,6 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) ce.assign_map.apply(rstval); ce.assign_map.apply(sig); - insig.optimize(); - rstval.optimize(); - sig.optimize(); - if (rstval == sig) { rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size()); sync_level = NULL; diff --git a/passes/proc/proc_init.cc b/passes/proc/proc_init.cc index ba1fb5ab9..4c9b6bcd2 100644 --- a/passes/proc/proc_init.cc +++ b/passes/proc/proc_init.cc @@ -28,7 +28,6 @@ static void proc_get_const(RTLIL::SigSpec &sig, RTLIL::CaseRule &rule) assert(rule.compare.size() == 0); while (1) { - sig.optimize(); RTLIL::SigSpec tmp = sig; for (auto &it : rule.actions) tmp.replace(it.first, it.second); @@ -53,7 +52,6 @@ static void proc_init(RTLIL::Module *mod, RTLIL::Process *proc) RTLIL::SigSpec lhs = action.first; RTLIL::SigSpec rhs = action.second; - lhs.optimize(); proc_get_const(rhs, proc->root_case); if (!rhs.is_fully_const()) diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc index 9b8c35361..6949b76db 100644 --- a/passes/sat/eval.cc +++ b/passes/sat/eval.cc @@ -53,8 +53,6 @@ struct BruteForceEquivChecker return; } - inputs.optimize(); - ConstEval ce1(mod1), ce2(mod2); ce1.set(mod1_inputs, inputs.as_const()); ce2.set(mod2_inputs, inputs.as_const()); @@ -482,7 +480,6 @@ struct EvalPass : public Pass { RTLIL::SigSpec signal, value, undef; if (!RTLIL::SigSpec::parse_sel(signal, design, module, it)) log_cmd_error("Failed to parse show expression `%s'.\n", it.c_str()); - signal.optimize(); value = signal; if (set_undef) { while (!ce.eval(value, undef)) { diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index 1e47e7de2..ba01bc322 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -349,7 +349,7 @@ struct PerformReduction std::vector bucket_sigbits; for (int idx : bucket) bucket_sigbits.push_back(out_bits[idx]); - log("%s Trying to shatter bucket with %d signals: %s\n", indt, int(bucket.size()), log_signal(RTLIL::SigSpec(bucket_sigbits).optimized())); + log("%s Trying to shatter bucket with %d signals: %s\n", indt, int(bucket.size()), log_signal(bucket_sigbits)); } std::vector sat_set_list, sat_clr_list; @@ -494,7 +494,7 @@ struct PerformReduction std::vector r_sigbits; for (int idx : r) r_sigbits.push_back(out_bits[idx]); - log(" Found group of %d equivialent signals: %s\n", int(r.size()), log_signal(RTLIL::SigSpec(r_sigbits).optimized())); + log(" Found group of %d equivialent signals: %s\n", int(r.size()), log_signal(r_sigbits)); } std::vector undef_slaves; @@ -640,7 +640,7 @@ struct FreduceWorker found_selected_wire: log(" Finding reduced input cone for signal batch %s%c\n", - log_signal(RTLIL::SigSpec(std::vector(batch.begin(), batch.end())).optimized()), verbose_level ? ':' : '.'); + log_signal(batch), verbose_level ? ':' : '.'); FindReducedInputs infinder(sigmap, drivers); for (auto &bit : batch) { @@ -663,12 +663,12 @@ struct FreduceWorker continue; if (bucket.first.size() == 0) { - log(" Finding const values for bucket %s%c\n", log_signal(RTLIL::SigSpec(bucket.second).optimized()), verbose_level ? ':' : '.'); + log(" Finding const values for bucket %s%c\n", log_signal(bucket.second), verbose_level ? ':' : '.'); PerformReduction worker(sigmap, drivers, inv_pairs, bucket.second, bucket.first.size()); for (size_t idx = 0; idx < bucket.second.size(); idx++) worker.analyze_const(equiv, idx); } else { - log(" Trying to shatter bucket %s%c\n", log_signal(RTLIL::SigSpec(bucket.second).optimized()), verbose_level ? ':' : '.'); + log(" Trying to shatter bucket %s%c\n", log_signal(bucket.second), verbose_level ? ':' : '.'); PerformReduction worker(sigmap, drivers, inv_pairs, bucket.second, bucket.first.size()); worker.analyze(equiv, 100 * bucket_count / (buckets.size() + 1)); } diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 34becaee8..4b6b1b719 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -114,10 +114,6 @@ struct SatHelper } } - lhs.optimize(); - rhs.optimize(); - removed_bits.optimize(); - if (removed_bits.size()) log("Warning: ignoring initial value on non-register: %s\n", log_signal(removed_bits)); @@ -152,7 +148,6 @@ struct SatHelper if (!satgen.initial_state.check_all(big_lhs)) { RTLIL::SigSpec rem = satgen.initial_state.remove(big_lhs); - rem.optimize(); log_cmd_error("Found -set-init bits that are not part of the initial_state: %s\n", log_signal(rem)); } -- cgit v1.2.3 From 20a7965f61a43b8c367b1042081a57b5a4005b33 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 23 Jul 2014 20:45:27 +0200 Subject: Various small fixes (from gcc compiler warnings) --- passes/fsm/fsmdata.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'passes') diff --git a/passes/fsm/fsmdata.h b/passes/fsm/fsmdata.h index d0be71c5b..ae9569ed7 100644 --- a/passes/fsm/fsmdata.h +++ b/passes/fsm/fsmdata.h @@ -143,25 +143,25 @@ struct FsmData log(" Input signals:\n"); RTLIL::SigSpec sig_in = cell->connections["\\CTRL_IN"]; for (int i = 0; i < SIZE(sig_in); i++) - log(" %3zd: %s\n", i, log_signal(sig_in[i])); + log(" %3d: %s\n", i, log_signal(sig_in[i])); log("\n"); log(" Output signals:\n"); RTLIL::SigSpec sig_out = cell->connections["\\CTRL_OUT"]; for (int i = 0; i < SIZE(sig_out); i++) - log(" %3zd: %s\n", i, log_signal(sig_out[i])); + log(" %3d: %s\n", i, log_signal(sig_out[i])); log("\n"); log(" State encoding:\n"); for (int i = 0; i < SIZE(state_table); i++) - log(" %3zd: %10s%s\n", i, log_signal(state_table[i], false), + log(" %3d: %10s%s\n", i, log_signal(state_table[i], false), int(i) == reset_state ? " " : ""); log("\n"); log(" Transition Table (state_in, ctrl_in, state_out, ctrl_out):\n"); for (int i = 0; i < SIZE(transition_table); i++) { transition_t &tr = transition_table[i]; - log(" %5zd: %5d %s -> %5d %s\n", i, tr.state_in, log_signal(tr.ctrl_in), tr.state_out, log_signal(tr.ctrl_out)); + log(" %5d: %5d %s -> %5d %s\n", i, tr.state_in, log_signal(tr.ctrl_in), tr.state_out, log_signal(tr.ctrl_out)); } log("\n"); -- cgit v1.2.3 From 2f54345cff3aea768bb89754654127a3b0ee58e9 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 24 Jul 2014 15:06:45 +0200 Subject: Added "cover" command --- passes/cmds/Makefile.inc | 1 + passes/cmds/cover.cc | 115 +++++++++++++++++++++++++++++++++++++++++++++++ passes/cmds/tee.cc | 2 +- 3 files changed, 117 insertions(+), 1 deletion(-) create mode 100644 passes/cmds/cover.cc (limited to 'passes') diff --git a/passes/cmds/Makefile.inc b/passes/cmds/Makefile.inc index 3a4b2da71..6ae4495a8 100644 --- a/passes/cmds/Makefile.inc +++ b/passes/cmds/Makefile.inc @@ -17,4 +17,5 @@ OBJS += passes/cmds/scc.o OBJS += passes/cmds/log.o OBJS += passes/cmds/tee.o OBJS += passes/cmds/connwrappers.o +OBJS += passes/cmds/cover.o diff --git a/passes/cmds/cover.cc b/passes/cmds/cover.cc new file mode 100644 index 000000000..ebbdc7c4c --- /dev/null +++ b/passes/cmds/cover.cc @@ -0,0 +1,115 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2014 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/register.h" +#include "kernel/rtlil.h" +#include "kernel/log.h" + +struct CoverPass : public Pass { + CoverPass() : Pass("cover", "print code coverage counters") { } + virtual void help() + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" cover [-q] [-o logfile|-a logfile]\n"); + log("\n"); + log("Print the code coverage counters collected using the cover() macro in the Yosys\n"); + log("C++ code. This is useful to figure out what parts of Yosys are utilized by a\n"); + log("test bench.\n"); + log("\n"); + log(" -q\n"); + log(" Do not print output to the normal destination (console and/or log file)\n"); + log("\n"); + log(" -o logfile\n"); + log(" Write output to this file, truncate if exists.\n"); + log("\n"); + log(" -a logfile\n"); + log(" Write output to this file, append if exists.\n"); + log("\n"); + log("\n"); + log("It is also possible to instruct Yosys to print the coverage counters to a file\n"); + log("using environment variables.\n"); + log("\n"); + log(" YOSYS_COVER_DIR=\"{dir-name}\" yosys {args}n"); + log("\n"); + log(" This will create a file (with an auto-generated name) in this\n"); + log(" directory and wire the coverage counters to it.\n"); + log("\n"); + log(" YOSYS_COVER_FILE=\"{file-name}\" yosys {args}n"); + log("\n"); + log(" This will append the coverage counters to the specified file.\n"); + log("\n"); + log("\n"); + log("Hint: Use the following AWK command to consolidate Yosys coverage files:\n"); + log("\n"); + log(" gawk '{ p[$3] = $1; c[$3] += $2; } END { for (i in p)\n"); + log(" printf \"%%-60s %%10d %%s\\n\", p[i], c[i], i; }' {files} | sort -k3\n"); + log("\n"); + } + virtual void execute(std::vector args, RTLIL::Design *design) + { + std::vector out_files; + bool do_log = true; + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) + { + if (args[argidx] == "-q") { + do_log = false; + continue; + } + if ((args[argidx] == "-o" || args[argidx] == "-a") && argidx+1 < args.size()) { + const char *open_mode = args[argidx] == "-o" ? "w" : "a+"; + FILE *f = fopen(args[++argidx].c_str(), open_mode); + if (f == NULL) { + for (auto f : out_files) + fclose(f); + log_cmd_error("Can't create file %s.\n", args[argidx].c_str()); + } + out_files.push_back(f); + continue; + } + break; + } + extra_args(args, argidx, design); + + if (do_log) { + log_header("Printing code coverage counters.\n"); + log("\n"); + } + +#ifndef NDEBUG + for (auto &it : get_coverage_data()) { + for (auto f : out_files) + fprintf(f, "%-60s %10d %s\n", it.second.first.c_str(), it.second.second, it.first.c_str()); + if (do_log) + log("%-60s %10d %s\n", it.second.first.c_str(), it.second.second, it.first.c_str()); + } +#else + for (auto f : out_files) + fclose(f); + + log_cmd_error("Coverage counters are only available in debug builds of Yosys."); +#endif + + for (auto f : out_files) + fclose(f); + } +} CoverPass; + diff --git a/passes/cmds/tee.cc b/passes/cmds/tee.cc index dd9591954..e2f69e599 100644 --- a/passes/cmds/tee.cc +++ b/passes/cmds/tee.cc @@ -56,7 +56,7 @@ struct TeePass : public Pass { continue; } if ((args[argidx] == "-o" || args[argidx] == "-a") && argidx+1 < args.size()) { - const char *open_mode = args[argidx] == "-o" ? "wt" : "at"; + const char *open_mode = args[argidx] == "-o" ? "w" : "a+"; FILE *f = fopen(args[++argidx].c_str(), open_mode); if (f == NULL) { for (auto cf : files_to_close) -- cgit v1.2.3 From b17d6531c833f9064c5888c694aa24e8a395b72a Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 24 Jul 2014 17:15:01 +0200 Subject: Added "make PRETTY=1" --- passes/techmap/Makefile.inc | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'passes') diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc index 85d580ce8..c901da1c9 100644 --- a/passes/techmap/Makefile.inc +++ b/passes/techmap/Makefile.inc @@ -10,11 +10,11 @@ OBJS += passes/techmap/extract.o GENFILES += passes/techmap/stdcells.inc passes/techmap/stdcells.inc: techlibs/common/stdcells.v - echo "// autogenerated from $<" > $@.new - echo "static char stdcells_code[] = {" >> $@.new - od -v -td1 -An $< | $(SED) -e 's/[0-9][0-9]*/&,/g' >> $@.new - echo "0};" >> $@.new - mv $@.new $@ + $(P) echo "// autogenerated from $<" > $@.new + $(Q) echo "static char stdcells_code[] = {" >> $@.new + $(Q) od -v -td1 -An $< | $(SED) -e 's/[0-9][0-9]*/&,/g' >> $@.new + $(Q) echo "0};" >> $@.new + $(Q) mv $@.new $@ passes/techmap/techmap.o: passes/techmap/stdcells.inc @@ -22,5 +22,5 @@ TARGETS += yosys-filterlib GENFILES += passes/techmap/filterlib.o yosys-filterlib: passes/techmap/filterlib.o - $(CXX) -o yosys-filterlib $(LDFLAGS) $^ $(LDLIBS) + $(P) $(CXX) -o yosys-filterlib $(LDFLAGS) $^ $(LDLIBS) -- cgit v1.2.3 From 45b4154b3799178a432d1f14dcaf51787b86f35d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 24 Jul 2014 19:03:57 +0200 Subject: Added "make SMALL=1" --- passes/techmap/Makefile.inc | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc index c901da1c9..e54c018aa 100644 --- a/passes/techmap/Makefile.inc +++ b/passes/techmap/Makefile.inc @@ -2,10 +2,13 @@ OBJS += passes/techmap/techmap.o OBJS += passes/techmap/simplemap.o OBJS += passes/techmap/dfflibmap.o +OBJS += passes/techmap/libparse.o + +ifneq ($(SMALL),1) OBJS += passes/techmap/iopadmap.o OBJS += passes/techmap/hilomap.o -OBJS += passes/techmap/libparse.o OBJS += passes/techmap/extract.o +endif GENFILES += passes/techmap/stdcells.inc -- cgit v1.2.3 From 9962384d3ed26ea0707f1ed8ebef91593d1a42a4 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 24 Jul 2014 19:36:43 +0200 Subject: Added cover() calls to opt_const --- passes/opt/opt_const.cc | 54 ++++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 45 insertions(+), 9 deletions(-) (limited to 'passes') diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index 800fbf109..e2bf7004f 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -183,6 +183,8 @@ static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool com log("\n"); } + cover_list("opt.opt_const.fine.group", "$not", "$pos", "$bu0", "$and", "$or", "$xor", "$xnor", cell->type); + module->remove(cell); OPT_DID_SOMETHING = true; did_something = true; @@ -209,7 +211,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo for (auto cell : cells) { -#define ACTION_DO(_p_, _s_) do { replace_cell(module, cell, input.as_string(), _p_, _s_); goto next_cell; } while (0) +#define ACTION_DO(_p_, _s_) do { cover("opt.opt_const.action_" S__LINE__); replace_cell(module, cell, input.as_string(), _p_, _s_); goto next_cell; } while (0) #define ACTION_DO_Y(_v_) ACTION_DO("\\Y", RTLIL::SigSpec(RTLIL::State::S ## _v_)) if (do_fine) @@ -236,6 +238,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo } if (new_a != RTLIL::State::Sm && RTLIL::SigSpec(new_a) != sig_a) { + cover("opt.opt_const.fine.$reduce_and"); log("Replacing port A of %s cell `%s' in module `%s' with constant driver: %s -> %s\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a)); cell->connections.at("\\A") = sig_a = new_a; @@ -262,6 +265,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo } if (new_a != RTLIL::State::Sm && RTLIL::SigSpec(new_a) != sig_a) { + cover_list("opt.opt_const.fine.A", "$logic_not", "$logic_and", "$logic_or", "$reduce_or", "$reduce_bool", cell->type); log("Replacing port A of %s cell `%s' in module `%s' with constant driver: %s -> %s\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a)); cell->connections.at("\\A") = sig_a = new_a; @@ -288,6 +292,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo } if (new_b != RTLIL::State::Sm && RTLIL::SigSpec(new_b) != sig_b) { + cover_list("opt.opt_const.fine.B", "$logic_and", "$logic_or", cell->type); log("Replacing port B of %s cell `%s' in module `%s' with constant driver: %s -> %s\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_b), log_signal(new_b)); cell->connections.at("\\B") = sig_b = new_b; @@ -299,11 +304,13 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo } if (cell->type == "$logic_or" && (assign_map(cell->connections.at("\\A")) == RTLIL::State::S1 || assign_map(cell->connections.at("\\B")) == RTLIL::State::S1)) { + cover("opt.opt_const.one_high"); replace_cell(module, cell, "one high", "\\Y", RTLIL::State::S1); goto next_cell; } if (cell->type == "$logic_and" && (assign_map(cell->connections.at("\\A")) == RTLIL::State::S0 || assign_map(cell->connections.at("\\B")) == RTLIL::State::S0)) { + cover("opt.opt_const.one_low"); replace_cell(module, cell, "one low", "\\Y", RTLIL::State::S0); goto next_cell; } @@ -330,6 +337,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (0) { found_the_x_bit: + cover_list("opt.opt_const.xbit", "$reduce_xor", "$reduce_xnor", "$shl", "$shr", "$sshl", "$sshr", "$lt", "$le", "$ge", "$gt", + "$neg", "$add", "$sub", "$mul", "$div", "$mod", "$pow", cell->type); if (cell->type == "$reduce_xor" || cell->type == "$reduce_xnor" || cell->type == "$lt" || cell->type == "$le" || cell->type == "$ge" || cell->type == "$gt") replace_cell(module, cell, "x-bit in input", "\\Y", RTLIL::State::Sx); @@ -341,11 +350,13 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if ((cell->type == "$_INV_" || cell->type == "$not" || cell->type == "$logic_not") && cell->connections["\\Y"].size() == 1 && invert_map.count(assign_map(cell->connections["\\A"])) != 0) { + cover_list("opt.opt_const.invert.double", "$_INV_", "$not", "$logic_not", cell->type); replace_cell(module, cell, "double_invert", "\\Y", invert_map.at(assign_map(cell->connections["\\A"]))); goto next_cell; } if ((cell->type == "$_MUX_" || cell->type == "$mux") && invert_map.count(assign_map(cell->connections["\\S"])) != 0) { + cover_list("opt.opt_const.invert.muxsel", "$_MUX_", "$mux", cell->type); RTLIL::SigSpec tmp = cell->connections["\\A"]; cell->connections["\\A"] = cell->connections["\\B"]; cell->connections["\\B"] = tmp; @@ -428,6 +439,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (input.match(" 1")) ACTION_DO("\\Y", input.extract(1, 1)); if (input.match("01 ")) ACTION_DO("\\Y", input.extract(0, 1)); if (input.match("10 ")) { + cover("opt.opt_const.mux_to_inv"); cell->type = "$_INV_"; cell->connections["\\A"] = input.extract(0, 1); cell->connections.erase("\\B"); @@ -462,9 +474,10 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo assert(SIZE(a) == SIZE(b)); for (int i = 0; i < SIZE(a); i++) { if (a[i].wire == NULL && b[i].wire == NULL && a[i] != b[i] && a[i].data <= RTLIL::State::S1 && b[i].data <= RTLIL::State::S1) { + cover_list("opt.opt_const.eqneq.isneq", "$eq", "$ne", "$eqx", "$nex", cell->type); RTLIL::SigSpec new_y = RTLIL::SigSpec((cell->type == "$eq" || cell->type == "$eqx") ? RTLIL::State::S0 : RTLIL::State::S1); new_y.extend(cell->parameters["\\Y_WIDTH"].as_int(), false); - replace_cell(module, cell, "empty", "\\Y", new_y); + replace_cell(module, cell, "isneq", "\\Y", new_y); goto next_cell; } if (a[i] == b[i]) @@ -474,6 +487,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo } if (new_a.size() == 0) { + cover_list("opt.opt_const.eqneq.empty", "$eq", "$ne", "$eqx", "$nex", cell->type); RTLIL::SigSpec new_y = RTLIL::SigSpec((cell->type == "$eq" || cell->type == "$eqx") ? RTLIL::State::S1 : RTLIL::State::S0); new_y.extend(cell->parameters["\\Y_WIDTH"].as_int(), false); replace_cell(module, cell, "empty", "\\Y", new_y); @@ -481,6 +495,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo } if (new_a.size() < a.size() || new_b.size() < b.size()) { + cover_list("opt.opt_const.eqneq.resize", "$eq", "$ne", "$eqx", "$nex", cell->type); cell->connections["\\A"] = new_a; cell->connections["\\B"] = new_b; cell->parameters["\\A_WIDTH"] = new_a.size(); @@ -495,10 +510,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo RTLIL::SigSpec b = assign_map(cell->connections["\\B"]); if (a.is_fully_const()) { - RTLIL::SigSpec tmp; - tmp = a, a = b, b = tmp; - cell->connections["\\A"] = a; - cell->connections["\\B"] = b; + cover_list("opt.opt_const.eqneq.swapconst", "$eq", "$ne", cell->type); + std::swap(cell->connections["\\A"], cell->connections["\\B"]); } if (b.is_fully_const()) { @@ -506,6 +519,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo RTLIL::SigSpec input = b; ACTION_DO("\\Y", cell->connections["\\A"]); } else { + cover_list("opt.opt_const.eqneq.isnot", "$eq", "$ne", cell->type); cell->type = "$not"; cell->parameters.erase("\\B_WIDTH"); cell->parameters.erase("\\B_SIGNED"); @@ -563,6 +577,11 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (identity_wrt_a || identity_wrt_b) { + if (identity_wrt_a) + cover_list("opt.opt_const.identwrt.a", "$add", "$sub", "$or", "$xor", "$shl", "$shr", "$sshl", "$sshr", "$mul", "$div", cell->type); + if (identity_wrt_b) + cover_list("opt.opt_const.identwrt.b", "$add", "$sub", "$or", "$xor", "$shl", "$shr", "$sshl", "$sshr", "$mul", "$div", cell->type); + log("Replacing %s cell `%s' in module `%s' with identity for port %c.\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str(), identity_wrt_a ? 'A' : 'B'); @@ -586,12 +605,14 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->connections["\\A"] == RTLIL::SigSpec(0, 1) && cell->connections["\\B"] == RTLIL::SigSpec(1, 1)) { + cover_list("opt.opt_const.mux_bool", "$mux", "$_MUX_", cell->type); replace_cell(module, cell, "mux_bool", "\\Y", cell->connections["\\S"]); goto next_cell; } if (mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->connections["\\A"] == RTLIL::SigSpec(1, 1) && cell->connections["\\B"] == RTLIL::SigSpec(0, 1)) { + cover_list("opt.opt_const.mux_invert", "$mux", "$_MUX_", cell->type); cell->connections["\\A"] = cell->connections["\\S"]; cell->connections.erase("\\B"); cell->connections.erase("\\S"); @@ -609,6 +630,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo } if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->connections["\\A"] == RTLIL::SigSpec(0, 1)) { + cover_list("opt.opt_const.mux_and", "$mux", "$_MUX_", cell->type); cell->connections["\\A"] = cell->connections["\\S"]; cell->connections.erase("\\S"); if (cell->type == "$mux") { @@ -627,6 +649,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo } if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->connections["\\B"] == RTLIL::SigSpec(1, 1)) { + cover_list("opt.opt_const.mux_or", "$mux", "$_MUX_", cell->type); cell->connections["\\B"] = cell->connections["\\S"]; cell->connections.erase("\\S"); if (cell->type == "$mux") { @@ -649,7 +672,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo int width = cell->connections.at("\\A").size(); if ((cell->connections.at("\\A").is_fully_undef() && cell->connections.at("\\B").is_fully_undef()) || cell->connections.at("\\S").is_fully_undef()) { - replace_cell(module, cell, "mux undef", "\\Y", cell->connections.at("\\A")); + cover_list("opt.opt_const.mux_undef", "$mux", "$pmux", cell->type); + replace_cell(module, cell, "mux_undef", "\\Y", cell->connections.at("\\A")); goto next_cell; } for (int i = 0; i < cell->connections.at("\\S").size(); i++) { @@ -667,14 +691,17 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo new_s = new_s.extract(0, new_s.size()-1); } if (new_s.size() == 0) { - replace_cell(module, cell, "mux undef", "\\Y", new_a); + cover_list("opt.opt_const.mux_empty", "$mux", "$pmux", cell->type); + replace_cell(module, cell, "mux_empty", "\\Y", new_a); goto next_cell; } if (new_a == RTLIL::SigSpec(RTLIL::State::S0) && new_b == RTLIL::SigSpec(RTLIL::State::S1)) { - replace_cell(module, cell, "mux undef", "\\Y", new_s); + cover_list("opt.opt_const.mux_sel01", "$mux", "$pmux", cell->type); + replace_cell(module, cell, "mux_sel01", "\\Y", new_s); goto next_cell; } if (cell->connections.at("\\S").size() != new_s.size()) { + cover_list("opt.opt_const.mux_reduce", "$mux", "$pmux", cell->type); cell->connections.at("\\A") = new_a; cell->connections.at("\\B") = new_b; cell->connections.at("\\S") = new_s; @@ -699,6 +726,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo RTLIL::SigSpec y(RTLIL::const_ ## _t(a.as_const(), dummy_arg, \ cell->parameters["\\A_SIGNED"].as_bool(), false, \ cell->parameters["\\Y_WIDTH"].as_int())); \ + cover("opt.opt_const.const.$" #_t); \ replace_cell(module, cell, stringf("%s", log_signal(a)), "\\Y", y); \ goto next_cell; \ } \ @@ -713,6 +741,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cell->parameters["\\A_SIGNED"].as_bool(), \ cell->parameters["\\B_SIGNED"].as_bool(), \ cell->parameters["\\Y_WIDTH"].as_int())); \ + cover("opt.opt_const.const.$" #_t); \ replace_cell(module, cell, stringf("%s, %s", log_signal(a), log_signal(b)), "\\Y", y); \ goto next_cell; \ } \ @@ -787,6 +816,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (a_val == 0) { + cover("opt.opt_const.mul_shift.zero"); + log("Replacing multiply-by-zero cell `%s' in module `%s' with zero-driver.\n", cell->name.c_str(), module->name.c_str()); @@ -801,6 +832,11 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo for (int i = 1; i < (a_signed ? sig_a.size()-1 : sig_a.size()); i++) if (a_val == (1 << i)) { + if (swapped_ab) + cover("opt.opt_const.mul_shift.swapped"); + else + cover("opt.opt_const.mul_shift.unswapped"); + log("Replacing multiply-by-%d cell `%s' in module `%s' with shift-by-%d.\n", a_val, cell->name.c_str(), module->name.c_str(), i); -- cgit v1.2.3 From 6aa792c864444324a1b140c2b63bd860f0cc3914 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 24 Jul 2014 22:47:57 +0200 Subject: Replaced more old SigChunk programming patterns --- passes/abc/abc.cc | 38 +++++++++++++++++++------------------- passes/cmds/show.cc | 4 ++-- passes/memory/memory_collect.cc | 10 +++++----- passes/opt/opt_clean.cc | 13 ++++--------- passes/proc/proc_dff.cc | 2 +- passes/proc/proc_init.cc | 19 +++++++++---------- 6 files changed, 40 insertions(+), 46 deletions(-) (limited to 'passes') diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index ba27a3fc6..d25f88c0d 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -709,15 +709,15 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std cell_stats[RTLIL::unescape_id(c->type)]++; if (c->type == "\\ZERO" || c->type == "\\ONE") { RTLIL::SigSig conn; - conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].chunks()[0].wire->name)]); + conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].as_wire()->name)]); conn.second = RTLIL::SigSpec(c->type == "\\ZERO" ? 0 : 1, 1); module->connections.push_back(conn); continue; } if (c->type == "\\BUF") { RTLIL::SigSig conn; - conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].chunks()[0].wire->name)]); - conn.second = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].chunks()[0].wire->name)]); + conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].as_wire()->name)]); + conn.second = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].as_wire()->name)]); module->connections.push_back(conn); continue; } @@ -725,8 +725,8 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std RTLIL::Cell *cell = new RTLIL::Cell; cell->type = "$_INV_"; cell->name = remap_name(c->name); - cell->connections["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].chunks()[0].wire->name)]); - cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].chunks()[0].wire->name)]); + cell->connections["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].as_wire()->name)]); + cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].as_wire()->name)]); module->cells[cell->name] = cell; design->select(module, cell); continue; @@ -735,9 +735,9 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std RTLIL::Cell *cell = new RTLIL::Cell; cell->type = "$_" + c->type.substr(1) + "_"; cell->name = remap_name(c->name); - cell->connections["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].chunks()[0].wire->name)]); - cell->connections["\\B"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\B"].chunks()[0].wire->name)]); - cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].chunks()[0].wire->name)]); + cell->connections["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].as_wire()->name)]); + cell->connections["\\B"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\B"].as_wire()->name)]); + cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].as_wire()->name)]); module->cells[cell->name] = cell; design->select(module, cell); continue; @@ -746,10 +746,10 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std RTLIL::Cell *cell = new RTLIL::Cell; cell->type = "$_MUX_"; cell->name = remap_name(c->name); - cell->connections["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].chunks()[0].wire->name)]); - cell->connections["\\B"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\B"].chunks()[0].wire->name)]); - cell->connections["\\S"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\S"].chunks()[0].wire->name)]); - cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].chunks()[0].wire->name)]); + cell->connections["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].as_wire()->name)]); + cell->connections["\\B"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\B"].as_wire()->name)]); + cell->connections["\\S"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\S"].as_wire()->name)]); + cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].as_wire()->name)]); module->cells[cell->name] = cell; design->select(module, cell); continue; @@ -759,8 +759,8 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std RTLIL::Cell *cell = new RTLIL::Cell; cell->type = clk_polarity ? "$_DFF_P_" : "$_DFF_N_"; cell->name = remap_name(c->name); - cell->connections["\\D"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\D"].chunks()[0].wire->name)]); - cell->connections["\\Q"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Q"].chunks()[0].wire->name)]); + cell->connections["\\D"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\D"].as_wire()->name)]); + cell->connections["\\Q"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Q"].as_wire()->name)]); cell->connections["\\C"] = clk_sig; module->cells[cell->name] = cell; design->select(module, cell); @@ -777,7 +777,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std cell_stats[RTLIL::unescape_id(c->type)]++; if (c->type == "\\_const0_" || c->type == "\\_const1_") { RTLIL::SigSig conn; - conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections.begin()->second.chunks()[0].wire->name)]); + conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections.begin()->second.as_wire()->name)]); conn.second = RTLIL::SigSpec(c->type == "\\_const0_" ? 0 : 1, 1); module->connections.push_back(conn); continue; @@ -787,8 +787,8 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std RTLIL::Cell *cell = new RTLIL::Cell; cell->type = clk_polarity ? "$_DFF_P_" : "$_DFF_N_"; cell->name = remap_name(c->name); - cell->connections["\\D"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\D"].chunks()[0].wire->name)]); - cell->connections["\\Q"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Q"].chunks()[0].wire->name)]); + cell->connections["\\D"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\D"].as_wire()->name)]); + cell->connections["\\Q"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Q"].as_wire()->name)]); cell->connections["\\C"] = clk_sig; module->cells[cell->name] = cell; design->select(module, cell); @@ -815,9 +815,9 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std for (auto conn : mapped_mod->connections) { if (!conn.first.is_fully_const()) - conn.first = RTLIL::SigSpec(module->wires[remap_name(conn.first.chunks()[0].wire->name)]); + conn.first = RTLIL::SigSpec(module->wires[remap_name(conn.first.as_wire()->name)]); if (!conn.second.is_fully_const()) - conn.second = RTLIL::SigSpec(module->wires[remap_name(conn.second.chunks()[0].wire->name)]); + conn.second = RTLIL::SigSpec(module->wires[remap_name(conn.second.as_wire()->name)]); module->connections.push_back(conn); } diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index 6b37b7bb1..0a1d584ca 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -177,7 +177,7 @@ struct ShowWorker } if (sig.chunks().size() == 1) { - const RTLIL::SigChunk &c = sig.chunks()[0]; + const RTLIL::SigChunk &c = sig.chunks().front(); if (c.wire != NULL && design->selected_member(module->name, c.wire->name)) { if (!range_check || c.wire->width == c.width) return stringf("n%d", id2num(c.wire->name)); @@ -200,7 +200,7 @@ struct ShowWorker int pos = sig.size()-1; int idx = single_idx_count++; for (int i = int(sig.chunks().size())-1; i >= 0; i--) { - const RTLIL::SigChunk &c = sig.chunks()[i]; + const RTLIL::SigChunk &c = sig.chunks().at(i); net = gen_signode_simple(c, false); assert(!net.empty()); if (driver) { diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc index fec0b407d..3ceb5da36 100644 --- a/passes/memory/memory_collect.cc +++ b/passes/memory/memory_collect.cc @@ -147,8 +147,8 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) assert(sig_wr_en.size() == wr_ports * memory->width); mem->parameters["\\WR_PORTS"] = RTLIL::Const(wr_ports); - mem->parameters["\\WR_CLK_ENABLE"] = wr_ports ? sig_wr_clk_enable.chunks()[0].data : RTLIL::Const(0, 0); - mem->parameters["\\WR_CLK_POLARITY"] = wr_ports ? sig_wr_clk_polarity.chunks()[0].data : RTLIL::Const(0, 0); + mem->parameters["\\WR_CLK_ENABLE"] = wr_ports ? sig_wr_clk_enable.as_const() : RTLIL::Const(0, 0); + mem->parameters["\\WR_CLK_POLARITY"] = wr_ports ? sig_wr_clk_polarity.as_const() : RTLIL::Const(0, 0); mem->connections["\\WR_CLK"] = sig_wr_clk; mem->connections["\\WR_ADDR"] = sig_wr_addr; @@ -162,9 +162,9 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) assert(sig_rd_data.size() == rd_ports * memory->width); mem->parameters["\\RD_PORTS"] = RTLIL::Const(rd_ports); - mem->parameters["\\RD_CLK_ENABLE"] = rd_ports ? sig_rd_clk_enable.chunks()[0].data : RTLIL::Const(0, 0); - mem->parameters["\\RD_CLK_POLARITY"] = rd_ports ? sig_rd_clk_polarity.chunks()[0].data : RTLIL::Const(0, 0); - mem->parameters["\\RD_TRANSPARENT"] = rd_ports ? sig_rd_transparent.chunks()[0].data : RTLIL::Const(0, 0); + mem->parameters["\\RD_CLK_ENABLE"] = rd_ports ? sig_rd_clk_enable.as_const() : RTLIL::Const(0, 0); + mem->parameters["\\RD_CLK_POLARITY"] = rd_ports ? sig_rd_clk_polarity.as_const() : RTLIL::Const(0, 0); + mem->parameters["\\RD_TRANSPARENT"] = rd_ports ? sig_rd_transparent.as_const() : RTLIL::Const(0, 0); mem->connections["\\RD_CLK"] = sig_rd_clk; mem->connections["\\RD_ADDR"] = sig_rd_addr; diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index ba0aadc6b..02efabf72 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -104,15 +104,10 @@ static int count_nontrivial_wire_attrs(RTLIL::Wire *w) return count; } -static bool compare_signals(RTLIL::SigSpec &s1, RTLIL::SigSpec &s2, SigPool ®s, SigPool &conns, std::set &direct_wires) +static bool compare_signals(RTLIL::SigBit &s1, RTLIL::SigBit &s2, SigPool ®s, SigPool &conns, std::set &direct_wires) { - assert(s1.size() == 1); - assert(s2.size() == 1); - assert(s1.chunks().size() == 1); - assert(s2.chunks().size() == 1); - - RTLIL::Wire *w1 = s1.chunks()[0].wire; - RTLIL::Wire *w2 = s2.chunks()[0].wire; + RTLIL::Wire *w1 = s1.wire; + RTLIL::Wire *w2 = s2.wire; if (w1 == NULL || w2 == NULL) return w2 == NULL; @@ -189,7 +184,7 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool for (auto &it : module->wires) { RTLIL::Wire *wire = it.second; for (int i = 0; i < wire->width; i++) { - RTLIL::SigSpec s1 = RTLIL::SigSpec(wire, i), s2 = assign_map(s1); + RTLIL::SigBit s1 = RTLIL::SigBit(wire, i), s2 = assign_map(s1); if (!compare_signals(s1, s2, register_signals, connected_signals, direct_wires)) assign_map.add(s1); } diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index a8aba903a..5982fd8e4 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -382,7 +382,7 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) sync_edge->signal, sync_level->signal, proc); } else - gen_dff(mod, insig, rstval.chunks()[0].data, sig, + gen_dff(mod, insig, rstval.as_const(), sig, sync_edge->type == RTLIL::SyncType::STp, sync_level && sync_level->type == RTLIL::SyncType::ST1, sync_edge->signal, sync_level ? &sync_level->signal : NULL, proc); diff --git a/passes/proc/proc_init.cc b/passes/proc/proc_init.cc index 4c9b6bcd2..5976c2162 100644 --- a/passes/proc/proc_init.cc +++ b/passes/proc/proc_init.cc @@ -58,16 +58,15 @@ static void proc_init(RTLIL::Module *mod, RTLIL::Process *proc) log_cmd_error("Failed to get a constant init value for %s: %s\n", log_signal(lhs), log_signal(rhs)); int offset = 0; - for (size_t i = 0; i < lhs.chunks().size(); i++) { - if (lhs.chunks()[i].wire == NULL) - continue; - RTLIL::Wire *wire = lhs.chunks()[i].wire; - RTLIL::SigSpec value = rhs.extract(offset, lhs.chunks()[i].width); - if (value.size() != wire->width) - log_cmd_error("Init value is not for the entire wire: %s = %s\n", log_signal(lhs.chunks()[i]), log_signal(value)); - log(" Setting init value: %s = %s\n", log_signal(wire), log_signal(value)); - wire->attributes["\\init"] = value.as_const(); - offset += wire->width; + for (auto &lhs_c : lhs.chunks()) { + if (lhs_c.wire != NULL) { + RTLIL::SigSpec value = rhs.extract(offset, lhs_c.width); + if (value.size() != lhs_c.wire->width) + log_cmd_error("Init value is not for the entire wire: %s = %s\n", log_signal(lhs_c), log_signal(value)); + log(" Setting init value: %s = %s\n", log_signal(lhs_c.wire), log_signal(value)); + lhs_c.wire->attributes["\\init"] = value.as_const(); + } + offset += lhs_c.width; } } } -- cgit v1.2.3 From 91bf0c90c86f5f857f440bec012b085d9f218ef0 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 25 Jul 2014 12:04:40 +0200 Subject: Improvements in "cover" command --- passes/cmds/cover.cc | 48 +++++++++++++++++++++++++++++++++++++----------- 1 file changed, 37 insertions(+), 11 deletions(-) (limited to 'passes') diff --git a/passes/cmds/cover.cc b/passes/cmds/cover.cc index ebbdc7c4c..0a96c0b23 100644 --- a/passes/cmds/cover.cc +++ b/passes/cmds/cover.cc @@ -17,6 +17,10 @@ * */ +#include +#include +#include + #include "kernel/register.h" #include "kernel/rtlil.h" #include "kernel/log.h" @@ -27,7 +31,7 @@ struct CoverPass : public Pass { { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); - log(" cover [-q] [-o logfile|-a logfile]\n"); + log(" cover [options] [pattern]\n"); log("\n"); log("Print the code coverage counters collected using the cover() macro in the Yosys\n"); log("C++ code. This is useful to figure out what parts of Yosys are utilized by a\n"); @@ -36,22 +40,28 @@ struct CoverPass : public Pass { log(" -q\n"); log(" Do not print output to the normal destination (console and/or log file)\n"); log("\n"); - log(" -o logfile\n"); + log(" -o file\n"); log(" Write output to this file, truncate if exists.\n"); log("\n"); - log(" -a logfile\n"); + log(" -a file\n"); log(" Write output to this file, append if exists.\n"); log("\n"); + log(" -d dir\n"); + log(" Write output to a newly created file in the specified directory.\n"); + log("\n"); + log("When one or more pattern (shell wildcards) are specified, then only counters\n"); + log("matching at least one pattern are printed.\n"); + log("\n"); log("\n"); - log("It is also possible to instruct Yosys to print the coverage counters to a file\n"); - log("using environment variables.\n"); + log("It is also possible to instruct Yosys to print the coverage counters on program\n"); + log("exit to a file using environment variables:\n"); log("\n"); - log(" YOSYS_COVER_DIR=\"{dir-name}\" yosys {args}n"); + log(" YOSYS_COVER_DIR=\"{dir-name}\" yosys {args}\n"); log("\n"); log(" This will create a file (with an auto-generated name) in this\n"); - log(" directory and wire the coverage counters to it.\n"); + log(" directory and write the coverage counters to it.\n"); log("\n"); - log(" YOSYS_COVER_FILE=\"{file-name}\" yosys {args}n"); + log(" YOSYS_COVER_FILE=\"{file-name}\" yosys {args}\n"); log("\n"); log(" This will append the coverage counters to the specified file.\n"); log("\n"); @@ -65,6 +75,7 @@ struct CoverPass : public Pass { virtual void execute(std::vector args, RTLIL::Design *design) { std::vector out_files; + std::vector patterns; bool do_log = true; size_t argidx; @@ -74,9 +85,15 @@ struct CoverPass : public Pass { do_log = false; continue; } - if ((args[argidx] == "-o" || args[argidx] == "-a") && argidx+1 < args.size()) { - const char *open_mode = args[argidx] == "-o" ? "w" : "a+"; - FILE *f = fopen(args[++argidx].c_str(), open_mode); + if ((args[argidx] == "-o" || args[argidx] == "-a" || args[argidx] == "-d") && argidx+1 < args.size()) { + const char *open_mode = args[argidx] == "-a" ? "a+" : "w"; + std::string filename = args[++argidx]; + if (args[argidx-1] == "-d") { + char filename_buffer[4096]; + snprintf(filename_buffer, 4096, "%s/yosys_cover_%d_XXXXXX.txt", filename.c_str(), getpid()); + filename = mkstemps(filename_buffer, 4); + } + FILE *f = fopen(filename.c_str(), open_mode); if (f == NULL) { for (auto f : out_files) fclose(f); @@ -87,6 +104,8 @@ struct CoverPass : public Pass { } break; } + while (argidx < args.size() && args[argidx].substr(0, 1) != "-") + patterns.push_back(args[argidx++]); extra_args(args, argidx, design); if (do_log) { @@ -96,6 +115,13 @@ struct CoverPass : public Pass { #ifndef NDEBUG for (auto &it : get_coverage_data()) { + if (!patterns.empty()) { + for (auto &p : patterns) + if (!fnmatch(p.c_str(), it.first.c_str(), 0)) + goto pattern_match; + continue; + } + pattern_match: for (auto f : out_files) fprintf(f, "%-60s %10d %s\n", it.second.first.c_str(), it.second.second, it.first.c_str()); if (do_log) -- cgit v1.2.3 From c4e4f79a2a2fd5530fa2677245f9361c7b04df70 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 25 Jul 2014 12:22:37 +0200 Subject: Disabled cover() for non-linux builds --- passes/cmds/cover.cc | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'passes') diff --git a/passes/cmds/cover.cc b/passes/cmds/cover.cc index 0a96c0b23..ac72ba53a 100644 --- a/passes/cmds/cover.cc +++ b/passes/cmds/cover.cc @@ -71,6 +71,9 @@ struct CoverPass : public Pass { log(" gawk '{ p[$3] = $1; c[$3] += $2; } END { for (i in p)\n"); log(" printf \"%%-60s %%10d %%s\\n\", p[i], c[i], i; }' {files} | sort -k3\n"); log("\n"); + log("\n"); + log("Coverage counters are only available in debug builds of Yosys for Linux.\n"); + log("\n"); } virtual void execute(std::vector args, RTLIL::Design *design) { @@ -113,7 +116,7 @@ struct CoverPass : public Pass { log("\n"); } -#ifndef NDEBUG +#ifdef COVER_ACTIVE for (auto &it : get_coverage_data()) { if (!patterns.empty()) { for (auto &p : patterns) @@ -131,7 +134,7 @@ struct CoverPass : public Pass { for (auto f : out_files) fclose(f); - log_cmd_error("Coverage counters are only available in debug builds of Yosys."); + log_cmd_error("Coverage counters are only available in debug builds of Yosys for Linux.\n"); #endif for (auto f : out_files) -- cgit v1.2.3 From 0520bfea892291a131134411d587034fcd36bf1c Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 25 Jul 2014 12:49:51 +0200 Subject: Fixed memory corruption in "opt_reduce" pass --- passes/opt/opt_reduce.cc | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) (limited to 'passes') diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc index 913855f48..0cc16ee67 100644 --- a/passes/opt/opt_reduce.cc +++ b/passes/opt/opt_reduce.cc @@ -312,12 +312,14 @@ struct OptReduceWorker // merge identical inputs on $mux and $pmux cells - for (auto &cell_it : module->cells) - { - RTLIL::Cell *cell = cell_it.second; - if ((cell->type != "$mux" && cell->type != "$pmux" && cell->type != "$safe_pmux") || !design->selected(module, cell)) - continue; + std::vector cells; + for (auto &it : module->cells) + if ((it.second->type == "$mux" || it.second->type == "$pmux" || it.second->type == "$safe_pmux") && design->selected(module, it.second)) + cells.push_back(it.second); + + for (auto cell : cells) + { // this optimization is to aggressive for most coarse-grain applications. // but we always want it for multiplexers driving write enable ports. if (do_fine || mem_wren_sigs.check_any(assign_map(cell->connections.at("\\Y")))) -- cgit v1.2.3 From 5826670009e1018734de49aaf1554cb8a43d09d7 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 25 Jul 2014 14:23:31 +0200 Subject: Various RTLIL::SigSpec related code cleanups --- passes/cmds/show.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'passes') diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index 0a1d584ca..8ff068999 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -171,13 +171,13 @@ struct ShowWorker std::string gen_signode_simple(RTLIL::SigSpec sig, bool range_check = true) { - if (sig.chunks().size() == 0) { + if (SIZE(sig) == 0) { fprintf(f, "v%d [ label=\"\" ];\n", single_idx_count); return stringf("v%d", single_idx_count++); } - if (sig.chunks().size() == 1) { - const RTLIL::SigChunk &c = sig.chunks().front(); + if (sig.is_chunk()) { + const RTLIL::SigChunk &c = sig.as_chunk(); if (c.wire != NULL && design->selected_member(module->name, c.wire->name)) { if (!range_check || c.wire->width == c.width) return stringf("n%d", id2num(c.wire->name)); -- cgit v1.2.3 From 2bec47a4045d23d46e7d300cbf80b2dce1a549a9 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 25 Jul 2014 15:05:18 +0200 Subject: Use only module->addCell() and module->remove() to create and delete cells --- passes/abc/abc.cc | 42 ++++++----------------- passes/abc/blifparse.cc | 24 ++++--------- passes/cmds/delete.cc | 9 +++-- passes/cmds/splice.cc | 10 ++---- passes/fsm/fsm_expand.cc | 6 ++-- passes/fsm/fsm_extract.cc | 5 +-- passes/fsm/fsm_map.cc | 68 +++++++++--------------------------- passes/hierarchy/submod.cc | 14 ++++---- passes/memory/memory_collect.cc | 18 ++++------ passes/memory/memory_map.cc | 42 +++++------------------ passes/memory/memory_share.cc | 6 ++-- passes/memory/memory_unpack.cc | 13 ++----- passes/opt/opt_clean.cc | 3 +- passes/opt/opt_const.cc | 3 +- passes/opt/opt_muxtree.cc | 6 ++-- passes/opt/opt_reduce.cc | 13 ++----- passes/opt/opt_rmdff.cc | 3 +- passes/opt/opt_share.cc | 3 +- passes/proc/proc_dff.cc | 65 +++++++---------------------------- passes/proc/proc_mux.cc | 17 ++------- passes/sat/expose.cc | 21 ++++-------- passes/sat/freduce.cc | 5 +-- passes/sat/miter.cc | 51 ++++++--------------------- passes/sat/share.cc | 8 ++--- passes/techmap/dfflibmap.cc | 35 ++++++++----------- passes/techmap/extract.cc | 13 ++----- passes/techmap/hilomap.cc | 10 ++---- passes/techmap/iopadmap.cc | 10 ++---- passes/techmap/simplemap.cc | 76 +++++++++-------------------------------- passes/techmap/techmap.cc | 37 +++++++++++--------- 30 files changed, 171 insertions(+), 465 deletions(-) (limited to 'passes') diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index d25f88c0d..980e69aa2 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -127,8 +127,7 @@ static void extract_cell(RTLIL::Cell *cell, bool keepff) map_signal(sig_q, 'f', map_signal(sig_d)); - module->cells.erase(cell->name); - delete cell; + module->remove(cell); return; } @@ -142,8 +141,7 @@ static void extract_cell(RTLIL::Cell *cell, bool keepff) map_signal(sig_y, 'n', map_signal(sig_a)); - module->cells.erase(cell->name); - delete cell; + module->remove(cell); return; } @@ -169,8 +167,7 @@ static void extract_cell(RTLIL::Cell *cell, bool keepff) else log_abort(); - module->cells.erase(cell->name); - delete cell; + module->remove(cell); return; } @@ -192,8 +189,7 @@ static void extract_cell(RTLIL::Cell *cell, bool keepff) map_signal(sig_y, 'm', mapped_a, mapped_b, mapped_s); - module->cells.erase(cell->name); - delete cell; + module->remove(cell); return; } } @@ -722,47 +718,35 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std continue; } if (c->type == "\\INV") { - RTLIL::Cell *cell = new RTLIL::Cell; - cell->type = "$_INV_"; - cell->name = remap_name(c->name); + RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_INV_"); cell->connections["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].as_wire()->name)]); cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].as_wire()->name)]); - module->cells[cell->name] = cell; design->select(module, cell); continue; } if (c->type == "\\AND" || c->type == "\\OR" || c->type == "\\XOR") { - RTLIL::Cell *cell = new RTLIL::Cell; - cell->type = "$_" + c->type.substr(1) + "_"; - cell->name = remap_name(c->name); + RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_" + c->type.substr(1) + "_"); cell->connections["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].as_wire()->name)]); cell->connections["\\B"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\B"].as_wire()->name)]); cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].as_wire()->name)]); - module->cells[cell->name] = cell; design->select(module, cell); continue; } if (c->type == "\\MUX") { - RTLIL::Cell *cell = new RTLIL::Cell; - cell->type = "$_MUX_"; - cell->name = remap_name(c->name); + RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_MUX_"); cell->connections["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].as_wire()->name)]); cell->connections["\\B"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\B"].as_wire()->name)]); cell->connections["\\S"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\S"].as_wire()->name)]); cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].as_wire()->name)]); - module->cells[cell->name] = cell; design->select(module, cell); continue; } if (c->type == "\\DFF") { log_assert(clk_sig.size() == 1); - RTLIL::Cell *cell = new RTLIL::Cell; - cell->type = clk_polarity ? "$_DFF_P_" : "$_DFF_N_"; - cell->name = remap_name(c->name); + RTLIL::Cell *cell = module->addCell(remap_name(c->name), clk_polarity ? "$_DFF_P_" : "$_DFF_N_"); cell->connections["\\D"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\D"].as_wire()->name)]); cell->connections["\\Q"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Q"].as_wire()->name)]); cell->connections["\\C"] = clk_sig; - module->cells[cell->name] = cell; design->select(module, cell); continue; } @@ -784,20 +768,15 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std } if (c->type == "\\_dff_") { log_assert(clk_sig.size() == 1); - RTLIL::Cell *cell = new RTLIL::Cell; - cell->type = clk_polarity ? "$_DFF_P_" : "$_DFF_N_"; - cell->name = remap_name(c->name); + RTLIL::Cell *cell = module->addCell(remap_name(c->name), clk_polarity ? "$_DFF_P_" : "$_DFF_N_"); cell->connections["\\D"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\D"].as_wire()->name)]); cell->connections["\\Q"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Q"].as_wire()->name)]); cell->connections["\\C"] = clk_sig; - module->cells[cell->name] = cell; design->select(module, cell); continue; } - RTLIL::Cell *cell = new RTLIL::Cell; - cell->type = c->type; + RTLIL::Cell *cell = module->addCell(remap_name(c->name), c->type); cell->parameters = c->parameters; - cell->name = remap_name(c->name); for (auto &conn : c->connections) { RTLIL::SigSpec newsig; for (auto &c : conn.second.chunks()) { @@ -808,7 +787,6 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std } cell->connections[conn.first] = newsig; } - module->cells[cell->name] = cell; design->select(module, cell); } } diff --git a/passes/abc/blifparse.cc b/passes/abc/blifparse.cc index 04977b369..e7feb1877 100644 --- a/passes/abc/blifparse.cc +++ b/passes/abc/blifparse.cc @@ -127,36 +127,27 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name) module->add(wire); } - RTLIL::Cell *cell = new RTLIL::Cell; - cell->name = NEW_ID; - cell->type = dff_name; + RTLIL::Cell *cell = module->addCell(NEW_ID, dff_name); cell->connections["\\D"] = module->wires.at(RTLIL::escape_id(d)); cell->connections["\\Q"] = module->wires.at(RTLIL::escape_id(q)); - module->add(cell); continue; } if (!strcmp(cmd, ".gate")) { - RTLIL::Cell *cell = new RTLIL::Cell; - cell->name = NEW_ID; - module->add(cell); - char *p = strtok(NULL, " \t\r\n"); if (p == NULL) goto error; - cell->type = RTLIL::escape_id(p); + + RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(p)); while ((p = strtok(NULL, " \t\r\n")) != NULL) { char *q = strchr(p, '='); if (q == NULL || !q[0] || !q[1]) goto error; *(q++) = 0; - if (module->wires.count(RTLIL::escape_id(q)) == 0) { - RTLIL::Wire *wire = new RTLIL::Wire; - wire->name = RTLIL::escape_id(q); - module->add(wire); - } + if (module->wires.count(RTLIL::escape_id(q)) == 0) + module->addWire(RTLIL::escape_id(q)); cell->connections[RTLIL::escape_id(p)] = module->wires.at(RTLIL::escape_id(q)); } continue; @@ -212,16 +203,13 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name) goto continue_without_read; } - RTLIL::Cell *cell = new RTLIL::Cell; - cell->name = NEW_ID; - cell->type = "$lut"; + RTLIL::Cell *cell = module->addCell(NEW_ID, "$lut"); cell->parameters["\\WIDTH"] = RTLIL::Const(input_sig.size()); cell->parameters["\\LUT"] = RTLIL::Const(RTLIL::State::Sx, 1 << input_sig.size()); cell->connections["\\I"] = input_sig; cell->connections["\\O"] = output_sig; lutptr = &cell->parameters.at("\\LUT"); lut_default_state = RTLIL::State::Sx; - module->add(cell); continue; } diff --git a/passes/cmds/delete.cc b/passes/cmds/delete.cc index 7fe95b0a9..79b7c3c30 100644 --- a/passes/cmds/delete.cc +++ b/passes/cmds/delete.cc @@ -107,7 +107,7 @@ struct DeletePass : public Pass { } std::set delete_wires; - std::set delete_cells; + std::set delete_cells; std::set delete_procs; std::set delete_mems; @@ -121,10 +121,10 @@ struct DeletePass : public Pass { for (auto &it : module->cells) { if (design->selected(module, it.second)) - delete_cells.insert(it.first); + delete_cells.insert(it.second); if ((it.second->type == "$memrd" || it.second->type == "$memwr") && delete_mems.count(it.second->parameters.at("\\MEMID").decode_string()) != 0) - delete_cells.insert(it.first); + delete_cells.insert(it.second); } for (auto &it : module->processes) @@ -147,8 +147,7 @@ struct DeletePass : public Pass { } for (auto &it : delete_cells) { - delete module->cells.at(it); - module->cells.erase(it); + module->remove(it); } for (auto &it : delete_procs) { diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc index 68e8951ff..a470aed00 100644 --- a/passes/cmds/splice.cc +++ b/passes/cmds/splice.cc @@ -70,16 +70,13 @@ struct SpliceWorker RTLIL::SigSpec new_sig = sig; if (sig_a.size() != sig.size()) { - RTLIL::Cell *cell = new RTLIL::Cell; - cell->name = NEW_ID; - cell->type = "$slice"; + RTLIL::Cell *cell = module->addCell(NEW_ID, "$slice"); cell->parameters["\\OFFSET"] = offset; cell->parameters["\\A_WIDTH"] = sig_a.size(); cell->parameters["\\Y_WIDTH"] = sig.size(); cell->connections["\\A"] = sig_a; cell->connections["\\Y"] = module->addWire(NEW_ID, sig.size()); new_sig = cell->connections["\\Y"]; - module->add(cell); } sliced_signals_cache[sig] = new_sig; @@ -130,16 +127,13 @@ struct SpliceWorker RTLIL::SigSpec new_sig = get_sliced_signal(chunks.front()); for (size_t i = 1; i < chunks.size(); i++) { RTLIL::SigSpec sig2 = get_sliced_signal(chunks[i]); - RTLIL::Cell *cell = new RTLIL::Cell; - cell->name = NEW_ID; - cell->type = "$concat"; + RTLIL::Cell *cell = module->addCell(NEW_ID, "$concat"); cell->parameters["\\A_WIDTH"] = new_sig.size(); cell->parameters["\\B_WIDTH"] = sig2.size(); cell->connections["\\A"] = new_sig; cell->connections["\\B"] = sig2; cell->connections["\\Y"] = module->addWire(NEW_ID, new_sig.size() + sig2.size()); new_sig = cell->connections["\\Y"]; - module->add(cell); } spliced_signals_cache[sig] = new_sig; diff --git a/passes/fsm/fsm_expand.cc b/passes/fsm/fsm_expand.cc index 0dd328db3..f3b6c998d 100644 --- a/passes/fsm/fsm_expand.cc +++ b/passes/fsm/fsm_expand.cc @@ -226,10 +226,8 @@ struct FsmExpand merge_cell_into_fsm(c); } - for (auto c : merged_set) { - module->cells.erase(c->name); - delete c; - } + for (auto c : merged_set) + module->remove(c); if (merged_set.size() > 0 && !already_optimized) FsmData::optimize_fsm(fsm_cell, module); diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index dfd025a51..1b5ea1bc0 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -270,9 +270,7 @@ static void extract_fsm(RTLIL::Wire *wire) // create fsm cell - RTLIL::Cell *fsm_cell = new RTLIL::Cell; - fsm_cell->name = stringf("$fsm$%s$%d", wire->name.c_str(), RTLIL::autoidx++); - fsm_cell->type = "$fsm"; + RTLIL::Cell *fsm_cell = module->addCell(stringf("$fsm$%s$%d", wire->name.c_str(), RTLIL::autoidx++), "$fsm"); fsm_cell->connections["\\CLK"] = clk; fsm_cell->connections["\\ARST"] = arst; fsm_cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity ? 1 : 0, 1); @@ -282,7 +280,6 @@ static void extract_fsm(RTLIL::Wire *wire) fsm_cell->parameters["\\NAME"] = RTLIL::Const(wire->name); fsm_cell->attributes = wire->attributes; fsm_data.copy_to_cell(fsm_cell); - module->cells[fsm_cell->name] = fsm_cell; // rename original state wire diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc index cee267629..78248eb6d 100644 --- a/passes/fsm/fsm_map.cc +++ b/passes/fsm/fsm_map.cc @@ -54,13 +54,10 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map 0) { - RTLIL::Wire *eq_wire = new RTLIL::Wire; - eq_wire->name = NEW_ID; - module->add(eq_wire); + RTLIL::Wire *eq_wire = module->addWire(NEW_ID); + and_sig.append(RTLIL::SigSpec(eq_wire)); - RTLIL::Cell *eq_cell = new RTLIL::Cell; - eq_cell->name = NEW_ID; - eq_cell->type = "$eq"; + RTLIL::Cell *eq_cell = module->addCell(NEW_ID, "$eq"); eq_cell->connections["\\A"] = eq_sig_a; eq_cell->connections["\\B"] = eq_sig_b; eq_cell->connections["\\Y"] = RTLIL::SigSpec(eq_wire); @@ -69,9 +66,6 @@ static void implement_pattern_cache(RTLIL::Module *module, std::mapparameters["\\A_WIDTH"] = RTLIL::Const(eq_sig_a.size()); eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(eq_sig_b.size()); eq_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - module->add(eq_cell); - - and_sig.append(RTLIL::SigSpec(eq_wire)); } if (or_sig.size() < num_states-int(fullstate_cache.size())) @@ -82,21 +76,15 @@ static void implement_pattern_cache(RTLIL::Module *module, std::mapname = NEW_ID; - module->add(or_wire); + RTLIL::Wire *or_wire = module->addWire(NEW_ID); + and_sig.append(RTLIL::SigSpec(or_wire)); - RTLIL::Cell *or_cell = new RTLIL::Cell; - or_cell->name = NEW_ID; - or_cell->type = "$reduce_or"; + RTLIL::Cell *or_cell = module->addCell(NEW_ID, "$reduce_or"); or_cell->connections["\\A"] = or_sig; or_cell->connections["\\Y"] = RTLIL::SigSpec(or_wire); or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false); or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(or_sig.size()); or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - module->add(or_cell); - - and_sig.append(RTLIL::SigSpec(or_wire)); } } @@ -104,13 +92,10 @@ static void implement_pattern_cache(RTLIL::Module *module, std::mapname = NEW_ID; - module->add(and_wire); + RTLIL::Wire *and_wire = module->addWire(NEW_ID); + cases_vector.append(RTLIL::SigSpec(and_wire)); - RTLIL::Cell *and_cell = new RTLIL::Cell; - and_cell->name = NEW_ID; - and_cell->type = "$and"; + RTLIL::Cell *and_cell = module->addCell(NEW_ID, "$and"); and_cell->connections["\\A"] = and_sig.extract(0, 1); and_cell->connections["\\B"] = and_sig.extract(1, 1); and_cell->connections["\\Y"] = RTLIL::SigSpec(and_wire); @@ -119,9 +104,6 @@ static void implement_pattern_cache(RTLIL::Module *module, std::mapparameters["\\A_WIDTH"] = RTLIL::Const(1); and_cell->parameters["\\B_WIDTH"] = RTLIL::Const(1); and_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - module->add(and_cell); - - cases_vector.append(RTLIL::SigSpec(and_wire)); break; } case 1: @@ -136,15 +118,12 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map 1) { - RTLIL::Cell *or_cell = new RTLIL::Cell; - or_cell->name = NEW_ID; - or_cell->type = "$reduce_or"; + RTLIL::Cell *or_cell = module->addCell(NEW_ID, "$reduce_or"); or_cell->connections["\\A"] = cases_vector; or_cell->connections["\\Y"] = output; or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false); or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cases_vector.size()); or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - module->add(or_cell); } else if (cases_vector.size() == 1) { module->connections.push_back(RTLIL::SigSig(output, cases_vector)); } else { @@ -171,13 +150,9 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) state_wire->width = fsm_data.state_bits; module->add(state_wire); - RTLIL::Wire *next_state_wire = new RTLIL::Wire; - next_state_wire->name = NEW_ID; - next_state_wire->width = fsm_data.state_bits; - module->add(next_state_wire); + RTLIL::Wire *next_state_wire = module->addWire(NEW_ID, fsm_data.state_bits); - RTLIL::Cell *state_dff = new RTLIL::Cell; - state_dff->name = NEW_ID; + RTLIL::Cell *state_dff = module->addCell(NEW_ID, ""); if (fsm_cell->connections["\\ARST"].is_fully_const()) { state_dff->type = "$dff"; } else { @@ -194,16 +169,12 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) state_dff->connections["\\CLK"] = fsm_cell->connections["\\CLK"]; state_dff->connections["\\D"] = RTLIL::SigSpec(next_state_wire); state_dff->connections["\\Q"] = RTLIL::SigSpec(state_wire); - module->add(state_dff); // decode state register bool encoding_is_onehot = true; - RTLIL::Wire *state_onehot = new RTLIL::Wire; - state_onehot->name = NEW_ID; - state_onehot->width = fsm_data.state_table.size(); - module->add(state_onehot); + RTLIL::Wire *state_onehot = module->addWire(NEW_ID, fsm_data.state_table.size()); for (size_t i = 0; i < fsm_data.state_table.size(); i++) { @@ -224,9 +195,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) { encoding_is_onehot = false; - RTLIL::Cell *eq_cell = new RTLIL::Cell; - eq_cell->name = NEW_ID; - eq_cell->type = "$eq"; + RTLIL::Cell *eq_cell = module->addCell(NEW_ID, "$eq"); eq_cell->connections["\\A"] = sig_a; eq_cell->connections["\\B"] = sig_b; eq_cell->connections["\\Y"] = RTLIL::SigSpec(state_onehot, i); @@ -235,7 +204,6 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_a.size()); eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(sig_b.size()); eq_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - module->add(eq_cell); } } @@ -296,16 +264,13 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) } } - RTLIL::Cell *mux_cell = new RTLIL::Cell; - mux_cell->name = NEW_ID; - mux_cell->type = "$safe_pmux"; + RTLIL::Cell *mux_cell = module->addCell(NEW_ID, "$safe_pmux"); mux_cell->connections["\\A"] = sig_a; mux_cell->connections["\\B"] = sig_b; mux_cell->connections["\\S"] = sig_s; mux_cell->connections["\\Y"] = RTLIL::SigSpec(next_state_wire); mux_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_a.size()); mux_cell->parameters["\\S_WIDTH"] = RTLIL::Const(sig_s.size()); - module->add(mux_cell); } // Generate ctrl_out signal @@ -335,8 +300,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) // Remove FSM cell - module->cells.erase(fsm_cell->name); - delete fsm_cell; + module->remove(fsm_cell); } struct FsmMapPass : public Pass { diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index 257301880..204f899a0 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -162,7 +162,10 @@ struct SubmodWorker } for (RTLIL::Cell *cell : submod.cells) { - RTLIL::Cell *new_cell = new RTLIL::Cell(*cell); + RTLIL::Cell *new_cell = new_mod->addCell(cell->name, cell->type); + new_cell->connections = cell->connections; + new_cell->parameters = cell->parameters; + new_cell->attributes = cell->attributes; for (auto &conn : new_cell->connections) for (auto &bit : conn.second) if (bit.wire != NULL) { @@ -170,15 +173,11 @@ struct SubmodWorker bit.wire = wire_flags[bit.wire].new_wire; } log(" cell %s (%s)\n", new_cell->name.c_str(), new_cell->type.c_str()); - new_mod->cells[new_cell->name] = new_cell; - module->cells.erase(cell->name); - delete cell; + module->remove(cell); } submod.cells.clear(); - RTLIL::Cell *new_cell = new RTLIL::Cell; - new_cell->name = submod.full_name; - new_cell->type = submod.full_name; + RTLIL::Cell *new_cell = module->addCell(submod.full_name, submod.full_name); for (auto &it : wire_flags) { RTLIL::Wire *old_wire = it.first; @@ -186,7 +185,6 @@ struct SubmodWorker if (new_wire->port_id > 0) new_cell->connections[new_wire->name] = RTLIL::SigSpec(old_wire); } - module->cells[new_cell->name] = new_cell; } SubmodWorker(RTLIL::Design *design, RTLIL::Module *module, std::string opt_name = std::string()) : design(design), module(module), opt_name(opt_name) diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc index 3ceb5da36..116b704e3 100644 --- a/passes/memory/memory_collect.cc +++ b/passes/memory/memory_collect.cc @@ -58,7 +58,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) RTLIL::SigSpec sig_rd_addr; RTLIL::SigSpec sig_rd_data; - std::vector del_cell_ids; + std::vector del_cells; std::vector memcells; for (auto &cell_it : module->cells) { @@ -74,7 +74,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) if (cell->type == "$memwr" && cell->parameters["\\MEMID"].decode_string() == memory->name) { wr_ports++; - del_cell_ids.push_back(cell->name); + del_cells.push_back(cell); RTLIL::SigSpec clk = cell->connections["\\CLK"]; RTLIL::SigSpec clk_enable = RTLIL::SigSpec(cell->parameters["\\CLK_ENABLE"]); @@ -101,7 +101,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) if (cell->type == "$memrd" && cell->parameters["\\MEMID"].decode_string() == memory->name) { rd_ports++; - del_cell_ids.push_back(cell->name); + del_cells.push_back(cell); RTLIL::SigSpec clk = cell->connections["\\CLK"]; RTLIL::SigSpec clk_enable = RTLIL::SigSpec(cell->parameters["\\CLK_ENABLE"]); @@ -129,10 +129,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) std::stringstream sstr; sstr << "$mem$" << memory->name << "$" << (RTLIL::autoidx++); - RTLIL::Cell *mem = new RTLIL::Cell; - mem->name = sstr.str(); - mem->type = "$mem"; - + RTLIL::Cell *mem = module->addCell(sstr.str(), "$mem"); mem->parameters["\\MEMID"] = RTLIL::Const(memory->name); mem->parameters["\\WIDTH"] = RTLIL::Const(memory->width); mem->parameters["\\OFFSET"] = RTLIL::Const(memory->start_offset); @@ -170,11 +167,8 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) mem->connections["\\RD_ADDR"] = sig_rd_addr; mem->connections["\\RD_DATA"] = sig_rd_data; - for (auto &id : del_cell_ids) { - delete module->cells[id]; - module->cells.erase(id); - } - module->cells[mem->name] = mem; + for (auto c : del_cells) + module->remove(c); } static void handle_module(RTLIL::Design *design, RTLIL::Module *module) diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index e605e6e51..b5f0520a4 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -57,8 +57,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) // delete unused memory cell if (cell->parameters["\\RD_PORTS"].as_int() == 0 && cell->parameters["\\WR_PORTS"].as_int() == 0) { - module->cells.erase(cell->name); - delete cell; + module->remove(cell); return; } @@ -117,9 +116,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) } else { - RTLIL::Cell *c = new RTLIL::Cell; - c->name = genid(cell->name, "", i); - c->type = "$dff"; + RTLIL::Cell *c = module->addCell(genid(cell->name, "", i), "$dff"); c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"]; if (clocks_pol.bits.size() > 0) { c->parameters["\\CLK_POLARITY"] = RTLIL::Const(clocks_pol.bits[0]); @@ -128,7 +125,6 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) c->parameters["\\CLK_POLARITY"] = RTLIL::Const(RTLIL::State::S1); c->connections["\\CLK"] = RTLIL::SigSpec(RTLIL::State::S0); } - module->cells[c->name] = c; RTLIL::Wire *w_in = new RTLIL::Wire; w_in->name = genid(cell->name, "", i, "$d"); @@ -164,14 +160,11 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) { if (cell->parameters["\\RD_TRANSPARENT"].bits[i] == RTLIL::State::S1) { - RTLIL::Cell *c = new RTLIL::Cell; - c->name = genid(cell->name, "$rdreg", i); - c->type = "$dff"; + RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdreg", i), "$dff"); c->parameters["\\WIDTH"] = RTLIL::Const(mem_abits); c->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]); c->connections["\\CLK"] = cell->connections["\\RD_CLK"].extract(i, 1); c->connections["\\D"] = rd_addr; - module->cells[c->name] = c; count_dff++; RTLIL::Wire *w = new RTLIL::Wire; @@ -184,14 +177,11 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) } else { - RTLIL::Cell *c = new RTLIL::Cell; - c->name = genid(cell->name, "$rdreg", i); - c->type = "$dff"; + RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdreg", i), "$dff"); c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"]; c->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]); c->connections["\\CLK"] = cell->connections["\\RD_CLK"].extract(i, 1); c->connections["\\Q"] = rd_signals.back(); - module->cells[c->name] = c; count_dff++; RTLIL::Wire *w = new RTLIL::Wire; @@ -211,13 +201,10 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) for (size_t k = 0; k < rd_signals.size(); k++) { - RTLIL::Cell *c = new RTLIL::Cell; - c->name = genid(cell->name, "$rdmux", i, "", j, "", k); - c->type = "$mux"; + RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdmux", i, "", j, "", k), "$mux"); c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"]; c->connections["\\Y"] = rd_signals[k]; c->connections["\\S"] = rd_addr.extract(mem_abits-j-1, 1); - module->cells[c->name] = c; count_mux++; RTLIL::Wire *w = new RTLIL::Wire; @@ -258,9 +245,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::SigSpec wr_data = cell->connections["\\WR_DATA"].extract(j*mem_width, mem_width); RTLIL::SigSpec wr_en = cell->connections["\\WR_EN"].extract(j*mem_width, mem_width); - RTLIL::Cell *c = new RTLIL::Cell; - c->name = genid(cell->name, "$wreq", i, "", j); - c->type = "$eq"; + RTLIL::Cell *c = module->addCell(genid(cell->name, "$wreq", i, "", j), "$eq"); c->parameters["\\A_SIGNED"] = RTLIL::Const(0); c->parameters["\\B_SIGNED"] = RTLIL::Const(0); c->parameters["\\A_WIDTH"] = cell->parameters["\\ABITS"]; @@ -268,7 +253,6 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) c->parameters["\\Y_WIDTH"] = RTLIL::Const(1); c->connections["\\A"] = RTLIL::SigSpec(i, mem_abits); c->connections["\\B"] = wr_addr; - module->cells[c->name] = c; count_wrmux++; RTLIL::Wire *w_seladdr = new RTLIL::Wire; @@ -293,9 +277,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) if (wr_bit != RTLIL::SigSpec(1, 1)) { - c = new RTLIL::Cell; - c->name = genid(cell->name, "$wren", i, "", j, "", wr_offset); - c->type = "$and"; + c = module->addCell(genid(cell->name, "$wren", i, "", j, "", wr_offset), "$and"); c->parameters["\\A_SIGNED"] = RTLIL::Const(0); c->parameters["\\B_SIGNED"] = RTLIL::Const(0); c->parameters["\\A_WIDTH"] = RTLIL::Const(1); @@ -303,7 +285,6 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) c->parameters["\\Y_WIDTH"] = RTLIL::Const(1); c->connections["\\A"] = w; c->connections["\\B"] = wr_bit; - module->cells[c->name] = c; w = new RTLIL::Wire; w->name = genid(cell->name, "$wren", i, "", j, "", wr_offset, "$y"); @@ -311,14 +292,11 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) c->connections["\\Y"] = RTLIL::SigSpec(w); } - c = new RTLIL::Cell; - c->name = genid(cell->name, "$wrmux", i, "", j, "", wr_offset); - c->type = "$mux"; + c = module->addCell(genid(cell->name, "$wrmux", i, "", j, "", wr_offset), "$mux"); c->parameters["\\WIDTH"] = wr_width; c->connections["\\A"] = sig.extract(wr_offset, wr_width); c->connections["\\B"] = wr_data.extract(wr_offset, wr_width); c->connections["\\S"] = RTLIL::SigSpec(w); - module->cells[c->name] = c; w = new RTLIL::Wire; w->name = genid(cell->name, "$wrmux", i, "", j, "", wr_offset, "$y"); @@ -336,9 +314,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) log(" write interface: %d blocks of $eq, $and and $mux cells.\n", count_wrmux); - module->cells.erase(cell->name); - delete cell; - return; + module->remove(cell); } static void handle_module(RTLIL::Design *design, RTLIL::Module *module) diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index dd2a32cad..63f6b14f8 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -446,8 +446,7 @@ struct MemoryShareWorker cell->connections.at("\\EN") = merged_en; cell->connections.at("\\DATA") = merged_data; - module->cells.erase(wr_ports[last_i]->name); - delete wr_ports[last_i]; + module->remove(wr_ports[last_i]); wr_ports[last_i] = NULL; log(" Active bits: "); @@ -617,8 +616,7 @@ struct MemoryShareWorker module->addMux(NEW_ID, grouped_last_en, grouped_this_en, this_en_active, grouped_en); wr_ports[i]->connections.at("\\EN") = en; - module->cells.erase(wr_ports[i-1]->name); - delete wr_ports[i-1]; + module->remove(wr_ports[i-1]); wr_ports[i-1] = NULL; } diff --git a/passes/memory/memory_unpack.cc b/passes/memory/memory_unpack.cc index bbd015833..97cda1443 100644 --- a/passes/memory/memory_unpack.cc +++ b/passes/memory/memory_unpack.cc @@ -47,9 +47,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory) for (int i = 0; i < num_rd_ports; i++) { - RTLIL::Cell *cell = new RTLIL::Cell; - cell->name = NEW_ID; - cell->type = "$memrd"; + RTLIL::Cell *cell = module->addCell(NEW_ID, "$memrd"); cell->parameters["\\MEMID"] = mem_name; cell->parameters["\\ABITS"] = memory->parameters.at("\\ABITS"); cell->parameters["\\WIDTH"] = memory->parameters.at("\\WIDTH"); @@ -59,14 +57,11 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory) cell->connections["\\CLK"] = memory->connections.at("\\RD_CLK").extract(i, 1); cell->connections["\\ADDR"] = memory->connections.at("\\RD_ADDR").extract(i*abits, abits); cell->connections["\\DATA"] = memory->connections.at("\\RD_DATA").extract(i*mem->width, mem->width); - module->add(cell); } for (int i = 0; i < num_wr_ports; i++) { - RTLIL::Cell *cell = new RTLIL::Cell; - cell->name = NEW_ID; - cell->type = "$memwr"; + RTLIL::Cell *cell = module->addCell(NEW_ID, "$memwr"); cell->parameters["\\MEMID"] = mem_name; cell->parameters["\\ABITS"] = memory->parameters.at("\\ABITS"); cell->parameters["\\WIDTH"] = memory->parameters.at("\\WIDTH"); @@ -77,11 +72,9 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory) cell->connections["\\EN"] = memory->connections.at("\\WR_EN").extract(i*mem->width, mem->width); cell->connections["\\ADDR"] = memory->connections.at("\\WR_ADDR").extract(i*abits, abits); cell->connections["\\DATA"] = memory->connections.at("\\WR_DATA").extract(i*mem->width, mem->width); - module->add(cell); } - module->cells.erase(memory->name); - delete memory; + module->remove(memory); } static void handle_module(RTLIL::Design *design, RTLIL::Module *module) diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 02efabf72..00fa6031f 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -90,9 +90,8 @@ static void rmunused_module_cells(RTLIL::Module *module, bool verbose) if (verbose) log(" removing unused `%s' cell `%s'.\n", cell->type.c_str(), cell->name.c_str()); OPT_DID_SOMETHING = true; - module->cells.erase(cell->name); + module->remove(cell); count_rm_cells++; - delete cell; } } diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index e2bf7004f..e1b6c598f 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -81,8 +81,7 @@ static void replace_cell(RTLIL::Module *module, RTLIL::Cell *cell, std::string i module->name.c_str(), log_signal(Y), log_signal(out_val)); // ILANG_BACKEND::dump_cell(stderr, "--> ", cell); module->connections.push_back(RTLIL::SigSig(Y, out_val)); - module->cells.erase(cell->name); - delete cell; + module->remove(cell); OPT_DID_SOMETHING = true; did_something = true; } diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc index dfcd55126..750a9d417 100644 --- a/passes/opt/opt_muxtree.cc +++ b/passes/opt/opt_muxtree.cc @@ -190,8 +190,7 @@ struct OptMuxtreeWorker continue; if (live_ports.size() == 0) { - module->cells.erase(mi.cell->name); - delete mi.cell; + module->remove(mi.cell); continue; } @@ -207,8 +206,7 @@ struct OptMuxtreeWorker { RTLIL::SigSpec sig_in = sig_ports.extract(live_ports[0]*sig_a.size(), sig_a.size()); module->connections.push_back(RTLIL::SigSig(sig_y, sig_in)); - module->cells.erase(mi.cell->name); - delete mi.cell; + module->remove(mi.cell); } else { diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc index 0cc16ee67..073af3087 100644 --- a/passes/opt/opt_reduce.cc +++ b/passes/opt/opt_reduce.cc @@ -124,19 +124,13 @@ struct OptReduceWorker if (this_s.size() > 1) { - RTLIL::Wire *reduce_or_wire = new RTLIL::Wire; - reduce_or_wire->name = NEW_ID; - module->wires[reduce_or_wire->name] = reduce_or_wire; - - RTLIL::Cell *reduce_or_cell = new RTLIL::Cell; - reduce_or_cell->name = NEW_ID; - reduce_or_cell->type = "$reduce_or"; + RTLIL::Cell *reduce_or_cell = module->addCell(NEW_ID, "$reduce_or"); reduce_or_cell->connections["\\A"] = this_s; reduce_or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); reduce_or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(this_s.size()); reduce_or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - module->cells[reduce_or_cell->name] = reduce_or_cell; + RTLIL::Wire *reduce_or_wire = module->addWire(NEW_ID); this_s = RTLIL::SigSpec(reduce_or_wire); reduce_or_cell->connections["\\Y"] = this_s; } @@ -157,8 +151,7 @@ struct OptReduceWorker { module->connections.push_back(RTLIL::SigSig(cell->connections["\\Y"], cell->connections["\\A"])); assign_map.add(cell->connections["\\Y"], cell->connections["\\A"]); - module->cells.erase(cell->name); - delete cell; + module->remove(cell); } else { diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc index 4215a7b54..6a35cb618 100644 --- a/passes/opt/opt_rmdff.cc +++ b/passes/opt/opt_rmdff.cc @@ -143,8 +143,7 @@ static bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) delete_dff: log("Removing %s (%s) from module %s.\n", dff->name.c_str(), dff->type.c_str(), mod->name.c_str()); OPT_DID_SOMETHING = true; - mod->cells.erase(dff->name); - delete dff; + mod->remove(dff); return true; } diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc index 819a0e460..e3e9511fd 100644 --- a/passes/opt/opt_share.cc +++ b/passes/opt/opt_share.cc @@ -271,10 +271,9 @@ struct OptShareWorker } } log(" Removing %s cell `%s' from module `%s'.\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str()); - module->cells.erase(cell->name); + module->remove(cell); OPT_DID_SOMETHING = true; total_count++; - delete cell; } else { sharemap[cell] = cell; } diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index 5982fd8e4..876adb0db 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -73,79 +73,59 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S log_abort(); if (sync_low_signals.size() > 1) { - RTLIL::Cell *cell = new RTLIL::Cell; - cell->name = NEW_ID; - cell->type = "$reduce_or"; + RTLIL::Cell *cell = mod->addCell(NEW_ID, "$reduce_or"); cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.size()); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); cell->connections["\\A"] = sync_low_signals; cell->connections["\\Y"] = sync_low_signals = mod->addWire(NEW_ID); - mod->add(cell); } if (sync_low_signals.size() > 0) { - RTLIL::Cell *cell = new RTLIL::Cell; - cell->name = NEW_ID; - cell->type = "$not"; + RTLIL::Cell *cell = mod->addCell(NEW_ID, "$not"); cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.size()); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); cell->connections["\\A"] = sync_low_signals; cell->connections["\\Y"] = mod->addWire(NEW_ID); sync_high_signals.append(cell->connections["\\Y"]); - mod->add(cell); } if (sync_high_signals.size() > 1) { - RTLIL::Cell *cell = new RTLIL::Cell; - cell->name = NEW_ID; - cell->type = "$reduce_or"; + RTLIL::Cell *cell = mod->addCell(NEW_ID, "$reduce_or"); cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_high_signals.size()); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); cell->connections["\\A"] = sync_high_signals; cell->connections["\\Y"] = sync_high_signals = mod->addWire(NEW_ID); - mod->add(cell); } - RTLIL::Cell *inv_cell = new RTLIL::Cell; - inv_cell->name = NEW_ID; - inv_cell->type = "$not"; + RTLIL::Cell *inv_cell = mod->addCell(NEW_ID, "$not"); inv_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); inv_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_d.size()); inv_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_d.size()); inv_cell->connections["\\A"] = sync_value; inv_cell->connections["\\Y"] = sync_value_inv = mod->addWire(NEW_ID, sig_d.size()); - mod->add(inv_cell); - RTLIL::Cell *mux_set_cell = new RTLIL::Cell; - mux_set_cell->name = NEW_ID; - mux_set_cell->type = "$mux"; + RTLIL::Cell *mux_set_cell = mod->addCell(NEW_ID, "$mux"); mux_set_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size()); mux_set_cell->connections["\\A"] = sig_sr_set; mux_set_cell->connections["\\B"] = sync_value; mux_set_cell->connections["\\S"] = sync_high_signals; mux_set_cell->connections["\\Y"] = sig_sr_set = mod->addWire(NEW_ID, sig_d.size()); - mod->add(mux_set_cell); - RTLIL::Cell *mux_clr_cell = new RTLIL::Cell; - mux_clr_cell->name = NEW_ID; - mux_clr_cell->type = "$mux"; + RTLIL::Cell *mux_clr_cell = mod->addCell(NEW_ID, "$mux"); mux_clr_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size()); mux_clr_cell->connections["\\A"] = sig_sr_clr; mux_clr_cell->connections["\\B"] = sync_value_inv; mux_clr_cell->connections["\\S"] = sync_high_signals; mux_clr_cell->connections["\\Y"] = sig_sr_clr = mod->addWire(NEW_ID, sig_d.size()); - mod->add(mux_clr_cell); } std::stringstream sstr; sstr << "$procdff$" << (RTLIL::autoidx++); - RTLIL::Cell *cell = new RTLIL::Cell; - cell->name = sstr.str(); - cell->type = "$dffsr"; + RTLIL::Cell *cell = mod->addCell(sstr.str(), "$dffsr"); cell->attributes = proc->attributes; cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size()); cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1); @@ -156,7 +136,6 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S cell->connections["\\CLK"] = clk; cell->connections["\\SET"] = sig_sr_set; cell->connections["\\CLR"] = sig_sr_clr; - mod->add(cell); log(" created %s cell `%s' with %s edge clock and multiple level-sensitive resets.\n", cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative"); @@ -172,39 +151,28 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec RTLIL::SigSpec sig_sr_set = mod->addWire(NEW_ID, sig_in.size()); RTLIL::SigSpec sig_sr_clr = mod->addWire(NEW_ID, sig_in.size()); - RTLIL::Cell *inv_set = new RTLIL::Cell; - inv_set->name = NEW_ID; - inv_set->type = "$not"; + RTLIL::Cell *inv_set = mod->addCell(NEW_ID, "$not"); inv_set->parameters["\\A_SIGNED"] = RTLIL::Const(0); inv_set->parameters["\\A_WIDTH"] = RTLIL::Const(sig_in.size()); inv_set->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_in.size()); inv_set->connections["\\A"] = sig_set; inv_set->connections["\\Y"] = sig_set_inv; - mod->add(inv_set); - RTLIL::Cell *mux_sr_set = new RTLIL::Cell; - mux_sr_set->name = NEW_ID; - mux_sr_set->type = "$mux"; + RTLIL::Cell *mux_sr_set = mod->addCell(NEW_ID, "$mux"); mux_sr_set->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size()); mux_sr_set->connections[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.size()); mux_sr_set->connections[set_polarity ? "\\B" : "\\A"] = sig_set; mux_sr_set->connections["\\Y"] = sig_sr_set; mux_sr_set->connections["\\S"] = set; - mod->add(mux_sr_set); - RTLIL::Cell *mux_sr_clr = new RTLIL::Cell; - mux_sr_clr->name = NEW_ID; - mux_sr_clr->type = "$mux"; + RTLIL::Cell *mux_sr_clr = mod->addCell(NEW_ID, "$mux"); mux_sr_clr->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size()); mux_sr_clr->connections[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.size()); mux_sr_clr->connections[set_polarity ? "\\B" : "\\A"] = sig_set_inv; mux_sr_clr->connections["\\Y"] = sig_sr_clr; mux_sr_clr->connections["\\S"] = set; - mod->add(mux_sr_clr); - RTLIL::Cell *cell = new RTLIL::Cell; - cell->name = sstr.str(); - cell->type = "$dffsr"; + RTLIL::Cell *cell = mod->addCell(sstr.str(), "$dffsr"); cell->attributes = proc->attributes; cell->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size()); cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1); @@ -215,7 +183,6 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec cell->connections["\\CLK"] = clk; cell->connections["\\SET"] = sig_sr_set; cell->connections["\\CLR"] = sig_sr_clr; - mod->add(cell); log(" created %s cell `%s' with %s edge clock and %s level non-const reset.\n", cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative", set_polarity ? "positive" : "negative"); @@ -227,11 +194,8 @@ static void gen_dff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::Const val_ std::stringstream sstr; sstr << "$procdff$" << (RTLIL::autoidx++); - RTLIL::Cell *cell = new RTLIL::Cell; - cell->name = sstr.str(); - cell->type = arst ? "$adff" : "$dff"; + RTLIL::Cell *cell = mod->addCell(sstr.str(), arst ? "$adff" : "$dff"); cell->attributes = proc->attributes; - mod->cells[cell->name] = cell; cell->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size()); if (arst) { @@ -326,9 +290,7 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) } assert(inputs.size() == compare.size()); - RTLIL::Cell *cell = new RTLIL::Cell; - cell->name = NEW_ID; - cell->type = "$ne"; + RTLIL::Cell *cell = mod->addCell(NEW_ID, "$ne"); cell->parameters["\\A_SIGNED"] = RTLIL::Const(false, 1); cell->parameters["\\B_SIGNED"] = RTLIL::Const(false, 1); cell->parameters["\\A_WIDTH"] = RTLIL::Const(inputs.size()); @@ -337,7 +299,6 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) cell->connections["\\A"] = inputs; cell->connections["\\B"] = compare; cell->connections["\\Y"] = sync_level->signal; - mod->add(cell); many_async_rules.clear(); } diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc index 804c51fd3..5bb1ab948 100644 --- a/passes/proc/proc_mux.cc +++ b/passes/proc/proc_mux.cc @@ -86,13 +86,8 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, else { // create compare cell - RTLIL::Cell *eq_cell = new RTLIL::Cell; - std::stringstream sstr2; - sstr2 << sstr.str() << "_CMP" << cmp_wire->width; - eq_cell->name = sstr2.str(); - eq_cell->type = "$eq"; + RTLIL::Cell *eq_cell = mod->addCell(stringf("%s_CMP%d", sstr.str().c_str(), cmp_wire->width), "$eq"); eq_cell->attributes = sw->attributes; - mod->cells[eq_cell->name] = eq_cell; eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(0); @@ -120,11 +115,8 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, mod->wires[ctrl_wire->name] = ctrl_wire; // reduce cmp vector to one logic signal - RTLIL::Cell *any_cell = new RTLIL::Cell; - any_cell->name = sstr.str() + "_ANY"; - any_cell->type = "$reduce_or"; + RTLIL::Cell *any_cell = mod->addCell(sstr.str() + "_ANY", "$reduce_or"); any_cell->attributes = sw->attributes; - mod->cells[any_cell->name] = any_cell; any_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); any_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cmp_wire->width); @@ -161,11 +153,8 @@ static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, mod->wires[result_wire->name] = result_wire; // create the multiplexer itself - RTLIL::Cell *mux_cell = new RTLIL::Cell; - mux_cell->name = sstr.str(); - mux_cell->type = "$mux"; + RTLIL::Cell *mux_cell = mod->addCell(sstr.str(), "$mux"); mux_cell->attributes = sw->attributes; - mod->cells[mux_cell->name] = mux_cell; mux_cell->parameters["\\WIDTH"] = RTLIL::Const(when_signal.size()); mux_cell->connections["\\A"] = else_signal; diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc index c9363f4bf..29ce899ef 100644 --- a/passes/sat/expose.cc +++ b/passes/sat/expose.cc @@ -554,15 +554,12 @@ struct ExposePass : public Pass { if (info.clk_polarity) { module->connections.push_back(RTLIL::SigSig(wire_c, info.sig_clk)); } else { - RTLIL::Cell *c = new RTLIL::Cell; - c->name = NEW_ID; - c->type = "$not"; + RTLIL::Cell *c = module->addCell(NEW_ID, "$not"); c->parameters["\\A_SIGNED"] = 0; c->parameters["\\A_WIDTH"] = 1; c->parameters["\\Y_WIDTH"] = 1; c->connections["\\A"] = info.sig_clk; c->connections["\\Y"] = wire_c; - module->add(c); } if (info.sig_arst != RTLIL::State::Sm) @@ -575,15 +572,12 @@ struct ExposePass : public Pass { if (info.arst_polarity) { module->connections.push_back(RTLIL::SigSig(wire_r, info.sig_arst)); } else { - RTLIL::Cell *c = new RTLIL::Cell; - c->name = NEW_ID; - c->type = "$not"; + RTLIL::Cell *c = module->addCell(NEW_ID, "$not"); c->parameters["\\A_SIGNED"] = 0; c->parameters["\\A_WIDTH"] = 1; c->parameters["\\Y_WIDTH"] = 1; c->connections["\\A"] = info.sig_arst; c->connections["\\Y"] = wire_r; - module->add(c); } RTLIL::Wire *wire_v = new RTLIL::Wire; @@ -598,7 +592,7 @@ struct ExposePass : public Pass { if (flag_evert) { - std::vector delete_cells; + std::vector delete_cells; for (auto &it : module->cells) { @@ -665,13 +659,12 @@ struct ExposePass : public Pass { } } - delete_cells.push_back(cell->name); + delete_cells.push_back(cell); } - for (auto &it : delete_cells) { - log("Removing cell: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(it), RTLIL::id2cstr(module->cells.at(it)->type)); - delete module->cells.at(it); - module->cells.erase(it); + for (auto cell : delete_cells) { + log("Removing cell: %s/%s (%s)\n", log_id(module), log_id(cell), log_id(cell->type)); + module->remove(cell); } } diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index ba01bc322..79dec3b54 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -718,12 +718,9 @@ struct FreduceWorker { inv_sig = module->addWire(NEW_ID); - RTLIL::Cell *inv_cell = new RTLIL::Cell; - inv_cell->name = NEW_ID; - inv_cell->type = "$_INV_"; + RTLIL::Cell *inv_cell = module->addCell(NEW_ID, "$_INV_"); inv_cell->connections["\\A"] = grp[0].bit; inv_cell->connections["\\Y"] = inv_sig; - module->add(inv_cell); } module->connections.push_back(RTLIL::SigSig(grp[i].bit, inv_sig)); diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index 12384e2cc..aff664242 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -115,15 +115,8 @@ static void create_miter_equiv(struct Pass *that, std::vector args, miter_module->name = miter_name; design->modules[miter_name] = miter_module; - RTLIL::Cell *gold_cell = new RTLIL::Cell; - gold_cell->name = "\\gold"; - gold_cell->type = gold_name; - miter_module->add(gold_cell); - - RTLIL::Cell *gate_cell = new RTLIL::Cell; - gate_cell->name = "\\gate"; - gate_cell->type = gate_name; - miter_module->add(gate_cell); + RTLIL::Cell *gold_cell = miter_module->addCell("\\gold", gold_name); + RTLIL::Cell *gate_cell = miter_module->addCell("\\gate", gate_name); RTLIL::SigSpec all_conditions; @@ -166,9 +159,7 @@ static void create_miter_equiv(struct Pass *that, std::vector args, { RTLIL::SigSpec gold_x = miter_module->addWire(NEW_ID, w2_gold->width); for (int i = 0; i < w2_gold->width; i++) { - RTLIL::Cell *eqx_cell = new RTLIL::Cell; - eqx_cell->name = NEW_ID; - eqx_cell->type = "$eqx"; + RTLIL::Cell *eqx_cell = miter_module->addCell(NEW_ID, "$eqx"); eqx_cell->parameters["\\A_WIDTH"] = 1; eqx_cell->parameters["\\B_WIDTH"] = 1; eqx_cell->parameters["\\Y_WIDTH"] = 1; @@ -177,15 +168,12 @@ static void create_miter_equiv(struct Pass *that, std::vector args, eqx_cell->connections["\\A"] = RTLIL::SigSpec(w2_gold, i); eqx_cell->connections["\\B"] = RTLIL::State::Sx; eqx_cell->connections["\\Y"] = gold_x.extract(i, 1); - miter_module->add(eqx_cell); } RTLIL::SigSpec gold_masked = miter_module->addWire(NEW_ID, w2_gold->width); RTLIL::SigSpec gate_masked = miter_module->addWire(NEW_ID, w2_gate->width); - RTLIL::Cell *or_gold_cell = new RTLIL::Cell; - or_gold_cell->name = NEW_ID; - or_gold_cell->type = "$or"; + RTLIL::Cell *or_gold_cell = miter_module->addCell(NEW_ID, "$or"); or_gold_cell->parameters["\\A_WIDTH"] = w2_gold->width; or_gold_cell->parameters["\\B_WIDTH"] = w2_gold->width; or_gold_cell->parameters["\\Y_WIDTH"] = w2_gold->width; @@ -194,11 +182,8 @@ static void create_miter_equiv(struct Pass *that, std::vector args, or_gold_cell->connections["\\A"] = w2_gold; or_gold_cell->connections["\\B"] = gold_x; or_gold_cell->connections["\\Y"] = gold_masked; - miter_module->add(or_gold_cell); - RTLIL::Cell *or_gate_cell = new RTLIL::Cell; - or_gate_cell->name = NEW_ID; - or_gate_cell->type = "$or"; + RTLIL::Cell *or_gate_cell = miter_module->addCell(NEW_ID, "$or"); or_gate_cell->parameters["\\A_WIDTH"] = w2_gate->width; or_gate_cell->parameters["\\B_WIDTH"] = w2_gate->width; or_gate_cell->parameters["\\Y_WIDTH"] = w2_gate->width; @@ -207,11 +192,8 @@ static void create_miter_equiv(struct Pass *that, std::vector args, or_gate_cell->connections["\\A"] = w2_gate; or_gate_cell->connections["\\B"] = gold_x; or_gate_cell->connections["\\Y"] = gate_masked; - miter_module->add(or_gate_cell); - RTLIL::Cell *eq_cell = new RTLIL::Cell; - eq_cell->name = NEW_ID; - eq_cell->type = "$eqx"; + RTLIL::Cell *eq_cell = miter_module->addCell(NEW_ID, "$eqx"); eq_cell->parameters["\\A_WIDTH"] = w2_gold->width; eq_cell->parameters["\\B_WIDTH"] = w2_gate->width; eq_cell->parameters["\\Y_WIDTH"] = 1; @@ -221,13 +203,10 @@ static void create_miter_equiv(struct Pass *that, std::vector args, eq_cell->connections["\\B"] = gate_masked; eq_cell->connections["\\Y"] = miter_module->addWire(NEW_ID); this_condition = eq_cell->connections["\\Y"]; - miter_module->add(eq_cell); } else { - RTLIL::Cell *eq_cell = new RTLIL::Cell; - eq_cell->name = NEW_ID; - eq_cell->type = "$eqx"; + RTLIL::Cell *eq_cell = miter_module->addCell(NEW_ID, "$eqx"); eq_cell->parameters["\\A_WIDTH"] = w2_gold->width; eq_cell->parameters["\\B_WIDTH"] = w2_gate->width; eq_cell->parameters["\\Y_WIDTH"] = 1; @@ -237,7 +216,6 @@ static void create_miter_equiv(struct Pass *that, std::vector args, eq_cell->connections["\\B"] = w2_gate; eq_cell->connections["\\Y"] = miter_module->addWire(NEW_ID); this_condition = eq_cell->connections["\\Y"]; - miter_module->add(eq_cell); } if (flag_make_outcmp) @@ -254,25 +232,19 @@ static void create_miter_equiv(struct Pass *that, std::vector args, } if (all_conditions.size() != 1) { - RTLIL::Cell *reduce_cell = new RTLIL::Cell; - reduce_cell->name = NEW_ID; - reduce_cell->type = "$reduce_and"; + RTLIL::Cell *reduce_cell = miter_module->addCell(NEW_ID, "$reduce_and"); reduce_cell->parameters["\\A_WIDTH"] = all_conditions.size(); reduce_cell->parameters["\\Y_WIDTH"] = 1; reduce_cell->parameters["\\A_SIGNED"] = 0; reduce_cell->connections["\\A"] = all_conditions; reduce_cell->connections["\\Y"] = miter_module->addWire(NEW_ID); all_conditions = reduce_cell->connections["\\Y"]; - miter_module->add(reduce_cell); } if (flag_make_assert) { - RTLIL::Cell *assert_cell = new RTLIL::Cell; - assert_cell->name = NEW_ID; - assert_cell->type = "$assert"; + RTLIL::Cell *assert_cell = miter_module->addCell(NEW_ID, "$assert"); assert_cell->connections["\\A"] = all_conditions; assert_cell->connections["\\EN"] = RTLIL::SigSpec(1, 1); - miter_module->add(assert_cell); } RTLIL::Wire *w_trigger = new RTLIL::Wire; @@ -280,16 +252,13 @@ static void create_miter_equiv(struct Pass *that, std::vector args, w_trigger->port_output = true; miter_module->add(w_trigger); - RTLIL::Cell *not_cell = new RTLIL::Cell; - not_cell->name = NEW_ID; - not_cell->type = "$not"; + RTLIL::Cell *not_cell = miter_module->addCell(NEW_ID, "$not"); not_cell->parameters["\\A_WIDTH"] = all_conditions.size(); not_cell->parameters["\\A_WIDTH"] = all_conditions.size(); not_cell->parameters["\\Y_WIDTH"] = w_trigger->width; not_cell->parameters["\\A_SIGNED"] = 0; not_cell->connections["\\A"] = all_conditions; not_cell->connections["\\Y"] = w_trigger; - miter_module->add(not_cell); miter_module->fixup_ports(); diff --git a/passes/sat/share.cc b/passes/sat/share.cc index ede2fa88c..7e24e1f04 100644 --- a/passes/sat/share.cc +++ b/passes/sat/share.cc @@ -282,15 +282,12 @@ struct ShareWorker RTLIL::SigSpec a = module->Mux(NEW_ID, a2, a1, act); RTLIL::Wire *y = module->addWire(NEW_ID, y_width); - RTLIL::Cell *supercell = new RTLIL::Cell; - supercell->name = NEW_ID; - supercell->type = c1->type; + RTLIL::Cell *supercell = module->addCell(NEW_ID, c1->type); supercell->parameters["\\A_SIGNED"] = a_signed; supercell->parameters["\\A_WIDTH"] = a_width; supercell->parameters["\\Y_WIDTH"] = y_width; supercell->connections["\\A"] = a; supercell->connections["\\Y"] = y; - module->add(supercell); RTLIL::SigSpec new_y1(y, 0, y1.size()); RTLIL::SigSpec new_y2(y, 0, y2.size()); @@ -846,8 +843,7 @@ struct ShareWorker log("Removing %d cells in module %s:\n", SIZE(cells_to_remove), log_id(module)); for (auto c : cells_to_remove) { log(" Removing cell %s (%s).\n", log_id(c), log_id(c->type)); - module->cells.erase(c->name); - delete c; + module->remove(c); } } diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc index 4bf73358b..c047e418a 100644 --- a/passes/techmap/dfflibmap.cc +++ b/passes/techmap/dfflibmap.cc @@ -394,28 +394,24 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module) } std::map stats; - for (auto cell : cell_list) { - cell_mapping &cm = cell_mappings[cell->type]; - RTLIL::Cell *new_cell = new RTLIL::Cell; - new_cell->name = cell->name; - new_cell->type = "\\" + cm.cell_name; + for (auto cell : cell_list) + { + auto cell_type = cell->type; + auto cell_name = cell->name; + auto cell_connections = cell->connections; + module->remove(cell); + + cell_mapping &cm = cell_mappings[cell_type]; + RTLIL::Cell *new_cell = module->addCell(cell_name, "\\" + cm.cell_name); + for (auto &port : cm.ports) { RTLIL::SigSpec sig; if ('A' <= port.second && port.second <= 'Z') { - sig = cell->connections[std::string("\\") + port.second]; + sig = cell_connections[std::string("\\") + port.second]; } else if ('a' <= port.second && port.second <= 'z') { - sig = cell->connections[std::string("\\") + char(port.second - ('a' - 'A'))]; - RTLIL::Cell *inv_cell = new RTLIL::Cell; - RTLIL::Wire *inv_wire = new RTLIL::Wire; - inv_cell->name = stringf("$dfflibmap$inv$%d", RTLIL::autoidx); - inv_wire->name = stringf("$dfflibmap$sig$%d", RTLIL::autoidx++); - inv_cell->type = "$_INV_"; - inv_cell->connections[port.second == 'q' ? "\\Y" : "\\A"] = sig; - sig = RTLIL::SigSpec(inv_wire); - inv_cell->connections[port.second == 'q' ? "\\A" : "\\Y"] = sig; - module->cells[inv_cell->name] = inv_cell; - module->wires[inv_wire->name] = inv_wire; + sig = cell_connections[std::string("\\") + char(port.second - ('a' - 'A'))]; + sig = module->InvGate(NEW_ID, sig); } else if (port.second == '0' || port.second == '1') { sig = RTLIL::SigSpec(port.second == '0' ? 0 : 1, 1); @@ -424,9 +420,8 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module) log_abort(); new_cell->connections["\\" + port.first] = sig; } - stats[stringf(" mapped %%d %s cells to %s cells.\n", cell->type.c_str(), new_cell->type.c_str())]++; - module->cells[cell->name] = new_cell; - delete cell; + + stats[stringf(" mapped %%d %s cells to %s cells.\n", cell_type.c_str(), new_cell->type.c_str())]++; } for (auto &stat: stats) diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index 4c3aec31d..e52c8fe52 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -297,10 +297,7 @@ namespace SigSet> sig2port; // create new cell - RTLIL::Cell *cell = new RTLIL::Cell; - cell->name = stringf("$extract$%s$%d", needle->name.c_str(), RTLIL::autoidx++); - cell->type = needle->name; - haystack->add(cell); + RTLIL::Cell *cell = haystack->addCell(stringf("$extract$%s$%d", needle->name.c_str(), RTLIL::autoidx++), needle->name); // create cell ports for (auto &it : needle->wires) { @@ -333,8 +330,7 @@ namespace } } - haystack->cells.erase(haystack_cell->name); - delete haystack_cell; + haystack->remove(haystack_cell); } return cell; @@ -741,9 +737,7 @@ struct ExtractPass : public Pass { } for (auto cell : cells) { - RTLIL::Cell *newCell = new RTLIL::Cell; - newCell->name = cell->name; - newCell->type = cell->type; + RTLIL::Cell *newCell = newMod->addCell(cell->name, cell->type); newCell->parameters = cell->parameters; for (auto &conn : cell->connections) { std::vector chunks = sigmap(conn.second); @@ -752,7 +746,6 @@ struct ExtractPass : public Pass { chunk.wire = newMod->wires.at(chunk.wire->name); newCell->connections[conn.first] = chunks; } - newMod->add(newCell); } } diff --git a/passes/techmap/hilomap.cc b/passes/techmap/hilomap.cc index 51b8802c4..e41536707 100644 --- a/passes/techmap/hilomap.cc +++ b/passes/techmap/hilomap.cc @@ -34,22 +34,16 @@ void hilomap_worker(RTLIL::SigSpec &sig) if (bit == RTLIL::State::S1 && !hicell_celltype.empty()) { if (!singleton_mode || last_hi == RTLIL::State::Sm) { last_hi = module->addWire(NEW_ID); - RTLIL::Cell *cell = new RTLIL::Cell; - cell->name = NEW_ID; - cell->type = RTLIL::escape_id(hicell_celltype); + RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(hicell_celltype)); cell->connections[RTLIL::escape_id(hicell_portname)] = last_hi; - module->add(cell); } bit = last_hi; } if (bit == RTLIL::State::S0 && !locell_celltype.empty()) { if (!singleton_mode || last_lo == RTLIL::State::Sm) { last_lo = module->addWire(NEW_ID); - RTLIL::Cell *cell = new RTLIL::Cell; - cell->name = NEW_ID; - cell->type = RTLIL::escape_id(locell_celltype); + RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(locell_celltype)); cell->connections[RTLIL::escape_id(locell_portname)] = last_lo; - module->add(cell); } bit = last_lo; } diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc index 09147383a..7b2484d84 100644 --- a/passes/techmap/iopadmap.cc +++ b/passes/techmap/iopadmap.cc @@ -176,9 +176,7 @@ struct IopadmapPass : public Pass { { for (int i = 0; i < wire->width; i++) { - RTLIL::Cell *cell = new RTLIL::Cell; - cell->name = NEW_ID; - cell->type = RTLIL::escape_id(celltype); + RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype)); cell->connections[RTLIL::escape_id(portname)] = RTLIL::SigSpec(wire, i); if (!portname2.empty()) cell->connections[RTLIL::escape_id(portname2)] = RTLIL::SigSpec(new_wire, i); @@ -187,14 +185,11 @@ struct IopadmapPass : public Pass { if (!nameparam.empty()) cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(stringf("%s[%d]", RTLIL::id2cstr(wire->name), i)); cell->attributes["\\keep"] = RTLIL::Const(1); - module->add(cell); } } else { - RTLIL::Cell *cell = new RTLIL::Cell; - cell->name = NEW_ID; - cell->type = RTLIL::escape_id(celltype); + RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype)); cell->connections[RTLIL::escape_id(portname)] = RTLIL::SigSpec(wire); if (!portname2.empty()) cell->connections[RTLIL::escape_id(portname2)] = RTLIL::SigSpec(new_wire); @@ -203,7 +198,6 @@ struct IopadmapPass : public Pass { if (!nameparam.empty()) cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(RTLIL::id2cstr(wire->name)); cell->attributes["\\keep"] = RTLIL::Const(1); - module->add(cell); } wire->port_id = 0; diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc index 034677d3b..8489e7fd9 100644 --- a/passes/techmap/simplemap.cc +++ b/passes/techmap/simplemap.cc @@ -35,12 +35,9 @@ static void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell) sig_a.extend(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool()); for (int i = 0; i < SIZE(sig_y); i++) { - RTLIL::Cell *gate = new RTLIL::Cell; - gate->name = NEW_ID; - gate->type = "$_INV_"; + RTLIL::Cell *gate = module->addCell(NEW_ID, "$_INV_"); gate->connections["\\A"] = sig_a[i]; gate->connections["\\Y"] = sig_y[i]; - module->add(gate); } } @@ -78,12 +75,9 @@ static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::SigSpec sig_t = module->addWire(NEW_ID, SIZE(sig_y)); for (int i = 0; i < SIZE(sig_y); i++) { - RTLIL::Cell *gate = new RTLIL::Cell; - gate->name = NEW_ID; - gate->type = "$_INV_"; + RTLIL::Cell *gate = module->addCell(NEW_ID, "$_INV_"); gate->connections["\\A"] = sig_t[i]; gate->connections["\\Y"] = sig_y[i]; - module->add(gate); } sig_y = sig_t; @@ -97,13 +91,10 @@ static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell) log_assert(!gate_type.empty()); for (int i = 0; i < SIZE(sig_y); i++) { - RTLIL::Cell *gate = new RTLIL::Cell; - gate->name = NEW_ID; - gate->type = gate_type; + RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); gate->connections["\\A"] = sig_a[i]; gate->connections["\\B"] = sig_b[i]; gate->connections["\\Y"] = sig_y[i]; - module->add(gate); } } @@ -150,14 +141,11 @@ static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) continue; } - RTLIL::Cell *gate = new RTLIL::Cell; - gate->name = NEW_ID; - gate->type = gate_type; + RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); gate->connections["\\A"] = sig_a[i]; gate->connections["\\B"] = sig_a[i+1]; gate->connections["\\Y"] = sig_t[i/2]; last_output = &gate->connections["\\Y"]; - module->add(gate); } sig_a = sig_t; @@ -165,13 +153,10 @@ static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) if (cell->type == "$reduce_xnor") { RTLIL::SigSpec sig_t = module->addWire(NEW_ID); - RTLIL::Cell *gate = new RTLIL::Cell; - gate->name = NEW_ID; - gate->type = "$_INV_"; + RTLIL::Cell *gate = module->addCell(NEW_ID, "$_INV_"); gate->connections["\\A"] = sig_a; gate->connections["\\Y"] = sig_t; last_output = &gate->connections["\\Y"]; - module->add(gate); sig_a = sig_t; } @@ -195,13 +180,10 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig) continue; } - RTLIL::Cell *gate = new RTLIL::Cell; - gate->name = NEW_ID; - gate->type = "$_OR_"; + RTLIL::Cell *gate = module->addCell(NEW_ID, "$_OR_"); gate->connections["\\A"] = sig[i]; gate->connections["\\B"] = sig[i+1]; gate->connections["\\Y"] = sig_t[i/2]; - module->add(gate); } sig = sig_t; @@ -226,12 +208,9 @@ static void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell) sig_y = sig_y.extract(0, 1); } - RTLIL::Cell *gate = new RTLIL::Cell; - gate->name = NEW_ID; - gate->type = "$_INV_"; + RTLIL::Cell *gate = module->addCell(NEW_ID, "$_INV_"); gate->connections["\\A"] = sig_a; gate->connections["\\Y"] = sig_y; - module->add(gate); } static void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell) @@ -257,13 +236,10 @@ static void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell) if (cell->type == "$logic_or") gate_type = "$_OR_"; log_assert(!gate_type.empty()); - RTLIL::Cell *gate = new RTLIL::Cell; - gate->name = NEW_ID; - gate->type = gate_type; + RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); gate->connections["\\A"] = sig_a; gate->connections["\\B"] = sig_b; gate->connections["\\Y"] = sig_y; - module->add(gate); } static void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell) @@ -273,14 +249,11 @@ static void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::SigSpec sig_y = cell->connections.at("\\Y"); for (int i = 0; i < SIZE(sig_y); i++) { - RTLIL::Cell *gate = new RTLIL::Cell; - gate->name = NEW_ID; - gate->type = "$_MUX_"; + RTLIL::Cell *gate = module->addCell(NEW_ID, "$_MUX_"); gate->connections["\\A"] = sig_a[i]; gate->connections["\\B"] = sig_b[i]; gate->connections["\\S"] = cell->connections.at("\\S"); gate->connections["\\Y"] = sig_y[i]; - module->add(gate); } } @@ -313,13 +286,10 @@ static void simplemap_sr(RTLIL::Module *module, RTLIL::Cell *cell) std::string gate_type = stringf("$_SR_%c%c_", set_pol, clr_pol); for (int i = 0; i < width; i++) { - RTLIL::Cell *gate = new RTLIL::Cell; - gate->name = NEW_ID; - gate->type = gate_type; + RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); gate->connections["\\S"] = sig_s[i]; gate->connections["\\R"] = sig_r[i]; gate->connections["\\Q"] = sig_q[i]; - module->add(gate); } } @@ -335,13 +305,10 @@ static void simplemap_dff(RTLIL::Module *module, RTLIL::Cell *cell) std::string gate_type = stringf("$_DFF_%c_", clk_pol); for (int i = 0; i < width; i++) { - RTLIL::Cell *gate = new RTLIL::Cell; - gate->name = NEW_ID; - gate->type = gate_type; + RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); gate->connections["\\C"] = sig_clk; gate->connections["\\D"] = sig_d[i]; gate->connections["\\Q"] = sig_q[i]; - module->add(gate); } } @@ -361,15 +328,12 @@ static void simplemap_dffsr(RTLIL::Module *module, RTLIL::Cell *cell) std::string gate_type = stringf("$_DFFSR_%c%c%c_", clk_pol, set_pol, clr_pol); for (int i = 0; i < width; i++) { - RTLIL::Cell *gate = new RTLIL::Cell; - gate->name = NEW_ID; - gate->type = gate_type; + RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); gate->connections["\\C"] = sig_clk; gate->connections["\\S"] = sig_s[i]; gate->connections["\\R"] = sig_r[i]; gate->connections["\\D"] = sig_d[i]; gate->connections["\\Q"] = sig_q[i]; - module->add(gate); } } @@ -392,14 +356,11 @@ static void simplemap_adff(RTLIL::Module *module, RTLIL::Cell *cell) std::string gate_type_1 = stringf("$_DFF_%c%c1_", clk_pol, rst_pol); for (int i = 0; i < width; i++) { - RTLIL::Cell *gate = new RTLIL::Cell; - gate->name = NEW_ID; - gate->type = rst_val.at(i) == RTLIL::State::S1 ? gate_type_1 : gate_type_0; + RTLIL::Cell *gate = module->addCell(NEW_ID, rst_val.at(i) == RTLIL::State::S1 ? gate_type_1 : gate_type_0); gate->connections["\\C"] = sig_clk; gate->connections["\\R"] = sig_rst; gate->connections["\\D"] = sig_d[i]; gate->connections["\\Q"] = sig_q[i]; - module->add(gate); } } @@ -415,13 +376,10 @@ static void simplemap_dlatch(RTLIL::Module *module, RTLIL::Cell *cell) std::string gate_type = stringf("$_DLATCH_%c_", en_pol); for (int i = 0; i < width; i++) { - RTLIL::Cell *gate = new RTLIL::Cell; - gate->name = NEW_ID; - gate->type = gate_type; + RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); gate->connections["\\E"] = sig_en; gate->connections["\\D"] = sig_d[i]; gate->connections["\\Q"] = sig_q[i]; - module->add(gate); } } @@ -490,10 +448,8 @@ struct SimplemapPass : public Pass { mappers.at(cell_it.second->type)(mod_it.second, cell_it.second); delete_cells.push_back(cell_it.second); } - for (auto &it : delete_cells) { - mod_it.second->cells.erase(it->name); - delete it; - } + for (auto c : delete_cells) + mod_it.second->remove(c); } } } SimplemapPass; diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 8d7b21e0f..e8385844d 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -114,15 +114,12 @@ struct TechmapWorker log_error("Technology map yielded processes -> this is not supported.\n"); } - // erase from namespace first for _TECHMAP_REPLACE_ to work - module->cells.erase(cell->name); std::string orig_cell_name; - if (!flatten_mode) for (auto &it : tpl->cells) if (it.first == "\\_TECHMAP_REPLACE_") { orig_cell_name = cell->name; - cell->name = stringf("$techmap%d", RTLIL::autoidx++) + cell->name; + module->rename(cell, stringf("$techmap%d", RTLIL::autoidx++) + cell->name); break; } @@ -183,20 +180,29 @@ struct TechmapWorker } } - for (auto &it : tpl->cells) { - RTLIL::Cell *c = new RTLIL::Cell(*it.second); - if (!flatten_mode && c->type.substr(0, 2) == "\\$") - c->type = c->type.substr(1); - if (!flatten_mode && c->name == "\\_TECHMAP_REPLACE_") - c->name = orig_cell_name; + for (auto &it : tpl->cells) + { + RTLIL::IdString c_name = it.second->name; + RTLIL::IdString c_type = it.second->type; + + if (!flatten_mode && c_type.substr(0, 2) == "\\$") + c_type = c_type.substr(1); + + if (!flatten_mode && c_name == "\\_TECHMAP_REPLACE_") + c_name = orig_cell_name; else - apply_prefix(cell->name, c->name); + apply_prefix(cell->name, c_name); + + RTLIL::Cell *c = module->addCell(c_name, c_type); + c->connections = it.second->connections; + c->parameters = it.second->parameters; + c->attributes = it.second->attributes; + design->select(module, c); + for (auto &it2 : c->connections) { apply_prefix(cell->name, it2.second, module); port_signal_map.apply(it2.second); } - module->add(c); - design->select(module, c); } for (auto &it : tpl->connections) { @@ -208,7 +214,7 @@ struct TechmapWorker module->connections.push_back(c); } - delete cell; + module->remove(cell); } bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, std::set &handled_cells, @@ -254,8 +260,7 @@ struct TechmapWorker if (simplemap_mappers.count(cell->type) == 0) log_error("No simplemap mapper for cell type %s found!\n", RTLIL::id2cstr(cell->type)); simplemap_mappers.at(cell->type)(module, cell); - module->cells.erase(cell->name); - delete cell; + module->remove(cell); cell = NULL; did_something = true; break; -- cgit v1.2.3 From 4755e14e7b9ba57ea21bec4c0d0b3ac6080307e4 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 26 Jul 2014 00:38:44 +0200 Subject: Added copy-constructor-like module->addCell(name, other) method --- passes/hierarchy/submod.cc | 5 +---- passes/techmap/techmap.cc | 12 ++++-------- 2 files changed, 5 insertions(+), 12 deletions(-) (limited to 'passes') diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index 204f899a0..be580ca04 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -162,10 +162,7 @@ struct SubmodWorker } for (RTLIL::Cell *cell : submod.cells) { - RTLIL::Cell *new_cell = new_mod->addCell(cell->name, cell->type); - new_cell->connections = cell->connections; - new_cell->parameters = cell->parameters; - new_cell->attributes = cell->attributes; + RTLIL::Cell *new_cell = new_mod->addCell(cell->name, cell); for (auto &conn : new_cell->connections) for (auto &bit : conn.second) if (bit.wire != NULL) { diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index e8385844d..94cb1e8dd 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -183,22 +183,18 @@ struct TechmapWorker for (auto &it : tpl->cells) { RTLIL::IdString c_name = it.second->name; - RTLIL::IdString c_type = it.second->type; - - if (!flatten_mode && c_type.substr(0, 2) == "\\$") - c_type = c_type.substr(1); if (!flatten_mode && c_name == "\\_TECHMAP_REPLACE_") c_name = orig_cell_name; else apply_prefix(cell->name, c_name); - RTLIL::Cell *c = module->addCell(c_name, c_type); - c->connections = it.second->connections; - c->parameters = it.second->parameters; - c->attributes = it.second->attributes; + RTLIL::Cell *c = module->addCell(c_name, it.second); design->select(module, c); + if (!flatten_mode && c->type.substr(0, 2) == "\\$") + c->type = c->type.substr(1); + for (auto &it2 : c->connections) { apply_prefix(cell->name, it2.second, module); port_signal_map.apply(it2.second); -- cgit v1.2.3 From cc4f10883bcc5f0a3c1b4f0937e60be3c6a1b121 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 26 Jul 2014 11:58:03 +0200 Subject: Renamed RTLIL::{Module,Cell}::connections to connections_ --- passes/abc/abc.cc | 84 ++++++++--------- passes/abc/blifparse.cc | 12 +-- passes/cmds/add.cc | 4 +- passes/cmds/connect.cc | 10 +- passes/cmds/connwrappers.cc | 4 +- passes/cmds/scatter.cc | 6 +- passes/cmds/scc.cc | 2 +- passes/cmds/select.cc | 4 +- passes/cmds/setundef.cc | 4 +- passes/cmds/show.cc | 10 +- passes/cmds/splice.cc | 20 ++-- passes/cmds/splitnets.cc | 2 +- passes/fsm/fsm_detect.cc | 18 ++-- passes/fsm/fsm_expand.cc | 56 +++++------ passes/fsm/fsm_extract.cc | 38 ++++---- passes/fsm/fsm_map.cc | 56 +++++------ passes/fsm/fsm_opt.cc | 16 ++-- passes/fsm/fsmdata.h | 4 +- passes/hierarchy/hierarchy.cc | 10 +- passes/hierarchy/submod.cc | 12 +-- passes/memory/memory_collect.cc | 28 +++--- passes/memory/memory_dff.cc | 38 ++++---- passes/memory/memory_map.cc | 74 +++++++-------- passes/memory/memory_share.cc | 102 ++++++++++---------- passes/memory/memory_unpack.cc | 14 +-- passes/opt/opt_clean.cc | 16 ++-- passes/opt/opt_const.cc | 202 ++++++++++++++++++++-------------------- passes/opt/opt_muxtree.cc | 26 +++--- passes/opt/opt_reduce.cc | 78 ++++++++-------- passes/opt/opt_rmdff.cc | 52 +++++------ passes/opt/opt_share.cc | 16 ++-- passes/proc/proc_arst.cc | 44 ++++----- passes/proc/proc_dff.cc | 90 +++++++++--------- passes/proc/proc_mux.cc | 30 +++--- passes/sat/expose.cc | 72 +++++++------- passes/sat/freduce.cc | 14 +-- passes/sat/miter.cc | 58 ++++++------ passes/sat/sat.cc | 4 +- passes/sat/share.cc | 84 ++++++++--------- passes/techmap/dfflibmap.cc | 4 +- passes/techmap/extract.cc | 24 ++--- passes/techmap/hilomap.cc | 4 +- passes/techmap/iopadmap.cc | 8 +- passes/techmap/simplemap.cc | 198 +++++++++++++++++++-------------------- passes/techmap/techmap.cc | 18 ++-- 45 files changed, 835 insertions(+), 835 deletions(-) (limited to 'passes') diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index 980e69aa2..80828e153 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -111,11 +111,11 @@ static void extract_cell(RTLIL::Cell *cell, bool keepff) { if (clk_polarity != (cell->type == "$_DFF_P_")) return; - if (clk_sig != assign_map(cell->connections["\\C"])) + if (clk_sig != assign_map(cell->connections_["\\C"])) return; - RTLIL::SigSpec sig_d = cell->connections["\\D"]; - RTLIL::SigSpec sig_q = cell->connections["\\Q"]; + RTLIL::SigSpec sig_d = cell->connections_["\\D"]; + RTLIL::SigSpec sig_q = cell->connections_["\\Q"]; if (keepff) for (auto &c : sig_q.chunks()) @@ -133,8 +133,8 @@ static void extract_cell(RTLIL::Cell *cell, bool keepff) if (cell->type == "$_INV_") { - RTLIL::SigSpec sig_a = cell->connections["\\A"]; - RTLIL::SigSpec sig_y = cell->connections["\\Y"]; + RTLIL::SigSpec sig_a = cell->connections_["\\A"]; + RTLIL::SigSpec sig_y = cell->connections_["\\Y"]; assign_map.apply(sig_a); assign_map.apply(sig_y); @@ -147,9 +147,9 @@ static void extract_cell(RTLIL::Cell *cell, bool keepff) if (cell->type == "$_AND_" || cell->type == "$_OR_" || cell->type == "$_XOR_") { - RTLIL::SigSpec sig_a = cell->connections["\\A"]; - RTLIL::SigSpec sig_b = cell->connections["\\B"]; - RTLIL::SigSpec sig_y = cell->connections["\\Y"]; + RTLIL::SigSpec sig_a = cell->connections_["\\A"]; + RTLIL::SigSpec sig_b = cell->connections_["\\B"]; + RTLIL::SigSpec sig_y = cell->connections_["\\Y"]; assign_map.apply(sig_a); assign_map.apply(sig_b); @@ -173,10 +173,10 @@ static void extract_cell(RTLIL::Cell *cell, bool keepff) if (cell->type == "$_MUX_") { - RTLIL::SigSpec sig_a = cell->connections["\\A"]; - RTLIL::SigSpec sig_b = cell->connections["\\B"]; - RTLIL::SigSpec sig_s = cell->connections["\\S"]; - RTLIL::SigSpec sig_y = cell->connections["\\Y"]; + RTLIL::SigSpec sig_a = cell->connections_["\\A"]; + RTLIL::SigSpec sig_b = cell->connections_["\\B"]; + RTLIL::SigSpec sig_s = cell->connections_["\\S"]; + RTLIL::SigSpec sig_y = cell->connections_["\\Y"]; assign_map.apply(sig_a); assign_map.apply(sig_b); @@ -347,7 +347,7 @@ static void handle_loops() } edges[id1].swap(edges[id3]); - module->connections.push_back(RTLIL::SigSig(signal_list[id3].bit, signal_list[id1].bit)); + module->connections_.push_back(RTLIL::SigSig(signal_list[id3].bit, signal_list[id1].bit)); dump_loop_graph(dot_f, dot_nr, edges, workpool, in_edges_count); } } @@ -470,7 +470,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std if (cell->type != "$_DFF_N_" && cell->type != "$_DFF_P_") continue; - std::pair key(cell->type == "$_DFF_P_", assign_map(cell->connections.at("\\C"))); + std::pair key(cell->type == "$_DFF_P_", assign_map(cell->connections_.at("\\C"))); if (++dff_counters[key] > best_dff_counter) { best_dff_counter = dff_counters[key]; clk_polarity = key.first; @@ -503,7 +503,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std } for (auto &cell_it : module->cells) - for (auto &port_it : cell_it.second->connections) + for (auto &port_it : cell_it.second->connections_) mark_port(port_it.second); handle_loops(); @@ -705,48 +705,48 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std cell_stats[RTLIL::unescape_id(c->type)]++; if (c->type == "\\ZERO" || c->type == "\\ONE") { RTLIL::SigSig conn; - conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].as_wire()->name)]); + conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\Y"].as_wire()->name)]); conn.second = RTLIL::SigSpec(c->type == "\\ZERO" ? 0 : 1, 1); - module->connections.push_back(conn); + module->connections_.push_back(conn); continue; } if (c->type == "\\BUF") { RTLIL::SigSig conn; - conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].as_wire()->name)]); - conn.second = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].as_wire()->name)]); - module->connections.push_back(conn); + conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\Y"].as_wire()->name)]); + conn.second = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\A"].as_wire()->name)]); + module->connections_.push_back(conn); continue; } if (c->type == "\\INV") { RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_INV_"); - cell->connections["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].as_wire()->name)]); - cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].as_wire()->name)]); + cell->connections_["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\A"].as_wire()->name)]); + cell->connections_["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\Y"].as_wire()->name)]); design->select(module, cell); continue; } if (c->type == "\\AND" || c->type == "\\OR" || c->type == "\\XOR") { RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_" + c->type.substr(1) + "_"); - cell->connections["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].as_wire()->name)]); - cell->connections["\\B"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\B"].as_wire()->name)]); - cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].as_wire()->name)]); + cell->connections_["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\A"].as_wire()->name)]); + cell->connections_["\\B"] = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\B"].as_wire()->name)]); + cell->connections_["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\Y"].as_wire()->name)]); design->select(module, cell); continue; } if (c->type == "\\MUX") { RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_MUX_"); - cell->connections["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].as_wire()->name)]); - cell->connections["\\B"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\B"].as_wire()->name)]); - cell->connections["\\S"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\S"].as_wire()->name)]); - cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].as_wire()->name)]); + cell->connections_["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\A"].as_wire()->name)]); + cell->connections_["\\B"] = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\B"].as_wire()->name)]); + cell->connections_["\\S"] = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\S"].as_wire()->name)]); + cell->connections_["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\Y"].as_wire()->name)]); design->select(module, cell); continue; } if (c->type == "\\DFF") { log_assert(clk_sig.size() == 1); RTLIL::Cell *cell = module->addCell(remap_name(c->name), clk_polarity ? "$_DFF_P_" : "$_DFF_N_"); - cell->connections["\\D"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\D"].as_wire()->name)]); - cell->connections["\\Q"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Q"].as_wire()->name)]); - cell->connections["\\C"] = clk_sig; + cell->connections_["\\D"] = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\D"].as_wire()->name)]); + cell->connections_["\\Q"] = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\Q"].as_wire()->name)]); + cell->connections_["\\C"] = clk_sig; design->select(module, cell); continue; } @@ -761,23 +761,23 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std cell_stats[RTLIL::unescape_id(c->type)]++; if (c->type == "\\_const0_" || c->type == "\\_const1_") { RTLIL::SigSig conn; - conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections.begin()->second.as_wire()->name)]); + conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections_.begin()->second.as_wire()->name)]); conn.second = RTLIL::SigSpec(c->type == "\\_const0_" ? 0 : 1, 1); - module->connections.push_back(conn); + module->connections_.push_back(conn); continue; } if (c->type == "\\_dff_") { log_assert(clk_sig.size() == 1); RTLIL::Cell *cell = module->addCell(remap_name(c->name), clk_polarity ? "$_DFF_P_" : "$_DFF_N_"); - cell->connections["\\D"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\D"].as_wire()->name)]); - cell->connections["\\Q"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Q"].as_wire()->name)]); - cell->connections["\\C"] = clk_sig; + cell->connections_["\\D"] = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\D"].as_wire()->name)]); + cell->connections_["\\Q"] = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\Q"].as_wire()->name)]); + cell->connections_["\\C"] = clk_sig; design->select(module, cell); continue; } RTLIL::Cell *cell = module->addCell(remap_name(c->name), c->type); cell->parameters = c->parameters; - for (auto &conn : c->connections) { + for (auto &conn : c->connections_) { RTLIL::SigSpec newsig; for (auto &c : conn.second.chunks()) { if (c.width == 0) @@ -785,18 +785,18 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std assert(c.width == 1); newsig.append(module->wires[remap_name(c.wire->name)]); } - cell->connections[conn.first] = newsig; + cell->connections_[conn.first] = newsig; } design->select(module, cell); } } - for (auto conn : mapped_mod->connections) { + for (auto conn : mapped_mod->connections_) { if (!conn.first.is_fully_const()) conn.first = RTLIL::SigSpec(module->wires[remap_name(conn.first.as_wire()->name)]); if (!conn.second.is_fully_const()) conn.second = RTLIL::SigSpec(module->wires[remap_name(conn.second.as_wire()->name)]); - module->connections.push_back(conn); + module->connections_.push_back(conn); } for (auto &it : cell_stats) @@ -816,7 +816,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std conn.second = si.bit; in_wires++; } - module->connections.push_back(conn); + module->connections_.push_back(conn); } log("ABC RESULTS: internal signals: %8d\n", int(signal_list.size()) - in_wires - out_wires); log("ABC RESULTS: input signals: %8d\n", in_wires); diff --git a/passes/abc/blifparse.cc b/passes/abc/blifparse.cc index e7feb1877..122f78454 100644 --- a/passes/abc/blifparse.cc +++ b/passes/abc/blifparse.cc @@ -128,8 +128,8 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name) } RTLIL::Cell *cell = module->addCell(NEW_ID, dff_name); - cell->connections["\\D"] = module->wires.at(RTLIL::escape_id(d)); - cell->connections["\\Q"] = module->wires.at(RTLIL::escape_id(q)); + cell->connections_["\\D"] = module->wires.at(RTLIL::escape_id(d)); + cell->connections_["\\Q"] = module->wires.at(RTLIL::escape_id(q)); continue; } @@ -148,7 +148,7 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name) *(q++) = 0; if (module->wires.count(RTLIL::escape_id(q)) == 0) module->addWire(RTLIL::escape_id(q)); - cell->connections[RTLIL::escape_id(p)] = module->wires.at(RTLIL::escape_id(q)); + cell->connections_[RTLIL::escape_id(p)] = module->wires.at(RTLIL::escape_id(q)); } continue; } @@ -199,15 +199,15 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name) finished_parsing_constval: if (state == RTLIL::State::Sa) state = RTLIL::State::S1; - module->connections.push_back(RTLIL::SigSig(output_sig, state)); + module->connections_.push_back(RTLIL::SigSig(output_sig, state)); goto continue_without_read; } RTLIL::Cell *cell = module->addCell(NEW_ID, "$lut"); cell->parameters["\\WIDTH"] = RTLIL::Const(input_sig.size()); cell->parameters["\\LUT"] = RTLIL::Const(RTLIL::State::Sx, 1 << input_sig.size()); - cell->connections["\\I"] = input_sig; - cell->connections["\\O"] = output_sig; + cell->connections_["\\I"] = input_sig; + cell->connections_["\\O"] = output_sig; lutptr = &cell->parameters.at("\\LUT"); lut_default_state = RTLIL::State::Sx; continue; diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc index acee4c46f..ce8ecc32d 100644 --- a/passes/cmds/add.cc +++ b/passes/cmds/add.cc @@ -75,10 +75,10 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n continue; if (mod->get_bool_attribute("\\blackbox")) continue; - if (it.second->connections.count(name) > 0) + if (it.second->connections_.count(name) > 0) continue; - it.second->connections[name] = wire; + it.second->connections_[name] = wire; log("Added connection %s to cell %s.%s (%s).\n", name.c_str(), module->name.c_str(), it.first.c_str(), it.second->type.c_str()); } } diff --git a/passes/cmds/connect.cc b/passes/cmds/connect.cc index dcd5fc96b..ea05026f3 100644 --- a/passes/cmds/connect.cc +++ b/passes/cmds/connect.cc @@ -30,11 +30,11 @@ static void unset_drivers(RTLIL::Design *design, RTLIL::Module *module, SigMap & RTLIL::Wire *dummy_wire = module->addWire(NEW_ID, sig.size()); for (auto &it : module->cells) - for (auto &port : it.second->connections) + for (auto &port : it.second->connections_) if (ct.cell_output(it.second->type, port.first)) sigmap(port.second).replace(sig, dummy_wire, &port.second); - for (auto &conn : module->connections) + for (auto &conn : module->connections_) sigmap(conn.first).replace(sig, dummy_wire, &conn.first); } @@ -123,7 +123,7 @@ struct ConnectPass : public Pass { SigMap sigmap; if (!flag_nomap) - for (auto &it : module->connections) { + for (auto &it : module->connections_) { std::vector lhs = it.first.to_sigbit_vector(); std::vector rhs = it.first.to_sigbit_vector(); for (size_t i = 0; i < lhs.size(); i++) @@ -148,7 +148,7 @@ struct ConnectPass : public Pass { if (!flag_nounset) unset_drivers(design, module, sigmap, sig_lhs); - module->connections.push_back(RTLIL::SigSig(sig_lhs, sig_rhs)); + module->connections_.push_back(RTLIL::SigSig(sig_lhs, sig_rhs)); } else if (!unset_expr.empty()) @@ -176,7 +176,7 @@ struct ConnectPass : public Pass { if (!RTLIL::SigSpec::parse_sel(sig, design, module, port_expr)) log_cmd_error("Failed to parse port expression `%s'.\n", port_expr.c_str()); - module->cells.at(RTLIL::escape_id(port_cell))->connections[RTLIL::escape_id(port_port)] = sigmap(sig); + module->cells.at(RTLIL::escape_id(port_cell))->connections_[RTLIL::escape_id(port_port)] = sigmap(sig); } else log_cmd_error("Expected -set, -unset, or -port.\n"); diff --git a/passes/cmds/connwrappers.cc b/passes/cmds/connwrappers.cc index 6cb2a892c..87ed3d856 100644 --- a/passes/cmds/connwrappers.cc +++ b/passes/cmds/connwrappers.cc @@ -74,7 +74,7 @@ struct ConnwrappersWorker if (!decl_celltypes.count(cell->type)) continue; - for (auto &conn : cell->connections) + for (auto &conn : cell->connections_) { std::pair key(cell->type, conn.first); @@ -109,7 +109,7 @@ struct ConnwrappersWorker if (!design->selected(module, cell)) continue; - for (auto &conn : cell->connections) + for (auto &conn : cell->connections_) { std::vector sigbits = sigmap(conn.second).to_sigbit_vector(); RTLIL::SigSpec old_sig; diff --git a/passes/cmds/scatter.cc b/passes/cmds/scatter.cc index d5976dcb0..0028f7ead 100644 --- a/passes/cmds/scatter.cc +++ b/passes/cmds/scatter.cc @@ -49,7 +49,7 @@ struct ScatterPass : public Pass { continue; for (auto &c : mod_it.second->cells) - for (auto &p : c.second->connections) + for (auto &p : c.second->connections_) { RTLIL::Wire *wire = new RTLIL::Wire; wire->name = NEW_ID; @@ -58,10 +58,10 @@ struct ScatterPass : public Pass { if (ct.cell_output(c.second->type, p.first)) { RTLIL::SigSig sigsig(p.second, wire); - mod_it.second->connections.push_back(sigsig); + mod_it.second->connections_.push_back(sigsig); } else { RTLIL::SigSig sigsig(wire, p.second); - mod_it.second->connections.push_back(sigsig); + mod_it.second->connections_.push_back(sigsig); } p.second = wire; diff --git a/passes/cmds/scc.cc b/passes/cmds/scc.cc index 49e79bd4d..40a2e48cb 100644 --- a/passes/cmds/scc.cc +++ b/passes/cmds/scc.cc @@ -132,7 +132,7 @@ struct SccWorker RTLIL::SigSpec inputSignals, outputSignals; - for (auto &conn : cell->connections) + for (auto &conn : cell->connections_) { bool isInput = true, isOutput = true; diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index 123483a3a..5d991d038 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -380,7 +380,7 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v if (lhs.selected_member(mod_it.first, it.first) && limits.count(it.first) == 0) selected_wires.insert(it.second); - for (auto &conn : mod->connections) + for (auto &conn : mod->connections_) { std::vector conn_lhs = conn.first.to_sigbit_vector(); std::vector conn_rhs = conn.second.to_sigbit_vector(); @@ -396,7 +396,7 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v } for (auto &cell : mod->cells) - for (auto &conn : cell.second->connections) + for (auto &conn : cell.second->connections_) { char last_mode = '-'; for (auto &rule : rules) { diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index 6c4bb16c0..e1005a270 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -135,7 +135,7 @@ struct SetundefPass : public Pass { CellTypes ct(design); for (auto &it : module->cells) - for (auto &conn : it.second->connections) + for (auto &conn : it.second->connections_) if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first)) undriven_signals.del(sigmap(conn.second)); @@ -144,7 +144,7 @@ struct SetundefPass : public Pass { RTLIL::SigSpec bits; for (int i = 0; i < c.width; i++) bits.append(worker.next_bit()); - module->connections.push_back(RTLIL::SigSig(c, bits)); + module->connections_.push_back(RTLIL::SigSig(c, bits)); } } diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index 8ff068999..29b83a9aa 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -344,7 +344,7 @@ struct ShowWorker std::vector in_ports, out_ports; - for (auto &conn : it.second->connections) { + for (auto &conn : it.second->connections_) { if (!ct.cell_output(it.second->type, conn.first)) in_ports.push_back(conn.first); else @@ -368,7 +368,7 @@ struct ShowWorker label_string += "}}"; std::string code; - for (auto &conn : it.second->connections) { + for (auto &conn : it.second->connections_) { code += gen_portbox(stringf("c%d:p%d", id2num(it.first), id2num(conn.first)), conn.second, ct.cell_output(it.second->type, conn.first)); } @@ -421,7 +421,7 @@ struct ShowWorker fprintf(f, "p%d [shape=box, style=rounded, label=\"PROC %s\\n%s\"];\n", pidx, findLabel(proc->name), proc_src.c_str()); } - for (auto &conn : module->connections) + for (auto &conn : module->connections_) { bool found_lhs_wire = false; for (auto &c : conn.first.chunks()) { @@ -516,7 +516,7 @@ struct ShowWorker log("Skipping blackbox module %s.\n", id2cstr(module->name)); continue; } else - if (module->cells.empty() && module->connections.empty() && module->processes.empty()) { + if (module->cells.empty() && module->connections_.empty() && module->processes.empty()) { log("Skipping empty module %s.\n", id2cstr(module->name)); continue; } else @@ -695,7 +695,7 @@ struct ShowPass : public Pass { for (auto &mod_it : design->modules) { if (mod_it.second->get_bool_attribute("\\blackbox")) continue; - if (mod_it.second->cells.empty() && mod_it.second->connections.empty()) + if (mod_it.second->cells.empty() && mod_it.second->connections_.empty()) continue; if (design->selected_module(mod_it.first)) modcount++; diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc index a470aed00..c8b3d0b0c 100644 --- a/passes/cmds/splice.cc +++ b/passes/cmds/splice.cc @@ -74,9 +74,9 @@ struct SpliceWorker cell->parameters["\\OFFSET"] = offset; cell->parameters["\\A_WIDTH"] = sig_a.size(); cell->parameters["\\Y_WIDTH"] = sig.size(); - cell->connections["\\A"] = sig_a; - cell->connections["\\Y"] = module->addWire(NEW_ID, sig.size()); - new_sig = cell->connections["\\Y"]; + cell->connections_["\\A"] = sig_a; + cell->connections_["\\Y"] = module->addWire(NEW_ID, sig.size()); + new_sig = cell->connections_["\\Y"]; } sliced_signals_cache[sig] = new_sig; @@ -130,10 +130,10 @@ struct SpliceWorker RTLIL::Cell *cell = module->addCell(NEW_ID, "$concat"); cell->parameters["\\A_WIDTH"] = new_sig.size(); cell->parameters["\\B_WIDTH"] = sig2.size(); - cell->connections["\\A"] = new_sig; - cell->connections["\\B"] = sig2; - cell->connections["\\Y"] = module->addWire(NEW_ID, new_sig.size() + sig2.size()); - new_sig = cell->connections["\\Y"]; + cell->connections_["\\A"] = new_sig; + cell->connections_["\\B"] = sig2; + cell->connections_["\\Y"] = module->addWire(NEW_ID, new_sig.size() + sig2.size()); + new_sig = cell->connections_["\\Y"]; } spliced_signals_cache[sig] = new_sig; @@ -159,7 +159,7 @@ struct SpliceWorker } for (auto &it : module->cells) - for (auto &conn : it.second->connections) + for (auto &conn : it.second->connections_) if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first)) { RTLIL::SigSpec sig = sigmap(conn.second); driven_chunks.insert(sig); @@ -182,7 +182,7 @@ struct SpliceWorker for (auto &it : module->cells) { if (!sel_by_wire && !design->selected(module, it.second)) continue; - for (auto &conn : it.second->connections) + for (auto &conn : it.second->connections_) if (ct.cell_input(it.second->type, conn.first)) { if (ports.size() > 0 && !ports.count(conn.first)) continue; @@ -232,7 +232,7 @@ struct SpliceWorker it.first->port_output = false; module->add(it.first); module->add(new_port); - module->connections.push_back(RTLIL::SigSig(new_port, it.second)); + module->connections_.push_back(RTLIL::SigSig(new_port, it.second)); } } }; diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc index c65b6a5f8..497d0a2a7 100644 --- a/passes/cmds/splitnets.cc +++ b/passes/cmds/splitnets.cc @@ -134,7 +134,7 @@ struct SplitnetsPass : public Pass { std::map> split_wires_at; for (auto &c : module->cells) - for (auto &p : c.second->connections) + for (auto &p : c.second->connections_) { if (!ct.cell_known(c.second->type)) continue; diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc index 2ba4c72b8..e59676599 100644 --- a/passes/fsm/fsm_detect.cc +++ b/passes/fsm/fsm_detect.cc @@ -52,8 +52,8 @@ static bool check_state_mux_tree(RTLIL::SigSpec old_sig, RTLIL::SigSpec sig, Sig for (auto &cellport : cellport_list) { if ((cellport.first->type != "$mux" && cellport.first->type != "$pmux" && cellport.first->type != "$safe_pmux") || cellport.second != "\\Y") return false; - RTLIL::SigSpec sig_a = assign_map(cellport.first->connections["\\A"]); - RTLIL::SigSpec sig_b = assign_map(cellport.first->connections["\\B"]); + RTLIL::SigSpec sig_a = assign_map(cellport.first->connections_["\\A"]); + RTLIL::SigSpec sig_b = assign_map(cellport.first->connections_["\\B"]); if (!check_state_mux_tree(old_sig, sig_a, recursion_monitor)) return false; for (int i = 0; i < sig_b.size(); i += sig_a.size()) @@ -80,14 +80,14 @@ static bool check_state_users(RTLIL::SigSpec sig) continue; if (cellport.second != "\\A" && cellport.second != "\\B") return false; - if (cell->connections.count("\\A") == 0 || cell->connections.count("\\B") == 0 || cell->connections.count("\\Y") == 0) + if (cell->connections_.count("\\A") == 0 || cell->connections_.count("\\B") == 0 || cell->connections_.count("\\Y") == 0) return false; - for (auto &port_it : cell->connections) + for (auto &port_it : cell->connections_) if (port_it.first != "\\A" && port_it.first != "\\B" && port_it.first != "\\Y") return false; - if (assign_map(cell->connections["\\A"]) == sig && cell->connections["\\B"].is_fully_const()) + if (assign_map(cell->connections_["\\A"]) == sig && cell->connections_["\\B"].is_fully_const()) continue; - if (assign_map(cell->connections["\\B"]) == sig && cell->connections["\\A"].is_fully_const()) + if (assign_map(cell->connections_["\\B"]) == sig && cell->connections_["\\A"].is_fully_const()) continue; return false; } @@ -109,8 +109,8 @@ static void detect_fsm(RTLIL::Wire *wire) continue; muxtree_cells.clear(); SigPool recursion_monitor; - RTLIL::SigSpec sig_q = assign_map(cellport.first->connections["\\Q"]); - RTLIL::SigSpec sig_d = assign_map(cellport.first->connections["\\D"]); + RTLIL::SigSpec sig_q = assign_map(cellport.first->connections_["\\Q"]); + RTLIL::SigSpec sig_d = assign_map(cellport.first->connections_["\\D"]); if (sig_q == RTLIL::SigSpec(wire) && check_state_mux_tree(sig_q, sig_d, recursion_monitor) && check_state_users(sig_q)) { log("Found FSM state register %s in module %s.\n", wire->name.c_str(), module->name.c_str()); wire->attributes["\\fsm_encoding"] = RTLIL::Const("auto"); @@ -160,7 +160,7 @@ struct FsmDetectPass : public Pass { sig2user.clear(); sig_at_port.clear(); for (auto &cell_it : module->cells) - for (auto &conn_it : cell_it.second->connections) { + for (auto &conn_it : cell_it.second->connections_) { if (ct.cell_output(cell_it.second->type, conn_it.first) || !ct.cell_known(cell_it.second->type)) { RTLIL::SigSpec sig = conn_it.second; assign_map.apply(sig); diff --git a/passes/fsm/fsm_expand.cc b/passes/fsm/fsm_expand.cc index f3b6c998d..431f086d2 100644 --- a/passes/fsm/fsm_expand.cc +++ b/passes/fsm/fsm_expand.cc @@ -43,34 +43,34 @@ struct FsmExpand bool is_cell_merge_candidate(RTLIL::Cell *cell) { if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux") - if (cell->connections.at("\\A").size() < 2) + if (cell->connections_.at("\\A").size() < 2) return true; RTLIL::SigSpec new_signals; - if (cell->connections.count("\\A") > 0) - new_signals.append(assign_map(cell->connections["\\A"])); - if (cell->connections.count("\\B") > 0) - new_signals.append(assign_map(cell->connections["\\B"])); - if (cell->connections.count("\\S") > 0) - new_signals.append(assign_map(cell->connections["\\S"])); - if (cell->connections.count("\\Y") > 0) - new_signals.append(assign_map(cell->connections["\\Y"])); + if (cell->connections_.count("\\A") > 0) + new_signals.append(assign_map(cell->connections_["\\A"])); + if (cell->connections_.count("\\B") > 0) + new_signals.append(assign_map(cell->connections_["\\B"])); + if (cell->connections_.count("\\S") > 0) + new_signals.append(assign_map(cell->connections_["\\S"])); + if (cell->connections_.count("\\Y") > 0) + new_signals.append(assign_map(cell->connections_["\\Y"])); new_signals.sort_and_unify(); new_signals.remove_const(); - new_signals.remove(assign_map(fsm_cell->connections["\\CTRL_IN"])); - new_signals.remove(assign_map(fsm_cell->connections["\\CTRL_OUT"])); + new_signals.remove(assign_map(fsm_cell->connections_["\\CTRL_IN"])); + new_signals.remove(assign_map(fsm_cell->connections_["\\CTRL_OUT"])); if (new_signals.size() > 3) return false; - if (cell->connections.count("\\Y") > 0) { - new_signals.append(assign_map(cell->connections["\\Y"])); + if (cell->connections_.count("\\Y") > 0) { + new_signals.append(assign_map(cell->connections_["\\Y"])); new_signals.sort_and_unify(); new_signals.remove_const(); - new_signals.remove(assign_map(fsm_cell->connections["\\CTRL_IN"])); - new_signals.remove(assign_map(fsm_cell->connections["\\CTRL_OUT"])); + new_signals.remove(assign_map(fsm_cell->connections_["\\CTRL_IN"])); + new_signals.remove(assign_map(fsm_cell->connections_["\\CTRL_OUT"])); } if (new_signals.size() > 2) @@ -83,10 +83,10 @@ struct FsmExpand { std::vector cell_list; - for (auto c : sig2driver.find(assign_map(fsm_cell->connections["\\CTRL_IN"]))) + for (auto c : sig2driver.find(assign_map(fsm_cell->connections_["\\CTRL_IN"]))) cell_list.push_back(c); - for (auto c : sig2user.find(assign_map(fsm_cell->connections["\\CTRL_OUT"]))) + for (auto c : sig2user.find(assign_map(fsm_cell->connections_["\\CTRL_OUT"]))) cell_list.push_back(c); current_set.clear(); @@ -94,7 +94,7 @@ struct FsmExpand { if (merged_set.count(c) > 0 || current_set.count(c) > 0 || no_candidate_set.count(c) > 0) continue; - for (auto &p : c->connections) { + for (auto &p : c->connections_) { if (p.first != "\\A" && p.first != "\\B" && p.first != "\\S" && p.first != "\\Y") goto next_cell; } @@ -135,7 +135,7 @@ struct FsmExpand RTLIL::SigSpec input_sig, output_sig; - for (auto &p : cell->connections) + for (auto &p : cell->connections_) if (ct.cell_output(cell->type, p.first)) output_sig.append(assign_map(p.second)); else @@ -148,12 +148,12 @@ struct FsmExpand for (int i = 0; i < (1 << input_sig.size()); i++) { RTLIL::Const in_val(i, input_sig.size()); RTLIL::SigSpec A, B, S; - if (cell->connections.count("\\A") > 0) - A = assign_map(cell->connections["\\A"]); - if (cell->connections.count("\\B") > 0) - B = assign_map(cell->connections["\\B"]); - if (cell->connections.count("\\S") > 0) - S = assign_map(cell->connections["\\S"]); + if (cell->connections_.count("\\A") > 0) + A = assign_map(cell->connections_["\\A"]); + if (cell->connections_.count("\\B") > 0) + B = assign_map(cell->connections_["\\B"]); + if (cell->connections_.count("\\S") > 0) + S = assign_map(cell->connections_["\\S"]); A.replace(input_sig, RTLIL::SigSpec(in_val)); B.replace(input_sig, RTLIL::SigSpec(in_val)); S.replace(input_sig, RTLIL::SigSpec(in_val)); @@ -167,10 +167,10 @@ struct FsmExpand fsm_data.copy_from_cell(fsm_cell); fsm_data.num_inputs += input_sig.size(); - fsm_cell->connections["\\CTRL_IN"].append(input_sig); + fsm_cell->connections_["\\CTRL_IN"].append(input_sig); fsm_data.num_outputs += output_sig.size(); - fsm_cell->connections["\\CTRL_OUT"].append(output_sig); + fsm_cell->connections_["\\CTRL_OUT"].append(output_sig); std::vector new_transition_table; for (auto &tr : fsm_data.transition_table) { @@ -204,7 +204,7 @@ struct FsmExpand for (auto &cell_it : module->cells) { RTLIL::Cell *c = cell_it.second; if (ct.cell_known(c->type) && design->selected(mod, c)) - for (auto &p : c->connections) { + for (auto &p : c->connections_) { if (ct.cell_output(c->type, p.first)) sig2driver.insert(assign_map(p.second), c); else diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index 1b5ea1bc0..b0e1c903b 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -58,9 +58,9 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL log(" unexpected cell type %s (%s) found in state selection tree.\n", cell->type.c_str(), cell->name.c_str()); return false; } - RTLIL::SigSpec sig_a = assign_map(cell->connections["\\A"]); - RTLIL::SigSpec sig_b = assign_map(cell->connections["\\B"]); - RTLIL::SigSpec sig_s = assign_map(cell->connections["\\S"]); + RTLIL::SigSpec sig_a = assign_map(cell->connections_["\\A"]); + RTLIL::SigSpec sig_b = assign_map(cell->connections_["\\B"]); + RTLIL::SigSpec sig_s = assign_map(cell->connections_["\\S"]); if (reset_state && RTLIL::SigSpec(*reset_state).is_fully_undef()) do { if (sig_a.is_fully_def()) @@ -183,12 +183,12 @@ static void extract_fsm(RTLIL::Wire *wire) if ((cell->type != "$dff" && cell->type != "$adff") || cellport.second != "\\Q") continue; log(" found %s cell for state register: %s\n", cell->type.c_str(), cell->name.c_str()); - RTLIL::SigSpec sig_q = assign_map(cell->connections["\\Q"]); - RTLIL::SigSpec sig_d = assign_map(cell->connections["\\D"]); - clk = cell->connections["\\CLK"]; + RTLIL::SigSpec sig_q = assign_map(cell->connections_["\\Q"]); + RTLIL::SigSpec sig_d = assign_map(cell->connections_["\\D"]); + clk = cell->connections_["\\CLK"]; clk_polarity = cell->parameters["\\CLK_POLARITY"].as_bool(); if (cell->type == "$adff") { - arst = cell->connections["\\ARST"]; + arst = cell->connections_["\\ARST"]; arst_polarity = cell->parameters["\\ARST_POLARITY"].as_bool(); reset_state = cell->parameters["\\ARST_VALUE"]; } @@ -224,9 +224,9 @@ static void extract_fsm(RTLIL::Wire *wire) sig2trigger.find(dff_out, cellport_list); for (auto &cellport : cellport_list) { RTLIL::Cell *cell = module->cells.at(cellport.first); - RTLIL::SigSpec sig_a = assign_map(cell->connections["\\A"]); - RTLIL::SigSpec sig_b = assign_map(cell->connections["\\B"]); - RTLIL::SigSpec sig_y = assign_map(cell->connections["\\Y"]); + RTLIL::SigSpec sig_a = assign_map(cell->connections_["\\A"]); + RTLIL::SigSpec sig_b = assign_map(cell->connections_["\\B"]); + RTLIL::SigSpec sig_y = assign_map(cell->connections_["\\Y"]); if (cellport.second == "\\A" && !sig_b.is_fully_const()) continue; if (cellport.second == "\\B" && !sig_a.is_fully_const()) @@ -271,12 +271,12 @@ static void extract_fsm(RTLIL::Wire *wire) // create fsm cell RTLIL::Cell *fsm_cell = module->addCell(stringf("$fsm$%s$%d", wire->name.c_str(), RTLIL::autoidx++), "$fsm"); - fsm_cell->connections["\\CLK"] = clk; - fsm_cell->connections["\\ARST"] = arst; + fsm_cell->connections_["\\CLK"] = clk; + fsm_cell->connections_["\\ARST"] = arst; fsm_cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity ? 1 : 0, 1); fsm_cell->parameters["\\ARST_POLARITY"] = RTLIL::Const(arst_polarity ? 1 : 0, 1); - fsm_cell->connections["\\CTRL_IN"] = ctrl_in; - fsm_cell->connections["\\CTRL_OUT"] = ctrl_out; + fsm_cell->connections_["\\CTRL_IN"] = ctrl_in; + fsm_cell->connections_["\\CTRL_OUT"] = ctrl_out; fsm_cell->parameters["\\NAME"] = RTLIL::Const(wire->name); fsm_cell->attributes = wire->attributes; fsm_data.copy_to_cell(fsm_cell); @@ -294,13 +294,13 @@ static void extract_fsm(RTLIL::Wire *wire) sig2driver.find(ctrl_out, cellport_list); for (auto &cellport : cellport_list) { RTLIL::Cell *cell = module->cells.at(cellport.first); - RTLIL::SigSpec port_sig = assign_map(cell->connections[cellport.second]); + RTLIL::SigSpec port_sig = assign_map(cell->connections_[cellport.second]); RTLIL::SigSpec unconn_sig = port_sig.extract(ctrl_out); RTLIL::Wire *unconn_wire = new RTLIL::Wire; unconn_wire->name = stringf("$fsm_unconnect$%s$%d", log_signal(unconn_sig), RTLIL::autoidx++); unconn_wire->width = unconn_sig.size(); module->wires[unconn_wire->name] = unconn_wire; - port_sig.replace(unconn_sig, RTLIL::SigSpec(unconn_wire), &cell->connections[cellport.second]); + port_sig.replace(unconn_sig, RTLIL::SigSpec(unconn_wire), &cell->connections_[cellport.second]); } } @@ -344,14 +344,14 @@ struct FsmExtractPass : public Pass { sig2driver.clear(); sig2trigger.clear(); for (auto &cell_it : module->cells) - for (auto &conn_it : cell_it.second->connections) { + for (auto &conn_it : cell_it.second->connections_) { if (ct.cell_output(cell_it.second->type, conn_it.first) || !ct.cell_known(cell_it.second->type)) { RTLIL::SigSpec sig = conn_it.second; assign_map.apply(sig); sig2driver.insert(sig, sig2driver_entry_t(cell_it.first, conn_it.first)); } - if (ct.cell_input(cell_it.second->type, conn_it.first) && cell_it.second->connections.count("\\Y") > 0 && - cell_it.second->connections["\\Y"].size() == 1 && (conn_it.first == "\\A" || conn_it.first == "\\B")) { + if (ct.cell_input(cell_it.second->type, conn_it.first) && cell_it.second->connections_.count("\\Y") > 0 && + cell_it.second->connections_["\\Y"].size() == 1 && (conn_it.first == "\\A" || conn_it.first == "\\B")) { RTLIL::SigSpec sig = conn_it.second; assign_map.apply(sig); sig2trigger.insert(sig, sig2driver_entry_t(cell_it.first, conn_it.first)); diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc index 78248eb6d..cf482d6df 100644 --- a/passes/fsm/fsm_map.cc +++ b/passes/fsm/fsm_map.cc @@ -58,9 +58,9 @@ static void implement_pattern_cache(RTLIL::Module *module, std::mapaddCell(NEW_ID, "$eq"); - eq_cell->connections["\\A"] = eq_sig_a; - eq_cell->connections["\\B"] = eq_sig_b; - eq_cell->connections["\\Y"] = RTLIL::SigSpec(eq_wire); + eq_cell->connections_["\\A"] = eq_sig_a; + eq_cell->connections_["\\B"] = eq_sig_b; + eq_cell->connections_["\\Y"] = RTLIL::SigSpec(eq_wire); eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false); eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false); eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(eq_sig_a.size()); @@ -80,8 +80,8 @@ static void implement_pattern_cache(RTLIL::Module *module, std::mapaddCell(NEW_ID, "$reduce_or"); - or_cell->connections["\\A"] = or_sig; - or_cell->connections["\\Y"] = RTLIL::SigSpec(or_wire); + or_cell->connections_["\\A"] = or_sig; + or_cell->connections_["\\Y"] = RTLIL::SigSpec(or_wire); or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false); or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(or_sig.size()); or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); @@ -96,9 +96,9 @@ static void implement_pattern_cache(RTLIL::Module *module, std::mapaddCell(NEW_ID, "$and"); - and_cell->connections["\\A"] = and_sig.extract(0, 1); - and_cell->connections["\\B"] = and_sig.extract(1, 1); - and_cell->connections["\\Y"] = RTLIL::SigSpec(and_wire); + and_cell->connections_["\\A"] = and_sig.extract(0, 1); + and_cell->connections_["\\B"] = and_sig.extract(1, 1); + and_cell->connections_["\\Y"] = RTLIL::SigSpec(and_wire); and_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false); and_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false); and_cell->parameters["\\A_WIDTH"] = RTLIL::Const(1); @@ -119,15 +119,15 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map 1) { RTLIL::Cell *or_cell = module->addCell(NEW_ID, "$reduce_or"); - or_cell->connections["\\A"] = cases_vector; - or_cell->connections["\\Y"] = output; + or_cell->connections_["\\A"] = cases_vector; + or_cell->connections_["\\Y"] = output; or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false); or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cases_vector.size()); or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); } else if (cases_vector.size() == 1) { - module->connections.push_back(RTLIL::SigSig(output, cases_vector)); + module->connections_.push_back(RTLIL::SigSig(output, cases_vector)); } else { - module->connections.push_back(RTLIL::SigSig(output, RTLIL::SigSpec(0, 1))); + module->connections_.push_back(RTLIL::SigSig(output, RTLIL::SigSpec(0, 1))); } } @@ -138,8 +138,8 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) FsmData fsm_data; fsm_data.copy_from_cell(fsm_cell); - RTLIL::SigSpec ctrl_in = fsm_cell->connections["\\CTRL_IN"]; - RTLIL::SigSpec ctrl_out = fsm_cell->connections["\\CTRL_OUT"]; + RTLIL::SigSpec ctrl_in = fsm_cell->connections_["\\CTRL_IN"]; + RTLIL::SigSpec ctrl_out = fsm_cell->connections_["\\CTRL_OUT"]; // create state register @@ -153,7 +153,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) RTLIL::Wire *next_state_wire = module->addWire(NEW_ID, fsm_data.state_bits); RTLIL::Cell *state_dff = module->addCell(NEW_ID, ""); - if (fsm_cell->connections["\\ARST"].is_fully_const()) { + if (fsm_cell->connections_["\\ARST"].is_fully_const()) { state_dff->type = "$dff"; } else { state_dff->type = "$adff"; @@ -162,13 +162,13 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) for (auto &bit : state_dff->parameters["\\ARST_VALUE"].bits) if (bit != RTLIL::State::S1) bit = RTLIL::State::S0; - state_dff->connections["\\ARST"] = fsm_cell->connections["\\ARST"]; + state_dff->connections_["\\ARST"] = fsm_cell->connections_["\\ARST"]; } state_dff->parameters["\\WIDTH"] = RTLIL::Const(fsm_data.state_bits); state_dff->parameters["\\CLK_POLARITY"] = fsm_cell->parameters["\\CLK_POLARITY"]; - state_dff->connections["\\CLK"] = fsm_cell->connections["\\CLK"]; - state_dff->connections["\\D"] = RTLIL::SigSpec(next_state_wire); - state_dff->connections["\\Q"] = RTLIL::SigSpec(state_wire); + state_dff->connections_["\\CLK"] = fsm_cell->connections_["\\CLK"]; + state_dff->connections_["\\D"] = RTLIL::SigSpec(next_state_wire); + state_dff->connections_["\\Q"] = RTLIL::SigSpec(state_wire); // decode state register @@ -189,16 +189,16 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) if (sig_b == RTLIL::SigSpec(RTLIL::State::S1)) { - module->connections.push_back(RTLIL::SigSig(RTLIL::SigSpec(state_onehot, i), sig_a)); + module->connections_.push_back(RTLIL::SigSig(RTLIL::SigSpec(state_onehot, i), sig_a)); } else { encoding_is_onehot = false; RTLIL::Cell *eq_cell = module->addCell(NEW_ID, "$eq"); - eq_cell->connections["\\A"] = sig_a; - eq_cell->connections["\\B"] = sig_b; - eq_cell->connections["\\Y"] = RTLIL::SigSpec(state_onehot, i); + eq_cell->connections_["\\A"] = sig_a; + eq_cell->connections_["\\B"] = sig_b; + eq_cell->connections_["\\Y"] = RTLIL::SigSpec(state_onehot, i); eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false); eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false); eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_a.size()); @@ -245,7 +245,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) next_state_sig.replace(bit_idx, RTLIL::SigSpec(next_state_onehot, i)); } log_assert(!next_state_sig.has_marked_bits()); - module->connections.push_back(RTLIL::SigSig(next_state_wire, next_state_sig)); + module->connections_.push_back(RTLIL::SigSig(next_state_wire, next_state_sig)); } else { @@ -265,10 +265,10 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) } RTLIL::Cell *mux_cell = module->addCell(NEW_ID, "$safe_pmux"); - mux_cell->connections["\\A"] = sig_a; - mux_cell->connections["\\B"] = sig_b; - mux_cell->connections["\\S"] = sig_s; - mux_cell->connections["\\Y"] = RTLIL::SigSpec(next_state_wire); + mux_cell->connections_["\\A"] = sig_a; + mux_cell->connections_["\\B"] = sig_b; + mux_cell->connections_["\\S"] = sig_s; + mux_cell->connections_["\\Y"] = RTLIL::SigSpec(next_state_wire); mux_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_a.size()); mux_cell->parameters["\\S_WIDTH"] = RTLIL::Const(sig_s.size()); } diff --git a/passes/fsm/fsm_opt.cc b/passes/fsm/fsm_opt.cc index efa61245a..3fde534da 100644 --- a/passes/fsm/fsm_opt.cc +++ b/passes/fsm/fsm_opt.cc @@ -52,7 +52,7 @@ struct FsmOpt void opt_const_and_unused_inputs() { - RTLIL::SigSpec ctrl_in = cell->connections["\\CTRL_IN"]; + RTLIL::SigSpec ctrl_in = cell->connections_["\\CTRL_IN"]; std::vector ctrl_in_used(ctrl_in.size()); std::vector new_transition_table; @@ -73,13 +73,13 @@ struct FsmOpt for (int i = int(ctrl_in_used.size())-1; i >= 0; i--) { if (!ctrl_in_used[i]) { - log(" Removing unused input signal %s.\n", log_signal(cell->connections["\\CTRL_IN"].extract(i, 1))); + log(" Removing unused input signal %s.\n", log_signal(cell->connections_["\\CTRL_IN"].extract(i, 1))); for (auto &tr : new_transition_table) { RTLIL::SigSpec tmp(tr.ctrl_in); tmp.remove(i, 1); tr.ctrl_in = tmp.as_const(); } - cell->connections["\\CTRL_IN"].remove(i, 1); + cell->connections_["\\CTRL_IN"].remove(i, 1); fsm_data.num_inputs--; } } @@ -91,10 +91,10 @@ struct FsmOpt void opt_unused_outputs() { for (int i = 0; i < fsm_data.num_outputs; i++) { - RTLIL::SigSpec sig = cell->connections["\\CTRL_OUT"].extract(i, 1); + RTLIL::SigSpec sig = cell->connections_["\\CTRL_OUT"].extract(i, 1); if (signal_is_unused(sig)) { log(" Removing unused output signal %s.\n", log_signal(sig)); - cell->connections["\\CTRL_OUT"].remove(i, 1); + cell->connections_["\\CTRL_OUT"].remove(i, 1); for (auto &tr : fsm_data.transition_table) { RTLIL::SigSpec tmp(tr.ctrl_out); tmp.remove(i, 1); @@ -108,7 +108,7 @@ struct FsmOpt void opt_alias_inputs() { - RTLIL::SigSpec &ctrl_in = cell->connections["\\CTRL_IN"]; + RTLIL::SigSpec &ctrl_in = cell->connections_["\\CTRL_IN"]; for (int i = 0; i < ctrl_in.size(); i++) for (int j = i+1; j < ctrl_in.size(); j++) @@ -145,8 +145,8 @@ struct FsmOpt void opt_feedback_inputs() { - RTLIL::SigSpec &ctrl_in = cell->connections["\\CTRL_IN"]; - RTLIL::SigSpec &ctrl_out = cell->connections["\\CTRL_OUT"]; + RTLIL::SigSpec &ctrl_in = cell->connections_["\\CTRL_IN"]; + RTLIL::SigSpec &ctrl_out = cell->connections_["\\CTRL_OUT"]; for (int j = 0; j < ctrl_out.size(); j++) for (int i = 0; i < ctrl_in.size(); i++) diff --git a/passes/fsm/fsmdata.h b/passes/fsm/fsmdata.h index ae9569ed7..a336d23f7 100644 --- a/passes/fsm/fsmdata.h +++ b/passes/fsm/fsmdata.h @@ -141,13 +141,13 @@ struct FsmData log("\n"); log(" Input signals:\n"); - RTLIL::SigSpec sig_in = cell->connections["\\CTRL_IN"]; + RTLIL::SigSpec sig_in = cell->connections_["\\CTRL_IN"]; for (int i = 0; i < SIZE(sig_in); i++) log(" %3d: %s\n", i, log_signal(sig_in[i])); log("\n"); log(" Output signals:\n"); - RTLIL::SigSpec sig_out = cell->connections["\\CTRL_OUT"]; + RTLIL::SigSpec sig_out = cell->connections_["\\CTRL_OUT"]; for (int i = 0; i < SIZE(sig_out); i++) log(" %3d: %s\n", i, log_signal(sig_out[i])); diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 90f377e0d..4306c29eb 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -58,7 +58,7 @@ static void generate(RTLIL::Design *design, const std::vector &cell for (auto i1 : design->modules) for (auto i2 : i1.second->cells) if (i2.second->type == celltype) { - for (auto &conn : i2.second->connections) { + for (auto &conn : i2.second->connections_) { if (conn.first[0] != '$') portnames.insert(conn.first); portwidths[conn.first] = std::max(portwidths[conn.first], conn.second.size()); @@ -219,7 +219,7 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla RTLIL::Module *mod = design->modules[cell->type]; - for (auto &conn : cell->connections) { + for (auto &conn : cell->connections_) { int conn_size = conn.second.size(); std::string portname = conn.first; if (portname.substr(0, 1) == "$") { @@ -486,7 +486,7 @@ struct HierarchyPass : public Pass { RTLIL::Cell *cell = cell_it.second; if (design->modules.count(cell->type) == 0) continue; - for (auto &conn : cell->connections) + for (auto &conn : cell->connections_) if (conn.first[0] == '$' && '0' <= conn.first[1] && conn.first[1] <= '9') { pos_mods.insert(design->modules.at(cell->type)); pos_work.push_back(std::pair(mod_it.second, cell)); @@ -507,7 +507,7 @@ struct HierarchyPass : public Pass { log("Mapping positional arguments of cell %s.%s (%s).\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); std::map new_connections; - for (auto &conn : cell->connections) + for (auto &conn : cell->connections_) if (conn.first[0] == '$' && '0' <= conn.first[1] && conn.first[1] <= '9') { int id = atoi(conn.first.c_str()+1); std::pair key(design->modules.at(cell->type), id); @@ -519,7 +519,7 @@ struct HierarchyPass : public Pass { new_connections[pos_map.at(key)] = conn.second; } else new_connections[conn.first] = conn.second; - cell->connections = new_connections; + cell->connections_ = new_connections; } } diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index be580ca04..df5fd8e37 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -79,11 +79,11 @@ struct SubmodWorker wire_flags.clear(); for (RTLIL::Cell *cell : submod.cells) { if (ct.cell_known(cell->type)) { - for (auto &conn : cell->connections) + for (auto &conn : cell->connections_) flag_signal(conn.second, true, ct.cell_output(cell->type, conn.first), ct.cell_input(cell->type, conn.first), false, false); } else { log("WARNING: Port directions for cell %s (%s) are unknown. Assuming inout for all ports.\n", cell->name.c_str(), cell->type.c_str()); - for (auto &conn : cell->connections) + for (auto &conn : cell->connections_) flag_signal(conn.second, true, true, true, false, false); } } @@ -92,11 +92,11 @@ struct SubmodWorker if (submod.cells.count(cell) > 0) continue; if (ct.cell_known(cell->type)) { - for (auto &conn : cell->connections) + for (auto &conn : cell->connections_) flag_signal(conn.second, false, false, false, ct.cell_output(cell->type, conn.first), ct.cell_input(cell->type, conn.first)); } else { flag_found_something = false; - for (auto &conn : cell->connections) + for (auto &conn : cell->connections_) flag_signal(conn.second, false, false, false, true, true); if (flag_found_something) log("WARNING: Port directions for cell %s (%s) are unknown. Assuming inout for all ports.\n", cell->name.c_str(), cell->type.c_str()); @@ -163,7 +163,7 @@ struct SubmodWorker for (RTLIL::Cell *cell : submod.cells) { RTLIL::Cell *new_cell = new_mod->addCell(cell->name, cell); - for (auto &conn : new_cell->connections) + for (auto &conn : new_cell->connections_) for (auto &bit : conn.second) if (bit.wire != NULL) { assert(wire_flags.count(bit.wire) > 0); @@ -180,7 +180,7 @@ struct SubmodWorker RTLIL::Wire *old_wire = it.first; RTLIL::Wire *new_wire = it.second.new_wire; if (new_wire->port_id > 0) - new_cell->connections[new_wire->name] = RTLIL::SigSpec(old_wire); + new_cell->connections_[new_wire->name] = RTLIL::SigSpec(old_wire); } } diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc index 116b704e3..b4242f250 100644 --- a/passes/memory/memory_collect.cc +++ b/passes/memory/memory_collect.cc @@ -76,12 +76,12 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) wr_ports++; del_cells.push_back(cell); - RTLIL::SigSpec clk = cell->connections["\\CLK"]; + RTLIL::SigSpec clk = cell->connections_["\\CLK"]; RTLIL::SigSpec clk_enable = RTLIL::SigSpec(cell->parameters["\\CLK_ENABLE"]); RTLIL::SigSpec clk_polarity = RTLIL::SigSpec(cell->parameters["\\CLK_POLARITY"]); - RTLIL::SigSpec addr = cell->connections["\\ADDR"]; - RTLIL::SigSpec data = cell->connections["\\DATA"]; - RTLIL::SigSpec en = cell->connections["\\EN"]; + RTLIL::SigSpec addr = cell->connections_["\\ADDR"]; + RTLIL::SigSpec data = cell->connections_["\\DATA"]; + RTLIL::SigSpec en = cell->connections_["\\EN"]; clk.extend(1, false); clk_enable.extend(1, false); @@ -103,12 +103,12 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) rd_ports++; del_cells.push_back(cell); - RTLIL::SigSpec clk = cell->connections["\\CLK"]; + RTLIL::SigSpec clk = cell->connections_["\\CLK"]; RTLIL::SigSpec clk_enable = RTLIL::SigSpec(cell->parameters["\\CLK_ENABLE"]); RTLIL::SigSpec clk_polarity = RTLIL::SigSpec(cell->parameters["\\CLK_POLARITY"]); RTLIL::SigSpec transparent = RTLIL::SigSpec(cell->parameters["\\TRANSPARENT"]); - RTLIL::SigSpec addr = cell->connections["\\ADDR"]; - RTLIL::SigSpec data = cell->connections["\\DATA"]; + RTLIL::SigSpec addr = cell->connections_["\\ADDR"]; + RTLIL::SigSpec data = cell->connections_["\\DATA"]; clk.extend(1, false); clk_enable.extend(1, false); @@ -147,10 +147,10 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) mem->parameters["\\WR_CLK_ENABLE"] = wr_ports ? sig_wr_clk_enable.as_const() : RTLIL::Const(0, 0); mem->parameters["\\WR_CLK_POLARITY"] = wr_ports ? sig_wr_clk_polarity.as_const() : RTLIL::Const(0, 0); - mem->connections["\\WR_CLK"] = sig_wr_clk; - mem->connections["\\WR_ADDR"] = sig_wr_addr; - mem->connections["\\WR_DATA"] = sig_wr_data; - mem->connections["\\WR_EN"] = sig_wr_en; + mem->connections_["\\WR_CLK"] = sig_wr_clk; + mem->connections_["\\WR_ADDR"] = sig_wr_addr; + mem->connections_["\\WR_DATA"] = sig_wr_data; + mem->connections_["\\WR_EN"] = sig_wr_en; assert(sig_rd_clk.size() == rd_ports); assert(sig_rd_clk_enable.size() == rd_ports && sig_rd_clk_enable.is_fully_const()); @@ -163,9 +163,9 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) mem->parameters["\\RD_CLK_POLARITY"] = rd_ports ? sig_rd_clk_polarity.as_const() : RTLIL::Const(0, 0); mem->parameters["\\RD_TRANSPARENT"] = rd_ports ? sig_rd_transparent.as_const() : RTLIL::Const(0, 0); - mem->connections["\\RD_CLK"] = sig_rd_clk; - mem->connections["\\RD_ADDR"] = sig_rd_addr; - mem->connections["\\RD_DATA"] = sig_rd_data; + mem->connections_["\\RD_CLK"] = sig_rd_clk; + mem->connections_["\\RD_ADDR"] = sig_rd_addr; + mem->connections_["\\RD_DATA"] = sig_rd_data; for (auto c : del_cells) module->remove(c); diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index 56915776e..63f7d0527 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -25,7 +25,7 @@ static void normalize_sig(RTLIL::Module *module, RTLIL::SigSpec &sig) { - for (auto &conn : module->connections) + for (auto &conn : module->connections_) sig.replace(conn.first, conn.second); } @@ -46,21 +46,21 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI continue; if (clk != RTLIL::SigSpec(RTLIL::State::Sx)) { - if (cell->connections["\\CLK"] != clk) + if (cell->connections_["\\CLK"] != clk) continue; if (cell->parameters["\\CLK_POLARITY"].as_bool() != clk_polarity) continue; } - RTLIL::SigSpec q_norm = cell->connections[after ? "\\D" : "\\Q"]; + RTLIL::SigSpec q_norm = cell->connections_[after ? "\\D" : "\\Q"]; normalize_sig(module, q_norm); - RTLIL::SigSpec d = q_norm.extract(bit, &cell->connections[after ? "\\Q" : "\\D"]); + RTLIL::SigSpec d = q_norm.extract(bit, &cell->connections_[after ? "\\Q" : "\\D"]); if (d.size() != 1) continue; bit = d; - clk = cell->connections["\\CLK"]; + clk = cell->connections_["\\CLK"]; clk_polarity = cell->parameters["\\CLK_POLARITY"].as_bool(); goto replaced_this_bit; } @@ -79,29 +79,29 @@ static void handle_wr_cell(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::SigSpec clk = RTLIL::SigSpec(RTLIL::State::Sx); bool clk_polarity = 0; - RTLIL::SigSpec sig_addr = cell->connections["\\ADDR"]; + RTLIL::SigSpec sig_addr = cell->connections_["\\ADDR"]; if (!find_sig_before_dff(module, sig_addr, clk, clk_polarity)) { log("no (compatible) $dff for address input found.\n"); return; } - RTLIL::SigSpec sig_data = cell->connections["\\DATA"]; + RTLIL::SigSpec sig_data = cell->connections_["\\DATA"]; if (!find_sig_before_dff(module, sig_data, clk, clk_polarity)) { log("no (compatible) $dff for data input found.\n"); return; } - RTLIL::SigSpec sig_en = cell->connections["\\EN"]; + RTLIL::SigSpec sig_en = cell->connections_["\\EN"]; if (!find_sig_before_dff(module, sig_en, clk, clk_polarity)) { log("no (compatible) $dff for enable input found.\n"); return; } if (clk != RTLIL::SigSpec(RTLIL::State::Sx)) { - cell->connections["\\CLK"] = clk; - cell->connections["\\ADDR"] = sig_addr; - cell->connections["\\DATA"] = sig_data; - cell->connections["\\EN"] = sig_en; + cell->connections_["\\CLK"] = clk; + cell->connections_["\\ADDR"] = sig_addr; + cell->connections_["\\DATA"] = sig_data; + cell->connections_["\\EN"] = sig_en; cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1); cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity); log("merged $dff to cell.\n"); @@ -128,7 +128,7 @@ static void disconnect_dff(RTLIL::Module *module, RTLIL::SigSpec sig) for (auto &cell_it : module->cells) { RTLIL::Cell *cell = cell_it.second; if (cell->type == "$dff") - cell->connections["\\Q"].replace(sig, newsig); + cell->connections_["\\Q"].replace(sig, newsig); } } @@ -139,13 +139,13 @@ static void handle_rd_cell(RTLIL::Module *module, RTLIL::Cell *cell) bool clk_polarity = 0; RTLIL::SigSpec clk_data = RTLIL::SigSpec(RTLIL::State::Sx); - RTLIL::SigSpec sig_data = cell->connections["\\DATA"]; + RTLIL::SigSpec sig_data = cell->connections_["\\DATA"]; if (find_sig_before_dff(module, sig_data, clk_data, clk_polarity, true) && clk_data != RTLIL::SigSpec(RTLIL::State::Sx)) { disconnect_dff(module, sig_data); - cell->connections["\\CLK"] = clk_data; - cell->connections["\\DATA"] = sig_data; + cell->connections_["\\CLK"] = clk_data; + cell->connections_["\\DATA"] = sig_data; cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1); cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity); cell->parameters["\\TRANSPARENT"] = RTLIL::Const(0); @@ -154,12 +154,12 @@ static void handle_rd_cell(RTLIL::Module *module, RTLIL::Cell *cell) } RTLIL::SigSpec clk_addr = RTLIL::SigSpec(RTLIL::State::Sx); - RTLIL::SigSpec sig_addr = cell->connections["\\ADDR"]; + RTLIL::SigSpec sig_addr = cell->connections_["\\ADDR"]; if (find_sig_before_dff(module, sig_addr, clk_addr, clk_polarity) && clk_addr != RTLIL::SigSpec(RTLIL::State::Sx)) { - cell->connections["\\CLK"] = clk_addr; - cell->connections["\\ADDR"] = sig_addr; + cell->connections_["\\CLK"] = clk_addr; + cell->connections_["\\ADDR"] = sig_addr; cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1); cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity); cell->parameters["\\TRANSPARENT"] = RTLIL::Const(1); diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index b5f0520a4..a626b5aff 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -62,20 +62,20 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) } // all write ports must share the same clock - RTLIL::SigSpec clocks = cell->connections["\\WR_CLK"]; + RTLIL::SigSpec clocks = cell->connections_["\\WR_CLK"]; RTLIL::Const clocks_pol = cell->parameters["\\WR_CLK_POLARITY"]; RTLIL::Const clocks_en = cell->parameters["\\WR_CLK_ENABLE"]; RTLIL::SigSpec refclock; RTLIL::State refclock_pol = RTLIL::State::Sx; for (int i = 0; i < clocks.size(); i++) { - RTLIL::SigSpec wr_en = cell->connections["\\WR_EN"].extract(i * mem_width, mem_width); + RTLIL::SigSpec wr_en = cell->connections_["\\WR_EN"].extract(i * mem_width, mem_width); if (wr_en.is_fully_const() && !wr_en.as_bool()) { static_ports.insert(i); continue; } if (clocks_en.bits[i] != RTLIL::State::S1) { - RTLIL::SigSpec wr_addr = cell->connections["\\WR_ADDR"].extract(i*mem_abits, mem_abits); - RTLIL::SigSpec wr_data = cell->connections["\\WR_DATA"].extract(i*mem_width, mem_width); + RTLIL::SigSpec wr_addr = cell->connections_["\\WR_ADDR"].extract(i*mem_abits, mem_abits); + RTLIL::SigSpec wr_data = cell->connections_["\\WR_DATA"].extract(i*mem_width, mem_width); if (wr_addr.is_fully_const()) { // FIXME: Actually we should check for wr_en.is_fully_const() also and // create a $adff cell with this ports wr_en input as reset pin when wr_en @@ -120,10 +120,10 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"]; if (clocks_pol.bits.size() > 0) { c->parameters["\\CLK_POLARITY"] = RTLIL::Const(clocks_pol.bits[0]); - c->connections["\\CLK"] = clocks.extract(0, 1); + c->connections_["\\CLK"] = clocks.extract(0, 1); } else { c->parameters["\\CLK_POLARITY"] = RTLIL::Const(RTLIL::State::S1); - c->connections["\\CLK"] = RTLIL::SigSpec(RTLIL::State::S0); + c->connections_["\\CLK"] = RTLIL::SigSpec(RTLIL::State::S0); } RTLIL::Wire *w_in = new RTLIL::Wire; @@ -131,7 +131,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) w_in->width = mem_width; module->wires[w_in->name] = w_in; data_reg_in.push_back(RTLIL::SigSpec(w_in)); - c->connections["\\D"] = data_reg_in.back(); + c->connections_["\\D"] = data_reg_in.back(); RTLIL::Wire *w_out = new RTLIL::Wire; w_out->name = stringf("%s[%d]", cell->parameters["\\MEMID"].decode_string().c_str(), i); @@ -141,7 +141,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) w_out->start_offset = mem_offset; module->wires[w_out->name] = w_out; data_reg_out.push_back(RTLIL::SigSpec(w_out)); - c->connections["\\Q"] = data_reg_out.back(); + c->connections_["\\Q"] = data_reg_out.back(); } } @@ -151,10 +151,10 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) for (int i = 0; i < cell->parameters["\\RD_PORTS"].as_int(); i++) { - RTLIL::SigSpec rd_addr = cell->connections["\\RD_ADDR"].extract(i*mem_abits, mem_abits); + RTLIL::SigSpec rd_addr = cell->connections_["\\RD_ADDR"].extract(i*mem_abits, mem_abits); std::vector rd_signals; - rd_signals.push_back(cell->connections["\\RD_DATA"].extract(i*mem_width, mem_width)); + rd_signals.push_back(cell->connections_["\\RD_DATA"].extract(i*mem_width, mem_width)); if (cell->parameters["\\RD_CLK_ENABLE"].bits[i] == RTLIL::State::S1) { @@ -163,8 +163,8 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdreg", i), "$dff"); c->parameters["\\WIDTH"] = RTLIL::Const(mem_abits); c->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]); - c->connections["\\CLK"] = cell->connections["\\RD_CLK"].extract(i, 1); - c->connections["\\D"] = rd_addr; + c->connections_["\\CLK"] = cell->connections_["\\RD_CLK"].extract(i, 1); + c->connections_["\\D"] = rd_addr; count_dff++; RTLIL::Wire *w = new RTLIL::Wire; @@ -172,7 +172,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) w->width = mem_abits; module->wires[w->name] = w; - c->connections["\\Q"] = RTLIL::SigSpec(w); + c->connections_["\\Q"] = RTLIL::SigSpec(w); rd_addr = RTLIL::SigSpec(w); } else @@ -180,8 +180,8 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdreg", i), "$dff"); c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"]; c->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]); - c->connections["\\CLK"] = cell->connections["\\RD_CLK"].extract(i, 1); - c->connections["\\Q"] = rd_signals.back(); + c->connections_["\\CLK"] = cell->connections_["\\RD_CLK"].extract(i, 1); + c->connections_["\\Q"] = rd_signals.back(); count_dff++; RTLIL::Wire *w = new RTLIL::Wire; @@ -191,7 +191,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) rd_signals.clear(); rd_signals.push_back(RTLIL::SigSpec(w)); - c->connections["\\D"] = rd_signals.back(); + c->connections_["\\D"] = rd_signals.back(); } } @@ -203,31 +203,31 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) { RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdmux", i, "", j, "", k), "$mux"); c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"]; - c->connections["\\Y"] = rd_signals[k]; - c->connections["\\S"] = rd_addr.extract(mem_abits-j-1, 1); + c->connections_["\\Y"] = rd_signals[k]; + c->connections_["\\S"] = rd_addr.extract(mem_abits-j-1, 1); count_mux++; RTLIL::Wire *w = new RTLIL::Wire; w->name = genid(cell->name, "$rdmux", i, "", j, "", k, "$a"); w->width = mem_width; module->wires[w->name] = w; - c->connections["\\A"] = RTLIL::SigSpec(w); + c->connections_["\\A"] = RTLIL::SigSpec(w); w = new RTLIL::Wire; w->name = genid(cell->name, "$rdmux", i, "", j, "", k, "$b"); w->width = mem_width; module->wires[w->name] = w; - c->connections["\\B"] = RTLIL::SigSpec(w); + c->connections_["\\B"] = RTLIL::SigSpec(w); - next_rd_signals.push_back(c->connections["\\A"]); - next_rd_signals.push_back(c->connections["\\B"]); + next_rd_signals.push_back(c->connections_["\\A"]); + next_rd_signals.push_back(c->connections_["\\B"]); } next_rd_signals.swap(rd_signals); } for (int j = 0; j < mem_size; j++) - module->connections.push_back(RTLIL::SigSig(rd_signals[j], data_reg_out[j])); + module->connections_.push_back(RTLIL::SigSig(rd_signals[j], data_reg_out[j])); } log(" read interface: %d $dff and %d $mux cells.\n", count_dff, count_mux); @@ -241,9 +241,9 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) for (int j = 0; j < cell->parameters["\\WR_PORTS"].as_int(); j++) { - RTLIL::SigSpec wr_addr = cell->connections["\\WR_ADDR"].extract(j*mem_abits, mem_abits); - RTLIL::SigSpec wr_data = cell->connections["\\WR_DATA"].extract(j*mem_width, mem_width); - RTLIL::SigSpec wr_en = cell->connections["\\WR_EN"].extract(j*mem_width, mem_width); + RTLIL::SigSpec wr_addr = cell->connections_["\\WR_ADDR"].extract(j*mem_abits, mem_abits); + RTLIL::SigSpec wr_data = cell->connections_["\\WR_DATA"].extract(j*mem_width, mem_width); + RTLIL::SigSpec wr_en = cell->connections_["\\WR_EN"].extract(j*mem_width, mem_width); RTLIL::Cell *c = module->addCell(genid(cell->name, "$wreq", i, "", j), "$eq"); c->parameters["\\A_SIGNED"] = RTLIL::Const(0); @@ -251,14 +251,14 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) c->parameters["\\A_WIDTH"] = cell->parameters["\\ABITS"]; c->parameters["\\B_WIDTH"] = cell->parameters["\\ABITS"]; c->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - c->connections["\\A"] = RTLIL::SigSpec(i, mem_abits); - c->connections["\\B"] = wr_addr; + c->connections_["\\A"] = RTLIL::SigSpec(i, mem_abits); + c->connections_["\\B"] = wr_addr; count_wrmux++; RTLIL::Wire *w_seladdr = new RTLIL::Wire; w_seladdr->name = genid(cell->name, "$wreq", i, "", j, "$y"); module->wires[w_seladdr->name] = w_seladdr; - c->connections["\\Y"] = w_seladdr; + c->connections_["\\Y"] = w_seladdr; int wr_offset = 0; while (wr_offset < wr_en.size()) @@ -283,33 +283,33 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) c->parameters["\\A_WIDTH"] = RTLIL::Const(1); c->parameters["\\B_WIDTH"] = RTLIL::Const(1); c->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - c->connections["\\A"] = w; - c->connections["\\B"] = wr_bit; + c->connections_["\\A"] = w; + c->connections_["\\B"] = wr_bit; w = new RTLIL::Wire; w->name = genid(cell->name, "$wren", i, "", j, "", wr_offset, "$y"); module->wires[w->name] = w; - c->connections["\\Y"] = RTLIL::SigSpec(w); + c->connections_["\\Y"] = RTLIL::SigSpec(w); } c = module->addCell(genid(cell->name, "$wrmux", i, "", j, "", wr_offset), "$mux"); c->parameters["\\WIDTH"] = wr_width; - c->connections["\\A"] = sig.extract(wr_offset, wr_width); - c->connections["\\B"] = wr_data.extract(wr_offset, wr_width); - c->connections["\\S"] = RTLIL::SigSpec(w); + c->connections_["\\A"] = sig.extract(wr_offset, wr_width); + c->connections_["\\B"] = wr_data.extract(wr_offset, wr_width); + c->connections_["\\S"] = RTLIL::SigSpec(w); w = new RTLIL::Wire; w->name = genid(cell->name, "$wrmux", i, "", j, "", wr_offset, "$y"); w->width = wr_width; module->wires[w->name] = w; - c->connections["\\Y"] = w; + c->connections_["\\Y"] = w; sig.replace(wr_offset, w); wr_offset += wr_width; } } - module->connections.push_back(RTLIL::SigSig(data_reg_in[i], sig)); + module->connections_.push_back(RTLIL::SigSig(data_reg_in[i], sig)); } log(" write interface: %d blocks of $eq, $and and $mux cells.\n", count_wrmux); diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index 63f6b14f8..919e24a4a 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -64,16 +64,16 @@ struct MemoryShareWorker RTLIL::Cell *cell = sig_to_mux.at(sig).first; int bit_idx = sig_to_mux.at(sig).second; - std::vector sig_a = sigmap(cell->connections.at("\\A")); - std::vector sig_b = sigmap(cell->connections.at("\\B")); - std::vector sig_s = sigmap(cell->connections.at("\\S")); - std::vector sig_y = sigmap(cell->connections.at("\\Y")); + std::vector sig_a = sigmap(cell->connections_.at("\\A")); + std::vector sig_b = sigmap(cell->connections_.at("\\B")); + std::vector sig_s = sigmap(cell->connections_.at("\\S")); + std::vector sig_y = sigmap(cell->connections_.at("\\Y")); log_assert(sig_y.at(bit_idx) == sig); for (int i = 0; i < int(sig_s.size()); i++) if (state.count(sig_s[i]) && state.at(sig_s[i]) == true) { if (find_data_feedback(async_rd_bits, sig_b.at(bit_idx + i*sig_y.size()), state, conditions)) - cell->connections.at("\\B").replace(bit_idx + i*sig_y.size(), RTLIL::State::Sx); + cell->connections_.at("\\B").replace(bit_idx + i*sig_y.size(), RTLIL::State::Sx); return false; } @@ -87,7 +87,7 @@ struct MemoryShareWorker new_state[sig_s[i]] = true; if (find_data_feedback(async_rd_bits, sig_b.at(bit_idx + i*sig_y.size()), new_state, conditions)) - cell->connections.at("\\B").replace(bit_idx + i*sig_y.size(), RTLIL::State::Sx); + cell->connections_.at("\\B").replace(bit_idx + i*sig_y.size(), RTLIL::State::Sx); } std::map new_state = state; @@ -95,7 +95,7 @@ struct MemoryShareWorker new_state[sig_s[i]] = false; if (find_data_feedback(async_rd_bits, sig_a.at(bit_idx), new_state, conditions)) - cell->connections.at("\\A").replace(bit_idx, RTLIL::State::Sx); + cell->connections_.at("\\A").replace(bit_idx, RTLIL::State::Sx); return false; } @@ -141,10 +141,10 @@ struct MemoryShareWorker if (cell->type == "$mux" || cell->type == "$pmux") { - std::vector sig_a = sigmap(cell->connections.at("\\A")); - std::vector sig_b = sigmap(cell->connections.at("\\B")); - std::vector sig_s = sigmap(cell->connections.at("\\S")); - std::vector sig_y = sigmap(cell->connections.at("\\Y")); + std::vector sig_a = sigmap(cell->connections_.at("\\A")); + std::vector sig_b = sigmap(cell->connections_.at("\\B")); + std::vector sig_s = sigmap(cell->connections_.at("\\S")); + std::vector sig_y = sigmap(cell->connections_.at("\\Y")); non_feedback_nets.insert(sig_s.begin(), sig_s.end()); @@ -161,7 +161,7 @@ struct MemoryShareWorker cell->parameters.at("\\MEMID").decode_string() == memid) ignore_data_port = true; - for (auto conn : cell_it.second->connections) + for (auto conn : cell_it.second->connections_) { if (ignore_data_port && conn.first == "\\DATA") continue; @@ -191,8 +191,8 @@ struct MemoryShareWorker if (cell->parameters.at("\\CLK_ENABLE").as_bool()) continue; - RTLIL::SigSpec sig_addr = sigmap(cell->connections.at("\\ADDR")); - std::vector sig_data = sigmap(cell->connections.at("\\DATA")); + RTLIL::SigSpec sig_addr = sigmap(cell->connections_.at("\\ADDR")); + std::vector sig_data = sigmap(cell->connections_.at("\\DATA")); for (int i = 0; i < int(sig_data.size()); i++) if (non_feedback_nets.count(sig_data[i])) @@ -212,14 +212,14 @@ struct MemoryShareWorker for (auto cell : wr_ports) { - RTLIL::SigSpec sig_addr = sigmap_xmux(cell->connections.at("\\ADDR")); + RTLIL::SigSpec sig_addr = sigmap_xmux(cell->connections_.at("\\ADDR")); if (!async_rd_bits.count(sig_addr)) continue; log(" Analyzing write port %s.\n", log_id(cell)); - std::vector cell_data = cell->connections.at("\\DATA"); - std::vector cell_en = cell->connections.at("\\EN"); + std::vector cell_data = cell->connections_.at("\\DATA"); + std::vector cell_en = cell->connections_.at("\\EN"); int created_conditions = 0; for (int i = 0; i < int(cell_data.size()); i++) @@ -239,7 +239,7 @@ struct MemoryShareWorker if (created_conditions) { log(" Added enable logic for %d different cases.\n", created_conditions); - cell->connections.at("\\EN") = cell_en; + cell->connections_.at("\\EN") = cell_en; } } } @@ -357,15 +357,15 @@ struct MemoryShareWorker for (int i = 0; i < int(wr_ports.size()); i++) { RTLIL::Cell *cell = wr_ports.at(i); - RTLIL::SigSpec addr = sigmap_xmux(cell->connections.at("\\ADDR")); + RTLIL::SigSpec addr = sigmap_xmux(cell->connections_.at("\\ADDR")); if (cell->parameters.at("\\CLK_ENABLE").as_bool() != cache_clk_enable || - (cache_clk_enable && (sigmap(cell->connections.at("\\CLK")) != cache_clk || + (cache_clk_enable && (sigmap(cell->connections_.at("\\CLK")) != cache_clk || cell->parameters.at("\\CLK_POLARITY").as_bool() != cache_clk_polarity))) { cache_clk_enable = cell->parameters.at("\\CLK_ENABLE").as_bool(); cache_clk_polarity = cell->parameters.at("\\CLK_POLARITY").as_bool(); - cache_clk = sigmap(cell->connections.at("\\CLK")); + cache_clk = sigmap(cell->connections_.at("\\CLK")); last_port_by_addr.clear(); if (cache_clk_enable) @@ -377,7 +377,7 @@ struct MemoryShareWorker log(" Port %d (%s) has addr %s.\n", i, log_id(cell), log_signal(addr)); log(" Active bits: "); - std::vector en_bits = sigmap(cell->connections.at("\\EN")); + std::vector en_bits = sigmap(cell->connections_.at("\\EN")); active_bits_on_port.push_back(std::vector(en_bits.size())); for (int k = int(en_bits.size())-1; k >= 0; k--) { active_bits_on_port[i][k] = en_bits[k].wire != NULL || en_bits[k].data != RTLIL::State::S0; @@ -399,13 +399,13 @@ struct MemoryShareWorker // Force this ports addr input to addr directly (skip don't care muxes) - cell->connections.at("\\ADDR") = addr; + cell->connections_.at("\\ADDR") = addr; // If any of the ports between `last_i' and `i' write to the same address, this // will have priority over whatever `last_i` wrote. So we need to revisit those // ports and mask the EN bits accordingly. - RTLIL::SigSpec merged_en = sigmap(wr_ports[last_i]->connections.at("\\EN")); + RTLIL::SigSpec merged_en = sigmap(wr_ports[last_i]->connections_.at("\\EN")); for (int j = last_i+1; j < i; j++) { @@ -420,20 +420,20 @@ struct MemoryShareWorker found_overlapping_bits_i_j: log(" Creating collosion-detect logic for port %d.\n", j); RTLIL::SigSpec is_same_addr = module->addWire(NEW_ID); - module->addEq(NEW_ID, addr, wr_ports[j]->connections.at("\\ADDR"), is_same_addr); - merged_en = mask_en_grouped(is_same_addr, merged_en, sigmap(wr_ports[j]->connections.at("\\EN"))); + module->addEq(NEW_ID, addr, wr_ports[j]->connections_.at("\\ADDR"), is_same_addr); + merged_en = mask_en_grouped(is_same_addr, merged_en, sigmap(wr_ports[j]->connections_.at("\\EN"))); } } // Then we need to merge the (masked) EN and the DATA signals. - RTLIL::SigSpec merged_data = wr_ports[last_i]->connections.at("\\DATA"); + RTLIL::SigSpec merged_data = wr_ports[last_i]->connections_.at("\\DATA"); if (found_overlapping_bits) { log(" Creating logic for merging DATA and EN ports.\n"); - merge_en_data(merged_en, merged_data, sigmap(cell->connections.at("\\EN")), sigmap(cell->connections.at("\\DATA"))); + merge_en_data(merged_en, merged_data, sigmap(cell->connections_.at("\\EN")), sigmap(cell->connections_.at("\\DATA"))); } else { - RTLIL::SigSpec cell_en = sigmap(cell->connections.at("\\EN")); - RTLIL::SigSpec cell_data = sigmap(cell->connections.at("\\DATA")); + RTLIL::SigSpec cell_en = sigmap(cell->connections_.at("\\EN")); + RTLIL::SigSpec cell_data = sigmap(cell->connections_.at("\\DATA")); for (int k = 0; k < int(en_bits.size()); k++) if (!active_bits_on_port[last_i][k]) { merged_en.replace(k, cell_en.extract(k, 1)); @@ -443,14 +443,14 @@ struct MemoryShareWorker // Connect the new EN and DATA signals and remove the old write port. - cell->connections.at("\\EN") = merged_en; - cell->connections.at("\\DATA") = merged_data; + cell->connections_.at("\\EN") = merged_en; + cell->connections_.at("\\DATA") = merged_data; module->remove(wr_ports[last_i]); wr_ports[last_i] = NULL; log(" Active bits: "); - std::vector en_bits = sigmap(cell->connections.at("\\EN")); + std::vector en_bits = sigmap(cell->connections_.at("\\EN")); active_bits_on_port.push_back(std::vector(en_bits.size())); for (int k = int(en_bits.size())-1; k >= 0; k--) log("%c", active_bits_on_port[i][k] ? '1' : '0'); @@ -489,7 +489,7 @@ struct MemoryShareWorker std::set considered_port_pairs; for (int i = 0; i < int(wr_ports.size()); i++) { - std::vector bits = modwalker.sigmap(wr_ports[i]->connections.at("\\EN")); + std::vector bits = modwalker.sigmap(wr_ports[i]->connections_.at("\\EN")); for (auto bit : bits) if (bit == RTLIL::State::S1) goto port_is_always_active; @@ -509,12 +509,12 @@ struct MemoryShareWorker RTLIL::Cell *cell = wr_ports.at(i); if (cell->parameters.at("\\CLK_ENABLE").as_bool() != cache_clk_enable || - (cache_clk_enable && (sigmap(cell->connections.at("\\CLK")) != cache_clk || + (cache_clk_enable && (sigmap(cell->connections_.at("\\CLK")) != cache_clk || cell->parameters.at("\\CLK_POLARITY").as_bool() != cache_clk_polarity))) { cache_clk_enable = cell->parameters.at("\\CLK_ENABLE").as_bool(); cache_clk_polarity = cell->parameters.at("\\CLK_POLARITY").as_bool(); - cache_clk = sigmap(cell->connections.at("\\CLK")); + cache_clk = sigmap(cell->connections_.at("\\CLK")); } else if (i > 0 && considered_ports.count(i-1) && considered_ports.count(i)) considered_port_pairs.insert(i); @@ -542,7 +542,7 @@ struct MemoryShareWorker for (int i = 0; i < int(wr_ports.size()); i++) if (considered_port_pairs.count(i) || considered_port_pairs.count(i+1)) { - RTLIL::SigSpec sig = modwalker.sigmap(wr_ports[i]->connections.at("\\EN")); + RTLIL::SigSpec sig = modwalker.sigmap(wr_ports[i]->connections_.at("\\EN")); port_to_sat_variable[i] = ez.expression(ez.OpOr, satgen.importSigSpec(sig)); std::vector bits = sig; @@ -585,18 +585,18 @@ struct MemoryShareWorker log(" Merging port %d into port %d.\n", i-1, i); port_to_sat_variable.at(i) = ez.OR(port_to_sat_variable.at(i-1), port_to_sat_variable.at(i)); - RTLIL::SigSpec last_addr = wr_ports[i-1]->connections.at("\\ADDR"); - RTLIL::SigSpec last_data = wr_ports[i-1]->connections.at("\\DATA"); - std::vector last_en = modwalker.sigmap(wr_ports[i-1]->connections.at("\\EN")); + RTLIL::SigSpec last_addr = wr_ports[i-1]->connections_.at("\\ADDR"); + RTLIL::SigSpec last_data = wr_ports[i-1]->connections_.at("\\DATA"); + std::vector last_en = modwalker.sigmap(wr_ports[i-1]->connections_.at("\\EN")); - RTLIL::SigSpec this_addr = wr_ports[i]->connections.at("\\ADDR"); - RTLIL::SigSpec this_data = wr_ports[i]->connections.at("\\DATA"); - std::vector this_en = modwalker.sigmap(wr_ports[i]->connections.at("\\EN")); + RTLIL::SigSpec this_addr = wr_ports[i]->connections_.at("\\ADDR"); + RTLIL::SigSpec this_data = wr_ports[i]->connections_.at("\\DATA"); + std::vector this_en = modwalker.sigmap(wr_ports[i]->connections_.at("\\EN")); RTLIL::SigBit this_en_active = module->ReduceOr(NEW_ID, this_en); - wr_ports[i]->connections.at("\\ADDR") = module->Mux(NEW_ID, last_addr, this_addr, this_en_active); - wr_ports[i]->connections.at("\\DATA") = module->Mux(NEW_ID, last_data, this_data, this_en_active); + wr_ports[i]->connections_.at("\\ADDR") = module->Mux(NEW_ID, last_addr, this_addr, this_en_active); + wr_ports[i]->connections_.at("\\DATA") = module->Mux(NEW_ID, last_data, this_data, this_en_active); std::map, int> groups_en; RTLIL::SigSpec grouped_last_en, grouped_this_en, en; @@ -614,7 +614,7 @@ struct MemoryShareWorker } module->addMux(NEW_ID, grouped_last_en, grouped_this_en, this_en_active, grouped_en); - wr_ports[i]->connections.at("\\EN") = en; + wr_ports[i]->connections_.at("\\EN") = en; module->remove(wr_ports[i-1]); wr_ports[i-1] = NULL; @@ -653,18 +653,18 @@ struct MemoryShareWorker if (cell->type == "$mux") { - RTLIL::SigSpec sig_a = sigmap_xmux(cell->connections.at("\\A")); - RTLIL::SigSpec sig_b = sigmap_xmux(cell->connections.at("\\B")); + RTLIL::SigSpec sig_a = sigmap_xmux(cell->connections_.at("\\A")); + RTLIL::SigSpec sig_b = sigmap_xmux(cell->connections_.at("\\B")); if (sig_a.is_fully_undef()) - sigmap_xmux.add(cell->connections.at("\\Y"), sig_b); + sigmap_xmux.add(cell->connections_.at("\\Y"), sig_b); else if (sig_b.is_fully_undef()) - sigmap_xmux.add(cell->connections.at("\\Y"), sig_a); + sigmap_xmux.add(cell->connections_.at("\\Y"), sig_a); } if (cell->type == "$mux" || cell->type == "$pmux") { - std::vector sig_y = sigmap(cell->connections.at("\\Y")); + std::vector sig_y = sigmap(cell->connections_.at("\\Y")); for (int i = 0; i < int(sig_y.size()); i++) sig_to_mux[sig_y[i]] = std::pair(cell, i); } diff --git a/passes/memory/memory_unpack.cc b/passes/memory/memory_unpack.cc index 97cda1443..9c457ad5d 100644 --- a/passes/memory/memory_unpack.cc +++ b/passes/memory/memory_unpack.cc @@ -54,9 +54,9 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory) cell->parameters["\\CLK_ENABLE"] = RTLIL::SigSpec(memory->parameters.at("\\RD_CLK_ENABLE")).extract(i, 1).as_const(); cell->parameters["\\CLK_POLARITY"] = RTLIL::SigSpec(memory->parameters.at("\\RD_CLK_POLARITY")).extract(i, 1).as_const(); cell->parameters["\\TRANSPARENT"] = RTLIL::SigSpec(memory->parameters.at("\\RD_TRANSPARENT")).extract(i, 1).as_const(); - cell->connections["\\CLK"] = memory->connections.at("\\RD_CLK").extract(i, 1); - cell->connections["\\ADDR"] = memory->connections.at("\\RD_ADDR").extract(i*abits, abits); - cell->connections["\\DATA"] = memory->connections.at("\\RD_DATA").extract(i*mem->width, mem->width); + cell->connections_["\\CLK"] = memory->connections_.at("\\RD_CLK").extract(i, 1); + cell->connections_["\\ADDR"] = memory->connections_.at("\\RD_ADDR").extract(i*abits, abits); + cell->connections_["\\DATA"] = memory->connections_.at("\\RD_DATA").extract(i*mem->width, mem->width); } for (int i = 0; i < num_wr_ports; i++) @@ -68,10 +68,10 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory) cell->parameters["\\CLK_ENABLE"] = RTLIL::SigSpec(memory->parameters.at("\\WR_CLK_ENABLE")).extract(i, 1).as_const(); cell->parameters["\\CLK_POLARITY"] = RTLIL::SigSpec(memory->parameters.at("\\WR_CLK_POLARITY")).extract(i, 1).as_const(); cell->parameters["\\PRIORITY"] = i; - cell->connections["\\CLK"] = memory->connections.at("\\WR_CLK").extract(i, 1); - cell->connections["\\EN"] = memory->connections.at("\\WR_EN").extract(i*mem->width, mem->width); - cell->connections["\\ADDR"] = memory->connections.at("\\WR_ADDR").extract(i*abits, abits); - cell->connections["\\DATA"] = memory->connections.at("\\WR_DATA").extract(i*mem->width, mem->width); + cell->connections_["\\CLK"] = memory->connections_.at("\\WR_CLK").extract(i, 1); + cell->connections_["\\EN"] = memory->connections_.at("\\WR_EN").extract(i*mem->width, mem->width); + cell->connections_["\\ADDR"] = memory->connections_.at("\\WR_ADDR").extract(i*abits, abits); + cell->connections_["\\DATA"] = memory->connections_.at("\\WR_DATA").extract(i*mem->width, mem->width); } module->remove(memory); diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 00fa6031f..30ab88146 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -40,7 +40,7 @@ static void rmunused_module_cells(RTLIL::Module *module, bool verbose) SigSet wire2driver; for (auto &it : module->cells) { RTLIL::Cell *cell = it.second; - for (auto &it2 : cell->connections) { + for (auto &it2 : cell->connections_) { if (!ct.cell_input(cell->type, it2.first)) { RTLIL::SigSpec sig = it2.second; assign_map.apply(sig); @@ -70,7 +70,7 @@ static void rmunused_module_cells(RTLIL::Module *module, bool verbose) for (auto cell : queue) unused.erase(cell); for (auto cell : queue) { - for (auto &it : cell->connections) { + for (auto &it : cell->connections_) { if (!ct.cell_output(cell->type, it.first)) { std::set cell_list; RTLIL::SigSpec sig = it.second; @@ -158,10 +158,10 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool for (auto &it : module->cells) { RTLIL::Cell *cell = it.second; if (ct_reg.cell_known(cell->type)) - for (auto &it2 : cell->connections) + for (auto &it2 : cell->connections_) if (ct_reg.cell_output(cell->type, it2.first)) register_signals.add(it2.second); - for (auto &it2 : cell->connections) + for (auto &it2 : cell->connections_) connected_signals.add(it2.second); } @@ -171,7 +171,7 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool for (auto &it : module->cells) { RTLIL::Cell *cell = it.second; if (ct_all.cell_known(cell->type)) - for (auto &it2 : cell->connections) + for (auto &it2 : cell->connections_) if (ct_all.cell_output(cell->type, it2.first)) direct_sigs.insert(assign_map(it2.second)); } @@ -189,13 +189,13 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool } } - module->connections.clear(); + module->connections_.clear(); SigPool used_signals; SigPool used_signals_nodrivers; for (auto &it : module->cells) { RTLIL::Cell *cell = it.second; - for (auto &it2 : cell->connections) { + for (auto &it2 : cell->connections_) { assign_map.apply(it2.second); used_signals.add(it2.second); if (!ct.cell_output(cell->type, it2.first)) @@ -237,7 +237,7 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool if (new_conn.first.size() > 0) { used_signals.add(new_conn.first); used_signals.add(new_conn.second); - module->connections.push_back(new_conn); + module->connections_.push_back(new_conn); } } } else { diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index e1b6c598f..2a5ec8bea 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -38,7 +38,7 @@ static void replace_undriven(RTLIL::Design *design, RTLIL::Module *module) SigPool all_signals; for (auto &it : module->cells) - for (auto &conn : it.second->connections) { + for (auto &conn : it.second->connections_) { if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first)) driven_signals.add(sigmap(conn.second)); if (!ct.cell_known(it.second->type) || ct.cell_input(it.second->type, conn.first)) @@ -66,21 +66,21 @@ static void replace_undriven(RTLIL::Design *design, RTLIL::Module *module) continue; log("Setting undriven signal in %s to undef: %s\n", RTLIL::id2cstr(module->name), log_signal(c)); - module->connections.push_back(RTLIL::SigSig(c, RTLIL::SigSpec(RTLIL::State::Sx, c.width))); + module->connections_.push_back(RTLIL::SigSig(c, RTLIL::SigSpec(RTLIL::State::Sx, c.width))); OPT_DID_SOMETHING = true; } } static void replace_cell(RTLIL::Module *module, RTLIL::Cell *cell, std::string info, std::string out_port, RTLIL::SigSpec out_val) { - RTLIL::SigSpec Y = cell->connections[out_port]; + RTLIL::SigSpec Y = cell->connections_[out_port]; out_val.extend_u0(Y.size(), false); log("Replacing %s cell `%s' (%s) in module `%s' with constant driver `%s = %s'.\n", cell->type.c_str(), cell->name.c_str(), info.c_str(), module->name.c_str(), log_signal(Y), log_signal(out_val)); // ILANG_BACKEND::dump_cell(stderr, "--> ", cell); - module->connections.push_back(RTLIL::SigSig(Y, out_val)); + module->connections_.push_back(RTLIL::SigSig(Y, out_val)); module->remove(cell); OPT_DID_SOMETHING = true; did_something = true; @@ -88,14 +88,14 @@ static void replace_cell(RTLIL::Module *module, RTLIL::Cell *cell, std::string i static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutative, bool extend_u0, SigMap &sigmap) { - std::string b_name = cell->connections.count("\\B") ? "\\B" : "\\A"; + std::string b_name = cell->connections_.count("\\B") ? "\\B" : "\\A"; bool a_signed = cell->parameters.at("\\A_SIGNED").as_bool(); bool b_signed = cell->parameters.at(b_name + "_SIGNED").as_bool(); - RTLIL::SigSpec sig_a = sigmap(cell->connections.at("\\A")); - RTLIL::SigSpec sig_b = sigmap(cell->connections.at(b_name)); - RTLIL::SigSpec sig_y = sigmap(cell->connections.at("\\Y")); + RTLIL::SigSpec sig_a = sigmap(cell->connections_.at("\\A")); + RTLIL::SigSpec sig_b = sigmap(cell->connections_.at(b_name)); + RTLIL::SigSpec sig_y = sigmap(cell->connections_.at("\\Y")); if (extend_u0) { sig_a.extend_u0(sig_y.size(), a_signed); @@ -160,21 +160,21 @@ static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool com RTLIL::Cell *c = module->addCell(NEW_ID, cell->type); - c->connections["\\A"] = new_a; + c->connections_["\\A"] = new_a; c->parameters["\\A_WIDTH"] = new_a.size(); c->parameters["\\A_SIGNED"] = false; if (b_name == "\\B") { - c->connections["\\B"] = new_b; + c->connections_["\\B"] = new_b; c->parameters["\\B_WIDTH"] = new_b.size(); c->parameters["\\B_SIGNED"] = false; } - c->connections["\\Y"] = new_y; + c->connections_["\\Y"] = new_y; c->parameters["\\Y_WIDTH"] = new_y->width; c->check(); - module->connections.push_back(new_conn); + module->connections_.push_back(new_conn); log(" New cell `%s': A=%s", log_id(c), log_signal(new_a)); if (b_name == "\\B") @@ -203,8 +203,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo for (auto &cell_it : module->cells) if (design->selected(module, cell_it.second)) { if ((cell_it.second->type == "$_INV_" || cell_it.second->type == "$not" || cell_it.second->type == "$logic_not") && - cell_it.second->connections["\\A"].size() == 1 && cell_it.second->connections["\\Y"].size() == 1) - invert_map[assign_map(cell_it.second->connections["\\Y"])] = assign_map(cell_it.second->connections["\\A"]); + cell_it.second->connections_["\\A"].size() == 1 && cell_it.second->connections_["\\Y"].size() == 1) + invert_map[assign_map(cell_it.second->connections_["\\Y"])] = assign_map(cell_it.second->connections_["\\A"]); cells.push_back(cell_it.second); } @@ -222,7 +222,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (cell->type == "$reduce_and") { - RTLIL::SigSpec sig_a = assign_map(cell->connections.at("\\A")); + RTLIL::SigSpec sig_a = assign_map(cell->connections_.at("\\A")); RTLIL::State new_a = RTLIL::State::S1; for (auto &bit : sig_a.to_sigbit_vector()) @@ -240,7 +240,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cover("opt.opt_const.fine.$reduce_and"); log("Replacing port A of %s cell `%s' in module `%s' with constant driver: %s -> %s\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a)); - cell->connections.at("\\A") = sig_a = new_a; + cell->connections_.at("\\A") = sig_a = new_a; cell->parameters.at("\\A_WIDTH") = 1; OPT_DID_SOMETHING = true; did_something = true; @@ -249,7 +249,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (cell->type == "$logic_not" || cell->type == "$logic_and" || cell->type == "$logic_or" || cell->type == "$reduce_or" || cell->type == "$reduce_bool") { - RTLIL::SigSpec sig_a = assign_map(cell->connections.at("\\A")); + RTLIL::SigSpec sig_a = assign_map(cell->connections_.at("\\A")); RTLIL::State new_a = RTLIL::State::S0; for (auto &bit : sig_a.to_sigbit_vector()) @@ -267,7 +267,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cover_list("opt.opt_const.fine.A", "$logic_not", "$logic_and", "$logic_or", "$reduce_or", "$reduce_bool", cell->type); log("Replacing port A of %s cell `%s' in module `%s' with constant driver: %s -> %s\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a)); - cell->connections.at("\\A") = sig_a = new_a; + cell->connections_.at("\\A") = sig_a = new_a; cell->parameters.at("\\A_WIDTH") = 1; OPT_DID_SOMETHING = true; did_something = true; @@ -276,7 +276,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (cell->type == "$logic_and" || cell->type == "$logic_or") { - RTLIL::SigSpec sig_b = assign_map(cell->connections.at("\\B")); + RTLIL::SigSpec sig_b = assign_map(cell->connections_.at("\\B")); RTLIL::State new_b = RTLIL::State::S0; for (auto &bit : sig_b.to_sigbit_vector()) @@ -294,7 +294,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cover_list("opt.opt_const.fine.B", "$logic_and", "$logic_or", cell->type); log("Replacing port B of %s cell `%s' in module `%s' with constant driver: %s -> %s\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_b), log_signal(new_b)); - cell->connections.at("\\B") = sig_b = new_b; + cell->connections_.at("\\B") = sig_b = new_b; cell->parameters.at("\\B_WIDTH") = 1; OPT_DID_SOMETHING = true; did_something = true; @@ -302,13 +302,13 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo } } - if (cell->type == "$logic_or" && (assign_map(cell->connections.at("\\A")) == RTLIL::State::S1 || assign_map(cell->connections.at("\\B")) == RTLIL::State::S1)) { + if (cell->type == "$logic_or" && (assign_map(cell->connections_.at("\\A")) == RTLIL::State::S1 || assign_map(cell->connections_.at("\\B")) == RTLIL::State::S1)) { cover("opt.opt_const.one_high"); replace_cell(module, cell, "one high", "\\Y", RTLIL::State::S1); goto next_cell; } - if (cell->type == "$logic_and" && (assign_map(cell->connections.at("\\A")) == RTLIL::State::S0 || assign_map(cell->connections.at("\\B")) == RTLIL::State::S0)) { + if (cell->type == "$logic_and" && (assign_map(cell->connections_.at("\\A")) == RTLIL::State::S0 || assign_map(cell->connections_.at("\\B")) == RTLIL::State::S0)) { cover("opt.opt_const.one_low"); replace_cell(module, cell, "one low", "\\Y", RTLIL::State::S0); goto next_cell; @@ -320,8 +320,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cell->type == "$neg" || cell->type == "$add" || cell->type == "$sub" || cell->type == "$mul" || cell->type == "$div" || cell->type == "$mod" || cell->type == "$pow") { - RTLIL::SigSpec sig_a = assign_map(cell->connections.at("\\A")); - RTLIL::SigSpec sig_b = cell->connections.count("\\B") ? assign_map(cell->connections.at("\\B")) : RTLIL::SigSpec(); + RTLIL::SigSpec sig_a = assign_map(cell->connections_.at("\\A")); + RTLIL::SigSpec sig_b = cell->connections_.count("\\B") ? assign_map(cell->connections_.at("\\B")) : RTLIL::SigSpec(); if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr") sig_a = RTLIL::SigSpec(); @@ -342,31 +342,31 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cell->type == "$lt" || cell->type == "$le" || cell->type == "$ge" || cell->type == "$gt") replace_cell(module, cell, "x-bit in input", "\\Y", RTLIL::State::Sx); else - replace_cell(module, cell, "x-bit in input", "\\Y", RTLIL::SigSpec(RTLIL::State::Sx, cell->connections.at("\\Y").size())); + replace_cell(module, cell, "x-bit in input", "\\Y", RTLIL::SigSpec(RTLIL::State::Sx, cell->connections_.at("\\Y").size())); goto next_cell; } } - if ((cell->type == "$_INV_" || cell->type == "$not" || cell->type == "$logic_not") && cell->connections["\\Y"].size() == 1 && - invert_map.count(assign_map(cell->connections["\\A"])) != 0) { + if ((cell->type == "$_INV_" || cell->type == "$not" || cell->type == "$logic_not") && cell->connections_["\\Y"].size() == 1 && + invert_map.count(assign_map(cell->connections_["\\A"])) != 0) { cover_list("opt.opt_const.invert.double", "$_INV_", "$not", "$logic_not", cell->type); - replace_cell(module, cell, "double_invert", "\\Y", invert_map.at(assign_map(cell->connections["\\A"]))); + replace_cell(module, cell, "double_invert", "\\Y", invert_map.at(assign_map(cell->connections_["\\A"]))); goto next_cell; } - if ((cell->type == "$_MUX_" || cell->type == "$mux") && invert_map.count(assign_map(cell->connections["\\S"])) != 0) { + if ((cell->type == "$_MUX_" || cell->type == "$mux") && invert_map.count(assign_map(cell->connections_["\\S"])) != 0) { cover_list("opt.opt_const.invert.muxsel", "$_MUX_", "$mux", cell->type); - RTLIL::SigSpec tmp = cell->connections["\\A"]; - cell->connections["\\A"] = cell->connections["\\B"]; - cell->connections["\\B"] = tmp; - cell->connections["\\S"] = invert_map.at(assign_map(cell->connections["\\S"])); + RTLIL::SigSpec tmp = cell->connections_["\\A"]; + cell->connections_["\\A"] = cell->connections_["\\B"]; + cell->connections_["\\B"] = tmp; + cell->connections_["\\S"] = invert_map.at(assign_map(cell->connections_["\\S"])); OPT_DID_SOMETHING = true; did_something = true; goto next_cell; } if (cell->type == "$_INV_") { - RTLIL::SigSpec input = cell->connections["\\A"]; + RTLIL::SigSpec input = cell->connections_["\\A"]; assign_map.apply(input); if (input.match("1")) ACTION_DO_Y(0); if (input.match("0")) ACTION_DO_Y(1); @@ -375,8 +375,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (cell->type == "$_AND_") { RTLIL::SigSpec input; - input.append(cell->connections["\\B"]); - input.append(cell->connections["\\A"]); + input.append(cell->connections_["\\B"]); + input.append(cell->connections_["\\A"]); assign_map.apply(input); if (input.match(" 0")) ACTION_DO_Y(0); if (input.match("0 ")) ACTION_DO_Y(0); @@ -394,8 +394,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (cell->type == "$_OR_") { RTLIL::SigSpec input; - input.append(cell->connections["\\B"]); - input.append(cell->connections["\\A"]); + input.append(cell->connections_["\\B"]); + input.append(cell->connections_["\\A"]); assign_map.apply(input); if (input.match(" 1")) ACTION_DO_Y(1); if (input.match("1 ")) ACTION_DO_Y(1); @@ -413,8 +413,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (cell->type == "$_XOR_") { RTLIL::SigSpec input; - input.append(cell->connections["\\B"]); - input.append(cell->connections["\\A"]); + input.append(cell->connections_["\\B"]); + input.append(cell->connections_["\\A"]); assign_map.apply(input); if (input.match("00")) ACTION_DO_Y(0); if (input.match("01")) ACTION_DO_Y(1); @@ -428,9 +428,9 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (cell->type == "$_MUX_") { RTLIL::SigSpec input; - input.append(cell->connections["\\S"]); - input.append(cell->connections["\\B"]); - input.append(cell->connections["\\A"]); + input.append(cell->connections_["\\S"]); + input.append(cell->connections_["\\B"]); + input.append(cell->connections_["\\A"]); assign_map.apply(input); if (input.extract(2, 1) == input.extract(1, 1)) ACTION_DO("\\Y", input.extract(2, 1)); @@ -440,9 +440,9 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (input.match("10 ")) { cover("opt.opt_const.mux_to_inv"); cell->type = "$_INV_"; - cell->connections["\\A"] = input.extract(0, 1); - cell->connections.erase("\\B"); - cell->connections.erase("\\S"); + cell->connections_["\\A"] = input.extract(0, 1); + cell->connections_.erase("\\B"); + cell->connections_.erase("\\S"); goto next_cell; } if (input.match("11 ")) ACTION_DO_Y(1); @@ -459,8 +459,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (cell->type == "$eq" || cell->type == "$ne" || cell->type == "$eqx" || cell->type == "$nex") { - RTLIL::SigSpec a = cell->connections["\\A"]; - RTLIL::SigSpec b = cell->connections["\\B"]; + RTLIL::SigSpec a = cell->connections_["\\A"]; + RTLIL::SigSpec b = cell->connections_["\\B"]; if (cell->parameters["\\A_WIDTH"].as_int() != cell->parameters["\\B_WIDTH"].as_int()) { int width = std::max(cell->parameters["\\A_WIDTH"].as_int(), cell->parameters["\\B_WIDTH"].as_int()); @@ -495,8 +495,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (new_a.size() < a.size() || new_b.size() < b.size()) { cover_list("opt.opt_const.eqneq.resize", "$eq", "$ne", "$eqx", "$nex", cell->type); - cell->connections["\\A"] = new_a; - cell->connections["\\B"] = new_b; + cell->connections_["\\A"] = new_a; + cell->connections_["\\B"] = new_b; cell->parameters["\\A_WIDTH"] = new_a.size(); cell->parameters["\\B_WIDTH"] = new_b.size(); } @@ -505,24 +505,24 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if ((cell->type == "$eq" || cell->type == "$ne") && cell->parameters["\\Y_WIDTH"].as_int() == 1 && cell->parameters["\\A_WIDTH"].as_int() == 1 && cell->parameters["\\B_WIDTH"].as_int() == 1) { - RTLIL::SigSpec a = assign_map(cell->connections["\\A"]); - RTLIL::SigSpec b = assign_map(cell->connections["\\B"]); + RTLIL::SigSpec a = assign_map(cell->connections_["\\A"]); + RTLIL::SigSpec b = assign_map(cell->connections_["\\B"]); if (a.is_fully_const()) { cover_list("opt.opt_const.eqneq.swapconst", "$eq", "$ne", cell->type); - std::swap(cell->connections["\\A"], cell->connections["\\B"]); + std::swap(cell->connections_["\\A"], cell->connections_["\\B"]); } if (b.is_fully_const()) { if (b.as_bool() == (cell->type == "$eq")) { RTLIL::SigSpec input = b; - ACTION_DO("\\Y", cell->connections["\\A"]); + ACTION_DO("\\Y", cell->connections_["\\A"]); } else { cover_list("opt.opt_const.eqneq.isnot", "$eq", "$ne", cell->type); cell->type = "$not"; cell->parameters.erase("\\B_WIDTH"); cell->parameters.erase("\\B_SIGNED"); - cell->connections.erase("\\B"); + cell->connections_.erase("\\B"); } goto next_cell; } @@ -536,8 +536,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (cell->type == "$add" || cell->type == "$sub" || cell->type == "$or" || cell->type == "$xor") { - RTLIL::SigSpec a = assign_map(cell->connections["\\A"]); - RTLIL::SigSpec b = assign_map(cell->connections["\\B"]); + RTLIL::SigSpec a = assign_map(cell->connections_["\\A"]); + RTLIL::SigSpec b = assign_map(cell->connections_["\\B"]); if (cell->type != "$sub" && a.is_fully_const() && a.as_bool() == false) identity_wrt_b = true; @@ -548,7 +548,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr") { - RTLIL::SigSpec b = assign_map(cell->connections["\\B"]); + RTLIL::SigSpec b = assign_map(cell->connections_["\\B"]); if (b.is_fully_const() && b.as_bool() == false) identity_wrt_a = true, identity_bu0 = true; @@ -556,8 +556,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (cell->type == "$mul") { - RTLIL::SigSpec a = assign_map(cell->connections["\\A"]); - RTLIL::SigSpec b = assign_map(cell->connections["\\B"]); + RTLIL::SigSpec a = assign_map(cell->connections_["\\A"]); + RTLIL::SigSpec b = assign_map(cell->connections_["\\B"]); if (a.is_fully_const() && a.size() <= 32 && a.as_int() == 1) identity_wrt_b = true; @@ -568,7 +568,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (cell->type == "$div") { - RTLIL::SigSpec b = assign_map(cell->connections["\\B"]); + RTLIL::SigSpec b = assign_map(cell->connections_["\\B"]); if (b.is_fully_const() && b.size() <= 32 && b.as_int() == 1) identity_wrt_a = true; @@ -585,13 +585,13 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cell->type.c_str(), cell->name.c_str(), module->name.c_str(), identity_wrt_a ? 'A' : 'B'); if (!identity_wrt_a) { - cell->connections.at("\\A") = cell->connections.at("\\B"); + cell->connections_.at("\\A") = cell->connections_.at("\\B"); cell->parameters.at("\\A_WIDTH") = cell->parameters.at("\\B_WIDTH"); cell->parameters.at("\\A_SIGNED") = cell->parameters.at("\\B_SIGNED"); } cell->type = identity_bu0 ? "$bu0" : "$pos"; - cell->connections.erase("\\B"); + cell->connections_.erase("\\B"); cell->parameters.erase("\\B_WIDTH"); cell->parameters.erase("\\B_SIGNED"); cell->check(); @@ -603,18 +603,18 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo } if (mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && - cell->connections["\\A"] == RTLIL::SigSpec(0, 1) && cell->connections["\\B"] == RTLIL::SigSpec(1, 1)) { + cell->connections_["\\A"] == RTLIL::SigSpec(0, 1) && cell->connections_["\\B"] == RTLIL::SigSpec(1, 1)) { cover_list("opt.opt_const.mux_bool", "$mux", "$_MUX_", cell->type); - replace_cell(module, cell, "mux_bool", "\\Y", cell->connections["\\S"]); + replace_cell(module, cell, "mux_bool", "\\Y", cell->connections_["\\S"]); goto next_cell; } if (mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && - cell->connections["\\A"] == RTLIL::SigSpec(1, 1) && cell->connections["\\B"] == RTLIL::SigSpec(0, 1)) { + cell->connections_["\\A"] == RTLIL::SigSpec(1, 1) && cell->connections_["\\B"] == RTLIL::SigSpec(0, 1)) { cover_list("opt.opt_const.mux_invert", "$mux", "$_MUX_", cell->type); - cell->connections["\\A"] = cell->connections["\\S"]; - cell->connections.erase("\\B"); - cell->connections.erase("\\S"); + cell->connections_["\\A"] = cell->connections_["\\S"]; + cell->connections_.erase("\\B"); + cell->connections_.erase("\\S"); if (cell->type == "$mux") { cell->parameters["\\A_WIDTH"] = cell->parameters["\\WIDTH"]; cell->parameters["\\Y_WIDTH"] = cell->parameters["\\WIDTH"]; @@ -628,10 +628,10 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo goto next_cell; } - if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->connections["\\A"] == RTLIL::SigSpec(0, 1)) { + if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->connections_["\\A"] == RTLIL::SigSpec(0, 1)) { cover_list("opt.opt_const.mux_and", "$mux", "$_MUX_", cell->type); - cell->connections["\\A"] = cell->connections["\\S"]; - cell->connections.erase("\\S"); + cell->connections_["\\A"] = cell->connections_["\\S"]; + cell->connections_.erase("\\S"); if (cell->type == "$mux") { cell->parameters["\\A_WIDTH"] = cell->parameters["\\WIDTH"]; cell->parameters["\\B_WIDTH"] = cell->parameters["\\WIDTH"]; @@ -647,10 +647,10 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo goto next_cell; } - if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->connections["\\B"] == RTLIL::SigSpec(1, 1)) { + if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->connections_["\\B"] == RTLIL::SigSpec(1, 1)) { cover_list("opt.opt_const.mux_or", "$mux", "$_MUX_", cell->type); - cell->connections["\\B"] = cell->connections["\\S"]; - cell->connections.erase("\\S"); + cell->connections_["\\B"] = cell->connections_["\\S"]; + cell->connections_.erase("\\S"); if (cell->type == "$mux") { cell->parameters["\\A_WIDTH"] = cell->parameters["\\WIDTH"]; cell->parameters["\\B_WIDTH"] = cell->parameters["\\WIDTH"]; @@ -668,22 +668,22 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (mux_undef && (cell->type == "$mux" || cell->type == "$pmux")) { RTLIL::SigSpec new_a, new_b, new_s; - int width = cell->connections.at("\\A").size(); - if ((cell->connections.at("\\A").is_fully_undef() && cell->connections.at("\\B").is_fully_undef()) || - cell->connections.at("\\S").is_fully_undef()) { + int width = cell->connections_.at("\\A").size(); + if ((cell->connections_.at("\\A").is_fully_undef() && cell->connections_.at("\\B").is_fully_undef()) || + cell->connections_.at("\\S").is_fully_undef()) { cover_list("opt.opt_const.mux_undef", "$mux", "$pmux", cell->type); - replace_cell(module, cell, "mux_undef", "\\Y", cell->connections.at("\\A")); + replace_cell(module, cell, "mux_undef", "\\Y", cell->connections_.at("\\A")); goto next_cell; } - for (int i = 0; i < cell->connections.at("\\S").size(); i++) { - RTLIL::SigSpec old_b = cell->connections.at("\\B").extract(i*width, width); - RTLIL::SigSpec old_s = cell->connections.at("\\S").extract(i, 1); + for (int i = 0; i < cell->connections_.at("\\S").size(); i++) { + RTLIL::SigSpec old_b = cell->connections_.at("\\B").extract(i*width, width); + RTLIL::SigSpec old_s = cell->connections_.at("\\S").extract(i, 1); if (old_b.is_fully_undef() || old_s.is_fully_undef()) continue; new_b.append(old_b); new_s.append(old_s); } - new_a = cell->connections.at("\\A"); + new_a = cell->connections_.at("\\A"); if (new_a.is_fully_undef() && new_s.size() > 0) { new_a = new_b.extract((new_s.size()-1)*width, width); new_b = new_b.extract(0, (new_s.size()-1)*width); @@ -699,11 +699,11 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo replace_cell(module, cell, "mux_sel01", "\\Y", new_s); goto next_cell; } - if (cell->connections.at("\\S").size() != new_s.size()) { + if (cell->connections_.at("\\S").size() != new_s.size()) { cover_list("opt.opt_const.mux_reduce", "$mux", "$pmux", cell->type); - cell->connections.at("\\A") = new_a; - cell->connections.at("\\B") = new_b; - cell->connections.at("\\S") = new_s; + cell->connections_.at("\\A") = new_a; + cell->connections_.at("\\B") = new_b; + cell->connections_.at("\\S") = new_s; if (new_s.size() > 1) { cell->type = "$pmux"; cell->parameters["\\S_WIDTH"] = new_s.size(); @@ -718,7 +718,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo #define FOLD_1ARG_CELL(_t) \ if (cell->type == "$" #_t) { \ - RTLIL::SigSpec a = cell->connections["\\A"]; \ + RTLIL::SigSpec a = cell->connections_["\\A"]; \ assign_map.apply(a); \ if (a.is_fully_const()) { \ RTLIL::Const dummy_arg(RTLIL::State::S0, 1); \ @@ -732,8 +732,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo } #define FOLD_2ARG_CELL(_t) \ if (cell->type == "$" #_t) { \ - RTLIL::SigSpec a = cell->connections["\\A"]; \ - RTLIL::SigSpec b = cell->connections["\\B"]; \ + RTLIL::SigSpec a = cell->connections_["\\A"]; \ + RTLIL::SigSpec b = cell->connections_["\\B"]; \ assign_map.apply(a), assign_map.apply(b); \ if (a.is_fully_const() && b.is_fully_const()) { \ RTLIL::SigSpec y(RTLIL::const_ ## _t(a.as_const(), b.as_const(), \ @@ -787,13 +787,13 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo // be very conservative with optimizing $mux cells as we do not want to break mux trees if (cell->type == "$mux") { - RTLIL::SigSpec input = assign_map(cell->connections["\\S"]); - RTLIL::SigSpec inA = assign_map(cell->connections["\\A"]); - RTLIL::SigSpec inB = assign_map(cell->connections["\\B"]); + RTLIL::SigSpec input = assign_map(cell->connections_["\\S"]); + RTLIL::SigSpec inA = assign_map(cell->connections_["\\A"]); + RTLIL::SigSpec inB = assign_map(cell->connections_["\\B"]); if (input.is_fully_const()) - ACTION_DO("\\Y", input.as_bool() ? cell->connections["\\B"] : cell->connections["\\A"]); + ACTION_DO("\\Y", input.as_bool() ? cell->connections_["\\B"] : cell->connections_["\\A"]); else if (inA == inB) - ACTION_DO("\\Y", cell->connections["\\A"]); + ACTION_DO("\\Y", cell->connections_["\\A"]); } if (!keepdc && cell->type == "$mul") @@ -802,9 +802,9 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo bool b_signed = cell->parameters["\\B_SIGNED"].as_bool(); bool swapped_ab = false; - RTLIL::SigSpec sig_a = assign_map(cell->connections["\\A"]); - RTLIL::SigSpec sig_b = assign_map(cell->connections["\\B"]); - RTLIL::SigSpec sig_y = assign_map(cell->connections["\\Y"]); + RTLIL::SigSpec sig_a = assign_map(cell->connections_["\\A"]); + RTLIL::SigSpec sig_b = assign_map(cell->connections_["\\B"]); + RTLIL::SigSpec sig_y = assign_map(cell->connections_["\\Y"]); if (sig_b.is_fully_const() && sig_b.size() <= 32) std::swap(sig_a, sig_b), std::swap(a_signed, b_signed), swapped_ab = true; @@ -820,7 +820,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo log("Replacing multiply-by-zero cell `%s' in module `%s' with zero-driver.\n", cell->name.c_str(), module->name.c_str()); - module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size()))); + module->connections_.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size()))); module->remove(cell); OPT_DID_SOMETHING = true; @@ -840,7 +840,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo a_val, cell->name.c_str(), module->name.c_str(), i); if (!swapped_ab) { - cell->connections["\\A"] = cell->connections["\\B"]; + cell->connections_["\\A"] = cell->connections_["\\B"]; cell->parameters["\\A_WIDTH"] = cell->parameters["\\B_WIDTH"]; cell->parameters["\\A_SIGNED"] = cell->parameters["\\B_SIGNED"]; } @@ -853,7 +853,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cell->type = "$shl"; cell->parameters["\\B_WIDTH"] = SIZE(new_b); cell->parameters["\\B_SIGNED"] = false; - cell->connections["\\B"] = new_b; + cell->connections_["\\B"] = new_b; cell->check(); OPT_DID_SOMETHING = true; diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc index 750a9d417..33e66e077 100644 --- a/passes/opt/opt_muxtree.cc +++ b/passes/opt/opt_muxtree.cc @@ -88,10 +88,10 @@ struct OptMuxtreeWorker RTLIL::Cell *cell = cell_it.second; if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux") { - RTLIL::SigSpec sig_a = cell->connections["\\A"]; - RTLIL::SigSpec sig_b = cell->connections["\\B"]; - RTLIL::SigSpec sig_s = cell->connections["\\S"]; - RTLIL::SigSpec sig_y = cell->connections["\\Y"]; + RTLIL::SigSpec sig_a = cell->connections_["\\A"]; + RTLIL::SigSpec sig_b = cell->connections_["\\B"]; + RTLIL::SigSpec sig_s = cell->connections_["\\S"]; + RTLIL::SigSpec sig_y = cell->connections_["\\Y"]; muxinfo_t muxinfo; muxinfo.cell = cell; @@ -130,7 +130,7 @@ struct OptMuxtreeWorker } else { - for (auto &it : cell->connections) { + for (auto &it : cell->connections_) { for (int idx : sig2bits(it.second)) bit2info[idx].seen_non_mux = true; } @@ -194,10 +194,10 @@ struct OptMuxtreeWorker continue; } - RTLIL::SigSpec sig_a = mi.cell->connections["\\A"]; - RTLIL::SigSpec sig_b = mi.cell->connections["\\B"]; - RTLIL::SigSpec sig_s = mi.cell->connections["\\S"]; - RTLIL::SigSpec sig_y = mi.cell->connections["\\Y"]; + RTLIL::SigSpec sig_a = mi.cell->connections_["\\A"]; + RTLIL::SigSpec sig_b = mi.cell->connections_["\\B"]; + RTLIL::SigSpec sig_s = mi.cell->connections_["\\S"]; + RTLIL::SigSpec sig_y = mi.cell->connections_["\\Y"]; RTLIL::SigSpec sig_ports = sig_b; sig_ports.append(sig_a); @@ -205,7 +205,7 @@ struct OptMuxtreeWorker if (live_ports.size() == 1) { RTLIL::SigSpec sig_in = sig_ports.extract(live_ports[0]*sig_a.size(), sig_a.size()); - module->connections.push_back(RTLIL::SigSig(sig_y, sig_in)); + module->connections_.push_back(RTLIL::SigSig(sig_y, sig_in)); module->remove(mi.cell); } else @@ -222,9 +222,9 @@ struct OptMuxtreeWorker } } - mi.cell->connections["\\A"] = new_sig_a; - mi.cell->connections["\\B"] = new_sig_b; - mi.cell->connections["\\S"] = new_sig_s; + mi.cell->connections_["\\A"] = new_sig_a; + mi.cell->connections_["\\B"] = new_sig_b; + mi.cell->connections_["\\S"] = new_sig_s; if (new_sig_s.size() == 1) { mi.cell->type = "$mux"; mi.cell->parameters.erase("\\S_WIDTH"); diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc index 073af3087..7a7f02f6d 100644 --- a/passes/opt/opt_reduce.cc +++ b/passes/opt/opt_reduce.cc @@ -43,7 +43,7 @@ struct OptReduceWorker return; cells.erase(cell); - RTLIL::SigSpec sig_a = assign_map(cell->connections["\\A"]); + RTLIL::SigSpec sig_a = assign_map(cell->connections_["\\A"]); std::set new_sig_a_bits; for (auto &bit : sig_a.to_sigbit_set()) @@ -73,8 +73,8 @@ struct OptReduceWorker for (auto child_cell : drivers.find(bit)) { if (child_cell->type == cell->type) { opt_reduce(cells, drivers, child_cell); - if (child_cell->connections["\\Y"][0] == bit) { - std::set child_sig_a_bits = assign_map(child_cell->connections["\\A"]).to_sigbit_set(); + if (child_cell->connections_["\\Y"][0] == bit) { + std::set child_sig_a_bits = assign_map(child_cell->connections_["\\A"]).to_sigbit_set(); new_sig_a_bits.insert(child_sig_a_bits.begin(), child_sig_a_bits.end()); } else new_sig_a_bits.insert(RTLIL::State::S0); @@ -87,23 +87,23 @@ struct OptReduceWorker RTLIL::SigSpec new_sig_a(new_sig_a_bits); - if (new_sig_a != sig_a || sig_a.size() != cell->connections["\\A"].size()) { + if (new_sig_a != sig_a || sig_a.size() != cell->connections_["\\A"].size()) { log(" New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a)); did_something = true; OPT_DID_SOMETHING = true; total_count++; } - cell->connections["\\A"] = new_sig_a; + cell->connections_["\\A"] = new_sig_a; cell->parameters["\\A_WIDTH"] = RTLIL::Const(new_sig_a.size()); return; } void opt_mux(RTLIL::Cell *cell) { - RTLIL::SigSpec sig_a = assign_map(cell->connections["\\A"]); - RTLIL::SigSpec sig_b = assign_map(cell->connections["\\B"]); - RTLIL::SigSpec sig_s = assign_map(cell->connections["\\S"]); + RTLIL::SigSpec sig_a = assign_map(cell->connections_["\\A"]); + RTLIL::SigSpec sig_b = assign_map(cell->connections_["\\B"]); + RTLIL::SigSpec sig_s = assign_map(cell->connections_["\\S"]); RTLIL::SigSpec new_sig_b, new_sig_s; std::set handled_sig; @@ -125,14 +125,14 @@ struct OptReduceWorker if (this_s.size() > 1) { RTLIL::Cell *reduce_or_cell = module->addCell(NEW_ID, "$reduce_or"); - reduce_or_cell->connections["\\A"] = this_s; + reduce_or_cell->connections_["\\A"] = this_s; reduce_or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); reduce_or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(this_s.size()); reduce_or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); RTLIL::Wire *reduce_or_wire = module->addWire(NEW_ID); this_s = RTLIL::SigSpec(reduce_or_wire); - reduce_or_cell->connections["\\Y"] = this_s; + reduce_or_cell->connections_["\\Y"] = this_s; } new_sig_b.append(this_b); @@ -149,14 +149,14 @@ struct OptReduceWorker if (new_sig_s.size() == 0) { - module->connections.push_back(RTLIL::SigSig(cell->connections["\\Y"], cell->connections["\\A"])); - assign_map.add(cell->connections["\\Y"], cell->connections["\\A"]); + module->connections_.push_back(RTLIL::SigSig(cell->connections_["\\Y"], cell->connections_["\\A"])); + assign_map.add(cell->connections_["\\Y"], cell->connections_["\\A"]); module->remove(cell); } else { - cell->connections["\\B"] = new_sig_b; - cell->connections["\\S"] = new_sig_s; + cell->connections_["\\B"] = new_sig_b; + cell->connections_["\\S"] = new_sig_s; if (new_sig_s.size() > 1) { cell->parameters["\\S_WIDTH"] = RTLIL::Const(new_sig_s.size()); } else { @@ -168,9 +168,9 @@ struct OptReduceWorker void opt_mux_bits(RTLIL::Cell *cell) { - std::vector sig_a = assign_map(cell->connections["\\A"]).to_sigbit_vector(); - std::vector sig_b = assign_map(cell->connections["\\B"]).to_sigbit_vector(); - std::vector sig_y = assign_map(cell->connections["\\Y"]).to_sigbit_vector(); + std::vector sig_a = assign_map(cell->connections_["\\A"]).to_sigbit_vector(); + std::vector sig_b = assign_map(cell->connections_["\\B"]).to_sigbit_vector(); + std::vector sig_y = assign_map(cell->connections_["\\Y"]).to_sigbit_vector(); std::vector new_sig_y; RTLIL::SigSig old_sig_conn; @@ -211,26 +211,26 @@ struct OptReduceWorker if (new_sig_y.size() != sig_y.size()) { log(" Consolidated identical input bits for %s cell %s:\n", cell->type.c_str(), cell->name.c_str()); - log(" Old ports: A=%s, B=%s, Y=%s\n", log_signal(cell->connections["\\A"]), - log_signal(cell->connections["\\B"]), log_signal(cell->connections["\\Y"])); + log(" Old ports: A=%s, B=%s, Y=%s\n", log_signal(cell->connections_["\\A"]), + log_signal(cell->connections_["\\B"]), log_signal(cell->connections_["\\Y"])); - cell->connections["\\A"] = RTLIL::SigSpec(); + cell->connections_["\\A"] = RTLIL::SigSpec(); for (auto &in_tuple : consolidated_in_tuples) - cell->connections["\\A"].append(in_tuple.at(0)); + cell->connections_["\\A"].append(in_tuple.at(0)); - cell->connections["\\B"] = RTLIL::SigSpec(); - for (int i = 1; i <= cell->connections["\\S"].size(); i++) + cell->connections_["\\B"] = RTLIL::SigSpec(); + for (int i = 1; i <= cell->connections_["\\S"].size(); i++) for (auto &in_tuple : consolidated_in_tuples) - cell->connections["\\B"].append(in_tuple.at(i)); + cell->connections_["\\B"].append(in_tuple.at(i)); cell->parameters["\\WIDTH"] = RTLIL::Const(new_sig_y.size()); - cell->connections["\\Y"] = new_sig_y; + cell->connections_["\\Y"] = new_sig_y; - log(" New ports: A=%s, B=%s, Y=%s\n", log_signal(cell->connections["\\A"]), - log_signal(cell->connections["\\B"]), log_signal(cell->connections["\\Y"])); + log(" New ports: A=%s, B=%s, Y=%s\n", log_signal(cell->connections_["\\A"]), + log_signal(cell->connections_["\\B"]), log_signal(cell->connections_["\\Y"])); log(" New connections: %s = %s\n", log_signal(old_sig_conn.first), log_signal(old_sig_conn.second)); - module->connections.push_back(old_sig_conn); + module->connections_.push_back(old_sig_conn); module->check(); did_something = true; @@ -251,14 +251,14 @@ struct OptReduceWorker for (auto &cell_it : module->cells) { RTLIL::Cell *cell = cell_it.second; if (cell->type == "$mem") - mem_wren_sigs.add(assign_map(cell->connections["\\WR_EN"])); + mem_wren_sigs.add(assign_map(cell->connections_["\\WR_EN"])); if (cell->type == "$memwr") - mem_wren_sigs.add(assign_map(cell->connections["\\EN"])); + mem_wren_sigs.add(assign_map(cell->connections_["\\EN"])); } for (auto &cell_it : module->cells) { RTLIL::Cell *cell = cell_it.second; - if (cell->type == "$dff" && mem_wren_sigs.check_any(assign_map(cell->connections["\\Q"]))) - mem_wren_sigs.add(assign_map(cell->connections["\\D"])); + if (cell->type == "$dff" && mem_wren_sigs.check_any(assign_map(cell->connections_["\\Q"]))) + mem_wren_sigs.add(assign_map(cell->connections_["\\D"])); } bool keep_expanding_mem_wren_sigs = true; @@ -266,12 +266,12 @@ struct OptReduceWorker keep_expanding_mem_wren_sigs = false; for (auto &cell_it : module->cells) { RTLIL::Cell *cell = cell_it.second; - if (cell->type == "$mux" && mem_wren_sigs.check_any(assign_map(cell->connections["\\Y"]))) { - if (!mem_wren_sigs.check_all(assign_map(cell->connections["\\A"])) || - !mem_wren_sigs.check_all(assign_map(cell->connections["\\B"]))) + if (cell->type == "$mux" && mem_wren_sigs.check_any(assign_map(cell->connections_["\\Y"]))) { + if (!mem_wren_sigs.check_all(assign_map(cell->connections_["\\A"])) || + !mem_wren_sigs.check_all(assign_map(cell->connections_["\\B"]))) keep_expanding_mem_wren_sigs = true; - mem_wren_sigs.add(assign_map(cell->connections["\\A"])); - mem_wren_sigs.add(assign_map(cell->connections["\\B"])); + mem_wren_sigs.add(assign_map(cell->connections_["\\A"])); + mem_wren_sigs.add(assign_map(cell->connections_["\\B"])); } } } @@ -293,7 +293,7 @@ struct OptReduceWorker RTLIL::Cell *cell = cell_it.second; if (cell->type != type || !design->selected(module, cell)) continue; - drivers.insert(assign_map(cell->connections["\\Y"]), cell); + drivers.insert(assign_map(cell->connections_["\\Y"]), cell); cells.insert(cell); } @@ -315,7 +315,7 @@ struct OptReduceWorker { // this optimization is to aggressive for most coarse-grain applications. // but we always want it for multiplexers driving write enable ports. - if (do_fine || mem_wren_sigs.check_any(assign_map(cell->connections.at("\\Y")))) + if (do_fine || mem_wren_sigs.check_any(assign_map(cell->connections_.at("\\Y")))) opt_mux_bits(cell); opt_mux(cell); diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc index 6a35cb618..4ece182f4 100644 --- a/passes/opt/opt_rmdff.cc +++ b/passes/opt/opt_rmdff.cc @@ -33,34 +33,34 @@ static bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) RTLIL::Const val_cp, val_rp, val_rv; if (dff->type == "$_DFF_N_" || dff->type == "$_DFF_P_") { - sig_d = dff->connections["\\D"]; - sig_q = dff->connections["\\Q"]; - sig_c = dff->connections["\\C"]; + sig_d = dff->connections_["\\D"]; + sig_q = dff->connections_["\\Q"]; + sig_c = dff->connections_["\\C"]; val_cp = RTLIL::Const(dff->type == "$_DFF_P_", 1); } else if (dff->type.substr(0,6) == "$_DFF_" && dff->type.substr(9) == "_" && (dff->type[6] == 'N' || dff->type[6] == 'P') && (dff->type[7] == 'N' || dff->type[7] == 'P') && (dff->type[8] == '0' || dff->type[8] == '1')) { - sig_d = dff->connections["\\D"]; - sig_q = dff->connections["\\Q"]; - sig_c = dff->connections["\\C"]; - sig_r = dff->connections["\\R"]; + sig_d = dff->connections_["\\D"]; + sig_q = dff->connections_["\\Q"]; + sig_c = dff->connections_["\\C"]; + sig_r = dff->connections_["\\R"]; val_cp = RTLIL::Const(dff->type[6] == 'P', 1); val_rp = RTLIL::Const(dff->type[7] == 'P', 1); val_rv = RTLIL::Const(dff->type[8] == '1', 1); } else if (dff->type == "$dff") { - sig_d = dff->connections["\\D"]; - sig_q = dff->connections["\\Q"]; - sig_c = dff->connections["\\CLK"]; + sig_d = dff->connections_["\\D"]; + sig_q = dff->connections_["\\Q"]; + sig_c = dff->connections_["\\CLK"]; val_cp = RTLIL::Const(dff->parameters["\\CLK_POLARITY"].as_bool(), 1); } else if (dff->type == "$adff") { - sig_d = dff->connections["\\D"]; - sig_q = dff->connections["\\Q"]; - sig_c = dff->connections["\\CLK"]; - sig_r = dff->connections["\\ARST"]; + sig_d = dff->connections_["\\D"]; + sig_q = dff->connections_["\\Q"]; + sig_c = dff->connections_["\\CLK"]; + sig_r = dff->connections_["\\ARST"]; val_cp = RTLIL::Const(dff->parameters["\\CLK_POLARITY"].as_bool(), 1); val_rp = RTLIL::Const(dff->parameters["\\ARST_POLARITY"].as_bool(), 1); val_rv = dff->parameters["\\ARST_VALUE"]; @@ -85,16 +85,16 @@ static bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) std::set muxes; mux_drivers.find(sig_d, muxes); for (auto mux : muxes) { - RTLIL::SigSpec sig_a = assign_map(mux->connections.at("\\A")); - RTLIL::SigSpec sig_b = assign_map(mux->connections.at("\\B")); + RTLIL::SigSpec sig_a = assign_map(mux->connections_.at("\\A")); + RTLIL::SigSpec sig_b = assign_map(mux->connections_.at("\\B")); if (sig_a == sig_q && sig_b.is_fully_const()) { RTLIL::SigSig conn(sig_q, sig_b); - mod->connections.push_back(conn); + mod->connections_.push_back(conn); goto delete_dff; } if (sig_b == sig_q && sig_a.is_fully_const()) { RTLIL::SigSig conn(sig_q, sig_a); - mod->connections.push_back(conn); + mod->connections_.push_back(conn); goto delete_dff; } } @@ -104,36 +104,36 @@ static bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) if (val_rv.bits.size() == 0) val_rv = val_init; RTLIL::SigSig conn(sig_q, val_rv); - mod->connections.push_back(conn); + mod->connections_.push_back(conn); goto delete_dff; } if (sig_d.is_fully_undef() && sig_r.size() && !has_init) { RTLIL::SigSig conn(sig_q, val_rv); - mod->connections.push_back(conn); + mod->connections_.push_back(conn); goto delete_dff; } if (sig_d.is_fully_undef() && !sig_r.size() && has_init) { RTLIL::SigSig conn(sig_q, val_init); - mod->connections.push_back(conn); + mod->connections_.push_back(conn); goto delete_dff; } if (sig_d.is_fully_const() && !sig_r.size() && !has_init) { RTLIL::SigSig conn(sig_q, sig_d); - mod->connections.push_back(conn); + mod->connections_.push_back(conn); goto delete_dff; } if (sig_d == sig_q && !(sig_r.size() && has_init)) { if (sig_r.size()) { RTLIL::SigSig conn(sig_q, val_rv); - mod->connections.push_back(conn); + mod->connections_.push_back(conn); } if (has_init) { RTLIL::SigSig conn(sig_q, val_init); - mod->connections.push_back(conn); + mod->connections_.push_back(conn); } goto delete_dff; } @@ -181,8 +181,8 @@ struct OptRmdffPass : public Pass { std::vector dff_list; for (auto &it : mod_it.second->cells) { if (it.second->type == "$mux" || it.second->type == "$pmux") { - if (it.second->connections.at("\\A").size() == it.second->connections.at("\\B").size()) - mux_drivers.insert(assign_map(it.second->connections.at("\\Y")), it.second); + if (it.second->connections_.at("\\A").size() == it.second->connections_.at("\\B").size()) + mux_drivers.insert(assign_map(it.second->connections_.at("\\Y")), it.second); continue; } if (!design->selected(mod_it.second, it.second)) diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc index e3e9511fd..b3a37209b 100644 --- a/passes/opt/opt_share.cc +++ b/passes/opt/opt_share.cc @@ -66,7 +66,7 @@ struct OptShareWorker for (auto &it : cell->parameters) hash_string += "P " + it.first + "=" + it.second.as_string() + "\n"; - const std::map *conn = &cell->connections; + const std::map *conn = &cell->connections_; std::map alt_conn; if (cell->type == "$and" || cell->type == "$or" || cell->type == "$xor" || cell->type == "$xnor" || cell->type == "$add" || cell->type == "$mul" || @@ -135,8 +135,8 @@ struct OptShareWorker return true; } - std::map conn1 = cell1->connections; - std::map conn2 = cell2->connections; + std::map conn1 = cell1->connections_; + std::map conn2 = cell2->connections_; for (auto &it : conn1) { if (ct.cell_output(cell1->type, it.first)) @@ -180,8 +180,8 @@ struct OptShareWorker } if (cell1->type.substr(0, 1) == "$" && conn1.count("\\Q") != 0) { - std::vector q1 = dff_init_map(cell1->connections.at("\\Q")).to_sigbit_vector(); - std::vector q2 = dff_init_map(cell2->connections.at("\\Q")).to_sigbit_vector(); + std::vector q1 = dff_init_map(cell1->connections_.at("\\Q")).to_sigbit_vector(); + std::vector q2 = dff_init_map(cell2->connections_.at("\\Q")).to_sigbit_vector(); for (size_t i = 0; i < q1.size(); i++) if ((q1.at(i).wire == NULL || q2.at(i).wire == NULL) && q1.at(i) != q2.at(i)) { lt = q1.at(i) < q2.at(i); @@ -261,12 +261,12 @@ struct OptShareWorker if (sharemap.count(cell) > 0) { did_something = true; log(" Cell `%s' is identical to cell `%s'.\n", cell->name.c_str(), sharemap[cell]->name.c_str()); - for (auto &it : cell->connections) { + for (auto &it : cell->connections_) { if (ct.cell_output(cell->type, it.first)) { - RTLIL::SigSpec other_sig = sharemap[cell]->connections[it.first]; + RTLIL::SigSpec other_sig = sharemap[cell]->connections_[it.first]; log(" Redirecting output %s: %s = %s\n", it.first.c_str(), log_signal(it.second), log_signal(other_sig)); - module->connections.push_back(RTLIL::SigSig(it.second, other_sig)); + module->connections_.push_back(RTLIL::SigSig(it.second, other_sig)); assign_map.add(it.second, other_sig); } } diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc index 145abfa43..ce3133601 100644 --- a/passes/proc/proc_arst.cc +++ b/passes/proc/proc_arst.cc @@ -35,40 +35,40 @@ static bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSp for (auto &cell_it : mod->cells) { RTLIL::Cell *cell = cell_it.second; - if (cell->type == "$reduce_or" && cell->connections["\\Y"] == signal) - return check_signal(mod, cell->connections["\\A"], ref, polarity); - if (cell->type == "$reduce_bool" && cell->connections["\\Y"] == signal) - return check_signal(mod, cell->connections["\\A"], ref, polarity); - if (cell->type == "$logic_not" && cell->connections["\\Y"] == signal) { + if (cell->type == "$reduce_or" && cell->connections_["\\Y"] == signal) + return check_signal(mod, cell->connections_["\\A"], ref, polarity); + if (cell->type == "$reduce_bool" && cell->connections_["\\Y"] == signal) + return check_signal(mod, cell->connections_["\\A"], ref, polarity); + if (cell->type == "$logic_not" && cell->connections_["\\Y"] == signal) { polarity = !polarity; - return check_signal(mod, cell->connections["\\A"], ref, polarity); + return check_signal(mod, cell->connections_["\\A"], ref, polarity); } - if (cell->type == "$not" && cell->connections["\\Y"] == signal) { + if (cell->type == "$not" && cell->connections_["\\Y"] == signal) { polarity = !polarity; - return check_signal(mod, cell->connections["\\A"], ref, polarity); + return check_signal(mod, cell->connections_["\\A"], ref, polarity); } - if ((cell->type == "$eq" || cell->type == "$eqx") && cell->connections["\\Y"] == signal) { - if (cell->connections["\\A"].is_fully_const()) { - if (!cell->connections["\\A"].as_bool()) + if ((cell->type == "$eq" || cell->type == "$eqx") && cell->connections_["\\Y"] == signal) { + if (cell->connections_["\\A"].is_fully_const()) { + if (!cell->connections_["\\A"].as_bool()) polarity = !polarity; - return check_signal(mod, cell->connections["\\B"], ref, polarity); + return check_signal(mod, cell->connections_["\\B"], ref, polarity); } - if (cell->connections["\\B"].is_fully_const()) { - if (!cell->connections["\\B"].as_bool()) + if (cell->connections_["\\B"].is_fully_const()) { + if (!cell->connections_["\\B"].as_bool()) polarity = !polarity; - return check_signal(mod, cell->connections["\\A"], ref, polarity); + return check_signal(mod, cell->connections_["\\A"], ref, polarity); } } - if ((cell->type == "$ne" || cell->type == "$nex") && cell->connections["\\Y"] == signal) { - if (cell->connections["\\A"].is_fully_const()) { - if (cell->connections["\\A"].as_bool()) + if ((cell->type == "$ne" || cell->type == "$nex") && cell->connections_["\\Y"] == signal) { + if (cell->connections_["\\A"].is_fully_const()) { + if (cell->connections_["\\A"].as_bool()) polarity = !polarity; - return check_signal(mod, cell->connections["\\B"], ref, polarity); + return check_signal(mod, cell->connections_["\\B"], ref, polarity); } - if (cell->connections["\\B"].is_fully_const()) { - if (cell->connections["\\B"].as_bool()) + if (cell->connections_["\\B"].is_fully_const()) { + if (cell->connections_["\\B"].as_bool()) polarity = !polarity; - return check_signal(mod, cell->connections["\\A"], ref, polarity); + return check_signal(mod, cell->connections_["\\A"], ref, polarity); } } } diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index 876adb0db..9d2c897ee 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -77,8 +77,8 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.size()); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - cell->connections["\\A"] = sync_low_signals; - cell->connections["\\Y"] = sync_low_signals = mod->addWire(NEW_ID); + cell->connections_["\\A"] = sync_low_signals; + cell->connections_["\\Y"] = sync_low_signals = mod->addWire(NEW_ID); } if (sync_low_signals.size() > 0) { @@ -86,9 +86,9 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.size()); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - cell->connections["\\A"] = sync_low_signals; - cell->connections["\\Y"] = mod->addWire(NEW_ID); - sync_high_signals.append(cell->connections["\\Y"]); + cell->connections_["\\A"] = sync_low_signals; + cell->connections_["\\Y"] = mod->addWire(NEW_ID); + sync_high_signals.append(cell->connections_["\\Y"]); } if (sync_high_signals.size() > 1) { @@ -96,30 +96,30 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_high_signals.size()); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - cell->connections["\\A"] = sync_high_signals; - cell->connections["\\Y"] = sync_high_signals = mod->addWire(NEW_ID); + cell->connections_["\\A"] = sync_high_signals; + cell->connections_["\\Y"] = sync_high_signals = mod->addWire(NEW_ID); } RTLIL::Cell *inv_cell = mod->addCell(NEW_ID, "$not"); inv_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); inv_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_d.size()); inv_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_d.size()); - inv_cell->connections["\\A"] = sync_value; - inv_cell->connections["\\Y"] = sync_value_inv = mod->addWire(NEW_ID, sig_d.size()); + inv_cell->connections_["\\A"] = sync_value; + inv_cell->connections_["\\Y"] = sync_value_inv = mod->addWire(NEW_ID, sig_d.size()); RTLIL::Cell *mux_set_cell = mod->addCell(NEW_ID, "$mux"); mux_set_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size()); - mux_set_cell->connections["\\A"] = sig_sr_set; - mux_set_cell->connections["\\B"] = sync_value; - mux_set_cell->connections["\\S"] = sync_high_signals; - mux_set_cell->connections["\\Y"] = sig_sr_set = mod->addWire(NEW_ID, sig_d.size()); + mux_set_cell->connections_["\\A"] = sig_sr_set; + mux_set_cell->connections_["\\B"] = sync_value; + mux_set_cell->connections_["\\S"] = sync_high_signals; + mux_set_cell->connections_["\\Y"] = sig_sr_set = mod->addWire(NEW_ID, sig_d.size()); RTLIL::Cell *mux_clr_cell = mod->addCell(NEW_ID, "$mux"); mux_clr_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size()); - mux_clr_cell->connections["\\A"] = sig_sr_clr; - mux_clr_cell->connections["\\B"] = sync_value_inv; - mux_clr_cell->connections["\\S"] = sync_high_signals; - mux_clr_cell->connections["\\Y"] = sig_sr_clr = mod->addWire(NEW_ID, sig_d.size()); + mux_clr_cell->connections_["\\A"] = sig_sr_clr; + mux_clr_cell->connections_["\\B"] = sync_value_inv; + mux_clr_cell->connections_["\\S"] = sync_high_signals; + mux_clr_cell->connections_["\\Y"] = sig_sr_clr = mod->addWire(NEW_ID, sig_d.size()); } std::stringstream sstr; @@ -131,11 +131,11 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1); cell->parameters["\\SET_POLARITY"] = RTLIL::Const(true, 1); cell->parameters["\\CLR_POLARITY"] = RTLIL::Const(true, 1); - cell->connections["\\D"] = sig_d; - cell->connections["\\Q"] = sig_q; - cell->connections["\\CLK"] = clk; - cell->connections["\\SET"] = sig_sr_set; - cell->connections["\\CLR"] = sig_sr_clr; + cell->connections_["\\D"] = sig_d; + cell->connections_["\\Q"] = sig_q; + cell->connections_["\\CLK"] = clk; + cell->connections_["\\SET"] = sig_sr_set; + cell->connections_["\\CLR"] = sig_sr_clr; log(" created %s cell `%s' with %s edge clock and multiple level-sensitive resets.\n", cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative"); @@ -155,22 +155,22 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec inv_set->parameters["\\A_SIGNED"] = RTLIL::Const(0); inv_set->parameters["\\A_WIDTH"] = RTLIL::Const(sig_in.size()); inv_set->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_in.size()); - inv_set->connections["\\A"] = sig_set; - inv_set->connections["\\Y"] = sig_set_inv; + inv_set->connections_["\\A"] = sig_set; + inv_set->connections_["\\Y"] = sig_set_inv; RTLIL::Cell *mux_sr_set = mod->addCell(NEW_ID, "$mux"); mux_sr_set->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size()); - mux_sr_set->connections[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.size()); - mux_sr_set->connections[set_polarity ? "\\B" : "\\A"] = sig_set; - mux_sr_set->connections["\\Y"] = sig_sr_set; - mux_sr_set->connections["\\S"] = set; + mux_sr_set->connections_[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.size()); + mux_sr_set->connections_[set_polarity ? "\\B" : "\\A"] = sig_set; + mux_sr_set->connections_["\\Y"] = sig_sr_set; + mux_sr_set->connections_["\\S"] = set; RTLIL::Cell *mux_sr_clr = mod->addCell(NEW_ID, "$mux"); mux_sr_clr->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size()); - mux_sr_clr->connections[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.size()); - mux_sr_clr->connections[set_polarity ? "\\B" : "\\A"] = sig_set_inv; - mux_sr_clr->connections["\\Y"] = sig_sr_clr; - mux_sr_clr->connections["\\S"] = set; + mux_sr_clr->connections_[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.size()); + mux_sr_clr->connections_[set_polarity ? "\\B" : "\\A"] = sig_set_inv; + mux_sr_clr->connections_["\\Y"] = sig_sr_clr; + mux_sr_clr->connections_["\\S"] = set; RTLIL::Cell *cell = mod->addCell(sstr.str(), "$dffsr"); cell->attributes = proc->attributes; @@ -178,11 +178,11 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1); cell->parameters["\\SET_POLARITY"] = RTLIL::Const(true, 1); cell->parameters["\\CLR_POLARITY"] = RTLIL::Const(true, 1); - cell->connections["\\D"] = sig_in; - cell->connections["\\Q"] = sig_out; - cell->connections["\\CLK"] = clk; - cell->connections["\\SET"] = sig_sr_set; - cell->connections["\\CLR"] = sig_sr_clr; + cell->connections_["\\D"] = sig_in; + cell->connections_["\\Q"] = sig_out; + cell->connections_["\\CLK"] = clk; + cell->connections_["\\SET"] = sig_sr_set; + cell->connections_["\\CLR"] = sig_sr_clr; log(" created %s cell `%s' with %s edge clock and %s level non-const reset.\n", cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative", set_polarity ? "positive" : "negative"); @@ -204,11 +204,11 @@ static void gen_dff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::Const val_ } cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1); - cell->connections["\\D"] = sig_in; - cell->connections["\\Q"] = sig_out; + cell->connections_["\\D"] = sig_in; + cell->connections_["\\Q"] = sig_out; if (arst) - cell->connections["\\ARST"] = *arst; - cell->connections["\\CLK"] = clk; + cell->connections_["\\ARST"] = *arst; + cell->connections_["\\CLK"] = clk; log(" created %s cell `%s' with %s edge clock", cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative"); if (arst) @@ -296,9 +296,9 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) cell->parameters["\\A_WIDTH"] = RTLIL::Const(inputs.size()); cell->parameters["\\B_WIDTH"] = RTLIL::Const(inputs.size()); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - cell->connections["\\A"] = inputs; - cell->connections["\\B"] = compare; - cell->connections["\\Y"] = sync_level->signal; + cell->connections_["\\A"] = inputs; + cell->connections_["\\B"] = compare; + cell->connections_["\\Y"] = sync_level->signal; many_async_rules.clear(); } @@ -322,7 +322,7 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) if (sync_edge || sync_level || many_async_rules.size() > 0) log_error("Mixed always event with edge and/or level sensitive events!\n"); log(" created direct connection (no actual register cell created).\n"); - mod->connections.push_back(RTLIL::SigSig(sig, insig)); + mod->connections_.push_back(RTLIL::SigSig(sig, insig)); continue; } diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc index 5bb1ab948..2cde749a5 100644 --- a/passes/proc/proc_mux.cc +++ b/passes/proc/proc_mux.cc @@ -81,7 +81,7 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, if (sig.size() == 1 && comp == RTLIL::SigSpec(1,1)) { - mod->connections.push_back(RTLIL::SigSig(RTLIL::SigSpec(cmp_wire, cmp_wire->width++), sig)); + mod->connections_.push_back(RTLIL::SigSig(RTLIL::SigSpec(cmp_wire, cmp_wire->width++), sig)); } else { @@ -96,9 +96,9 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(comp.size()); eq_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - eq_cell->connections["\\A"] = sig; - eq_cell->connections["\\B"] = comp; - eq_cell->connections["\\Y"] = RTLIL::SigSpec(cmp_wire, cmp_wire->width++); + eq_cell->connections_["\\A"] = sig; + eq_cell->connections_["\\B"] = comp; + eq_cell->connections_["\\Y"] = RTLIL::SigSpec(cmp_wire, cmp_wire->width++); } } @@ -122,8 +122,8 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, any_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cmp_wire->width); any_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - any_cell->connections["\\A"] = cmp_wire; - any_cell->connections["\\Y"] = RTLIL::SigSpec(ctrl_wire); + any_cell->connections_["\\A"] = cmp_wire; + any_cell->connections_["\\Y"] = RTLIL::SigSpec(ctrl_wire); } return RTLIL::SigSpec(ctrl_wire); @@ -157,10 +157,10 @@ static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, mux_cell->attributes = sw->attributes; mux_cell->parameters["\\WIDTH"] = RTLIL::Const(when_signal.size()); - mux_cell->connections["\\A"] = else_signal; - mux_cell->connections["\\B"] = when_signal; - mux_cell->connections["\\S"] = ctrl_sig; - mux_cell->connections["\\Y"] = RTLIL::SigSpec(result_wire); + mux_cell->connections_["\\A"] = else_signal; + mux_cell->connections_["\\B"] = when_signal; + mux_cell->connections_["\\S"] = ctrl_sig; + mux_cell->connections_["\\Y"] = RTLIL::SigSpec(result_wire); last_mux_cell = mux_cell; return RTLIL::SigSpec(result_wire); @@ -169,14 +169,14 @@ static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, static void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector &compare, RTLIL::SigSpec when_signal, RTLIL::Cell *last_mux_cell, RTLIL::SwitchRule *sw) { assert(last_mux_cell != NULL); - assert(when_signal.size() == last_mux_cell->connections["\\A"].size()); + assert(when_signal.size() == last_mux_cell->connections_["\\A"].size()); RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw); assert(ctrl_sig.size() == 1); last_mux_cell->type = "$pmux"; - last_mux_cell->connections["\\S"].append(ctrl_sig); - last_mux_cell->connections["\\B"].append(when_signal); - last_mux_cell->parameters["\\S_WIDTH"] = last_mux_cell->connections["\\S"].size(); + last_mux_cell->connections_["\\S"].append(ctrl_sig); + last_mux_cell->connections_["\\B"].append(when_signal); + last_mux_cell->parameters["\\S_WIDTH"] = last_mux_cell->connections_["\\S"].size(); } static RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, RTLIL::CaseRule *cs, const RTLIL::SigSpec &sig, const RTLIL::SigSpec &defval) @@ -256,7 +256,7 @@ static void proc_mux(RTLIL::Module *mod, RTLIL::Process *proc) log(" creating decoder for signal `%s'.\n", log_signal(sig)); RTLIL::SigSpec value = signal_to_mux_tree(mod, &proc->root_case, sig, RTLIL::SigSpec(RTLIL::State::Sx, sig.size())); - mod->connections.push_back(RTLIL::SigSig(sig, value)); + mod->connections_.push_back(RTLIL::SigSig(sig, value)); } } diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc index 29ce899ef..22b724d53 100644 --- a/passes/sat/expose.cc +++ b/passes/sat/expose.cc @@ -83,8 +83,8 @@ static void find_dff_wires(std::set &dff_wires, RTLIL::Module *modu SigPool dffsignals; for (auto &it : module->cells) { - if (ct.cell_known(it.second->type) && it.second->connections.count("\\Q")) - dffsignals.add(sigmap(it.second->connections.at("\\Q"))); + if (ct.cell_known(it.second->type) && it.second->connections_.count("\\Q")) + dffsignals.add(sigmap(it.second->connections_.at("\\Q"))); } for (auto &it : module->wires) { @@ -113,10 +113,10 @@ static void create_dff_dq_map(std::map &map, RTLIL: info.cell = it.second; if (info.cell->type == "$dff") { - info.bit_clk = sigmap(info.cell->connections.at("\\CLK")).to_single_sigbit(); + info.bit_clk = sigmap(info.cell->connections_.at("\\CLK")).to_single_sigbit(); info.clk_polarity = info.cell->parameters.at("\\CLK_POLARITY").as_bool(); - std::vector sig_d = sigmap(info.cell->connections.at("\\D")).to_sigbit_vector(); - std::vector sig_q = sigmap(info.cell->connections.at("\\Q")).to_sigbit_vector(); + std::vector sig_d = sigmap(info.cell->connections_.at("\\D")).to_sigbit_vector(); + std::vector sig_q = sigmap(info.cell->connections_.at("\\Q")).to_sigbit_vector(); for (size_t i = 0; i < sig_d.size(); i++) { info.bit_d = sig_d.at(i); bit_info[sig_q.at(i)] = info; @@ -125,12 +125,12 @@ static void create_dff_dq_map(std::map &map, RTLIL: } if (info.cell->type == "$adff") { - info.bit_clk = sigmap(info.cell->connections.at("\\CLK")).to_single_sigbit(); - info.bit_arst = sigmap(info.cell->connections.at("\\ARST")).to_single_sigbit(); + info.bit_clk = sigmap(info.cell->connections_.at("\\CLK")).to_single_sigbit(); + info.bit_arst = sigmap(info.cell->connections_.at("\\ARST")).to_single_sigbit(); info.clk_polarity = info.cell->parameters.at("\\CLK_POLARITY").as_bool(); info.arst_polarity = info.cell->parameters.at("\\ARST_POLARITY").as_bool(); - std::vector sig_d = sigmap(info.cell->connections.at("\\D")).to_sigbit_vector(); - std::vector sig_q = sigmap(info.cell->connections.at("\\Q")).to_sigbit_vector(); + std::vector sig_d = sigmap(info.cell->connections_.at("\\D")).to_sigbit_vector(); + std::vector sig_q = sigmap(info.cell->connections_.at("\\Q")).to_sigbit_vector(); std::vector arst_value = info.cell->parameters.at("\\ARST_VALUE").bits; for (size_t i = 0; i < sig_d.size(); i++) { info.bit_d = sig_d.at(i); @@ -141,21 +141,21 @@ static void create_dff_dq_map(std::map &map, RTLIL: } if (info.cell->type == "$_DFF_N_" || info.cell->type == "$_DFF_P_") { - info.bit_clk = sigmap(info.cell->connections.at("\\C")).to_single_sigbit(); + info.bit_clk = sigmap(info.cell->connections_.at("\\C")).to_single_sigbit(); info.clk_polarity = info.cell->type == "$_DFF_P_"; - info.bit_d = sigmap(info.cell->connections.at("\\D")).to_single_sigbit(); - bit_info[sigmap(info.cell->connections.at("\\Q")).to_single_sigbit()] = info; + info.bit_d = sigmap(info.cell->connections_.at("\\D")).to_single_sigbit(); + bit_info[sigmap(info.cell->connections_.at("\\Q")).to_single_sigbit()] = info; continue; } if (info.cell->type.size() == 10 && info.cell->type.substr(0, 6) == "$_DFF_") { - info.bit_clk = sigmap(info.cell->connections.at("\\C")).to_single_sigbit(); - info.bit_arst = sigmap(info.cell->connections.at("\\R")).to_single_sigbit(); + info.bit_clk = sigmap(info.cell->connections_.at("\\C")).to_single_sigbit(); + info.bit_arst = sigmap(info.cell->connections_.at("\\R")).to_single_sigbit(); info.clk_polarity = info.cell->type[6] == 'P'; info.arst_polarity = info.cell->type[7] == 'P'; info.arst_value = info.cell->type[0] == '1' ? RTLIL::State::S1 : RTLIL::State::S0; - info.bit_d = sigmap(info.cell->connections.at("\\D")).to_single_sigbit(); - bit_info[sigmap(info.cell->connections.at("\\Q")).to_single_sigbit()] = info; + info.bit_d = sigmap(info.cell->connections_.at("\\D")).to_single_sigbit(); + bit_info[sigmap(info.cell->connections_.at("\\Q")).to_single_sigbit()] = info; continue; } } @@ -485,12 +485,12 @@ struct ExposePass : public Pass { for (auto &it : module->cells) { if (!ct.cell_known(it.second->type)) continue; - for (auto &conn : it.second->connections) + for (auto &conn : it.second->connections_) if (ct.cell_input(it.second->type, conn.first)) conn.second = out_to_in_map(sigmap(conn.second)); } - for (auto &conn : module->connections) + for (auto &conn : module->connections_) conn.second = out_to_in_map(sigmap(conn.second)); } @@ -514,11 +514,11 @@ struct ExposePass : public Pass { for (auto &cell_name : info.cells) { RTLIL::Cell *cell = module->cells.at(cell_name); - std::vector cell_q_bits = sigmap(cell->connections.at("\\Q")).to_sigbit_vector(); + std::vector cell_q_bits = sigmap(cell->connections_.at("\\Q")).to_sigbit_vector(); for (auto &bit : cell_q_bits) if (wire_bits_set.count(bit)) bit = RTLIL::SigBit(wire_dummy_q, wire_dummy_q->width++); - cell->connections.at("\\Q") = cell_q_bits; + cell->connections_.at("\\Q") = cell_q_bits; } RTLIL::Wire *wire_q = new RTLIL::Wire; @@ -536,7 +536,7 @@ struct ExposePass : public Pass { connect_q.second.append(RTLIL::SigBit(wire_q, i)); set_q_bits.insert(wire_bits_vec[i]); } - module->connections.push_back(connect_q); + module->connections_.push_back(connect_q); RTLIL::Wire *wire_d = new RTLIL::Wire; wire_d->name = wire->name + sep + "d"; @@ -544,7 +544,7 @@ struct ExposePass : public Pass { wire_d->port_output = true; log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_d->name)); add_new_wire(module, wire_d); - module->connections.push_back(RTLIL::SigSig(wire_d, info.sig_d)); + module->connections_.push_back(RTLIL::SigSig(wire_d, info.sig_d)); RTLIL::Wire *wire_c = new RTLIL::Wire; wire_c->name = wire->name + sep + "c"; @@ -552,14 +552,14 @@ struct ExposePass : public Pass { log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_c->name)); add_new_wire(module, wire_c); if (info.clk_polarity) { - module->connections.push_back(RTLIL::SigSig(wire_c, info.sig_clk)); + module->connections_.push_back(RTLIL::SigSig(wire_c, info.sig_clk)); } else { RTLIL::Cell *c = module->addCell(NEW_ID, "$not"); c->parameters["\\A_SIGNED"] = 0; c->parameters["\\A_WIDTH"] = 1; c->parameters["\\Y_WIDTH"] = 1; - c->connections["\\A"] = info.sig_clk; - c->connections["\\Y"] = wire_c; + c->connections_["\\A"] = info.sig_clk; + c->connections_["\\Y"] = wire_c; } if (info.sig_arst != RTLIL::State::Sm) @@ -570,14 +570,14 @@ struct ExposePass : public Pass { log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_r->name)); add_new_wire(module, wire_r); if (info.arst_polarity) { - module->connections.push_back(RTLIL::SigSig(wire_r, info.sig_arst)); + module->connections_.push_back(RTLIL::SigSig(wire_r, info.sig_arst)); } else { RTLIL::Cell *c = module->addCell(NEW_ID, "$not"); c->parameters["\\A_SIGNED"] = 0; c->parameters["\\A_WIDTH"] = 1; c->parameters["\\Y_WIDTH"] = 1; - c->connections["\\A"] = info.sig_arst; - c->connections["\\Y"] = wire_r; + c->connections_["\\A"] = info.sig_arst; + c->connections_["\\Y"] = wire_r; } RTLIL::Wire *wire_v = new RTLIL::Wire; @@ -586,7 +586,7 @@ struct ExposePass : public Pass { wire_v->port_output = true; log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_v->name)); add_new_wire(module, wire_v); - module->connections.push_back(RTLIL::SigSig(wire_v, info.arst_value)); + module->connections_.push_back(RTLIL::SigSig(wire_v, info.arst_value)); } } @@ -628,18 +628,18 @@ struct ExposePass : public Pass { log("New module port: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name), RTLIL::id2cstr(cell->type)); RTLIL::SigSpec sig; - if (cell->connections.count(p->name) != 0) - sig = cell->connections.at(p->name); + if (cell->connections_.count(p->name) != 0) + sig = cell->connections_.at(p->name); sig.extend(w->width); if (w->port_input) - module->connections.push_back(RTLIL::SigSig(sig, w)); + module->connections_.push_back(RTLIL::SigSig(sig, w)); else - module->connections.push_back(RTLIL::SigSig(w, sig)); + module->connections_.push_back(RTLIL::SigSig(w, sig)); } } else { - for (auto &it : cell->connections) + for (auto &it : cell->connections_) { RTLIL::Wire *w = new RTLIL::Wire; w->name = cell->name + sep + RTLIL::unescape_id(it.first); @@ -653,9 +653,9 @@ struct ExposePass : public Pass { log("New module port: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name), RTLIL::id2cstr(cell->type)); if (w->port_input) - module->connections.push_back(RTLIL::SigSig(it.second, w)); + module->connections_.push_back(RTLIL::SigSig(it.second, w)); else - module->connections.push_back(RTLIL::SigSig(w, it.second)); + module->connections_.push_back(RTLIL::SigSig(w, it.second)); } } diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index 79dec3b54..517e6713c 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -610,7 +610,7 @@ struct FreduceWorker for (auto &it : module->cells) { if (ct.cell_known(it.second->type)) { std::set inputs, outputs; - for (auto &port : it.second->connections) { + for (auto &port : it.second->connections_) { std::vector bits = sigmap(port.second).to_sigbit_vector(); if (ct.cell_output(it.second->type, port.first)) outputs.insert(bits.begin(), bits.end()); @@ -624,7 +624,7 @@ struct FreduceWorker bits_full_total += outputs.size(); } if (inv_mode && it.second->type == "$_INV_") - inv_pairs.insert(std::pair(sigmap(it.second->connections.at("\\A")), sigmap(it.second->connections.at("\\Y")))); + inv_pairs.insert(std::pair(sigmap(it.second->connections_.at("\\A")), sigmap(it.second->connections_.at("\\Y")))); } int bits_count = 0; @@ -708,7 +708,7 @@ struct FreduceWorker RTLIL::Cell *drv = drivers.at(grp[i].bit).first; RTLIL::Wire *dummy_wire = module->addWire(NEW_ID); - for (auto &port : drv->connections) + for (auto &port : drv->connections_) if (ct.cell_output(drv->type, port.first)) sigmap(port.second).replace(grp[i].bit, dummy_wire, &port.second); @@ -719,14 +719,14 @@ struct FreduceWorker inv_sig = module->addWire(NEW_ID); RTLIL::Cell *inv_cell = module->addCell(NEW_ID, "$_INV_"); - inv_cell->connections["\\A"] = grp[0].bit; - inv_cell->connections["\\Y"] = inv_sig; + inv_cell->connections_["\\A"] = grp[0].bit; + inv_cell->connections_["\\Y"] = inv_sig; } - module->connections.push_back(RTLIL::SigSig(grp[i].bit, inv_sig)); + module->connections_.push_back(RTLIL::SigSig(grp[i].bit, inv_sig)); } else - module->connections.push_back(RTLIL::SigSig(grp[i].bit, grp[0].bit)); + module->connections_.push_back(RTLIL::SigSig(grp[i].bit, grp[0].bit)); rewired_sigbits++; } diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index aff664242..9e151cdfc 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -132,8 +132,8 @@ static void create_miter_equiv(struct Pass *that, std::vector args, w2->width = w1->width; miter_module->add(w2); - gold_cell->connections[w1->name] = w2; - gate_cell->connections[w1->name] = w2; + gold_cell->connections_[w1->name] = w2; + gate_cell->connections_[w1->name] = w2; } if (w1->port_output) @@ -150,8 +150,8 @@ static void create_miter_equiv(struct Pass *that, std::vector args, w2_gate->width = w1->width; miter_module->add(w2_gate); - gold_cell->connections[w1->name] = w2_gold; - gate_cell->connections[w1->name] = w2_gate; + gold_cell->connections_[w1->name] = w2_gold; + gate_cell->connections_[w1->name] = w2_gate; RTLIL::SigSpec this_condition; @@ -165,9 +165,9 @@ static void create_miter_equiv(struct Pass *that, std::vector args, eqx_cell->parameters["\\Y_WIDTH"] = 1; eqx_cell->parameters["\\A_SIGNED"] = 0; eqx_cell->parameters["\\B_SIGNED"] = 0; - eqx_cell->connections["\\A"] = RTLIL::SigSpec(w2_gold, i); - eqx_cell->connections["\\B"] = RTLIL::State::Sx; - eqx_cell->connections["\\Y"] = gold_x.extract(i, 1); + eqx_cell->connections_["\\A"] = RTLIL::SigSpec(w2_gold, i); + eqx_cell->connections_["\\B"] = RTLIL::State::Sx; + eqx_cell->connections_["\\Y"] = gold_x.extract(i, 1); } RTLIL::SigSpec gold_masked = miter_module->addWire(NEW_ID, w2_gold->width); @@ -179,9 +179,9 @@ static void create_miter_equiv(struct Pass *that, std::vector args, or_gold_cell->parameters["\\Y_WIDTH"] = w2_gold->width; or_gold_cell->parameters["\\A_SIGNED"] = 0; or_gold_cell->parameters["\\B_SIGNED"] = 0; - or_gold_cell->connections["\\A"] = w2_gold; - or_gold_cell->connections["\\B"] = gold_x; - or_gold_cell->connections["\\Y"] = gold_masked; + or_gold_cell->connections_["\\A"] = w2_gold; + or_gold_cell->connections_["\\B"] = gold_x; + or_gold_cell->connections_["\\Y"] = gold_masked; RTLIL::Cell *or_gate_cell = miter_module->addCell(NEW_ID, "$or"); or_gate_cell->parameters["\\A_WIDTH"] = w2_gate->width; @@ -189,9 +189,9 @@ static void create_miter_equiv(struct Pass *that, std::vector args, or_gate_cell->parameters["\\Y_WIDTH"] = w2_gate->width; or_gate_cell->parameters["\\A_SIGNED"] = 0; or_gate_cell->parameters["\\B_SIGNED"] = 0; - or_gate_cell->connections["\\A"] = w2_gate; - or_gate_cell->connections["\\B"] = gold_x; - or_gate_cell->connections["\\Y"] = gate_masked; + or_gate_cell->connections_["\\A"] = w2_gate; + or_gate_cell->connections_["\\B"] = gold_x; + or_gate_cell->connections_["\\Y"] = gate_masked; RTLIL::Cell *eq_cell = miter_module->addCell(NEW_ID, "$eqx"); eq_cell->parameters["\\A_WIDTH"] = w2_gold->width; @@ -199,10 +199,10 @@ static void create_miter_equiv(struct Pass *that, std::vector args, eq_cell->parameters["\\Y_WIDTH"] = 1; eq_cell->parameters["\\A_SIGNED"] = 0; eq_cell->parameters["\\B_SIGNED"] = 0; - eq_cell->connections["\\A"] = gold_masked; - eq_cell->connections["\\B"] = gate_masked; - eq_cell->connections["\\Y"] = miter_module->addWire(NEW_ID); - this_condition = eq_cell->connections["\\Y"]; + eq_cell->connections_["\\A"] = gold_masked; + eq_cell->connections_["\\B"] = gate_masked; + eq_cell->connections_["\\Y"] = miter_module->addWire(NEW_ID); + this_condition = eq_cell->connections_["\\Y"]; } else { @@ -212,10 +212,10 @@ static void create_miter_equiv(struct Pass *that, std::vector args, eq_cell->parameters["\\Y_WIDTH"] = 1; eq_cell->parameters["\\A_SIGNED"] = 0; eq_cell->parameters["\\B_SIGNED"] = 0; - eq_cell->connections["\\A"] = w2_gold; - eq_cell->connections["\\B"] = w2_gate; - eq_cell->connections["\\Y"] = miter_module->addWire(NEW_ID); - this_condition = eq_cell->connections["\\Y"]; + eq_cell->connections_["\\A"] = w2_gold; + eq_cell->connections_["\\B"] = w2_gate; + eq_cell->connections_["\\Y"] = miter_module->addWire(NEW_ID); + this_condition = eq_cell->connections_["\\Y"]; } if (flag_make_outcmp) @@ -224,7 +224,7 @@ static void create_miter_equiv(struct Pass *that, std::vector args, w_cmp->name = "\\cmp_" + RTLIL::unescape_id(w1->name); w_cmp->port_output = true; miter_module->add(w_cmp); - miter_module->connections.push_back(RTLIL::SigSig(w_cmp, this_condition)); + miter_module->connections_.push_back(RTLIL::SigSig(w_cmp, this_condition)); } all_conditions.append(this_condition); @@ -236,15 +236,15 @@ static void create_miter_equiv(struct Pass *that, std::vector args, reduce_cell->parameters["\\A_WIDTH"] = all_conditions.size(); reduce_cell->parameters["\\Y_WIDTH"] = 1; reduce_cell->parameters["\\A_SIGNED"] = 0; - reduce_cell->connections["\\A"] = all_conditions; - reduce_cell->connections["\\Y"] = miter_module->addWire(NEW_ID); - all_conditions = reduce_cell->connections["\\Y"]; + reduce_cell->connections_["\\A"] = all_conditions; + reduce_cell->connections_["\\Y"] = miter_module->addWire(NEW_ID); + all_conditions = reduce_cell->connections_["\\Y"]; } if (flag_make_assert) { RTLIL::Cell *assert_cell = miter_module->addCell(NEW_ID, "$assert"); - assert_cell->connections["\\A"] = all_conditions; - assert_cell->connections["\\EN"] = RTLIL::SigSpec(1, 1); + assert_cell->connections_["\\A"] = all_conditions; + assert_cell->connections_["\\EN"] = RTLIL::SigSpec(1, 1); } RTLIL::Wire *w_trigger = new RTLIL::Wire; @@ -257,8 +257,8 @@ static void create_miter_equiv(struct Pass *that, std::vector args, not_cell->parameters["\\A_WIDTH"] = all_conditions.size(); not_cell->parameters["\\Y_WIDTH"] = w_trigger->width; not_cell->parameters["\\A_SIGNED"] = 0; - not_cell->connections["\\A"] = all_conditions; - not_cell->connections["\\Y"] = w_trigger; + not_cell->connections_["\\A"] = all_conditions; + not_cell->connections_["\\Y"] = w_trigger; miter_module->fixup_ports(); diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 4b6b1b719..cc041391b 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -321,7 +321,7 @@ struct SatHelper if (design->selected(module, c.second)) { // log("Import cell: %s\n", RTLIL::id2cstr(c.first)); if (satgen.importCell(c.second, timestep)) { - for (auto &p : c.second->connections) + for (auto &p : c.second->connections_) if (ct.cell_output(c.second->type, p.first)) show_drivers.insert(sigmap(p.second), c.second); import_cell_counter++; @@ -505,7 +505,7 @@ struct SatHelper final_signals.add(sig); } else { for (auto &d : drivers) - for (auto &p : d->connections) { + for (auto &p : d->connections_) { if (d->type == "$dff" && p.first == "\\CLK") continue; if (d->type.substr(0, 6) == "$_DFF_" && p.first == "\\C") diff --git a/passes/sat/share.cc b/passes/sat/share.cc index 7e24e1f04..01acf50df 100644 --- a/passes/sat/share.cc +++ b/passes/sat/share.cc @@ -77,7 +77,7 @@ struct ShareWorker for (auto &pbit : portbits) { if (pbit.cell->type == "$mux" || pbit.cell->type == "$pmux") { - std::set bits = modwalker.sigmap(pbit.cell->connections.at("\\S")).to_sigbit_set(); + std::set bits = modwalker.sigmap(pbit.cell->connections_.at("\\S")).to_sigbit_set(); terminal_bits.insert(bits.begin(), bits.end()); queue_bits.insert(bits.begin(), bits.end()); visited_cells.insert(pbit.cell); @@ -256,9 +256,9 @@ struct ShareWorker if (c1->parameters.at("\\A_SIGNED").as_bool() != c2->parameters.at("\\A_SIGNED").as_bool()) { RTLIL::Cell *unsigned_cell = c1->parameters.at("\\A_SIGNED").as_bool() ? c2 : c1; - if (unsigned_cell->connections.at("\\A").to_sigbit_vector().back() != RTLIL::State::S0) { + if (unsigned_cell->connections_.at("\\A").to_sigbit_vector().back() != RTLIL::State::S0) { unsigned_cell->parameters.at("\\A_WIDTH") = unsigned_cell->parameters.at("\\A_WIDTH").as_int() + 1; - unsigned_cell->connections.at("\\A").append_bit(RTLIL::State::S0); + unsigned_cell->connections_.at("\\A").append_bit(RTLIL::State::S0); } unsigned_cell->parameters.at("\\A_SIGNED") = true; unsigned_cell->check(); @@ -267,17 +267,17 @@ struct ShareWorker bool a_signed = c1->parameters.at("\\A_SIGNED").as_bool(); log_assert(a_signed == c2->parameters.at("\\A_SIGNED").as_bool()); - RTLIL::SigSpec a1 = c1->connections.at("\\A"); - RTLIL::SigSpec y1 = c1->connections.at("\\Y"); + RTLIL::SigSpec a1 = c1->connections_.at("\\A"); + RTLIL::SigSpec y1 = c1->connections_.at("\\Y"); - RTLIL::SigSpec a2 = c2->connections.at("\\A"); - RTLIL::SigSpec y2 = c2->connections.at("\\Y"); + RTLIL::SigSpec a2 = c2->connections_.at("\\A"); + RTLIL::SigSpec y2 = c2->connections_.at("\\Y"); int a_width = std::max(a1.size(), a2.size()); int y_width = std::max(y1.size(), y2.size()); - if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y"); - if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y"); + if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->connections_.at("\\Y"); + if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->connections_.at("\\Y"); RTLIL::SigSpec a = module->Mux(NEW_ID, a2, a1, act); RTLIL::Wire *y = module->addWire(NEW_ID, y_width); @@ -286,14 +286,14 @@ struct ShareWorker supercell->parameters["\\A_SIGNED"] = a_signed; supercell->parameters["\\A_WIDTH"] = a_width; supercell->parameters["\\Y_WIDTH"] = y_width; - supercell->connections["\\A"] = a; - supercell->connections["\\Y"] = y; + supercell->connections_["\\A"] = a; + supercell->connections_["\\Y"] = y; RTLIL::SigSpec new_y1(y, 0, y1.size()); RTLIL::SigSpec new_y2(y, 0, y2.size()); - module->connections.push_back(RTLIL::SigSig(y1, new_y1)); - module->connections.push_back(RTLIL::SigSig(y2, new_y2)); + module->connections_.push_back(RTLIL::SigSig(y1, new_y1)); + module->connections_.push_back(RTLIL::SigSig(y2, new_y2)); return supercell; } @@ -312,7 +312,7 @@ struct ShareWorker if (score_flipped < score_unflipped) { - std::swap(c2->connections.at("\\A"), c2->connections.at("\\B")); + std::swap(c2->connections_.at("\\A"), c2->connections_.at("\\B")); std::swap(c2->parameters.at("\\A_WIDTH"), c2->parameters.at("\\B_WIDTH")); std::swap(c2->parameters.at("\\A_SIGNED"), c2->parameters.at("\\B_SIGNED")); modified_src_cells = true; @@ -323,9 +323,9 @@ struct ShareWorker { RTLIL::Cell *unsigned_cell = c1->parameters.at("\\A_SIGNED").as_bool() ? c2 : c1; - if (unsigned_cell->connections.at("\\A").to_sigbit_vector().back() != RTLIL::State::S0) { + if (unsigned_cell->connections_.at("\\A").to_sigbit_vector().back() != RTLIL::State::S0) { unsigned_cell->parameters.at("\\A_WIDTH") = unsigned_cell->parameters.at("\\A_WIDTH").as_int() + 1; - unsigned_cell->connections.at("\\A").append_bit(RTLIL::State::S0); + unsigned_cell->connections_.at("\\A").append_bit(RTLIL::State::S0); } unsigned_cell->parameters.at("\\A_SIGNED") = true; modified_src_cells = true; @@ -334,9 +334,9 @@ struct ShareWorker if (c1->parameters.at("\\B_SIGNED").as_bool() != c2->parameters.at("\\B_SIGNED").as_bool()) { RTLIL::Cell *unsigned_cell = c1->parameters.at("\\B_SIGNED").as_bool() ? c2 : c1; - if (unsigned_cell->connections.at("\\B").to_sigbit_vector().back() != RTLIL::State::S0) { + if (unsigned_cell->connections_.at("\\B").to_sigbit_vector().back() != RTLIL::State::S0) { unsigned_cell->parameters.at("\\B_WIDTH") = unsigned_cell->parameters.at("\\B_WIDTH").as_int() + 1; - unsigned_cell->connections.at("\\B").append_bit(RTLIL::State::S0); + unsigned_cell->connections_.at("\\B").append_bit(RTLIL::State::S0); } unsigned_cell->parameters.at("\\B_SIGNED") = true; modified_src_cells = true; @@ -356,13 +356,13 @@ struct ShareWorker if (c1->type == "$shl" || c1->type == "$shr" || c1->type == "$sshl" || c1->type == "$sshr") b_signed = false; - RTLIL::SigSpec a1 = c1->connections.at("\\A"); - RTLIL::SigSpec b1 = c1->connections.at("\\B"); - RTLIL::SigSpec y1 = c1->connections.at("\\Y"); + RTLIL::SigSpec a1 = c1->connections_.at("\\A"); + RTLIL::SigSpec b1 = c1->connections_.at("\\B"); + RTLIL::SigSpec y1 = c1->connections_.at("\\Y"); - RTLIL::SigSpec a2 = c2->connections.at("\\A"); - RTLIL::SigSpec b2 = c2->connections.at("\\B"); - RTLIL::SigSpec y2 = c2->connections.at("\\Y"); + RTLIL::SigSpec a2 = c2->connections_.at("\\A"); + RTLIL::SigSpec b2 = c2->connections_.at("\\B"); + RTLIL::SigSpec y2 = c2->connections_.at("\\Y"); int a_width = std::max(a1.size(), a2.size()); int b_width = std::max(b1.size(), b2.size()); @@ -372,20 +372,20 @@ struct ShareWorker { a_width = std::max(y_width, a_width); - if (a1.size() < y1.size()) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, y1.size()), true)->connections.at("\\Y"); - if (a2.size() < y2.size()) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, y2.size()), true)->connections.at("\\Y"); + if (a1.size() < y1.size()) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, y1.size()), true)->connections_.at("\\Y"); + if (a2.size() < y2.size()) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, y2.size()), true)->connections_.at("\\Y"); - if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), false)->connections.at("\\Y"); - if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), false)->connections.at("\\Y"); + if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), false)->connections_.at("\\Y"); + if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), false)->connections_.at("\\Y"); } else { - if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y"); - if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y"); + if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->connections_.at("\\Y"); + if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->connections_.at("\\Y"); } - if (b1.size() != b_width) b1 = module->addPos(NEW_ID, b1, module->addWire(NEW_ID, b_width), b_signed)->connections.at("\\Y"); - if (b2.size() != b_width) b2 = module->addPos(NEW_ID, b2, module->addWire(NEW_ID, b_width), b_signed)->connections.at("\\Y"); + if (b1.size() != b_width) b1 = module->addPos(NEW_ID, b1, module->addWire(NEW_ID, b_width), b_signed)->connections_.at("\\Y"); + if (b2.size() != b_width) b2 = module->addPos(NEW_ID, b2, module->addWire(NEW_ID, b_width), b_signed)->connections_.at("\\Y"); RTLIL::SigSpec a = module->Mux(NEW_ID, a2, a1, act); RTLIL::SigSpec b = module->Mux(NEW_ID, b2, b1, act); @@ -397,16 +397,16 @@ struct ShareWorker supercell->parameters["\\A_WIDTH"] = a_width; supercell->parameters["\\B_WIDTH"] = b_width; supercell->parameters["\\Y_WIDTH"] = y_width; - supercell->connections["\\A"] = a; - supercell->connections["\\B"] = b; - supercell->connections["\\Y"] = y; + supercell->connections_["\\A"] = a; + supercell->connections_["\\B"] = b; + supercell->connections_["\\Y"] = y; supercell->check(); RTLIL::SigSpec new_y1(y, 0, y1.size()); RTLIL::SigSpec new_y2(y, 0, y2.size()); - module->connections.push_back(RTLIL::SigSig(y1, new_y1)); - module->connections.push_back(RTLIL::SigSig(y2, new_y2)); + module->connections_.push_back(RTLIL::SigSig(y1, new_y1)); + module->connections_.push_back(RTLIL::SigSig(y2, new_y2)); return supercell; } @@ -438,7 +438,7 @@ struct ShareWorker for (auto &bit : pbits) { if ((bit.cell->type == "$mux" || bit.cell->type == "$pmux") && bit.port == "\\S") - forbidden_controls_cache[cell].insert(bit.cell->connections.at("\\S").extract(bit.offset, 1)); + forbidden_controls_cache[cell].insert(bit.cell->connections_.at("\\S").extract(bit.offset, 1)); consumer_cells.insert(bit.cell); } @@ -532,9 +532,9 @@ struct ShareWorker std::set used_in_b_parts; int width = c->parameters.at("\\WIDTH").as_int(); - std::vector sig_a = modwalker.sigmap(c->connections.at("\\A")); - std::vector sig_b = modwalker.sigmap(c->connections.at("\\B")); - std::vector sig_s = modwalker.sigmap(c->connections.at("\\S")); + std::vector sig_a = modwalker.sigmap(c->connections_.at("\\A")); + std::vector sig_b = modwalker.sigmap(c->connections_.at("\\B")); + std::vector sig_s = modwalker.sigmap(c->connections_.at("\\S")); for (auto &bit : sig_a) if (cell_out_bits.count(bit)) @@ -572,7 +572,7 @@ struct ShareWorker if (activation_patterns_cache[cell].empty()) { log("%sFound cell that is never activated: %s\n", indent, log_id(cell)); RTLIL::SigSpec cell_outputs = modwalker.cell_outputs[cell]; - module->connections.push_back(RTLIL::SigSig(cell_outputs, RTLIL::SigSpec(RTLIL::State::Sx, cell_outputs.size()))); + module->connections_.push_back(RTLIL::SigSig(cell_outputs, RTLIL::SigSpec(RTLIL::State::Sx, cell_outputs.size()))); cells_to_remove.insert(cell); } diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc index c047e418a..ac0064f70 100644 --- a/passes/techmap/dfflibmap.cc +++ b/passes/techmap/dfflibmap.cc @@ -398,7 +398,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module) { auto cell_type = cell->type; auto cell_name = cell->name; - auto cell_connections = cell->connections; + auto cell_connections = cell->connections_; module->remove(cell); cell_mapping &cm = cell_mappings[cell_type]; @@ -418,7 +418,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module) } else if (port.second != 0) log_abort(); - new_cell->connections["\\" + port.first] = sig; + new_cell->connections_["\\" + port.first] = sig; } stats[stringf(" mapped %%d %s cells to %s cells.\n", cell_type.c_str(), new_cell->type.c_str())]++; diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index e52c8fe52..5dfcd63d1 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -125,10 +125,10 @@ namespace RTLIL::Wire *lastHaystackWire = NULL; std::map emptyAttr; - for (auto &conn : needleCell->connections) + for (auto &conn : needleCell->connections_) { RTLIL::SigSpec needleSig = conn.second; - RTLIL::SigSpec haystackSig = haystackCell->connections.at(portMapping.at(conn.first)); + RTLIL::SigSpec haystackSig = haystackCell->connections_.at(portMapping.at(conn.first)); for (int i = 0; i < std::min(needleSig.size(), haystackSig.size()); i++) { RTLIL::Wire *needleWire = needleSig[i].wire, *haystackWire = haystackSig[i].wire; @@ -186,7 +186,7 @@ namespace { RTLIL::Cell *cell = cell_it.second; if (!sel || sel->selected(mod, cell)) - for (auto &conn : cell->connections) { + for (auto &conn : cell->connections_) { RTLIL::SigSpec conn_sig = conn.second; sigmap.apply(conn_sig); for (auto &bit : conn_sig) @@ -207,7 +207,7 @@ namespace type = type.substr(1); graph.createNode(cell->name, type, (void*)cell); - for (auto &conn : cell->connections) + for (auto &conn : cell->connections_) { graph.createPort(cell->name, conn.first, conn.second.size()); @@ -257,7 +257,7 @@ namespace { RTLIL::Cell *cell = cell_it.second; if (sel && !sel->selected(mod, cell)) - for (auto &conn : cell->connections) + for (auto &conn : cell->connections_) { RTLIL::SigSpec conn_sig = conn.second; sigmap.apply(conn_sig); @@ -305,7 +305,7 @@ namespace if (wire->port_id > 0) { for (int i = 0; i < wire->width; i++) sig2port.insert(sigmap(RTLIL::SigSpec(wire, i)), std::pair(wire->name, i)); - cell->connections[wire->name] = RTLIL::SigSpec(RTLIL::State::Sz, wire->width); + cell->connections_[wire->name] = RTLIL::SigSpec(RTLIL::State::Sz, wire->width); } } @@ -319,13 +319,13 @@ namespace if (needle_cell == NULL) continue; - for (auto &conn : needle_cell->connections) { + for (auto &conn : needle_cell->connections_) { RTLIL::SigSpec sig = sigmap(conn.second); if (mapping.portMapping.count(conn.first) > 0 && sig2port.has(sigmap(sig))) { for (int i = 0; i < sig.size(); i++) for (auto &port : sig2port.find(sig[i])) { - RTLIL::SigSpec bitsig = haystack_cell->connections.at(mapping.portMapping[conn.first]).extract(i, 1); - cell->connections.at(port.first).replace(port.second, bitsig); + RTLIL::SigSpec bitsig = haystack_cell->connections_.at(mapping.portMapping[conn.first]).extract(i, 1); + cell->connections_.at(port.first).replace(port.second, bitsig); } } } @@ -714,7 +714,7 @@ struct ExtractPass : public Pass { cells.insert((RTLIL::Cell*)node.userData); for (auto cell : cells) - for (auto &conn : cell->connections) { + for (auto &conn : cell->connections_) { RTLIL::SigSpec sig = sigmap(conn.second); for (auto &chunk : sig.chunks()) if (chunk.wire != NULL) @@ -739,12 +739,12 @@ struct ExtractPass : public Pass { for (auto cell : cells) { RTLIL::Cell *newCell = newMod->addCell(cell->name, cell->type); newCell->parameters = cell->parameters; - for (auto &conn : cell->connections) { + for (auto &conn : cell->connections_) { std::vector chunks = sigmap(conn.second); for (auto &chunk : chunks) if (chunk.wire != NULL) chunk.wire = newMod->wires.at(chunk.wire->name); - newCell->connections[conn.first] = chunks; + newCell->connections_[conn.first] = chunks; } } } diff --git a/passes/techmap/hilomap.cc b/passes/techmap/hilomap.cc index e41536707..286ad8ac0 100644 --- a/passes/techmap/hilomap.cc +++ b/passes/techmap/hilomap.cc @@ -35,7 +35,7 @@ void hilomap_worker(RTLIL::SigSpec &sig) if (!singleton_mode || last_hi == RTLIL::State::Sm) { last_hi = module->addWire(NEW_ID); RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(hicell_celltype)); - cell->connections[RTLIL::escape_id(hicell_portname)] = last_hi; + cell->connections_[RTLIL::escape_id(hicell_portname)] = last_hi; } bit = last_hi; } @@ -43,7 +43,7 @@ void hilomap_worker(RTLIL::SigSpec &sig) if (!singleton_mode || last_lo == RTLIL::State::Sm) { last_lo = module->addWire(NEW_ID); RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(locell_celltype)); - cell->connections[RTLIL::escape_id(locell_portname)] = last_lo; + cell->connections_[RTLIL::escape_id(locell_portname)] = last_lo; } bit = last_lo; } diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc index 7b2484d84..ba9bf51d3 100644 --- a/passes/techmap/iopadmap.cc +++ b/passes/techmap/iopadmap.cc @@ -177,9 +177,9 @@ struct IopadmapPass : public Pass { for (int i = 0; i < wire->width; i++) { RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype)); - cell->connections[RTLIL::escape_id(portname)] = RTLIL::SigSpec(wire, i); + cell->connections_[RTLIL::escape_id(portname)] = RTLIL::SigSpec(wire, i); if (!portname2.empty()) - cell->connections[RTLIL::escape_id(portname2)] = RTLIL::SigSpec(new_wire, i); + cell->connections_[RTLIL::escape_id(portname2)] = RTLIL::SigSpec(new_wire, i); if (!widthparam.empty()) cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(1); if (!nameparam.empty()) @@ -190,9 +190,9 @@ struct IopadmapPass : public Pass { else { RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype)); - cell->connections[RTLIL::escape_id(portname)] = RTLIL::SigSpec(wire); + cell->connections_[RTLIL::escape_id(portname)] = RTLIL::SigSpec(wire); if (!portname2.empty()) - cell->connections[RTLIL::escape_id(portname2)] = RTLIL::SigSpec(new_wire); + cell->connections_[RTLIL::escape_id(portname2)] = RTLIL::SigSpec(new_wire); if (!widthparam.empty()) cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(wire->width); if (!nameparam.empty()) diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc index 8489e7fd9..df7592cef 100644 --- a/passes/techmap/simplemap.cc +++ b/passes/techmap/simplemap.cc @@ -29,43 +29,43 @@ extern void simplemap_get_mappers(std::mapconnections.at("\\A"); - RTLIL::SigSpec sig_y = cell->connections.at("\\Y"); + RTLIL::SigSpec sig_a = cell->connections_.at("\\A"); + RTLIL::SigSpec sig_y = cell->connections_.at("\\Y"); sig_a.extend(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool()); for (int i = 0; i < SIZE(sig_y); i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, "$_INV_"); - gate->connections["\\A"] = sig_a[i]; - gate->connections["\\Y"] = sig_y[i]; + gate->connections_["\\A"] = sig_a[i]; + gate->connections_["\\Y"] = sig_y[i]; } } static void simplemap_pos(RTLIL::Module *module, RTLIL::Cell *cell) { - RTLIL::SigSpec sig_a = cell->connections.at("\\A"); - RTLIL::SigSpec sig_y = cell->connections.at("\\Y"); + RTLIL::SigSpec sig_a = cell->connections_.at("\\A"); + RTLIL::SigSpec sig_y = cell->connections_.at("\\Y"); sig_a.extend(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool()); - module->connections.push_back(RTLIL::SigSig(sig_y, sig_a)); + module->connections_.push_back(RTLIL::SigSig(sig_y, sig_a)); } static void simplemap_bu0(RTLIL::Module *module, RTLIL::Cell *cell) { - RTLIL::SigSpec sig_a = cell->connections.at("\\A"); - RTLIL::SigSpec sig_y = cell->connections.at("\\Y"); + RTLIL::SigSpec sig_a = cell->connections_.at("\\A"); + RTLIL::SigSpec sig_y = cell->connections_.at("\\Y"); sig_a.extend_u0(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool()); - module->connections.push_back(RTLIL::SigSig(sig_y, sig_a)); + module->connections_.push_back(RTLIL::SigSig(sig_y, sig_a)); } static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell) { - RTLIL::SigSpec sig_a = cell->connections.at("\\A"); - RTLIL::SigSpec sig_b = cell->connections.at("\\B"); - RTLIL::SigSpec sig_y = cell->connections.at("\\Y"); + RTLIL::SigSpec sig_a = cell->connections_.at("\\A"); + RTLIL::SigSpec sig_b = cell->connections_.at("\\B"); + RTLIL::SigSpec sig_y = cell->connections_.at("\\Y"); sig_a.extend_u0(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool()); sig_b.extend_u0(SIZE(sig_y), cell->parameters.at("\\B_SIGNED").as_bool()); @@ -76,8 +76,8 @@ static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell) for (int i = 0; i < SIZE(sig_y); i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, "$_INV_"); - gate->connections["\\A"] = sig_t[i]; - gate->connections["\\Y"] = sig_y[i]; + gate->connections_["\\A"] = sig_t[i]; + gate->connections_["\\Y"] = sig_y[i]; } sig_y = sig_t; @@ -92,31 +92,31 @@ static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell) for (int i = 0; i < SIZE(sig_y); i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); - gate->connections["\\A"] = sig_a[i]; - gate->connections["\\B"] = sig_b[i]; - gate->connections["\\Y"] = sig_y[i]; + gate->connections_["\\A"] = sig_a[i]; + gate->connections_["\\B"] = sig_b[i]; + gate->connections_["\\Y"] = sig_y[i]; } } static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) { - RTLIL::SigSpec sig_a = cell->connections.at("\\A"); - RTLIL::SigSpec sig_y = cell->connections.at("\\Y"); + RTLIL::SigSpec sig_a = cell->connections_.at("\\A"); + RTLIL::SigSpec sig_y = cell->connections_.at("\\Y"); if (sig_y.size() == 0) return; if (sig_a.size() == 0) { - if (cell->type == "$reduce_and") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size()))); - if (cell->type == "$reduce_or") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size()))); - if (cell->type == "$reduce_xor") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size()))); - if (cell->type == "$reduce_xnor") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size()))); - if (cell->type == "$reduce_bool") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size()))); + if (cell->type == "$reduce_and") module->connections_.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size()))); + if (cell->type == "$reduce_or") module->connections_.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size()))); + if (cell->type == "$reduce_xor") module->connections_.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size()))); + if (cell->type == "$reduce_xnor") module->connections_.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size()))); + if (cell->type == "$reduce_bool") module->connections_.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size()))); return; } if (sig_y.size() > 1) { - module->connections.push_back(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1))); + module->connections_.push_back(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1))); sig_y = sig_y.extract(0, 1); } @@ -142,10 +142,10 @@ static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) } RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); - gate->connections["\\A"] = sig_a[i]; - gate->connections["\\B"] = sig_a[i+1]; - gate->connections["\\Y"] = sig_t[i/2]; - last_output = &gate->connections["\\Y"]; + gate->connections_["\\A"] = sig_a[i]; + gate->connections_["\\B"] = sig_a[i+1]; + gate->connections_["\\Y"] = sig_t[i/2]; + last_output = &gate->connections_["\\Y"]; } sig_a = sig_t; @@ -154,14 +154,14 @@ static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) if (cell->type == "$reduce_xnor") { RTLIL::SigSpec sig_t = module->addWire(NEW_ID); RTLIL::Cell *gate = module->addCell(NEW_ID, "$_INV_"); - gate->connections["\\A"] = sig_a; - gate->connections["\\Y"] = sig_t; - last_output = &gate->connections["\\Y"]; + gate->connections_["\\A"] = sig_a; + gate->connections_["\\Y"] = sig_t; + last_output = &gate->connections_["\\Y"]; sig_a = sig_t; } if (last_output == NULL) { - module->connections.push_back(RTLIL::SigSig(sig_y, sig_a)); + module->connections_.push_back(RTLIL::SigSig(sig_y, sig_a)); } else { *last_output = sig_y; } @@ -181,9 +181,9 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig) } RTLIL::Cell *gate = module->addCell(NEW_ID, "$_OR_"); - gate->connections["\\A"] = sig[i]; - gate->connections["\\B"] = sig[i+1]; - gate->connections["\\Y"] = sig_t[i/2]; + gate->connections_["\\A"] = sig[i]; + gate->connections_["\\B"] = sig[i+1]; + gate->connections_["\\Y"] = sig_t[i/2]; } sig = sig_t; @@ -195,39 +195,39 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig) static void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell) { - RTLIL::SigSpec sig_a = cell->connections.at("\\A"); + RTLIL::SigSpec sig_a = cell->connections_.at("\\A"); logic_reduce(module, sig_a); - RTLIL::SigSpec sig_y = cell->connections.at("\\Y"); + RTLIL::SigSpec sig_y = cell->connections_.at("\\Y"); if (sig_y.size() == 0) return; if (sig_y.size() > 1) { - module->connections.push_back(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1))); + module->connections_.push_back(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1))); sig_y = sig_y.extract(0, 1); } RTLIL::Cell *gate = module->addCell(NEW_ID, "$_INV_"); - gate->connections["\\A"] = sig_a; - gate->connections["\\Y"] = sig_y; + gate->connections_["\\A"] = sig_a; + gate->connections_["\\Y"] = sig_y; } static void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell) { - RTLIL::SigSpec sig_a = cell->connections.at("\\A"); + RTLIL::SigSpec sig_a = cell->connections_.at("\\A"); logic_reduce(module, sig_a); - RTLIL::SigSpec sig_b = cell->connections.at("\\B"); + RTLIL::SigSpec sig_b = cell->connections_.at("\\B"); logic_reduce(module, sig_b); - RTLIL::SigSpec sig_y = cell->connections.at("\\Y"); + RTLIL::SigSpec sig_y = cell->connections_.at("\\Y"); if (sig_y.size() == 0) return; if (sig_y.size() > 1) { - module->connections.push_back(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1))); + module->connections_.push_back(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1))); sig_y = sig_y.extract(0, 1); } @@ -237,40 +237,40 @@ static void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell) log_assert(!gate_type.empty()); RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); - gate->connections["\\A"] = sig_a; - gate->connections["\\B"] = sig_b; - gate->connections["\\Y"] = sig_y; + gate->connections_["\\A"] = sig_a; + gate->connections_["\\B"] = sig_b; + gate->connections_["\\Y"] = sig_y; } static void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell) { - RTLIL::SigSpec sig_a = cell->connections.at("\\A"); - RTLIL::SigSpec sig_b = cell->connections.at("\\B"); - RTLIL::SigSpec sig_y = cell->connections.at("\\Y"); + RTLIL::SigSpec sig_a = cell->connections_.at("\\A"); + RTLIL::SigSpec sig_b = cell->connections_.at("\\B"); + RTLIL::SigSpec sig_y = cell->connections_.at("\\Y"); for (int i = 0; i < SIZE(sig_y); i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, "$_MUX_"); - gate->connections["\\A"] = sig_a[i]; - gate->connections["\\B"] = sig_b[i]; - gate->connections["\\S"] = cell->connections.at("\\S"); - gate->connections["\\Y"] = sig_y[i]; + gate->connections_["\\A"] = sig_a[i]; + gate->connections_["\\B"] = sig_b[i]; + gate->connections_["\\S"] = cell->connections_.at("\\S"); + gate->connections_["\\Y"] = sig_y[i]; } } static void simplemap_slice(RTLIL::Module *module, RTLIL::Cell *cell) { int offset = cell->parameters.at("\\OFFSET").as_int(); - RTLIL::SigSpec sig_a = cell->connections.at("\\A"); - RTLIL::SigSpec sig_y = cell->connections.at("\\Y"); - module->connections.push_back(RTLIL::SigSig(sig_y, sig_a.extract(offset, sig_y.size()))); + RTLIL::SigSpec sig_a = cell->connections_.at("\\A"); + RTLIL::SigSpec sig_y = cell->connections_.at("\\Y"); + module->connections_.push_back(RTLIL::SigSig(sig_y, sig_a.extract(offset, sig_y.size()))); } static void simplemap_concat(RTLIL::Module *module, RTLIL::Cell *cell) { - RTLIL::SigSpec sig_ab = cell->connections.at("\\A"); - sig_ab.append(cell->connections.at("\\B")); - RTLIL::SigSpec sig_y = cell->connections.at("\\Y"); - module->connections.push_back(RTLIL::SigSig(sig_y, sig_ab)); + RTLIL::SigSpec sig_ab = cell->connections_.at("\\A"); + sig_ab.append(cell->connections_.at("\\B")); + RTLIL::SigSpec sig_y = cell->connections_.at("\\Y"); + module->connections_.push_back(RTLIL::SigSig(sig_y, sig_ab)); } static void simplemap_sr(RTLIL::Module *module, RTLIL::Cell *cell) @@ -279,17 +279,17 @@ static void simplemap_sr(RTLIL::Module *module, RTLIL::Cell *cell) char set_pol = cell->parameters.at("\\SET_POLARITY").as_bool() ? 'P' : 'N'; char clr_pol = cell->parameters.at("\\CLR_POLARITY").as_bool() ? 'P' : 'N'; - RTLIL::SigSpec sig_s = cell->connections.at("\\SET"); - RTLIL::SigSpec sig_r = cell->connections.at("\\CLR"); - RTLIL::SigSpec sig_q = cell->connections.at("\\Q"); + RTLIL::SigSpec sig_s = cell->connections_.at("\\SET"); + RTLIL::SigSpec sig_r = cell->connections_.at("\\CLR"); + RTLIL::SigSpec sig_q = cell->connections_.at("\\Q"); std::string gate_type = stringf("$_SR_%c%c_", set_pol, clr_pol); for (int i = 0; i < width; i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); - gate->connections["\\S"] = sig_s[i]; - gate->connections["\\R"] = sig_r[i]; - gate->connections["\\Q"] = sig_q[i]; + gate->connections_["\\S"] = sig_s[i]; + gate->connections_["\\R"] = sig_r[i]; + gate->connections_["\\Q"] = sig_q[i]; } } @@ -298,17 +298,17 @@ static void simplemap_dff(RTLIL::Module *module, RTLIL::Cell *cell) int width = cell->parameters.at("\\WIDTH").as_int(); char clk_pol = cell->parameters.at("\\CLK_POLARITY").as_bool() ? 'P' : 'N'; - RTLIL::SigSpec sig_clk = cell->connections.at("\\CLK"); - RTLIL::SigSpec sig_d = cell->connections.at("\\D"); - RTLIL::SigSpec sig_q = cell->connections.at("\\Q"); + RTLIL::SigSpec sig_clk = cell->connections_.at("\\CLK"); + RTLIL::SigSpec sig_d = cell->connections_.at("\\D"); + RTLIL::SigSpec sig_q = cell->connections_.at("\\Q"); std::string gate_type = stringf("$_DFF_%c_", clk_pol); for (int i = 0; i < width; i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); - gate->connections["\\C"] = sig_clk; - gate->connections["\\D"] = sig_d[i]; - gate->connections["\\Q"] = sig_q[i]; + gate->connections_["\\C"] = sig_clk; + gate->connections_["\\D"] = sig_d[i]; + gate->connections_["\\Q"] = sig_q[i]; } } @@ -319,21 +319,21 @@ static void simplemap_dffsr(RTLIL::Module *module, RTLIL::Cell *cell) char set_pol = cell->parameters.at("\\SET_POLARITY").as_bool() ? 'P' : 'N'; char clr_pol = cell->parameters.at("\\CLR_POLARITY").as_bool() ? 'P' : 'N'; - RTLIL::SigSpec sig_clk = cell->connections.at("\\CLK"); - RTLIL::SigSpec sig_s = cell->connections.at("\\SET"); - RTLIL::SigSpec sig_r = cell->connections.at("\\CLR"); - RTLIL::SigSpec sig_d = cell->connections.at("\\D"); - RTLIL::SigSpec sig_q = cell->connections.at("\\Q"); + RTLIL::SigSpec sig_clk = cell->connections_.at("\\CLK"); + RTLIL::SigSpec sig_s = cell->connections_.at("\\SET"); + RTLIL::SigSpec sig_r = cell->connections_.at("\\CLR"); + RTLIL::SigSpec sig_d = cell->connections_.at("\\D"); + RTLIL::SigSpec sig_q = cell->connections_.at("\\Q"); std::string gate_type = stringf("$_DFFSR_%c%c%c_", clk_pol, set_pol, clr_pol); for (int i = 0; i < width; i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); - gate->connections["\\C"] = sig_clk; - gate->connections["\\S"] = sig_s[i]; - gate->connections["\\R"] = sig_r[i]; - gate->connections["\\D"] = sig_d[i]; - gate->connections["\\Q"] = sig_q[i]; + gate->connections_["\\C"] = sig_clk; + gate->connections_["\\S"] = sig_s[i]; + gate->connections_["\\R"] = sig_r[i]; + gate->connections_["\\D"] = sig_d[i]; + gate->connections_["\\Q"] = sig_q[i]; } } @@ -347,20 +347,20 @@ static void simplemap_adff(RTLIL::Module *module, RTLIL::Cell *cell) while (int(rst_val.size()) < width) rst_val.push_back(RTLIL::State::S0); - RTLIL::SigSpec sig_clk = cell->connections.at("\\CLK"); - RTLIL::SigSpec sig_rst = cell->connections.at("\\ARST"); - RTLIL::SigSpec sig_d = cell->connections.at("\\D"); - RTLIL::SigSpec sig_q = cell->connections.at("\\Q"); + RTLIL::SigSpec sig_clk = cell->connections_.at("\\CLK"); + RTLIL::SigSpec sig_rst = cell->connections_.at("\\ARST"); + RTLIL::SigSpec sig_d = cell->connections_.at("\\D"); + RTLIL::SigSpec sig_q = cell->connections_.at("\\Q"); std::string gate_type_0 = stringf("$_DFF_%c%c0_", clk_pol, rst_pol); std::string gate_type_1 = stringf("$_DFF_%c%c1_", clk_pol, rst_pol); for (int i = 0; i < width; i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, rst_val.at(i) == RTLIL::State::S1 ? gate_type_1 : gate_type_0); - gate->connections["\\C"] = sig_clk; - gate->connections["\\R"] = sig_rst; - gate->connections["\\D"] = sig_d[i]; - gate->connections["\\Q"] = sig_q[i]; + gate->connections_["\\C"] = sig_clk; + gate->connections_["\\R"] = sig_rst; + gate->connections_["\\D"] = sig_d[i]; + gate->connections_["\\Q"] = sig_q[i]; } } @@ -369,17 +369,17 @@ static void simplemap_dlatch(RTLIL::Module *module, RTLIL::Cell *cell) int width = cell->parameters.at("\\WIDTH").as_int(); char en_pol = cell->parameters.at("\\EN_POLARITY").as_bool() ? 'P' : 'N'; - RTLIL::SigSpec sig_en = cell->connections.at("\\EN"); - RTLIL::SigSpec sig_d = cell->connections.at("\\D"); - RTLIL::SigSpec sig_q = cell->connections.at("\\Q"); + RTLIL::SigSpec sig_en = cell->connections_.at("\\EN"); + RTLIL::SigSpec sig_d = cell->connections_.at("\\D"); + RTLIL::SigSpec sig_q = cell->connections_.at("\\Q"); std::string gate_type = stringf("$_DLATCH_%c_", en_pol); for (int i = 0; i < width; i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); - gate->connections["\\E"] = sig_en; - gate->connections["\\D"] = sig_d[i]; - gate->connections["\\Q"] = sig_q[i]; + gate->connections_["\\E"] = sig_en; + gate->connections_["\\D"] = sig_d[i]; + gate->connections_["\\Q"] = sig_q[i]; } } diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 94cb1e8dd..ab95c003a 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -141,7 +141,7 @@ struct TechmapWorker SigMap port_signal_map; - for (auto &it : cell->connections) { + for (auto &it : cell->connections_) { RTLIL::IdString portname = it.first; if (positional_ports.count(portname) > 0) portname = positional_ports.at(portname); @@ -169,7 +169,7 @@ struct TechmapWorker if (flatten_mode) { // more conservative approach: // connect internal and external wires - module->connections.push_back(c); + module->connections_.push_back(c); } else { // approach that yields nicer outputs: // replace internal wires that are connected to external wires @@ -195,19 +195,19 @@ struct TechmapWorker if (!flatten_mode && c->type.substr(0, 2) == "\\$") c->type = c->type.substr(1); - for (auto &it2 : c->connections) { + for (auto &it2 : c->connections_) { apply_prefix(cell->name, it2.second, module); port_signal_map.apply(it2.second); } } - for (auto &it : tpl->connections) { + for (auto &it : tpl->connections_) { RTLIL::SigSig c = it; apply_prefix(cell->name, c.first, module); apply_prefix(cell->name, c.second, module); port_signal_map.apply(c.first); port_signal_map.apply(c.second); - module->connections.push_back(c); + module->connections_.push_back(c); } module->remove(cell); @@ -262,7 +262,7 @@ struct TechmapWorker break; } - for (auto conn : cell->connections) { + for (auto conn : cell->connections_) { if (conn.first.substr(0, 1) == "$") continue; if (tpl->wires.count(conn.first) > 0 && tpl->wires.at(conn.first)->port_id > 0) @@ -280,7 +280,7 @@ struct TechmapWorker if (tpl->avail_parameters.count("\\_TECHMAP_CELLTYPE_") != 0) parameters["\\_TECHMAP_CELLTYPE_"] = RTLIL::unescape_id(cell->type); - for (auto conn : cell->connections) { + for (auto conn : cell->connections_) { if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", RTLIL::id2cstr(conn.first))) != 0) { std::vector v = sigmap(conn.second).to_sigbit_vector(); for (auto &bit : v) @@ -303,7 +303,7 @@ struct TechmapWorker unique_bit_id[RTLIL::State::Sx] = unique_bit_id_counter++; unique_bit_id[RTLIL::State::Sz] = unique_bit_id_counter++; - for (auto conn : cell->connections) + for (auto conn : cell->connections_) if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))) != 0) { for (auto &bit : sigmap(conn.second).to_sigbit_vector()) if (unique_bit_id.count(bit) == 0) @@ -317,7 +317,7 @@ struct TechmapWorker if (tpl->avail_parameters.count("\\_TECHMAP_BITS_CONNMAP_")) parameters["\\_TECHMAP_BITS_CONNMAP_"] = bits; - for (auto conn : cell->connections) + for (auto conn : cell->connections_) if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))) != 0) { RTLIL::Const value; for (auto &bit : sigmap(conn.second).to_sigbit_vector()) { -- cgit v1.2.3 From b7dda723022ad00c6c0089be888eab319953faa8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 26 Jul 2014 14:32:50 +0200 Subject: Changed users of cell->connections_ to the new API (sed command) git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;' --- passes/abc/abc.cc | 84 ++++++++--------- passes/abc/blifparse.cc | 12 +-- passes/cmds/add.cc | 4 +- passes/cmds/connect.cc | 10 +- passes/cmds/connwrappers.cc | 4 +- passes/cmds/scatter.cc | 6 +- passes/cmds/scc.cc | 2 +- passes/cmds/select.cc | 4 +- passes/cmds/setundef.cc | 4 +- passes/cmds/show.cc | 10 +- passes/cmds/splice.cc | 20 ++-- passes/cmds/splitnets.cc | 2 +- passes/fsm/fsm_detect.cc | 18 ++-- passes/fsm/fsm_expand.cc | 56 +++++------ passes/fsm/fsm_extract.cc | 38 ++++---- passes/fsm/fsm_map.cc | 56 +++++------ passes/fsm/fsm_opt.cc | 16 ++-- passes/fsm/fsmdata.h | 4 +- passes/hierarchy/hierarchy.cc | 10 +- passes/hierarchy/submod.cc | 12 +-- passes/memory/memory_collect.cc | 28 +++--- passes/memory/memory_dff.cc | 38 ++++---- passes/memory/memory_map.cc | 74 +++++++-------- passes/memory/memory_share.cc | 102 ++++++++++---------- passes/memory/memory_unpack.cc | 14 +-- passes/opt/opt_clean.cc | 16 ++-- passes/opt/opt_const.cc | 202 ++++++++++++++++++++-------------------- passes/opt/opt_muxtree.cc | 26 +++--- passes/opt/opt_reduce.cc | 78 ++++++++-------- passes/opt/opt_rmdff.cc | 52 +++++------ passes/opt/opt_share.cc | 16 ++-- passes/proc/proc_arst.cc | 44 ++++----- passes/proc/proc_dff.cc | 90 +++++++++--------- passes/proc/proc_mux.cc | 30 +++--- passes/sat/expose.cc | 72 +++++++------- passes/sat/freduce.cc | 14 +-- passes/sat/miter.cc | 58 ++++++------ passes/sat/sat.cc | 4 +- passes/sat/share.cc | 84 ++++++++--------- passes/techmap/dfflibmap.cc | 4 +- passes/techmap/extract.cc | 24 ++--- passes/techmap/hilomap.cc | 4 +- passes/techmap/iopadmap.cc | 8 +- passes/techmap/simplemap.cc | 198 +++++++++++++++++++-------------------- passes/techmap/techmap.cc | 18 ++-- 45 files changed, 835 insertions(+), 835 deletions(-) (limited to 'passes') diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index 80828e153..c53c44503 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -111,11 +111,11 @@ static void extract_cell(RTLIL::Cell *cell, bool keepff) { if (clk_polarity != (cell->type == "$_DFF_P_")) return; - if (clk_sig != assign_map(cell->connections_["\\C"])) + if (clk_sig != assign_map(cell->get("\\C"))) return; - RTLIL::SigSpec sig_d = cell->connections_["\\D"]; - RTLIL::SigSpec sig_q = cell->connections_["\\Q"]; + RTLIL::SigSpec sig_d = cell->get("\\D"); + RTLIL::SigSpec sig_q = cell->get("\\Q"); if (keepff) for (auto &c : sig_q.chunks()) @@ -133,8 +133,8 @@ static void extract_cell(RTLIL::Cell *cell, bool keepff) if (cell->type == "$_INV_") { - RTLIL::SigSpec sig_a = cell->connections_["\\A"]; - RTLIL::SigSpec sig_y = cell->connections_["\\Y"]; + RTLIL::SigSpec sig_a = cell->get("\\A"); + RTLIL::SigSpec sig_y = cell->get("\\Y"); assign_map.apply(sig_a); assign_map.apply(sig_y); @@ -147,9 +147,9 @@ static void extract_cell(RTLIL::Cell *cell, bool keepff) if (cell->type == "$_AND_" || cell->type == "$_OR_" || cell->type == "$_XOR_") { - RTLIL::SigSpec sig_a = cell->connections_["\\A"]; - RTLIL::SigSpec sig_b = cell->connections_["\\B"]; - RTLIL::SigSpec sig_y = cell->connections_["\\Y"]; + RTLIL::SigSpec sig_a = cell->get("\\A"); + RTLIL::SigSpec sig_b = cell->get("\\B"); + RTLIL::SigSpec sig_y = cell->get("\\Y"); assign_map.apply(sig_a); assign_map.apply(sig_b); @@ -173,10 +173,10 @@ static void extract_cell(RTLIL::Cell *cell, bool keepff) if (cell->type == "$_MUX_") { - RTLIL::SigSpec sig_a = cell->connections_["\\A"]; - RTLIL::SigSpec sig_b = cell->connections_["\\B"]; - RTLIL::SigSpec sig_s = cell->connections_["\\S"]; - RTLIL::SigSpec sig_y = cell->connections_["\\Y"]; + RTLIL::SigSpec sig_a = cell->get("\\A"); + RTLIL::SigSpec sig_b = cell->get("\\B"); + RTLIL::SigSpec sig_s = cell->get("\\S"); + RTLIL::SigSpec sig_y = cell->get("\\Y"); assign_map.apply(sig_a); assign_map.apply(sig_b); @@ -347,7 +347,7 @@ static void handle_loops() } edges[id1].swap(edges[id3]); - module->connections_.push_back(RTLIL::SigSig(signal_list[id3].bit, signal_list[id1].bit)); + module->connect(RTLIL::SigSig(signal_list[id3].bit, signal_list[id1].bit)); dump_loop_graph(dot_f, dot_nr, edges, workpool, in_edges_count); } } @@ -470,7 +470,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std if (cell->type != "$_DFF_N_" && cell->type != "$_DFF_P_") continue; - std::pair key(cell->type == "$_DFF_P_", assign_map(cell->connections_.at("\\C"))); + std::pair key(cell->type == "$_DFF_P_", assign_map(cell->get("\\C"))); if (++dff_counters[key] > best_dff_counter) { best_dff_counter = dff_counters[key]; clk_polarity = key.first; @@ -503,7 +503,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std } for (auto &cell_it : module->cells) - for (auto &port_it : cell_it.second->connections_) + for (auto &port_it : cell_it.second->connections()) mark_port(port_it.second); handle_loops(); @@ -705,48 +705,48 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std cell_stats[RTLIL::unescape_id(c->type)]++; if (c->type == "\\ZERO" || c->type == "\\ONE") { RTLIL::SigSig conn; - conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\Y"].as_wire()->name)]); + conn.first = RTLIL::SigSpec(module->wires[remap_name(c->get("\\Y").as_wire()->name)]); conn.second = RTLIL::SigSpec(c->type == "\\ZERO" ? 0 : 1, 1); - module->connections_.push_back(conn); + module->connect(conn); continue; } if (c->type == "\\BUF") { RTLIL::SigSig conn; - conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\Y"].as_wire()->name)]); - conn.second = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\A"].as_wire()->name)]); - module->connections_.push_back(conn); + conn.first = RTLIL::SigSpec(module->wires[remap_name(c->get("\\Y").as_wire()->name)]); + conn.second = RTLIL::SigSpec(module->wires[remap_name(c->get("\\A").as_wire()->name)]); + module->connect(conn); continue; } if (c->type == "\\INV") { RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_INV_"); - cell->connections_["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\A"].as_wire()->name)]); - cell->connections_["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\Y"].as_wire()->name)]); + cell->set("\\A", RTLIL::SigSpec(module->wires[remap_name(c->get("\\A").as_wire()->name)])); + cell->set("\\Y", RTLIL::SigSpec(module->wires[remap_name(c->get("\\Y").as_wire()->name)])); design->select(module, cell); continue; } if (c->type == "\\AND" || c->type == "\\OR" || c->type == "\\XOR") { RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_" + c->type.substr(1) + "_"); - cell->connections_["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\A"].as_wire()->name)]); - cell->connections_["\\B"] = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\B"].as_wire()->name)]); - cell->connections_["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\Y"].as_wire()->name)]); + cell->set("\\A", RTLIL::SigSpec(module->wires[remap_name(c->get("\\A").as_wire()->name)])); + cell->set("\\B", RTLIL::SigSpec(module->wires[remap_name(c->get("\\B").as_wire()->name)])); + cell->set("\\Y", RTLIL::SigSpec(module->wires[remap_name(c->get("\\Y").as_wire()->name)])); design->select(module, cell); continue; } if (c->type == "\\MUX") { RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_MUX_"); - cell->connections_["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\A"].as_wire()->name)]); - cell->connections_["\\B"] = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\B"].as_wire()->name)]); - cell->connections_["\\S"] = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\S"].as_wire()->name)]); - cell->connections_["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\Y"].as_wire()->name)]); + cell->set("\\A", RTLIL::SigSpec(module->wires[remap_name(c->get("\\A").as_wire()->name)])); + cell->set("\\B", RTLIL::SigSpec(module->wires[remap_name(c->get("\\B").as_wire()->name)])); + cell->set("\\S", RTLIL::SigSpec(module->wires[remap_name(c->get("\\S").as_wire()->name)])); + cell->set("\\Y", RTLIL::SigSpec(module->wires[remap_name(c->get("\\Y").as_wire()->name)])); design->select(module, cell); continue; } if (c->type == "\\DFF") { log_assert(clk_sig.size() == 1); RTLIL::Cell *cell = module->addCell(remap_name(c->name), clk_polarity ? "$_DFF_P_" : "$_DFF_N_"); - cell->connections_["\\D"] = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\D"].as_wire()->name)]); - cell->connections_["\\Q"] = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\Q"].as_wire()->name)]); - cell->connections_["\\C"] = clk_sig; + cell->set("\\D", RTLIL::SigSpec(module->wires[remap_name(c->get("\\D").as_wire()->name)])); + cell->set("\\Q", RTLIL::SigSpec(module->wires[remap_name(c->get("\\Q").as_wire()->name)])); + cell->set("\\C", clk_sig); design->select(module, cell); continue; } @@ -761,23 +761,23 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std cell_stats[RTLIL::unescape_id(c->type)]++; if (c->type == "\\_const0_" || c->type == "\\_const1_") { RTLIL::SigSig conn; - conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections_.begin()->second.as_wire()->name)]); + conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections().begin()->second.as_wire()->name)]); conn.second = RTLIL::SigSpec(c->type == "\\_const0_" ? 0 : 1, 1); - module->connections_.push_back(conn); + module->connect(conn); continue; } if (c->type == "\\_dff_") { log_assert(clk_sig.size() == 1); RTLIL::Cell *cell = module->addCell(remap_name(c->name), clk_polarity ? "$_DFF_P_" : "$_DFF_N_"); - cell->connections_["\\D"] = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\D"].as_wire()->name)]); - cell->connections_["\\Q"] = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\Q"].as_wire()->name)]); - cell->connections_["\\C"] = clk_sig; + cell->set("\\D", RTLIL::SigSpec(module->wires[remap_name(c->get("\\D").as_wire()->name)])); + cell->set("\\Q", RTLIL::SigSpec(module->wires[remap_name(c->get("\\Q").as_wire()->name)])); + cell->set("\\C", clk_sig); design->select(module, cell); continue; } RTLIL::Cell *cell = module->addCell(remap_name(c->name), c->type); cell->parameters = c->parameters; - for (auto &conn : c->connections_) { + for (auto &conn : c->connections()) { RTLIL::SigSpec newsig; for (auto &c : conn.second.chunks()) { if (c.width == 0) @@ -785,18 +785,18 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std assert(c.width == 1); newsig.append(module->wires[remap_name(c.wire->name)]); } - cell->connections_[conn.first] = newsig; + cell->connections()[conn.first] = newsig; } design->select(module, cell); } } - for (auto conn : mapped_mod->connections_) { + for (auto conn : mapped_mod->connections()) { if (!conn.first.is_fully_const()) conn.first = RTLIL::SigSpec(module->wires[remap_name(conn.first.as_wire()->name)]); if (!conn.second.is_fully_const()) conn.second = RTLIL::SigSpec(module->wires[remap_name(conn.second.as_wire()->name)]); - module->connections_.push_back(conn); + module->connect(conn); } for (auto &it : cell_stats) @@ -816,7 +816,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std conn.second = si.bit; in_wires++; } - module->connections_.push_back(conn); + module->connect(conn); } log("ABC RESULTS: internal signals: %8d\n", int(signal_list.size()) - in_wires - out_wires); log("ABC RESULTS: input signals: %8d\n", in_wires); diff --git a/passes/abc/blifparse.cc b/passes/abc/blifparse.cc index 122f78454..e5bfb98b4 100644 --- a/passes/abc/blifparse.cc +++ b/passes/abc/blifparse.cc @@ -128,8 +128,8 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name) } RTLIL::Cell *cell = module->addCell(NEW_ID, dff_name); - cell->connections_["\\D"] = module->wires.at(RTLIL::escape_id(d)); - cell->connections_["\\Q"] = module->wires.at(RTLIL::escape_id(q)); + cell->set("\\D", module->wires.at(RTLIL::escape_id(d))); + cell->set("\\Q", module->wires.at(RTLIL::escape_id(q))); continue; } @@ -148,7 +148,7 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name) *(q++) = 0; if (module->wires.count(RTLIL::escape_id(q)) == 0) module->addWire(RTLIL::escape_id(q)); - cell->connections_[RTLIL::escape_id(p)] = module->wires.at(RTLIL::escape_id(q)); + cell->connections()[RTLIL::escape_id(p)] = module->wires.at(RTLIL::escape_id(q)); } continue; } @@ -199,15 +199,15 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name) finished_parsing_constval: if (state == RTLIL::State::Sa) state = RTLIL::State::S1; - module->connections_.push_back(RTLIL::SigSig(output_sig, state)); + module->connect(RTLIL::SigSig(output_sig, state)); goto continue_without_read; } RTLIL::Cell *cell = module->addCell(NEW_ID, "$lut"); cell->parameters["\\WIDTH"] = RTLIL::Const(input_sig.size()); cell->parameters["\\LUT"] = RTLIL::Const(RTLIL::State::Sx, 1 << input_sig.size()); - cell->connections_["\\I"] = input_sig; - cell->connections_["\\O"] = output_sig; + cell->set("\\I", input_sig); + cell->set("\\O", output_sig); lutptr = &cell->parameters.at("\\LUT"); lut_default_state = RTLIL::State::Sx; continue; diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc index ce8ecc32d..9004bf75b 100644 --- a/passes/cmds/add.cc +++ b/passes/cmds/add.cc @@ -75,10 +75,10 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n continue; if (mod->get_bool_attribute("\\blackbox")) continue; - if (it.second->connections_.count(name) > 0) + if (it.second->connections().count(name) > 0) continue; - it.second->connections_[name] = wire; + it.second->connections()[name] = wire; log("Added connection %s to cell %s.%s (%s).\n", name.c_str(), module->name.c_str(), it.first.c_str(), it.second->type.c_str()); } } diff --git a/passes/cmds/connect.cc b/passes/cmds/connect.cc index ea05026f3..ffe7a5efa 100644 --- a/passes/cmds/connect.cc +++ b/passes/cmds/connect.cc @@ -30,11 +30,11 @@ static void unset_drivers(RTLIL::Design *design, RTLIL::Module *module, SigMap & RTLIL::Wire *dummy_wire = module->addWire(NEW_ID, sig.size()); for (auto &it : module->cells) - for (auto &port : it.second->connections_) + for (auto &port : it.second->connections()) if (ct.cell_output(it.second->type, port.first)) sigmap(port.second).replace(sig, dummy_wire, &port.second); - for (auto &conn : module->connections_) + for (auto &conn : module->connections()) sigmap(conn.first).replace(sig, dummy_wire, &conn.first); } @@ -123,7 +123,7 @@ struct ConnectPass : public Pass { SigMap sigmap; if (!flag_nomap) - for (auto &it : module->connections_) { + for (auto &it : module->connections()) { std::vector lhs = it.first.to_sigbit_vector(); std::vector rhs = it.first.to_sigbit_vector(); for (size_t i = 0; i < lhs.size(); i++) @@ -148,7 +148,7 @@ struct ConnectPass : public Pass { if (!flag_nounset) unset_drivers(design, module, sigmap, sig_lhs); - module->connections_.push_back(RTLIL::SigSig(sig_lhs, sig_rhs)); + module->connect(RTLIL::SigSig(sig_lhs, sig_rhs)); } else if (!unset_expr.empty()) @@ -176,7 +176,7 @@ struct ConnectPass : public Pass { if (!RTLIL::SigSpec::parse_sel(sig, design, module, port_expr)) log_cmd_error("Failed to parse port expression `%s'.\n", port_expr.c_str()); - module->cells.at(RTLIL::escape_id(port_cell))->connections_[RTLIL::escape_id(port_port)] = sigmap(sig); + module->cells.at(RTLIL::escape_id(port_cell))->connections()[RTLIL::escape_id(port_port)] = sigmap(sig); } else log_cmd_error("Expected -set, -unset, or -port.\n"); diff --git a/passes/cmds/connwrappers.cc b/passes/cmds/connwrappers.cc index 87ed3d856..d7560ab1a 100644 --- a/passes/cmds/connwrappers.cc +++ b/passes/cmds/connwrappers.cc @@ -74,7 +74,7 @@ struct ConnwrappersWorker if (!decl_celltypes.count(cell->type)) continue; - for (auto &conn : cell->connections_) + for (auto &conn : cell->connections()) { std::pair key(cell->type, conn.first); @@ -109,7 +109,7 @@ struct ConnwrappersWorker if (!design->selected(module, cell)) continue; - for (auto &conn : cell->connections_) + for (auto &conn : cell->connections()) { std::vector sigbits = sigmap(conn.second).to_sigbit_vector(); RTLIL::SigSpec old_sig; diff --git a/passes/cmds/scatter.cc b/passes/cmds/scatter.cc index 0028f7ead..1a780466a 100644 --- a/passes/cmds/scatter.cc +++ b/passes/cmds/scatter.cc @@ -49,7 +49,7 @@ struct ScatterPass : public Pass { continue; for (auto &c : mod_it.second->cells) - for (auto &p : c.second->connections_) + for (auto &p : c.second->connections()) { RTLIL::Wire *wire = new RTLIL::Wire; wire->name = NEW_ID; @@ -58,10 +58,10 @@ struct ScatterPass : public Pass { if (ct.cell_output(c.second->type, p.first)) { RTLIL::SigSig sigsig(p.second, wire); - mod_it.second->connections_.push_back(sigsig); + mod_it.second->connect(sigsig); } else { RTLIL::SigSig sigsig(wire, p.second); - mod_it.second->connections_.push_back(sigsig); + mod_it.second->connect(sigsig); } p.second = wire; diff --git a/passes/cmds/scc.cc b/passes/cmds/scc.cc index 40a2e48cb..3380a935a 100644 --- a/passes/cmds/scc.cc +++ b/passes/cmds/scc.cc @@ -132,7 +132,7 @@ struct SccWorker RTLIL::SigSpec inputSignals, outputSignals; - for (auto &conn : cell->connections_) + for (auto &conn : cell->connections()) { bool isInput = true, isOutput = true; diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index 5d991d038..e0f1a6d69 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -380,7 +380,7 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v if (lhs.selected_member(mod_it.first, it.first) && limits.count(it.first) == 0) selected_wires.insert(it.second); - for (auto &conn : mod->connections_) + for (auto &conn : mod->connections()) { std::vector conn_lhs = conn.first.to_sigbit_vector(); std::vector conn_rhs = conn.second.to_sigbit_vector(); @@ -396,7 +396,7 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v } for (auto &cell : mod->cells) - for (auto &conn : cell.second->connections_) + for (auto &conn : cell.second->connections()) { char last_mode = '-'; for (auto &rule : rules) { diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index e1005a270..e26106103 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -135,7 +135,7 @@ struct SetundefPass : public Pass { CellTypes ct(design); for (auto &it : module->cells) - for (auto &conn : it.second->connections_) + for (auto &conn : it.second->connections()) if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first)) undriven_signals.del(sigmap(conn.second)); @@ -144,7 +144,7 @@ struct SetundefPass : public Pass { RTLIL::SigSpec bits; for (int i = 0; i < c.width; i++) bits.append(worker.next_bit()); - module->connections_.push_back(RTLIL::SigSig(c, bits)); + module->connect(RTLIL::SigSig(c, bits)); } } diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index 29b83a9aa..441268ee9 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -344,7 +344,7 @@ struct ShowWorker std::vector in_ports, out_ports; - for (auto &conn : it.second->connections_) { + for (auto &conn : it.second->connections()) { if (!ct.cell_output(it.second->type, conn.first)) in_ports.push_back(conn.first); else @@ -368,7 +368,7 @@ struct ShowWorker label_string += "}}"; std::string code; - for (auto &conn : it.second->connections_) { + for (auto &conn : it.second->connections()) { code += gen_portbox(stringf("c%d:p%d", id2num(it.first), id2num(conn.first)), conn.second, ct.cell_output(it.second->type, conn.first)); } @@ -421,7 +421,7 @@ struct ShowWorker fprintf(f, "p%d [shape=box, style=rounded, label=\"PROC %s\\n%s\"];\n", pidx, findLabel(proc->name), proc_src.c_str()); } - for (auto &conn : module->connections_) + for (auto &conn : module->connections()) { bool found_lhs_wire = false; for (auto &c : conn.first.chunks()) { @@ -516,7 +516,7 @@ struct ShowWorker log("Skipping blackbox module %s.\n", id2cstr(module->name)); continue; } else - if (module->cells.empty() && module->connections_.empty() && module->processes.empty()) { + if (module->cells.empty() && module->connections().empty() && module->processes.empty()) { log("Skipping empty module %s.\n", id2cstr(module->name)); continue; } else @@ -695,7 +695,7 @@ struct ShowPass : public Pass { for (auto &mod_it : design->modules) { if (mod_it.second->get_bool_attribute("\\blackbox")) continue; - if (mod_it.second->cells.empty() && mod_it.second->connections_.empty()) + if (mod_it.second->cells.empty() && mod_it.second->connections().empty()) continue; if (design->selected_module(mod_it.first)) modcount++; diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc index c8b3d0b0c..94f8365bc 100644 --- a/passes/cmds/splice.cc +++ b/passes/cmds/splice.cc @@ -74,9 +74,9 @@ struct SpliceWorker cell->parameters["\\OFFSET"] = offset; cell->parameters["\\A_WIDTH"] = sig_a.size(); cell->parameters["\\Y_WIDTH"] = sig.size(); - cell->connections_["\\A"] = sig_a; - cell->connections_["\\Y"] = module->addWire(NEW_ID, sig.size()); - new_sig = cell->connections_["\\Y"]; + cell->set("\\A", sig_a); + cell->set("\\Y", module->addWire(NEW_ID, sig.size())); + new_sig = cell->get("\\Y"); } sliced_signals_cache[sig] = new_sig; @@ -130,10 +130,10 @@ struct SpliceWorker RTLIL::Cell *cell = module->addCell(NEW_ID, "$concat"); cell->parameters["\\A_WIDTH"] = new_sig.size(); cell->parameters["\\B_WIDTH"] = sig2.size(); - cell->connections_["\\A"] = new_sig; - cell->connections_["\\B"] = sig2; - cell->connections_["\\Y"] = module->addWire(NEW_ID, new_sig.size() + sig2.size()); - new_sig = cell->connections_["\\Y"]; + cell->set("\\A", new_sig); + cell->set("\\B", sig2); + cell->set("\\Y", module->addWire(NEW_ID, new_sig.size() + sig2.size())); + new_sig = cell->get("\\Y"); } spliced_signals_cache[sig] = new_sig; @@ -159,7 +159,7 @@ struct SpliceWorker } for (auto &it : module->cells) - for (auto &conn : it.second->connections_) + for (auto &conn : it.second->connections()) if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first)) { RTLIL::SigSpec sig = sigmap(conn.second); driven_chunks.insert(sig); @@ -182,7 +182,7 @@ struct SpliceWorker for (auto &it : module->cells) { if (!sel_by_wire && !design->selected(module, it.second)) continue; - for (auto &conn : it.second->connections_) + for (auto &conn : it.second->connections()) if (ct.cell_input(it.second->type, conn.first)) { if (ports.size() > 0 && !ports.count(conn.first)) continue; @@ -232,7 +232,7 @@ struct SpliceWorker it.first->port_output = false; module->add(it.first); module->add(new_port); - module->connections_.push_back(RTLIL::SigSig(new_port, it.second)); + module->connect(RTLIL::SigSig(new_port, it.second)); } } }; diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc index 497d0a2a7..28575e7b4 100644 --- a/passes/cmds/splitnets.cc +++ b/passes/cmds/splitnets.cc @@ -134,7 +134,7 @@ struct SplitnetsPass : public Pass { std::map> split_wires_at; for (auto &c : module->cells) - for (auto &p : c.second->connections_) + for (auto &p : c.second->connections()) { if (!ct.cell_known(c.second->type)) continue; diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc index e59676599..be851afa6 100644 --- a/passes/fsm/fsm_detect.cc +++ b/passes/fsm/fsm_detect.cc @@ -52,8 +52,8 @@ static bool check_state_mux_tree(RTLIL::SigSpec old_sig, RTLIL::SigSpec sig, Sig for (auto &cellport : cellport_list) { if ((cellport.first->type != "$mux" && cellport.first->type != "$pmux" && cellport.first->type != "$safe_pmux") || cellport.second != "\\Y") return false; - RTLIL::SigSpec sig_a = assign_map(cellport.first->connections_["\\A"]); - RTLIL::SigSpec sig_b = assign_map(cellport.first->connections_["\\B"]); + RTLIL::SigSpec sig_a = assign_map(cellport.first->get("\\A")); + RTLIL::SigSpec sig_b = assign_map(cellport.first->get("\\B")); if (!check_state_mux_tree(old_sig, sig_a, recursion_monitor)) return false; for (int i = 0; i < sig_b.size(); i += sig_a.size()) @@ -80,14 +80,14 @@ static bool check_state_users(RTLIL::SigSpec sig) continue; if (cellport.second != "\\A" && cellport.second != "\\B") return false; - if (cell->connections_.count("\\A") == 0 || cell->connections_.count("\\B") == 0 || cell->connections_.count("\\Y") == 0) + if (cell->connections().count("\\A") == 0 || cell->connections().count("\\B") == 0 || cell->connections().count("\\Y") == 0) return false; - for (auto &port_it : cell->connections_) + for (auto &port_it : cell->connections()) if (port_it.first != "\\A" && port_it.first != "\\B" && port_it.first != "\\Y") return false; - if (assign_map(cell->connections_["\\A"]) == sig && cell->connections_["\\B"].is_fully_const()) + if (assign_map(cell->get("\\A")) == sig && cell->get("\\B").is_fully_const()) continue; - if (assign_map(cell->connections_["\\B"]) == sig && cell->connections_["\\A"].is_fully_const()) + if (assign_map(cell->get("\\B")) == sig && cell->get("\\A").is_fully_const()) continue; return false; } @@ -109,8 +109,8 @@ static void detect_fsm(RTLIL::Wire *wire) continue; muxtree_cells.clear(); SigPool recursion_monitor; - RTLIL::SigSpec sig_q = assign_map(cellport.first->connections_["\\Q"]); - RTLIL::SigSpec sig_d = assign_map(cellport.first->connections_["\\D"]); + RTLIL::SigSpec sig_q = assign_map(cellport.first->get("\\Q")); + RTLIL::SigSpec sig_d = assign_map(cellport.first->get("\\D")); if (sig_q == RTLIL::SigSpec(wire) && check_state_mux_tree(sig_q, sig_d, recursion_monitor) && check_state_users(sig_q)) { log("Found FSM state register %s in module %s.\n", wire->name.c_str(), module->name.c_str()); wire->attributes["\\fsm_encoding"] = RTLIL::Const("auto"); @@ -160,7 +160,7 @@ struct FsmDetectPass : public Pass { sig2user.clear(); sig_at_port.clear(); for (auto &cell_it : module->cells) - for (auto &conn_it : cell_it.second->connections_) { + for (auto &conn_it : cell_it.second->connections()) { if (ct.cell_output(cell_it.second->type, conn_it.first) || !ct.cell_known(cell_it.second->type)) { RTLIL::SigSpec sig = conn_it.second; assign_map.apply(sig); diff --git a/passes/fsm/fsm_expand.cc b/passes/fsm/fsm_expand.cc index 431f086d2..126c4866a 100644 --- a/passes/fsm/fsm_expand.cc +++ b/passes/fsm/fsm_expand.cc @@ -43,34 +43,34 @@ struct FsmExpand bool is_cell_merge_candidate(RTLIL::Cell *cell) { if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux") - if (cell->connections_.at("\\A").size() < 2) + if (cell->get("\\A").size() < 2) return true; RTLIL::SigSpec new_signals; - if (cell->connections_.count("\\A") > 0) - new_signals.append(assign_map(cell->connections_["\\A"])); - if (cell->connections_.count("\\B") > 0) - new_signals.append(assign_map(cell->connections_["\\B"])); - if (cell->connections_.count("\\S") > 0) - new_signals.append(assign_map(cell->connections_["\\S"])); - if (cell->connections_.count("\\Y") > 0) - new_signals.append(assign_map(cell->connections_["\\Y"])); + if (cell->connections().count("\\A") > 0) + new_signals.append(assign_map(cell->get("\\A"))); + if (cell->connections().count("\\B") > 0) + new_signals.append(assign_map(cell->get("\\B"))); + if (cell->connections().count("\\S") > 0) + new_signals.append(assign_map(cell->get("\\S"))); + if (cell->connections().count("\\Y") > 0) + new_signals.append(assign_map(cell->get("\\Y"))); new_signals.sort_and_unify(); new_signals.remove_const(); - new_signals.remove(assign_map(fsm_cell->connections_["\\CTRL_IN"])); - new_signals.remove(assign_map(fsm_cell->connections_["\\CTRL_OUT"])); + new_signals.remove(assign_map(fsm_cell->get("\\CTRL_IN"))); + new_signals.remove(assign_map(fsm_cell->get("\\CTRL_OUT"))); if (new_signals.size() > 3) return false; - if (cell->connections_.count("\\Y") > 0) { - new_signals.append(assign_map(cell->connections_["\\Y"])); + if (cell->connections().count("\\Y") > 0) { + new_signals.append(assign_map(cell->get("\\Y"))); new_signals.sort_and_unify(); new_signals.remove_const(); - new_signals.remove(assign_map(fsm_cell->connections_["\\CTRL_IN"])); - new_signals.remove(assign_map(fsm_cell->connections_["\\CTRL_OUT"])); + new_signals.remove(assign_map(fsm_cell->get("\\CTRL_IN"))); + new_signals.remove(assign_map(fsm_cell->get("\\CTRL_OUT"))); } if (new_signals.size() > 2) @@ -83,10 +83,10 @@ struct FsmExpand { std::vector cell_list; - for (auto c : sig2driver.find(assign_map(fsm_cell->connections_["\\CTRL_IN"]))) + for (auto c : sig2driver.find(assign_map(fsm_cell->get("\\CTRL_IN")))) cell_list.push_back(c); - for (auto c : sig2user.find(assign_map(fsm_cell->connections_["\\CTRL_OUT"]))) + for (auto c : sig2user.find(assign_map(fsm_cell->get("\\CTRL_OUT")))) cell_list.push_back(c); current_set.clear(); @@ -94,7 +94,7 @@ struct FsmExpand { if (merged_set.count(c) > 0 || current_set.count(c) > 0 || no_candidate_set.count(c) > 0) continue; - for (auto &p : c->connections_) { + for (auto &p : c->connections()) { if (p.first != "\\A" && p.first != "\\B" && p.first != "\\S" && p.first != "\\Y") goto next_cell; } @@ -135,7 +135,7 @@ struct FsmExpand RTLIL::SigSpec input_sig, output_sig; - for (auto &p : cell->connections_) + for (auto &p : cell->connections()) if (ct.cell_output(cell->type, p.first)) output_sig.append(assign_map(p.second)); else @@ -148,12 +148,12 @@ struct FsmExpand for (int i = 0; i < (1 << input_sig.size()); i++) { RTLIL::Const in_val(i, input_sig.size()); RTLIL::SigSpec A, B, S; - if (cell->connections_.count("\\A") > 0) - A = assign_map(cell->connections_["\\A"]); - if (cell->connections_.count("\\B") > 0) - B = assign_map(cell->connections_["\\B"]); - if (cell->connections_.count("\\S") > 0) - S = assign_map(cell->connections_["\\S"]); + if (cell->connections().count("\\A") > 0) + A = assign_map(cell->get("\\A")); + if (cell->connections().count("\\B") > 0) + B = assign_map(cell->get("\\B")); + if (cell->connections().count("\\S") > 0) + S = assign_map(cell->get("\\S")); A.replace(input_sig, RTLIL::SigSpec(in_val)); B.replace(input_sig, RTLIL::SigSpec(in_val)); S.replace(input_sig, RTLIL::SigSpec(in_val)); @@ -167,10 +167,10 @@ struct FsmExpand fsm_data.copy_from_cell(fsm_cell); fsm_data.num_inputs += input_sig.size(); - fsm_cell->connections_["\\CTRL_IN"].append(input_sig); + fsm_cell->get("\\CTRL_IN").append(input_sig); fsm_data.num_outputs += output_sig.size(); - fsm_cell->connections_["\\CTRL_OUT"].append(output_sig); + fsm_cell->get("\\CTRL_OUT").append(output_sig); std::vector new_transition_table; for (auto &tr : fsm_data.transition_table) { @@ -204,7 +204,7 @@ struct FsmExpand for (auto &cell_it : module->cells) { RTLIL::Cell *c = cell_it.second; if (ct.cell_known(c->type) && design->selected(mod, c)) - for (auto &p : c->connections_) { + for (auto &p : c->connections()) { if (ct.cell_output(c->type, p.first)) sig2driver.insert(assign_map(p.second), c); else diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index b0e1c903b..3ded8aca7 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -58,9 +58,9 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL log(" unexpected cell type %s (%s) found in state selection tree.\n", cell->type.c_str(), cell->name.c_str()); return false; } - RTLIL::SigSpec sig_a = assign_map(cell->connections_["\\A"]); - RTLIL::SigSpec sig_b = assign_map(cell->connections_["\\B"]); - RTLIL::SigSpec sig_s = assign_map(cell->connections_["\\S"]); + RTLIL::SigSpec sig_a = assign_map(cell->get("\\A")); + RTLIL::SigSpec sig_b = assign_map(cell->get("\\B")); + RTLIL::SigSpec sig_s = assign_map(cell->get("\\S")); if (reset_state && RTLIL::SigSpec(*reset_state).is_fully_undef()) do { if (sig_a.is_fully_def()) @@ -183,12 +183,12 @@ static void extract_fsm(RTLIL::Wire *wire) if ((cell->type != "$dff" && cell->type != "$adff") || cellport.second != "\\Q") continue; log(" found %s cell for state register: %s\n", cell->type.c_str(), cell->name.c_str()); - RTLIL::SigSpec sig_q = assign_map(cell->connections_["\\Q"]); - RTLIL::SigSpec sig_d = assign_map(cell->connections_["\\D"]); - clk = cell->connections_["\\CLK"]; + RTLIL::SigSpec sig_q = assign_map(cell->get("\\Q")); + RTLIL::SigSpec sig_d = assign_map(cell->get("\\D")); + clk = cell->get("\\CLK"); clk_polarity = cell->parameters["\\CLK_POLARITY"].as_bool(); if (cell->type == "$adff") { - arst = cell->connections_["\\ARST"]; + arst = cell->get("\\ARST"); arst_polarity = cell->parameters["\\ARST_POLARITY"].as_bool(); reset_state = cell->parameters["\\ARST_VALUE"]; } @@ -224,9 +224,9 @@ static void extract_fsm(RTLIL::Wire *wire) sig2trigger.find(dff_out, cellport_list); for (auto &cellport : cellport_list) { RTLIL::Cell *cell = module->cells.at(cellport.first); - RTLIL::SigSpec sig_a = assign_map(cell->connections_["\\A"]); - RTLIL::SigSpec sig_b = assign_map(cell->connections_["\\B"]); - RTLIL::SigSpec sig_y = assign_map(cell->connections_["\\Y"]); + RTLIL::SigSpec sig_a = assign_map(cell->get("\\A")); + RTLIL::SigSpec sig_b = assign_map(cell->get("\\B")); + RTLIL::SigSpec sig_y = assign_map(cell->get("\\Y")); if (cellport.second == "\\A" && !sig_b.is_fully_const()) continue; if (cellport.second == "\\B" && !sig_a.is_fully_const()) @@ -271,12 +271,12 @@ static void extract_fsm(RTLIL::Wire *wire) // create fsm cell RTLIL::Cell *fsm_cell = module->addCell(stringf("$fsm$%s$%d", wire->name.c_str(), RTLIL::autoidx++), "$fsm"); - fsm_cell->connections_["\\CLK"] = clk; - fsm_cell->connections_["\\ARST"] = arst; + fsm_cell->set("\\CLK", clk); + fsm_cell->set("\\ARST", arst); fsm_cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity ? 1 : 0, 1); fsm_cell->parameters["\\ARST_POLARITY"] = RTLIL::Const(arst_polarity ? 1 : 0, 1); - fsm_cell->connections_["\\CTRL_IN"] = ctrl_in; - fsm_cell->connections_["\\CTRL_OUT"] = ctrl_out; + fsm_cell->set("\\CTRL_IN", ctrl_in); + fsm_cell->set("\\CTRL_OUT", ctrl_out); fsm_cell->parameters["\\NAME"] = RTLIL::Const(wire->name); fsm_cell->attributes = wire->attributes; fsm_data.copy_to_cell(fsm_cell); @@ -294,13 +294,13 @@ static void extract_fsm(RTLIL::Wire *wire) sig2driver.find(ctrl_out, cellport_list); for (auto &cellport : cellport_list) { RTLIL::Cell *cell = module->cells.at(cellport.first); - RTLIL::SigSpec port_sig = assign_map(cell->connections_[cellport.second]); + RTLIL::SigSpec port_sig = assign_map(cell->connections()[cellport.second]); RTLIL::SigSpec unconn_sig = port_sig.extract(ctrl_out); RTLIL::Wire *unconn_wire = new RTLIL::Wire; unconn_wire->name = stringf("$fsm_unconnect$%s$%d", log_signal(unconn_sig), RTLIL::autoidx++); unconn_wire->width = unconn_sig.size(); module->wires[unconn_wire->name] = unconn_wire; - port_sig.replace(unconn_sig, RTLIL::SigSpec(unconn_wire), &cell->connections_[cellport.second]); + port_sig.replace(unconn_sig, RTLIL::SigSpec(unconn_wire), &cell->connections()[cellport.second]); } } @@ -344,14 +344,14 @@ struct FsmExtractPass : public Pass { sig2driver.clear(); sig2trigger.clear(); for (auto &cell_it : module->cells) - for (auto &conn_it : cell_it.second->connections_) { + for (auto &conn_it : cell_it.second->connections()) { if (ct.cell_output(cell_it.second->type, conn_it.first) || !ct.cell_known(cell_it.second->type)) { RTLIL::SigSpec sig = conn_it.second; assign_map.apply(sig); sig2driver.insert(sig, sig2driver_entry_t(cell_it.first, conn_it.first)); } - if (ct.cell_input(cell_it.second->type, conn_it.first) && cell_it.second->connections_.count("\\Y") > 0 && - cell_it.second->connections_["\\Y"].size() == 1 && (conn_it.first == "\\A" || conn_it.first == "\\B")) { + if (ct.cell_input(cell_it.second->type, conn_it.first) && cell_it.second->connections().count("\\Y") > 0 && + cell_it.second->get("\\Y").size() == 1 && (conn_it.first == "\\A" || conn_it.first == "\\B")) { RTLIL::SigSpec sig = conn_it.second; assign_map.apply(sig); sig2trigger.insert(sig, sig2driver_entry_t(cell_it.first, conn_it.first)); diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc index cf482d6df..a22441b4a 100644 --- a/passes/fsm/fsm_map.cc +++ b/passes/fsm/fsm_map.cc @@ -58,9 +58,9 @@ static void implement_pattern_cache(RTLIL::Module *module, std::mapaddCell(NEW_ID, "$eq"); - eq_cell->connections_["\\A"] = eq_sig_a; - eq_cell->connections_["\\B"] = eq_sig_b; - eq_cell->connections_["\\Y"] = RTLIL::SigSpec(eq_wire); + eq_cell->set("\\A", eq_sig_a); + eq_cell->set("\\B", eq_sig_b); + eq_cell->set("\\Y", RTLIL::SigSpec(eq_wire)); eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false); eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false); eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(eq_sig_a.size()); @@ -80,8 +80,8 @@ static void implement_pattern_cache(RTLIL::Module *module, std::mapaddCell(NEW_ID, "$reduce_or"); - or_cell->connections_["\\A"] = or_sig; - or_cell->connections_["\\Y"] = RTLIL::SigSpec(or_wire); + or_cell->set("\\A", or_sig); + or_cell->set("\\Y", RTLIL::SigSpec(or_wire)); or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false); or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(or_sig.size()); or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); @@ -96,9 +96,9 @@ static void implement_pattern_cache(RTLIL::Module *module, std::mapaddCell(NEW_ID, "$and"); - and_cell->connections_["\\A"] = and_sig.extract(0, 1); - and_cell->connections_["\\B"] = and_sig.extract(1, 1); - and_cell->connections_["\\Y"] = RTLIL::SigSpec(and_wire); + and_cell->set("\\A", and_sig.extract(0, 1)); + and_cell->set("\\B", and_sig.extract(1, 1)); + and_cell->set("\\Y", RTLIL::SigSpec(and_wire)); and_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false); and_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false); and_cell->parameters["\\A_WIDTH"] = RTLIL::Const(1); @@ -119,15 +119,15 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map 1) { RTLIL::Cell *or_cell = module->addCell(NEW_ID, "$reduce_or"); - or_cell->connections_["\\A"] = cases_vector; - or_cell->connections_["\\Y"] = output; + or_cell->set("\\A", cases_vector); + or_cell->set("\\Y", output); or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false); or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cases_vector.size()); or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); } else if (cases_vector.size() == 1) { - module->connections_.push_back(RTLIL::SigSig(output, cases_vector)); + module->connect(RTLIL::SigSig(output, cases_vector)); } else { - module->connections_.push_back(RTLIL::SigSig(output, RTLIL::SigSpec(0, 1))); + module->connect(RTLIL::SigSig(output, RTLIL::SigSpec(0, 1))); } } @@ -138,8 +138,8 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) FsmData fsm_data; fsm_data.copy_from_cell(fsm_cell); - RTLIL::SigSpec ctrl_in = fsm_cell->connections_["\\CTRL_IN"]; - RTLIL::SigSpec ctrl_out = fsm_cell->connections_["\\CTRL_OUT"]; + RTLIL::SigSpec ctrl_in = fsm_cell->get("\\CTRL_IN"); + RTLIL::SigSpec ctrl_out = fsm_cell->get("\\CTRL_OUT"); // create state register @@ -153,7 +153,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) RTLIL::Wire *next_state_wire = module->addWire(NEW_ID, fsm_data.state_bits); RTLIL::Cell *state_dff = module->addCell(NEW_ID, ""); - if (fsm_cell->connections_["\\ARST"].is_fully_const()) { + if (fsm_cell->get("\\ARST").is_fully_const()) { state_dff->type = "$dff"; } else { state_dff->type = "$adff"; @@ -162,13 +162,13 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) for (auto &bit : state_dff->parameters["\\ARST_VALUE"].bits) if (bit != RTLIL::State::S1) bit = RTLIL::State::S0; - state_dff->connections_["\\ARST"] = fsm_cell->connections_["\\ARST"]; + state_dff->set("\\ARST", fsm_cell->get("\\ARST")); } state_dff->parameters["\\WIDTH"] = RTLIL::Const(fsm_data.state_bits); state_dff->parameters["\\CLK_POLARITY"] = fsm_cell->parameters["\\CLK_POLARITY"]; - state_dff->connections_["\\CLK"] = fsm_cell->connections_["\\CLK"]; - state_dff->connections_["\\D"] = RTLIL::SigSpec(next_state_wire); - state_dff->connections_["\\Q"] = RTLIL::SigSpec(state_wire); + state_dff->set("\\CLK", fsm_cell->get("\\CLK")); + state_dff->set("\\D", RTLIL::SigSpec(next_state_wire)); + state_dff->set("\\Q", RTLIL::SigSpec(state_wire)); // decode state register @@ -189,16 +189,16 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) if (sig_b == RTLIL::SigSpec(RTLIL::State::S1)) { - module->connections_.push_back(RTLIL::SigSig(RTLIL::SigSpec(state_onehot, i), sig_a)); + module->connect(RTLIL::SigSig(RTLIL::SigSpec(state_onehot, i), sig_a)); } else { encoding_is_onehot = false; RTLIL::Cell *eq_cell = module->addCell(NEW_ID, "$eq"); - eq_cell->connections_["\\A"] = sig_a; - eq_cell->connections_["\\B"] = sig_b; - eq_cell->connections_["\\Y"] = RTLIL::SigSpec(state_onehot, i); + eq_cell->set("\\A", sig_a); + eq_cell->set("\\B", sig_b); + eq_cell->set("\\Y", RTLIL::SigSpec(state_onehot, i)); eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false); eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false); eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_a.size()); @@ -245,7 +245,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) next_state_sig.replace(bit_idx, RTLIL::SigSpec(next_state_onehot, i)); } log_assert(!next_state_sig.has_marked_bits()); - module->connections_.push_back(RTLIL::SigSig(next_state_wire, next_state_sig)); + module->connect(RTLIL::SigSig(next_state_wire, next_state_sig)); } else { @@ -265,10 +265,10 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) } RTLIL::Cell *mux_cell = module->addCell(NEW_ID, "$safe_pmux"); - mux_cell->connections_["\\A"] = sig_a; - mux_cell->connections_["\\B"] = sig_b; - mux_cell->connections_["\\S"] = sig_s; - mux_cell->connections_["\\Y"] = RTLIL::SigSpec(next_state_wire); + mux_cell->set("\\A", sig_a); + mux_cell->set("\\B", sig_b); + mux_cell->set("\\S", sig_s); + mux_cell->set("\\Y", RTLIL::SigSpec(next_state_wire)); mux_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_a.size()); mux_cell->parameters["\\S_WIDTH"] = RTLIL::Const(sig_s.size()); } diff --git a/passes/fsm/fsm_opt.cc b/passes/fsm/fsm_opt.cc index 3fde534da..e82b53631 100644 --- a/passes/fsm/fsm_opt.cc +++ b/passes/fsm/fsm_opt.cc @@ -52,7 +52,7 @@ struct FsmOpt void opt_const_and_unused_inputs() { - RTLIL::SigSpec ctrl_in = cell->connections_["\\CTRL_IN"]; + RTLIL::SigSpec ctrl_in = cell->get("\\CTRL_IN"); std::vector ctrl_in_used(ctrl_in.size()); std::vector new_transition_table; @@ -73,13 +73,13 @@ struct FsmOpt for (int i = int(ctrl_in_used.size())-1; i >= 0; i--) { if (!ctrl_in_used[i]) { - log(" Removing unused input signal %s.\n", log_signal(cell->connections_["\\CTRL_IN"].extract(i, 1))); + log(" Removing unused input signal %s.\n", log_signal(cell->get("\\CTRL_IN").extract(i, 1))); for (auto &tr : new_transition_table) { RTLIL::SigSpec tmp(tr.ctrl_in); tmp.remove(i, 1); tr.ctrl_in = tmp.as_const(); } - cell->connections_["\\CTRL_IN"].remove(i, 1); + cell->get("\\CTRL_IN").remove(i, 1); fsm_data.num_inputs--; } } @@ -91,10 +91,10 @@ struct FsmOpt void opt_unused_outputs() { for (int i = 0; i < fsm_data.num_outputs; i++) { - RTLIL::SigSpec sig = cell->connections_["\\CTRL_OUT"].extract(i, 1); + RTLIL::SigSpec sig = cell->get("\\CTRL_OUT").extract(i, 1); if (signal_is_unused(sig)) { log(" Removing unused output signal %s.\n", log_signal(sig)); - cell->connections_["\\CTRL_OUT"].remove(i, 1); + cell->get("\\CTRL_OUT").remove(i, 1); for (auto &tr : fsm_data.transition_table) { RTLIL::SigSpec tmp(tr.ctrl_out); tmp.remove(i, 1); @@ -108,7 +108,7 @@ struct FsmOpt void opt_alias_inputs() { - RTLIL::SigSpec &ctrl_in = cell->connections_["\\CTRL_IN"]; + RTLIL::SigSpec &ctrl_in = cell->get("\\CTRL_IN"); for (int i = 0; i < ctrl_in.size(); i++) for (int j = i+1; j < ctrl_in.size(); j++) @@ -145,8 +145,8 @@ struct FsmOpt void opt_feedback_inputs() { - RTLIL::SigSpec &ctrl_in = cell->connections_["\\CTRL_IN"]; - RTLIL::SigSpec &ctrl_out = cell->connections_["\\CTRL_OUT"]; + RTLIL::SigSpec &ctrl_in = cell->get("\\CTRL_IN"); + RTLIL::SigSpec &ctrl_out = cell->get("\\CTRL_OUT"); for (int j = 0; j < ctrl_out.size(); j++) for (int i = 0; i < ctrl_in.size(); i++) diff --git a/passes/fsm/fsmdata.h b/passes/fsm/fsmdata.h index a336d23f7..8f0e5d621 100644 --- a/passes/fsm/fsmdata.h +++ b/passes/fsm/fsmdata.h @@ -141,13 +141,13 @@ struct FsmData log("\n"); log(" Input signals:\n"); - RTLIL::SigSpec sig_in = cell->connections_["\\CTRL_IN"]; + RTLIL::SigSpec sig_in = cell->get("\\CTRL_IN"); for (int i = 0; i < SIZE(sig_in); i++) log(" %3d: %s\n", i, log_signal(sig_in[i])); log("\n"); log(" Output signals:\n"); - RTLIL::SigSpec sig_out = cell->connections_["\\CTRL_OUT"]; + RTLIL::SigSpec sig_out = cell->get("\\CTRL_OUT"); for (int i = 0; i < SIZE(sig_out); i++) log(" %3d: %s\n", i, log_signal(sig_out[i])); diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 4306c29eb..5937373fa 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -58,7 +58,7 @@ static void generate(RTLIL::Design *design, const std::vector &cell for (auto i1 : design->modules) for (auto i2 : i1.second->cells) if (i2.second->type == celltype) { - for (auto &conn : i2.second->connections_) { + for (auto &conn : i2.second->connections()) { if (conn.first[0] != '$') portnames.insert(conn.first); portwidths[conn.first] = std::max(portwidths[conn.first], conn.second.size()); @@ -219,7 +219,7 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla RTLIL::Module *mod = design->modules[cell->type]; - for (auto &conn : cell->connections_) { + for (auto &conn : cell->connections()) { int conn_size = conn.second.size(); std::string portname = conn.first; if (portname.substr(0, 1) == "$") { @@ -486,7 +486,7 @@ struct HierarchyPass : public Pass { RTLIL::Cell *cell = cell_it.second; if (design->modules.count(cell->type) == 0) continue; - for (auto &conn : cell->connections_) + for (auto &conn : cell->connections()) if (conn.first[0] == '$' && '0' <= conn.first[1] && conn.first[1] <= '9') { pos_mods.insert(design->modules.at(cell->type)); pos_work.push_back(std::pair(mod_it.second, cell)); @@ -507,7 +507,7 @@ struct HierarchyPass : public Pass { log("Mapping positional arguments of cell %s.%s (%s).\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); std::map new_connections; - for (auto &conn : cell->connections_) + for (auto &conn : cell->connections()) if (conn.first[0] == '$' && '0' <= conn.first[1] && conn.first[1] <= '9') { int id = atoi(conn.first.c_str()+1); std::pair key(design->modules.at(cell->type), id); @@ -519,7 +519,7 @@ struct HierarchyPass : public Pass { new_connections[pos_map.at(key)] = conn.second; } else new_connections[conn.first] = conn.second; - cell->connections_ = new_connections; + cell->connections() = new_connections; } } diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index df5fd8e37..d72ebb127 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -79,11 +79,11 @@ struct SubmodWorker wire_flags.clear(); for (RTLIL::Cell *cell : submod.cells) { if (ct.cell_known(cell->type)) { - for (auto &conn : cell->connections_) + for (auto &conn : cell->connections()) flag_signal(conn.second, true, ct.cell_output(cell->type, conn.first), ct.cell_input(cell->type, conn.first), false, false); } else { log("WARNING: Port directions for cell %s (%s) are unknown. Assuming inout for all ports.\n", cell->name.c_str(), cell->type.c_str()); - for (auto &conn : cell->connections_) + for (auto &conn : cell->connections()) flag_signal(conn.second, true, true, true, false, false); } } @@ -92,11 +92,11 @@ struct SubmodWorker if (submod.cells.count(cell) > 0) continue; if (ct.cell_known(cell->type)) { - for (auto &conn : cell->connections_) + for (auto &conn : cell->connections()) flag_signal(conn.second, false, false, false, ct.cell_output(cell->type, conn.first), ct.cell_input(cell->type, conn.first)); } else { flag_found_something = false; - for (auto &conn : cell->connections_) + for (auto &conn : cell->connections()) flag_signal(conn.second, false, false, false, true, true); if (flag_found_something) log("WARNING: Port directions for cell %s (%s) are unknown. Assuming inout for all ports.\n", cell->name.c_str(), cell->type.c_str()); @@ -163,7 +163,7 @@ struct SubmodWorker for (RTLIL::Cell *cell : submod.cells) { RTLIL::Cell *new_cell = new_mod->addCell(cell->name, cell); - for (auto &conn : new_cell->connections_) + for (auto &conn : new_cell->connections()) for (auto &bit : conn.second) if (bit.wire != NULL) { assert(wire_flags.count(bit.wire) > 0); @@ -180,7 +180,7 @@ struct SubmodWorker RTLIL::Wire *old_wire = it.first; RTLIL::Wire *new_wire = it.second.new_wire; if (new_wire->port_id > 0) - new_cell->connections_[new_wire->name] = RTLIL::SigSpec(old_wire); + new_cell->connections()[new_wire->name] = RTLIL::SigSpec(old_wire); } } diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc index b4242f250..a8caf883f 100644 --- a/passes/memory/memory_collect.cc +++ b/passes/memory/memory_collect.cc @@ -76,12 +76,12 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) wr_ports++; del_cells.push_back(cell); - RTLIL::SigSpec clk = cell->connections_["\\CLK"]; + RTLIL::SigSpec clk = cell->get("\\CLK"); RTLIL::SigSpec clk_enable = RTLIL::SigSpec(cell->parameters["\\CLK_ENABLE"]); RTLIL::SigSpec clk_polarity = RTLIL::SigSpec(cell->parameters["\\CLK_POLARITY"]); - RTLIL::SigSpec addr = cell->connections_["\\ADDR"]; - RTLIL::SigSpec data = cell->connections_["\\DATA"]; - RTLIL::SigSpec en = cell->connections_["\\EN"]; + RTLIL::SigSpec addr = cell->get("\\ADDR"); + RTLIL::SigSpec data = cell->get("\\DATA"); + RTLIL::SigSpec en = cell->get("\\EN"); clk.extend(1, false); clk_enable.extend(1, false); @@ -103,12 +103,12 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) rd_ports++; del_cells.push_back(cell); - RTLIL::SigSpec clk = cell->connections_["\\CLK"]; + RTLIL::SigSpec clk = cell->get("\\CLK"); RTLIL::SigSpec clk_enable = RTLIL::SigSpec(cell->parameters["\\CLK_ENABLE"]); RTLIL::SigSpec clk_polarity = RTLIL::SigSpec(cell->parameters["\\CLK_POLARITY"]); RTLIL::SigSpec transparent = RTLIL::SigSpec(cell->parameters["\\TRANSPARENT"]); - RTLIL::SigSpec addr = cell->connections_["\\ADDR"]; - RTLIL::SigSpec data = cell->connections_["\\DATA"]; + RTLIL::SigSpec addr = cell->get("\\ADDR"); + RTLIL::SigSpec data = cell->get("\\DATA"); clk.extend(1, false); clk_enable.extend(1, false); @@ -147,10 +147,10 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) mem->parameters["\\WR_CLK_ENABLE"] = wr_ports ? sig_wr_clk_enable.as_const() : RTLIL::Const(0, 0); mem->parameters["\\WR_CLK_POLARITY"] = wr_ports ? sig_wr_clk_polarity.as_const() : RTLIL::Const(0, 0); - mem->connections_["\\WR_CLK"] = sig_wr_clk; - mem->connections_["\\WR_ADDR"] = sig_wr_addr; - mem->connections_["\\WR_DATA"] = sig_wr_data; - mem->connections_["\\WR_EN"] = sig_wr_en; + mem->set("\\WR_CLK", sig_wr_clk); + mem->set("\\WR_ADDR", sig_wr_addr); + mem->set("\\WR_DATA", sig_wr_data); + mem->set("\\WR_EN", sig_wr_en); assert(sig_rd_clk.size() == rd_ports); assert(sig_rd_clk_enable.size() == rd_ports && sig_rd_clk_enable.is_fully_const()); @@ -163,9 +163,9 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) mem->parameters["\\RD_CLK_POLARITY"] = rd_ports ? sig_rd_clk_polarity.as_const() : RTLIL::Const(0, 0); mem->parameters["\\RD_TRANSPARENT"] = rd_ports ? sig_rd_transparent.as_const() : RTLIL::Const(0, 0); - mem->connections_["\\RD_CLK"] = sig_rd_clk; - mem->connections_["\\RD_ADDR"] = sig_rd_addr; - mem->connections_["\\RD_DATA"] = sig_rd_data; + mem->set("\\RD_CLK", sig_rd_clk); + mem->set("\\RD_ADDR", sig_rd_addr); + mem->set("\\RD_DATA", sig_rd_data); for (auto c : del_cells) module->remove(c); diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index 63f7d0527..0513aa3d2 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -25,7 +25,7 @@ static void normalize_sig(RTLIL::Module *module, RTLIL::SigSpec &sig) { - for (auto &conn : module->connections_) + for (auto &conn : module->connections()) sig.replace(conn.first, conn.second); } @@ -46,21 +46,21 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI continue; if (clk != RTLIL::SigSpec(RTLIL::State::Sx)) { - if (cell->connections_["\\CLK"] != clk) + if (cell->get("\\CLK") != clk) continue; if (cell->parameters["\\CLK_POLARITY"].as_bool() != clk_polarity) continue; } - RTLIL::SigSpec q_norm = cell->connections_[after ? "\\D" : "\\Q"]; + RTLIL::SigSpec q_norm = cell->connections()[after ? "\\D" : "\\Q"]; normalize_sig(module, q_norm); - RTLIL::SigSpec d = q_norm.extract(bit, &cell->connections_[after ? "\\Q" : "\\D"]); + RTLIL::SigSpec d = q_norm.extract(bit, &cell->connections()[after ? "\\Q" : "\\D"]); if (d.size() != 1) continue; bit = d; - clk = cell->connections_["\\CLK"]; + clk = cell->get("\\CLK"); clk_polarity = cell->parameters["\\CLK_POLARITY"].as_bool(); goto replaced_this_bit; } @@ -79,29 +79,29 @@ static void handle_wr_cell(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::SigSpec clk = RTLIL::SigSpec(RTLIL::State::Sx); bool clk_polarity = 0; - RTLIL::SigSpec sig_addr = cell->connections_["\\ADDR"]; + RTLIL::SigSpec sig_addr = cell->get("\\ADDR"); if (!find_sig_before_dff(module, sig_addr, clk, clk_polarity)) { log("no (compatible) $dff for address input found.\n"); return; } - RTLIL::SigSpec sig_data = cell->connections_["\\DATA"]; + RTLIL::SigSpec sig_data = cell->get("\\DATA"); if (!find_sig_before_dff(module, sig_data, clk, clk_polarity)) { log("no (compatible) $dff for data input found.\n"); return; } - RTLIL::SigSpec sig_en = cell->connections_["\\EN"]; + RTLIL::SigSpec sig_en = cell->get("\\EN"); if (!find_sig_before_dff(module, sig_en, clk, clk_polarity)) { log("no (compatible) $dff for enable input found.\n"); return; } if (clk != RTLIL::SigSpec(RTLIL::State::Sx)) { - cell->connections_["\\CLK"] = clk; - cell->connections_["\\ADDR"] = sig_addr; - cell->connections_["\\DATA"] = sig_data; - cell->connections_["\\EN"] = sig_en; + cell->set("\\CLK", clk); + cell->set("\\ADDR", sig_addr); + cell->set("\\DATA", sig_data); + cell->set("\\EN", sig_en); cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1); cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity); log("merged $dff to cell.\n"); @@ -128,7 +128,7 @@ static void disconnect_dff(RTLIL::Module *module, RTLIL::SigSpec sig) for (auto &cell_it : module->cells) { RTLIL::Cell *cell = cell_it.second; if (cell->type == "$dff") - cell->connections_["\\Q"].replace(sig, newsig); + cell->get("\\Q").replace(sig, newsig); } } @@ -139,13 +139,13 @@ static void handle_rd_cell(RTLIL::Module *module, RTLIL::Cell *cell) bool clk_polarity = 0; RTLIL::SigSpec clk_data = RTLIL::SigSpec(RTLIL::State::Sx); - RTLIL::SigSpec sig_data = cell->connections_["\\DATA"]; + RTLIL::SigSpec sig_data = cell->get("\\DATA"); if (find_sig_before_dff(module, sig_data, clk_data, clk_polarity, true) && clk_data != RTLIL::SigSpec(RTLIL::State::Sx)) { disconnect_dff(module, sig_data); - cell->connections_["\\CLK"] = clk_data; - cell->connections_["\\DATA"] = sig_data; + cell->set("\\CLK", clk_data); + cell->set("\\DATA", sig_data); cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1); cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity); cell->parameters["\\TRANSPARENT"] = RTLIL::Const(0); @@ -154,12 +154,12 @@ static void handle_rd_cell(RTLIL::Module *module, RTLIL::Cell *cell) } RTLIL::SigSpec clk_addr = RTLIL::SigSpec(RTLIL::State::Sx); - RTLIL::SigSpec sig_addr = cell->connections_["\\ADDR"]; + RTLIL::SigSpec sig_addr = cell->get("\\ADDR"); if (find_sig_before_dff(module, sig_addr, clk_addr, clk_polarity) && clk_addr != RTLIL::SigSpec(RTLIL::State::Sx)) { - cell->connections_["\\CLK"] = clk_addr; - cell->connections_["\\ADDR"] = sig_addr; + cell->set("\\CLK", clk_addr); + cell->set("\\ADDR", sig_addr); cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1); cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity); cell->parameters["\\TRANSPARENT"] = RTLIL::Const(1); diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index a626b5aff..5b180db62 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -62,20 +62,20 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) } // all write ports must share the same clock - RTLIL::SigSpec clocks = cell->connections_["\\WR_CLK"]; + RTLIL::SigSpec clocks = cell->get("\\WR_CLK"); RTLIL::Const clocks_pol = cell->parameters["\\WR_CLK_POLARITY"]; RTLIL::Const clocks_en = cell->parameters["\\WR_CLK_ENABLE"]; RTLIL::SigSpec refclock; RTLIL::State refclock_pol = RTLIL::State::Sx; for (int i = 0; i < clocks.size(); i++) { - RTLIL::SigSpec wr_en = cell->connections_["\\WR_EN"].extract(i * mem_width, mem_width); + RTLIL::SigSpec wr_en = cell->get("\\WR_EN").extract(i * mem_width, mem_width); if (wr_en.is_fully_const() && !wr_en.as_bool()) { static_ports.insert(i); continue; } if (clocks_en.bits[i] != RTLIL::State::S1) { - RTLIL::SigSpec wr_addr = cell->connections_["\\WR_ADDR"].extract(i*mem_abits, mem_abits); - RTLIL::SigSpec wr_data = cell->connections_["\\WR_DATA"].extract(i*mem_width, mem_width); + RTLIL::SigSpec wr_addr = cell->get("\\WR_ADDR").extract(i*mem_abits, mem_abits); + RTLIL::SigSpec wr_data = cell->get("\\WR_DATA").extract(i*mem_width, mem_width); if (wr_addr.is_fully_const()) { // FIXME: Actually we should check for wr_en.is_fully_const() also and // create a $adff cell with this ports wr_en input as reset pin when wr_en @@ -120,10 +120,10 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"]; if (clocks_pol.bits.size() > 0) { c->parameters["\\CLK_POLARITY"] = RTLIL::Const(clocks_pol.bits[0]); - c->connections_["\\CLK"] = clocks.extract(0, 1); + c->set("\\CLK", clocks.extract(0, 1)); } else { c->parameters["\\CLK_POLARITY"] = RTLIL::Const(RTLIL::State::S1); - c->connections_["\\CLK"] = RTLIL::SigSpec(RTLIL::State::S0); + c->set("\\CLK", RTLIL::SigSpec(RTLIL::State::S0)); } RTLIL::Wire *w_in = new RTLIL::Wire; @@ -131,7 +131,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) w_in->width = mem_width; module->wires[w_in->name] = w_in; data_reg_in.push_back(RTLIL::SigSpec(w_in)); - c->connections_["\\D"] = data_reg_in.back(); + c->set("\\D", data_reg_in.back()); RTLIL::Wire *w_out = new RTLIL::Wire; w_out->name = stringf("%s[%d]", cell->parameters["\\MEMID"].decode_string().c_str(), i); @@ -141,7 +141,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) w_out->start_offset = mem_offset; module->wires[w_out->name] = w_out; data_reg_out.push_back(RTLIL::SigSpec(w_out)); - c->connections_["\\Q"] = data_reg_out.back(); + c->set("\\Q", data_reg_out.back()); } } @@ -151,10 +151,10 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) for (int i = 0; i < cell->parameters["\\RD_PORTS"].as_int(); i++) { - RTLIL::SigSpec rd_addr = cell->connections_["\\RD_ADDR"].extract(i*mem_abits, mem_abits); + RTLIL::SigSpec rd_addr = cell->get("\\RD_ADDR").extract(i*mem_abits, mem_abits); std::vector rd_signals; - rd_signals.push_back(cell->connections_["\\RD_DATA"].extract(i*mem_width, mem_width)); + rd_signals.push_back(cell->get("\\RD_DATA").extract(i*mem_width, mem_width)); if (cell->parameters["\\RD_CLK_ENABLE"].bits[i] == RTLIL::State::S1) { @@ -163,8 +163,8 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdreg", i), "$dff"); c->parameters["\\WIDTH"] = RTLIL::Const(mem_abits); c->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]); - c->connections_["\\CLK"] = cell->connections_["\\RD_CLK"].extract(i, 1); - c->connections_["\\D"] = rd_addr; + c->set("\\CLK", cell->get("\\RD_CLK").extract(i, 1)); + c->set("\\D", rd_addr); count_dff++; RTLIL::Wire *w = new RTLIL::Wire; @@ -172,7 +172,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) w->width = mem_abits; module->wires[w->name] = w; - c->connections_["\\Q"] = RTLIL::SigSpec(w); + c->set("\\Q", RTLIL::SigSpec(w)); rd_addr = RTLIL::SigSpec(w); } else @@ -180,8 +180,8 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdreg", i), "$dff"); c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"]; c->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]); - c->connections_["\\CLK"] = cell->connections_["\\RD_CLK"].extract(i, 1); - c->connections_["\\Q"] = rd_signals.back(); + c->set("\\CLK", cell->get("\\RD_CLK").extract(i, 1)); + c->set("\\Q", rd_signals.back()); count_dff++; RTLIL::Wire *w = new RTLIL::Wire; @@ -191,7 +191,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) rd_signals.clear(); rd_signals.push_back(RTLIL::SigSpec(w)); - c->connections_["\\D"] = rd_signals.back(); + c->set("\\D", rd_signals.back()); } } @@ -203,31 +203,31 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) { RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdmux", i, "", j, "", k), "$mux"); c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"]; - c->connections_["\\Y"] = rd_signals[k]; - c->connections_["\\S"] = rd_addr.extract(mem_abits-j-1, 1); + c->set("\\Y", rd_signals[k]); + c->set("\\S", rd_addr.extract(mem_abits-j-1, 1)); count_mux++; RTLIL::Wire *w = new RTLIL::Wire; w->name = genid(cell->name, "$rdmux", i, "", j, "", k, "$a"); w->width = mem_width; module->wires[w->name] = w; - c->connections_["\\A"] = RTLIL::SigSpec(w); + c->set("\\A", RTLIL::SigSpec(w)); w = new RTLIL::Wire; w->name = genid(cell->name, "$rdmux", i, "", j, "", k, "$b"); w->width = mem_width; module->wires[w->name] = w; - c->connections_["\\B"] = RTLIL::SigSpec(w); + c->set("\\B", RTLIL::SigSpec(w)); - next_rd_signals.push_back(c->connections_["\\A"]); - next_rd_signals.push_back(c->connections_["\\B"]); + next_rd_signals.push_back(c->get("\\A")); + next_rd_signals.push_back(c->get("\\B")); } next_rd_signals.swap(rd_signals); } for (int j = 0; j < mem_size; j++) - module->connections_.push_back(RTLIL::SigSig(rd_signals[j], data_reg_out[j])); + module->connect(RTLIL::SigSig(rd_signals[j], data_reg_out[j])); } log(" read interface: %d $dff and %d $mux cells.\n", count_dff, count_mux); @@ -241,9 +241,9 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) for (int j = 0; j < cell->parameters["\\WR_PORTS"].as_int(); j++) { - RTLIL::SigSpec wr_addr = cell->connections_["\\WR_ADDR"].extract(j*mem_abits, mem_abits); - RTLIL::SigSpec wr_data = cell->connections_["\\WR_DATA"].extract(j*mem_width, mem_width); - RTLIL::SigSpec wr_en = cell->connections_["\\WR_EN"].extract(j*mem_width, mem_width); + RTLIL::SigSpec wr_addr = cell->get("\\WR_ADDR").extract(j*mem_abits, mem_abits); + RTLIL::SigSpec wr_data = cell->get("\\WR_DATA").extract(j*mem_width, mem_width); + RTLIL::SigSpec wr_en = cell->get("\\WR_EN").extract(j*mem_width, mem_width); RTLIL::Cell *c = module->addCell(genid(cell->name, "$wreq", i, "", j), "$eq"); c->parameters["\\A_SIGNED"] = RTLIL::Const(0); @@ -251,14 +251,14 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) c->parameters["\\A_WIDTH"] = cell->parameters["\\ABITS"]; c->parameters["\\B_WIDTH"] = cell->parameters["\\ABITS"]; c->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - c->connections_["\\A"] = RTLIL::SigSpec(i, mem_abits); - c->connections_["\\B"] = wr_addr; + c->set("\\A", RTLIL::SigSpec(i, mem_abits)); + c->set("\\B", wr_addr); count_wrmux++; RTLIL::Wire *w_seladdr = new RTLIL::Wire; w_seladdr->name = genid(cell->name, "$wreq", i, "", j, "$y"); module->wires[w_seladdr->name] = w_seladdr; - c->connections_["\\Y"] = w_seladdr; + c->set("\\Y", w_seladdr); int wr_offset = 0; while (wr_offset < wr_en.size()) @@ -283,33 +283,33 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) c->parameters["\\A_WIDTH"] = RTLIL::Const(1); c->parameters["\\B_WIDTH"] = RTLIL::Const(1); c->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - c->connections_["\\A"] = w; - c->connections_["\\B"] = wr_bit; + c->set("\\A", w); + c->set("\\B", wr_bit); w = new RTLIL::Wire; w->name = genid(cell->name, "$wren", i, "", j, "", wr_offset, "$y"); module->wires[w->name] = w; - c->connections_["\\Y"] = RTLIL::SigSpec(w); + c->set("\\Y", RTLIL::SigSpec(w)); } c = module->addCell(genid(cell->name, "$wrmux", i, "", j, "", wr_offset), "$mux"); c->parameters["\\WIDTH"] = wr_width; - c->connections_["\\A"] = sig.extract(wr_offset, wr_width); - c->connections_["\\B"] = wr_data.extract(wr_offset, wr_width); - c->connections_["\\S"] = RTLIL::SigSpec(w); + c->set("\\A", sig.extract(wr_offset, wr_width)); + c->set("\\B", wr_data.extract(wr_offset, wr_width)); + c->set("\\S", RTLIL::SigSpec(w)); w = new RTLIL::Wire; w->name = genid(cell->name, "$wrmux", i, "", j, "", wr_offset, "$y"); w->width = wr_width; module->wires[w->name] = w; - c->connections_["\\Y"] = w; + c->set("\\Y", w); sig.replace(wr_offset, w); wr_offset += wr_width; } } - module->connections_.push_back(RTLIL::SigSig(data_reg_in[i], sig)); + module->connect(RTLIL::SigSig(data_reg_in[i], sig)); } log(" write interface: %d blocks of $eq, $and and $mux cells.\n", count_wrmux); diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index 919e24a4a..8b4eb0d0e 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -64,16 +64,16 @@ struct MemoryShareWorker RTLIL::Cell *cell = sig_to_mux.at(sig).first; int bit_idx = sig_to_mux.at(sig).second; - std::vector sig_a = sigmap(cell->connections_.at("\\A")); - std::vector sig_b = sigmap(cell->connections_.at("\\B")); - std::vector sig_s = sigmap(cell->connections_.at("\\S")); - std::vector sig_y = sigmap(cell->connections_.at("\\Y")); + std::vector sig_a = sigmap(cell->get("\\A")); + std::vector sig_b = sigmap(cell->get("\\B")); + std::vector sig_s = sigmap(cell->get("\\S")); + std::vector sig_y = sigmap(cell->get("\\Y")); log_assert(sig_y.at(bit_idx) == sig); for (int i = 0; i < int(sig_s.size()); i++) if (state.count(sig_s[i]) && state.at(sig_s[i]) == true) { if (find_data_feedback(async_rd_bits, sig_b.at(bit_idx + i*sig_y.size()), state, conditions)) - cell->connections_.at("\\B").replace(bit_idx + i*sig_y.size(), RTLIL::State::Sx); + cell->get("\\B").replace(bit_idx + i*sig_y.size(), RTLIL::State::Sx); return false; } @@ -87,7 +87,7 @@ struct MemoryShareWorker new_state[sig_s[i]] = true; if (find_data_feedback(async_rd_bits, sig_b.at(bit_idx + i*sig_y.size()), new_state, conditions)) - cell->connections_.at("\\B").replace(bit_idx + i*sig_y.size(), RTLIL::State::Sx); + cell->get("\\B").replace(bit_idx + i*sig_y.size(), RTLIL::State::Sx); } std::map new_state = state; @@ -95,7 +95,7 @@ struct MemoryShareWorker new_state[sig_s[i]] = false; if (find_data_feedback(async_rd_bits, sig_a.at(bit_idx), new_state, conditions)) - cell->connections_.at("\\A").replace(bit_idx, RTLIL::State::Sx); + cell->get("\\A").replace(bit_idx, RTLIL::State::Sx); return false; } @@ -141,10 +141,10 @@ struct MemoryShareWorker if (cell->type == "$mux" || cell->type == "$pmux") { - std::vector sig_a = sigmap(cell->connections_.at("\\A")); - std::vector sig_b = sigmap(cell->connections_.at("\\B")); - std::vector sig_s = sigmap(cell->connections_.at("\\S")); - std::vector sig_y = sigmap(cell->connections_.at("\\Y")); + std::vector sig_a = sigmap(cell->get("\\A")); + std::vector sig_b = sigmap(cell->get("\\B")); + std::vector sig_s = sigmap(cell->get("\\S")); + std::vector sig_y = sigmap(cell->get("\\Y")); non_feedback_nets.insert(sig_s.begin(), sig_s.end()); @@ -161,7 +161,7 @@ struct MemoryShareWorker cell->parameters.at("\\MEMID").decode_string() == memid) ignore_data_port = true; - for (auto conn : cell_it.second->connections_) + for (auto conn : cell_it.second->connections()) { if (ignore_data_port && conn.first == "\\DATA") continue; @@ -191,8 +191,8 @@ struct MemoryShareWorker if (cell->parameters.at("\\CLK_ENABLE").as_bool()) continue; - RTLIL::SigSpec sig_addr = sigmap(cell->connections_.at("\\ADDR")); - std::vector sig_data = sigmap(cell->connections_.at("\\DATA")); + RTLIL::SigSpec sig_addr = sigmap(cell->get("\\ADDR")); + std::vector sig_data = sigmap(cell->get("\\DATA")); for (int i = 0; i < int(sig_data.size()); i++) if (non_feedback_nets.count(sig_data[i])) @@ -212,14 +212,14 @@ struct MemoryShareWorker for (auto cell : wr_ports) { - RTLIL::SigSpec sig_addr = sigmap_xmux(cell->connections_.at("\\ADDR")); + RTLIL::SigSpec sig_addr = sigmap_xmux(cell->get("\\ADDR")); if (!async_rd_bits.count(sig_addr)) continue; log(" Analyzing write port %s.\n", log_id(cell)); - std::vector cell_data = cell->connections_.at("\\DATA"); - std::vector cell_en = cell->connections_.at("\\EN"); + std::vector cell_data = cell->get("\\DATA"); + std::vector cell_en = cell->get("\\EN"); int created_conditions = 0; for (int i = 0; i < int(cell_data.size()); i++) @@ -239,7 +239,7 @@ struct MemoryShareWorker if (created_conditions) { log(" Added enable logic for %d different cases.\n", created_conditions); - cell->connections_.at("\\EN") = cell_en; + cell->get("\\EN") = cell_en; } } } @@ -357,15 +357,15 @@ struct MemoryShareWorker for (int i = 0; i < int(wr_ports.size()); i++) { RTLIL::Cell *cell = wr_ports.at(i); - RTLIL::SigSpec addr = sigmap_xmux(cell->connections_.at("\\ADDR")); + RTLIL::SigSpec addr = sigmap_xmux(cell->get("\\ADDR")); if (cell->parameters.at("\\CLK_ENABLE").as_bool() != cache_clk_enable || - (cache_clk_enable && (sigmap(cell->connections_.at("\\CLK")) != cache_clk || + (cache_clk_enable && (sigmap(cell->get("\\CLK")) != cache_clk || cell->parameters.at("\\CLK_POLARITY").as_bool() != cache_clk_polarity))) { cache_clk_enable = cell->parameters.at("\\CLK_ENABLE").as_bool(); cache_clk_polarity = cell->parameters.at("\\CLK_POLARITY").as_bool(); - cache_clk = sigmap(cell->connections_.at("\\CLK")); + cache_clk = sigmap(cell->get("\\CLK")); last_port_by_addr.clear(); if (cache_clk_enable) @@ -377,7 +377,7 @@ struct MemoryShareWorker log(" Port %d (%s) has addr %s.\n", i, log_id(cell), log_signal(addr)); log(" Active bits: "); - std::vector en_bits = sigmap(cell->connections_.at("\\EN")); + std::vector en_bits = sigmap(cell->get("\\EN")); active_bits_on_port.push_back(std::vector(en_bits.size())); for (int k = int(en_bits.size())-1; k >= 0; k--) { active_bits_on_port[i][k] = en_bits[k].wire != NULL || en_bits[k].data != RTLIL::State::S0; @@ -399,13 +399,13 @@ struct MemoryShareWorker // Force this ports addr input to addr directly (skip don't care muxes) - cell->connections_.at("\\ADDR") = addr; + cell->get("\\ADDR") = addr; // If any of the ports between `last_i' and `i' write to the same address, this // will have priority over whatever `last_i` wrote. So we need to revisit those // ports and mask the EN bits accordingly. - RTLIL::SigSpec merged_en = sigmap(wr_ports[last_i]->connections_.at("\\EN")); + RTLIL::SigSpec merged_en = sigmap(wr_ports[last_i]->get("\\EN")); for (int j = last_i+1; j < i; j++) { @@ -420,20 +420,20 @@ struct MemoryShareWorker found_overlapping_bits_i_j: log(" Creating collosion-detect logic for port %d.\n", j); RTLIL::SigSpec is_same_addr = module->addWire(NEW_ID); - module->addEq(NEW_ID, addr, wr_ports[j]->connections_.at("\\ADDR"), is_same_addr); - merged_en = mask_en_grouped(is_same_addr, merged_en, sigmap(wr_ports[j]->connections_.at("\\EN"))); + module->addEq(NEW_ID, addr, wr_ports[j]->get("\\ADDR"), is_same_addr); + merged_en = mask_en_grouped(is_same_addr, merged_en, sigmap(wr_ports[j]->get("\\EN"))); } } // Then we need to merge the (masked) EN and the DATA signals. - RTLIL::SigSpec merged_data = wr_ports[last_i]->connections_.at("\\DATA"); + RTLIL::SigSpec merged_data = wr_ports[last_i]->get("\\DATA"); if (found_overlapping_bits) { log(" Creating logic for merging DATA and EN ports.\n"); - merge_en_data(merged_en, merged_data, sigmap(cell->connections_.at("\\EN")), sigmap(cell->connections_.at("\\DATA"))); + merge_en_data(merged_en, merged_data, sigmap(cell->get("\\EN")), sigmap(cell->get("\\DATA"))); } else { - RTLIL::SigSpec cell_en = sigmap(cell->connections_.at("\\EN")); - RTLIL::SigSpec cell_data = sigmap(cell->connections_.at("\\DATA")); + RTLIL::SigSpec cell_en = sigmap(cell->get("\\EN")); + RTLIL::SigSpec cell_data = sigmap(cell->get("\\DATA")); for (int k = 0; k < int(en_bits.size()); k++) if (!active_bits_on_port[last_i][k]) { merged_en.replace(k, cell_en.extract(k, 1)); @@ -443,14 +443,14 @@ struct MemoryShareWorker // Connect the new EN and DATA signals and remove the old write port. - cell->connections_.at("\\EN") = merged_en; - cell->connections_.at("\\DATA") = merged_data; + cell->get("\\EN") = merged_en; + cell->get("\\DATA") = merged_data; module->remove(wr_ports[last_i]); wr_ports[last_i] = NULL; log(" Active bits: "); - std::vector en_bits = sigmap(cell->connections_.at("\\EN")); + std::vector en_bits = sigmap(cell->get("\\EN")); active_bits_on_port.push_back(std::vector(en_bits.size())); for (int k = int(en_bits.size())-1; k >= 0; k--) log("%c", active_bits_on_port[i][k] ? '1' : '0'); @@ -489,7 +489,7 @@ struct MemoryShareWorker std::set considered_port_pairs; for (int i = 0; i < int(wr_ports.size()); i++) { - std::vector bits = modwalker.sigmap(wr_ports[i]->connections_.at("\\EN")); + std::vector bits = modwalker.sigmap(wr_ports[i]->get("\\EN")); for (auto bit : bits) if (bit == RTLIL::State::S1) goto port_is_always_active; @@ -509,12 +509,12 @@ struct MemoryShareWorker RTLIL::Cell *cell = wr_ports.at(i); if (cell->parameters.at("\\CLK_ENABLE").as_bool() != cache_clk_enable || - (cache_clk_enable && (sigmap(cell->connections_.at("\\CLK")) != cache_clk || + (cache_clk_enable && (sigmap(cell->get("\\CLK")) != cache_clk || cell->parameters.at("\\CLK_POLARITY").as_bool() != cache_clk_polarity))) { cache_clk_enable = cell->parameters.at("\\CLK_ENABLE").as_bool(); cache_clk_polarity = cell->parameters.at("\\CLK_POLARITY").as_bool(); - cache_clk = sigmap(cell->connections_.at("\\CLK")); + cache_clk = sigmap(cell->get("\\CLK")); } else if (i > 0 && considered_ports.count(i-1) && considered_ports.count(i)) considered_port_pairs.insert(i); @@ -542,7 +542,7 @@ struct MemoryShareWorker for (int i = 0; i < int(wr_ports.size()); i++) if (considered_port_pairs.count(i) || considered_port_pairs.count(i+1)) { - RTLIL::SigSpec sig = modwalker.sigmap(wr_ports[i]->connections_.at("\\EN")); + RTLIL::SigSpec sig = modwalker.sigmap(wr_ports[i]->get("\\EN")); port_to_sat_variable[i] = ez.expression(ez.OpOr, satgen.importSigSpec(sig)); std::vector bits = sig; @@ -585,18 +585,18 @@ struct MemoryShareWorker log(" Merging port %d into port %d.\n", i-1, i); port_to_sat_variable.at(i) = ez.OR(port_to_sat_variable.at(i-1), port_to_sat_variable.at(i)); - RTLIL::SigSpec last_addr = wr_ports[i-1]->connections_.at("\\ADDR"); - RTLIL::SigSpec last_data = wr_ports[i-1]->connections_.at("\\DATA"); - std::vector last_en = modwalker.sigmap(wr_ports[i-1]->connections_.at("\\EN")); + RTLIL::SigSpec last_addr = wr_ports[i-1]->get("\\ADDR"); + RTLIL::SigSpec last_data = wr_ports[i-1]->get("\\DATA"); + std::vector last_en = modwalker.sigmap(wr_ports[i-1]->get("\\EN")); - RTLIL::SigSpec this_addr = wr_ports[i]->connections_.at("\\ADDR"); - RTLIL::SigSpec this_data = wr_ports[i]->connections_.at("\\DATA"); - std::vector this_en = modwalker.sigmap(wr_ports[i]->connections_.at("\\EN")); + RTLIL::SigSpec this_addr = wr_ports[i]->get("\\ADDR"); + RTLIL::SigSpec this_data = wr_ports[i]->get("\\DATA"); + std::vector this_en = modwalker.sigmap(wr_ports[i]->get("\\EN")); RTLIL::SigBit this_en_active = module->ReduceOr(NEW_ID, this_en); - wr_ports[i]->connections_.at("\\ADDR") = module->Mux(NEW_ID, last_addr, this_addr, this_en_active); - wr_ports[i]->connections_.at("\\DATA") = module->Mux(NEW_ID, last_data, this_data, this_en_active); + wr_ports[i]->get("\\ADDR") = module->Mux(NEW_ID, last_addr, this_addr, this_en_active); + wr_ports[i]->get("\\DATA") = module->Mux(NEW_ID, last_data, this_data, this_en_active); std::map, int> groups_en; RTLIL::SigSpec grouped_last_en, grouped_this_en, en; @@ -614,7 +614,7 @@ struct MemoryShareWorker } module->addMux(NEW_ID, grouped_last_en, grouped_this_en, this_en_active, grouped_en); - wr_ports[i]->connections_.at("\\EN") = en; + wr_ports[i]->get("\\EN") = en; module->remove(wr_ports[i-1]); wr_ports[i-1] = NULL; @@ -653,18 +653,18 @@ struct MemoryShareWorker if (cell->type == "$mux") { - RTLIL::SigSpec sig_a = sigmap_xmux(cell->connections_.at("\\A")); - RTLIL::SigSpec sig_b = sigmap_xmux(cell->connections_.at("\\B")); + RTLIL::SigSpec sig_a = sigmap_xmux(cell->get("\\A")); + RTLIL::SigSpec sig_b = sigmap_xmux(cell->get("\\B")); if (sig_a.is_fully_undef()) - sigmap_xmux.add(cell->connections_.at("\\Y"), sig_b); + sigmap_xmux.add(cell->get("\\Y"), sig_b); else if (sig_b.is_fully_undef()) - sigmap_xmux.add(cell->connections_.at("\\Y"), sig_a); + sigmap_xmux.add(cell->get("\\Y"), sig_a); } if (cell->type == "$mux" || cell->type == "$pmux") { - std::vector sig_y = sigmap(cell->connections_.at("\\Y")); + std::vector sig_y = sigmap(cell->get("\\Y")); for (int i = 0; i < int(sig_y.size()); i++) sig_to_mux[sig_y[i]] = std::pair(cell, i); } diff --git a/passes/memory/memory_unpack.cc b/passes/memory/memory_unpack.cc index 9c457ad5d..f08350768 100644 --- a/passes/memory/memory_unpack.cc +++ b/passes/memory/memory_unpack.cc @@ -54,9 +54,9 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory) cell->parameters["\\CLK_ENABLE"] = RTLIL::SigSpec(memory->parameters.at("\\RD_CLK_ENABLE")).extract(i, 1).as_const(); cell->parameters["\\CLK_POLARITY"] = RTLIL::SigSpec(memory->parameters.at("\\RD_CLK_POLARITY")).extract(i, 1).as_const(); cell->parameters["\\TRANSPARENT"] = RTLIL::SigSpec(memory->parameters.at("\\RD_TRANSPARENT")).extract(i, 1).as_const(); - cell->connections_["\\CLK"] = memory->connections_.at("\\RD_CLK").extract(i, 1); - cell->connections_["\\ADDR"] = memory->connections_.at("\\RD_ADDR").extract(i*abits, abits); - cell->connections_["\\DATA"] = memory->connections_.at("\\RD_DATA").extract(i*mem->width, mem->width); + cell->set("\\CLK", memory->get("\\RD_CLK").extract(i, 1)); + cell->set("\\ADDR", memory->get("\\RD_ADDR").extract(i*abits, abits)); + cell->set("\\DATA", memory->get("\\RD_DATA").extract(i*mem->width, mem->width)); } for (int i = 0; i < num_wr_ports; i++) @@ -68,10 +68,10 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory) cell->parameters["\\CLK_ENABLE"] = RTLIL::SigSpec(memory->parameters.at("\\WR_CLK_ENABLE")).extract(i, 1).as_const(); cell->parameters["\\CLK_POLARITY"] = RTLIL::SigSpec(memory->parameters.at("\\WR_CLK_POLARITY")).extract(i, 1).as_const(); cell->parameters["\\PRIORITY"] = i; - cell->connections_["\\CLK"] = memory->connections_.at("\\WR_CLK").extract(i, 1); - cell->connections_["\\EN"] = memory->connections_.at("\\WR_EN").extract(i*mem->width, mem->width); - cell->connections_["\\ADDR"] = memory->connections_.at("\\WR_ADDR").extract(i*abits, abits); - cell->connections_["\\DATA"] = memory->connections_.at("\\WR_DATA").extract(i*mem->width, mem->width); + cell->set("\\CLK", memory->get("\\WR_CLK").extract(i, 1)); + cell->set("\\EN", memory->get("\\WR_EN").extract(i*mem->width, mem->width)); + cell->set("\\ADDR", memory->get("\\WR_ADDR").extract(i*abits, abits)); + cell->set("\\DATA", memory->get("\\WR_DATA").extract(i*mem->width, mem->width)); } module->remove(memory); diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 30ab88146..fa5d8f189 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -40,7 +40,7 @@ static void rmunused_module_cells(RTLIL::Module *module, bool verbose) SigSet wire2driver; for (auto &it : module->cells) { RTLIL::Cell *cell = it.second; - for (auto &it2 : cell->connections_) { + for (auto &it2 : cell->connections()) { if (!ct.cell_input(cell->type, it2.first)) { RTLIL::SigSpec sig = it2.second; assign_map.apply(sig); @@ -70,7 +70,7 @@ static void rmunused_module_cells(RTLIL::Module *module, bool verbose) for (auto cell : queue) unused.erase(cell); for (auto cell : queue) { - for (auto &it : cell->connections_) { + for (auto &it : cell->connections()) { if (!ct.cell_output(cell->type, it.first)) { std::set cell_list; RTLIL::SigSpec sig = it.second; @@ -158,10 +158,10 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool for (auto &it : module->cells) { RTLIL::Cell *cell = it.second; if (ct_reg.cell_known(cell->type)) - for (auto &it2 : cell->connections_) + for (auto &it2 : cell->connections()) if (ct_reg.cell_output(cell->type, it2.first)) register_signals.add(it2.second); - for (auto &it2 : cell->connections_) + for (auto &it2 : cell->connections()) connected_signals.add(it2.second); } @@ -171,7 +171,7 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool for (auto &it : module->cells) { RTLIL::Cell *cell = it.second; if (ct_all.cell_known(cell->type)) - for (auto &it2 : cell->connections_) + for (auto &it2 : cell->connections()) if (ct_all.cell_output(cell->type, it2.first)) direct_sigs.insert(assign_map(it2.second)); } @@ -189,13 +189,13 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool } } - module->connections_.clear(); + module->connections().clear(); SigPool used_signals; SigPool used_signals_nodrivers; for (auto &it : module->cells) { RTLIL::Cell *cell = it.second; - for (auto &it2 : cell->connections_) { + for (auto &it2 : cell->connections()) { assign_map.apply(it2.second); used_signals.add(it2.second); if (!ct.cell_output(cell->type, it2.first)) @@ -237,7 +237,7 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool if (new_conn.first.size() > 0) { used_signals.add(new_conn.first); used_signals.add(new_conn.second); - module->connections_.push_back(new_conn); + module->connect(new_conn); } } } else { diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index 2a5ec8bea..7f420ec34 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -38,7 +38,7 @@ static void replace_undriven(RTLIL::Design *design, RTLIL::Module *module) SigPool all_signals; for (auto &it : module->cells) - for (auto &conn : it.second->connections_) { + for (auto &conn : it.second->connections()) { if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first)) driven_signals.add(sigmap(conn.second)); if (!ct.cell_known(it.second->type) || ct.cell_input(it.second->type, conn.first)) @@ -66,21 +66,21 @@ static void replace_undriven(RTLIL::Design *design, RTLIL::Module *module) continue; log("Setting undriven signal in %s to undef: %s\n", RTLIL::id2cstr(module->name), log_signal(c)); - module->connections_.push_back(RTLIL::SigSig(c, RTLIL::SigSpec(RTLIL::State::Sx, c.width))); + module->connect(RTLIL::SigSig(c, RTLIL::SigSpec(RTLIL::State::Sx, c.width))); OPT_DID_SOMETHING = true; } } static void replace_cell(RTLIL::Module *module, RTLIL::Cell *cell, std::string info, std::string out_port, RTLIL::SigSpec out_val) { - RTLIL::SigSpec Y = cell->connections_[out_port]; + RTLIL::SigSpec Y = cell->connections()[out_port]; out_val.extend_u0(Y.size(), false); log("Replacing %s cell `%s' (%s) in module `%s' with constant driver `%s = %s'.\n", cell->type.c_str(), cell->name.c_str(), info.c_str(), module->name.c_str(), log_signal(Y), log_signal(out_val)); // ILANG_BACKEND::dump_cell(stderr, "--> ", cell); - module->connections_.push_back(RTLIL::SigSig(Y, out_val)); + module->connect(RTLIL::SigSig(Y, out_val)); module->remove(cell); OPT_DID_SOMETHING = true; did_something = true; @@ -88,14 +88,14 @@ static void replace_cell(RTLIL::Module *module, RTLIL::Cell *cell, std::string i static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutative, bool extend_u0, SigMap &sigmap) { - std::string b_name = cell->connections_.count("\\B") ? "\\B" : "\\A"; + std::string b_name = cell->connections().count("\\B") ? "\\B" : "\\A"; bool a_signed = cell->parameters.at("\\A_SIGNED").as_bool(); bool b_signed = cell->parameters.at(b_name + "_SIGNED").as_bool(); - RTLIL::SigSpec sig_a = sigmap(cell->connections_.at("\\A")); - RTLIL::SigSpec sig_b = sigmap(cell->connections_.at(b_name)); - RTLIL::SigSpec sig_y = sigmap(cell->connections_.at("\\Y")); + RTLIL::SigSpec sig_a = sigmap(cell->get("\\A")); + RTLIL::SigSpec sig_b = sigmap(cell->connections().at(b_name)); + RTLIL::SigSpec sig_y = sigmap(cell->get("\\Y")); if (extend_u0) { sig_a.extend_u0(sig_y.size(), a_signed); @@ -160,21 +160,21 @@ static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool com RTLIL::Cell *c = module->addCell(NEW_ID, cell->type); - c->connections_["\\A"] = new_a; + c->set("\\A", new_a); c->parameters["\\A_WIDTH"] = new_a.size(); c->parameters["\\A_SIGNED"] = false; if (b_name == "\\B") { - c->connections_["\\B"] = new_b; + c->set("\\B", new_b); c->parameters["\\B_WIDTH"] = new_b.size(); c->parameters["\\B_SIGNED"] = false; } - c->connections_["\\Y"] = new_y; + c->set("\\Y", new_y); c->parameters["\\Y_WIDTH"] = new_y->width; c->check(); - module->connections_.push_back(new_conn); + module->connect(new_conn); log(" New cell `%s': A=%s", log_id(c), log_signal(new_a)); if (b_name == "\\B") @@ -203,8 +203,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo for (auto &cell_it : module->cells) if (design->selected(module, cell_it.second)) { if ((cell_it.second->type == "$_INV_" || cell_it.second->type == "$not" || cell_it.second->type == "$logic_not") && - cell_it.second->connections_["\\A"].size() == 1 && cell_it.second->connections_["\\Y"].size() == 1) - invert_map[assign_map(cell_it.second->connections_["\\Y"])] = assign_map(cell_it.second->connections_["\\A"]); + cell_it.second->get("\\A").size() == 1 && cell_it.second->get("\\Y").size() == 1) + invert_map[assign_map(cell_it.second->get("\\Y"))] = assign_map(cell_it.second->get("\\A")); cells.push_back(cell_it.second); } @@ -222,7 +222,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (cell->type == "$reduce_and") { - RTLIL::SigSpec sig_a = assign_map(cell->connections_.at("\\A")); + RTLIL::SigSpec sig_a = assign_map(cell->get("\\A")); RTLIL::State new_a = RTLIL::State::S1; for (auto &bit : sig_a.to_sigbit_vector()) @@ -240,7 +240,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cover("opt.opt_const.fine.$reduce_and"); log("Replacing port A of %s cell `%s' in module `%s' with constant driver: %s -> %s\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a)); - cell->connections_.at("\\A") = sig_a = new_a; + cell->get("\\A") = sig_a = new_a; cell->parameters.at("\\A_WIDTH") = 1; OPT_DID_SOMETHING = true; did_something = true; @@ -249,7 +249,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (cell->type == "$logic_not" || cell->type == "$logic_and" || cell->type == "$logic_or" || cell->type == "$reduce_or" || cell->type == "$reduce_bool") { - RTLIL::SigSpec sig_a = assign_map(cell->connections_.at("\\A")); + RTLIL::SigSpec sig_a = assign_map(cell->get("\\A")); RTLIL::State new_a = RTLIL::State::S0; for (auto &bit : sig_a.to_sigbit_vector()) @@ -267,7 +267,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cover_list("opt.opt_const.fine.A", "$logic_not", "$logic_and", "$logic_or", "$reduce_or", "$reduce_bool", cell->type); log("Replacing port A of %s cell `%s' in module `%s' with constant driver: %s -> %s\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a)); - cell->connections_.at("\\A") = sig_a = new_a; + cell->get("\\A") = sig_a = new_a; cell->parameters.at("\\A_WIDTH") = 1; OPT_DID_SOMETHING = true; did_something = true; @@ -276,7 +276,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (cell->type == "$logic_and" || cell->type == "$logic_or") { - RTLIL::SigSpec sig_b = assign_map(cell->connections_.at("\\B")); + RTLIL::SigSpec sig_b = assign_map(cell->get("\\B")); RTLIL::State new_b = RTLIL::State::S0; for (auto &bit : sig_b.to_sigbit_vector()) @@ -294,7 +294,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cover_list("opt.opt_const.fine.B", "$logic_and", "$logic_or", cell->type); log("Replacing port B of %s cell `%s' in module `%s' with constant driver: %s -> %s\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_b), log_signal(new_b)); - cell->connections_.at("\\B") = sig_b = new_b; + cell->get("\\B") = sig_b = new_b; cell->parameters.at("\\B_WIDTH") = 1; OPT_DID_SOMETHING = true; did_something = true; @@ -302,13 +302,13 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo } } - if (cell->type == "$logic_or" && (assign_map(cell->connections_.at("\\A")) == RTLIL::State::S1 || assign_map(cell->connections_.at("\\B")) == RTLIL::State::S1)) { + if (cell->type == "$logic_or" && (assign_map(cell->get("\\A")) == RTLIL::State::S1 || assign_map(cell->get("\\B")) == RTLIL::State::S1)) { cover("opt.opt_const.one_high"); replace_cell(module, cell, "one high", "\\Y", RTLIL::State::S1); goto next_cell; } - if (cell->type == "$logic_and" && (assign_map(cell->connections_.at("\\A")) == RTLIL::State::S0 || assign_map(cell->connections_.at("\\B")) == RTLIL::State::S0)) { + if (cell->type == "$logic_and" && (assign_map(cell->get("\\A")) == RTLIL::State::S0 || assign_map(cell->get("\\B")) == RTLIL::State::S0)) { cover("opt.opt_const.one_low"); replace_cell(module, cell, "one low", "\\Y", RTLIL::State::S0); goto next_cell; @@ -320,8 +320,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cell->type == "$neg" || cell->type == "$add" || cell->type == "$sub" || cell->type == "$mul" || cell->type == "$div" || cell->type == "$mod" || cell->type == "$pow") { - RTLIL::SigSpec sig_a = assign_map(cell->connections_.at("\\A")); - RTLIL::SigSpec sig_b = cell->connections_.count("\\B") ? assign_map(cell->connections_.at("\\B")) : RTLIL::SigSpec(); + RTLIL::SigSpec sig_a = assign_map(cell->get("\\A")); + RTLIL::SigSpec sig_b = cell->connections().count("\\B") ? assign_map(cell->get("\\B")) : RTLIL::SigSpec(); if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr") sig_a = RTLIL::SigSpec(); @@ -342,31 +342,31 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cell->type == "$lt" || cell->type == "$le" || cell->type == "$ge" || cell->type == "$gt") replace_cell(module, cell, "x-bit in input", "\\Y", RTLIL::State::Sx); else - replace_cell(module, cell, "x-bit in input", "\\Y", RTLIL::SigSpec(RTLIL::State::Sx, cell->connections_.at("\\Y").size())); + replace_cell(module, cell, "x-bit in input", "\\Y", RTLIL::SigSpec(RTLIL::State::Sx, cell->get("\\Y").size())); goto next_cell; } } - if ((cell->type == "$_INV_" || cell->type == "$not" || cell->type == "$logic_not") && cell->connections_["\\Y"].size() == 1 && - invert_map.count(assign_map(cell->connections_["\\A"])) != 0) { + if ((cell->type == "$_INV_" || cell->type == "$not" || cell->type == "$logic_not") && cell->get("\\Y").size() == 1 && + invert_map.count(assign_map(cell->get("\\A"))) != 0) { cover_list("opt.opt_const.invert.double", "$_INV_", "$not", "$logic_not", cell->type); - replace_cell(module, cell, "double_invert", "\\Y", invert_map.at(assign_map(cell->connections_["\\A"]))); + replace_cell(module, cell, "double_invert", "\\Y", invert_map.at(assign_map(cell->get("\\A")))); goto next_cell; } - if ((cell->type == "$_MUX_" || cell->type == "$mux") && invert_map.count(assign_map(cell->connections_["\\S"])) != 0) { + if ((cell->type == "$_MUX_" || cell->type == "$mux") && invert_map.count(assign_map(cell->get("\\S"))) != 0) { cover_list("opt.opt_const.invert.muxsel", "$_MUX_", "$mux", cell->type); - RTLIL::SigSpec tmp = cell->connections_["\\A"]; - cell->connections_["\\A"] = cell->connections_["\\B"]; - cell->connections_["\\B"] = tmp; - cell->connections_["\\S"] = invert_map.at(assign_map(cell->connections_["\\S"])); + RTLIL::SigSpec tmp = cell->get("\\A"); + cell->set("\\A", cell->get("\\B")); + cell->set("\\B", tmp); + cell->set("\\S", invert_map.at(assign_map(cell->get("\\S")))); OPT_DID_SOMETHING = true; did_something = true; goto next_cell; } if (cell->type == "$_INV_") { - RTLIL::SigSpec input = cell->connections_["\\A"]; + RTLIL::SigSpec input = cell->get("\\A"); assign_map.apply(input); if (input.match("1")) ACTION_DO_Y(0); if (input.match("0")) ACTION_DO_Y(1); @@ -375,8 +375,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (cell->type == "$_AND_") { RTLIL::SigSpec input; - input.append(cell->connections_["\\B"]); - input.append(cell->connections_["\\A"]); + input.append(cell->get("\\B")); + input.append(cell->get("\\A")); assign_map.apply(input); if (input.match(" 0")) ACTION_DO_Y(0); if (input.match("0 ")) ACTION_DO_Y(0); @@ -394,8 +394,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (cell->type == "$_OR_") { RTLIL::SigSpec input; - input.append(cell->connections_["\\B"]); - input.append(cell->connections_["\\A"]); + input.append(cell->get("\\B")); + input.append(cell->get("\\A")); assign_map.apply(input); if (input.match(" 1")) ACTION_DO_Y(1); if (input.match("1 ")) ACTION_DO_Y(1); @@ -413,8 +413,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (cell->type == "$_XOR_") { RTLIL::SigSpec input; - input.append(cell->connections_["\\B"]); - input.append(cell->connections_["\\A"]); + input.append(cell->get("\\B")); + input.append(cell->get("\\A")); assign_map.apply(input); if (input.match("00")) ACTION_DO_Y(0); if (input.match("01")) ACTION_DO_Y(1); @@ -428,9 +428,9 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (cell->type == "$_MUX_") { RTLIL::SigSpec input; - input.append(cell->connections_["\\S"]); - input.append(cell->connections_["\\B"]); - input.append(cell->connections_["\\A"]); + input.append(cell->get("\\S")); + input.append(cell->get("\\B")); + input.append(cell->get("\\A")); assign_map.apply(input); if (input.extract(2, 1) == input.extract(1, 1)) ACTION_DO("\\Y", input.extract(2, 1)); @@ -440,9 +440,9 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (input.match("10 ")) { cover("opt.opt_const.mux_to_inv"); cell->type = "$_INV_"; - cell->connections_["\\A"] = input.extract(0, 1); - cell->connections_.erase("\\B"); - cell->connections_.erase("\\S"); + cell->set("\\A", input.extract(0, 1)); + cell->connections().erase("\\B"); + cell->connections().erase("\\S"); goto next_cell; } if (input.match("11 ")) ACTION_DO_Y(1); @@ -459,8 +459,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (cell->type == "$eq" || cell->type == "$ne" || cell->type == "$eqx" || cell->type == "$nex") { - RTLIL::SigSpec a = cell->connections_["\\A"]; - RTLIL::SigSpec b = cell->connections_["\\B"]; + RTLIL::SigSpec a = cell->get("\\A"); + RTLIL::SigSpec b = cell->get("\\B"); if (cell->parameters["\\A_WIDTH"].as_int() != cell->parameters["\\B_WIDTH"].as_int()) { int width = std::max(cell->parameters["\\A_WIDTH"].as_int(), cell->parameters["\\B_WIDTH"].as_int()); @@ -495,8 +495,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (new_a.size() < a.size() || new_b.size() < b.size()) { cover_list("opt.opt_const.eqneq.resize", "$eq", "$ne", "$eqx", "$nex", cell->type); - cell->connections_["\\A"] = new_a; - cell->connections_["\\B"] = new_b; + cell->set("\\A", new_a); + cell->set("\\B", new_b); cell->parameters["\\A_WIDTH"] = new_a.size(); cell->parameters["\\B_WIDTH"] = new_b.size(); } @@ -505,24 +505,24 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if ((cell->type == "$eq" || cell->type == "$ne") && cell->parameters["\\Y_WIDTH"].as_int() == 1 && cell->parameters["\\A_WIDTH"].as_int() == 1 && cell->parameters["\\B_WIDTH"].as_int() == 1) { - RTLIL::SigSpec a = assign_map(cell->connections_["\\A"]); - RTLIL::SigSpec b = assign_map(cell->connections_["\\B"]); + RTLIL::SigSpec a = assign_map(cell->get("\\A")); + RTLIL::SigSpec b = assign_map(cell->get("\\B")); if (a.is_fully_const()) { cover_list("opt.opt_const.eqneq.swapconst", "$eq", "$ne", cell->type); - std::swap(cell->connections_["\\A"], cell->connections_["\\B"]); + std::swap(cell->get("\\A"), cell->get("\\B")); } if (b.is_fully_const()) { if (b.as_bool() == (cell->type == "$eq")) { RTLIL::SigSpec input = b; - ACTION_DO("\\Y", cell->connections_["\\A"]); + ACTION_DO("\\Y", cell->get("\\A")); } else { cover_list("opt.opt_const.eqneq.isnot", "$eq", "$ne", cell->type); cell->type = "$not"; cell->parameters.erase("\\B_WIDTH"); cell->parameters.erase("\\B_SIGNED"); - cell->connections_.erase("\\B"); + cell->connections().erase("\\B"); } goto next_cell; } @@ -536,8 +536,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (cell->type == "$add" || cell->type == "$sub" || cell->type == "$or" || cell->type == "$xor") { - RTLIL::SigSpec a = assign_map(cell->connections_["\\A"]); - RTLIL::SigSpec b = assign_map(cell->connections_["\\B"]); + RTLIL::SigSpec a = assign_map(cell->get("\\A")); + RTLIL::SigSpec b = assign_map(cell->get("\\B")); if (cell->type != "$sub" && a.is_fully_const() && a.as_bool() == false) identity_wrt_b = true; @@ -548,7 +548,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr") { - RTLIL::SigSpec b = assign_map(cell->connections_["\\B"]); + RTLIL::SigSpec b = assign_map(cell->get("\\B")); if (b.is_fully_const() && b.as_bool() == false) identity_wrt_a = true, identity_bu0 = true; @@ -556,8 +556,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (cell->type == "$mul") { - RTLIL::SigSpec a = assign_map(cell->connections_["\\A"]); - RTLIL::SigSpec b = assign_map(cell->connections_["\\B"]); + RTLIL::SigSpec a = assign_map(cell->get("\\A")); + RTLIL::SigSpec b = assign_map(cell->get("\\B")); if (a.is_fully_const() && a.size() <= 32 && a.as_int() == 1) identity_wrt_b = true; @@ -568,7 +568,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (cell->type == "$div") { - RTLIL::SigSpec b = assign_map(cell->connections_["\\B"]); + RTLIL::SigSpec b = assign_map(cell->get("\\B")); if (b.is_fully_const() && b.size() <= 32 && b.as_int() == 1) identity_wrt_a = true; @@ -585,13 +585,13 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cell->type.c_str(), cell->name.c_str(), module->name.c_str(), identity_wrt_a ? 'A' : 'B'); if (!identity_wrt_a) { - cell->connections_.at("\\A") = cell->connections_.at("\\B"); + cell->get("\\A") = cell->get("\\B"); cell->parameters.at("\\A_WIDTH") = cell->parameters.at("\\B_WIDTH"); cell->parameters.at("\\A_SIGNED") = cell->parameters.at("\\B_SIGNED"); } cell->type = identity_bu0 ? "$bu0" : "$pos"; - cell->connections_.erase("\\B"); + cell->connections().erase("\\B"); cell->parameters.erase("\\B_WIDTH"); cell->parameters.erase("\\B_SIGNED"); cell->check(); @@ -603,18 +603,18 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo } if (mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && - cell->connections_["\\A"] == RTLIL::SigSpec(0, 1) && cell->connections_["\\B"] == RTLIL::SigSpec(1, 1)) { + cell->get("\\A") == RTLIL::SigSpec(0, 1) && cell->get("\\B") == RTLIL::SigSpec(1, 1)) { cover_list("opt.opt_const.mux_bool", "$mux", "$_MUX_", cell->type); - replace_cell(module, cell, "mux_bool", "\\Y", cell->connections_["\\S"]); + replace_cell(module, cell, "mux_bool", "\\Y", cell->get("\\S")); goto next_cell; } if (mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && - cell->connections_["\\A"] == RTLIL::SigSpec(1, 1) && cell->connections_["\\B"] == RTLIL::SigSpec(0, 1)) { + cell->get("\\A") == RTLIL::SigSpec(1, 1) && cell->get("\\B") == RTLIL::SigSpec(0, 1)) { cover_list("opt.opt_const.mux_invert", "$mux", "$_MUX_", cell->type); - cell->connections_["\\A"] = cell->connections_["\\S"]; - cell->connections_.erase("\\B"); - cell->connections_.erase("\\S"); + cell->set("\\A", cell->get("\\S")); + cell->connections().erase("\\B"); + cell->connections().erase("\\S"); if (cell->type == "$mux") { cell->parameters["\\A_WIDTH"] = cell->parameters["\\WIDTH"]; cell->parameters["\\Y_WIDTH"] = cell->parameters["\\WIDTH"]; @@ -628,10 +628,10 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo goto next_cell; } - if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->connections_["\\A"] == RTLIL::SigSpec(0, 1)) { + if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->get("\\A") == RTLIL::SigSpec(0, 1)) { cover_list("opt.opt_const.mux_and", "$mux", "$_MUX_", cell->type); - cell->connections_["\\A"] = cell->connections_["\\S"]; - cell->connections_.erase("\\S"); + cell->set("\\A", cell->get("\\S")); + cell->connections().erase("\\S"); if (cell->type == "$mux") { cell->parameters["\\A_WIDTH"] = cell->parameters["\\WIDTH"]; cell->parameters["\\B_WIDTH"] = cell->parameters["\\WIDTH"]; @@ -647,10 +647,10 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo goto next_cell; } - if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->connections_["\\B"] == RTLIL::SigSpec(1, 1)) { + if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->get("\\B") == RTLIL::SigSpec(1, 1)) { cover_list("opt.opt_const.mux_or", "$mux", "$_MUX_", cell->type); - cell->connections_["\\B"] = cell->connections_["\\S"]; - cell->connections_.erase("\\S"); + cell->set("\\B", cell->get("\\S")); + cell->connections().erase("\\S"); if (cell->type == "$mux") { cell->parameters["\\A_WIDTH"] = cell->parameters["\\WIDTH"]; cell->parameters["\\B_WIDTH"] = cell->parameters["\\WIDTH"]; @@ -668,22 +668,22 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (mux_undef && (cell->type == "$mux" || cell->type == "$pmux")) { RTLIL::SigSpec new_a, new_b, new_s; - int width = cell->connections_.at("\\A").size(); - if ((cell->connections_.at("\\A").is_fully_undef() && cell->connections_.at("\\B").is_fully_undef()) || - cell->connections_.at("\\S").is_fully_undef()) { + int width = cell->get("\\A").size(); + if ((cell->get("\\A").is_fully_undef() && cell->get("\\B").is_fully_undef()) || + cell->get("\\S").is_fully_undef()) { cover_list("opt.opt_const.mux_undef", "$mux", "$pmux", cell->type); - replace_cell(module, cell, "mux_undef", "\\Y", cell->connections_.at("\\A")); + replace_cell(module, cell, "mux_undef", "\\Y", cell->get("\\A")); goto next_cell; } - for (int i = 0; i < cell->connections_.at("\\S").size(); i++) { - RTLIL::SigSpec old_b = cell->connections_.at("\\B").extract(i*width, width); - RTLIL::SigSpec old_s = cell->connections_.at("\\S").extract(i, 1); + for (int i = 0; i < cell->get("\\S").size(); i++) { + RTLIL::SigSpec old_b = cell->get("\\B").extract(i*width, width); + RTLIL::SigSpec old_s = cell->get("\\S").extract(i, 1); if (old_b.is_fully_undef() || old_s.is_fully_undef()) continue; new_b.append(old_b); new_s.append(old_s); } - new_a = cell->connections_.at("\\A"); + new_a = cell->get("\\A"); if (new_a.is_fully_undef() && new_s.size() > 0) { new_a = new_b.extract((new_s.size()-1)*width, width); new_b = new_b.extract(0, (new_s.size()-1)*width); @@ -699,11 +699,11 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo replace_cell(module, cell, "mux_sel01", "\\Y", new_s); goto next_cell; } - if (cell->connections_.at("\\S").size() != new_s.size()) { + if (cell->get("\\S").size() != new_s.size()) { cover_list("opt.opt_const.mux_reduce", "$mux", "$pmux", cell->type); - cell->connections_.at("\\A") = new_a; - cell->connections_.at("\\B") = new_b; - cell->connections_.at("\\S") = new_s; + cell->get("\\A") = new_a; + cell->get("\\B") = new_b; + cell->get("\\S") = new_s; if (new_s.size() > 1) { cell->type = "$pmux"; cell->parameters["\\S_WIDTH"] = new_s.size(); @@ -718,7 +718,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo #define FOLD_1ARG_CELL(_t) \ if (cell->type == "$" #_t) { \ - RTLIL::SigSpec a = cell->connections_["\\A"]; \ + RTLIL::SigSpec a = cell->get("\\A"); \ assign_map.apply(a); \ if (a.is_fully_const()) { \ RTLIL::Const dummy_arg(RTLIL::State::S0, 1); \ @@ -732,8 +732,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo } #define FOLD_2ARG_CELL(_t) \ if (cell->type == "$" #_t) { \ - RTLIL::SigSpec a = cell->connections_["\\A"]; \ - RTLIL::SigSpec b = cell->connections_["\\B"]; \ + RTLIL::SigSpec a = cell->get("\\A"); \ + RTLIL::SigSpec b = cell->get("\\B"); \ assign_map.apply(a), assign_map.apply(b); \ if (a.is_fully_const() && b.is_fully_const()) { \ RTLIL::SigSpec y(RTLIL::const_ ## _t(a.as_const(), b.as_const(), \ @@ -787,13 +787,13 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo // be very conservative with optimizing $mux cells as we do not want to break mux trees if (cell->type == "$mux") { - RTLIL::SigSpec input = assign_map(cell->connections_["\\S"]); - RTLIL::SigSpec inA = assign_map(cell->connections_["\\A"]); - RTLIL::SigSpec inB = assign_map(cell->connections_["\\B"]); + RTLIL::SigSpec input = assign_map(cell->get("\\S")); + RTLIL::SigSpec inA = assign_map(cell->get("\\A")); + RTLIL::SigSpec inB = assign_map(cell->get("\\B")); if (input.is_fully_const()) - ACTION_DO("\\Y", input.as_bool() ? cell->connections_["\\B"] : cell->connections_["\\A"]); + ACTION_DO("\\Y", input.as_bool() ? cell->get("\\B") : cell->get("\\A")); else if (inA == inB) - ACTION_DO("\\Y", cell->connections_["\\A"]); + ACTION_DO("\\Y", cell->get("\\A")); } if (!keepdc && cell->type == "$mul") @@ -802,9 +802,9 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo bool b_signed = cell->parameters["\\B_SIGNED"].as_bool(); bool swapped_ab = false; - RTLIL::SigSpec sig_a = assign_map(cell->connections_["\\A"]); - RTLIL::SigSpec sig_b = assign_map(cell->connections_["\\B"]); - RTLIL::SigSpec sig_y = assign_map(cell->connections_["\\Y"]); + RTLIL::SigSpec sig_a = assign_map(cell->get("\\A")); + RTLIL::SigSpec sig_b = assign_map(cell->get("\\B")); + RTLIL::SigSpec sig_y = assign_map(cell->get("\\Y")); if (sig_b.is_fully_const() && sig_b.size() <= 32) std::swap(sig_a, sig_b), std::swap(a_signed, b_signed), swapped_ab = true; @@ -820,7 +820,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo log("Replacing multiply-by-zero cell `%s' in module `%s' with zero-driver.\n", cell->name.c_str(), module->name.c_str()); - module->connections_.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size()))); + module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size()))); module->remove(cell); OPT_DID_SOMETHING = true; @@ -840,7 +840,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo a_val, cell->name.c_str(), module->name.c_str(), i); if (!swapped_ab) { - cell->connections_["\\A"] = cell->connections_["\\B"]; + cell->set("\\A", cell->get("\\B")); cell->parameters["\\A_WIDTH"] = cell->parameters["\\B_WIDTH"]; cell->parameters["\\A_SIGNED"] = cell->parameters["\\B_SIGNED"]; } @@ -853,7 +853,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cell->type = "$shl"; cell->parameters["\\B_WIDTH"] = SIZE(new_b); cell->parameters["\\B_SIGNED"] = false; - cell->connections_["\\B"] = new_b; + cell->set("\\B", new_b); cell->check(); OPT_DID_SOMETHING = true; diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc index 33e66e077..8487152ff 100644 --- a/passes/opt/opt_muxtree.cc +++ b/passes/opt/opt_muxtree.cc @@ -88,10 +88,10 @@ struct OptMuxtreeWorker RTLIL::Cell *cell = cell_it.second; if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux") { - RTLIL::SigSpec sig_a = cell->connections_["\\A"]; - RTLIL::SigSpec sig_b = cell->connections_["\\B"]; - RTLIL::SigSpec sig_s = cell->connections_["\\S"]; - RTLIL::SigSpec sig_y = cell->connections_["\\Y"]; + RTLIL::SigSpec sig_a = cell->get("\\A"); + RTLIL::SigSpec sig_b = cell->get("\\B"); + RTLIL::SigSpec sig_s = cell->get("\\S"); + RTLIL::SigSpec sig_y = cell->get("\\Y"); muxinfo_t muxinfo; muxinfo.cell = cell; @@ -130,7 +130,7 @@ struct OptMuxtreeWorker } else { - for (auto &it : cell->connections_) { + for (auto &it : cell->connections()) { for (int idx : sig2bits(it.second)) bit2info[idx].seen_non_mux = true; } @@ -194,10 +194,10 @@ struct OptMuxtreeWorker continue; } - RTLIL::SigSpec sig_a = mi.cell->connections_["\\A"]; - RTLIL::SigSpec sig_b = mi.cell->connections_["\\B"]; - RTLIL::SigSpec sig_s = mi.cell->connections_["\\S"]; - RTLIL::SigSpec sig_y = mi.cell->connections_["\\Y"]; + RTLIL::SigSpec sig_a = mi.cell->get("\\A"); + RTLIL::SigSpec sig_b = mi.cell->get("\\B"); + RTLIL::SigSpec sig_s = mi.cell->get("\\S"); + RTLIL::SigSpec sig_y = mi.cell->get("\\Y"); RTLIL::SigSpec sig_ports = sig_b; sig_ports.append(sig_a); @@ -205,7 +205,7 @@ struct OptMuxtreeWorker if (live_ports.size() == 1) { RTLIL::SigSpec sig_in = sig_ports.extract(live_ports[0]*sig_a.size(), sig_a.size()); - module->connections_.push_back(RTLIL::SigSig(sig_y, sig_in)); + module->connect(RTLIL::SigSig(sig_y, sig_in)); module->remove(mi.cell); } else @@ -222,9 +222,9 @@ struct OptMuxtreeWorker } } - mi.cell->connections_["\\A"] = new_sig_a; - mi.cell->connections_["\\B"] = new_sig_b; - mi.cell->connections_["\\S"] = new_sig_s; + mi.cell->set("\\A", new_sig_a); + mi.cell->set("\\B", new_sig_b); + mi.cell->set("\\S", new_sig_s); if (new_sig_s.size() == 1) { mi.cell->type = "$mux"; mi.cell->parameters.erase("\\S_WIDTH"); diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc index 7a7f02f6d..8c281b342 100644 --- a/passes/opt/opt_reduce.cc +++ b/passes/opt/opt_reduce.cc @@ -43,7 +43,7 @@ struct OptReduceWorker return; cells.erase(cell); - RTLIL::SigSpec sig_a = assign_map(cell->connections_["\\A"]); + RTLIL::SigSpec sig_a = assign_map(cell->get("\\A")); std::set new_sig_a_bits; for (auto &bit : sig_a.to_sigbit_set()) @@ -73,8 +73,8 @@ struct OptReduceWorker for (auto child_cell : drivers.find(bit)) { if (child_cell->type == cell->type) { opt_reduce(cells, drivers, child_cell); - if (child_cell->connections_["\\Y"][0] == bit) { - std::set child_sig_a_bits = assign_map(child_cell->connections_["\\A"]).to_sigbit_set(); + if (child_cell->get("\\Y")[0] == bit) { + std::set child_sig_a_bits = assign_map(child_cell->get("\\A")).to_sigbit_set(); new_sig_a_bits.insert(child_sig_a_bits.begin(), child_sig_a_bits.end()); } else new_sig_a_bits.insert(RTLIL::State::S0); @@ -87,23 +87,23 @@ struct OptReduceWorker RTLIL::SigSpec new_sig_a(new_sig_a_bits); - if (new_sig_a != sig_a || sig_a.size() != cell->connections_["\\A"].size()) { + if (new_sig_a != sig_a || sig_a.size() != cell->get("\\A").size()) { log(" New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a)); did_something = true; OPT_DID_SOMETHING = true; total_count++; } - cell->connections_["\\A"] = new_sig_a; + cell->set("\\A", new_sig_a); cell->parameters["\\A_WIDTH"] = RTLIL::Const(new_sig_a.size()); return; } void opt_mux(RTLIL::Cell *cell) { - RTLIL::SigSpec sig_a = assign_map(cell->connections_["\\A"]); - RTLIL::SigSpec sig_b = assign_map(cell->connections_["\\B"]); - RTLIL::SigSpec sig_s = assign_map(cell->connections_["\\S"]); + RTLIL::SigSpec sig_a = assign_map(cell->get("\\A")); + RTLIL::SigSpec sig_b = assign_map(cell->get("\\B")); + RTLIL::SigSpec sig_s = assign_map(cell->get("\\S")); RTLIL::SigSpec new_sig_b, new_sig_s; std::set handled_sig; @@ -125,14 +125,14 @@ struct OptReduceWorker if (this_s.size() > 1) { RTLIL::Cell *reduce_or_cell = module->addCell(NEW_ID, "$reduce_or"); - reduce_or_cell->connections_["\\A"] = this_s; + reduce_or_cell->set("\\A", this_s); reduce_or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); reduce_or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(this_s.size()); reduce_or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); RTLIL::Wire *reduce_or_wire = module->addWire(NEW_ID); this_s = RTLIL::SigSpec(reduce_or_wire); - reduce_or_cell->connections_["\\Y"] = this_s; + reduce_or_cell->set("\\Y", this_s); } new_sig_b.append(this_b); @@ -149,14 +149,14 @@ struct OptReduceWorker if (new_sig_s.size() == 0) { - module->connections_.push_back(RTLIL::SigSig(cell->connections_["\\Y"], cell->connections_["\\A"])); - assign_map.add(cell->connections_["\\Y"], cell->connections_["\\A"]); + module->connect(RTLIL::SigSig(cell->get("\\Y"), cell->get("\\A"))); + assign_map.add(cell->get("\\Y"), cell->get("\\A")); module->remove(cell); } else { - cell->connections_["\\B"] = new_sig_b; - cell->connections_["\\S"] = new_sig_s; + cell->set("\\B", new_sig_b); + cell->set("\\S", new_sig_s); if (new_sig_s.size() > 1) { cell->parameters["\\S_WIDTH"] = RTLIL::Const(new_sig_s.size()); } else { @@ -168,9 +168,9 @@ struct OptReduceWorker void opt_mux_bits(RTLIL::Cell *cell) { - std::vector sig_a = assign_map(cell->connections_["\\A"]).to_sigbit_vector(); - std::vector sig_b = assign_map(cell->connections_["\\B"]).to_sigbit_vector(); - std::vector sig_y = assign_map(cell->connections_["\\Y"]).to_sigbit_vector(); + std::vector sig_a = assign_map(cell->get("\\A")).to_sigbit_vector(); + std::vector sig_b = assign_map(cell->get("\\B")).to_sigbit_vector(); + std::vector sig_y = assign_map(cell->get("\\Y")).to_sigbit_vector(); std::vector new_sig_y; RTLIL::SigSig old_sig_conn; @@ -211,26 +211,26 @@ struct OptReduceWorker if (new_sig_y.size() != sig_y.size()) { log(" Consolidated identical input bits for %s cell %s:\n", cell->type.c_str(), cell->name.c_str()); - log(" Old ports: A=%s, B=%s, Y=%s\n", log_signal(cell->connections_["\\A"]), - log_signal(cell->connections_["\\B"]), log_signal(cell->connections_["\\Y"])); + log(" Old ports: A=%s, B=%s, Y=%s\n", log_signal(cell->get("\\A")), + log_signal(cell->get("\\B")), log_signal(cell->get("\\Y"))); - cell->connections_["\\A"] = RTLIL::SigSpec(); + cell->set("\\A", RTLIL::SigSpec()); for (auto &in_tuple : consolidated_in_tuples) - cell->connections_["\\A"].append(in_tuple.at(0)); + cell->get("\\A").append(in_tuple.at(0)); - cell->connections_["\\B"] = RTLIL::SigSpec(); - for (int i = 1; i <= cell->connections_["\\S"].size(); i++) + cell->set("\\B", RTLIL::SigSpec()); + for (int i = 1; i <= cell->get("\\S").size(); i++) for (auto &in_tuple : consolidated_in_tuples) - cell->connections_["\\B"].append(in_tuple.at(i)); + cell->get("\\B").append(in_tuple.at(i)); cell->parameters["\\WIDTH"] = RTLIL::Const(new_sig_y.size()); - cell->connections_["\\Y"] = new_sig_y; + cell->set("\\Y", new_sig_y); - log(" New ports: A=%s, B=%s, Y=%s\n", log_signal(cell->connections_["\\A"]), - log_signal(cell->connections_["\\B"]), log_signal(cell->connections_["\\Y"])); + log(" New ports: A=%s, B=%s, Y=%s\n", log_signal(cell->get("\\A")), + log_signal(cell->get("\\B")), log_signal(cell->get("\\Y"))); log(" New connections: %s = %s\n", log_signal(old_sig_conn.first), log_signal(old_sig_conn.second)); - module->connections_.push_back(old_sig_conn); + module->connect(old_sig_conn); module->check(); did_something = true; @@ -251,14 +251,14 @@ struct OptReduceWorker for (auto &cell_it : module->cells) { RTLIL::Cell *cell = cell_it.second; if (cell->type == "$mem") - mem_wren_sigs.add(assign_map(cell->connections_["\\WR_EN"])); + mem_wren_sigs.add(assign_map(cell->get("\\WR_EN"))); if (cell->type == "$memwr") - mem_wren_sigs.add(assign_map(cell->connections_["\\EN"])); + mem_wren_sigs.add(assign_map(cell->get("\\EN"))); } for (auto &cell_it : module->cells) { RTLIL::Cell *cell = cell_it.second; - if (cell->type == "$dff" && mem_wren_sigs.check_any(assign_map(cell->connections_["\\Q"]))) - mem_wren_sigs.add(assign_map(cell->connections_["\\D"])); + if (cell->type == "$dff" && mem_wren_sigs.check_any(assign_map(cell->get("\\Q")))) + mem_wren_sigs.add(assign_map(cell->get("\\D"))); } bool keep_expanding_mem_wren_sigs = true; @@ -266,12 +266,12 @@ struct OptReduceWorker keep_expanding_mem_wren_sigs = false; for (auto &cell_it : module->cells) { RTLIL::Cell *cell = cell_it.second; - if (cell->type == "$mux" && mem_wren_sigs.check_any(assign_map(cell->connections_["\\Y"]))) { - if (!mem_wren_sigs.check_all(assign_map(cell->connections_["\\A"])) || - !mem_wren_sigs.check_all(assign_map(cell->connections_["\\B"]))) + if (cell->type == "$mux" && mem_wren_sigs.check_any(assign_map(cell->get("\\Y")))) { + if (!mem_wren_sigs.check_all(assign_map(cell->get("\\A"))) || + !mem_wren_sigs.check_all(assign_map(cell->get("\\B")))) keep_expanding_mem_wren_sigs = true; - mem_wren_sigs.add(assign_map(cell->connections_["\\A"])); - mem_wren_sigs.add(assign_map(cell->connections_["\\B"])); + mem_wren_sigs.add(assign_map(cell->get("\\A"))); + mem_wren_sigs.add(assign_map(cell->get("\\B"))); } } } @@ -293,7 +293,7 @@ struct OptReduceWorker RTLIL::Cell *cell = cell_it.second; if (cell->type != type || !design->selected(module, cell)) continue; - drivers.insert(assign_map(cell->connections_["\\Y"]), cell); + drivers.insert(assign_map(cell->get("\\Y")), cell); cells.insert(cell); } @@ -315,7 +315,7 @@ struct OptReduceWorker { // this optimization is to aggressive for most coarse-grain applications. // but we always want it for multiplexers driving write enable ports. - if (do_fine || mem_wren_sigs.check_any(assign_map(cell->connections_.at("\\Y")))) + if (do_fine || mem_wren_sigs.check_any(assign_map(cell->get("\\Y")))) opt_mux_bits(cell); opt_mux(cell); diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc index 4ece182f4..8c09f5414 100644 --- a/passes/opt/opt_rmdff.cc +++ b/passes/opt/opt_rmdff.cc @@ -33,34 +33,34 @@ static bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) RTLIL::Const val_cp, val_rp, val_rv; if (dff->type == "$_DFF_N_" || dff->type == "$_DFF_P_") { - sig_d = dff->connections_["\\D"]; - sig_q = dff->connections_["\\Q"]; - sig_c = dff->connections_["\\C"]; + sig_d = dff->get("\\D"); + sig_q = dff->get("\\Q"); + sig_c = dff->get("\\C"); val_cp = RTLIL::Const(dff->type == "$_DFF_P_", 1); } else if (dff->type.substr(0,6) == "$_DFF_" && dff->type.substr(9) == "_" && (dff->type[6] == 'N' || dff->type[6] == 'P') && (dff->type[7] == 'N' || dff->type[7] == 'P') && (dff->type[8] == '0' || dff->type[8] == '1')) { - sig_d = dff->connections_["\\D"]; - sig_q = dff->connections_["\\Q"]; - sig_c = dff->connections_["\\C"]; - sig_r = dff->connections_["\\R"]; + sig_d = dff->get("\\D"); + sig_q = dff->get("\\Q"); + sig_c = dff->get("\\C"); + sig_r = dff->get("\\R"); val_cp = RTLIL::Const(dff->type[6] == 'P', 1); val_rp = RTLIL::Const(dff->type[7] == 'P', 1); val_rv = RTLIL::Const(dff->type[8] == '1', 1); } else if (dff->type == "$dff") { - sig_d = dff->connections_["\\D"]; - sig_q = dff->connections_["\\Q"]; - sig_c = dff->connections_["\\CLK"]; + sig_d = dff->get("\\D"); + sig_q = dff->get("\\Q"); + sig_c = dff->get("\\CLK"); val_cp = RTLIL::Const(dff->parameters["\\CLK_POLARITY"].as_bool(), 1); } else if (dff->type == "$adff") { - sig_d = dff->connections_["\\D"]; - sig_q = dff->connections_["\\Q"]; - sig_c = dff->connections_["\\CLK"]; - sig_r = dff->connections_["\\ARST"]; + sig_d = dff->get("\\D"); + sig_q = dff->get("\\Q"); + sig_c = dff->get("\\CLK"); + sig_r = dff->get("\\ARST"); val_cp = RTLIL::Const(dff->parameters["\\CLK_POLARITY"].as_bool(), 1); val_rp = RTLIL::Const(dff->parameters["\\ARST_POLARITY"].as_bool(), 1); val_rv = dff->parameters["\\ARST_VALUE"]; @@ -85,16 +85,16 @@ static bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) std::set muxes; mux_drivers.find(sig_d, muxes); for (auto mux : muxes) { - RTLIL::SigSpec sig_a = assign_map(mux->connections_.at("\\A")); - RTLIL::SigSpec sig_b = assign_map(mux->connections_.at("\\B")); + RTLIL::SigSpec sig_a = assign_map(mux->get("\\A")); + RTLIL::SigSpec sig_b = assign_map(mux->get("\\B")); if (sig_a == sig_q && sig_b.is_fully_const()) { RTLIL::SigSig conn(sig_q, sig_b); - mod->connections_.push_back(conn); + mod->connect(conn); goto delete_dff; } if (sig_b == sig_q && sig_a.is_fully_const()) { RTLIL::SigSig conn(sig_q, sig_a); - mod->connections_.push_back(conn); + mod->connect(conn); goto delete_dff; } } @@ -104,36 +104,36 @@ static bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) if (val_rv.bits.size() == 0) val_rv = val_init; RTLIL::SigSig conn(sig_q, val_rv); - mod->connections_.push_back(conn); + mod->connect(conn); goto delete_dff; } if (sig_d.is_fully_undef() && sig_r.size() && !has_init) { RTLIL::SigSig conn(sig_q, val_rv); - mod->connections_.push_back(conn); + mod->connect(conn); goto delete_dff; } if (sig_d.is_fully_undef() && !sig_r.size() && has_init) { RTLIL::SigSig conn(sig_q, val_init); - mod->connections_.push_back(conn); + mod->connect(conn); goto delete_dff; } if (sig_d.is_fully_const() && !sig_r.size() && !has_init) { RTLIL::SigSig conn(sig_q, sig_d); - mod->connections_.push_back(conn); + mod->connect(conn); goto delete_dff; } if (sig_d == sig_q && !(sig_r.size() && has_init)) { if (sig_r.size()) { RTLIL::SigSig conn(sig_q, val_rv); - mod->connections_.push_back(conn); + mod->connect(conn); } if (has_init) { RTLIL::SigSig conn(sig_q, val_init); - mod->connections_.push_back(conn); + mod->connect(conn); } goto delete_dff; } @@ -181,8 +181,8 @@ struct OptRmdffPass : public Pass { std::vector dff_list; for (auto &it : mod_it.second->cells) { if (it.second->type == "$mux" || it.second->type == "$pmux") { - if (it.second->connections_.at("\\A").size() == it.second->connections_.at("\\B").size()) - mux_drivers.insert(assign_map(it.second->connections_.at("\\Y")), it.second); + if (it.second->get("\\A").size() == it.second->get("\\B").size()) + mux_drivers.insert(assign_map(it.second->get("\\Y")), it.second); continue; } if (!design->selected(mod_it.second, it.second)) diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc index b3a37209b..8412f929f 100644 --- a/passes/opt/opt_share.cc +++ b/passes/opt/opt_share.cc @@ -66,7 +66,7 @@ struct OptShareWorker for (auto &it : cell->parameters) hash_string += "P " + it.first + "=" + it.second.as_string() + "\n"; - const std::map *conn = &cell->connections_; + const std::map *conn = &cell->connections(); std::map alt_conn; if (cell->type == "$and" || cell->type == "$or" || cell->type == "$xor" || cell->type == "$xnor" || cell->type == "$add" || cell->type == "$mul" || @@ -135,8 +135,8 @@ struct OptShareWorker return true; } - std::map conn1 = cell1->connections_; - std::map conn2 = cell2->connections_; + std::map conn1 = cell1->connections(); + std::map conn2 = cell2->connections(); for (auto &it : conn1) { if (ct.cell_output(cell1->type, it.first)) @@ -180,8 +180,8 @@ struct OptShareWorker } if (cell1->type.substr(0, 1) == "$" && conn1.count("\\Q") != 0) { - std::vector q1 = dff_init_map(cell1->connections_.at("\\Q")).to_sigbit_vector(); - std::vector q2 = dff_init_map(cell2->connections_.at("\\Q")).to_sigbit_vector(); + std::vector q1 = dff_init_map(cell1->get("\\Q")).to_sigbit_vector(); + std::vector q2 = dff_init_map(cell2->get("\\Q")).to_sigbit_vector(); for (size_t i = 0; i < q1.size(); i++) if ((q1.at(i).wire == NULL || q2.at(i).wire == NULL) && q1.at(i) != q2.at(i)) { lt = q1.at(i) < q2.at(i); @@ -261,12 +261,12 @@ struct OptShareWorker if (sharemap.count(cell) > 0) { did_something = true; log(" Cell `%s' is identical to cell `%s'.\n", cell->name.c_str(), sharemap[cell]->name.c_str()); - for (auto &it : cell->connections_) { + for (auto &it : cell->connections()) { if (ct.cell_output(cell->type, it.first)) { - RTLIL::SigSpec other_sig = sharemap[cell]->connections_[it.first]; + RTLIL::SigSpec other_sig = sharemap[cell]->connections()[it.first]; log(" Redirecting output %s: %s = %s\n", it.first.c_str(), log_signal(it.second), log_signal(other_sig)); - module->connections_.push_back(RTLIL::SigSig(it.second, other_sig)); + module->connect(RTLIL::SigSig(it.second, other_sig)); assign_map.add(it.second, other_sig); } } diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc index ce3133601..114f2567e 100644 --- a/passes/proc/proc_arst.cc +++ b/passes/proc/proc_arst.cc @@ -35,40 +35,40 @@ static bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSp for (auto &cell_it : mod->cells) { RTLIL::Cell *cell = cell_it.second; - if (cell->type == "$reduce_or" && cell->connections_["\\Y"] == signal) - return check_signal(mod, cell->connections_["\\A"], ref, polarity); - if (cell->type == "$reduce_bool" && cell->connections_["\\Y"] == signal) - return check_signal(mod, cell->connections_["\\A"], ref, polarity); - if (cell->type == "$logic_not" && cell->connections_["\\Y"] == signal) { + if (cell->type == "$reduce_or" && cell->get("\\Y") == signal) + return check_signal(mod, cell->get("\\A"), ref, polarity); + if (cell->type == "$reduce_bool" && cell->get("\\Y") == signal) + return check_signal(mod, cell->get("\\A"), ref, polarity); + if (cell->type == "$logic_not" && cell->get("\\Y") == signal) { polarity = !polarity; - return check_signal(mod, cell->connections_["\\A"], ref, polarity); + return check_signal(mod, cell->get("\\A"), ref, polarity); } - if (cell->type == "$not" && cell->connections_["\\Y"] == signal) { + if (cell->type == "$not" && cell->get("\\Y") == signal) { polarity = !polarity; - return check_signal(mod, cell->connections_["\\A"], ref, polarity); + return check_signal(mod, cell->get("\\A"), ref, polarity); } - if ((cell->type == "$eq" || cell->type == "$eqx") && cell->connections_["\\Y"] == signal) { - if (cell->connections_["\\A"].is_fully_const()) { - if (!cell->connections_["\\A"].as_bool()) + if ((cell->type == "$eq" || cell->type == "$eqx") && cell->get("\\Y") == signal) { + if (cell->get("\\A").is_fully_const()) { + if (!cell->get("\\A").as_bool()) polarity = !polarity; - return check_signal(mod, cell->connections_["\\B"], ref, polarity); + return check_signal(mod, cell->get("\\B"), ref, polarity); } - if (cell->connections_["\\B"].is_fully_const()) { - if (!cell->connections_["\\B"].as_bool()) + if (cell->get("\\B").is_fully_const()) { + if (!cell->get("\\B").as_bool()) polarity = !polarity; - return check_signal(mod, cell->connections_["\\A"], ref, polarity); + return check_signal(mod, cell->get("\\A"), ref, polarity); } } - if ((cell->type == "$ne" || cell->type == "$nex") && cell->connections_["\\Y"] == signal) { - if (cell->connections_["\\A"].is_fully_const()) { - if (cell->connections_["\\A"].as_bool()) + if ((cell->type == "$ne" || cell->type == "$nex") && cell->get("\\Y") == signal) { + if (cell->get("\\A").is_fully_const()) { + if (cell->get("\\A").as_bool()) polarity = !polarity; - return check_signal(mod, cell->connections_["\\B"], ref, polarity); + return check_signal(mod, cell->get("\\B"), ref, polarity); } - if (cell->connections_["\\B"].is_fully_const()) { - if (cell->connections_["\\B"].as_bool()) + if (cell->get("\\B").is_fully_const()) { + if (cell->get("\\B").as_bool()) polarity = !polarity; - return check_signal(mod, cell->connections_["\\A"], ref, polarity); + return check_signal(mod, cell->get("\\A"), ref, polarity); } } } diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index 9d2c897ee..2e2d4701f 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -77,8 +77,8 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.size()); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - cell->connections_["\\A"] = sync_low_signals; - cell->connections_["\\Y"] = sync_low_signals = mod->addWire(NEW_ID); + cell->set("\\A", sync_low_signals); + cell->set("\\Y", sync_low_signals = mod->addWire(NEW_ID)); } if (sync_low_signals.size() > 0) { @@ -86,9 +86,9 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.size()); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - cell->connections_["\\A"] = sync_low_signals; - cell->connections_["\\Y"] = mod->addWire(NEW_ID); - sync_high_signals.append(cell->connections_["\\Y"]); + cell->set("\\A", sync_low_signals); + cell->set("\\Y", mod->addWire(NEW_ID)); + sync_high_signals.append(cell->get("\\Y")); } if (sync_high_signals.size() > 1) { @@ -96,30 +96,30 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_high_signals.size()); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - cell->connections_["\\A"] = sync_high_signals; - cell->connections_["\\Y"] = sync_high_signals = mod->addWire(NEW_ID); + cell->set("\\A", sync_high_signals); + cell->set("\\Y", sync_high_signals = mod->addWire(NEW_ID)); } RTLIL::Cell *inv_cell = mod->addCell(NEW_ID, "$not"); inv_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); inv_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_d.size()); inv_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_d.size()); - inv_cell->connections_["\\A"] = sync_value; - inv_cell->connections_["\\Y"] = sync_value_inv = mod->addWire(NEW_ID, sig_d.size()); + inv_cell->set("\\A", sync_value); + inv_cell->set("\\Y", sync_value_inv = mod->addWire(NEW_ID, sig_d.size())); RTLIL::Cell *mux_set_cell = mod->addCell(NEW_ID, "$mux"); mux_set_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size()); - mux_set_cell->connections_["\\A"] = sig_sr_set; - mux_set_cell->connections_["\\B"] = sync_value; - mux_set_cell->connections_["\\S"] = sync_high_signals; - mux_set_cell->connections_["\\Y"] = sig_sr_set = mod->addWire(NEW_ID, sig_d.size()); + mux_set_cell->set("\\A", sig_sr_set); + mux_set_cell->set("\\B", sync_value); + mux_set_cell->set("\\S", sync_high_signals); + mux_set_cell->set("\\Y", sig_sr_set = mod->addWire(NEW_ID, sig_d.size())); RTLIL::Cell *mux_clr_cell = mod->addCell(NEW_ID, "$mux"); mux_clr_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size()); - mux_clr_cell->connections_["\\A"] = sig_sr_clr; - mux_clr_cell->connections_["\\B"] = sync_value_inv; - mux_clr_cell->connections_["\\S"] = sync_high_signals; - mux_clr_cell->connections_["\\Y"] = sig_sr_clr = mod->addWire(NEW_ID, sig_d.size()); + mux_clr_cell->set("\\A", sig_sr_clr); + mux_clr_cell->set("\\B", sync_value_inv); + mux_clr_cell->set("\\S", sync_high_signals); + mux_clr_cell->set("\\Y", sig_sr_clr = mod->addWire(NEW_ID, sig_d.size())); } std::stringstream sstr; @@ -131,11 +131,11 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1); cell->parameters["\\SET_POLARITY"] = RTLIL::Const(true, 1); cell->parameters["\\CLR_POLARITY"] = RTLIL::Const(true, 1); - cell->connections_["\\D"] = sig_d; - cell->connections_["\\Q"] = sig_q; - cell->connections_["\\CLK"] = clk; - cell->connections_["\\SET"] = sig_sr_set; - cell->connections_["\\CLR"] = sig_sr_clr; + cell->set("\\D", sig_d); + cell->set("\\Q", sig_q); + cell->set("\\CLK", clk); + cell->set("\\SET", sig_sr_set); + cell->set("\\CLR", sig_sr_clr); log(" created %s cell `%s' with %s edge clock and multiple level-sensitive resets.\n", cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative"); @@ -155,22 +155,22 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec inv_set->parameters["\\A_SIGNED"] = RTLIL::Const(0); inv_set->parameters["\\A_WIDTH"] = RTLIL::Const(sig_in.size()); inv_set->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_in.size()); - inv_set->connections_["\\A"] = sig_set; - inv_set->connections_["\\Y"] = sig_set_inv; + inv_set->set("\\A", sig_set); + inv_set->set("\\Y", sig_set_inv); RTLIL::Cell *mux_sr_set = mod->addCell(NEW_ID, "$mux"); mux_sr_set->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size()); - mux_sr_set->connections_[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.size()); - mux_sr_set->connections_[set_polarity ? "\\B" : "\\A"] = sig_set; - mux_sr_set->connections_["\\Y"] = sig_sr_set; - mux_sr_set->connections_["\\S"] = set; + mux_sr_set->connections()[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.size()); + mux_sr_set->connections()[set_polarity ? "\\B" : "\\A"] = sig_set; + mux_sr_set->set("\\Y", sig_sr_set); + mux_sr_set->set("\\S", set); RTLIL::Cell *mux_sr_clr = mod->addCell(NEW_ID, "$mux"); mux_sr_clr->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size()); - mux_sr_clr->connections_[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.size()); - mux_sr_clr->connections_[set_polarity ? "\\B" : "\\A"] = sig_set_inv; - mux_sr_clr->connections_["\\Y"] = sig_sr_clr; - mux_sr_clr->connections_["\\S"] = set; + mux_sr_clr->connections()[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.size()); + mux_sr_clr->connections()[set_polarity ? "\\B" : "\\A"] = sig_set_inv; + mux_sr_clr->set("\\Y", sig_sr_clr); + mux_sr_clr->set("\\S", set); RTLIL::Cell *cell = mod->addCell(sstr.str(), "$dffsr"); cell->attributes = proc->attributes; @@ -178,11 +178,11 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1); cell->parameters["\\SET_POLARITY"] = RTLIL::Const(true, 1); cell->parameters["\\CLR_POLARITY"] = RTLIL::Const(true, 1); - cell->connections_["\\D"] = sig_in; - cell->connections_["\\Q"] = sig_out; - cell->connections_["\\CLK"] = clk; - cell->connections_["\\SET"] = sig_sr_set; - cell->connections_["\\CLR"] = sig_sr_clr; + cell->set("\\D", sig_in); + cell->set("\\Q", sig_out); + cell->set("\\CLK", clk); + cell->set("\\SET", sig_sr_set); + cell->set("\\CLR", sig_sr_clr); log(" created %s cell `%s' with %s edge clock and %s level non-const reset.\n", cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative", set_polarity ? "positive" : "negative"); @@ -204,11 +204,11 @@ static void gen_dff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::Const val_ } cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1); - cell->connections_["\\D"] = sig_in; - cell->connections_["\\Q"] = sig_out; + cell->set("\\D", sig_in); + cell->set("\\Q", sig_out); if (arst) - cell->connections_["\\ARST"] = *arst; - cell->connections_["\\CLK"] = clk; + cell->set("\\ARST", *arst); + cell->set("\\CLK", clk); log(" created %s cell `%s' with %s edge clock", cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative"); if (arst) @@ -296,9 +296,9 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) cell->parameters["\\A_WIDTH"] = RTLIL::Const(inputs.size()); cell->parameters["\\B_WIDTH"] = RTLIL::Const(inputs.size()); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - cell->connections_["\\A"] = inputs; - cell->connections_["\\B"] = compare; - cell->connections_["\\Y"] = sync_level->signal; + cell->set("\\A", inputs); + cell->set("\\B", compare); + cell->set("\\Y", sync_level->signal); many_async_rules.clear(); } @@ -322,7 +322,7 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) if (sync_edge || sync_level || many_async_rules.size() > 0) log_error("Mixed always event with edge and/or level sensitive events!\n"); log(" created direct connection (no actual register cell created).\n"); - mod->connections_.push_back(RTLIL::SigSig(sig, insig)); + mod->connect(RTLIL::SigSig(sig, insig)); continue; } diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc index 2cde749a5..2ff755aef 100644 --- a/passes/proc/proc_mux.cc +++ b/passes/proc/proc_mux.cc @@ -81,7 +81,7 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, if (sig.size() == 1 && comp == RTLIL::SigSpec(1,1)) { - mod->connections_.push_back(RTLIL::SigSig(RTLIL::SigSpec(cmp_wire, cmp_wire->width++), sig)); + mod->connect(RTLIL::SigSig(RTLIL::SigSpec(cmp_wire, cmp_wire->width++), sig)); } else { @@ -96,9 +96,9 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(comp.size()); eq_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - eq_cell->connections_["\\A"] = sig; - eq_cell->connections_["\\B"] = comp; - eq_cell->connections_["\\Y"] = RTLIL::SigSpec(cmp_wire, cmp_wire->width++); + eq_cell->set("\\A", sig); + eq_cell->set("\\B", comp); + eq_cell->set("\\Y", RTLIL::SigSpec(cmp_wire, cmp_wire->width++)); } } @@ -122,8 +122,8 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, any_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cmp_wire->width); any_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - any_cell->connections_["\\A"] = cmp_wire; - any_cell->connections_["\\Y"] = RTLIL::SigSpec(ctrl_wire); + any_cell->set("\\A", cmp_wire); + any_cell->set("\\Y", RTLIL::SigSpec(ctrl_wire)); } return RTLIL::SigSpec(ctrl_wire); @@ -157,10 +157,10 @@ static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, mux_cell->attributes = sw->attributes; mux_cell->parameters["\\WIDTH"] = RTLIL::Const(when_signal.size()); - mux_cell->connections_["\\A"] = else_signal; - mux_cell->connections_["\\B"] = when_signal; - mux_cell->connections_["\\S"] = ctrl_sig; - mux_cell->connections_["\\Y"] = RTLIL::SigSpec(result_wire); + mux_cell->set("\\A", else_signal); + mux_cell->set("\\B", when_signal); + mux_cell->set("\\S", ctrl_sig); + mux_cell->set("\\Y", RTLIL::SigSpec(result_wire)); last_mux_cell = mux_cell; return RTLIL::SigSpec(result_wire); @@ -169,14 +169,14 @@ static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, static void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector &compare, RTLIL::SigSpec when_signal, RTLIL::Cell *last_mux_cell, RTLIL::SwitchRule *sw) { assert(last_mux_cell != NULL); - assert(when_signal.size() == last_mux_cell->connections_["\\A"].size()); + assert(when_signal.size() == last_mux_cell->get("\\A").size()); RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw); assert(ctrl_sig.size() == 1); last_mux_cell->type = "$pmux"; - last_mux_cell->connections_["\\S"].append(ctrl_sig); - last_mux_cell->connections_["\\B"].append(when_signal); - last_mux_cell->parameters["\\S_WIDTH"] = last_mux_cell->connections_["\\S"].size(); + last_mux_cell->get("\\S").append(ctrl_sig); + last_mux_cell->get("\\B").append(when_signal); + last_mux_cell->parameters["\\S_WIDTH"] = last_mux_cell->get("\\S").size(); } static RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, RTLIL::CaseRule *cs, const RTLIL::SigSpec &sig, const RTLIL::SigSpec &defval) @@ -256,7 +256,7 @@ static void proc_mux(RTLIL::Module *mod, RTLIL::Process *proc) log(" creating decoder for signal `%s'.\n", log_signal(sig)); RTLIL::SigSpec value = signal_to_mux_tree(mod, &proc->root_case, sig, RTLIL::SigSpec(RTLIL::State::Sx, sig.size())); - mod->connections_.push_back(RTLIL::SigSig(sig, value)); + mod->connect(RTLIL::SigSig(sig, value)); } } diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc index 22b724d53..58dcf915f 100644 --- a/passes/sat/expose.cc +++ b/passes/sat/expose.cc @@ -83,8 +83,8 @@ static void find_dff_wires(std::set &dff_wires, RTLIL::Module *modu SigPool dffsignals; for (auto &it : module->cells) { - if (ct.cell_known(it.second->type) && it.second->connections_.count("\\Q")) - dffsignals.add(sigmap(it.second->connections_.at("\\Q"))); + if (ct.cell_known(it.second->type) && it.second->connections().count("\\Q")) + dffsignals.add(sigmap(it.second->get("\\Q"))); } for (auto &it : module->wires) { @@ -113,10 +113,10 @@ static void create_dff_dq_map(std::map &map, RTLIL: info.cell = it.second; if (info.cell->type == "$dff") { - info.bit_clk = sigmap(info.cell->connections_.at("\\CLK")).to_single_sigbit(); + info.bit_clk = sigmap(info.cell->get("\\CLK")).to_single_sigbit(); info.clk_polarity = info.cell->parameters.at("\\CLK_POLARITY").as_bool(); - std::vector sig_d = sigmap(info.cell->connections_.at("\\D")).to_sigbit_vector(); - std::vector sig_q = sigmap(info.cell->connections_.at("\\Q")).to_sigbit_vector(); + std::vector sig_d = sigmap(info.cell->get("\\D")).to_sigbit_vector(); + std::vector sig_q = sigmap(info.cell->get("\\Q")).to_sigbit_vector(); for (size_t i = 0; i < sig_d.size(); i++) { info.bit_d = sig_d.at(i); bit_info[sig_q.at(i)] = info; @@ -125,12 +125,12 @@ static void create_dff_dq_map(std::map &map, RTLIL: } if (info.cell->type == "$adff") { - info.bit_clk = sigmap(info.cell->connections_.at("\\CLK")).to_single_sigbit(); - info.bit_arst = sigmap(info.cell->connections_.at("\\ARST")).to_single_sigbit(); + info.bit_clk = sigmap(info.cell->get("\\CLK")).to_single_sigbit(); + info.bit_arst = sigmap(info.cell->get("\\ARST")).to_single_sigbit(); info.clk_polarity = info.cell->parameters.at("\\CLK_POLARITY").as_bool(); info.arst_polarity = info.cell->parameters.at("\\ARST_POLARITY").as_bool(); - std::vector sig_d = sigmap(info.cell->connections_.at("\\D")).to_sigbit_vector(); - std::vector sig_q = sigmap(info.cell->connections_.at("\\Q")).to_sigbit_vector(); + std::vector sig_d = sigmap(info.cell->get("\\D")).to_sigbit_vector(); + std::vector sig_q = sigmap(info.cell->get("\\Q")).to_sigbit_vector(); std::vector arst_value = info.cell->parameters.at("\\ARST_VALUE").bits; for (size_t i = 0; i < sig_d.size(); i++) { info.bit_d = sig_d.at(i); @@ -141,21 +141,21 @@ static void create_dff_dq_map(std::map &map, RTLIL: } if (info.cell->type == "$_DFF_N_" || info.cell->type == "$_DFF_P_") { - info.bit_clk = sigmap(info.cell->connections_.at("\\C")).to_single_sigbit(); + info.bit_clk = sigmap(info.cell->get("\\C")).to_single_sigbit(); info.clk_polarity = info.cell->type == "$_DFF_P_"; - info.bit_d = sigmap(info.cell->connections_.at("\\D")).to_single_sigbit(); - bit_info[sigmap(info.cell->connections_.at("\\Q")).to_single_sigbit()] = info; + info.bit_d = sigmap(info.cell->get("\\D")).to_single_sigbit(); + bit_info[sigmap(info.cell->get("\\Q")).to_single_sigbit()] = info; continue; } if (info.cell->type.size() == 10 && info.cell->type.substr(0, 6) == "$_DFF_") { - info.bit_clk = sigmap(info.cell->connections_.at("\\C")).to_single_sigbit(); - info.bit_arst = sigmap(info.cell->connections_.at("\\R")).to_single_sigbit(); + info.bit_clk = sigmap(info.cell->get("\\C")).to_single_sigbit(); + info.bit_arst = sigmap(info.cell->get("\\R")).to_single_sigbit(); info.clk_polarity = info.cell->type[6] == 'P'; info.arst_polarity = info.cell->type[7] == 'P'; info.arst_value = info.cell->type[0] == '1' ? RTLIL::State::S1 : RTLIL::State::S0; - info.bit_d = sigmap(info.cell->connections_.at("\\D")).to_single_sigbit(); - bit_info[sigmap(info.cell->connections_.at("\\Q")).to_single_sigbit()] = info; + info.bit_d = sigmap(info.cell->get("\\D")).to_single_sigbit(); + bit_info[sigmap(info.cell->get("\\Q")).to_single_sigbit()] = info; continue; } } @@ -485,12 +485,12 @@ struct ExposePass : public Pass { for (auto &it : module->cells) { if (!ct.cell_known(it.second->type)) continue; - for (auto &conn : it.second->connections_) + for (auto &conn : it.second->connections()) if (ct.cell_input(it.second->type, conn.first)) conn.second = out_to_in_map(sigmap(conn.second)); } - for (auto &conn : module->connections_) + for (auto &conn : module->connections()) conn.second = out_to_in_map(sigmap(conn.second)); } @@ -514,11 +514,11 @@ struct ExposePass : public Pass { for (auto &cell_name : info.cells) { RTLIL::Cell *cell = module->cells.at(cell_name); - std::vector cell_q_bits = sigmap(cell->connections_.at("\\Q")).to_sigbit_vector(); + std::vector cell_q_bits = sigmap(cell->get("\\Q")).to_sigbit_vector(); for (auto &bit : cell_q_bits) if (wire_bits_set.count(bit)) bit = RTLIL::SigBit(wire_dummy_q, wire_dummy_q->width++); - cell->connections_.at("\\Q") = cell_q_bits; + cell->get("\\Q") = cell_q_bits; } RTLIL::Wire *wire_q = new RTLIL::Wire; @@ -536,7 +536,7 @@ struct ExposePass : public Pass { connect_q.second.append(RTLIL::SigBit(wire_q, i)); set_q_bits.insert(wire_bits_vec[i]); } - module->connections_.push_back(connect_q); + module->connect(connect_q); RTLIL::Wire *wire_d = new RTLIL::Wire; wire_d->name = wire->name + sep + "d"; @@ -544,7 +544,7 @@ struct ExposePass : public Pass { wire_d->port_output = true; log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_d->name)); add_new_wire(module, wire_d); - module->connections_.push_back(RTLIL::SigSig(wire_d, info.sig_d)); + module->connect(RTLIL::SigSig(wire_d, info.sig_d)); RTLIL::Wire *wire_c = new RTLIL::Wire; wire_c->name = wire->name + sep + "c"; @@ -552,14 +552,14 @@ struct ExposePass : public Pass { log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_c->name)); add_new_wire(module, wire_c); if (info.clk_polarity) { - module->connections_.push_back(RTLIL::SigSig(wire_c, info.sig_clk)); + module->connect(RTLIL::SigSig(wire_c, info.sig_clk)); } else { RTLIL::Cell *c = module->addCell(NEW_ID, "$not"); c->parameters["\\A_SIGNED"] = 0; c->parameters["\\A_WIDTH"] = 1; c->parameters["\\Y_WIDTH"] = 1; - c->connections_["\\A"] = info.sig_clk; - c->connections_["\\Y"] = wire_c; + c->set("\\A", info.sig_clk); + c->set("\\Y", wire_c); } if (info.sig_arst != RTLIL::State::Sm) @@ -570,14 +570,14 @@ struct ExposePass : public Pass { log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_r->name)); add_new_wire(module, wire_r); if (info.arst_polarity) { - module->connections_.push_back(RTLIL::SigSig(wire_r, info.sig_arst)); + module->connect(RTLIL::SigSig(wire_r, info.sig_arst)); } else { RTLIL::Cell *c = module->addCell(NEW_ID, "$not"); c->parameters["\\A_SIGNED"] = 0; c->parameters["\\A_WIDTH"] = 1; c->parameters["\\Y_WIDTH"] = 1; - c->connections_["\\A"] = info.sig_arst; - c->connections_["\\Y"] = wire_r; + c->set("\\A", info.sig_arst); + c->set("\\Y", wire_r); } RTLIL::Wire *wire_v = new RTLIL::Wire; @@ -586,7 +586,7 @@ struct ExposePass : public Pass { wire_v->port_output = true; log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_v->name)); add_new_wire(module, wire_v); - module->connections_.push_back(RTLIL::SigSig(wire_v, info.arst_value)); + module->connect(RTLIL::SigSig(wire_v, info.arst_value)); } } @@ -628,18 +628,18 @@ struct ExposePass : public Pass { log("New module port: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name), RTLIL::id2cstr(cell->type)); RTLIL::SigSpec sig; - if (cell->connections_.count(p->name) != 0) - sig = cell->connections_.at(p->name); + if (cell->connections().count(p->name) != 0) + sig = cell->connections().at(p->name); sig.extend(w->width); if (w->port_input) - module->connections_.push_back(RTLIL::SigSig(sig, w)); + module->connect(RTLIL::SigSig(sig, w)); else - module->connections_.push_back(RTLIL::SigSig(w, sig)); + module->connect(RTLIL::SigSig(w, sig)); } } else { - for (auto &it : cell->connections_) + for (auto &it : cell->connections()) { RTLIL::Wire *w = new RTLIL::Wire; w->name = cell->name + sep + RTLIL::unescape_id(it.first); @@ -653,9 +653,9 @@ struct ExposePass : public Pass { log("New module port: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name), RTLIL::id2cstr(cell->type)); if (w->port_input) - module->connections_.push_back(RTLIL::SigSig(it.second, w)); + module->connect(RTLIL::SigSig(it.second, w)); else - module->connections_.push_back(RTLIL::SigSig(w, it.second)); + module->connect(RTLIL::SigSig(w, it.second)); } } diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index 517e6713c..da9345855 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -610,7 +610,7 @@ struct FreduceWorker for (auto &it : module->cells) { if (ct.cell_known(it.second->type)) { std::set inputs, outputs; - for (auto &port : it.second->connections_) { + for (auto &port : it.second->connections()) { std::vector bits = sigmap(port.second).to_sigbit_vector(); if (ct.cell_output(it.second->type, port.first)) outputs.insert(bits.begin(), bits.end()); @@ -624,7 +624,7 @@ struct FreduceWorker bits_full_total += outputs.size(); } if (inv_mode && it.second->type == "$_INV_") - inv_pairs.insert(std::pair(sigmap(it.second->connections_.at("\\A")), sigmap(it.second->connections_.at("\\Y")))); + inv_pairs.insert(std::pair(sigmap(it.second->get("\\A")), sigmap(it.second->get("\\Y")))); } int bits_count = 0; @@ -708,7 +708,7 @@ struct FreduceWorker RTLIL::Cell *drv = drivers.at(grp[i].bit).first; RTLIL::Wire *dummy_wire = module->addWire(NEW_ID); - for (auto &port : drv->connections_) + for (auto &port : drv->connections()) if (ct.cell_output(drv->type, port.first)) sigmap(port.second).replace(grp[i].bit, dummy_wire, &port.second); @@ -719,14 +719,14 @@ struct FreduceWorker inv_sig = module->addWire(NEW_ID); RTLIL::Cell *inv_cell = module->addCell(NEW_ID, "$_INV_"); - inv_cell->connections_["\\A"] = grp[0].bit; - inv_cell->connections_["\\Y"] = inv_sig; + inv_cell->set("\\A", grp[0].bit); + inv_cell->set("\\Y", inv_sig); } - module->connections_.push_back(RTLIL::SigSig(grp[i].bit, inv_sig)); + module->connect(RTLIL::SigSig(grp[i].bit, inv_sig)); } else - module->connections_.push_back(RTLIL::SigSig(grp[i].bit, grp[0].bit)); + module->connect(RTLIL::SigSig(grp[i].bit, grp[0].bit)); rewired_sigbits++; } diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index 9e151cdfc..34355122a 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -132,8 +132,8 @@ static void create_miter_equiv(struct Pass *that, std::vector args, w2->width = w1->width; miter_module->add(w2); - gold_cell->connections_[w1->name] = w2; - gate_cell->connections_[w1->name] = w2; + gold_cell->connections()[w1->name] = w2; + gate_cell->connections()[w1->name] = w2; } if (w1->port_output) @@ -150,8 +150,8 @@ static void create_miter_equiv(struct Pass *that, std::vector args, w2_gate->width = w1->width; miter_module->add(w2_gate); - gold_cell->connections_[w1->name] = w2_gold; - gate_cell->connections_[w1->name] = w2_gate; + gold_cell->connections()[w1->name] = w2_gold; + gate_cell->connections()[w1->name] = w2_gate; RTLIL::SigSpec this_condition; @@ -165,9 +165,9 @@ static void create_miter_equiv(struct Pass *that, std::vector args, eqx_cell->parameters["\\Y_WIDTH"] = 1; eqx_cell->parameters["\\A_SIGNED"] = 0; eqx_cell->parameters["\\B_SIGNED"] = 0; - eqx_cell->connections_["\\A"] = RTLIL::SigSpec(w2_gold, i); - eqx_cell->connections_["\\B"] = RTLIL::State::Sx; - eqx_cell->connections_["\\Y"] = gold_x.extract(i, 1); + eqx_cell->set("\\A", RTLIL::SigSpec(w2_gold, i)); + eqx_cell->set("\\B", RTLIL::State::Sx); + eqx_cell->set("\\Y", gold_x.extract(i, 1)); } RTLIL::SigSpec gold_masked = miter_module->addWire(NEW_ID, w2_gold->width); @@ -179,9 +179,9 @@ static void create_miter_equiv(struct Pass *that, std::vector args, or_gold_cell->parameters["\\Y_WIDTH"] = w2_gold->width; or_gold_cell->parameters["\\A_SIGNED"] = 0; or_gold_cell->parameters["\\B_SIGNED"] = 0; - or_gold_cell->connections_["\\A"] = w2_gold; - or_gold_cell->connections_["\\B"] = gold_x; - or_gold_cell->connections_["\\Y"] = gold_masked; + or_gold_cell->set("\\A", w2_gold); + or_gold_cell->set("\\B", gold_x); + or_gold_cell->set("\\Y", gold_masked); RTLIL::Cell *or_gate_cell = miter_module->addCell(NEW_ID, "$or"); or_gate_cell->parameters["\\A_WIDTH"] = w2_gate->width; @@ -189,9 +189,9 @@ static void create_miter_equiv(struct Pass *that, std::vector args, or_gate_cell->parameters["\\Y_WIDTH"] = w2_gate->width; or_gate_cell->parameters["\\A_SIGNED"] = 0; or_gate_cell->parameters["\\B_SIGNED"] = 0; - or_gate_cell->connections_["\\A"] = w2_gate; - or_gate_cell->connections_["\\B"] = gold_x; - or_gate_cell->connections_["\\Y"] = gate_masked; + or_gate_cell->set("\\A", w2_gate); + or_gate_cell->set("\\B", gold_x); + or_gate_cell->set("\\Y", gate_masked); RTLIL::Cell *eq_cell = miter_module->addCell(NEW_ID, "$eqx"); eq_cell->parameters["\\A_WIDTH"] = w2_gold->width; @@ -199,10 +199,10 @@ static void create_miter_equiv(struct Pass *that, std::vector args, eq_cell->parameters["\\Y_WIDTH"] = 1; eq_cell->parameters["\\A_SIGNED"] = 0; eq_cell->parameters["\\B_SIGNED"] = 0; - eq_cell->connections_["\\A"] = gold_masked; - eq_cell->connections_["\\B"] = gate_masked; - eq_cell->connections_["\\Y"] = miter_module->addWire(NEW_ID); - this_condition = eq_cell->connections_["\\Y"]; + eq_cell->set("\\A", gold_masked); + eq_cell->set("\\B", gate_masked); + eq_cell->set("\\Y", miter_module->addWire(NEW_ID)); + this_condition = eq_cell->get("\\Y"); } else { @@ -212,10 +212,10 @@ static void create_miter_equiv(struct Pass *that, std::vector args, eq_cell->parameters["\\Y_WIDTH"] = 1; eq_cell->parameters["\\A_SIGNED"] = 0; eq_cell->parameters["\\B_SIGNED"] = 0; - eq_cell->connections_["\\A"] = w2_gold; - eq_cell->connections_["\\B"] = w2_gate; - eq_cell->connections_["\\Y"] = miter_module->addWire(NEW_ID); - this_condition = eq_cell->connections_["\\Y"]; + eq_cell->set("\\A", w2_gold); + eq_cell->set("\\B", w2_gate); + eq_cell->set("\\Y", miter_module->addWire(NEW_ID)); + this_condition = eq_cell->get("\\Y"); } if (flag_make_outcmp) @@ -224,7 +224,7 @@ static void create_miter_equiv(struct Pass *that, std::vector args, w_cmp->name = "\\cmp_" + RTLIL::unescape_id(w1->name); w_cmp->port_output = true; miter_module->add(w_cmp); - miter_module->connections_.push_back(RTLIL::SigSig(w_cmp, this_condition)); + miter_module->connect(RTLIL::SigSig(w_cmp, this_condition)); } all_conditions.append(this_condition); @@ -236,15 +236,15 @@ static void create_miter_equiv(struct Pass *that, std::vector args, reduce_cell->parameters["\\A_WIDTH"] = all_conditions.size(); reduce_cell->parameters["\\Y_WIDTH"] = 1; reduce_cell->parameters["\\A_SIGNED"] = 0; - reduce_cell->connections_["\\A"] = all_conditions; - reduce_cell->connections_["\\Y"] = miter_module->addWire(NEW_ID); - all_conditions = reduce_cell->connections_["\\Y"]; + reduce_cell->set("\\A", all_conditions); + reduce_cell->set("\\Y", miter_module->addWire(NEW_ID)); + all_conditions = reduce_cell->get("\\Y"); } if (flag_make_assert) { RTLIL::Cell *assert_cell = miter_module->addCell(NEW_ID, "$assert"); - assert_cell->connections_["\\A"] = all_conditions; - assert_cell->connections_["\\EN"] = RTLIL::SigSpec(1, 1); + assert_cell->set("\\A", all_conditions); + assert_cell->set("\\EN", RTLIL::SigSpec(1, 1)); } RTLIL::Wire *w_trigger = new RTLIL::Wire; @@ -257,8 +257,8 @@ static void create_miter_equiv(struct Pass *that, std::vector args, not_cell->parameters["\\A_WIDTH"] = all_conditions.size(); not_cell->parameters["\\Y_WIDTH"] = w_trigger->width; not_cell->parameters["\\A_SIGNED"] = 0; - not_cell->connections_["\\A"] = all_conditions; - not_cell->connections_["\\Y"] = w_trigger; + not_cell->set("\\A", all_conditions); + not_cell->set("\\Y", w_trigger); miter_module->fixup_ports(); diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index cc041391b..71eba2f7f 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -321,7 +321,7 @@ struct SatHelper if (design->selected(module, c.second)) { // log("Import cell: %s\n", RTLIL::id2cstr(c.first)); if (satgen.importCell(c.second, timestep)) { - for (auto &p : c.second->connections_) + for (auto &p : c.second->connections()) if (ct.cell_output(c.second->type, p.first)) show_drivers.insert(sigmap(p.second), c.second); import_cell_counter++; @@ -505,7 +505,7 @@ struct SatHelper final_signals.add(sig); } else { for (auto &d : drivers) - for (auto &p : d->connections_) { + for (auto &p : d->connections()) { if (d->type == "$dff" && p.first == "\\CLK") continue; if (d->type.substr(0, 6) == "$_DFF_" && p.first == "\\C") diff --git a/passes/sat/share.cc b/passes/sat/share.cc index 01acf50df..13ef695e7 100644 --- a/passes/sat/share.cc +++ b/passes/sat/share.cc @@ -77,7 +77,7 @@ struct ShareWorker for (auto &pbit : portbits) { if (pbit.cell->type == "$mux" || pbit.cell->type == "$pmux") { - std::set bits = modwalker.sigmap(pbit.cell->connections_.at("\\S")).to_sigbit_set(); + std::set bits = modwalker.sigmap(pbit.cell->get("\\S")).to_sigbit_set(); terminal_bits.insert(bits.begin(), bits.end()); queue_bits.insert(bits.begin(), bits.end()); visited_cells.insert(pbit.cell); @@ -256,9 +256,9 @@ struct ShareWorker if (c1->parameters.at("\\A_SIGNED").as_bool() != c2->parameters.at("\\A_SIGNED").as_bool()) { RTLIL::Cell *unsigned_cell = c1->parameters.at("\\A_SIGNED").as_bool() ? c2 : c1; - if (unsigned_cell->connections_.at("\\A").to_sigbit_vector().back() != RTLIL::State::S0) { + if (unsigned_cell->get("\\A").to_sigbit_vector().back() != RTLIL::State::S0) { unsigned_cell->parameters.at("\\A_WIDTH") = unsigned_cell->parameters.at("\\A_WIDTH").as_int() + 1; - unsigned_cell->connections_.at("\\A").append_bit(RTLIL::State::S0); + unsigned_cell->get("\\A").append_bit(RTLIL::State::S0); } unsigned_cell->parameters.at("\\A_SIGNED") = true; unsigned_cell->check(); @@ -267,17 +267,17 @@ struct ShareWorker bool a_signed = c1->parameters.at("\\A_SIGNED").as_bool(); log_assert(a_signed == c2->parameters.at("\\A_SIGNED").as_bool()); - RTLIL::SigSpec a1 = c1->connections_.at("\\A"); - RTLIL::SigSpec y1 = c1->connections_.at("\\Y"); + RTLIL::SigSpec a1 = c1->get("\\A"); + RTLIL::SigSpec y1 = c1->get("\\Y"); - RTLIL::SigSpec a2 = c2->connections_.at("\\A"); - RTLIL::SigSpec y2 = c2->connections_.at("\\Y"); + RTLIL::SigSpec a2 = c2->get("\\A"); + RTLIL::SigSpec y2 = c2->get("\\Y"); int a_width = std::max(a1.size(), a2.size()); int y_width = std::max(y1.size(), y2.size()); - if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->connections_.at("\\Y"); - if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->connections_.at("\\Y"); + if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->get("\\Y"); + if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->get("\\Y"); RTLIL::SigSpec a = module->Mux(NEW_ID, a2, a1, act); RTLIL::Wire *y = module->addWire(NEW_ID, y_width); @@ -286,14 +286,14 @@ struct ShareWorker supercell->parameters["\\A_SIGNED"] = a_signed; supercell->parameters["\\A_WIDTH"] = a_width; supercell->parameters["\\Y_WIDTH"] = y_width; - supercell->connections_["\\A"] = a; - supercell->connections_["\\Y"] = y; + supercell->set("\\A", a); + supercell->set("\\Y", y); RTLIL::SigSpec new_y1(y, 0, y1.size()); RTLIL::SigSpec new_y2(y, 0, y2.size()); - module->connections_.push_back(RTLIL::SigSig(y1, new_y1)); - module->connections_.push_back(RTLIL::SigSig(y2, new_y2)); + module->connect(RTLIL::SigSig(y1, new_y1)); + module->connect(RTLIL::SigSig(y2, new_y2)); return supercell; } @@ -312,7 +312,7 @@ struct ShareWorker if (score_flipped < score_unflipped) { - std::swap(c2->connections_.at("\\A"), c2->connections_.at("\\B")); + std::swap(c2->get("\\A"), c2->get("\\B")); std::swap(c2->parameters.at("\\A_WIDTH"), c2->parameters.at("\\B_WIDTH")); std::swap(c2->parameters.at("\\A_SIGNED"), c2->parameters.at("\\B_SIGNED")); modified_src_cells = true; @@ -323,9 +323,9 @@ struct ShareWorker { RTLIL::Cell *unsigned_cell = c1->parameters.at("\\A_SIGNED").as_bool() ? c2 : c1; - if (unsigned_cell->connections_.at("\\A").to_sigbit_vector().back() != RTLIL::State::S0) { + if (unsigned_cell->get("\\A").to_sigbit_vector().back() != RTLIL::State::S0) { unsigned_cell->parameters.at("\\A_WIDTH") = unsigned_cell->parameters.at("\\A_WIDTH").as_int() + 1; - unsigned_cell->connections_.at("\\A").append_bit(RTLIL::State::S0); + unsigned_cell->get("\\A").append_bit(RTLIL::State::S0); } unsigned_cell->parameters.at("\\A_SIGNED") = true; modified_src_cells = true; @@ -334,9 +334,9 @@ struct ShareWorker if (c1->parameters.at("\\B_SIGNED").as_bool() != c2->parameters.at("\\B_SIGNED").as_bool()) { RTLIL::Cell *unsigned_cell = c1->parameters.at("\\B_SIGNED").as_bool() ? c2 : c1; - if (unsigned_cell->connections_.at("\\B").to_sigbit_vector().back() != RTLIL::State::S0) { + if (unsigned_cell->get("\\B").to_sigbit_vector().back() != RTLIL::State::S0) { unsigned_cell->parameters.at("\\B_WIDTH") = unsigned_cell->parameters.at("\\B_WIDTH").as_int() + 1; - unsigned_cell->connections_.at("\\B").append_bit(RTLIL::State::S0); + unsigned_cell->get("\\B").append_bit(RTLIL::State::S0); } unsigned_cell->parameters.at("\\B_SIGNED") = true; modified_src_cells = true; @@ -356,13 +356,13 @@ struct ShareWorker if (c1->type == "$shl" || c1->type == "$shr" || c1->type == "$sshl" || c1->type == "$sshr") b_signed = false; - RTLIL::SigSpec a1 = c1->connections_.at("\\A"); - RTLIL::SigSpec b1 = c1->connections_.at("\\B"); - RTLIL::SigSpec y1 = c1->connections_.at("\\Y"); + RTLIL::SigSpec a1 = c1->get("\\A"); + RTLIL::SigSpec b1 = c1->get("\\B"); + RTLIL::SigSpec y1 = c1->get("\\Y"); - RTLIL::SigSpec a2 = c2->connections_.at("\\A"); - RTLIL::SigSpec b2 = c2->connections_.at("\\B"); - RTLIL::SigSpec y2 = c2->connections_.at("\\Y"); + RTLIL::SigSpec a2 = c2->get("\\A"); + RTLIL::SigSpec b2 = c2->get("\\B"); + RTLIL::SigSpec y2 = c2->get("\\Y"); int a_width = std::max(a1.size(), a2.size()); int b_width = std::max(b1.size(), b2.size()); @@ -372,20 +372,20 @@ struct ShareWorker { a_width = std::max(y_width, a_width); - if (a1.size() < y1.size()) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, y1.size()), true)->connections_.at("\\Y"); - if (a2.size() < y2.size()) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, y2.size()), true)->connections_.at("\\Y"); + if (a1.size() < y1.size()) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, y1.size()), true)->get("\\Y"); + if (a2.size() < y2.size()) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, y2.size()), true)->get("\\Y"); - if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), false)->connections_.at("\\Y"); - if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), false)->connections_.at("\\Y"); + if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), false)->get("\\Y"); + if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), false)->get("\\Y"); } else { - if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->connections_.at("\\Y"); - if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->connections_.at("\\Y"); + if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->get("\\Y"); + if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->get("\\Y"); } - if (b1.size() != b_width) b1 = module->addPos(NEW_ID, b1, module->addWire(NEW_ID, b_width), b_signed)->connections_.at("\\Y"); - if (b2.size() != b_width) b2 = module->addPos(NEW_ID, b2, module->addWire(NEW_ID, b_width), b_signed)->connections_.at("\\Y"); + if (b1.size() != b_width) b1 = module->addPos(NEW_ID, b1, module->addWire(NEW_ID, b_width), b_signed)->get("\\Y"); + if (b2.size() != b_width) b2 = module->addPos(NEW_ID, b2, module->addWire(NEW_ID, b_width), b_signed)->get("\\Y"); RTLIL::SigSpec a = module->Mux(NEW_ID, a2, a1, act); RTLIL::SigSpec b = module->Mux(NEW_ID, b2, b1, act); @@ -397,16 +397,16 @@ struct ShareWorker supercell->parameters["\\A_WIDTH"] = a_width; supercell->parameters["\\B_WIDTH"] = b_width; supercell->parameters["\\Y_WIDTH"] = y_width; - supercell->connections_["\\A"] = a; - supercell->connections_["\\B"] = b; - supercell->connections_["\\Y"] = y; + supercell->set("\\A", a); + supercell->set("\\B", b); + supercell->set("\\Y", y); supercell->check(); RTLIL::SigSpec new_y1(y, 0, y1.size()); RTLIL::SigSpec new_y2(y, 0, y2.size()); - module->connections_.push_back(RTLIL::SigSig(y1, new_y1)); - module->connections_.push_back(RTLIL::SigSig(y2, new_y2)); + module->connect(RTLIL::SigSig(y1, new_y1)); + module->connect(RTLIL::SigSig(y2, new_y2)); return supercell; } @@ -438,7 +438,7 @@ struct ShareWorker for (auto &bit : pbits) { if ((bit.cell->type == "$mux" || bit.cell->type == "$pmux") && bit.port == "\\S") - forbidden_controls_cache[cell].insert(bit.cell->connections_.at("\\S").extract(bit.offset, 1)); + forbidden_controls_cache[cell].insert(bit.cell->get("\\S").extract(bit.offset, 1)); consumer_cells.insert(bit.cell); } @@ -532,9 +532,9 @@ struct ShareWorker std::set used_in_b_parts; int width = c->parameters.at("\\WIDTH").as_int(); - std::vector sig_a = modwalker.sigmap(c->connections_.at("\\A")); - std::vector sig_b = modwalker.sigmap(c->connections_.at("\\B")); - std::vector sig_s = modwalker.sigmap(c->connections_.at("\\S")); + std::vector sig_a = modwalker.sigmap(c->get("\\A")); + std::vector sig_b = modwalker.sigmap(c->get("\\B")); + std::vector sig_s = modwalker.sigmap(c->get("\\S")); for (auto &bit : sig_a) if (cell_out_bits.count(bit)) @@ -572,7 +572,7 @@ struct ShareWorker if (activation_patterns_cache[cell].empty()) { log("%sFound cell that is never activated: %s\n", indent, log_id(cell)); RTLIL::SigSpec cell_outputs = modwalker.cell_outputs[cell]; - module->connections_.push_back(RTLIL::SigSig(cell_outputs, RTLIL::SigSpec(RTLIL::State::Sx, cell_outputs.size()))); + module->connect(RTLIL::SigSig(cell_outputs, RTLIL::SigSpec(RTLIL::State::Sx, cell_outputs.size()))); cells_to_remove.insert(cell); } diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc index ac0064f70..1dce39f69 100644 --- a/passes/techmap/dfflibmap.cc +++ b/passes/techmap/dfflibmap.cc @@ -398,7 +398,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module) { auto cell_type = cell->type; auto cell_name = cell->name; - auto cell_connections = cell->connections_; + auto cell_connections = cell->connections(); module->remove(cell); cell_mapping &cm = cell_mappings[cell_type]; @@ -418,7 +418,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module) } else if (port.second != 0) log_abort(); - new_cell->connections_["\\" + port.first] = sig; + new_cell->connections()["\\" + port.first] = sig; } stats[stringf(" mapped %%d %s cells to %s cells.\n", cell_type.c_str(), new_cell->type.c_str())]++; diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index 5dfcd63d1..0d8f6ab0d 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -125,10 +125,10 @@ namespace RTLIL::Wire *lastHaystackWire = NULL; std::map emptyAttr; - for (auto &conn : needleCell->connections_) + for (auto &conn : needleCell->connections()) { RTLIL::SigSpec needleSig = conn.second; - RTLIL::SigSpec haystackSig = haystackCell->connections_.at(portMapping.at(conn.first)); + RTLIL::SigSpec haystackSig = haystackCell->connections().at(portMapping.at(conn.first)); for (int i = 0; i < std::min(needleSig.size(), haystackSig.size()); i++) { RTLIL::Wire *needleWire = needleSig[i].wire, *haystackWire = haystackSig[i].wire; @@ -186,7 +186,7 @@ namespace { RTLIL::Cell *cell = cell_it.second; if (!sel || sel->selected(mod, cell)) - for (auto &conn : cell->connections_) { + for (auto &conn : cell->connections()) { RTLIL::SigSpec conn_sig = conn.second; sigmap.apply(conn_sig); for (auto &bit : conn_sig) @@ -207,7 +207,7 @@ namespace type = type.substr(1); graph.createNode(cell->name, type, (void*)cell); - for (auto &conn : cell->connections_) + for (auto &conn : cell->connections()) { graph.createPort(cell->name, conn.first, conn.second.size()); @@ -257,7 +257,7 @@ namespace { RTLIL::Cell *cell = cell_it.second; if (sel && !sel->selected(mod, cell)) - for (auto &conn : cell->connections_) + for (auto &conn : cell->connections()) { RTLIL::SigSpec conn_sig = conn.second; sigmap.apply(conn_sig); @@ -305,7 +305,7 @@ namespace if (wire->port_id > 0) { for (int i = 0; i < wire->width; i++) sig2port.insert(sigmap(RTLIL::SigSpec(wire, i)), std::pair(wire->name, i)); - cell->connections_[wire->name] = RTLIL::SigSpec(RTLIL::State::Sz, wire->width); + cell->connections()[wire->name] = RTLIL::SigSpec(RTLIL::State::Sz, wire->width); } } @@ -319,13 +319,13 @@ namespace if (needle_cell == NULL) continue; - for (auto &conn : needle_cell->connections_) { + for (auto &conn : needle_cell->connections()) { RTLIL::SigSpec sig = sigmap(conn.second); if (mapping.portMapping.count(conn.first) > 0 && sig2port.has(sigmap(sig))) { for (int i = 0; i < sig.size(); i++) for (auto &port : sig2port.find(sig[i])) { - RTLIL::SigSpec bitsig = haystack_cell->connections_.at(mapping.portMapping[conn.first]).extract(i, 1); - cell->connections_.at(port.first).replace(port.second, bitsig); + RTLIL::SigSpec bitsig = haystack_cell->connections().at(mapping.portMapping[conn.first]).extract(i, 1); + cell->connections().at(port.first).replace(port.second, bitsig); } } } @@ -714,7 +714,7 @@ struct ExtractPass : public Pass { cells.insert((RTLIL::Cell*)node.userData); for (auto cell : cells) - for (auto &conn : cell->connections_) { + for (auto &conn : cell->connections()) { RTLIL::SigSpec sig = sigmap(conn.second); for (auto &chunk : sig.chunks()) if (chunk.wire != NULL) @@ -739,12 +739,12 @@ struct ExtractPass : public Pass { for (auto cell : cells) { RTLIL::Cell *newCell = newMod->addCell(cell->name, cell->type); newCell->parameters = cell->parameters; - for (auto &conn : cell->connections_) { + for (auto &conn : cell->connections()) { std::vector chunks = sigmap(conn.second); for (auto &chunk : chunks) if (chunk.wire != NULL) chunk.wire = newMod->wires.at(chunk.wire->name); - newCell->connections_[conn.first] = chunks; + newCell->connections()[conn.first] = chunks; } } } diff --git a/passes/techmap/hilomap.cc b/passes/techmap/hilomap.cc index 286ad8ac0..2e5dd7dca 100644 --- a/passes/techmap/hilomap.cc +++ b/passes/techmap/hilomap.cc @@ -35,7 +35,7 @@ void hilomap_worker(RTLIL::SigSpec &sig) if (!singleton_mode || last_hi == RTLIL::State::Sm) { last_hi = module->addWire(NEW_ID); RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(hicell_celltype)); - cell->connections_[RTLIL::escape_id(hicell_portname)] = last_hi; + cell->connections()[RTLIL::escape_id(hicell_portname)] = last_hi; } bit = last_hi; } @@ -43,7 +43,7 @@ void hilomap_worker(RTLIL::SigSpec &sig) if (!singleton_mode || last_lo == RTLIL::State::Sm) { last_lo = module->addWire(NEW_ID); RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(locell_celltype)); - cell->connections_[RTLIL::escape_id(locell_portname)] = last_lo; + cell->connections()[RTLIL::escape_id(locell_portname)] = last_lo; } bit = last_lo; } diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc index ba9bf51d3..199fd6029 100644 --- a/passes/techmap/iopadmap.cc +++ b/passes/techmap/iopadmap.cc @@ -177,9 +177,9 @@ struct IopadmapPass : public Pass { for (int i = 0; i < wire->width; i++) { RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype)); - cell->connections_[RTLIL::escape_id(portname)] = RTLIL::SigSpec(wire, i); + cell->connections()[RTLIL::escape_id(portname)] = RTLIL::SigSpec(wire, i); if (!portname2.empty()) - cell->connections_[RTLIL::escape_id(portname2)] = RTLIL::SigSpec(new_wire, i); + cell->connections()[RTLIL::escape_id(portname2)] = RTLIL::SigSpec(new_wire, i); if (!widthparam.empty()) cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(1); if (!nameparam.empty()) @@ -190,9 +190,9 @@ struct IopadmapPass : public Pass { else { RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype)); - cell->connections_[RTLIL::escape_id(portname)] = RTLIL::SigSpec(wire); + cell->connections()[RTLIL::escape_id(portname)] = RTLIL::SigSpec(wire); if (!portname2.empty()) - cell->connections_[RTLIL::escape_id(portname2)] = RTLIL::SigSpec(new_wire); + cell->connections()[RTLIL::escape_id(portname2)] = RTLIL::SigSpec(new_wire); if (!widthparam.empty()) cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(wire->width); if (!nameparam.empty()) diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc index df7592cef..f8851400f 100644 --- a/passes/techmap/simplemap.cc +++ b/passes/techmap/simplemap.cc @@ -29,43 +29,43 @@ extern void simplemap_get_mappers(std::mapconnections_.at("\\A"); - RTLIL::SigSpec sig_y = cell->connections_.at("\\Y"); + RTLIL::SigSpec sig_a = cell->get("\\A"); + RTLIL::SigSpec sig_y = cell->get("\\Y"); sig_a.extend(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool()); for (int i = 0; i < SIZE(sig_y); i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, "$_INV_"); - gate->connections_["\\A"] = sig_a[i]; - gate->connections_["\\Y"] = sig_y[i]; + gate->set("\\A", sig_a[i]); + gate->set("\\Y", sig_y[i]); } } static void simplemap_pos(RTLIL::Module *module, RTLIL::Cell *cell) { - RTLIL::SigSpec sig_a = cell->connections_.at("\\A"); - RTLIL::SigSpec sig_y = cell->connections_.at("\\Y"); + RTLIL::SigSpec sig_a = cell->get("\\A"); + RTLIL::SigSpec sig_y = cell->get("\\Y"); sig_a.extend(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool()); - module->connections_.push_back(RTLIL::SigSig(sig_y, sig_a)); + module->connect(RTLIL::SigSig(sig_y, sig_a)); } static void simplemap_bu0(RTLIL::Module *module, RTLIL::Cell *cell) { - RTLIL::SigSpec sig_a = cell->connections_.at("\\A"); - RTLIL::SigSpec sig_y = cell->connections_.at("\\Y"); + RTLIL::SigSpec sig_a = cell->get("\\A"); + RTLIL::SigSpec sig_y = cell->get("\\Y"); sig_a.extend_u0(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool()); - module->connections_.push_back(RTLIL::SigSig(sig_y, sig_a)); + module->connect(RTLIL::SigSig(sig_y, sig_a)); } static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell) { - RTLIL::SigSpec sig_a = cell->connections_.at("\\A"); - RTLIL::SigSpec sig_b = cell->connections_.at("\\B"); - RTLIL::SigSpec sig_y = cell->connections_.at("\\Y"); + RTLIL::SigSpec sig_a = cell->get("\\A"); + RTLIL::SigSpec sig_b = cell->get("\\B"); + RTLIL::SigSpec sig_y = cell->get("\\Y"); sig_a.extend_u0(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool()); sig_b.extend_u0(SIZE(sig_y), cell->parameters.at("\\B_SIGNED").as_bool()); @@ -76,8 +76,8 @@ static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell) for (int i = 0; i < SIZE(sig_y); i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, "$_INV_"); - gate->connections_["\\A"] = sig_t[i]; - gate->connections_["\\Y"] = sig_y[i]; + gate->set("\\A", sig_t[i]); + gate->set("\\Y", sig_y[i]); } sig_y = sig_t; @@ -92,31 +92,31 @@ static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell) for (int i = 0; i < SIZE(sig_y); i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); - gate->connections_["\\A"] = sig_a[i]; - gate->connections_["\\B"] = sig_b[i]; - gate->connections_["\\Y"] = sig_y[i]; + gate->set("\\A", sig_a[i]); + gate->set("\\B", sig_b[i]); + gate->set("\\Y", sig_y[i]); } } static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) { - RTLIL::SigSpec sig_a = cell->connections_.at("\\A"); - RTLIL::SigSpec sig_y = cell->connections_.at("\\Y"); + RTLIL::SigSpec sig_a = cell->get("\\A"); + RTLIL::SigSpec sig_y = cell->get("\\Y"); if (sig_y.size() == 0) return; if (sig_a.size() == 0) { - if (cell->type == "$reduce_and") module->connections_.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size()))); - if (cell->type == "$reduce_or") module->connections_.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size()))); - if (cell->type == "$reduce_xor") module->connections_.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size()))); - if (cell->type == "$reduce_xnor") module->connections_.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size()))); - if (cell->type == "$reduce_bool") module->connections_.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size()))); + if (cell->type == "$reduce_and") module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size()))); + if (cell->type == "$reduce_or") module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size()))); + if (cell->type == "$reduce_xor") module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size()))); + if (cell->type == "$reduce_xnor") module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size()))); + if (cell->type == "$reduce_bool") module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size()))); return; } if (sig_y.size() > 1) { - module->connections_.push_back(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1))); + module->connect(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1))); sig_y = sig_y.extract(0, 1); } @@ -142,10 +142,10 @@ static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) } RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); - gate->connections_["\\A"] = sig_a[i]; - gate->connections_["\\B"] = sig_a[i+1]; - gate->connections_["\\Y"] = sig_t[i/2]; - last_output = &gate->connections_["\\Y"]; + gate->set("\\A", sig_a[i]); + gate->set("\\B", sig_a[i+1]); + gate->set("\\Y", sig_t[i/2]); + last_output = &gate->get("\\Y"); } sig_a = sig_t; @@ -154,14 +154,14 @@ static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) if (cell->type == "$reduce_xnor") { RTLIL::SigSpec sig_t = module->addWire(NEW_ID); RTLIL::Cell *gate = module->addCell(NEW_ID, "$_INV_"); - gate->connections_["\\A"] = sig_a; - gate->connections_["\\Y"] = sig_t; - last_output = &gate->connections_["\\Y"]; + gate->set("\\A", sig_a); + gate->set("\\Y", sig_t); + last_output = &gate->get("\\Y"); sig_a = sig_t; } if (last_output == NULL) { - module->connections_.push_back(RTLIL::SigSig(sig_y, sig_a)); + module->connect(RTLIL::SigSig(sig_y, sig_a)); } else { *last_output = sig_y; } @@ -181,9 +181,9 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig) } RTLIL::Cell *gate = module->addCell(NEW_ID, "$_OR_"); - gate->connections_["\\A"] = sig[i]; - gate->connections_["\\B"] = sig[i+1]; - gate->connections_["\\Y"] = sig_t[i/2]; + gate->set("\\A", sig[i]); + gate->set("\\B", sig[i+1]); + gate->set("\\Y", sig_t[i/2]); } sig = sig_t; @@ -195,39 +195,39 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig) static void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell) { - RTLIL::SigSpec sig_a = cell->connections_.at("\\A"); + RTLIL::SigSpec sig_a = cell->get("\\A"); logic_reduce(module, sig_a); - RTLIL::SigSpec sig_y = cell->connections_.at("\\Y"); + RTLIL::SigSpec sig_y = cell->get("\\Y"); if (sig_y.size() == 0) return; if (sig_y.size() > 1) { - module->connections_.push_back(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1))); + module->connect(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1))); sig_y = sig_y.extract(0, 1); } RTLIL::Cell *gate = module->addCell(NEW_ID, "$_INV_"); - gate->connections_["\\A"] = sig_a; - gate->connections_["\\Y"] = sig_y; + gate->set("\\A", sig_a); + gate->set("\\Y", sig_y); } static void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell) { - RTLIL::SigSpec sig_a = cell->connections_.at("\\A"); + RTLIL::SigSpec sig_a = cell->get("\\A"); logic_reduce(module, sig_a); - RTLIL::SigSpec sig_b = cell->connections_.at("\\B"); + RTLIL::SigSpec sig_b = cell->get("\\B"); logic_reduce(module, sig_b); - RTLIL::SigSpec sig_y = cell->connections_.at("\\Y"); + RTLIL::SigSpec sig_y = cell->get("\\Y"); if (sig_y.size() == 0) return; if (sig_y.size() > 1) { - module->connections_.push_back(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1))); + module->connect(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1))); sig_y = sig_y.extract(0, 1); } @@ -237,40 +237,40 @@ static void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell) log_assert(!gate_type.empty()); RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); - gate->connections_["\\A"] = sig_a; - gate->connections_["\\B"] = sig_b; - gate->connections_["\\Y"] = sig_y; + gate->set("\\A", sig_a); + gate->set("\\B", sig_b); + gate->set("\\Y", sig_y); } static void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell) { - RTLIL::SigSpec sig_a = cell->connections_.at("\\A"); - RTLIL::SigSpec sig_b = cell->connections_.at("\\B"); - RTLIL::SigSpec sig_y = cell->connections_.at("\\Y"); + RTLIL::SigSpec sig_a = cell->get("\\A"); + RTLIL::SigSpec sig_b = cell->get("\\B"); + RTLIL::SigSpec sig_y = cell->get("\\Y"); for (int i = 0; i < SIZE(sig_y); i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, "$_MUX_"); - gate->connections_["\\A"] = sig_a[i]; - gate->connections_["\\B"] = sig_b[i]; - gate->connections_["\\S"] = cell->connections_.at("\\S"); - gate->connections_["\\Y"] = sig_y[i]; + gate->set("\\A", sig_a[i]); + gate->set("\\B", sig_b[i]); + gate->set("\\S", cell->get("\\S")); + gate->set("\\Y", sig_y[i]); } } static void simplemap_slice(RTLIL::Module *module, RTLIL::Cell *cell) { int offset = cell->parameters.at("\\OFFSET").as_int(); - RTLIL::SigSpec sig_a = cell->connections_.at("\\A"); - RTLIL::SigSpec sig_y = cell->connections_.at("\\Y"); - module->connections_.push_back(RTLIL::SigSig(sig_y, sig_a.extract(offset, sig_y.size()))); + RTLIL::SigSpec sig_a = cell->get("\\A"); + RTLIL::SigSpec sig_y = cell->get("\\Y"); + module->connect(RTLIL::SigSig(sig_y, sig_a.extract(offset, sig_y.size()))); } static void simplemap_concat(RTLIL::Module *module, RTLIL::Cell *cell) { - RTLIL::SigSpec sig_ab = cell->connections_.at("\\A"); - sig_ab.append(cell->connections_.at("\\B")); - RTLIL::SigSpec sig_y = cell->connections_.at("\\Y"); - module->connections_.push_back(RTLIL::SigSig(sig_y, sig_ab)); + RTLIL::SigSpec sig_ab = cell->get("\\A"); + sig_ab.append(cell->get("\\B")); + RTLIL::SigSpec sig_y = cell->get("\\Y"); + module->connect(RTLIL::SigSig(sig_y, sig_ab)); } static void simplemap_sr(RTLIL::Module *module, RTLIL::Cell *cell) @@ -279,17 +279,17 @@ static void simplemap_sr(RTLIL::Module *module, RTLIL::Cell *cell) char set_pol = cell->parameters.at("\\SET_POLARITY").as_bool() ? 'P' : 'N'; char clr_pol = cell->parameters.at("\\CLR_POLARITY").as_bool() ? 'P' : 'N'; - RTLIL::SigSpec sig_s = cell->connections_.at("\\SET"); - RTLIL::SigSpec sig_r = cell->connections_.at("\\CLR"); - RTLIL::SigSpec sig_q = cell->connections_.at("\\Q"); + RTLIL::SigSpec sig_s = cell->get("\\SET"); + RTLIL::SigSpec sig_r = cell->get("\\CLR"); + RTLIL::SigSpec sig_q = cell->get("\\Q"); std::string gate_type = stringf("$_SR_%c%c_", set_pol, clr_pol); for (int i = 0; i < width; i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); - gate->connections_["\\S"] = sig_s[i]; - gate->connections_["\\R"] = sig_r[i]; - gate->connections_["\\Q"] = sig_q[i]; + gate->set("\\S", sig_s[i]); + gate->set("\\R", sig_r[i]); + gate->set("\\Q", sig_q[i]); } } @@ -298,17 +298,17 @@ static void simplemap_dff(RTLIL::Module *module, RTLIL::Cell *cell) int width = cell->parameters.at("\\WIDTH").as_int(); char clk_pol = cell->parameters.at("\\CLK_POLARITY").as_bool() ? 'P' : 'N'; - RTLIL::SigSpec sig_clk = cell->connections_.at("\\CLK"); - RTLIL::SigSpec sig_d = cell->connections_.at("\\D"); - RTLIL::SigSpec sig_q = cell->connections_.at("\\Q"); + RTLIL::SigSpec sig_clk = cell->get("\\CLK"); + RTLIL::SigSpec sig_d = cell->get("\\D"); + RTLIL::SigSpec sig_q = cell->get("\\Q"); std::string gate_type = stringf("$_DFF_%c_", clk_pol); for (int i = 0; i < width; i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); - gate->connections_["\\C"] = sig_clk; - gate->connections_["\\D"] = sig_d[i]; - gate->connections_["\\Q"] = sig_q[i]; + gate->set("\\C", sig_clk); + gate->set("\\D", sig_d[i]); + gate->set("\\Q", sig_q[i]); } } @@ -319,21 +319,21 @@ static void simplemap_dffsr(RTLIL::Module *module, RTLIL::Cell *cell) char set_pol = cell->parameters.at("\\SET_POLARITY").as_bool() ? 'P' : 'N'; char clr_pol = cell->parameters.at("\\CLR_POLARITY").as_bool() ? 'P' : 'N'; - RTLIL::SigSpec sig_clk = cell->connections_.at("\\CLK"); - RTLIL::SigSpec sig_s = cell->connections_.at("\\SET"); - RTLIL::SigSpec sig_r = cell->connections_.at("\\CLR"); - RTLIL::SigSpec sig_d = cell->connections_.at("\\D"); - RTLIL::SigSpec sig_q = cell->connections_.at("\\Q"); + RTLIL::SigSpec sig_clk = cell->get("\\CLK"); + RTLIL::SigSpec sig_s = cell->get("\\SET"); + RTLIL::SigSpec sig_r = cell->get("\\CLR"); + RTLIL::SigSpec sig_d = cell->get("\\D"); + RTLIL::SigSpec sig_q = cell->get("\\Q"); std::string gate_type = stringf("$_DFFSR_%c%c%c_", clk_pol, set_pol, clr_pol); for (int i = 0; i < width; i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); - gate->connections_["\\C"] = sig_clk; - gate->connections_["\\S"] = sig_s[i]; - gate->connections_["\\R"] = sig_r[i]; - gate->connections_["\\D"] = sig_d[i]; - gate->connections_["\\Q"] = sig_q[i]; + gate->set("\\C", sig_clk); + gate->set("\\S", sig_s[i]); + gate->set("\\R", sig_r[i]); + gate->set("\\D", sig_d[i]); + gate->set("\\Q", sig_q[i]); } } @@ -347,20 +347,20 @@ static void simplemap_adff(RTLIL::Module *module, RTLIL::Cell *cell) while (int(rst_val.size()) < width) rst_val.push_back(RTLIL::State::S0); - RTLIL::SigSpec sig_clk = cell->connections_.at("\\CLK"); - RTLIL::SigSpec sig_rst = cell->connections_.at("\\ARST"); - RTLIL::SigSpec sig_d = cell->connections_.at("\\D"); - RTLIL::SigSpec sig_q = cell->connections_.at("\\Q"); + RTLIL::SigSpec sig_clk = cell->get("\\CLK"); + RTLIL::SigSpec sig_rst = cell->get("\\ARST"); + RTLIL::SigSpec sig_d = cell->get("\\D"); + RTLIL::SigSpec sig_q = cell->get("\\Q"); std::string gate_type_0 = stringf("$_DFF_%c%c0_", clk_pol, rst_pol); std::string gate_type_1 = stringf("$_DFF_%c%c1_", clk_pol, rst_pol); for (int i = 0; i < width; i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, rst_val.at(i) == RTLIL::State::S1 ? gate_type_1 : gate_type_0); - gate->connections_["\\C"] = sig_clk; - gate->connections_["\\R"] = sig_rst; - gate->connections_["\\D"] = sig_d[i]; - gate->connections_["\\Q"] = sig_q[i]; + gate->set("\\C", sig_clk); + gate->set("\\R", sig_rst); + gate->set("\\D", sig_d[i]); + gate->set("\\Q", sig_q[i]); } } @@ -369,17 +369,17 @@ static void simplemap_dlatch(RTLIL::Module *module, RTLIL::Cell *cell) int width = cell->parameters.at("\\WIDTH").as_int(); char en_pol = cell->parameters.at("\\EN_POLARITY").as_bool() ? 'P' : 'N'; - RTLIL::SigSpec sig_en = cell->connections_.at("\\EN"); - RTLIL::SigSpec sig_d = cell->connections_.at("\\D"); - RTLIL::SigSpec sig_q = cell->connections_.at("\\Q"); + RTLIL::SigSpec sig_en = cell->get("\\EN"); + RTLIL::SigSpec sig_d = cell->get("\\D"); + RTLIL::SigSpec sig_q = cell->get("\\Q"); std::string gate_type = stringf("$_DLATCH_%c_", en_pol); for (int i = 0; i < width; i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); - gate->connections_["\\E"] = sig_en; - gate->connections_["\\D"] = sig_d[i]; - gate->connections_["\\Q"] = sig_q[i]; + gate->set("\\E", sig_en); + gate->set("\\D", sig_d[i]); + gate->set("\\Q", sig_q[i]); } } diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index ab95c003a..4c8f92505 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -141,7 +141,7 @@ struct TechmapWorker SigMap port_signal_map; - for (auto &it : cell->connections_) { + for (auto &it : cell->connections()) { RTLIL::IdString portname = it.first; if (positional_ports.count(portname) > 0) portname = positional_ports.at(portname); @@ -169,7 +169,7 @@ struct TechmapWorker if (flatten_mode) { // more conservative approach: // connect internal and external wires - module->connections_.push_back(c); + module->connect(c); } else { // approach that yields nicer outputs: // replace internal wires that are connected to external wires @@ -195,19 +195,19 @@ struct TechmapWorker if (!flatten_mode && c->type.substr(0, 2) == "\\$") c->type = c->type.substr(1); - for (auto &it2 : c->connections_) { + for (auto &it2 : c->connections()) { apply_prefix(cell->name, it2.second, module); port_signal_map.apply(it2.second); } } - for (auto &it : tpl->connections_) { + for (auto &it : tpl->connections()) { RTLIL::SigSig c = it; apply_prefix(cell->name, c.first, module); apply_prefix(cell->name, c.second, module); port_signal_map.apply(c.first); port_signal_map.apply(c.second); - module->connections_.push_back(c); + module->connect(c); } module->remove(cell); @@ -262,7 +262,7 @@ struct TechmapWorker break; } - for (auto conn : cell->connections_) { + for (auto conn : cell->connections()) { if (conn.first.substr(0, 1) == "$") continue; if (tpl->wires.count(conn.first) > 0 && tpl->wires.at(conn.first)->port_id > 0) @@ -280,7 +280,7 @@ struct TechmapWorker if (tpl->avail_parameters.count("\\_TECHMAP_CELLTYPE_") != 0) parameters["\\_TECHMAP_CELLTYPE_"] = RTLIL::unescape_id(cell->type); - for (auto conn : cell->connections_) { + for (auto conn : cell->connections()) { if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", RTLIL::id2cstr(conn.first))) != 0) { std::vector v = sigmap(conn.second).to_sigbit_vector(); for (auto &bit : v) @@ -303,7 +303,7 @@ struct TechmapWorker unique_bit_id[RTLIL::State::Sx] = unique_bit_id_counter++; unique_bit_id[RTLIL::State::Sz] = unique_bit_id_counter++; - for (auto conn : cell->connections_) + for (auto conn : cell->connections()) if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))) != 0) { for (auto &bit : sigmap(conn.second).to_sigbit_vector()) if (unique_bit_id.count(bit) == 0) @@ -317,7 +317,7 @@ struct TechmapWorker if (tpl->avail_parameters.count("\\_TECHMAP_BITS_CONNMAP_")) parameters["\\_TECHMAP_BITS_CONNMAP_"] = bits; - for (auto conn : cell->connections_) + for (auto conn : cell->connections()) if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))) != 0) { RTLIL::Const value; for (auto &bit : sigmap(conn.second).to_sigbit_vector()) { -- cgit v1.2.3 From f8fdc47d3361c1a3445a9357ca26cfe75907d6b0 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 26 Jul 2014 15:57:57 +0200 Subject: Manual fixes for new cell connections API --- passes/abc/abc.cc | 2 +- passes/abc/blifparse.cc | 2 +- passes/cmds/add.cc | 2 +- passes/cmds/connect.cc | 6 +++--- passes/cmds/connwrappers.cc | 2 +- passes/cmds/scatter.cc | 2 +- passes/cmds/show.cc | 6 +++--- passes/cmds/splice.cc | 2 +- passes/fsm/fsm_expand.cc | 8 ++++++-- passes/fsm/fsm_extract.cc | 4 ++-- passes/fsm/fsm_opt.cc | 14 +++++++++----- passes/hierarchy/hierarchy.cc | 4 ++-- passes/hierarchy/submod.cc | 6 +++--- passes/memory/memory_dff.cc | 11 +++++++---- passes/memory/memory_share.cc | 35 ++++++++++++++++++++++------------- passes/opt/opt_clean.cc | 4 ++-- passes/opt/opt_const.cc | 36 +++++++++++++++++++----------------- passes/opt/opt_reduce.cc | 14 ++++++++++---- passes/opt/opt_share.cc | 2 +- passes/proc/proc_dff.cc | 8 ++++---- passes/proc/proc_mux.cc | 11 +++++++++-- passes/sat/expose.cc | 6 +++--- passes/sat/freduce.cc | 2 +- passes/sat/miter.cc | 8 ++++---- passes/sat/share.cc | 17 +++++++++++++---- passes/techmap/dfflibmap.cc | 2 +- passes/techmap/extract.cc | 8 +++++--- passes/techmap/hilomap.cc | 4 ++-- passes/techmap/iopadmap.cc | 8 ++++---- passes/techmap/simplemap.cc | 10 +++++----- passes/techmap/techmap.cc | 2 +- 31 files changed, 147 insertions(+), 101 deletions(-) (limited to 'passes') diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index c53c44503..4d9a6c136 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -785,7 +785,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std assert(c.width == 1); newsig.append(module->wires[remap_name(c.wire->name)]); } - cell->connections()[conn.first] = newsig; + cell->set(conn.first, newsig); } design->select(module, cell); } diff --git a/passes/abc/blifparse.cc b/passes/abc/blifparse.cc index e5bfb98b4..45a9ac765 100644 --- a/passes/abc/blifparse.cc +++ b/passes/abc/blifparse.cc @@ -148,7 +148,7 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name) *(q++) = 0; if (module->wires.count(RTLIL::escape_id(q)) == 0) module->addWire(RTLIL::escape_id(q)); - cell->connections()[RTLIL::escape_id(p)] = module->wires.at(RTLIL::escape_id(q)); + cell->set(RTLIL::escape_id(p), module->wires.at(RTLIL::escape_id(q))); } continue; } diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc index 9004bf75b..1401193fd 100644 --- a/passes/cmds/add.cc +++ b/passes/cmds/add.cc @@ -78,7 +78,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n if (it.second->connections().count(name) > 0) continue; - it.second->connections()[name] = wire; + it.second->set(name, wire); log("Added connection %s to cell %s.%s (%s).\n", name.c_str(), module->name.c_str(), it.first.c_str(), it.second->type.c_str()); } } diff --git a/passes/cmds/connect.cc b/passes/cmds/connect.cc index ffe7a5efa..99a28d4a0 100644 --- a/passes/cmds/connect.cc +++ b/passes/cmds/connect.cc @@ -30,11 +30,11 @@ static void unset_drivers(RTLIL::Design *design, RTLIL::Module *module, SigMap & RTLIL::Wire *dummy_wire = module->addWire(NEW_ID, sig.size()); for (auto &it : module->cells) - for (auto &port : it.second->connections()) + for (auto &port : it.second->connections_) if (ct.cell_output(it.second->type, port.first)) sigmap(port.second).replace(sig, dummy_wire, &port.second); - for (auto &conn : module->connections()) + for (auto &conn : module->connections_) sigmap(conn.first).replace(sig, dummy_wire, &conn.first); } @@ -176,7 +176,7 @@ struct ConnectPass : public Pass { if (!RTLIL::SigSpec::parse_sel(sig, design, module, port_expr)) log_cmd_error("Failed to parse port expression `%s'.\n", port_expr.c_str()); - module->cells.at(RTLIL::escape_id(port_cell))->connections()[RTLIL::escape_id(port_port)] = sigmap(sig); + module->cells.at(RTLIL::escape_id(port_cell))->set(RTLIL::escape_id(port_port), sigmap(sig)); } else log_cmd_error("Expected -set, -unset, or -port.\n"); diff --git a/passes/cmds/connwrappers.cc b/passes/cmds/connwrappers.cc index d7560ab1a..9faeffafa 100644 --- a/passes/cmds/connwrappers.cc +++ b/passes/cmds/connwrappers.cc @@ -109,7 +109,7 @@ struct ConnwrappersWorker if (!design->selected(module, cell)) continue; - for (auto &conn : cell->connections()) + for (auto &conn : cell->connections_) { std::vector sigbits = sigmap(conn.second).to_sigbit_vector(); RTLIL::SigSpec old_sig; diff --git a/passes/cmds/scatter.cc b/passes/cmds/scatter.cc index 1a780466a..35ce0a110 100644 --- a/passes/cmds/scatter.cc +++ b/passes/cmds/scatter.cc @@ -49,7 +49,7 @@ struct ScatterPass : public Pass { continue; for (auto &c : mod_it.second->cells) - for (auto &p : c.second->connections()) + for (auto &p : c.second->connections_) { RTLIL::Wire *wire = new RTLIL::Wire; wire->name = NEW_ID; diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index 441268ee9..d63d98972 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -87,17 +87,17 @@ struct ShowWorker return defaultColor; } - std::string nextColor(RTLIL::SigSig &conn, std::string defaultColor) + std::string nextColor(const RTLIL::SigSig &conn, std::string defaultColor) { return nextColor(conn.first, nextColor(conn.second, defaultColor)); } - std::string nextColor(RTLIL::SigSpec &sig) + std::string nextColor(const RTLIL::SigSpec &sig) { return nextColor(sig, nextColor()); } - std::string nextColor(RTLIL::SigSig &conn) + std::string nextColor(const RTLIL::SigSig &conn) { return nextColor(conn, nextColor()); } diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc index 94f8365bc..8b7e04062 100644 --- a/passes/cmds/splice.cc +++ b/passes/cmds/splice.cc @@ -182,7 +182,7 @@ struct SpliceWorker for (auto &it : module->cells) { if (!sel_by_wire && !design->selected(module, it.second)) continue; - for (auto &conn : it.second->connections()) + for (auto &conn : it.second->connections_) if (ct.cell_input(it.second->type, conn.first)) { if (ports.size() > 0 && !ports.count(conn.first)) continue; diff --git a/passes/fsm/fsm_expand.cc b/passes/fsm/fsm_expand.cc index 126c4866a..ed80d7c31 100644 --- a/passes/fsm/fsm_expand.cc +++ b/passes/fsm/fsm_expand.cc @@ -167,10 +167,14 @@ struct FsmExpand fsm_data.copy_from_cell(fsm_cell); fsm_data.num_inputs += input_sig.size(); - fsm_cell->get("\\CTRL_IN").append(input_sig); + RTLIL::SigSpec new_ctrl_in = fsm_cell->get("\\CTRL_IN"); + new_ctrl_in.append(input_sig); + fsm_cell->set("\\CTRL_IN", new_ctrl_in); fsm_data.num_outputs += output_sig.size(); - fsm_cell->get("\\CTRL_OUT").append(output_sig); + RTLIL::SigSpec new_ctrl_out = fsm_cell->get("\\CTRL_OUT"); + new_ctrl_out.append(output_sig); + fsm_cell->set("\\CTRL_OUT", new_ctrl_out); std::vector new_transition_table; for (auto &tr : fsm_data.transition_table) { diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index 3ded8aca7..e89bba893 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -294,13 +294,13 @@ static void extract_fsm(RTLIL::Wire *wire) sig2driver.find(ctrl_out, cellport_list); for (auto &cellport : cellport_list) { RTLIL::Cell *cell = module->cells.at(cellport.first); - RTLIL::SigSpec port_sig = assign_map(cell->connections()[cellport.second]); + RTLIL::SigSpec port_sig = assign_map(cell->get(cellport.second)); RTLIL::SigSpec unconn_sig = port_sig.extract(ctrl_out); RTLIL::Wire *unconn_wire = new RTLIL::Wire; unconn_wire->name = stringf("$fsm_unconnect$%s$%d", log_signal(unconn_sig), RTLIL::autoidx++); unconn_wire->width = unconn_sig.size(); module->wires[unconn_wire->name] = unconn_wire; - port_sig.replace(unconn_sig, RTLIL::SigSpec(unconn_wire), &cell->connections()[cellport.second]); + port_sig.replace(unconn_sig, RTLIL::SigSpec(unconn_wire), &cell->connections_[cellport.second]); } } diff --git a/passes/fsm/fsm_opt.cc b/passes/fsm/fsm_opt.cc index e82b53631..1441378a0 100644 --- a/passes/fsm/fsm_opt.cc +++ b/passes/fsm/fsm_opt.cc @@ -79,7 +79,9 @@ struct FsmOpt tmp.remove(i, 1); tr.ctrl_in = tmp.as_const(); } - cell->get("\\CTRL_IN").remove(i, 1); + RTLIL::SigSpec new_ctrl_in = cell->get("\\CTRL_IN"); + new_ctrl_in.remove(i, 1); + cell->set("\\CTRL_IN", new_ctrl_in); fsm_data.num_inputs--; } } @@ -94,7 +96,9 @@ struct FsmOpt RTLIL::SigSpec sig = cell->get("\\CTRL_OUT").extract(i, 1); if (signal_is_unused(sig)) { log(" Removing unused output signal %s.\n", log_signal(sig)); - cell->get("\\CTRL_OUT").remove(i, 1); + RTLIL::SigSpec new_ctrl_out = cell->get("\\CTRL_OUT"); + new_ctrl_out.remove(i, 1); + cell->set("\\CTRL_OUT", new_ctrl_out); for (auto &tr : fsm_data.transition_table) { RTLIL::SigSpec tmp(tr.ctrl_out); tmp.remove(i, 1); @@ -108,7 +112,7 @@ struct FsmOpt void opt_alias_inputs() { - RTLIL::SigSpec &ctrl_in = cell->get("\\CTRL_IN"); + RTLIL::SigSpec &ctrl_in = cell->connections_["\\CTRL_IN"]; for (int i = 0; i < ctrl_in.size(); i++) for (int j = i+1; j < ctrl_in.size(); j++) @@ -145,8 +149,8 @@ struct FsmOpt void opt_feedback_inputs() { - RTLIL::SigSpec &ctrl_in = cell->get("\\CTRL_IN"); - RTLIL::SigSpec &ctrl_out = cell->get("\\CTRL_OUT"); + RTLIL::SigSpec &ctrl_in = cell->connections_["\\CTRL_IN"]; + RTLIL::SigSpec &ctrl_out = cell->connections_["\\CTRL_OUT"]; for (int j = 0; j < ctrl_out.size(); j++) for (int i = 0; i < ctrl_in.size(); i++) diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 5937373fa..76b667b86 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -219,7 +219,7 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla RTLIL::Module *mod = design->modules[cell->type]; - for (auto &conn : cell->connections()) { + for (auto &conn : cell->connections_) { int conn_size = conn.second.size(); std::string portname = conn.first; if (portname.substr(0, 1) == "$") { @@ -519,7 +519,7 @@ struct HierarchyPass : public Pass { new_connections[pos_map.at(key)] = conn.second; } else new_connections[conn.first] = conn.second; - cell->connections() = new_connections; + cell->connections_ = new_connections; } } diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index d72ebb127..ef4a9f16d 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -65,7 +65,7 @@ struct SubmodWorker flag_found_something = true; } - void flag_signal(RTLIL::SigSpec &sig, bool create, bool set_int_driven, bool set_int_used, bool set_ext_driven, bool set_ext_used) + void flag_signal(const RTLIL::SigSpec &sig, bool create, bool set_int_driven, bool set_int_used, bool set_ext_driven, bool set_ext_used) { for (auto &c : sig.chunks()) if (c.wire != NULL) @@ -163,7 +163,7 @@ struct SubmodWorker for (RTLIL::Cell *cell : submod.cells) { RTLIL::Cell *new_cell = new_mod->addCell(cell->name, cell); - for (auto &conn : new_cell->connections()) + for (auto &conn : new_cell->connections_) for (auto &bit : conn.second) if (bit.wire != NULL) { assert(wire_flags.count(bit.wire) > 0); @@ -180,7 +180,7 @@ struct SubmodWorker RTLIL::Wire *old_wire = it.first; RTLIL::Wire *new_wire = it.second.new_wire; if (new_wire->port_id > 0) - new_cell->connections()[new_wire->name] = RTLIL::SigSpec(old_wire); + new_cell->set(new_wire->name, RTLIL::SigSpec(old_wire)); } } diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index 0513aa3d2..999c969b5 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -52,10 +52,10 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI continue; } - RTLIL::SigSpec q_norm = cell->connections()[after ? "\\D" : "\\Q"]; + RTLIL::SigSpec q_norm = cell->get(after ? "\\D" : "\\Q"); normalize_sig(module, q_norm); - RTLIL::SigSpec d = q_norm.extract(bit, &cell->connections()[after ? "\\Q" : "\\D"]); + RTLIL::SigSpec d = q_norm.extract(bit, &cell->get(after ? "\\Q" : "\\D")); if (d.size() != 1) continue; @@ -127,8 +127,11 @@ static void disconnect_dff(RTLIL::Module *module, RTLIL::SigSpec sig) for (auto &cell_it : module->cells) { RTLIL::Cell *cell = cell_it.second; - if (cell->type == "$dff") - cell->get("\\Q").replace(sig, newsig); + if (cell->type == "$dff") { + RTLIL::SigSpec new_q = cell->get("\\Q"); + new_q.replace(sig, newsig); + cell->set("\\Q", new_q); + } } } diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index 8b4eb0d0e..df1a2697a 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -72,8 +72,11 @@ struct MemoryShareWorker for (int i = 0; i < int(sig_s.size()); i++) if (state.count(sig_s[i]) && state.at(sig_s[i]) == true) { - if (find_data_feedback(async_rd_bits, sig_b.at(bit_idx + i*sig_y.size()), state, conditions)) - cell->get("\\B").replace(bit_idx + i*sig_y.size(), RTLIL::State::Sx); + if (find_data_feedback(async_rd_bits, sig_b.at(bit_idx + i*sig_y.size()), state, conditions)) { + RTLIL::SigSpec new_b = cell->get("\\B"); + new_b.replace(bit_idx + i*sig_y.size(), RTLIL::State::Sx); + cell->set("\\B", new_b); + } return false; } @@ -86,16 +89,22 @@ struct MemoryShareWorker std::map new_state = state; new_state[sig_s[i]] = true; - if (find_data_feedback(async_rd_bits, sig_b.at(bit_idx + i*sig_y.size()), new_state, conditions)) - cell->get("\\B").replace(bit_idx + i*sig_y.size(), RTLIL::State::Sx); + if (find_data_feedback(async_rd_bits, sig_b.at(bit_idx + i*sig_y.size()), new_state, conditions)) { + RTLIL::SigSpec new_b = cell->get("\\B"); + new_b.replace(bit_idx + i*sig_y.size(), RTLIL::State::Sx); + cell->set("\\B", new_b); + } } std::map new_state = state; for (int i = 0; i < int(sig_s.size()); i++) new_state[sig_s[i]] = false; - if (find_data_feedback(async_rd_bits, sig_a.at(bit_idx), new_state, conditions)) - cell->get("\\A").replace(bit_idx, RTLIL::State::Sx); + if (find_data_feedback(async_rd_bits, sig_a.at(bit_idx), new_state, conditions)) { + RTLIL::SigSpec new_a = cell->get("\\A"); + new_a.replace(bit_idx, RTLIL::State::Sx); + cell->set("\\A", new_a); + } return false; } @@ -239,7 +248,7 @@ struct MemoryShareWorker if (created_conditions) { log(" Added enable logic for %d different cases.\n", created_conditions); - cell->get("\\EN") = cell_en; + cell->set("\\EN", cell_en); } } } @@ -399,7 +408,7 @@ struct MemoryShareWorker // Force this ports addr input to addr directly (skip don't care muxes) - cell->get("\\ADDR") = addr; + cell->set("\\ADDR", addr); // If any of the ports between `last_i' and `i' write to the same address, this // will have priority over whatever `last_i` wrote. So we need to revisit those @@ -443,8 +452,8 @@ struct MemoryShareWorker // Connect the new EN and DATA signals and remove the old write port. - cell->get("\\EN") = merged_en; - cell->get("\\DATA") = merged_data; + cell->set("\\EN", merged_en); + cell->set("\\DATA", merged_data); module->remove(wr_ports[last_i]); wr_ports[last_i] = NULL; @@ -595,8 +604,8 @@ struct MemoryShareWorker RTLIL::SigBit this_en_active = module->ReduceOr(NEW_ID, this_en); - wr_ports[i]->get("\\ADDR") = module->Mux(NEW_ID, last_addr, this_addr, this_en_active); - wr_ports[i]->get("\\DATA") = module->Mux(NEW_ID, last_data, this_data, this_en_active); + wr_ports[i]->set("\\ADDR", module->Mux(NEW_ID, last_addr, this_addr, this_en_active)); + wr_ports[i]->set("\\DATA", module->Mux(NEW_ID, last_data, this_data, this_en_active)); std::map, int> groups_en; RTLIL::SigSpec grouped_last_en, grouped_this_en, en; @@ -614,7 +623,7 @@ struct MemoryShareWorker } module->addMux(NEW_ID, grouped_last_en, grouped_this_en, this_en_active, grouped_en); - wr_ports[i]->get("\\EN") = en; + wr_ports[i]->set("\\EN", en); module->remove(wr_ports[i-1]); wr_ports[i-1] = NULL; diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index fa5d8f189..e279c0209 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -189,13 +189,13 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool } } - module->connections().clear(); + module->connections_.clear(); SigPool used_signals; SigPool used_signals_nodrivers; for (auto &it : module->cells) { RTLIL::Cell *cell = it.second; - for (auto &it2 : cell->connections()) { + for (auto &it2 : cell->connections_) { assign_map.apply(it2.second); used_signals.add(it2.second); if (!ct.cell_output(cell->type, it2.first)) diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index 7f420ec34..e52882316 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -73,7 +73,7 @@ static void replace_undriven(RTLIL::Design *design, RTLIL::Module *module) static void replace_cell(RTLIL::Module *module, RTLIL::Cell *cell, std::string info, std::string out_port, RTLIL::SigSpec out_val) { - RTLIL::SigSpec Y = cell->connections()[out_port]; + RTLIL::SigSpec Y = cell->get(out_port); out_val.extend_u0(Y.size(), false); log("Replacing %s cell `%s' (%s) in module `%s' with constant driver `%s = %s'.\n", @@ -240,7 +240,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cover("opt.opt_const.fine.$reduce_and"); log("Replacing port A of %s cell `%s' in module `%s' with constant driver: %s -> %s\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a)); - cell->get("\\A") = sig_a = new_a; + cell->set("\\A", sig_a = new_a); cell->parameters.at("\\A_WIDTH") = 1; OPT_DID_SOMETHING = true; did_something = true; @@ -267,7 +267,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cover_list("opt.opt_const.fine.A", "$logic_not", "$logic_and", "$logic_or", "$reduce_or", "$reduce_bool", cell->type); log("Replacing port A of %s cell `%s' in module `%s' with constant driver: %s -> %s\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a)); - cell->get("\\A") = sig_a = new_a; + cell->set("\\A", sig_a = new_a); cell->parameters.at("\\A_WIDTH") = 1; OPT_DID_SOMETHING = true; did_something = true; @@ -294,7 +294,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cover_list("opt.opt_const.fine.B", "$logic_and", "$logic_or", cell->type); log("Replacing port B of %s cell `%s' in module `%s' with constant driver: %s -> %s\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_b), log_signal(new_b)); - cell->get("\\B") = sig_b = new_b; + cell->set("\\B", sig_b = new_b); cell->parameters.at("\\B_WIDTH") = 1; OPT_DID_SOMETHING = true; did_something = true; @@ -441,8 +441,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cover("opt.opt_const.mux_to_inv"); cell->type = "$_INV_"; cell->set("\\A", input.extract(0, 1)); - cell->connections().erase("\\B"); - cell->connections().erase("\\S"); + cell->unset("\\B"); + cell->unset("\\S"); goto next_cell; } if (input.match("11 ")) ACTION_DO_Y(1); @@ -510,7 +510,9 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (a.is_fully_const()) { cover_list("opt.opt_const.eqneq.swapconst", "$eq", "$ne", cell->type); - std::swap(cell->get("\\A"), cell->get("\\B")); + RTLIL::SigSpec tmp = cell->get("\\A"); + cell->set("\\A", cell->get("\\B")); + cell->set("\\B", tmp); } if (b.is_fully_const()) { @@ -522,7 +524,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cell->type = "$not"; cell->parameters.erase("\\B_WIDTH"); cell->parameters.erase("\\B_SIGNED"); - cell->connections().erase("\\B"); + cell->unset("\\B"); } goto next_cell; } @@ -585,13 +587,13 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cell->type.c_str(), cell->name.c_str(), module->name.c_str(), identity_wrt_a ? 'A' : 'B'); if (!identity_wrt_a) { - cell->get("\\A") = cell->get("\\B"); + cell->set("\\A", cell->get("\\B")); cell->parameters.at("\\A_WIDTH") = cell->parameters.at("\\B_WIDTH"); cell->parameters.at("\\A_SIGNED") = cell->parameters.at("\\B_SIGNED"); } cell->type = identity_bu0 ? "$bu0" : "$pos"; - cell->connections().erase("\\B"); + cell->unset("\\B"); cell->parameters.erase("\\B_WIDTH"); cell->parameters.erase("\\B_SIGNED"); cell->check(); @@ -613,8 +615,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cell->get("\\A") == RTLIL::SigSpec(1, 1) && cell->get("\\B") == RTLIL::SigSpec(0, 1)) { cover_list("opt.opt_const.mux_invert", "$mux", "$_MUX_", cell->type); cell->set("\\A", cell->get("\\S")); - cell->connections().erase("\\B"); - cell->connections().erase("\\S"); + cell->unset("\\B"); + cell->unset("\\S"); if (cell->type == "$mux") { cell->parameters["\\A_WIDTH"] = cell->parameters["\\WIDTH"]; cell->parameters["\\Y_WIDTH"] = cell->parameters["\\WIDTH"]; @@ -631,7 +633,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->get("\\A") == RTLIL::SigSpec(0, 1)) { cover_list("opt.opt_const.mux_and", "$mux", "$_MUX_", cell->type); cell->set("\\A", cell->get("\\S")); - cell->connections().erase("\\S"); + cell->unset("\\S"); if (cell->type == "$mux") { cell->parameters["\\A_WIDTH"] = cell->parameters["\\WIDTH"]; cell->parameters["\\B_WIDTH"] = cell->parameters["\\WIDTH"]; @@ -650,7 +652,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->get("\\B") == RTLIL::SigSpec(1, 1)) { cover_list("opt.opt_const.mux_or", "$mux", "$_MUX_", cell->type); cell->set("\\B", cell->get("\\S")); - cell->connections().erase("\\S"); + cell->unset("\\S"); if (cell->type == "$mux") { cell->parameters["\\A_WIDTH"] = cell->parameters["\\WIDTH"]; cell->parameters["\\B_WIDTH"] = cell->parameters["\\WIDTH"]; @@ -701,9 +703,9 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo } if (cell->get("\\S").size() != new_s.size()) { cover_list("opt.opt_const.mux_reduce", "$mux", "$pmux", cell->type); - cell->get("\\A") = new_a; - cell->get("\\B") = new_b; - cell->get("\\S") = new_s; + cell->set("\\A", new_a); + cell->set("\\B", new_b); + cell->set("\\S", new_s); if (new_s.size() > 1) { cell->type = "$pmux"; cell->parameters["\\S_WIDTH"] = new_s.size(); diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc index 8c281b342..1f8648c45 100644 --- a/passes/opt/opt_reduce.cc +++ b/passes/opt/opt_reduce.cc @@ -215,13 +215,19 @@ struct OptReduceWorker log_signal(cell->get("\\B")), log_signal(cell->get("\\Y"))); cell->set("\\A", RTLIL::SigSpec()); - for (auto &in_tuple : consolidated_in_tuples) - cell->get("\\A").append(in_tuple.at(0)); + for (auto &in_tuple : consolidated_in_tuples) { + RTLIL::SigSpec new_a = cell->get("\\A"); + new_a.append(in_tuple.at(0)); + cell->set("\\A", new_a); + } cell->set("\\B", RTLIL::SigSpec()); for (int i = 1; i <= cell->get("\\S").size(); i++) - for (auto &in_tuple : consolidated_in_tuples) - cell->get("\\B").append(in_tuple.at(i)); + for (auto &in_tuple : consolidated_in_tuples) { + RTLIL::SigSpec new_b = cell->get("\\B"); + new_b.append(in_tuple.at(i)); + cell->set("\\B", new_b); + } cell->parameters["\\WIDTH"] = RTLIL::Const(new_sig_y.size()); cell->set("\\Y", new_sig_y); diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc index 8412f929f..4f733a373 100644 --- a/passes/opt/opt_share.cc +++ b/passes/opt/opt_share.cc @@ -263,7 +263,7 @@ struct OptShareWorker log(" Cell `%s' is identical to cell `%s'.\n", cell->name.c_str(), sharemap[cell]->name.c_str()); for (auto &it : cell->connections()) { if (ct.cell_output(cell->type, it.first)) { - RTLIL::SigSpec other_sig = sharemap[cell]->connections()[it.first]; + RTLIL::SigSpec other_sig = sharemap[cell]->get(it.first); log(" Redirecting output %s: %s = %s\n", it.first.c_str(), log_signal(it.second), log_signal(other_sig)); module->connect(RTLIL::SigSig(it.second, other_sig)); diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index 2e2d4701f..cfd2eb7a7 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -160,15 +160,15 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec RTLIL::Cell *mux_sr_set = mod->addCell(NEW_ID, "$mux"); mux_sr_set->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size()); - mux_sr_set->connections()[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.size()); - mux_sr_set->connections()[set_polarity ? "\\B" : "\\A"] = sig_set; + mux_sr_set->set(set_polarity ? "\\A" : "\\B", RTLIL::Const(0, sig_in.size())); + mux_sr_set->set(set_polarity ? "\\B" : "\\A", sig_set); mux_sr_set->set("\\Y", sig_sr_set); mux_sr_set->set("\\S", set); RTLIL::Cell *mux_sr_clr = mod->addCell(NEW_ID, "$mux"); mux_sr_clr->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size()); - mux_sr_clr->connections()[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.size()); - mux_sr_clr->connections()[set_polarity ? "\\B" : "\\A"] = sig_set_inv; + mux_sr_clr->set(set_polarity ? "\\A" : "\\B", RTLIL::Const(0, sig_in.size())); + mux_sr_clr->set(set_polarity ? "\\B" : "\\A", sig_set_inv); mux_sr_clr->set("\\Y", sig_sr_clr); mux_sr_clr->set("\\S", set); diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc index 2ff755aef..30e7b748b 100644 --- a/passes/proc/proc_mux.cc +++ b/passes/proc/proc_mux.cc @@ -174,8 +174,15 @@ static void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw); assert(ctrl_sig.size() == 1); last_mux_cell->type = "$pmux"; - last_mux_cell->get("\\S").append(ctrl_sig); - last_mux_cell->get("\\B").append(when_signal); + + RTLIL::SigSpec new_s = last_mux_cell->get("\\S"); + new_s.append(ctrl_sig); + last_mux_cell->set("\\S", new_s); + + RTLIL::SigSpec new_b = last_mux_cell->get("\\B"); + new_b.append(when_signal); + last_mux_cell->set("\\B", new_b); + last_mux_cell->parameters["\\S_WIDTH"] = last_mux_cell->get("\\S").size(); } diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc index 58dcf915f..a84faf792 100644 --- a/passes/sat/expose.cc +++ b/passes/sat/expose.cc @@ -485,12 +485,12 @@ struct ExposePass : public Pass { for (auto &it : module->cells) { if (!ct.cell_known(it.second->type)) continue; - for (auto &conn : it.second->connections()) + for (auto &conn : it.second->connections_) if (ct.cell_input(it.second->type, conn.first)) conn.second = out_to_in_map(sigmap(conn.second)); } - for (auto &conn : module->connections()) + for (auto &conn : module->connections_) conn.second = out_to_in_map(sigmap(conn.second)); } @@ -518,7 +518,7 @@ struct ExposePass : public Pass { for (auto &bit : cell_q_bits) if (wire_bits_set.count(bit)) bit = RTLIL::SigBit(wire_dummy_q, wire_dummy_q->width++); - cell->get("\\Q") = cell_q_bits; + cell->set("\\Q", cell_q_bits); } RTLIL::Wire *wire_q = new RTLIL::Wire; diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index da9345855..d5336ca01 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -708,7 +708,7 @@ struct FreduceWorker RTLIL::Cell *drv = drivers.at(grp[i].bit).first; RTLIL::Wire *dummy_wire = module->addWire(NEW_ID); - for (auto &port : drv->connections()) + for (auto &port : drv->connections_) if (ct.cell_output(drv->type, port.first)) sigmap(port.second).replace(grp[i].bit, dummy_wire, &port.second); diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index 34355122a..96aa10ba3 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -132,8 +132,8 @@ static void create_miter_equiv(struct Pass *that, std::vector args, w2->width = w1->width; miter_module->add(w2); - gold_cell->connections()[w1->name] = w2; - gate_cell->connections()[w1->name] = w2; + gold_cell->set(w1->name, w2); + gate_cell->set(w1->name, w2); } if (w1->port_output) @@ -150,8 +150,8 @@ static void create_miter_equiv(struct Pass *that, std::vector args, w2_gate->width = w1->width; miter_module->add(w2_gate); - gold_cell->connections()[w1->name] = w2_gold; - gate_cell->connections()[w1->name] = w2_gate; + gold_cell->set(w1->name, w2_gold); + gate_cell->set(w1->name, w2_gate); RTLIL::SigSpec this_condition; diff --git a/passes/sat/share.cc b/passes/sat/share.cc index 13ef695e7..0ee5af186 100644 --- a/passes/sat/share.cc +++ b/passes/sat/share.cc @@ -258,7 +258,9 @@ struct ShareWorker RTLIL::Cell *unsigned_cell = c1->parameters.at("\\A_SIGNED").as_bool() ? c2 : c1; if (unsigned_cell->get("\\A").to_sigbit_vector().back() != RTLIL::State::S0) { unsigned_cell->parameters.at("\\A_WIDTH") = unsigned_cell->parameters.at("\\A_WIDTH").as_int() + 1; - unsigned_cell->get("\\A").append_bit(RTLIL::State::S0); + RTLIL::SigSpec new_a = unsigned_cell->get("\\A"); + new_a.append_bit(RTLIL::State::S0); + unsigned_cell->set("\\A", new_a); } unsigned_cell->parameters.at("\\A_SIGNED") = true; unsigned_cell->check(); @@ -312,7 +314,10 @@ struct ShareWorker if (score_flipped < score_unflipped) { - std::swap(c2->get("\\A"), c2->get("\\B")); + RTLIL::SigSpec tmp = c2->get("\\A"); + c2->set("\\A", c2->get("\\B")); + c2->set("\\B", tmp); + std::swap(c2->parameters.at("\\A_WIDTH"), c2->parameters.at("\\B_WIDTH")); std::swap(c2->parameters.at("\\A_SIGNED"), c2->parameters.at("\\B_SIGNED")); modified_src_cells = true; @@ -325,7 +330,9 @@ struct ShareWorker RTLIL::Cell *unsigned_cell = c1->parameters.at("\\A_SIGNED").as_bool() ? c2 : c1; if (unsigned_cell->get("\\A").to_sigbit_vector().back() != RTLIL::State::S0) { unsigned_cell->parameters.at("\\A_WIDTH") = unsigned_cell->parameters.at("\\A_WIDTH").as_int() + 1; - unsigned_cell->get("\\A").append_bit(RTLIL::State::S0); + RTLIL::SigSpec new_a = unsigned_cell->get("\\A"); + new_a.append_bit(RTLIL::State::S0); + unsigned_cell->set("\\A", new_a); } unsigned_cell->parameters.at("\\A_SIGNED") = true; modified_src_cells = true; @@ -336,7 +343,9 @@ struct ShareWorker RTLIL::Cell *unsigned_cell = c1->parameters.at("\\B_SIGNED").as_bool() ? c2 : c1; if (unsigned_cell->get("\\B").to_sigbit_vector().back() != RTLIL::State::S0) { unsigned_cell->parameters.at("\\B_WIDTH") = unsigned_cell->parameters.at("\\B_WIDTH").as_int() + 1; - unsigned_cell->get("\\B").append_bit(RTLIL::State::S0); + RTLIL::SigSpec new_b = unsigned_cell->get("\\B"); + new_b.append_bit(RTLIL::State::S0); + unsigned_cell->set("\\B", new_b); } unsigned_cell->parameters.at("\\B_SIGNED") = true; modified_src_cells = true; diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc index 1dce39f69..eabc56bd2 100644 --- a/passes/techmap/dfflibmap.cc +++ b/passes/techmap/dfflibmap.cc @@ -418,7 +418,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module) } else if (port.second != 0) log_abort(); - new_cell->connections()["\\" + port.first] = sig; + new_cell->set("\\" + port.first, sig); } stats[stringf(" mapped %%d %s cells to %s cells.\n", cell_type.c_str(), new_cell->type.c_str())]++; diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index 0d8f6ab0d..6439302cd 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -305,7 +305,7 @@ namespace if (wire->port_id > 0) { for (int i = 0; i < wire->width; i++) sig2port.insert(sigmap(RTLIL::SigSpec(wire, i)), std::pair(wire->name, i)); - cell->connections()[wire->name] = RTLIL::SigSpec(RTLIL::State::Sz, wire->width); + cell->set(wire->name, RTLIL::SigSpec(RTLIL::State::Sz, wire->width)); } } @@ -325,7 +325,9 @@ namespace for (int i = 0; i < sig.size(); i++) for (auto &port : sig2port.find(sig[i])) { RTLIL::SigSpec bitsig = haystack_cell->connections().at(mapping.portMapping[conn.first]).extract(i, 1); - cell->connections().at(port.first).replace(port.second, bitsig); + RTLIL::SigSpec new_sig = cell->get(port.first); + new_sig.replace(port.second, bitsig); + cell->set(port.first, new_sig); } } } @@ -744,7 +746,7 @@ struct ExtractPass : public Pass { for (auto &chunk : chunks) if (chunk.wire != NULL) chunk.wire = newMod->wires.at(chunk.wire->name); - newCell->connections()[conn.first] = chunks; + newCell->set(conn.first, chunks); } } } diff --git a/passes/techmap/hilomap.cc b/passes/techmap/hilomap.cc index 2e5dd7dca..309777876 100644 --- a/passes/techmap/hilomap.cc +++ b/passes/techmap/hilomap.cc @@ -35,7 +35,7 @@ void hilomap_worker(RTLIL::SigSpec &sig) if (!singleton_mode || last_hi == RTLIL::State::Sm) { last_hi = module->addWire(NEW_ID); RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(hicell_celltype)); - cell->connections()[RTLIL::escape_id(hicell_portname)] = last_hi; + cell->set(RTLIL::escape_id(hicell_portname), last_hi); } bit = last_hi; } @@ -43,7 +43,7 @@ void hilomap_worker(RTLIL::SigSpec &sig) if (!singleton_mode || last_lo == RTLIL::State::Sm) { last_lo = module->addWire(NEW_ID); RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(locell_celltype)); - cell->connections()[RTLIL::escape_id(locell_portname)] = last_lo; + cell->set(RTLIL::escape_id(locell_portname), last_lo); } bit = last_lo; } diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc index 199fd6029..114d28e25 100644 --- a/passes/techmap/iopadmap.cc +++ b/passes/techmap/iopadmap.cc @@ -177,9 +177,9 @@ struct IopadmapPass : public Pass { for (int i = 0; i < wire->width; i++) { RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype)); - cell->connections()[RTLIL::escape_id(portname)] = RTLIL::SigSpec(wire, i); + cell->set(RTLIL::escape_id(portname), RTLIL::SigSpec(wire, i)); if (!portname2.empty()) - cell->connections()[RTLIL::escape_id(portname2)] = RTLIL::SigSpec(new_wire, i); + cell->set(RTLIL::escape_id(portname2), RTLIL::SigSpec(new_wire, i)); if (!widthparam.empty()) cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(1); if (!nameparam.empty()) @@ -190,9 +190,9 @@ struct IopadmapPass : public Pass { else { RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype)); - cell->connections()[RTLIL::escape_id(portname)] = RTLIL::SigSpec(wire); + cell->set(RTLIL::escape_id(portname), RTLIL::SigSpec(wire)); if (!portname2.empty()) - cell->connections()[RTLIL::escape_id(portname2)] = RTLIL::SigSpec(new_wire); + cell->set(RTLIL::escape_id(portname2), RTLIL::SigSpec(new_wire)); if (!widthparam.empty()) cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(wire->width); if (!nameparam.empty()) diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc index f8851400f..355c07c84 100644 --- a/passes/techmap/simplemap.cc +++ b/passes/techmap/simplemap.cc @@ -128,7 +128,7 @@ static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) if (cell->type == "$reduce_bool") gate_type = "$_OR_"; log_assert(!gate_type.empty()); - RTLIL::SigSpec *last_output = NULL; + RTLIL::Cell *last_output_cell = NULL; while (sig_a.size() > 1) { @@ -145,7 +145,7 @@ static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) gate->set("\\A", sig_a[i]); gate->set("\\B", sig_a[i+1]); gate->set("\\Y", sig_t[i/2]); - last_output = &gate->get("\\Y"); + last_output_cell = gate; } sig_a = sig_t; @@ -156,14 +156,14 @@ static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::Cell *gate = module->addCell(NEW_ID, "$_INV_"); gate->set("\\A", sig_a); gate->set("\\Y", sig_t); - last_output = &gate->get("\\Y"); + last_output_cell = gate; sig_a = sig_t; } - if (last_output == NULL) { + if (last_output_cell == NULL) { module->connect(RTLIL::SigSig(sig_y, sig_a)); } else { - *last_output = sig_y; + last_output_cell->set("\\Y", sig_y); } } diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 4c8f92505..9dcd6a45b 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -195,7 +195,7 @@ struct TechmapWorker if (!flatten_mode && c->type.substr(0, 2) == "\\$") c->type = c->type.substr(1); - for (auto &it2 : c->connections()) { + for (auto &it2 : c->connections_) { apply_prefix(cell->name, it2.second, module); port_signal_map.apply(it2.second); } -- cgit v1.2.3 From 97a59851a6c411ccb06162d4b31725bf89262378 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 26 Jul 2014 16:11:28 +0200 Subject: Added RTLIL::Cell::has(portname) --- passes/cmds/add.cc | 2 +- passes/fsm/fsm_detect.cc | 2 +- passes/fsm/fsm_expand.cc | 16 ++++++++-------- passes/fsm/fsm_extract.cc | 2 +- passes/opt/opt_const.cc | 4 ++-- passes/sat/expose.cc | 4 ++-- 6 files changed, 15 insertions(+), 15 deletions(-) (limited to 'passes') diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc index 1401193fd..f94ea639b 100644 --- a/passes/cmds/add.cc +++ b/passes/cmds/add.cc @@ -75,7 +75,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n continue; if (mod->get_bool_attribute("\\blackbox")) continue; - if (it.second->connections().count(name) > 0) + if (it.second->has(name)) continue; it.second->set(name, wire); diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc index be851afa6..55fe336f4 100644 --- a/passes/fsm/fsm_detect.cc +++ b/passes/fsm/fsm_detect.cc @@ -80,7 +80,7 @@ static bool check_state_users(RTLIL::SigSpec sig) continue; if (cellport.second != "\\A" && cellport.second != "\\B") return false; - if (cell->connections().count("\\A") == 0 || cell->connections().count("\\B") == 0 || cell->connections().count("\\Y") == 0) + if (!cell->has("\\A") || !cell->has("\\B") || !cell->has("\\Y")) return false; for (auto &port_it : cell->connections()) if (port_it.first != "\\A" && port_it.first != "\\B" && port_it.first != "\\Y") diff --git a/passes/fsm/fsm_expand.cc b/passes/fsm/fsm_expand.cc index ed80d7c31..186ea2fd4 100644 --- a/passes/fsm/fsm_expand.cc +++ b/passes/fsm/fsm_expand.cc @@ -47,13 +47,13 @@ struct FsmExpand return true; RTLIL::SigSpec new_signals; - if (cell->connections().count("\\A") > 0) + if (cell->has("\\A")) new_signals.append(assign_map(cell->get("\\A"))); - if (cell->connections().count("\\B") > 0) + if (cell->has("\\B")) new_signals.append(assign_map(cell->get("\\B"))); - if (cell->connections().count("\\S") > 0) + if (cell->has("\\S")) new_signals.append(assign_map(cell->get("\\S"))); - if (cell->connections().count("\\Y") > 0) + if (cell->has("\\Y")) new_signals.append(assign_map(cell->get("\\Y"))); new_signals.sort_and_unify(); @@ -65,7 +65,7 @@ struct FsmExpand if (new_signals.size() > 3) return false; - if (cell->connections().count("\\Y") > 0) { + if (cell->has("\\Y")) { new_signals.append(assign_map(cell->get("\\Y"))); new_signals.sort_and_unify(); new_signals.remove_const(); @@ -148,11 +148,11 @@ struct FsmExpand for (int i = 0; i < (1 << input_sig.size()); i++) { RTLIL::Const in_val(i, input_sig.size()); RTLIL::SigSpec A, B, S; - if (cell->connections().count("\\A") > 0) + if (cell->has("\\A")) A = assign_map(cell->get("\\A")); - if (cell->connections().count("\\B") > 0) + if (cell->has("\\B")) B = assign_map(cell->get("\\B")); - if (cell->connections().count("\\S") > 0) + if (cell->has("\\S")) S = assign_map(cell->get("\\S")); A.replace(input_sig, RTLIL::SigSpec(in_val)); B.replace(input_sig, RTLIL::SigSpec(in_val)); diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index e89bba893..ff3ac7608 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -350,7 +350,7 @@ struct FsmExtractPass : public Pass { assign_map.apply(sig); sig2driver.insert(sig, sig2driver_entry_t(cell_it.first, conn_it.first)); } - if (ct.cell_input(cell_it.second->type, conn_it.first) && cell_it.second->connections().count("\\Y") > 0 && + if (ct.cell_input(cell_it.second->type, conn_it.first) && cell_it.second->has("\\Y") && cell_it.second->get("\\Y").size() == 1 && (conn_it.first == "\\A" || conn_it.first == "\\B")) { RTLIL::SigSpec sig = conn_it.second; assign_map.apply(sig); diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index e52882316..000a9ec2b 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -88,7 +88,7 @@ static void replace_cell(RTLIL::Module *module, RTLIL::Cell *cell, std::string i static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutative, bool extend_u0, SigMap &sigmap) { - std::string b_name = cell->connections().count("\\B") ? "\\B" : "\\A"; + std::string b_name = cell->has("\\B") ? "\\B" : "\\A"; bool a_signed = cell->parameters.at("\\A_SIGNED").as_bool(); bool b_signed = cell->parameters.at(b_name + "_SIGNED").as_bool(); @@ -321,7 +321,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cell->type == "$mul" || cell->type == "$div" || cell->type == "$mod" || cell->type == "$pow") { RTLIL::SigSpec sig_a = assign_map(cell->get("\\A")); - RTLIL::SigSpec sig_b = cell->connections().count("\\B") ? assign_map(cell->get("\\B")) : RTLIL::SigSpec(); + RTLIL::SigSpec sig_b = cell->has("\\B") ? assign_map(cell->get("\\B")) : RTLIL::SigSpec(); if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr") sig_a = RTLIL::SigSpec(); diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc index a84faf792..198f83477 100644 --- a/passes/sat/expose.cc +++ b/passes/sat/expose.cc @@ -83,7 +83,7 @@ static void find_dff_wires(std::set &dff_wires, RTLIL::Module *modu SigPool dffsignals; for (auto &it : module->cells) { - if (ct.cell_known(it.second->type) && it.second->connections().count("\\Q")) + if (ct.cell_known(it.second->type) && it.second->has("\\Q")) dffsignals.add(sigmap(it.second->get("\\Q"))); } @@ -628,7 +628,7 @@ struct ExposePass : public Pass { log("New module port: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name), RTLIL::id2cstr(cell->type)); RTLIL::SigSpec sig; - if (cell->connections().count(p->name) != 0) + if (cell->has(p->name)) sig = cell->connections().at(p->name); sig.extend(w->width); if (w->port_input) -- cgit v1.2.3 From 3f4e3ca8ad480c2e73e2072ada77078ffd95e08f Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 26 Jul 2014 16:14:02 +0200 Subject: More RTLIL::Cell API usage cleanups --- passes/opt/opt_const.cc | 2 +- passes/sat/expose.cc | 2 +- passes/techmap/extract.cc | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) (limited to 'passes') diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index 000a9ec2b..672186006 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -94,7 +94,7 @@ static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool com bool b_signed = cell->parameters.at(b_name + "_SIGNED").as_bool(); RTLIL::SigSpec sig_a = sigmap(cell->get("\\A")); - RTLIL::SigSpec sig_b = sigmap(cell->connections().at(b_name)); + RTLIL::SigSpec sig_b = sigmap(cell->get(b_name)); RTLIL::SigSpec sig_y = sigmap(cell->get("\\Y")); if (extend_u0) { diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc index 198f83477..9ce3b43d3 100644 --- a/passes/sat/expose.cc +++ b/passes/sat/expose.cc @@ -629,7 +629,7 @@ struct ExposePass : public Pass { RTLIL::SigSpec sig; if (cell->has(p->name)) - sig = cell->connections().at(p->name); + sig = cell->get(p->name); sig.extend(w->width); if (w->port_input) module->connect(RTLIL::SigSig(sig, w)); diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index 6439302cd..b8c349f5c 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -128,7 +128,7 @@ namespace for (auto &conn : needleCell->connections()) { RTLIL::SigSpec needleSig = conn.second; - RTLIL::SigSpec haystackSig = haystackCell->connections().at(portMapping.at(conn.first)); + RTLIL::SigSpec haystackSig = haystackCell->get(portMapping.at(conn.first)); for (int i = 0; i < std::min(needleSig.size(), haystackSig.size()); i++) { RTLIL::Wire *needleWire = needleSig[i].wire, *haystackWire = haystackSig[i].wire; @@ -324,7 +324,7 @@ namespace if (mapping.portMapping.count(conn.first) > 0 && sig2port.has(sigmap(sig))) { for (int i = 0; i < sig.size(); i++) for (auto &port : sig2port.find(sig[i])) { - RTLIL::SigSpec bitsig = haystack_cell->connections().at(mapping.portMapping[conn.first]).extract(i, 1); + RTLIL::SigSpec bitsig = haystack_cell->get(mapping.portMapping[conn.first]).extract(i, 1); RTLIL::SigSpec new_sig = cell->get(port.first); new_sig.replace(port.second, bitsig); cell->set(port.first, new_sig); -- cgit v1.2.3 From 946ddff9cef3ea0b4dad8664319fb13074133775 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 26 Jul 2014 20:12:50 +0200 Subject: Changed a lot of code to the new RTLIL::Wire constructors --- passes/abc/abc.cc | 8 ++----- passes/abc/blifparse.cc | 22 +++++------------- passes/cmds/add.cc | 5 +--- passes/cmds/delete.cc | 35 ++++------------------------ passes/cmds/scatter.cc | 5 +--- passes/cmds/splitnets.cc | 38 +++++++++++++++---------------- passes/fsm/fsm_extract.cc | 5 +--- passes/fsm/fsm_map.cc | 20 ++++------------ passes/hierarchy/hierarchy.cc | 5 +--- passes/hierarchy/submod.cc | 39 +++++++++++++++++-------------- passes/memory/memory_dff.cc | 9 ++------ passes/memory/memory_map.cc | 53 ++++++++++++------------------------------- passes/opt/opt_clean.cc | 16 ++++++++----- passes/proc/proc_mux.cc | 15 +++--------- passes/sat/miter.cc | 23 ++++--------------- 15 files changed, 96 insertions(+), 202 deletions(-) (limited to 'passes') diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index 4d9a6c136..41cfe88f6 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -313,11 +313,9 @@ static void handle_loops() continue; } - RTLIL::Wire *wire = new RTLIL::Wire; std::stringstream sstr; sstr << "$abcloop$" << (RTLIL::autoidx++); - wire->name = sstr.str(); - module->wires[wire->name] = wire; + RTLIL::Wire *wire = module->addWire(sstr.str()); bool first_line = true; for (int id2 : edges[id1]) { @@ -691,9 +689,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std log_error("ABC output file does not contain a module `netlist'.\n"); for (auto &it : mapped_mod->wires) { RTLIL::Wire *w = it.second; - RTLIL::Wire *wire = new RTLIL::Wire; - wire->name = remap_name(w->name); - module->wires[wire->name] = wire; + RTLIL::Wire *wire = module->addWire(remap_name(w->name)); design->select(module, wire); } diff --git a/passes/abc/blifparse.cc b/passes/abc/blifparse.cc index 45a9ac765..e86afa1b7 100644 --- a/passes/abc/blifparse.cc +++ b/passes/abc/blifparse.cc @@ -98,14 +98,12 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name) if (!strcmp(cmd, ".inputs") || !strcmp(cmd, ".outputs")) { char *p; while ((p = strtok(NULL, " \t\r\n")) != NULL) { - RTLIL::Wire *wire = new RTLIL::Wire; - wire->name = stringf("\\%s", p); + RTLIL::Wire *wire = module->addWire(stringf("\\%s", p)); wire->port_id = ++port_count; if (!strcmp(cmd, ".inputs")) wire->port_input = true; else wire->port_output = true; - module->add(wire); } continue; } @@ -115,17 +113,11 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name) char *d = strtok(NULL, " \t\r\n"); char *q = strtok(NULL, " \t\r\n"); - if (module->wires.count(RTLIL::escape_id(d)) == 0) { - RTLIL::Wire *wire = new RTLIL::Wire; - wire->name = RTLIL::escape_id(d); - module->add(wire); - } + if (module->wires.count(RTLIL::escape_id(d)) == 0) + module->addWire(RTLIL::escape_id(d)); - if (module->wires.count(RTLIL::escape_id(q)) == 0) { - RTLIL::Wire *wire = new RTLIL::Wire; - wire->name = RTLIL::escape_id(q); - module->add(wire); - } + if (module->wires.count(RTLIL::escape_id(q)) == 0) + module->addWire(RTLIL::escape_id(q)); RTLIL::Cell *cell = module->addCell(NEW_ID, dff_name); cell->set("\\D", module->wires.at(RTLIL::escape_id(d))); @@ -162,9 +154,7 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name) if (module->wires.count(stringf("\\%s", p)) > 0) { wire = module->wires.at(stringf("\\%s", p)); } else { - wire = new RTLIL::Wire; - wire->name = stringf("\\%s", p); - module->add(wire); + wire = module->addWire(stringf("\\%s", p)); } input_sig.append(wire); } diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc index f94ea639b..7e9ba97ec 100644 --- a/passes/cmds/add.cc +++ b/passes/cmds/add.cc @@ -47,12 +47,9 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n } else { - wire = new RTLIL::Wire; - wire->name = name; - wire->width = width; + wire = module->addWire(name, width); wire->port_input = flag_input; wire->port_output = flag_output; - module->add(wire); if (flag_input || flag_output) { wire->port_id = module->wires.size(); diff --git a/passes/cmds/delete.cc b/passes/cmds/delete.cc index 79b7c3c30..df5a3d4b9 100644 --- a/passes/cmds/delete.cc +++ b/passes/cmds/delete.cc @@ -21,22 +21,6 @@ #include "kernel/rtlil.h" #include "kernel/log.h" -struct DeleteWireWorker -{ - RTLIL::Module *module; - std::set *delete_wires_p; - - void operator()(RTLIL::SigSpec &sig) { - std::vector chunks = sig; - for (auto &c : chunks) - if (c.wire != NULL && delete_wires_p->count(c.wire->name)) { - c.wire = module->addWire(NEW_ID, c.width); - c.offset = 0; - } - sig = chunks; - } -}; - struct DeletePass : public Pass { DeletePass() : Pass("delete", "delete objects in the design") { } virtual void help() @@ -106,14 +90,14 @@ struct DeletePass : public Pass { continue; } - std::set delete_wires; + std::set delete_wires; std::set delete_cells; std::set delete_procs; std::set delete_mems; for (auto &it : module->wires) if (design->selected(module, it.second)) - delete_wires.insert(it.first); + delete_wires.insert(it.second); for (auto &it : module->memories) if (design->selected(module, it.second)) @@ -131,30 +115,21 @@ struct DeletePass : public Pass { if (design->selected(module, it.second)) delete_procs.insert(it.first); - DeleteWireWorker delete_wire_worker; - delete_wire_worker.module = module; - delete_wire_worker.delete_wires_p = &delete_wires; - module->rewrite_sigspecs(delete_wire_worker); - - for (auto &it : delete_wires) { - delete module->wires.at(it); - module->wires.erase(it); - } - for (auto &it : delete_mems) { delete module->memories.at(it); module->memories.erase(it); } - for (auto &it : delete_cells) { + for (auto &it : delete_cells) module->remove(it); - } for (auto &it : delete_procs) { delete module->processes.at(it); module->processes.erase(it); } + module->remove(delete_wires); + module->fixup_ports(); } diff --git a/passes/cmds/scatter.cc b/passes/cmds/scatter.cc index 35ce0a110..0b95fe024 100644 --- a/passes/cmds/scatter.cc +++ b/passes/cmds/scatter.cc @@ -51,10 +51,7 @@ struct ScatterPass : public Pass { for (auto &c : mod_it.second->cells) for (auto &p : c.second->connections_) { - RTLIL::Wire *wire = new RTLIL::Wire; - wire->name = NEW_ID; - wire->width = p.second.size(); - mod_it.second->add(wire); + RTLIL::Wire *wire = mod_it.second->addWire(NEW_ID, p.second.size()); if (ct.cell_output(c.second->type, p.first)) { RTLIL::SigSig sigsig(p.second, wire); diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc index 28575e7b4..6bffba622 100644 --- a/passes/cmds/splitnets.cc +++ b/passes/cmds/splitnets.cc @@ -28,33 +28,31 @@ struct SplitnetsWorker void append_wire(RTLIL::Module *module, RTLIL::Wire *wire, int offset, int width, std::string format) { - RTLIL::Wire *new_wire = new RTLIL::Wire; - - new_wire->port_id = wire->port_id; - new_wire->port_input = wire->port_input; - new_wire->port_output = wire->port_output; - new_wire->name = wire->name; - new_wire->width = width; + std::string new_wire_name = wire->name; if (format.size() > 0) - new_wire->name += format.substr(0, 1); + new_wire_name += format.substr(0, 1); if (width > 1) { - new_wire->name += stringf("%d", offset+width-1); + new_wire_name += stringf("%d", offset+width-1); if (format.size() > 2) - new_wire->name += format.substr(2, 1); + new_wire_name += format.substr(2, 1); else - new_wire->name += ":"; + new_wire_name += ":"; } - new_wire->name += stringf("%d", offset); + new_wire_name += stringf("%d", offset); if (format.size() > 1) - new_wire->name += format.substr(1, 1); + new_wire_name += format.substr(1, 1); - while (module->count_id(new_wire->name) > 0) - new_wire->name = new_wire->name + "_"; - module->add(new_wire); + while (module->count_id(new_wire_name) > 0) + new_wire_name += "_"; + + RTLIL::Wire *new_wire = module->addWire(new_wire_name, width); + new_wire->port_id = wire->port_id; + new_wire->port_input = wire->port_input; + new_wire->port_output = wire->port_output; std::vector sigvec = RTLIL::SigSpec(new_wire).to_sigbit_vector(); splitmap[wire].insert(splitmap[wire].end(), sigvec.begin(), sigvec.end()); @@ -178,10 +176,10 @@ struct SplitnetsPass : public Pass { module->rewrite_sigspecs(worker); - for (auto &it : worker.splitmap) { - module->wires.erase(it.first->name); - delete it.first; - } + std::set delete_wires; + for (auto &it : worker.splitmap) + delete_wires.insert(it.first); + module->remove(delete_wires); module->fixup_ports(); } diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index ff3ac7608..51a4a75e7 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -296,10 +296,7 @@ static void extract_fsm(RTLIL::Wire *wire) RTLIL::Cell *cell = module->cells.at(cellport.first); RTLIL::SigSpec port_sig = assign_map(cell->get(cellport.second)); RTLIL::SigSpec unconn_sig = port_sig.extract(ctrl_out); - RTLIL::Wire *unconn_wire = new RTLIL::Wire; - unconn_wire->name = stringf("$fsm_unconnect$%s$%d", log_signal(unconn_sig), RTLIL::autoidx++); - unconn_wire->width = unconn_sig.size(); - module->wires[unconn_wire->name] = unconn_wire; + RTLIL::Wire *unconn_wire = module->addWire(stringf("$fsm_unconnect$%s$%d", log_signal(unconn_sig), RTLIL::autoidx++), unconn_sig.size()); port_sig.replace(unconn_sig, RTLIL::SigSpec(unconn_wire), &cell->connections_[cellport.second]); } } diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc index a22441b4a..7ab159540 100644 --- a/passes/fsm/fsm_map.cc +++ b/passes/fsm/fsm_map.cc @@ -143,13 +143,11 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) // create state register - RTLIL::Wire *state_wire = new RTLIL::Wire; - state_wire->name = fsm_cell->parameters["\\NAME"].decode_string(); - while (module->count_id(state_wire->name) > 0) - state_wire->name += "_"; - state_wire->width = fsm_data.state_bits; - module->add(state_wire); + std::string state_wire_name = fsm_cell->parameters["\\NAME"].decode_string(); + while (module->count_id(state_wire_name) > 0) + state_wire_name += "_"; + RTLIL::Wire *state_wire = module->addWire(state_wire_name, fsm_data.state_bits); RTLIL::Wire *next_state_wire = module->addWire(NEW_ID, fsm_data.state_bits); RTLIL::Cell *state_dff = module->addCell(NEW_ID, ""); @@ -209,10 +207,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) // generate next_state signal - RTLIL::Wire *next_state_onehot = new RTLIL::Wire; - next_state_onehot->name = NEW_ID; - next_state_onehot->width = fsm_data.state_table.size(); - module->add(next_state_onehot); + RTLIL::Wire *next_state_onehot = module->addWire(NEW_ID, fsm_data.state_table.size()); for (size_t i = 0; i < fsm_data.state_table.size(); i++) { @@ -275,11 +270,6 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) // Generate ctrl_out signal - RTLIL::Wire *ctrl_out_wire = new RTLIL::Wire; - ctrl_out_wire->name = NEW_ID; - ctrl_out_wire->width = fsm_data.num_outputs; - module->add(ctrl_out_wire); - for (int i = 0; i < fsm_data.num_outputs; i++) { std::map> pattern_cache; diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 76b667b86..8c09d2eaa 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -118,13 +118,10 @@ static void generate(RTLIL::Design *design, const std::vector &cell design->modules[mod->name] = mod; for (auto &decl : ports) { - RTLIL::Wire *wire = new RTLIL::Wire; - wire->name = decl.portname; - wire->width = portwidths.at(decl.portname); + RTLIL::Wire *wire = mod->addWire(decl.portname, portwidths.at(decl.portname)); wire->port_id = decl.index; wire->port_input = decl.input; wire->port_output = decl.output; - mod->add(wire); } for (auto ¶ : parameters) diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index ef4a9f16d..e39f96ca8 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -123,31 +123,37 @@ struct SubmodWorker if (wire->port_output) flags.is_ext_used = true; - RTLIL::Wire *new_wire = new RTLIL::Wire; - new_wire->name = wire->name; - new_wire->width = wire->width; - new_wire->start_offset = wire->start_offset; - new_wire->attributes = wire->attributes; + bool new_wire_port_input = false; + bool new_wire_port_output = false; if (flags.is_int_driven && flags.is_ext_used) - new_wire->port_output = true; + new_wire_port_output = true; if (flags.is_ext_driven && flags.is_int_used) - new_wire->port_input = true; + new_wire_port_input = true; if (flags.is_int_driven && flags.is_ext_driven) - new_wire->port_input = true, new_wire->port_output = true; - - if (new_wire->port_input || new_wire->port_output) { - new_wire->port_id = port_counter++; - while (new_wire->name[0] == '$') { - std::string new_wire_name = stringf("\\n%d", auto_name_counter++); - if (all_wire_names.count(new_wire_name) == 0) { - all_wire_names.insert(new_wire_name); - new_wire->name = new_wire_name; + new_wire_port_input = true, new_wire_port_output = true; + + std::string new_wire_name = wire->name; + if (new_wire_port_input || new_wire_port_output) { + while (new_wire_name[0] == '$') { + std::string next_wire_name = stringf("\\n%d", auto_name_counter++); + if (all_wire_names.count(next_wire_name) == 0) { + all_wire_names.insert(next_wire_name); + new_wire_name = next_wire_name; } } } + RTLIL::Wire *new_wire = new_mod->addWire(new_wire_name, wire->width); + new_wire->port_input = new_wire_port_input; + new_wire->port_output = new_wire_port_output; + new_wire->start_offset = wire->start_offset; + new_wire->attributes = wire->attributes; + + if (new_wire->port_input || new_wire->port_output) + new_wire->port_id = port_counter++; + if (new_wire->port_input && new_wire->port_output) log(" signal %s: inout %s\n", wire->name.c_str(), new_wire->name.c_str()); else if (new_wire->port_input) @@ -157,7 +163,6 @@ struct SubmodWorker else log(" signal %s: internal\n", wire->name.c_str()); - new_mod->wires[new_wire->name] = new_wire; flags.new_wire = new_wire; } diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index 999c969b5..b63b3aec6 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -118,18 +118,13 @@ static void disconnect_dff(RTLIL::Module *module, RTLIL::SigSpec sig) std::stringstream sstr; sstr << "$memory_dff_disconnected$" << (RTLIL::autoidx++); - RTLIL::Wire *wire = new RTLIL::Wire; - wire->name = sstr.str(); - wire->width = sig.size(); - module->wires[wire->name] = wire; - - RTLIL::SigSpec newsig(wire); + RTLIL::SigSpec new_sig = module->addWire(sstr.str(), sig.size()); for (auto &cell_it : module->cells) { RTLIL::Cell *cell = cell_it.second; if (cell->type == "$dff") { RTLIL::SigSpec new_q = cell->get("\\Q"); - new_q.replace(sig, newsig); + new_q.replace(sig, new_sig); cell->set("\\Q", new_q); } } diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index 5b180db62..32c7e63a0 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -126,20 +126,17 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) c->set("\\CLK", RTLIL::SigSpec(RTLIL::State::S0)); } - RTLIL::Wire *w_in = new RTLIL::Wire; - w_in->name = genid(cell->name, "", i, "$d"); - w_in->width = mem_width; - module->wires[w_in->name] = w_in; + RTLIL::Wire *w_in = module->addWire(genid(cell->name, "", i, "$d"), mem_width); data_reg_in.push_back(RTLIL::SigSpec(w_in)); c->set("\\D", data_reg_in.back()); - RTLIL::Wire *w_out = new RTLIL::Wire; - w_out->name = stringf("%s[%d]", cell->parameters["\\MEMID"].decode_string().c_str(), i); - if (module->wires.count(w_out->name) > 0) - w_out->name = genid(cell->name, "", i, "$q"); - w_out->width = mem_width; + std::string w_out_name = stringf("%s[%d]", cell->parameters["\\MEMID"].decode_string().c_str(), i); + if (module->wires.count(w_out_name) > 0) + w_out_name = genid(cell->name, "", i, "$q"); + + RTLIL::Wire *w_out = module->addWire(w_out_name, mem_width); w_out->start_offset = mem_offset; - module->wires[w_out->name] = w_out; + data_reg_out.push_back(RTLIL::SigSpec(w_out)); c->set("\\Q", data_reg_out.back()); } @@ -167,10 +164,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) c->set("\\D", rd_addr); count_dff++; - RTLIL::Wire *w = new RTLIL::Wire; - w->name = genid(cell->name, "$rdreg", i, "$q"); - w->width = mem_abits; - module->wires[w->name] = w; + RTLIL::Wire *w = module->addWire(genid(cell->name, "$rdreg", i, "$q"), mem_abits); c->set("\\Q", RTLIL::SigSpec(w)); rd_addr = RTLIL::SigSpec(w); @@ -184,10 +178,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) c->set("\\Q", rd_signals.back()); count_dff++; - RTLIL::Wire *w = new RTLIL::Wire; - w->name = genid(cell->name, "$rdreg", i, "$d"); - w->width = mem_width; - module->wires[w->name] = w; + RTLIL::Wire *w = module->addWire(genid(cell->name, "$rdreg", i, "$d"), mem_width); rd_signals.clear(); rd_signals.push_back(RTLIL::SigSpec(w)); @@ -207,17 +198,8 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) c->set("\\S", rd_addr.extract(mem_abits-j-1, 1)); count_mux++; - RTLIL::Wire *w = new RTLIL::Wire; - w->name = genid(cell->name, "$rdmux", i, "", j, "", k, "$a"); - w->width = mem_width; - module->wires[w->name] = w; - c->set("\\A", RTLIL::SigSpec(w)); - - w = new RTLIL::Wire; - w->name = genid(cell->name, "$rdmux", i, "", j, "", k, "$b"); - w->width = mem_width; - module->wires[w->name] = w; - c->set("\\B", RTLIL::SigSpec(w)); + c->set("\\A", module->addWire(genid(cell->name, "$rdmux", i, "", j, "", k, "$a"), mem_width)); + c->set("\\B", module->addWire(genid(cell->name, "$rdmux", i, "", j, "", k, "$b"), mem_width)); next_rd_signals.push_back(c->get("\\A")); next_rd_signals.push_back(c->get("\\B")); @@ -255,9 +237,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) c->set("\\B", wr_addr); count_wrmux++; - RTLIL::Wire *w_seladdr = new RTLIL::Wire; - w_seladdr->name = genid(cell->name, "$wreq", i, "", j, "$y"); - module->wires[w_seladdr->name] = w_seladdr; + RTLIL::Wire *w_seladdr = module->addWire(genid(cell->name, "$wreq", i, "", j, "$y")); c->set("\\Y", w_seladdr); int wr_offset = 0; @@ -286,9 +266,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) c->set("\\A", w); c->set("\\B", wr_bit); - w = new RTLIL::Wire; - w->name = genid(cell->name, "$wren", i, "", j, "", wr_offset, "$y"); - module->wires[w->name] = w; + w = module->addWire(genid(cell->name, "$wren", i, "", j, "", wr_offset, "$y")); c->set("\\Y", RTLIL::SigSpec(w)); } @@ -298,10 +276,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) c->set("\\B", wr_data.extract(wr_offset, wr_width)); c->set("\\S", RTLIL::SigSpec(w)); - w = new RTLIL::Wire; - w->name = genid(cell->name, "$wrmux", i, "", j, "", wr_offset, "$y"); - w->width = wr_width; - module->wires[w->name] = w; + w = module->addWire(genid(cell->name, "$wrmux", i, "", j, "", wr_offset, "$y"), wr_width); c->set("\\Y", w); sig.replace(wr_offset, w); diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index e279c0209..63d03b205 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -218,14 +218,14 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool } } - std::vector del_wires; + std::vector maybe_del_wires; for (auto &it : module->wires) { RTLIL::Wire *wire = it.second; if ((!purge_mode && check_public_name(wire->name)) || wire->port_id != 0 || wire->get_bool_attribute("\\keep")) { RTLIL::SigSpec s1 = RTLIL::SigSpec(wire), s2 = s1; assign_map.apply(s2); if (!used_signals.check_any(s2) && wire->port_id == 0 && !wire->get_bool_attribute("\\keep")) { - del_wires.push_back(wire); + maybe_del_wires.push_back(wire); } else { assert(SIZE(s1) == SIZE(s2)); RTLIL::SigSig new_conn; @@ -242,7 +242,7 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool } } else { if (!used_signals.check_any(RTLIL::SigSpec(wire))) - del_wires.push_back(wire); + maybe_del_wires.push_back(wire); } RTLIL::SigSpec sig = assign_map(RTLIL::SigSpec(wire)); if (!used_signals_nodrivers.check_any(sig)) { @@ -265,6 +265,9 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool } } + + std::set del_wires; + int del_wires_count = 0; for (auto wire : del_wires) if (!used_signals.check_any(RTLIL::SigSpec(wire))) { @@ -272,11 +275,12 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool log(" removing unused non-port wire %s.\n", wire->name.c_str()); del_wires_count++; } - module->wires.erase(wire->name); - count_rm_wires++; - delete wire; + del_wires.insert(wire); } + module->remove(del_wires); + count_rm_wires += del_wires.size();; + if (del_wires_count > 0) log(" removed %d unused temporary wires.\n", del_wires_count); } diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc index 30e7b748b..67113a682 100644 --- a/passes/proc/proc_mux.cc +++ b/passes/proc/proc_mux.cc @@ -60,10 +60,7 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, std::stringstream sstr; sstr << "$procmux$" << (RTLIL::autoidx++); - RTLIL::Wire *cmp_wire = new RTLIL::Wire; - cmp_wire->name = sstr.str() + "_CMP"; - cmp_wire->width = 0; - mod->wires[cmp_wire->name] = cmp_wire; + RTLIL::Wire *cmp_wire = mod->addWire(sstr.str() + "_CMP", 0); for (auto comp : compare) { @@ -109,10 +106,7 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, } else { - ctrl_wire = new RTLIL::Wire; - ctrl_wire->name = sstr.str() + "_CTRL"; - ctrl_wire->width = 1; - mod->wires[ctrl_wire->name] = ctrl_wire; + ctrl_wire = mod->addWire(sstr.str() + "_CTRL"); // reduce cmp vector to one logic signal RTLIL::Cell *any_cell = mod->addCell(sstr.str() + "_ANY", "$reduce_or"); @@ -147,10 +141,7 @@ static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, assert(ctrl_sig.size() == 1); // prepare multiplexer output signal - RTLIL::Wire *result_wire = new RTLIL::Wire; - result_wire->name = sstr.str() + "_Y"; - result_wire->width = when_signal.size(); - mod->wires[result_wire->name] = result_wire; + RTLIL::Wire *result_wire = mod->addWire(sstr.str() + "_Y", when_signal.size()); // create the multiplexer itself RTLIL::Cell *mux_cell = mod->addCell(sstr.str(), "$mux"); diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index 96aa10ba3..0c5989b10 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -126,11 +126,8 @@ static void create_miter_equiv(struct Pass *that, std::vector args, if (w1->port_input) { - RTLIL::Wire *w2 = new RTLIL::Wire; - w2->name = "\\in_" + RTLIL::unescape_id(w1->name); + RTLIL::Wire *w2 = miter_module->addWire("\\in_" + RTLIL::unescape_id(w1->name), w1->width); w2->port_input = true; - w2->width = w1->width; - miter_module->add(w2); gold_cell->set(w1->name, w2); gate_cell->set(w1->name, w2); @@ -138,17 +135,11 @@ static void create_miter_equiv(struct Pass *that, std::vector args, if (w1->port_output) { - RTLIL::Wire *w2_gold = new RTLIL::Wire; - w2_gold->name = "\\gold_" + RTLIL::unescape_id(w1->name); + RTLIL::Wire *w2_gold = miter_module->addWire("\\gold_" + RTLIL::unescape_id(w1->name), w1->width); w2_gold->port_output = flag_make_outputs; - w2_gold->width = w1->width; - miter_module->add(w2_gold); - RTLIL::Wire *w2_gate = new RTLIL::Wire; - w2_gate->name = "\\gate_" + RTLIL::unescape_id(w1->name); + RTLIL::Wire *w2_gate = miter_module->addWire("\\gate_" + RTLIL::unescape_id(w1->name), w1->width); w2_gate->port_output = flag_make_outputs; - w2_gate->width = w1->width; - miter_module->add(w2_gate); gold_cell->set(w1->name, w2_gold); gate_cell->set(w1->name, w2_gate); @@ -220,10 +211,8 @@ static void create_miter_equiv(struct Pass *that, std::vector args, if (flag_make_outcmp) { - RTLIL::Wire *w_cmp = new RTLIL::Wire; - w_cmp->name = "\\cmp_" + RTLIL::unescape_id(w1->name); + RTLIL::Wire *w_cmp = miter_module->addWire("\\cmp_" + RTLIL::unescape_id(w1->name)); w_cmp->port_output = true; - miter_module->add(w_cmp); miter_module->connect(RTLIL::SigSig(w_cmp, this_condition)); } @@ -247,10 +236,8 @@ static void create_miter_equiv(struct Pass *that, std::vector args, assert_cell->set("\\EN", RTLIL::SigSpec(1, 1)); } - RTLIL::Wire *w_trigger = new RTLIL::Wire; - w_trigger->name = "\\trigger"; + RTLIL::Wire *w_trigger = miter_module->addWire("\\trigger"); w_trigger->port_output = true; - miter_module->add(w_trigger); RTLIL::Cell *not_cell = miter_module->addCell(NEW_ID, "$not"); not_cell->parameters["\\A_WIDTH"] = all_conditions.size(); -- cgit v1.2.3 From d68c993ed2ea384db4d6af5161b3b36096828499 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 26 Jul 2014 21:16:05 +0200 Subject: Changed more code to the new RTLIL::Wire constructors --- passes/cmds/rename.cc | 14 ++++-------- passes/cmds/splice.cc | 10 ++++----- passes/sat/expose.cc | 55 +++++++++++----------------------------------- passes/techmap/extract.cc | 5 +---- passes/techmap/iopadmap.cc | 9 ++------ passes/techmap/techmap.cc | 10 ++++----- 6 files changed, 29 insertions(+), 74 deletions(-) (limited to 'passes') diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc index 519dce452..721d5c987 100644 --- a/passes/cmds/rename.cc +++ b/passes/cmds/rename.cc @@ -31,21 +31,15 @@ static void rename_in_module(RTLIL::Module *module, std::string from_name, std:: for (auto &it : module->wires) if (it.first == from_name) { - RTLIL::Wire *wire = it.second; - log("Renaming wire %s to %s in module %s.\n", wire->name.c_str(), to_name.c_str(), module->name.c_str()); - module->wires.erase(wire->name); - wire->name = to_name; - module->add(wire); + log("Renaming wire %s to %s in module %s.\n", log_id(it.second), log_id(to_name), log_id(module)); + module->rename(it.second, to_name); return; } for (auto &it : module->cells) if (it.first == from_name) { - RTLIL::Cell *cell = it.second; - log("Renaming cell %s to %s in module %s.\n", cell->name.c_str(), to_name.c_str(), module->name.c_str()); - module->cells.erase(cell->name); - cell->name = to_name; - module->add(cell); + log("Renaming cell %s to %s in module %s.\n", log_id(it.second), log_id(to_name), log_id(module)); + module->rename(it.second, to_name); return; } diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc index 8b7e04062..61de44066 100644 --- a/passes/cmds/splice.cc +++ b/passes/cmds/splice.cc @@ -224,14 +224,14 @@ struct SpliceWorker for (auto &it : rework_wires) { - module->wires.erase(it.first->name); - RTLIL::Wire *new_port = new RTLIL::Wire(*it.first); - it.first->name = NEW_ID; + std::string orig_name = it.first->name; + module->rename(it.first, NEW_ID); + + RTLIL::Wire *new_port = module->addWire(orig_name, it.first); it.first->port_id = 0; it.first->port_input = false; it.first->port_output = false; - module->add(it.first); - module->add(new_port); + module->connect(RTLIL::SigSig(new_port, it.second)); } } diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc index 9ce3b43d3..21af63a36 100644 --- a/passes/sat/expose.cc +++ b/passes/sat/expose.cc @@ -208,11 +208,11 @@ static void create_dff_dq_map(std::map &map, RTLIL: } } -static void add_new_wire(RTLIL::Module *module, RTLIL::Wire *wire) +static RTLIL::Wire *add_new_wire(RTLIL::Module *module, std::string name, int width = 1) { - if (module->count_id(wire->name)) - log_error("Attempting to create wire %s, but a wire of this name exists already! Hint: Try another value for -sep.\n", RTLIL::id2cstr(wire->name)); - module->add(wire); + if (module->count_id(name)) + log_error("Attempting to create wire %s, but a wire of this name exists already! Hint: Try another value for -sep.\n", log_id(name)); + return module->addWire(name, width); } struct ExposePass : public Pass { @@ -448,7 +448,6 @@ struct ExposePass : public Pass { SigMap sigmap(module); SigMap out_to_in_map; - std::vector new_wires; for (auto &it : module->wires) { @@ -468,20 +467,14 @@ struct ExposePass : public Pass { } if (flag_cut) { - RTLIL::Wire *in_wire = new RTLIL::Wire; - in_wire->name = it.second->name + sep + "i"; - in_wire->width = it.second->width; + RTLIL::Wire *in_wire = add_new_wire(module, it.second->name + sep + "i", it.second->width); in_wire->port_input = true; out_to_in_map.add(sigmap(it.second), in_wire); - new_wires.push_back(in_wire); } } if (flag_cut) { - for (auto it : new_wires) - add_new_wire(module, it); - for (auto &it : module->cells) { if (!ct.cell_known(it.second->type)) continue; @@ -507,10 +500,7 @@ struct ExposePass : public Pass { dff_map_info_t &info = dq.second; - RTLIL::Wire *wire_dummy_q = new RTLIL::Wire; - wire_dummy_q->name = NEW_ID; - wire_dummy_q->width = 0; - add_new_wire(module, wire_dummy_q); + RTLIL::Wire *wire_dummy_q = add_new_wire(module, NEW_ID, 0); for (auto &cell_name : info.cells) { RTLIL::Cell *cell = module->cells.at(cell_name); @@ -521,12 +511,9 @@ struct ExposePass : public Pass { cell->set("\\Q", cell_q_bits); } - RTLIL::Wire *wire_q = new RTLIL::Wire; - wire_q->name = wire->name + sep + "q"; - wire_q->width = wire->width; + RTLIL::Wire *wire_q = add_new_wire(module, wire->name + sep + "q", wire->width); wire_q->port_input = true; log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_q->name)); - add_new_wire(module, wire_q); RTLIL::SigSig connect_q; for (size_t i = 0; i < wire_bits_vec.size(); i++) { @@ -538,19 +525,14 @@ struct ExposePass : public Pass { } module->connect(connect_q); - RTLIL::Wire *wire_d = new RTLIL::Wire; - wire_d->name = wire->name + sep + "d"; - wire_d->width = wire->width; + RTLIL::Wire *wire_d = add_new_wire(module, wire->name + sep + "d", wire->width); wire_d->port_output = true; log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_d->name)); - add_new_wire(module, wire_d); module->connect(RTLIL::SigSig(wire_d, info.sig_d)); - RTLIL::Wire *wire_c = new RTLIL::Wire; - wire_c->name = wire->name + sep + "c"; + RTLIL::Wire *wire_c = add_new_wire(module, wire->name + sep + "c"); wire_c->port_output = true; log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_c->name)); - add_new_wire(module, wire_c); if (info.clk_polarity) { module->connect(RTLIL::SigSig(wire_c, info.sig_clk)); } else { @@ -564,11 +546,9 @@ struct ExposePass : public Pass { if (info.sig_arst != RTLIL::State::Sm) { - RTLIL::Wire *wire_r = new RTLIL::Wire; - wire_r->name = wire->name + sep + "r"; + RTLIL::Wire *wire_r = add_new_wire(module, wire->name + sep + "r"); wire_r->port_output = true; log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_r->name)); - add_new_wire(module, wire_r); if (info.arst_polarity) { module->connect(RTLIL::SigSig(wire_r, info.sig_arst)); } else { @@ -580,12 +560,9 @@ struct ExposePass : public Pass { c->set("\\Y", wire_r); } - RTLIL::Wire *wire_v = new RTLIL::Wire; - wire_v->name = wire->name + sep + "v"; - wire_v->width = wire->width; + RTLIL::Wire *wire_v = add_new_wire(module, wire->name + sep + "v", wire->width); wire_v->port_output = true; log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_v->name)); - add_new_wire(module, wire_v); module->connect(RTLIL::SigSig(wire_v, info.arst_value)); } } @@ -616,14 +593,11 @@ struct ExposePass : public Pass { if (!p->port_input && !p->port_output) continue; - RTLIL::Wire *w = new RTLIL::Wire; - w->name = cell->name + sep + RTLIL::unescape_id(p->name); - w->width = p->width; + RTLIL::Wire *w = add_new_wire(module, cell->name + sep + RTLIL::unescape_id(p->name), p->width); if (p->port_input) w->port_output = true; if (p->port_output) w->port_input = true; - add_new_wire(module, w); log("New module port: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name), RTLIL::id2cstr(cell->type)); @@ -641,14 +615,11 @@ struct ExposePass : public Pass { { for (auto &it : cell->connections()) { - RTLIL::Wire *w = new RTLIL::Wire; - w->name = cell->name + sep + RTLIL::unescape_id(it.first); - w->width = it.second.size(); + RTLIL::Wire *w = add_new_wire(module, cell->name + sep + RTLIL::unescape_id(it.first), it.second.size()); if (ct.cell_input(cell->type, it.first)) w->port_output = true; if (ct.cell_output(cell->type, it.first)) w->port_input = true; - add_new_wire(module, w); log("New module port: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name), RTLIL::id2cstr(cell->type)); diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index b8c349f5c..92bcafc00 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -729,13 +729,10 @@ struct ExtractPass : public Pass { int portCounter = 1; for (auto wire : wires) { - RTLIL::Wire *newWire = new RTLIL::Wire; - newWire->name = wire->name; - newWire->width = wire->width; + RTLIL::Wire *newWire = newMod->addWire(wire->name, wire->width); newWire->port_id = portCounter++; newWire->port_input = true; newWire->port_output = true; - newMod->add(newWire); } for (auto cell : cells) { diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc index 114d28e25..ab3bb3ed0 100644 --- a/passes/techmap/iopadmap.cc +++ b/passes/techmap/iopadmap.cc @@ -164,13 +164,8 @@ struct IopadmapPass : public Pass { log("Mapping port %s.%s using %s.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name), celltype.c_str()); RTLIL::Wire *new_wire = NULL; - if (!portname2.empty()) { - new_wire = new RTLIL::Wire; - *new_wire = *wire; - wire->name = NEW_ID; - module->wires[wire->name] = wire; - module->wires[new_wire->name] = new_wire; - } + if (!portname2.empty()) + new_wire = module->addWire(NEW_ID, wire); if (flag_bits) { diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 9dcd6a45b..bee1df406 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -128,14 +128,14 @@ struct TechmapWorker for (auto &it : tpl->wires) { if (it.second->port_id > 0) positional_ports[stringf("$%d", it.second->port_id)] = it.first; - RTLIL::Wire *w = new RTLIL::Wire(*it.second); - apply_prefix(cell->name, w->name); + std::string w_name = it.second->name; + apply_prefix(cell->name, w_name); + RTLIL::Wire *w = module->addWire(w_name, it.second); w->port_input = false; w->port_output = false; w->port_id = 0; if (it.second->get_bool_attribute("\\_techmap_special_")) w->attributes.clear(); - module->add(w); design->select(module, w); } @@ -381,7 +381,6 @@ struct TechmapWorker log_error("Techmap yielded config wire %s with non-const value %s.\n", RTLIL::id2cstr(data.wire->name), log_signal(data.value)); techmap_wire_names.erase(it.first); - tpl->wires.erase(data.wire->name); const char *p = data.wire->name.c_str(); const char *q = strrchr(p+1, '.'); @@ -391,8 +390,7 @@ struct TechmapWorker std::string new_name = data.wire->name.substr(0, q-p) + "_TECHMAP_DONE_" + data.wire->name.substr(q-p+12); while (tpl->wires.count(new_name)) new_name += "_"; - data.wire->name = new_name; - tpl->add(data.wire); + tpl->rename(data.wire, new_name); std::string cmd_string = data.value.as_const().decode_string(); Pass::call_on_module(map, tpl, cmd_string); -- cgit v1.2.3 From f9946232adf887e5aa4a48c64f88eaa17e424009 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 01:49:51 +0200 Subject: Refactoring: Renamed RTLIL::Module::wires to wires_ --- passes/abc/abc.cc | 52 +++++++++++++++++++++---------------------- passes/abc/blifparse.cc | 16 ++++++------- passes/cmds/add.cc | 6 ++--- passes/cmds/delete.cc | 4 ++-- passes/cmds/rename.cc | 10 ++++----- passes/cmds/scc.cc | 2 +- passes/cmds/select.cc | 32 +++++++++++++------------- passes/cmds/setattr.cc | 2 +- passes/cmds/setundef.cc | 2 +- passes/cmds/show.cc | 2 +- passes/cmds/splice.cc | 6 ++--- passes/cmds/splitnets.cc | 2 +- passes/cmds/stat.cc | 2 +- passes/fsm/fsm_detect.cc | 4 ++-- passes/fsm/fsm_extract.cc | 6 ++--- passes/hierarchy/hierarchy.cc | 8 +++---- passes/hierarchy/submod.cc | 2 +- passes/memory/memory_map.cc | 2 +- passes/memory/memory_share.cc | 2 +- passes/opt/opt_clean.cc | 10 ++++----- passes/opt/opt_const.cc | 2 +- passes/opt/opt_muxtree.cc | 2 +- passes/opt/opt_rmdff.cc | 2 +- passes/opt/opt_share.cc | 2 +- passes/proc/proc_arst.cc | 4 ++-- passes/sat/eval.cc | 22 +++++++++--------- passes/sat/expose.cc | 22 +++++++++--------- passes/sat/freduce.cc | 2 +- passes/sat/miter.cc | 14 ++++++------ passes/sat/sat.cc | 8 +++---- passes/techmap/extract.cc | 6 ++--- passes/techmap/iopadmap.cc | 2 +- passes/techmap/techmap.cc | 16 ++++++------- 33 files changed, 138 insertions(+), 138 deletions(-) (limited to 'passes') diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index 41cfe88f6..184f143a1 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -453,8 +453,8 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std clk_polarity = false; clk_str = clk_str.substr(1); } - if (module->wires.count(RTLIL::escape_id(clk_str)) != 0) - clk_sig = assign_map(RTLIL::SigSpec(module->wires.at(RTLIL::escape_id(clk_str)), 0)); + if (module->wires_.count(RTLIL::escape_id(clk_str)) != 0) + clk_sig = assign_map(RTLIL::SigSpec(module->wires_.at(RTLIL::escape_id(clk_str)), 0)); } if (dff_mode && clk_sig.size() == 0) @@ -495,7 +495,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std for (auto c : cells) extract_cell(c, keepff); - for (auto &wire_it : module->wires) { + for (auto &wire_it : module->wires_) { if (wire_it.second->port_id > 0 || wire_it.second->get_bool_attribute("\\keep")) mark_port(RTLIL::SigSpec(wire_it.second)); } @@ -687,7 +687,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std RTLIL::Module *mapped_mod = mapped_design->modules["\\netlist"]; if (mapped_mod == NULL) log_error("ABC output file does not contain a module `netlist'.\n"); - for (auto &it : mapped_mod->wires) { + for (auto &it : mapped_mod->wires_) { RTLIL::Wire *w = it.second; RTLIL::Wire *wire = module->addWire(remap_name(w->name)); design->select(module, wire); @@ -701,47 +701,47 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std cell_stats[RTLIL::unescape_id(c->type)]++; if (c->type == "\\ZERO" || c->type == "\\ONE") { RTLIL::SigSig conn; - conn.first = RTLIL::SigSpec(module->wires[remap_name(c->get("\\Y").as_wire()->name)]); + conn.first = RTLIL::SigSpec(module->wires_[remap_name(c->get("\\Y").as_wire()->name)]); conn.second = RTLIL::SigSpec(c->type == "\\ZERO" ? 0 : 1, 1); module->connect(conn); continue; } if (c->type == "\\BUF") { RTLIL::SigSig conn; - conn.first = RTLIL::SigSpec(module->wires[remap_name(c->get("\\Y").as_wire()->name)]); - conn.second = RTLIL::SigSpec(module->wires[remap_name(c->get("\\A").as_wire()->name)]); + conn.first = RTLIL::SigSpec(module->wires_[remap_name(c->get("\\Y").as_wire()->name)]); + conn.second = RTLIL::SigSpec(module->wires_[remap_name(c->get("\\A").as_wire()->name)]); module->connect(conn); continue; } if (c->type == "\\INV") { RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_INV_"); - cell->set("\\A", RTLIL::SigSpec(module->wires[remap_name(c->get("\\A").as_wire()->name)])); - cell->set("\\Y", RTLIL::SigSpec(module->wires[remap_name(c->get("\\Y").as_wire()->name)])); + cell->set("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\A").as_wire()->name)])); + cell->set("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\Y").as_wire()->name)])); design->select(module, cell); continue; } if (c->type == "\\AND" || c->type == "\\OR" || c->type == "\\XOR") { RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_" + c->type.substr(1) + "_"); - cell->set("\\A", RTLIL::SigSpec(module->wires[remap_name(c->get("\\A").as_wire()->name)])); - cell->set("\\B", RTLIL::SigSpec(module->wires[remap_name(c->get("\\B").as_wire()->name)])); - cell->set("\\Y", RTLIL::SigSpec(module->wires[remap_name(c->get("\\Y").as_wire()->name)])); + cell->set("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\A").as_wire()->name)])); + cell->set("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\B").as_wire()->name)])); + cell->set("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\Y").as_wire()->name)])); design->select(module, cell); continue; } if (c->type == "\\MUX") { RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_MUX_"); - cell->set("\\A", RTLIL::SigSpec(module->wires[remap_name(c->get("\\A").as_wire()->name)])); - cell->set("\\B", RTLIL::SigSpec(module->wires[remap_name(c->get("\\B").as_wire()->name)])); - cell->set("\\S", RTLIL::SigSpec(module->wires[remap_name(c->get("\\S").as_wire()->name)])); - cell->set("\\Y", RTLIL::SigSpec(module->wires[remap_name(c->get("\\Y").as_wire()->name)])); + cell->set("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\A").as_wire()->name)])); + cell->set("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\B").as_wire()->name)])); + cell->set("\\S", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\S").as_wire()->name)])); + cell->set("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\Y").as_wire()->name)])); design->select(module, cell); continue; } if (c->type == "\\DFF") { log_assert(clk_sig.size() == 1); RTLIL::Cell *cell = module->addCell(remap_name(c->name), clk_polarity ? "$_DFF_P_" : "$_DFF_N_"); - cell->set("\\D", RTLIL::SigSpec(module->wires[remap_name(c->get("\\D").as_wire()->name)])); - cell->set("\\Q", RTLIL::SigSpec(module->wires[remap_name(c->get("\\Q").as_wire()->name)])); + cell->set("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\D").as_wire()->name)])); + cell->set("\\Q", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\Q").as_wire()->name)])); cell->set("\\C", clk_sig); design->select(module, cell); continue; @@ -757,7 +757,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std cell_stats[RTLIL::unescape_id(c->type)]++; if (c->type == "\\_const0_" || c->type == "\\_const1_") { RTLIL::SigSig conn; - conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections().begin()->second.as_wire()->name)]); + conn.first = RTLIL::SigSpec(module->wires_[remap_name(c->connections().begin()->second.as_wire()->name)]); conn.second = RTLIL::SigSpec(c->type == "\\_const0_" ? 0 : 1, 1); module->connect(conn); continue; @@ -765,8 +765,8 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std if (c->type == "\\_dff_") { log_assert(clk_sig.size() == 1); RTLIL::Cell *cell = module->addCell(remap_name(c->name), clk_polarity ? "$_DFF_P_" : "$_DFF_N_"); - cell->set("\\D", RTLIL::SigSpec(module->wires[remap_name(c->get("\\D").as_wire()->name)])); - cell->set("\\Q", RTLIL::SigSpec(module->wires[remap_name(c->get("\\Q").as_wire()->name)])); + cell->set("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\D").as_wire()->name)])); + cell->set("\\Q", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\Q").as_wire()->name)])); cell->set("\\C", clk_sig); design->select(module, cell); continue; @@ -779,7 +779,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std if (c.width == 0) continue; assert(c.width == 1); - newsig.append(module->wires[remap_name(c.wire->name)]); + newsig.append(module->wires_[remap_name(c.wire->name)]); } cell->set(conn.first, newsig); } @@ -789,9 +789,9 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std for (auto conn : mapped_mod->connections()) { if (!conn.first.is_fully_const()) - conn.first = RTLIL::SigSpec(module->wires[remap_name(conn.first.as_wire()->name)]); + conn.first = RTLIL::SigSpec(module->wires_[remap_name(conn.first.as_wire()->name)]); if (!conn.second.is_fully_const()) - conn.second = RTLIL::SigSpec(module->wires[remap_name(conn.second.as_wire()->name)]); + conn.second = RTLIL::SigSpec(module->wires_[remap_name(conn.second.as_wire()->name)]); module->connect(conn); } @@ -805,10 +805,10 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std RTLIL::SigSig conn; if (si.type >= 0) { conn.first = si.bit; - conn.second = RTLIL::SigSpec(module->wires[remap_name(buffer)]); + conn.second = RTLIL::SigSpec(module->wires_[remap_name(buffer)]); out_wires++; } else { - conn.first = RTLIL::SigSpec(module->wires[remap_name(buffer)]); + conn.first = RTLIL::SigSpec(module->wires_[remap_name(buffer)]); conn.second = si.bit; in_wires++; } diff --git a/passes/abc/blifparse.cc b/passes/abc/blifparse.cc index e86afa1b7..773bbe5d2 100644 --- a/passes/abc/blifparse.cc +++ b/passes/abc/blifparse.cc @@ -113,15 +113,15 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name) char *d = strtok(NULL, " \t\r\n"); char *q = strtok(NULL, " \t\r\n"); - if (module->wires.count(RTLIL::escape_id(d)) == 0) + if (module->wires_.count(RTLIL::escape_id(d)) == 0) module->addWire(RTLIL::escape_id(d)); - if (module->wires.count(RTLIL::escape_id(q)) == 0) + if (module->wires_.count(RTLIL::escape_id(q)) == 0) module->addWire(RTLIL::escape_id(q)); RTLIL::Cell *cell = module->addCell(NEW_ID, dff_name); - cell->set("\\D", module->wires.at(RTLIL::escape_id(d))); - cell->set("\\Q", module->wires.at(RTLIL::escape_id(q))); + cell->set("\\D", module->wires_.at(RTLIL::escape_id(d))); + cell->set("\\Q", module->wires_.at(RTLIL::escape_id(q))); continue; } @@ -138,9 +138,9 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name) if (q == NULL || !q[0] || !q[1]) goto error; *(q++) = 0; - if (module->wires.count(RTLIL::escape_id(q)) == 0) + if (module->wires_.count(RTLIL::escape_id(q)) == 0) module->addWire(RTLIL::escape_id(q)); - cell->set(RTLIL::escape_id(p), module->wires.at(RTLIL::escape_id(q))); + cell->set(RTLIL::escape_id(p), module->wires_.at(RTLIL::escape_id(q))); } continue; } @@ -151,8 +151,8 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name) RTLIL::SigSpec input_sig, output_sig; while ((p = strtok(NULL, " \t\r\n")) != NULL) { RTLIL::Wire *wire; - if (module->wires.count(stringf("\\%s", p)) > 0) { - wire = module->wires.at(stringf("\\%s", p)); + if (module->wires_.count(stringf("\\%s", p)) > 0) { + wire = module->wires_.at(stringf("\\%s", p)); } else { wire = module->addWire(stringf("\\%s", p)); } diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc index 7e9ba97ec..e97bf8fc1 100644 --- a/passes/cmds/add.cc +++ b/passes/cmds/add.cc @@ -28,8 +28,8 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n if (module->count_id(name) != 0) { - if (module->wires.count(name) > 0) - wire = module->wires.at(name); + if (module->wires_.count(name) > 0) + wire = module->wires_.at(name); if (wire != NULL && wire->width != width) wire = NULL; @@ -52,7 +52,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n wire->port_output = flag_output; if (flag_input || flag_output) { - wire->port_id = module->wires.size(); + wire->port_id = module->wires_.size(); module->fixup_ports(); } diff --git a/passes/cmds/delete.cc b/passes/cmds/delete.cc index df5a3d4b9..460dd9663 100644 --- a/passes/cmds/delete.cc +++ b/passes/cmds/delete.cc @@ -79,7 +79,7 @@ struct DeletePass : public Pass { RTLIL::Module *module = mod_it.second; if (flag_input || flag_output) { - for (auto &it : module->wires) + for (auto &it : module->wires_) if (design->selected(module, it.second)) { if (flag_input) it.second->port_input = false; @@ -95,7 +95,7 @@ struct DeletePass : public Pass { std::set delete_procs; std::set delete_mems; - for (auto &it : module->wires) + for (auto &it : module->wires_) if (design->selected(module, it.second)) delete_wires.insert(it.second); diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc index 721d5c987..e163e7243 100644 --- a/passes/cmds/rename.cc +++ b/passes/cmds/rename.cc @@ -29,7 +29,7 @@ static void rename_in_module(RTLIL::Module *module, std::string from_name, std:: if (module->count_id(to_name)) log_cmd_error("There is already an object `%s' in module `%s'.\n", to_name.c_str(), module->name.c_str()); - for (auto &it : module->wires) + for (auto &it : module->wires_) if (it.first == from_name) { log("Renaming wire %s to %s in module %s.\n", log_id(it.second), log_id(to_name), log_id(module)); module->rename(it.second, to_name); @@ -105,13 +105,13 @@ struct RenamePass : public Pass { continue; std::map new_wires; - for (auto &it : module->wires) { + for (auto &it : module->wires_) { if (it.first[0] == '$' && design->selected(module, it.second)) do it.second->name = stringf("\\_%d_", counter++); while (module->count_id(it.second->name) > 0); new_wires[it.second->name] = it.second; } - module->wires.swap(new_wires); + module->wires_.swap(new_wires); std::map new_cells; for (auto &it : module->cells) { @@ -135,13 +135,13 @@ struct RenamePass : public Pass { continue; std::map new_wires; - for (auto &it : module->wires) { + for (auto &it : module->wires_) { if (design->selected(module, it.second)) if (it.first[0] == '\\' && it.second->port_id == 0) it.second->name = NEW_ID; new_wires[it.second->name] = it.second; } - module->wires.swap(new_wires); + module->wires_.swap(new_wires); std::map new_cells; for (auto &it : module->cells) { diff --git a/passes/cmds/scc.cc b/passes/cmds/scc.cc index 3380a935a..7e2b2fc9f 100644 --- a/passes/cmds/scc.cc +++ b/passes/cmds/scc.cc @@ -114,7 +114,7 @@ struct SccWorker SigPool selectedSignals; SigSet sigToNextCells; - for (auto &it : module->wires) + for (auto &it : module->wires_) if (design->selected(module, it.second)) selectedSignals.add(sigmap(RTLIL::SigSpec(it.second))); diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index e0f1a6d69..0cabdc06b 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -161,7 +161,7 @@ static void select_op_neg(RTLIL::Design *design, RTLIL::Selection &lhs) } RTLIL::Module *mod = mod_it.second; - for (auto &it : mod->wires) + for (auto &it : mod->wires_) if (!lhs.selected_member(mod_it.first, it.first)) new_sel.selected_members[mod->name].insert(it.first); for (auto &it : mod->memories) @@ -215,11 +215,11 @@ static void select_op_alias(RTLIL::Design *design, RTLIL::Selection &lhs) SigMap sigmap(mod_it.second); SigPool selected_bits; - for (auto &it : mod_it.second->wires) + for (auto &it : mod_it.second->wires_) if (lhs.selected_member(mod_it.first, it.first)) selected_bits.add(sigmap(it.second)); - for (auto &it : mod_it.second->wires) + for (auto &it : mod_it.second->wires_) if (!lhs.selected_member(mod_it.first, it.first) && selected_bits.check_any(sigmap(it.second))) lhs.selected_members[mod_it.first].insert(it.first); } @@ -278,7 +278,7 @@ static void select_op_diff(RTLIL::Design *design, RTLIL::Selection &lhs, const R if (lhs.selected_modules.count(mod->name) > 0) { - for (auto &it : mod->wires) + for (auto &it : mod->wires_) lhs.selected_members[mod->name].insert(it.first); for (auto &it : mod->memories) lhs.selected_members[mod->name].insert(it.first); @@ -376,7 +376,7 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v RTLIL::Module *mod = mod_it.second; std::set selected_wires; - for (auto &it : mod->wires) + for (auto &it : mod->wires_) if (lhs.selected_member(mod_it.first, it.first) && limits.count(it.first) == 0) selected_wires.insert(it.second); @@ -700,22 +700,22 @@ static void select_stmt(RTLIL::Design *design, std::string arg) RTLIL::Module *mod = mod_it.second; if (arg_memb.substr(0, 2) == "w:") { - for (auto &it : mod->wires) + for (auto &it : mod->wires_) if (match_ids(it.first, arg_memb.substr(2))) sel.selected_members[mod->name].insert(it.first); } else if (arg_memb.substr(0, 2) == "i:") { - for (auto &it : mod->wires) + for (auto &it : mod->wires_) if (it.second->port_input && match_ids(it.first, arg_memb.substr(2))) sel.selected_members[mod->name].insert(it.first); } else if (arg_memb.substr(0, 2) == "o:") { - for (auto &it : mod->wires) + for (auto &it : mod->wires_) if (it.second->port_output && match_ids(it.first, arg_memb.substr(2))) sel.selected_members[mod->name].insert(it.first); } else if (arg_memb.substr(0, 2) == "x:") { - for (auto &it : mod->wires) + for (auto &it : mod->wires_) if ((it.second->port_input || it.second->port_output) && match_ids(it.first, arg_memb.substr(2))) sel.selected_members[mod->name].insert(it.first); } else @@ -723,7 +723,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg) size_t delim = arg_memb.substr(2).find(':'); if (delim == std::string::npos) { int width = atoi(arg_memb.substr(2).c_str()); - for (auto &it : mod->wires) + for (auto &it : mod->wires_) if (it.second->width == width) sel.selected_members[mod->name].insert(it.first); } else { @@ -731,7 +731,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg) std::string max_str = arg_memb.substr(2+delim+1); int min_width = min_str.empty() ? 0 : atoi(min_str.c_str()); int max_width = max_str.empty() ? -1 : atoi(max_str.c_str()); - for (auto &it : mod->wires) + for (auto &it : mod->wires_) if (min_width <= it.second->width && (it.second->width <= max_width || max_width == -1)) sel.selected_members[mod->name].insert(it.first); } @@ -757,7 +757,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg) sel.selected_members[mod->name].insert(it.first); } else if (arg_memb.substr(0, 2) == "a:") { - for (auto &it : mod->wires) + for (auto &it : mod->wires_) if (match_attr(it.second->attributes, arg_memb.substr(2))) sel.selected_members[mod->name].insert(it.first); for (auto &it : mod->memories) @@ -777,7 +777,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg) } else { if (arg_memb.substr(0, 2) == "n:") arg_memb = arg_memb.substr(2); - for (auto &it : mod->wires) + for (auto &it : mod->wires_) if (match_ids(it.first, arg_memb)) sel.selected_members[mod->name].insert(it.first); for (auto &it : mod->memories) @@ -1152,7 +1152,7 @@ struct SelectPass : public Pass { if (sel->selected_whole_module(mod_it.first) && list_mode) log("%s\n", id2cstr(mod_it.first)); if (sel->selected_module(mod_it.first)) { - for (auto &it : mod_it.second->wires) + for (auto &it : mod_it.second->wires_) if (sel->selected_member(mod_it.first, it.first)) LOG_OBJECT("%s/%s\n", id2cstr(mod_it.first), id2cstr(it.first)); for (auto &it : mod_it.second->memories) @@ -1219,7 +1219,7 @@ struct SelectPass : public Pass { sel->optimize(design); for (auto mod_it : design->modules) if (sel->selected_module(mod_it.first)) { - for (auto &it : mod_it.second->wires) + for (auto &it : mod_it.second->wires_) if (sel->selected_member(mod_it.first, it.first)) total_count++; for (auto &it : mod_it.second->memories) @@ -1374,7 +1374,7 @@ struct LsPass : public Pass { if (design->modules.count(design->selected_active_module) > 0) { RTLIL::Module *module = design->modules.at(design->selected_active_module); - counter += log_matches("wires", pattern, module->wires); + counter += log_matches("wires", pattern, module->wires_); counter += log_matches("memories", pattern, module->memories); counter += log_matches("cells", pattern, module->cells); counter += log_matches("processes", pattern, module->processes); diff --git a/passes/cmds/setattr.cc b/passes/cmds/setattr.cc index 8d98df719..0b4f2a8a2 100644 --- a/passes/cmds/setattr.cc +++ b/passes/cmds/setattr.cc @@ -111,7 +111,7 @@ struct SetattrPass : public Pass { if (!design->selected(module)) continue; - for (auto &it : module->wires) + for (auto &it : module->wires_) if (design->selected(module, it.second)) do_setunset(it.second->attributes, setunset_list); diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index e26106103..82dc1d999 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -129,7 +129,7 @@ struct SetundefPass : public Pass { SigMap sigmap(module); SigPool undriven_signals; - for (auto &it : module->wires) + for (auto &it : module->wires_) if (!it.second->port_input) undriven_signals.add(sigmap(it.second)); diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index d63d98972..1feb90afb 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -305,7 +305,7 @@ struct ShowWorker std::set all_sources, all_sinks; std::map wires_on_demand; - for (auto &it : module->wires) { + for (auto &it : module->wires_) { if (!design->selected_member(module->name, it.first)) continue; const char *shape = "diamond"; diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc index 61de44066..691d972cf 100644 --- a/passes/cmds/splice.cc +++ b/passes/cmds/splice.cc @@ -149,7 +149,7 @@ struct SpliceWorker driven_bits.push_back(RTLIL::State::Sm); driven_bits.push_back(RTLIL::State::Sm); - for (auto &it : module->wires) + for (auto &it : module->wires_) if (it.second->port_input) { RTLIL::SigSpec sig = sigmap(it.second); driven_chunks.insert(sig); @@ -175,7 +175,7 @@ struct SpliceWorker SigPool selected_bits; if (!sel_by_cell) - for (auto &it : module->wires) + for (auto &it : module->wires_) if (design->selected(module, it.second)) selected_bits.add(sigmap(it.second)); @@ -203,7 +203,7 @@ struct SpliceWorker std::vector> rework_wires; - for (auto &it : module->wires) + for (auto &it : module->wires_) if (!no_outputs && it.second->port_output) { if (!design->selected(module, it.second)) continue; diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc index 6bffba622..accb178ba 100644 --- a/passes/cmds/splitnets.cc +++ b/passes/cmds/splitnets.cc @@ -163,7 +163,7 @@ struct SplitnetsPass : public Pass { } else { - for (auto &w : module->wires) { + for (auto &w : module->wires_) { RTLIL::Wire *wire = w.second; if (wire->width > 1 && (wire->port_id == 0 || flag_ports) && design->selected(module, w.second)) worker.splitmap[wire] = std::vector(); diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc index 834770071..fabf1a73f 100644 --- a/passes/cmds/stat.cc +++ b/passes/cmds/stat.cc @@ -69,7 +69,7 @@ namespace STAT_INT_MEMBERS #undef X - for (auto &it : mod->wires) + for (auto &it : mod->wires_) { if (!design->selected(mod, it.second)) continue; diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc index 55fe336f4..cb420f90a 100644 --- a/passes/fsm/fsm_detect.cc +++ b/passes/fsm/fsm_detect.cc @@ -173,11 +173,11 @@ struct FsmDetectPass : public Pass { } } - for (auto &wire_it : module->wires) + for (auto &wire_it : module->wires_) if (wire_it.second->port_id != 0) sig_at_port.add(assign_map(RTLIL::SigSpec(wire_it.second))); - for (auto &wire_it : module->wires) + for (auto &wire_it : module->wires_) if (design->selected(module, wire_it.second)) detect_fsm(wire_it.second); } diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index 51a4a75e7..85ff4af2a 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -283,10 +283,10 @@ static void extract_fsm(RTLIL::Wire *wire) // rename original state wire - module->wires.erase(wire->name); + module->wires_.erase(wire->name); wire->attributes.erase("\\fsm_encoding"); wire->name = stringf("$fsm$oldstate%s", wire->name.c_str()); - module->wires[wire->name] = wire; + module->wires_[wire->name] = wire; // unconnect control outputs from old drivers @@ -356,7 +356,7 @@ struct FsmExtractPass : public Pass { } std::vector wire_list; - for (auto &wire_it : module->wires) + for (auto &wire_it : module->wires_) if (wire_it.second->attributes.count("\\fsm_encoding") > 0 && wire_it.second->attributes["\\fsm_encoding"].decode_string() != "none") if (design->selected(module, wire_it.second)) wire_list.push_back(wire_it.second); diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 8c09d2eaa..a266c3445 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -221,15 +221,15 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla std::string portname = conn.first; if (portname.substr(0, 1) == "$") { int port_id = atoi(portname.substr(1).c_str()); - for (auto &wire_it : mod->wires) + for (auto &wire_it : mod->wires_) if (wire_it.second->port_id == port_id) { portname = wire_it.first; break; } } - if (mod->wires.count(portname) == 0) + if (mod->wires_.count(portname) == 0) log_error("Array cell `%s.%s' connects to unkown port `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(conn.first)); - int port_size = mod->wires.at(portname)->width; + int port_size = mod->wires_.at(portname)->width; if (conn_size == port_size) continue; if (conn_size != port_size*num) @@ -492,7 +492,7 @@ struct HierarchyPass : public Pass { } for (auto module : pos_mods) - for (auto &wire_it : module->wires) { + for (auto &wire_it : module->wires_) { RTLIL::Wire *wire = wire_it.second; if (wire->port_id > 0) pos_map[std::pair(module, wire->port_id)] = wire->name; diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index e39f96ca8..774aabae1 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -212,7 +212,7 @@ struct SubmodWorker if (opt_name.empty()) { - for (auto &it : module->wires) + for (auto &it : module->wires_) it.second->attributes.erase("\\submod"); for (auto &it : module->cells) diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index 32c7e63a0..4f1666533 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -131,7 +131,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) c->set("\\D", data_reg_in.back()); std::string w_out_name = stringf("%s[%d]", cell->parameters["\\MEMID"].decode_string().c_str(), i); - if (module->wires.count(w_out_name) > 0) + if (module->wires_.count(w_out_name) > 0) w_out_name = genid(cell->name, "", i, "$q"); RTLIL::Wire *w_out = module->addWire(w_out_name, mem_width); diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index df1a2697a..35a28d17d 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -137,7 +137,7 @@ struct MemoryShareWorker std::map> muxtree_upstream_map; std::set non_feedback_nets; - for (auto wire_it : module->wires) + for (auto wire_it : module->wires_) if (wire_it.second->port_output) { std::vector bits = RTLIL::SigSpec(wire_it.second); non_feedback_nets.insert(bits.begin(), bits.end()); diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 63d03b205..9542e10df 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -52,7 +52,7 @@ static void rmunused_module_cells(RTLIL::Module *module, bool verbose) unused.insert(cell); } - for (auto &it : module->wires) { + for (auto &it : module->wires_) { RTLIL::Wire *wire = it.second; if (wire->port_output || wire->get_bool_attribute("\\keep")) { std::set cell_list; @@ -175,12 +175,12 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool if (ct_all.cell_output(cell->type, it2.first)) direct_sigs.insert(assign_map(it2.second)); } - for (auto &it : module->wires) { + for (auto &it : module->wires_) { if (direct_sigs.count(assign_map(it.second)) || it.second->port_input) direct_wires.insert(it.second); } - for (auto &it : module->wires) { + for (auto &it : module->wires_) { RTLIL::Wire *wire = it.second; for (int i = 0; i < wire->width; i++) { RTLIL::SigBit s1 = RTLIL::SigBit(wire, i), s2 = assign_map(s1); @@ -202,7 +202,7 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool used_signals_nodrivers.add(it2.second); } } - for (auto &it : module->wires) { + for (auto &it : module->wires_) { RTLIL::Wire *wire = it.second; if (wire->port_id > 0) { RTLIL::SigSpec sig = RTLIL::SigSpec(wire); @@ -219,7 +219,7 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool } std::vector maybe_del_wires; - for (auto &it : module->wires) { + for (auto &it : module->wires_) { RTLIL::Wire *wire = it.second; if ((!purge_mode && check_public_name(wire->name)) || wire->port_id != 0 || wire->get_bool_attribute("\\keep")) { RTLIL::SigSpec s1 = RTLIL::SigSpec(wire), s2 = s1; diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index 672186006..290d4ffd9 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -45,7 +45,7 @@ static void replace_undriven(RTLIL::Design *design, RTLIL::Module *module) used_signals.add(sigmap(conn.second)); } - for (auto &it : module->wires) { + for (auto &it : module->wires_) { if (it.second->port_input) driven_signals.add(sigmap(it.second)); if (it.second->port_output) diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc index 8487152ff..16dedef58 100644 --- a/passes/opt/opt_muxtree.cc +++ b/passes/opt/opt_muxtree.cc @@ -136,7 +136,7 @@ struct OptMuxtreeWorker } } } - for (auto &it : module->wires) { + for (auto &it : module->wires_) { if (it.second->port_output) for (int idx : sig2bits(RTLIL::SigSpec(it.second))) bit2info[idx].seen_non_mux = true; diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc index 8c09f5414..b26e8b37e 100644 --- a/passes/opt/opt_rmdff.cc +++ b/passes/opt/opt_rmdff.cc @@ -173,7 +173,7 @@ struct OptRmdffPass : public Pass { assign_map.set(mod_it.second); dff_init_map.set(mod_it.second); - for (auto &it : mod_it.second->wires) + for (auto &it : mod_it.second->wires_) if (it.second->attributes.count("\\init") != 0) dff_init_map.add(it.second, it.second->attributes.at("\\init")); mux_drivers.clear(); diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc index 4f733a373..c91f037d4 100644 --- a/passes/opt/opt_share.cc +++ b/passes/opt/opt_share.cc @@ -237,7 +237,7 @@ struct OptShareWorker assign_map.set(module); dff_init_map.set(module); - for (auto &it : module->wires) + for (auto &it : module->wires_) if (it.second->attributes.count("\\init") != 0) dff_init_map.add(it.second, it.second->attributes.at("\\init")); diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc index 114f2567e..565d86a72 100644 --- a/passes/proc/proc_arst.cc +++ b/passes/proc/proc_arst.cc @@ -243,7 +243,7 @@ struct ProcArstPass : public Pass { if (!design->selected(mod_it.second, proc_it.second)) continue; proc_arst(mod_it.second, proc_it.second, assign_map); - if (global_arst.empty() || mod_it.second->wires.count(global_arst) == 0) + if (global_arst.empty() || mod_it.second->wires_.count(global_arst) == 0) continue; std::vector arst_actions; for (auto sync : proc_it.second->syncs) @@ -266,7 +266,7 @@ struct ProcArstPass : public Pass { if (!arst_actions.empty()) { RTLIL::SyncRule *sync = new RTLIL::SyncRule; sync->type = global_arst_neg ? RTLIL::SyncType::ST0 : RTLIL::SyncType::ST1; - sync->signal = mod_it.second->wires.at(global_arst); + sync->signal = mod_it.second->wires_.at(global_arst); sync->actions = arst_actions; proc_it.second->syncs.push_back(sync); } diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc index 6949b76db..d4ff2a86c 100644 --- a/passes/sat/eval.cc +++ b/passes/sat/eval.cc @@ -87,16 +87,16 @@ struct BruteForceEquivChecker mod1(mod1), mod2(mod2), counter(0), errors(0), ignore_x_mod1(ignore_x_mod1) { log("Checking for equivialence (brute-force): %s vs %s\n", mod1->name.c_str(), mod2->name.c_str()); - for (auto &w : mod1->wires) + for (auto &w : mod1->wires_) { RTLIL::Wire *wire1 = w.second; if (wire1->port_id == 0) continue; - if (mod2->wires.count(wire1->name) == 0) + if (mod2->wires_.count(wire1->name) == 0) log_cmd_error("Port %s in module 1 has no counterpart in module 2!\n", wire1->name.c_str()); - RTLIL::Wire *wire2 = mod2->wires.at(wire1->name); + RTLIL::Wire *wire2 = mod2->wires_.at(wire1->name); if (wire1->width != wire2->width || wire1->port_input != wire2->port_input || wire1->port_output != wire2->port_output) log_cmd_error("Port %s in module 1 does not match its counterpart in module 2!\n", wire1->name.c_str()); @@ -153,11 +153,11 @@ struct VlogHammerReporter ez.assume(satgen.signals_eq(recorded_set_vars, recorded_set_vals)); - std::vector y_vec = satgen.importDefSigSpec(module->wires.at("\\y")); + std::vector y_vec = satgen.importDefSigSpec(module->wires_.at("\\y")); std::vector y_values; if (model_undef) { - std::vector y_undef_vec = satgen.importUndefSigSpec(module->wires.at("\\y")); + std::vector y_undef_vec = satgen.importUndefSigSpec(module->wires_.at("\\y")); y_vec.insert(y_vec.end(), y_undef_vec.begin(), y_undef_vec.end()); } @@ -252,7 +252,7 @@ struct VlogHammerReporter std::vector bits(patterns[idx].bits.begin(), patterns[idx].bits.begin() + total_input_width); for (int i = 0; i < int(inputs.size()); i++) { - RTLIL::Wire *wire = module->wires.at(inputs[i]); + RTLIL::Wire *wire = module->wires_.at(inputs[i]); for (int j = input_widths[i]-1; j >= 0; j--) { ce.set(RTLIL::SigSpec(wire, j), bits.back()); recorded_set_vars.append(RTLIL::SigSpec(wire, j)); @@ -268,10 +268,10 @@ struct VlogHammerReporter } } - if (module->wires.count("\\y") == 0) + if (module->wires_.count("\\y") == 0) log_error("No output wire (y) found in module %s!\n", RTLIL::id2cstr(module->name)); - RTLIL::SigSpec sig(module->wires.at("\\y")); + RTLIL::SigSpec sig(module->wires_.at("\\y")); RTLIL::SigSpec undef; while (!ce.eval(sig, undef)) { @@ -318,9 +318,9 @@ struct VlogHammerReporter int width = -1; RTLIL::IdString esc_name = RTLIL::escape_id(name); for (auto mod : modules) { - if (mod->wires.count(esc_name) == 0) + if (mod->wires_.count(esc_name) == 0) log_error("Can't find input %s in module %s!\n", name.c_str(), RTLIL::id2cstr(mod->name)); - RTLIL::Wire *port = mod->wires.at(esc_name); + RTLIL::Wire *port = mod->wires_.at(esc_name); if (!port->port_input || port->port_output) log_error("Wire %s in module %s is not an input!\n", name.c_str(), RTLIL::id2cstr(mod->name)); if (width >= 0 && width != port->width) @@ -469,7 +469,7 @@ struct EvalPass : public Pass { } if (shows.size() == 0) { - for (auto &it : module->wires) + for (auto &it : module->wires_) if (it.second->port_output) shows.push_back(it.second->name); } diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc index 21af63a36..c30e6e0c8 100644 --- a/passes/sat/expose.cc +++ b/passes/sat/expose.cc @@ -87,7 +87,7 @@ static void find_dff_wires(std::set &dff_wires, RTLIL::Module *modu dffsignals.add(sigmap(it.second->get("\\Q"))); } - for (auto &it : module->wires) { + for (auto &it : module->wires_) { if (dffsignals.check_any(it.second)) dff_wires.insert(it.first); } @@ -161,7 +161,7 @@ static void create_dff_dq_map(std::map &map, RTLIL: } std::map empty_dq_map; - for (auto &it : module->wires) + for (auto &it : module->wires_) { if (!consider_wire(it.second, empty_dq_map)) continue; @@ -321,7 +321,7 @@ struct ExposePass : public Pass { for (auto &it : shared_dff_wires) { if (!dff_dq_maps[mod_it.second].count(it)) continue; - if (!compare_wires(first_module->wires.at(it), mod_it.second->wires.at(it))) + if (!compare_wires(first_module->wires_.at(it), mod_it.second->wires_.at(it))) continue; new_shared_dff_wires.insert(it); } @@ -365,7 +365,7 @@ struct ExposePass : public Pass { if (first_module == NULL) { - for (auto &it : module->wires) + for (auto &it : module->wires_) if (design->selected(module, it.second) && consider_wire(it.second, dff_dq_maps[module])) if (!flag_dff || dff_wires.count(it.first)) shared_wires.insert(it.first); @@ -385,16 +385,16 @@ struct ExposePass : public Pass { { RTLIL::Wire *wire; - if (module->wires.count(it) == 0) + if (module->wires_.count(it) == 0) goto delete_shared_wire; - wire = module->wires.at(it); + wire = module->wires_.at(it); if (!design->selected(module, wire)) goto delete_shared_wire; if (!consider_wire(wire, dff_dq_maps[module])) goto delete_shared_wire; - if (!compare_wires(first_module->wires.at(it), wire)) + if (!compare_wires(first_module->wires_.at(it), wire)) goto delete_shared_wire; if (flag_dff && !dff_wires.count(it)) goto delete_shared_wire; @@ -449,7 +449,7 @@ struct ExposePass : public Pass { SigMap out_to_in_map; - for (auto &it : module->wires) + for (auto &it : module->wires_) { if (flag_shared) { if (shared_wires.count(it.first) == 0) @@ -491,10 +491,10 @@ struct ExposePass : public Pass { for (auto &dq : dff_dq_maps[module]) { - if (!module->wires.count(dq.first)) + if (!module->wires_.count(dq.first)) continue; - RTLIL::Wire *wire = module->wires.at(dq.first); + RTLIL::Wire *wire = module->wires_.at(dq.first); std::set wire_bits_set = sigmap(wire).to_sigbit_set(); std::vector wire_bits_vec = sigmap(wire).to_sigbit_vector(); @@ -587,7 +587,7 @@ struct ExposePass : public Pass { { RTLIL::Module *mod = design->modules.at(cell->type); - for (auto &it : mod->wires) + for (auto &it : mod->wires_) { RTLIL::Wire *p = it.second; if (!p->port_input && !p->port_output) diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index d5336ca01..5d23318ce 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -602,7 +602,7 @@ struct FreduceWorker int bits_full_total = 0; std::vector> batches; - for (auto &it : module->wires) + for (auto &it : module->wires_) if (it.second->port_input) { batches.push_back(sigmap(it.second).to_sigbit_set()); bits_full_total += it.second->width; diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index 0c5989b10..248f934c5 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -73,13 +73,13 @@ static void create_miter_equiv(struct Pass *that, std::vector args, RTLIL::Module *gold_module = design->modules.at(gold_name); RTLIL::Module *gate_module = design->modules.at(gate_name); - for (auto &it : gold_module->wires) { + for (auto &it : gold_module->wires_) { RTLIL::Wire *w1 = it.second, *w2; if (w1->port_id == 0) continue; - if (gate_module->wires.count(it.second->name) == 0) + if (gate_module->wires_.count(it.second->name) == 0) goto match_gold_port_error; - w2 = gate_module->wires.at(it.second->name); + w2 = gate_module->wires_.at(it.second->name); if (w1->port_input != w2->port_input) goto match_gold_port_error; if (w1->port_output != w2->port_output) @@ -91,13 +91,13 @@ static void create_miter_equiv(struct Pass *that, std::vector args, log_cmd_error("No matching port in gate module was found for %s!\n", it.second->name.c_str()); } - for (auto &it : gate_module->wires) { + for (auto &it : gate_module->wires_) { RTLIL::Wire *w1 = it.second, *w2; if (w1->port_id == 0) continue; - if (gold_module->wires.count(it.second->name) == 0) + if (gold_module->wires_.count(it.second->name) == 0) goto match_gate_port_error; - w2 = gold_module->wires.at(it.second->name); + w2 = gold_module->wires_.at(it.second->name); if (w1->port_input != w2->port_input) goto match_gate_port_error; if (w1->port_output != w2->port_output) @@ -120,7 +120,7 @@ static void create_miter_equiv(struct Pass *that, std::vector args, RTLIL::SigSpec all_conditions; - for (auto &it : gold_module->wires) + for (auto &it : gold_module->wires_) { RTLIL::Wire *w1 = it.second; diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 71eba2f7f..90c671165 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -94,7 +94,7 @@ struct SatHelper RTLIL::SigSpec big_lhs, big_rhs; - for (auto &it : module->wires) + for (auto &it : module->wires_) { if (it.second->attributes.count("\\init") == 0) continue; @@ -1158,19 +1158,19 @@ struct SatPass : public Pass { log_cmd_error("The options -set-init-undef, -set-init-def, and -set-init-zero are exclusive!\n"); if (set_def_inputs) { - for (auto &it : module->wires) + for (auto &it : module->wires_) if (it.second->port_input) sets_def.push_back(it.second->name); } if (show_inputs) { - for (auto &it : module->wires) + for (auto &it : module->wires_) if (it.second->port_input) shows.push_back(it.second->name); } if (show_outputs) { - for (auto &it : module->wires) + for (auto &it : module->wires_) if (it.second->port_output) shows.push_back(it.second->name); } diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index 92bcafc00..813e0e3e1 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -271,7 +271,7 @@ namespace } // mark external signals (used in module ports) - for (auto &wire_it : mod->wires) + for (auto &wire_it : mod->wires_) { RTLIL::Wire *wire = wire_it.second; if (wire->port_id > 0) @@ -300,7 +300,7 @@ namespace RTLIL::Cell *cell = haystack->addCell(stringf("$extract$%s$%d", needle->name.c_str(), RTLIL::autoidx++), needle->name); // create cell ports - for (auto &it : needle->wires) { + for (auto &it : needle->wires_) { RTLIL::Wire *wire = it.second; if (wire->port_id > 0) { for (int i = 0; i < wire->width; i++) @@ -742,7 +742,7 @@ struct ExtractPass : public Pass { std::vector chunks = sigmap(conn.second); for (auto &chunk : chunks) if (chunk.wire != NULL) - chunk.wire = newMod->wires.at(chunk.wire->name); + chunk.wire = newMod->wires_.at(chunk.wire->name); newCell->set(conn.first, chunks); } } diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc index ab3bb3ed0..6f7427f03 100644 --- a/passes/techmap/iopadmap.cc +++ b/passes/techmap/iopadmap.cc @@ -118,7 +118,7 @@ struct IopadmapPass : public Pass { if (!design->selected(module) || module->get_bool_attribute("\\blackbox")) continue; - for (auto &it2 : module->wires) + for (auto &it2 : module->wires_) { RTLIL::Wire *wire = it2.second; diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index bee1df406..03aac6693 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -46,8 +46,8 @@ static void apply_prefix(std::string prefix, RTLIL::SigSpec &sig, RTLIL::Module if (chunk.wire != NULL) { std::string wire_name = chunk.wire->name; apply_prefix(prefix, wire_name); - assert(module->wires.count(wire_name) > 0); - chunk.wire = module->wires[wire_name]; + assert(module->wires_.count(wire_name) > 0); + chunk.wire = module->wires_[wire_name]; } sig = chunks; } @@ -72,7 +72,7 @@ struct TechmapWorker if (module == NULL) return result; - for (auto &it : module->wires) { + for (auto &it : module->wires_) { const char *p = it.first.c_str(); if (*p == '$') continue; @@ -125,7 +125,7 @@ struct TechmapWorker std::map positional_ports; - for (auto &it : tpl->wires) { + for (auto &it : tpl->wires_) { if (it.second->port_id > 0) positional_ports[stringf("$%d", it.second->port_id)] = it.first; std::string w_name = it.second->name; @@ -145,12 +145,12 @@ struct TechmapWorker RTLIL::IdString portname = it.first; if (positional_ports.count(portname) > 0) portname = positional_ports.at(portname); - if (tpl->wires.count(portname) == 0 || tpl->wires.at(portname)->port_id == 0) { + if (tpl->wires_.count(portname) == 0 || tpl->wires_.at(portname)->port_id == 0) { if (portname.substr(0, 1) == "$") log_error("Can't map port `%s' of cell `%s' to template `%s'!\n", portname.c_str(), cell->name.c_str(), tpl->name.c_str()); continue; } - RTLIL::Wire *w = tpl->wires.at(portname); + RTLIL::Wire *w = tpl->wires_.at(portname); RTLIL::SigSig c; if (w->port_output) { c.first = it.second; @@ -265,7 +265,7 @@ struct TechmapWorker for (auto conn : cell->connections()) { if (conn.first.substr(0, 1) == "$") continue; - if (tpl->wires.count(conn.first) > 0 && tpl->wires.at(conn.first)->port_id > 0) + if (tpl->wires_.count(conn.first) > 0 && tpl->wires_.at(conn.first)->port_id > 0) continue; if (!conn.second.is_fully_const() || parameters.count(conn.first) > 0 || tpl->avail_parameters.count(conn.first) == 0) goto next_tpl; @@ -388,7 +388,7 @@ struct TechmapWorker assert(!strncmp(q, "_TECHMAP_DO_", 12)); std::string new_name = data.wire->name.substr(0, q-p) + "_TECHMAP_DONE_" + data.wire->name.substr(q-p+12); - while (tpl->wires.count(new_name)) + while (tpl->wires_.count(new_name)) new_name += "_"; tpl->rename(data.wire, new_name); -- cgit v1.2.3 From 4c4b6021562c598c4510831bd547edaa97d14dac Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 01:51:45 +0200 Subject: Refactoring: Renamed RTLIL::Module::cells to cells_ --- passes/abc/abc.cc | 12 ++++++------ passes/cmds/add.cc | 2 +- passes/cmds/connect.cc | 6 +++--- passes/cmds/connwrappers.cc | 4 ++-- passes/cmds/delete.cc | 2 +- passes/cmds/rename.cc | 10 +++++----- passes/cmds/scatter.cc | 2 +- passes/cmds/scc.cc | 2 +- passes/cmds/select.cc | 28 ++++++++++++++-------------- passes/cmds/setattr.cc | 4 ++-- passes/cmds/setundef.cc | 2 +- passes/cmds/show.cc | 6 +++--- passes/cmds/splice.cc | 4 ++-- passes/cmds/splitnets.cc | 2 +- passes/cmds/stat.cc | 2 +- passes/fsm/fsm_detect.cc | 2 +- passes/fsm/fsm_expand.cc | 4 ++-- passes/fsm/fsm_export.cc | 2 +- passes/fsm/fsm_extract.cc | 10 +++++----- passes/fsm/fsm_info.cc | 2 +- passes/fsm/fsm_map.cc | 2 +- passes/fsm/fsm_opt.cc | 2 +- passes/fsm/fsm_recode.cc | 2 +- passes/hierarchy/hierarchy.cc | 10 +++++----- passes/hierarchy/submod.cc | 6 +++--- passes/memory/memory_collect.cc | 2 +- passes/memory/memory_dff.cc | 6 +++--- passes/memory/memory_map.cc | 2 +- passes/memory/memory_share.cc | 4 ++-- passes/memory/memory_unpack.cc | 4 ++-- passes/opt/opt_clean.cc | 8 ++++---- passes/opt/opt_const.cc | 6 +++--- passes/opt/opt_muxtree.cc | 2 +- passes/opt/opt_reduce.cc | 10 +++++----- passes/opt/opt_rmdff.cc | 6 +++--- passes/opt/opt_share.cc | 4 ++-- passes/proc/proc_arst.cc | 2 +- passes/sat/eval.cc | 2 +- passes/sat/expose.cc | 18 +++++++++--------- passes/sat/freduce.cc | 2 +- passes/sat/sat.cc | 2 +- passes/sat/share.cc | 4 ++-- passes/techmap/dfflibmap.cc | 2 +- passes/techmap/extract.cc | 6 +++--- passes/techmap/simplemap.cc | 2 +- passes/techmap/techmap.cc | 10 +++++----- 46 files changed, 117 insertions(+), 117 deletions(-) (limited to 'passes') diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index 184f143a1..7ba9424e8 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -462,7 +462,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std int best_dff_counter = 0; std::map, int> dff_counters; - for (auto &it : module->cells) + for (auto &it : module->cells_) { RTLIL::Cell *cell = it.second; if (cell->type != "$_DFF_N_" && cell->type != "$_DFF_P_") @@ -488,8 +488,8 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std mark_port(clk_sig); std::vector cells; - cells.reserve(module->cells.size()); - for (auto &it : module->cells) + cells.reserve(module->cells_.size()); + for (auto &it : module->cells_) if (design->selected(current_module, it.second)) cells.push_back(it.second); for (auto c : cells) @@ -500,7 +500,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std mark_port(RTLIL::SigSpec(wire_it.second)); } - for (auto &cell_it : module->cells) + for (auto &cell_it : module->cells_) for (auto &port_it : cell_it.second->connections()) mark_port(port_it.second); @@ -696,7 +696,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std std::map cell_stats; if (builtin_lib) { - for (auto &it : mapped_mod->cells) { + for (auto &it : mapped_mod->cells_) { RTLIL::Cell *c = it.second; cell_stats[RTLIL::unescape_id(c->type)]++; if (c->type == "\\ZERO" || c->type == "\\ONE") { @@ -751,7 +751,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std } else { - for (auto &it : mapped_mod->cells) + for (auto &it : mapped_mod->cells_) { RTLIL::Cell *c = it.second; cell_stats[RTLIL::unescape_id(c->type)]++; diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc index e97bf8fc1..49aa7c98d 100644 --- a/passes/cmds/add.cc +++ b/passes/cmds/add.cc @@ -62,7 +62,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n if (!flag_global) return; - for (auto &it : module->cells) + for (auto &it : module->cells_) { if (design->modules.count(it.second->type) == 0) continue; diff --git a/passes/cmds/connect.cc b/passes/cmds/connect.cc index 99a28d4a0..6494ea6f6 100644 --- a/passes/cmds/connect.cc +++ b/passes/cmds/connect.cc @@ -29,7 +29,7 @@ static void unset_drivers(RTLIL::Design *design, RTLIL::Module *module, SigMap & RTLIL::Wire *dummy_wire = module->addWire(NEW_ID, sig.size()); - for (auto &it : module->cells) + for (auto &it : module->cells_) for (auto &port : it.second->connections_) if (ct.cell_output(it.second->type, port.first)) sigmap(port.second).replace(sig, dummy_wire, &port.second); @@ -169,14 +169,14 @@ struct ConnectPass : public Pass { if (flag_nounset) log_cmd_error("Cant use -port together with -nounset.\n"); - if (module->cells.count(RTLIL::escape_id(port_cell)) == 0) + if (module->cells_.count(RTLIL::escape_id(port_cell)) == 0) log_cmd_error("Can't find cell %s.\n", port_cell.c_str()); RTLIL::SigSpec sig; if (!RTLIL::SigSpec::parse_sel(sig, design, module, port_expr)) log_cmd_error("Failed to parse port expression `%s'.\n", port_expr.c_str()); - module->cells.at(RTLIL::escape_id(port_cell))->set(RTLIL::escape_id(port_port), sigmap(sig)); + module->cells_.at(RTLIL::escape_id(port_cell))->set(RTLIL::escape_id(port_port), sigmap(sig)); } else log_cmd_error("Expected -set, -unset, or -port.\n"); diff --git a/passes/cmds/connwrappers.cc b/passes/cmds/connwrappers.cc index 9faeffafa..cc8147c53 100644 --- a/passes/cmds/connwrappers.cc +++ b/passes/cmds/connwrappers.cc @@ -67,7 +67,7 @@ struct ConnwrappersWorker std::map> extend_map; SigMap sigmap(module); - for (auto &it : module->cells) + for (auto &it : module->cells_) { RTLIL::Cell *cell = it.second; @@ -102,7 +102,7 @@ struct ConnwrappersWorker } } - for (auto &it : module->cells) + for (auto &it : module->cells_) { RTLIL::Cell *cell = it.second; diff --git a/passes/cmds/delete.cc b/passes/cmds/delete.cc index 460dd9663..2c2c370dd 100644 --- a/passes/cmds/delete.cc +++ b/passes/cmds/delete.cc @@ -103,7 +103,7 @@ struct DeletePass : public Pass { if (design->selected(module, it.second)) delete_mems.insert(it.first); - for (auto &it : module->cells) { + for (auto &it : module->cells_) { if (design->selected(module, it.second)) delete_cells.insert(it.second); if ((it.second->type == "$memrd" || it.second->type == "$memwr") && diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc index e163e7243..c8b8160f1 100644 --- a/passes/cmds/rename.cc +++ b/passes/cmds/rename.cc @@ -36,7 +36,7 @@ static void rename_in_module(RTLIL::Module *module, std::string from_name, std:: return; } - for (auto &it : module->cells) + for (auto &it : module->cells_) if (it.first == from_name) { log("Renaming cell %s to %s in module %s.\n", log_id(it.second), log_id(to_name), log_id(module)); module->rename(it.second, to_name); @@ -114,13 +114,13 @@ struct RenamePass : public Pass { module->wires_.swap(new_wires); std::map new_cells; - for (auto &it : module->cells) { + for (auto &it : module->cells_) { if (it.first[0] == '$' && design->selected(module, it.second)) do it.second->name = stringf("\\_%d_", counter++); while (module->count_id(it.second->name) > 0); new_cells[it.second->name] = it.second; } - module->cells.swap(new_cells); + module->cells_.swap(new_cells); } } else @@ -144,13 +144,13 @@ struct RenamePass : public Pass { module->wires_.swap(new_wires); std::map new_cells; - for (auto &it : module->cells) { + for (auto &it : module->cells_) { if (design->selected(module, it.second)) if (it.first[0] == '\\') it.second->name = NEW_ID; new_cells[it.second->name] = it.second; } - module->cells.swap(new_cells); + module->cells_.swap(new_cells); } } else diff --git a/passes/cmds/scatter.cc b/passes/cmds/scatter.cc index 0b95fe024..a1c12f1ee 100644 --- a/passes/cmds/scatter.cc +++ b/passes/cmds/scatter.cc @@ -48,7 +48,7 @@ struct ScatterPass : public Pass { if (!design->selected(mod_it.second)) continue; - for (auto &c : mod_it.second->cells) + for (auto &c : mod_it.second->cells_) for (auto &p : c.second->connections_) { RTLIL::Wire *wire = mod_it.second->addWire(NEW_ID, p.second.size()); diff --git a/passes/cmds/scc.cc b/passes/cmds/scc.cc index 7e2b2fc9f..c95043417 100644 --- a/passes/cmds/scc.cc +++ b/passes/cmds/scc.cc @@ -118,7 +118,7 @@ struct SccWorker if (design->selected(module, it.second)) selectedSignals.add(sigmap(RTLIL::SigSpec(it.second))); - for (auto &it : module->cells) + for (auto &it : module->cells_) { RTLIL::Cell *cell = it.second; diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index 0cabdc06b..306b7a5b1 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -167,7 +167,7 @@ static void select_op_neg(RTLIL::Design *design, RTLIL::Selection &lhs) for (auto &it : mod->memories) if (!lhs.selected_member(mod_it.first, it.first)) new_sel.selected_members[mod->name].insert(it.first); - for (auto &it : mod->cells) + for (auto &it : mod->cells_) if (!lhs.selected_member(mod_it.first, it.first)) new_sel.selected_members[mod->name].insert(it.first); for (auto &it : mod->processes) @@ -185,7 +185,7 @@ static void select_op_submod(RTLIL::Design *design, RTLIL::Selection &lhs) { if (lhs.selected_whole_module(mod_it.first)) { - for (auto &cell_it : mod_it.second->cells) + for (auto &cell_it : mod_it.second->cells_) { if (design->modules.count(cell_it.second->type) == 0) continue; @@ -282,7 +282,7 @@ static void select_op_diff(RTLIL::Design *design, RTLIL::Selection &lhs, const R lhs.selected_members[mod->name].insert(it.first); for (auto &it : mod->memories) lhs.selected_members[mod->name].insert(it.first); - for (auto &it : mod->cells) + for (auto &it : mod->cells_) lhs.selected_members[mod->name].insert(it.first); for (auto &it : mod->processes) lhs.selected_members[mod->name].insert(it.first); @@ -395,7 +395,7 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v } } - for (auto &cell : mod->cells) + for (auto &cell : mod->cells_) for (auto &conn : cell.second->connections()) { char last_mode = '-'; @@ -742,12 +742,12 @@ static void select_stmt(RTLIL::Design *design, std::string arg) sel.selected_members[mod->name].insert(it.first); } else if (arg_memb.substr(0, 2) == "c:") { - for (auto &it : mod->cells) + for (auto &it : mod->cells_) if (match_ids(it.first, arg_memb.substr(2))) sel.selected_members[mod->name].insert(it.first); } else if (arg_memb.substr(0, 2) == "t:") { - for (auto &it : mod->cells) + for (auto &it : mod->cells_) if (match_ids(it.second->type, arg_memb.substr(2))) sel.selected_members[mod->name].insert(it.first); } else @@ -763,7 +763,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg) for (auto &it : mod->memories) if (match_attr(it.second->attributes, arg_memb.substr(2))) sel.selected_members[mod->name].insert(it.first); - for (auto &it : mod->cells) + for (auto &it : mod->cells_) if (match_attr(it.second->attributes, arg_memb.substr(2))) sel.selected_members[mod->name].insert(it.first); for (auto &it : mod->processes) @@ -771,7 +771,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg) sel.selected_members[mod->name].insert(it.first); } else if (arg_memb.substr(0, 2) == "r:") { - for (auto &it : mod->cells) + for (auto &it : mod->cells_) if (match_attr(it.second->parameters, arg_memb.substr(2))) sel.selected_members[mod->name].insert(it.first); } else { @@ -783,7 +783,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg) for (auto &it : mod->memories) if (match_ids(it.first, arg_memb)) sel.selected_members[mod->name].insert(it.first); - for (auto &it : mod->cells) + for (auto &it : mod->cells_) if (match_ids(it.first, arg_memb)) sel.selected_members[mod->name].insert(it.first); for (auto &it : mod->processes) @@ -1158,7 +1158,7 @@ struct SelectPass : public Pass { for (auto &it : mod_it.second->memories) if (sel->selected_member(mod_it.first, it.first)) LOG_OBJECT("%s/%s\n", id2cstr(mod_it.first), id2cstr(it.first)); - for (auto &it : mod_it.second->cells) + for (auto &it : mod_it.second->cells_) if (sel->selected_member(mod_it.first, it.first)) LOG_OBJECT("%s/%s\n", id2cstr(mod_it.first), id2cstr(it.first)); for (auto &it : mod_it.second->processes) @@ -1225,7 +1225,7 @@ struct SelectPass : public Pass { for (auto &it : mod_it.second->memories) if (sel->selected_member(mod_it.first, it.first)) total_count++; - for (auto &it : mod_it.second->cells) + for (auto &it : mod_it.second->cells_) if (sel->selected_member(mod_it.first, it.first)) total_count++; for (auto &it : mod_it.second->processes) @@ -1303,8 +1303,8 @@ struct CdPass : public Pass { RTLIL::Module *module = NULL; if (design->modules.count(design->selected_active_module) > 0) module = design->modules.at(design->selected_active_module); - if (module != NULL && module->cells.count(modname) > 0) - modname = module->cells.at(modname)->type; + if (module != NULL && module->cells_.count(modname) > 0) + modname = module->cells_.at(modname)->type; } if (design->modules.count(modname) > 0) { @@ -1376,7 +1376,7 @@ struct LsPass : public Pass { RTLIL::Module *module = design->modules.at(design->selected_active_module); counter += log_matches("wires", pattern, module->wires_); counter += log_matches("memories", pattern, module->memories); - counter += log_matches("cells", pattern, module->cells); + counter += log_matches("cells", pattern, module->cells_); counter += log_matches("processes", pattern, module->processes); } diff --git a/passes/cmds/setattr.cc b/passes/cmds/setattr.cc index 0b4f2a8a2..ea5221f6d 100644 --- a/passes/cmds/setattr.cc +++ b/passes/cmds/setattr.cc @@ -119,7 +119,7 @@ struct SetattrPass : public Pass { if (design->selected(module, it.second)) do_setunset(it.second->attributes, setunset_list); - for (auto &it : module->cells) + for (auto &it : module->cells_) if (design->selected(module, it.second)) do_setunset(it.second->attributes, setunset_list); @@ -171,7 +171,7 @@ struct SetparamPass : public Pass { if (!design->selected(module)) continue; - for (auto &it : module->cells) + for (auto &it : module->cells_) if (design->selected(module, it.second)) do_setunset(it.second->parameters, setunset_list); } diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index 82dc1d999..e7779415d 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -134,7 +134,7 @@ struct SetundefPass : public Pass { undriven_signals.add(sigmap(it.second)); CellTypes ct(design); - for (auto &it : module->cells) + for (auto &it : module->cells_) for (auto &conn : it.second->connections()) if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first)) undriven_signals.del(sigmap(conn.second)); diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index 1feb90afb..18af8dfce 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -337,7 +337,7 @@ struct ShowWorker fprintf(f, "}\n"); } - for (auto &it : module->cells) + for (auto &it : module->cells_) { if (!design->selected_member(module->name, it.first)) continue; @@ -516,7 +516,7 @@ struct ShowWorker log("Skipping blackbox module %s.\n", id2cstr(module->name)); continue; } else - if (module->cells.empty() && module->connections().empty() && module->processes.empty()) { + if (module->cells_.empty() && module->connections().empty() && module->processes.empty()) { log("Skipping empty module %s.\n", id2cstr(module->name)); continue; } else @@ -695,7 +695,7 @@ struct ShowPass : public Pass { for (auto &mod_it : design->modules) { if (mod_it.second->get_bool_attribute("\\blackbox")) continue; - if (mod_it.second->cells.empty() && mod_it.second->connections().empty()) + if (mod_it.second->cells_.empty() && mod_it.second->connections().empty()) continue; if (design->selected_module(mod_it.first)) modcount++; diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc index 691d972cf..dcd2f819f 100644 --- a/passes/cmds/splice.cc +++ b/passes/cmds/splice.cc @@ -158,7 +158,7 @@ struct SpliceWorker driven_bits.push_back(RTLIL::State::Sm); } - for (auto &it : module->cells) + for (auto &it : module->cells_) for (auto &conn : it.second->connections()) if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first)) { RTLIL::SigSpec sig = sigmap(conn.second); @@ -179,7 +179,7 @@ struct SpliceWorker if (design->selected(module, it.second)) selected_bits.add(sigmap(it.second)); - for (auto &it : module->cells) { + for (auto &it : module->cells_) { if (!sel_by_wire && !design->selected(module, it.second)) continue; for (auto &conn : it.second->connections_) diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc index accb178ba..0998a1622 100644 --- a/passes/cmds/splitnets.cc +++ b/passes/cmds/splitnets.cc @@ -131,7 +131,7 @@ struct SplitnetsPass : public Pass { std::map> split_wires_at; - for (auto &c : module->cells) + for (auto &c : module->cells_) for (auto &p : c.second->connections()) { if (!ct.cell_known(c.second->type)) diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc index fabf1a73f..153226ab5 100644 --- a/passes/cmds/stat.cc +++ b/passes/cmds/stat.cc @@ -90,7 +90,7 @@ namespace num_memory_bits += it.second->width * it.second->size; } - for (auto &it : mod->cells) { + for (auto &it : mod->cells_) { if (!design->selected(mod, it.second)) continue; num_cells++; diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc index cb420f90a..e1528f31d 100644 --- a/passes/fsm/fsm_detect.cc +++ b/passes/fsm/fsm_detect.cc @@ -159,7 +159,7 @@ struct FsmDetectPass : public Pass { sig2driver.clear(); sig2user.clear(); sig_at_port.clear(); - for (auto &cell_it : module->cells) + for (auto &cell_it : module->cells_) for (auto &conn_it : cell_it.second->connections()) { if (ct.cell_output(cell_it.second->type, conn_it.first) || !ct.cell_known(cell_it.second->type)) { RTLIL::SigSpec sig = conn_it.second; diff --git a/passes/fsm/fsm_expand.cc b/passes/fsm/fsm_expand.cc index 186ea2fd4..40ec55c11 100644 --- a/passes/fsm/fsm_expand.cc +++ b/passes/fsm/fsm_expand.cc @@ -205,7 +205,7 @@ struct FsmExpand assign_map.set(module); ct.setup_internals(); - for (auto &cell_it : module->cells) { + for (auto &cell_it : module->cells_) { RTLIL::Cell *c = cell_it.second; if (ct.cell_known(c->type) && design->selected(mod, c)) for (auto &p : c->connections()) { @@ -262,7 +262,7 @@ struct FsmExpandPass : public Pass { if (!design->selected(mod_it.second)) continue; std::vector fsm_cells; - for (auto &cell_it : mod_it.second->cells) + for (auto &cell_it : mod_it.second->cells_) if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second)) fsm_cells.push_back(cell_it.second); for (auto c : fsm_cells) { diff --git a/passes/fsm/fsm_export.cc b/passes/fsm/fsm_export.cc index cc328ce34..129e7f9a6 100644 --- a/passes/fsm/fsm_export.cc +++ b/passes/fsm/fsm_export.cc @@ -176,7 +176,7 @@ struct FsmExportPass : public Pass { for (auto &mod_it : design->modules) if (design->selected(mod_it.second)) - for (auto &cell_it : mod_it.second->cells) + for (auto &cell_it : mod_it.second->cells_) if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second)) { attr_it = cell_it.second->attributes.find("\\fsm_export"); if (!flag_noauto || (attr_it != cell_it.second->attributes.end())) { diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index 85ff4af2a..64b01064a 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -53,7 +53,7 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL std::set cellport_list; sig2driver.find(sig, cellport_list); for (auto &cellport : cellport_list) { - RTLIL::Cell *cell = module->cells.at(cellport.first); + RTLIL::Cell *cell = module->cells_.at(cellport.first); if ((cell->type != "$mux" && cell->type != "$pmux" && cell->type != "$safe_pmux") || cellport.second != "\\Y") { log(" unexpected cell type %s (%s) found in state selection tree.\n", cell->type.c_str(), cell->name.c_str()); return false; @@ -179,7 +179,7 @@ static void extract_fsm(RTLIL::Wire *wire) std::set cellport_list; sig2driver.find(dff_out, cellport_list); for (auto &cellport : cellport_list) { - RTLIL::Cell *cell = module->cells.at(cellport.first); + RTLIL::Cell *cell = module->cells_.at(cellport.first); if ((cell->type != "$dff" && cell->type != "$adff") || cellport.second != "\\Q") continue; log(" found %s cell for state register: %s\n", cell->type.c_str(), cell->name.c_str()); @@ -223,7 +223,7 @@ static void extract_fsm(RTLIL::Wire *wire) cellport_list.clear(); sig2trigger.find(dff_out, cellport_list); for (auto &cellport : cellport_list) { - RTLIL::Cell *cell = module->cells.at(cellport.first); + RTLIL::Cell *cell = module->cells_.at(cellport.first); RTLIL::SigSpec sig_a = assign_map(cell->get("\\A")); RTLIL::SigSpec sig_b = assign_map(cell->get("\\B")); RTLIL::SigSpec sig_y = assign_map(cell->get("\\Y")); @@ -293,7 +293,7 @@ static void extract_fsm(RTLIL::Wire *wire) cellport_list.clear(); sig2driver.find(ctrl_out, cellport_list); for (auto &cellport : cellport_list) { - RTLIL::Cell *cell = module->cells.at(cellport.first); + RTLIL::Cell *cell = module->cells_.at(cellport.first); RTLIL::SigSpec port_sig = assign_map(cell->get(cellport.second)); RTLIL::SigSpec unconn_sig = port_sig.extract(ctrl_out); RTLIL::Wire *unconn_wire = module->addWire(stringf("$fsm_unconnect$%s$%d", log_signal(unconn_sig), RTLIL::autoidx++), unconn_sig.size()); @@ -340,7 +340,7 @@ struct FsmExtractPass : public Pass { sig2driver.clear(); sig2trigger.clear(); - for (auto &cell_it : module->cells) + for (auto &cell_it : module->cells_) for (auto &conn_it : cell_it.second->connections()) { if (ct.cell_output(cell_it.second->type, conn_it.first) || !ct.cell_known(cell_it.second->type)) { RTLIL::SigSpec sig = conn_it.second; diff --git a/passes/fsm/fsm_info.cc b/passes/fsm/fsm_info.cc index f2d0c1a81..4526939ce 100644 --- a/passes/fsm/fsm_info.cc +++ b/passes/fsm/fsm_info.cc @@ -45,7 +45,7 @@ struct FsmInfoPass : public Pass { for (auto &mod_it : design->modules) if (design->selected(mod_it.second)) - for (auto &cell_it : mod_it.second->cells) + for (auto &cell_it : mod_it.second->cells_) if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second)) { log("\n"); log("FSM `%s' from module `%s':\n", cell_it.second->name.c_str(), mod_it.first.c_str()); diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc index 7ab159540..f6ef12a7a 100644 --- a/passes/fsm/fsm_map.cc +++ b/passes/fsm/fsm_map.cc @@ -313,7 +313,7 @@ struct FsmMapPass : public Pass { if (!design->selected(mod_it.second)) continue; std::vector fsm_cells; - for (auto &cell_it : mod_it.second->cells) + for (auto &cell_it : mod_it.second->cells_) if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second)) fsm_cells.push_back(cell_it.second); for (auto cell : fsm_cells) diff --git a/passes/fsm/fsm_opt.cc b/passes/fsm/fsm_opt.cc index 1441378a0..165b09747 100644 --- a/passes/fsm/fsm_opt.cc +++ b/passes/fsm/fsm_opt.cc @@ -290,7 +290,7 @@ struct FsmOptPass : public Pass { for (auto &mod_it : design->modules) { if (design->selected(mod_it.second)) - for (auto &cell_it : mod_it.second->cells) + for (auto &cell_it : mod_it.second->cells_) if (cell_it.second->type == "$fsm" and design->selected(mod_it.second, cell_it.second)) FsmData::optimize_fsm(cell_it.second, mod_it.second); } diff --git a/passes/fsm/fsm_recode.cc b/passes/fsm/fsm_recode.cc index b02287962..1b2eeb237 100644 --- a/passes/fsm/fsm_recode.cc +++ b/passes/fsm/fsm_recode.cc @@ -146,7 +146,7 @@ struct FsmRecodePass : public Pass { for (auto &mod_it : design->modules) if (design->selected(mod_it.second)) - for (auto &cell_it : mod_it.second->cells) + for (auto &cell_it : mod_it.second->cells_) if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second)) fsm_recode(cell_it.second, mod_it.second, fm_set_fsm_file, default_encoding); diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index a266c3445..550ec39f0 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -38,7 +38,7 @@ static void generate(RTLIL::Design *design, const std::vector &cell std::set found_celltypes; for (auto i1 : design->modules) - for (auto i2 : i1.second->cells) + for (auto i2 : i1.second->cells_) { RTLIL::Cell *cell = i2.second; if (cell->type[0] == '$' || design->modules.count(cell->type) > 0) @@ -56,7 +56,7 @@ static void generate(RTLIL::Design *design, const std::vector &cell log("Generate module for cell type %s:\n", celltype.c_str()); for (auto i1 : design->modules) - for (auto i2 : i1.second->cells) + for (auto i2 : i1.second->cells_) if (i2.second->type == celltype) { for (auto &conn : i2.second->connections()) { if (conn.first[0] != '$') @@ -137,7 +137,7 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla std::map> array_cells; std::string filename; - for (auto &cell_it : module->cells) + for (auto &cell_it : module->cells_) { RTLIL::Cell *cell = cell_it.second; @@ -252,7 +252,7 @@ static void hierarchy_worker(RTLIL::Design *design, std::set &us log("Used module: %*s%s\n", indent, "", mod->name.c_str()); used.insert(mod); - for (auto &it : mod->cells) { + for (auto &it : mod->cells_) { if (design->modules.count(it.second->type) > 0) hierarchy_worker(design, used, design->modules[it.second->type], indent+4); } @@ -479,7 +479,7 @@ struct HierarchyPass : public Pass { std::vector> pos_work; for (auto &mod_it : design->modules) - for (auto &cell_it : mod_it.second->cells) { + for (auto &cell_it : mod_it.second->cells_) { RTLIL::Cell *cell = cell_it.second; if (design->modules.count(cell->type) == 0) continue; diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index 774aabae1..374102756 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -87,7 +87,7 @@ struct SubmodWorker flag_signal(conn.second, true, true, true, false, false); } } - for (auto &it : module->cells) { + for (auto &it : module->cells_) { RTLIL::Cell *cell = it.second; if (submod.cells.count(cell) > 0) continue; @@ -215,7 +215,7 @@ struct SubmodWorker for (auto &it : module->wires_) it.second->attributes.erase("\\submod"); - for (auto &it : module->cells) + for (auto &it : module->cells_) { RTLIL::Cell *cell = it.second; if (cell->attributes.count("\\submod") == 0 || cell->attributes["\\submod"].bits.size() == 0) { @@ -239,7 +239,7 @@ struct SubmodWorker } else { - for (auto &it : module->cells) + for (auto &it : module->cells_) { RTLIL::Cell *cell = it.second; if (!design->selected(module, cell)) diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc index a8caf883f..d5995ee0e 100644 --- a/passes/memory/memory_collect.cc +++ b/passes/memory/memory_collect.cc @@ -61,7 +61,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) std::vector del_cells; std::vector memcells; - for (auto &cell_it : module->cells) { + for (auto &cell_it : module->cells_) { RTLIL::Cell *cell = cell_it.second; if ((cell->type == "$memwr" || cell->type == "$memrd") && cell->parameters["\\MEMID"].decode_string() == memory->name) memcells.push_back(cell); diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index b63b3aec6..bb8b052dc 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -38,7 +38,7 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI if (bit.wire == NULL) continue; - for (auto &cell_it : module->cells) + for (auto &cell_it : module->cells_) { RTLIL::Cell *cell = cell_it.second; @@ -120,7 +120,7 @@ static void disconnect_dff(RTLIL::Module *module, RTLIL::SigSpec sig) RTLIL::SigSpec new_sig = module->addWire(sstr.str(), sig.size()); - for (auto &cell_it : module->cells) { + for (auto &cell_it : module->cells_) { RTLIL::Cell *cell = cell_it.second; if (cell->type == "$dff") { RTLIL::SigSpec new_q = cell->get("\\Q"); @@ -170,7 +170,7 @@ static void handle_rd_cell(RTLIL::Module *module, RTLIL::Cell *cell) static void handle_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_wr_only) { - for (auto &cell_it : module->cells) { + for (auto &cell_it : module->cells_) { if (!design->selected(module, cell_it.second)) continue; if (cell_it.second->type == "$memwr" && !cell_it.second->parameters["\\CLK_ENABLE"].as_bool()) diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index 4f1666533..4bb0c8ccd 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -295,7 +295,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) static void handle_module(RTLIL::Design *design, RTLIL::Module *module) { std::vector cells; - for (auto &it : module->cells) + for (auto &it : module->cells_) if (it.second->type == "$mem" && design->selected(module, it.second)) cells.push_back(it.second); for (auto cell : cells) diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index 35a28d17d..b25cf73a7 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -143,7 +143,7 @@ struct MemoryShareWorker non_feedback_nets.insert(bits.begin(), bits.end()); } - for (auto cell_it : module->cells) + for (auto cell_it : module->cells_) { RTLIL::Cell *cell = cell_it.second; bool ignore_data_port = false; @@ -650,7 +650,7 @@ struct MemoryShareWorker std::map, std::vector>> memindex; sigmap_xmux = sigmap; - for (auto &it : module->cells) + for (auto &it : module->cells_) { RTLIL::Cell *cell = it.second; diff --git a/passes/memory/memory_unpack.cc b/passes/memory/memory_unpack.cc index f08350768..48b83f5fa 100644 --- a/passes/memory/memory_unpack.cc +++ b/passes/memory/memory_unpack.cc @@ -80,11 +80,11 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory) static void handle_module(RTLIL::Design *design, RTLIL::Module *module) { std::vector memcells; - for (auto &cell_it : module->cells) + for (auto &cell_it : module->cells_) if (cell_it.second->type == "$mem" && design->selected(module, cell_it.second)) memcells.push_back(cell_it.first); for (auto &it : memcells) - handle_memory(module, module->cells.at(it)); + handle_memory(module, module->cells_.at(it)); } struct MemoryUnpackPass : public Pass { diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 9542e10df..4cc5fc89a 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -38,7 +38,7 @@ static void rmunused_module_cells(RTLIL::Module *module, bool verbose) std::set> queue, unused; SigSet wire2driver; - for (auto &it : module->cells) { + for (auto &it : module->cells_) { RTLIL::Cell *cell = it.second; for (auto &it2 : cell->connections()) { if (!ct.cell_input(cell->type, it2.first)) { @@ -155,7 +155,7 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool SigPool connected_signals; if (!purge_mode) - for (auto &it : module->cells) { + for (auto &it : module->cells_) { RTLIL::Cell *cell = it.second; if (ct_reg.cell_known(cell->type)) for (auto &it2 : cell->connections()) @@ -168,7 +168,7 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool SigMap assign_map(module); std::set direct_sigs; std::set direct_wires; - for (auto &it : module->cells) { + for (auto &it : module->cells_) { RTLIL::Cell *cell = it.second; if (ct_all.cell_known(cell->type)) for (auto &it2 : cell->connections()) @@ -193,7 +193,7 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool SigPool used_signals; SigPool used_signals_nodrivers; - for (auto &it : module->cells) { + for (auto &it : module->cells_) { RTLIL::Cell *cell = it.second; for (auto &it2 : cell->connections_) { assign_map.apply(it2.second); diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index 290d4ffd9..39e2254e0 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -37,7 +37,7 @@ static void replace_undriven(RTLIL::Design *design, RTLIL::Module *module) SigPool used_signals; SigPool all_signals; - for (auto &it : module->cells) + for (auto &it : module->cells_) for (auto &conn : it.second->connections()) { if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first)) driven_signals.add(sigmap(conn.second)); @@ -199,8 +199,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo std::map invert_map; std::vector cells; - cells.reserve(module->cells.size()); - for (auto &cell_it : module->cells) + cells.reserve(module->cells_.size()); + for (auto &cell_it : module->cells_) if (design->selected(module, cell_it.second)) { if ((cell_it.second->type == "$_INV_" || cell_it.second->type == "$not" || cell_it.second->type == "$logic_not") && cell_it.second->get("\\A").size() == 1 && cell_it.second->get("\\Y").size() == 1) diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc index 16dedef58..1d4916b56 100644 --- a/passes/opt/opt_muxtree.cc +++ b/passes/opt/opt_muxtree.cc @@ -83,7 +83,7 @@ struct OptMuxtreeWorker // .ctrl_sigs // .input_sigs // .const_activated - for (auto &cell_it : module->cells) + for (auto &cell_it : module->cells_) { RTLIL::Cell *cell = cell_it.second; if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux") diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc index 1f8648c45..d7de72353 100644 --- a/passes/opt/opt_reduce.cc +++ b/passes/opt/opt_reduce.cc @@ -254,14 +254,14 @@ struct OptReduceWorker did_something = true; SigPool mem_wren_sigs; - for (auto &cell_it : module->cells) { + for (auto &cell_it : module->cells_) { RTLIL::Cell *cell = cell_it.second; if (cell->type == "$mem") mem_wren_sigs.add(assign_map(cell->get("\\WR_EN"))); if (cell->type == "$memwr") mem_wren_sigs.add(assign_map(cell->get("\\EN"))); } - for (auto &cell_it : module->cells) { + for (auto &cell_it : module->cells_) { RTLIL::Cell *cell = cell_it.second; if (cell->type == "$dff" && mem_wren_sigs.check_any(assign_map(cell->get("\\Q")))) mem_wren_sigs.add(assign_map(cell->get("\\D"))); @@ -270,7 +270,7 @@ struct OptReduceWorker bool keep_expanding_mem_wren_sigs = true; while (keep_expanding_mem_wren_sigs) { keep_expanding_mem_wren_sigs = false; - for (auto &cell_it : module->cells) { + for (auto &cell_it : module->cells_) { RTLIL::Cell *cell = cell_it.second; if (cell->type == "$mux" && mem_wren_sigs.check_any(assign_map(cell->get("\\Y")))) { if (!mem_wren_sigs.check_all(assign_map(cell->get("\\A"))) || @@ -295,7 +295,7 @@ struct OptReduceWorker SigSet drivers; std::set cells; - for (auto &cell_it : module->cells) { + for (auto &cell_it : module->cells_) { RTLIL::Cell *cell = cell_it.second; if (cell->type != type || !design->selected(module, cell)) continue; @@ -313,7 +313,7 @@ struct OptReduceWorker std::vector cells; - for (auto &it : module->cells) + for (auto &it : module->cells_) if ((it.second->type == "$mux" || it.second->type == "$pmux" || it.second->type == "$safe_pmux") && design->selected(module, it.second)) cells.push_back(it.second); diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc index b26e8b37e..14b734d7d 100644 --- a/passes/opt/opt_rmdff.cc +++ b/passes/opt/opt_rmdff.cc @@ -179,7 +179,7 @@ struct OptRmdffPass : public Pass { mux_drivers.clear(); std::vector dff_list; - for (auto &it : mod_it.second->cells) { + for (auto &it : mod_it.second->cells_) { if (it.second->type == "$mux" || it.second->type == "$pmux") { if (it.second->get("\\A").size() == it.second->get("\\B").size()) mux_drivers.insert(assign_map(it.second->get("\\Y")), it.second); @@ -202,8 +202,8 @@ struct OptRmdffPass : public Pass { } for (auto &id : dff_list) { - if (mod_it.second->cells.count(id) > 0 && - handle_dff(mod_it.second, mod_it.second->cells[id])) + if (mod_it.second->cells_.count(id) > 0 && + handle_dff(mod_it.second, mod_it.second->cells_[id])) total_count++; } } diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc index c91f037d4..304ba9f83 100644 --- a/passes/opt/opt_share.cc +++ b/passes/opt/opt_share.cc @@ -248,8 +248,8 @@ struct OptShareWorker cell_hash_cache.clear(); #endif std::vector cells; - cells.reserve(module->cells.size()); - for (auto &it : module->cells) { + cells.reserve(module->cells_.size()); + for (auto &it : module->cells_) { if (ct.cell_known(it.second->type) && design->selected(module, it.second)) cells.push_back(it.second); } diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc index 565d86a72..63d04d351 100644 --- a/passes/proc/proc_arst.cc +++ b/passes/proc/proc_arst.cc @@ -33,7 +33,7 @@ static bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSp if (signal == ref) return true; - for (auto &cell_it : mod->cells) { + for (auto &cell_it : mod->cells_) { RTLIL::Cell *cell = cell_it.second; if (cell->type == "$reduce_or" && cell->get("\\Y") == signal) return check_signal(mod, cell->get("\\A"), ref, polarity); diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc index d4ff2a86c..454233267 100644 --- a/passes/sat/eval.cc +++ b/passes/sat/eval.cc @@ -147,7 +147,7 @@ struct VlogHammerReporter SatGen satgen(&ez, &sigmap); satgen.model_undef = model_undef; - for (auto &c : module->cells) + for (auto &c : module->cells_) if (!satgen.importCell(c.second)) log_error("Failed to import cell %s (type %s) to SAT database.\n", RTLIL::id2cstr(c.first), RTLIL::id2cstr(c.second->type)); diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc index c30e6e0c8..24b812bb2 100644 --- a/passes/sat/expose.cc +++ b/passes/sat/expose.cc @@ -82,7 +82,7 @@ static void find_dff_wires(std::set &dff_wires, RTLIL::Module *modu SigMap sigmap(module); SigPool dffsignals; - for (auto &it : module->cells) { + for (auto &it : module->cells_) { if (ct.cell_known(it.second->type) && it.second->has("\\Q")) dffsignals.add(sigmap(it.second->get("\\Q"))); } @@ -98,7 +98,7 @@ static void create_dff_dq_map(std::map &map, RTLIL: std::map bit_info; SigMap sigmap(module); - for (auto &it : module->cells) + for (auto &it : module->cells_) { if (!design->selected(module, it.second)) continue; @@ -371,7 +371,7 @@ struct ExposePass : public Pass { shared_wires.insert(it.first); if (flag_evert) - for (auto &it : module->cells) + for (auto &it : module->cells_) if (design->selected(module, it.second) && consider_cell(design, dff_cells[module], it.second)) shared_cells.insert(it.first); @@ -409,16 +409,16 @@ struct ExposePass : public Pass { { RTLIL::Cell *cell; - if (module->cells.count(it) == 0) + if (module->cells_.count(it) == 0) goto delete_shared_cell; - cell = module->cells.at(it); + cell = module->cells_.at(it); if (!design->selected(module, cell)) goto delete_shared_cell; if (!consider_cell(design, dff_cells[module], cell)) goto delete_shared_cell; - if (!compare_cells(first_module->cells.at(it), cell)) + if (!compare_cells(first_module->cells_.at(it), cell)) goto delete_shared_cell; if (0) @@ -475,7 +475,7 @@ struct ExposePass : public Pass { if (flag_cut) { - for (auto &it : module->cells) { + for (auto &it : module->cells_) { if (!ct.cell_known(it.second->type)) continue; for (auto &conn : it.second->connections_) @@ -503,7 +503,7 @@ struct ExposePass : public Pass { RTLIL::Wire *wire_dummy_q = add_new_wire(module, NEW_ID, 0); for (auto &cell_name : info.cells) { - RTLIL::Cell *cell = module->cells.at(cell_name); + RTLIL::Cell *cell = module->cells_.at(cell_name); std::vector cell_q_bits = sigmap(cell->get("\\Q")).to_sigbit_vector(); for (auto &bit : cell_q_bits) if (wire_bits_set.count(bit)) @@ -571,7 +571,7 @@ struct ExposePass : public Pass { { std::vector delete_cells; - for (auto &it : module->cells) + for (auto &it : module->cells_) { if (flag_shared) { if (shared_cells.count(it.first) == 0) diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index 5d23318ce..f8d5cf6c4 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -607,7 +607,7 @@ struct FreduceWorker batches.push_back(sigmap(it.second).to_sigbit_set()); bits_full_total += it.second->width; } - for (auto &it : module->cells) { + for (auto &it : module->cells_) { if (ct.cell_known(it.second->type)) { std::set inputs, outputs; for (auto &port : it.second->connections()) { diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 90c671165..3e1c72224 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -317,7 +317,7 @@ struct SatHelper } int import_cell_counter = 0; - for (auto &c : module->cells) + for (auto &c : module->cells_) if (design->selected(module, c.second)) { // log("Import cell: %s\n", RTLIL::id2cstr(c.first)); if (satgen.importCell(c.second, timestep)) { diff --git a/passes/sat/share.cc b/passes/sat/share.cc index 0ee5af186..facacf196 100644 --- a/passes/sat/share.cc +++ b/passes/sat/share.cc @@ -61,7 +61,7 @@ struct ShareWorker queue_bits.insert(modwalker.signal_outputs.begin(), modwalker.signal_outputs.end()); - for (auto &it : module->cells) + for (auto &it : module->cells_) if (!fwd_ct.cell_known(it.second->type)) { std::set &bits = modwalker.cell_inputs[it.second]; queue_bits.insert(bits.begin(), bits.end()); @@ -101,7 +101,7 @@ struct ShareWorker void find_shareable_cells() { - for (auto &it : module->cells) + for (auto &it : module->cells_) { RTLIL::Cell *cell = it.second; diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc index eabc56bd2..01284656d 100644 --- a/passes/techmap/dfflibmap.cc +++ b/passes/techmap/dfflibmap.cc @@ -388,7 +388,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module) log("Mapping DFF cells in module `%s':\n", module->name.c_str()); std::vector cell_list; - for (auto &it : module->cells) { + for (auto &it : module->cells_) { if (design->selected(module, it.second) && cell_mappings.count(it.second->type) > 0) cell_list.push_back(it.second); } diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index 813e0e3e1..b66a11b85 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -182,7 +182,7 @@ namespace std::map, int> sig_use_count; if (max_fanout > 0) - for (auto &cell_it : mod->cells) + for (auto &cell_it : mod->cells_) { RTLIL::Cell *cell = cell_it.second; if (!sel || sel->selected(mod, cell)) @@ -196,7 +196,7 @@ namespace } // create graph nodes from cells - for (auto &cell_it : mod->cells) + for (auto &cell_it : mod->cells_) { RTLIL::Cell *cell = cell_it.second; if (sel && !sel->selected(mod, cell)) @@ -253,7 +253,7 @@ namespace } // mark external signals (used in non-selected cells) - for (auto &cell_it : mod->cells) + for (auto &cell_it : mod->cells_) { RTLIL::Cell *cell = cell_it.second; if (sel && !sel->selected(mod, cell)) diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc index 355c07c84..8c7f64230 100644 --- a/passes/techmap/simplemap.cc +++ b/passes/techmap/simplemap.cc @@ -439,7 +439,7 @@ struct SimplemapPass : public Pass { if (!design->selected(mod_it.second)) continue; std::vector delete_cells; - for (auto &cell_it : mod_it.second->cells) { + for (auto &cell_it : mod_it.second->cells_) { if (mappers.count(cell_it.second->type) == 0) continue; if (!design->selected(mod_it.second, cell_it.second)) diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 03aac6693..86d9e73ae 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -116,7 +116,7 @@ struct TechmapWorker std::string orig_cell_name; if (!flatten_mode) - for (auto &it : tpl->cells) + for (auto &it : tpl->cells_) if (it.first == "\\_TECHMAP_REPLACE_") { orig_cell_name = cell->name; module->rename(cell, stringf("$techmap%d", RTLIL::autoidx++) + cell->name); @@ -180,7 +180,7 @@ struct TechmapWorker } } - for (auto &it : tpl->cells) + for (auto &it : tpl->cells_) { RTLIL::IdString c_name = it.second->name; @@ -224,15 +224,15 @@ struct TechmapWorker std::vector cell_names; SigMap sigmap(module); - for (auto &cell_it : module->cells) + for (auto &cell_it : module->cells_) cell_names.push_back(cell_it.first); for (auto &cell_name : cell_names) { - if (module->cells.count(cell_name) == 0) + if (module->cells_.count(cell_name) == 0) continue; - RTLIL::Cell *cell = module->cells[cell_name]; + RTLIL::Cell *cell = module->cells_[cell_name]; if (!design->selected(module, cell) || handled_cells.count(cell) > 0) continue; -- cgit v1.2.3 From 10e5791c5e5660cb784503d36439ee90d61eb06b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 10:18:00 +0200 Subject: Refactoring: Renamed RTLIL::Design::modules to modules_ --- passes/abc/abc.cc | 4 +-- passes/abc/blifparse.cc | 2 +- passes/cmds/add.cc | 6 ++--- passes/cmds/connect.cc | 2 +- passes/cmds/connwrappers.cc | 2 +- passes/cmds/copy.cc | 8 +++--- passes/cmds/delete.cc | 6 ++--- passes/cmds/design.cc | 22 +++++++-------- passes/cmds/rename.cc | 14 +++++----- passes/cmds/scatter.cc | 2 +- passes/cmds/scc.cc | 2 +- passes/cmds/select.cc | 40 +++++++++++++-------------- passes/cmds/setattr.cc | 4 +-- passes/cmds/setundef.cc | 2 +- passes/cmds/show.cc | 4 +-- passes/cmds/splice.cc | 2 +- passes/cmds/splitnets.cc | 2 +- passes/cmds/stat.cc | 6 ++--- passes/fsm/fsm_detect.cc | 2 +- passes/fsm/fsm_expand.cc | 2 +- passes/fsm/fsm_export.cc | 2 +- passes/fsm/fsm_extract.cc | 2 +- passes/fsm/fsm_info.cc | 2 +- passes/fsm/fsm_map.cc | 2 +- passes/fsm/fsm_opt.cc | 2 +- passes/fsm/fsm_recode.cc | 2 +- passes/hierarchy/hierarchy.cc | 60 ++++++++++++++++++++--------------------- passes/hierarchy/submod.cc | 12 ++++----- passes/memory/memory_collect.cc | 2 +- passes/memory/memory_dff.cc | 2 +- passes/memory/memory_map.cc | 2 +- passes/memory/memory_share.cc | 2 +- passes/memory/memory_unpack.cc | 2 +- passes/opt/opt_clean.cc | 4 +-- passes/opt/opt_const.cc | 2 +- passes/opt/opt_muxtree.cc | 2 +- passes/opt/opt_reduce.cc | 2 +- passes/opt/opt_rmdff.cc | 2 +- passes/opt/opt_share.cc | 2 +- passes/proc/proc_arst.cc | 2 +- passes/proc/proc_clean.cc | 2 +- passes/proc/proc_dff.cc | 2 +- passes/proc/proc_init.cc | 2 +- passes/proc/proc_mux.cc | 2 +- passes/proc/proc_rmdead.cc | 2 +- passes/sat/eval.cc | 12 ++++----- passes/sat/expose.cc | 12 ++++----- passes/sat/freduce.cc | 2 +- passes/sat/miter.cc | 12 ++++----- passes/sat/sat.cc | 2 +- passes/sat/share.cc | 2 +- passes/techmap/dfflibmap.cc | 2 +- passes/techmap/extract.cc | 12 ++++----- passes/techmap/hilomap.cc | 2 +- passes/techmap/iopadmap.cc | 2 +- passes/techmap/simplemap.cc | 2 +- passes/techmap/techmap.cc | 22 +++++++-------- 57 files changed, 169 insertions(+), 169 deletions(-) (limited to 'passes') diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index 7ba9424e8..03fc9f937 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -684,7 +684,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std free(p); log_header("Re-integrating ABC results.\n"); - RTLIL::Module *mapped_mod = mapped_design->modules["\\netlist"]; + RTLIL::Module *mapped_mod = mapped_design->modules_["\\netlist"]; if (mapped_mod == NULL) log_error("ABC output file does not contain a module `netlist'.\n"); for (auto &it : mapped_mod->wires_) { @@ -1000,7 +1000,7 @@ struct AbcPass : public Pass { if (!constr_file.empty() && liberty_file.empty()) log_cmd_error("Got -constr but no -liberty!\n"); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (design->selected(mod_it.second)) { if (mod_it.second->processes.size() > 0) log("Skipping module %s as it contains processes.\n", mod_it.second->name.c_str()); diff --git a/passes/abc/blifparse.cc b/passes/abc/blifparse.cc index 773bbe5d2..4bcbc0131 100644 --- a/passes/abc/blifparse.cc +++ b/passes/abc/blifparse.cc @@ -60,7 +60,7 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name) int port_count = 0; module->name = "\\netlist"; - design->modules[module->name] = module; + design->modules_[module->name] = module; size_t buffer_size = 4096; char *buffer = (char*)malloc(buffer_size); diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc index 49aa7c98d..62995a49d 100644 --- a/passes/cmds/add.cc +++ b/passes/cmds/add.cc @@ -64,10 +64,10 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n for (auto &it : module->cells_) { - if (design->modules.count(it.second->type) == 0) + if (design->modules_.count(it.second->type) == 0) continue; - RTLIL::Module *mod = design->modules.at(it.second->type); + RTLIL::Module *mod = design->modules_.at(it.second->type); if (!design->selected_whole_module(mod->name)) continue; if (mod->get_bool_attribute("\\blackbox")) @@ -136,7 +136,7 @@ struct AddPass : public Pass { } extra_args(args, argidx, design); - for (auto &mod : design->modules) + for (auto &mod : design->modules_) { RTLIL::Module *module = mod.second; if (!design->selected_whole_module(module->name)) diff --git a/passes/cmds/connect.cc b/passes/cmds/connect.cc index 6494ea6f6..3e13fd4d4 100644 --- a/passes/cmds/connect.cc +++ b/passes/cmds/connect.cc @@ -75,7 +75,7 @@ struct ConnectPass : public Pass { virtual void execute(std::vector args, RTLIL::Design *design) { RTLIL::Module *module = NULL; - for (auto &it : design->modules) { + for (auto &it : design->modules_) { if (!design->selected(it.second)) continue; if (module != NULL) diff --git a/passes/cmds/connwrappers.cc b/passes/cmds/connwrappers.cc index cc8147c53..5125ff5e2 100644 --- a/passes/cmds/connwrappers.cc +++ b/passes/cmds/connwrappers.cc @@ -197,7 +197,7 @@ struct ConnwrappersPass : public Pass { log_header("Executing CONNWRAPPERS pass (connect extended ports of wrapper cells).\n"); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (design->selected(mod_it.second)) worker.work(design, mod_it.second); } diff --git a/passes/cmds/copy.cc b/passes/cmds/copy.cc index 4b1a8db81..fc801f61f 100644 --- a/passes/cmds/copy.cc +++ b/passes/cmds/copy.cc @@ -41,14 +41,14 @@ struct CopyPass : public Pass { std::string src_name = RTLIL::escape_id(args[1]); std::string trg_name = RTLIL::escape_id(args[2]); - if (design->modules.count(src_name) == 0) + if (design->modules_.count(src_name) == 0) log_cmd_error("Can't find source module %s.\n", src_name.c_str()); - if (design->modules.count(trg_name) != 0) + if (design->modules_.count(trg_name) != 0) log_cmd_error("Target module name %s already exists.\n", trg_name.c_str()); - design->modules[trg_name] = design->modules.at(src_name)->clone(); - design->modules[trg_name]->name = trg_name; + design->modules_[trg_name] = design->modules_.at(src_name)->clone(); + design->modules_[trg_name]->name = trg_name; } } CopyPass; diff --git a/passes/cmds/delete.cc b/passes/cmds/delete.cc index 2c2c370dd..67b4d939f 100644 --- a/passes/cmds/delete.cc +++ b/passes/cmds/delete.cc @@ -66,7 +66,7 @@ struct DeletePass : public Pass { std::vector delete_mods; - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) { if (design->selected_whole_module(mod_it.first) && !flag_input && !flag_output) { delete_mods.push_back(mod_it.first); @@ -134,8 +134,8 @@ struct DeletePass : public Pass { } for (auto &it : delete_mods) { - delete design->modules.at(it); - design->modules.erase(it); + delete design->modules_.at(it); + design->modules_.erase(it); } } } DeletePass; diff --git a/passes/cmds/design.cc b/passes/cmds/design.cc index 7b8889d60..bd1ee68f2 100644 --- a/passes/cmds/design.cc +++ b/passes/cmds/design.cc @@ -165,7 +165,7 @@ struct DesignPass : public Pass { argidx = args.size(); } - for (auto &it : copy_from_design->modules) { + for (auto &it : copy_from_design->modules_) { if (sel.selected_whole_module(it.first)) { copy_src_modules.push_back(it.second); continue; @@ -192,10 +192,10 @@ struct DesignPass : public Pass { { std::string trg_name = as_name.empty() ? mod->name : RTLIL::escape_id(as_name); - if (copy_to_design->modules.count(trg_name)) - delete copy_to_design->modules.at(trg_name); - copy_to_design->modules[trg_name] = mod->clone(); - copy_to_design->modules[trg_name]->name = trg_name; + if (copy_to_design->modules_.count(trg_name)) + delete copy_to_design->modules_.at(trg_name); + copy_to_design->modules_[trg_name] = mod->clone(); + copy_to_design->modules_[trg_name]->name = trg_name; } } @@ -203,8 +203,8 @@ struct DesignPass : public Pass { { RTLIL::Design *design_copy = new RTLIL::Design; - for (auto &it : design->modules) - design_copy->modules[it.first] = it.second->clone(); + for (auto &it : design->modules_) + design_copy->modules_[it.first] = it.second->clone(); design_copy->selection_stack = design->selection_stack; design_copy->selection_vars = design->selection_vars; @@ -221,9 +221,9 @@ struct DesignPass : public Pass { if (reset_mode || !load_name.empty() || push_mode || pop_mode) { - for (auto &it : design->modules) + for (auto &it : design->modules_) delete it.second; - design->modules.clear(); + design->modules_.clear(); design->selection_stack.clear(); design->selection_vars.clear(); @@ -239,8 +239,8 @@ struct DesignPass : public Pass { if (pop_mode) pushed_designs.pop_back(); - for (auto &it : saved_design->modules) - design->modules[it.first] = it.second->clone(); + for (auto &it : saved_design->modules_) + design->modules_[it.first] = it.second->clone(); design->selection_stack = saved_design->selection_stack; design->selection_vars = saved_design->selection_vars; diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc index c8b8160f1..3a6008721 100644 --- a/passes/cmds/rename.cc +++ b/passes/cmds/rename.cc @@ -96,7 +96,7 @@ struct RenamePass : public Pass { { extra_args(args, argidx, design); - for (auto &mod : design->modules) + for (auto &mod : design->modules_) { int counter = 0; @@ -128,7 +128,7 @@ struct RenamePass : public Pass { { extra_args(args, argidx, design); - for (auto &mod : design->modules) + for (auto &mod : design->modules_) { RTLIL::Module *module = mod.second; if (!design->selected(module)) @@ -163,19 +163,19 @@ struct RenamePass : public Pass { if (!design->selected_active_module.empty()) { - if (design->modules.count(design->selected_active_module) > 0) - rename_in_module(design->modules.at(design->selected_active_module), from_name, to_name); + if (design->modules_.count(design->selected_active_module) > 0) + rename_in_module(design->modules_.at(design->selected_active_module), from_name, to_name); } else { - for (auto &mod : design->modules) { + for (auto &mod : design->modules_) { if (mod.first == from_name || RTLIL::unescape_id(mod.first) == from_name) { to_name = RTLIL::escape_id(to_name); log("Renaming module %s to %s.\n", mod.first.c_str(), to_name.c_str()); RTLIL::Module *module = mod.second; - design->modules.erase(module->name); + design->modules_.erase(module->name); module->name = to_name; - design->modules[module->name] = module; + design->modules_[module->name] = module; goto rename_ok; } } diff --git a/passes/cmds/scatter.cc b/passes/cmds/scatter.cc index a1c12f1ee..e09c00123 100644 --- a/passes/cmds/scatter.cc +++ b/passes/cmds/scatter.cc @@ -43,7 +43,7 @@ struct ScatterPass : public Pass { CellTypes ct(design); extra_args(args, 1, design); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) { if (!design->selected(mod_it.second)) continue; diff --git a/passes/cmds/scc.cc b/passes/cmds/scc.cc index c95043417..1fa1b4c9c 100644 --- a/passes/cmds/scc.cc +++ b/passes/cmds/scc.cc @@ -280,7 +280,7 @@ struct SccPass : public Pass { RTLIL::Selection newSelection(false); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (design->selected(mod_it.second)) { SccWorker worker(design, mod_it.second, allCellTypes, maxDepth); diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index 306b7a5b1..85c52277c 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -151,7 +151,7 @@ static void select_op_neg(RTLIL::Design *design, RTLIL::Selection &lhs) RTLIL::Selection new_sel(false); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) { if (lhs.selected_whole_module(mod_it.first)) continue; @@ -181,13 +181,13 @@ static void select_op_neg(RTLIL::Design *design, RTLIL::Selection &lhs) static void select_op_submod(RTLIL::Design *design, RTLIL::Selection &lhs) { - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) { if (lhs.selected_whole_module(mod_it.first)) { for (auto &cell_it : mod_it.second->cells_) { - if (design->modules.count(cell_it.second->type) == 0) + if (design->modules_.count(cell_it.second->type) == 0) continue; lhs.selected_modules.insert(cell_it.second->type); } @@ -205,7 +205,7 @@ static void select_op_fullmod(RTLIL::Design *design, RTLIL::Selection &lhs) static void select_op_alias(RTLIL::Design *design, RTLIL::Selection &lhs) { - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) { if (lhs.selected_whole_module(mod_it.first)) continue; @@ -260,7 +260,7 @@ static void select_op_diff(RTLIL::Design *design, RTLIL::Selection &lhs, const R if (!rhs.full_selection && rhs.selected_modules.size() == 0 && rhs.selected_members.size() == 0) return; lhs.full_selection = false; - for (auto &it : design->modules) + for (auto &it : design->modules_) lhs.selected_modules.insert(it.first); } @@ -271,10 +271,10 @@ static void select_op_diff(RTLIL::Design *design, RTLIL::Selection &lhs, const R for (auto &it : rhs.selected_members) { - if (design->modules.count(it.first) == 0) + if (design->modules_.count(it.first) == 0) continue; - RTLIL::Module *mod = design->modules[it.first]; + RTLIL::Module *mod = design->modules_[it.first]; if (lhs.selected_modules.count(mod->name) > 0) { @@ -304,7 +304,7 @@ static void select_op_intersect(RTLIL::Design *design, RTLIL::Selection &lhs, co if (lhs.full_selection) { lhs.full_selection = false; - for (auto &it : design->modules) + for (auto &it : design->modules_) lhs.selected_modules.insert(it.first); } @@ -368,7 +368,7 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v { int sel_objects = 0; bool is_input, is_output; - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) { if (lhs.selected_whole_module(mod_it.first) || !lhs.selected_module(mod_it.first)) continue; @@ -684,7 +684,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg) } sel.full_selection = false; - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) { if (arg_mod.substr(0, 2) == "A:") { if (!match_attr(mod_it.second->attributes, arg_mod.substr(2))) @@ -1078,7 +1078,7 @@ struct SelectPass : public Pass { } if (arg == "-module" && argidx+1 < args.size()) { RTLIL::IdString mod_name = RTLIL::escape_id(args[++argidx]); - if (design->modules.count(mod_name) == 0) + if (design->modules_.count(mod_name) == 0) log_cmd_error("No such module: %s\n", id2cstr(mod_name)); design->selected_active_module = mod_name; got_module = true; @@ -1147,7 +1147,7 @@ struct SelectPass : public Pass { if (work_stack.size() > 0) sel = &work_stack.back(); sel->optimize(design); - for (auto mod_it : design->modules) + for (auto mod_it : design->modules_) { if (sel->selected_whole_module(mod_it.first) && list_mode) log("%s\n", id2cstr(mod_it.first)); @@ -1217,7 +1217,7 @@ struct SelectPass : public Pass { log_cmd_error("No selection to check.\n"); RTLIL::Selection *sel = &work_stack.back(); sel->optimize(design); - for (auto mod_it : design->modules) + for (auto mod_it : design->modules_) if (sel->selected_module(mod_it.first)) { for (auto &it : mod_it.second->wires_) if (sel->selected_member(mod_it.first, it.first)) @@ -1299,15 +1299,15 @@ struct CdPass : public Pass { std::string modname = RTLIL::escape_id(args[1]); - if (design->modules.count(modname) == 0 && !design->selected_active_module.empty()) { + if (design->modules_.count(modname) == 0 && !design->selected_active_module.empty()) { RTLIL::Module *module = NULL; - if (design->modules.count(design->selected_active_module) > 0) - module = design->modules.at(design->selected_active_module); + if (design->modules_.count(design->selected_active_module) > 0) + module = design->modules_.at(design->selected_active_module); if (module != NULL && module->cells_.count(modname) > 0) modname = module->cells_.at(modname)->type; } - if (design->modules.count(modname) > 0) { + if (design->modules_.count(modname) > 0) { design->selected_active_module = modname; design->selection_stack.back() = RTLIL::Selection(); select_filter_active_mod(design, design->selection_stack.back()); @@ -1368,12 +1368,12 @@ struct LsPass : public Pass { if (design->selected_active_module.empty()) { - counter += log_matches("modules", pattern, design->modules); + counter += log_matches("modules", pattern, design->modules_); } else - if (design->modules.count(design->selected_active_module) > 0) + if (design->modules_.count(design->selected_active_module) > 0) { - RTLIL::Module *module = design->modules.at(design->selected_active_module); + RTLIL::Module *module = design->modules_.at(design->selected_active_module); counter += log_matches("wires", pattern, module->wires_); counter += log_matches("memories", pattern, module->memories); counter += log_matches("cells", pattern, module->cells_); diff --git a/passes/cmds/setattr.cc b/passes/cmds/setattr.cc index ea5221f6d..029c0ec79 100644 --- a/passes/cmds/setattr.cc +++ b/passes/cmds/setattr.cc @@ -98,7 +98,7 @@ struct SetattrPass : public Pass { } extra_args(args, argidx, design); - for (auto &mod : design->modules) + for (auto &mod : design->modules_) { RTLIL::Module *module = mod.second; @@ -164,7 +164,7 @@ struct SetparamPass : public Pass { } extra_args(args, argidx, design); - for (auto &mod : design->modules) + for (auto &mod : design->modules_) { RTLIL::Module *module = mod.second; diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index e7779415d..c72e64b80 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -115,7 +115,7 @@ struct SetundefPass : public Pass { if (!got_value) log_cmd_error("One of the options -zero, -one, or -random must be specified.\n"); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) { RTLIL::Module *module = mod_it.second; if (!design->selected(module)) diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index 18af8dfce..7ab1daf00 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -506,7 +506,7 @@ struct ShowWorker design->optimize(); page_counter = 0; - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) { module = mod_it.second; if (!design->selected_module(module->name)) @@ -692,7 +692,7 @@ struct ShowPass : public Pass { if (format != "ps") { int modcount = 0; - for (auto &mod_it : design->modules) { + for (auto &mod_it : design->modules_) { if (mod_it.second->get_bool_attribute("\\blackbox")) continue; if (mod_it.second->cells_.empty() && mod_it.second->connections().empty()) diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc index dcd2f819f..5fce2d6cb 100644 --- a/passes/cmds/splice.cc +++ b/passes/cmds/splice.cc @@ -327,7 +327,7 @@ struct SplicePass : public Pass { log_header("Executing SPLICE pass (creating cells for signal splicing).\n"); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) { if (!design->selected(mod_it.second)) continue; diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc index 0998a1622..6b1dbe13c 100644 --- a/passes/cmds/splitnets.cc +++ b/passes/cmds/splitnets.cc @@ -117,7 +117,7 @@ struct SplitnetsPass : public Pass { } extra_args(args, argidx, design); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) { RTLIL::Module *module = mod_it.second; if (!design->selected(module)) diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc index 153226ab5..fabc80ec0 100644 --- a/passes/cmds/stat.cc +++ b/passes/cmds/stat.cc @@ -166,16 +166,16 @@ struct StatPass : public Pass { for (argidx = 1; argidx < args.size(); argidx++) { if (args[argidx] == "-top" && argidx+1 < args.size()) { - if (design->modules.count(RTLIL::escape_id(args[argidx+1])) == 0) + if (design->modules_.count(RTLIL::escape_id(args[argidx+1])) == 0) log_cmd_error("Can't find module %s.\n", args[argidx+1].c_str()); - top_mod = design->modules.at(RTLIL::escape_id(args[++argidx])); + top_mod = design->modules_.at(RTLIL::escape_id(args[++argidx])); continue; } break; } extra_args(args, argidx, design); - for (auto &it : design->modules) + for (auto &it : design->modules_) { if (!design->selected_module(it.first)) continue; diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc index e1528f31d..a619cf57d 100644 --- a/passes/fsm/fsm_detect.cc +++ b/passes/fsm/fsm_detect.cc @@ -148,7 +148,7 @@ struct FsmDetectPass : public Pass { ct.setup_stdcells(); ct.setup_stdcells_mem(); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) { if (!design->selected(mod_it.second)) continue; diff --git a/passes/fsm/fsm_expand.cc b/passes/fsm/fsm_expand.cc index 40ec55c11..f107366d6 100644 --- a/passes/fsm/fsm_expand.cc +++ b/passes/fsm/fsm_expand.cc @@ -258,7 +258,7 @@ struct FsmExpandPass : public Pass { log_header("Executing FSM_EXPAND pass (merging auxiliary logic into FSMs).\n"); extra_args(args, 1, design); - for (auto &mod_it : design->modules) { + for (auto &mod_it : design->modules_) { if (!design->selected(mod_it.second)) continue; std::vector fsm_cells; diff --git a/passes/fsm/fsm_export.cc b/passes/fsm/fsm_export.cc index 129e7f9a6..f84f372ac 100644 --- a/passes/fsm/fsm_export.cc +++ b/passes/fsm/fsm_export.cc @@ -174,7 +174,7 @@ struct FsmExportPass : public Pass { } extra_args(args, argidx, design); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (design->selected(mod_it.second)) for (auto &cell_it : mod_it.second->cells_) if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second)) { diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index 64b01064a..99352b10a 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -330,7 +330,7 @@ struct FsmExtractPass : public Pass { ct.setup_stdcells(); ct.setup_stdcells_mem(); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) { if (!design->selected(mod_it.second)) continue; diff --git a/passes/fsm/fsm_info.cc b/passes/fsm/fsm_info.cc index 4526939ce..45d68a906 100644 --- a/passes/fsm/fsm_info.cc +++ b/passes/fsm/fsm_info.cc @@ -43,7 +43,7 @@ struct FsmInfoPass : public Pass { log_header("Executing FSM_INFO pass (dumping all available information on FSM cells).\n"); extra_args(args, 1, design); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (design->selected(mod_it.second)) for (auto &cell_it : mod_it.second->cells_) if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second)) { diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc index f6ef12a7a..8b9ad6be7 100644 --- a/passes/fsm/fsm_map.cc +++ b/passes/fsm/fsm_map.cc @@ -309,7 +309,7 @@ struct FsmMapPass : public Pass { log_header("Executing FSM_MAP pass (mapping FSMs to basic logic).\n"); extra_args(args, 1, design); - for (auto &mod_it : design->modules) { + for (auto &mod_it : design->modules_) { if (!design->selected(mod_it.second)) continue; std::vector fsm_cells; diff --git a/passes/fsm/fsm_opt.cc b/passes/fsm/fsm_opt.cc index 165b09747..9d9156ae3 100644 --- a/passes/fsm/fsm_opt.cc +++ b/passes/fsm/fsm_opt.cc @@ -288,7 +288,7 @@ struct FsmOptPass : public Pass { log_header("Executing FSM_OPT pass (simple optimizations of FSMs).\n"); extra_args(args, 1, design); - for (auto &mod_it : design->modules) { + for (auto &mod_it : design->modules_) { if (design->selected(mod_it.second)) for (auto &cell_it : mod_it.second->cells_) if (cell_it.second->type == "$fsm" and design->selected(mod_it.second, cell_it.second)) diff --git a/passes/fsm/fsm_recode.cc b/passes/fsm/fsm_recode.cc index 1b2eeb237..40fed130e 100644 --- a/passes/fsm/fsm_recode.cc +++ b/passes/fsm/fsm_recode.cc @@ -144,7 +144,7 @@ struct FsmRecodePass : public Pass { } extra_args(args, argidx, design); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (design->selected(mod_it.second)) for (auto &cell_it : mod_it.second->cells_) if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second)) diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 550ec39f0..8aec25eba 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -37,11 +37,11 @@ static void generate(RTLIL::Design *design, const std::vector &cell { std::set found_celltypes; - for (auto i1 : design->modules) + for (auto i1 : design->modules_) for (auto i2 : i1.second->cells_) { RTLIL::Cell *cell = i2.second; - if (cell->type[0] == '$' || design->modules.count(cell->type) > 0) + if (cell->type[0] == '$' || design->modules_.count(cell->type) > 0) continue; for (auto &pattern : celltypes) if (!fnmatch(pattern.c_str(), RTLIL::unescape_id(cell->type).c_str(), FNM_NOESCAPE)) @@ -55,7 +55,7 @@ static void generate(RTLIL::Design *design, const std::vector &cell std::map portwidths; log("Generate module for cell type %s:\n", celltype.c_str()); - for (auto i1 : design->modules) + for (auto i1 : design->modules_) for (auto i2 : i1.second->cells_) if (i2.second->type == celltype) { for (auto &conn : i2.second->connections()) { @@ -115,7 +115,7 @@ static void generate(RTLIL::Design *design, const std::vector &cell RTLIL::Module *mod = new RTLIL::Module; mod->name = celltype; mod->attributes["\\blackbox"] = RTLIL::Const(1); - design->modules[mod->name] = mod; + design->modules_[mod->name] = mod; for (auto &decl : ports) { RTLIL::Wire *wire = mod->addWire(decl.portname, portwidths.at(decl.portname)); @@ -151,11 +151,11 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla cell->type = cell->type.substr(pos_type + 1); } - if (design->modules.count(cell->type) == 0) + if (design->modules_.count(cell->type) == 0) { - if (design->modules.count("$abstract" + cell->type)) + if (design->modules_.count("$abstract" + cell->type)) { - cell->type = design->modules.at("$abstract" + cell->type)->derive(design, cell->parameters); + cell->type = design->modules_.at("$abstract" + cell->type)->derive(design, cell->parameters); cell->parameters.clear(); did_something = true; continue; @@ -189,7 +189,7 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla continue; loaded_module: - if (design->modules.count(cell->type) == 0) + if (design->modules_.count(cell->type) == 0) log_error("File `%s' from libdir does not declare module `%s'.\n", filename.c_str(), cell->type.c_str()); did_something = true; } @@ -197,10 +197,10 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla if (cell->parameters.size() == 0) continue; - if (design->modules.at(cell->type)->get_bool_attribute("\\blackbox")) + if (design->modules_.at(cell->type)->get_bool_attribute("\\blackbox")) continue; - RTLIL::Module *mod = design->modules[cell->type]; + RTLIL::Module *mod = design->modules_[cell->type]; cell->type = mod->derive(design, cell->parameters); cell->parameters.clear(); did_something = true; @@ -211,10 +211,10 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla RTLIL::Cell *cell = it.first; int idx = it.second.first, num = it.second.second; - if (design->modules.count(cell->type) == 0) + if (design->modules_.count(cell->type) == 0) log_error("Array cell `%s.%s' of unkown type `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); - RTLIL::Module *mod = design->modules[cell->type]; + RTLIL::Module *mod = design->modules_[cell->type]; for (auto &conn : cell->connections_) { int conn_size = conn.second.size(); @@ -253,8 +253,8 @@ static void hierarchy_worker(RTLIL::Design *design, std::set &us used.insert(mod); for (auto &it : mod->cells_) { - if (design->modules.count(it.second->type) > 0) - hierarchy_worker(design, used, design->modules[it.second->type], indent+4); + if (design->modules_.count(it.second->type) > 0) + hierarchy_worker(design, used, design->modules_[it.second->type], indent+4); } } @@ -264,7 +264,7 @@ static void hierarchy(RTLIL::Design *design, RTLIL::Module *top, bool purge_lib, hierarchy_worker(design, used, top, 0); std::vector del_modules; - for (auto &it : design->modules) + for (auto &it : design->modules_) if (used.count(it.second) == 0) del_modules.push_back(it.second); @@ -274,7 +274,7 @@ static void hierarchy(RTLIL::Design *design, RTLIL::Module *top, bool purge_lib, if (!purge_lib && mod->get_bool_attribute("\\blackbox")) continue; log("Removing unused module `%s'.\n", mod->name.c_str()); - design->modules.erase(mod->name); + design->modules_.erase(mod->name); delete mod; } @@ -412,11 +412,11 @@ struct HierarchyPass : public Pass { if (args[argidx] == "-top") { if (++argidx >= args.size()) log_cmd_error("Option -top requires an additional argument!\n"); - top_mod = design->modules.count(RTLIL::escape_id(args[argidx])) ? design->modules.at(RTLIL::escape_id(args[argidx])) : NULL; - if (top_mod == NULL && design->modules.count("$abstract" + RTLIL::escape_id(args[argidx]))) { + top_mod = design->modules_.count(RTLIL::escape_id(args[argidx])) ? design->modules_.at(RTLIL::escape_id(args[argidx])) : NULL; + if (top_mod == NULL && design->modules_.count("$abstract" + RTLIL::escape_id(args[argidx]))) { std::map empty_parameters; - design->modules.at("$abstract" + RTLIL::escape_id(args[argidx]))->derive(design, empty_parameters); - top_mod = design->modules.count(RTLIL::escape_id(args[argidx])) ? design->modules.at(RTLIL::escape_id(args[argidx])) : NULL; + design->modules_.at("$abstract" + RTLIL::escape_id(args[argidx]))->derive(design, empty_parameters); + top_mod = design->modules_.count(RTLIL::escape_id(args[argidx])) ? design->modules_.at(RTLIL::escape_id(args[argidx])) : NULL; } if (top_mod == NULL) log_cmd_error("Module `%s' not found!\n", args[argidx].c_str()); @@ -434,7 +434,7 @@ struct HierarchyPass : public Pass { log_push(); if (top_mod == NULL) - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (mod_it.second->get_bool_attribute("\\top")) top_mod = mod_it.second; @@ -446,13 +446,13 @@ struct HierarchyPass : public Pass { while (did_something) { did_something = false; std::vector modnames; - modnames.reserve(design->modules.size()); - for (auto &mod_it : design->modules) + modnames.reserve(design->modules_.size()); + for (auto &mod_it : design->modules_) modnames.push_back(mod_it.first); for (auto &modname : modnames) { - if (design->modules.count(modname) == 0) + if (design->modules_.count(modname) == 0) continue; - if (expand_module(design, design->modules[modname], flag_check, libdirs)) + if (expand_module(design, design->modules_[modname], flag_check, libdirs)) did_something = true; } if (did_something) @@ -465,7 +465,7 @@ struct HierarchyPass : public Pass { } if (top_mod != NULL) { - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (mod_it.second == top_mod) mod_it.second->attributes["\\top"] = RTLIL::Const(1); else @@ -478,14 +478,14 @@ struct HierarchyPass : public Pass { std::map, RTLIL::IdString> pos_map; std::vector> pos_work; - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) for (auto &cell_it : mod_it.second->cells_) { RTLIL::Cell *cell = cell_it.second; - if (design->modules.count(cell->type) == 0) + if (design->modules_.count(cell->type) == 0) continue; for (auto &conn : cell->connections()) if (conn.first[0] == '$' && '0' <= conn.first[1] && conn.first[1] <= '9') { - pos_mods.insert(design->modules.at(cell->type)); + pos_mods.insert(design->modules_.at(cell->type)); pos_work.push_back(std::pair(mod_it.second, cell)); break; } @@ -507,7 +507,7 @@ struct HierarchyPass : public Pass { for (auto &conn : cell->connections()) if (conn.first[0] == '$' && '0' <= conn.first[1] && conn.first[1] <= '9') { int id = atoi(conn.first.c_str()+1); - std::pair key(design->modules.at(cell->type), id); + std::pair key(design->modules_.at(cell->type), id); if (pos_map.count(key) == 0) { log(" Failed to map positional argument %d of cell %s.%s (%s).\n", id, RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index 374102756..d32b5e1d3 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -105,7 +105,7 @@ struct SubmodWorker RTLIL::Module *new_mod = new RTLIL::Module; new_mod->name = submod.full_name; - design->modules[new_mod->name] = new_mod; + design->modules_[new_mod->name] = new_mod; int port_counter = 1, auto_name_counter = 1; std::set all_wire_names; @@ -229,7 +229,7 @@ struct SubmodWorker if (submodules.count(submod_str) == 0) { submodules[submod_str].name = submod_str; submodules[submod_str].full_name = module->name + "_" + submod_str; - while (design->modules.count(submodules[submod_str].full_name) != 0 || + while (design->modules_.count(submodules[submod_str].full_name) != 0 || module->count_id(submodules[submod_str].full_name) != 0) submodules[submod_str].full_name += "_"; } @@ -312,12 +312,12 @@ struct SubmodPass : public Pass { while (did_something) { did_something = false; std::vector queued_modules; - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (handled_modules.count(mod_it.first) == 0 && design->selected_whole_module(mod_it.first)) queued_modules.push_back(mod_it.first); for (auto &modname : queued_modules) - if (design->modules.count(modname) != 0) { - SubmodWorker worker(design, design->modules[modname]); + if (design->modules_.count(modname) != 0) { + SubmodWorker worker(design, design->modules_[modname]); handled_modules.insert(modname); did_something = true; } @@ -328,7 +328,7 @@ struct SubmodPass : public Pass { else { RTLIL::Module *module = NULL; - for (auto &mod_it : design->modules) { + for (auto &mod_it : design->modules_) { if (!design->selected_module(mod_it.first)) continue; if (module != NULL) diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc index d5995ee0e..d2803ae78 100644 --- a/passes/memory/memory_collect.cc +++ b/passes/memory/memory_collect.cc @@ -200,7 +200,7 @@ struct MemoryCollectPass : public Pass { virtual void execute(std::vector args, RTLIL::Design *design) { log_header("Executing MEMORY_COLLECT pass (generating $mem cells).\n"); extra_args(args, 1, design); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (design->selected(mod_it.second)) handle_module(design, mod_it.second); } diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index bb8b052dc..9a1e96796 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -212,7 +212,7 @@ struct MemoryDffPass : public Pass { } extra_args(args, argidx, design); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (design->selected(mod_it.second)) handle_module(design, mod_it.second, flag_wr_only); } diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index 4bb0c8ccd..53394b19a 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -317,7 +317,7 @@ struct MemoryMapPass : public Pass { virtual void execute(std::vector args, RTLIL::Design *design) { log_header("Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).\n"); extra_args(args, 1, design); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (design->selected(mod_it.second)) handle_module(design, mod_it.second); } diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index b25cf73a7..e61661a20 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -734,7 +734,7 @@ struct MemorySharePass : public Pass { virtual void execute(std::vector args, RTLIL::Design *design) { log_header("Executing MEMORY_SHARE pass (consolidating $memrc/$memwr cells).\n"); extra_args(args, 1, design); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (design->selected(mod_it.second)) MemoryShareWorker(design, mod_it.second); } diff --git a/passes/memory/memory_unpack.cc b/passes/memory/memory_unpack.cc index 48b83f5fa..d2b9c0eeb 100644 --- a/passes/memory/memory_unpack.cc +++ b/passes/memory/memory_unpack.cc @@ -102,7 +102,7 @@ struct MemoryUnpackPass : public Pass { virtual void execute(std::vector args, RTLIL::Design *design) { log_header("Executing MEMORY_UNPACK pass (generating $memrd/$memwr cells form $mem cells).\n"); extra_args(args, 1, design); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (design->selected(mod_it.second)) handle_module(design, mod_it.second); } diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 4cc5fc89a..c219bc047 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -338,7 +338,7 @@ struct OptCleanPass : public Pass { ct_reg.setup_internals_mem(); ct_reg.setup_stdcells_mem(); - for (auto &mod_it : design->modules) { + for (auto &mod_it : design->modules_) { if (!design->selected_whole_module(mod_it.first)) { if (design->selected(mod_it.second)) log("Skipping module %s as it is only partially selected.\n", id2cstr(mod_it.second->name)); @@ -402,7 +402,7 @@ struct CleanPass : public Pass { count_rm_cells = 0; count_rm_wires = 0; - for (auto &mod_it : design->modules) { + for (auto &mod_it : design->modules_) { if (design->selected_whole_module(mod_it.first) && mod_it.second->processes.size() == 0) do { OPT_DID_SOMETHING = false; diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index 39e2254e0..bfd0161bf 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -939,7 +939,7 @@ struct OptConstPass : public Pass { } extra_args(args, argidx, design); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) { if (undriven) replace_undriven(design, mod_it.second); diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc index 1d4916b56..82cc78bed 100644 --- a/passes/opt/opt_muxtree.cc +++ b/passes/opt/opt_muxtree.cc @@ -423,7 +423,7 @@ struct OptMuxtreePass : public Pass { extra_args(args, 1, design); int total_count = 0; - for (auto &mod_it : design->modules) { + for (auto &mod_it : design->modules_) { if (!design->selected_whole_module(mod_it.first)) { if (design->selected(mod_it.second)) log("Skipping module %s as it is only partially selected.\n", id2cstr(mod_it.second->name)); diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc index d7de72353..b2b7cc8b9 100644 --- a/passes/opt/opt_reduce.cc +++ b/passes/opt/opt_reduce.cc @@ -367,7 +367,7 @@ struct OptReducePass : public Pass { extra_args(args, argidx, design); int total_count = 0; - for (auto &mod_it : design->modules) { + for (auto &mod_it : design->modules_) { if (!design->selected(mod_it.second)) continue; OptReduceWorker worker(design, mod_it.second, do_fine); diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc index 14b734d7d..b01778b5e 100644 --- a/passes/opt/opt_rmdff.cc +++ b/passes/opt/opt_rmdff.cc @@ -166,7 +166,7 @@ struct OptRmdffPass : public Pass { extra_args(args, 1, design); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) { if (!design->selected(mod_it.second)) continue; diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc index 304ba9f83..45130229f 100644 --- a/passes/opt/opt_share.cc +++ b/passes/opt/opt_share.cc @@ -315,7 +315,7 @@ struct OptSharePass : public Pass { extra_args(args, argidx, design); int total_count = 0; - for (auto &mod_it : design->modules) { + for (auto &mod_it : design->modules_) { if (!design->selected(mod_it.second)) continue; OptShareWorker worker(design, mod_it.second, mode_nomux); diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc index 63d04d351..e84394770 100644 --- a/passes/proc/proc_arst.cc +++ b/passes/proc/proc_arst.cc @@ -236,7 +236,7 @@ struct ProcArstPass : public Pass { extra_args(args, argidx, design); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (design->selected(mod_it.second)) { SigMap assign_map(mod_it.second); for (auto &proc_it : mod_it.second->processes) { diff --git a/passes/proc/proc_clean.cc b/passes/proc/proc_clean.cc index 682515c5e..678d620be 100644 --- a/passes/proc/proc_clean.cc +++ b/passes/proc/proc_clean.cc @@ -149,7 +149,7 @@ struct ProcCleanPass : public Pass { extra_args(args, 1, design); - for (auto &mod_it : design->modules) { + for (auto &mod_it : design->modules_) { std::vector delme; if (!design->selected(mod_it.second)) continue; diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index cfd2eb7a7..7bd909a68 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -371,7 +371,7 @@ struct ProcDffPass : public Pass { extra_args(args, 1, design); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (design->selected(mod_it.second)) { ConstEval ce(mod_it.second); for (auto &proc_it : mod_it.second->processes) diff --git a/passes/proc/proc_init.cc b/passes/proc/proc_init.cc index 5976c2162..3607905f5 100644 --- a/passes/proc/proc_init.cc +++ b/passes/proc/proc_init.cc @@ -101,7 +101,7 @@ struct ProcInitPass : public Pass { extra_args(args, 1, design); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (design->selected(mod_it.second)) for (auto &proc_it : mod_it.second->processes) if (design->selected(mod_it.second, proc_it.second)) diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc index 67113a682..bcbee6cfc 100644 --- a/passes/proc/proc_mux.cc +++ b/passes/proc/proc_mux.cc @@ -276,7 +276,7 @@ struct ProcMuxPass : public Pass { extra_args(args, 1, design); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (design->selected(mod_it.second)) for (auto &proc_it : mod_it.second->processes) if (design->selected(mod_it.second, proc_it.second)) diff --git a/passes/proc/proc_rmdead.cc b/passes/proc/proc_rmdead.cc index d5fbef0d2..e7e4bbc54 100644 --- a/passes/proc/proc_rmdead.cc +++ b/passes/proc/proc_rmdead.cc @@ -79,7 +79,7 @@ struct ProcRmdeadPass : public Pass { extra_args(args, 1, design); int total_counter = 0; - for (auto &mod_it : design->modules) { + for (auto &mod_it : design->modules_) { if (!design->selected(mod_it.second)) continue; for (auto &proc_it : mod_it.second->processes) { diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc index 454233267..8a2dd929b 100644 --- a/passes/sat/eval.cc +++ b/passes/sat/eval.cc @@ -306,10 +306,10 @@ struct VlogHammerReporter { for (auto name : split(module_list, ",")) { RTLIL::IdString esc_name = RTLIL::escape_id(module_prefix + name); - if (design->modules.count(esc_name) == 0) + if (design->modules_.count(esc_name) == 0) log_error("Can't find module %s in current design!\n", name.c_str()); log("Using module %s (%s).\n", esc_name.c_str(), name.c_str()); - modules.push_back(design->modules.at(esc_name)); + modules.push_back(design->modules_.at(esc_name)); module_names.push_back(name); } @@ -416,11 +416,11 @@ struct EvalPass : public Pass { /* this should only be used for regression testing of ConstEval -- see vloghammer */ std::string mod1_name = RTLIL::escape_id(args[++argidx]); std::string mod2_name = RTLIL::escape_id(args[++argidx]); - if (design->modules.count(mod1_name) == 0) + if (design->modules_.count(mod1_name) == 0) log_error("Can't find module `%s'!\n", mod1_name.c_str()); - if (design->modules.count(mod2_name) == 0) + if (design->modules_.count(mod2_name) == 0) log_error("Can't find module `%s'!\n", mod2_name.c_str()); - BruteForceEquivChecker checker(design->modules.at(mod1_name), design->modules.at(mod2_name), args[argidx-2] == "-brute_force_equiv_checker_x"); + BruteForceEquivChecker checker(design->modules_.at(mod1_name), design->modules_.at(mod2_name), args[argidx-2] == "-brute_force_equiv_checker_x"); if (checker.errors > 0) log_cmd_error("Modules are not equivialent!\n"); log("Verified %s = %s (using brute-force check on %d cases).\n", @@ -442,7 +442,7 @@ struct EvalPass : public Pass { extra_args(args, argidx, design); RTLIL::Module *module = NULL; - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (design->selected(mod_it.second)) { if (module) log_cmd_error("Only one module must be selected for the EVAL pass! (selected: %s and %s)\n", diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc index 24b812bb2..f2b89b000 100644 --- a/passes/sat/expose.cc +++ b/passes/sat/expose.cc @@ -50,7 +50,7 @@ static bool consider_cell(RTLIL::Design *design, std::set &dff_cell { if (cell->name[0] == '$' || dff_cells.count(cell->name)) return false; - if (cell->type.at(0) == '\\' && !design->modules.count(cell->type)) + if (cell->type.at(0) == '\\' && !design->modules_.count(cell->type)) return false; return true; } @@ -302,7 +302,7 @@ struct ExposePass : public Pass { RTLIL::Module *first_module = NULL; std::set shared_dff_wires; - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) { if (!design->selected(mod_it.second)) continue; @@ -352,7 +352,7 @@ struct ExposePass : public Pass { { RTLIL::Module *first_module = NULL; - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) { RTLIL::Module *module = mod_it.second; @@ -434,7 +434,7 @@ struct ExposePass : public Pass { } } - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) { RTLIL::Module *module = mod_it.second; @@ -583,9 +583,9 @@ struct ExposePass : public Pass { RTLIL::Cell *cell = it.second; - if (design->modules.count(cell->type)) + if (design->modules_.count(cell->type)) { - RTLIL::Module *mod = design->modules.at(cell->type); + RTLIL::Module *mod = design->modules_.at(cell->type); for (auto &it : mod->wires_) { diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index f8d5cf6c4..ad304c723 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -817,7 +817,7 @@ struct FreducePass : public Pass { extra_args(args, argidx, design); int bitcount = 0; - for (auto &mod_it : design->modules) { + for (auto &mod_it : design->modules_) { RTLIL::Module *module = mod_it.second; if (design->selected(module)) bitcount += FreduceWorker(design, module).run(); diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index 248f934c5..0f00e71a6 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -63,15 +63,15 @@ static void create_miter_equiv(struct Pass *that, std::vector args, std::string gate_name = RTLIL::escape_id(args[argidx++]); std::string miter_name = RTLIL::escape_id(args[argidx++]); - if (design->modules.count(gold_name) == 0) + if (design->modules_.count(gold_name) == 0) log_cmd_error("Can't find gold module %s!\n", gold_name.c_str()); - if (design->modules.count(gate_name) == 0) + if (design->modules_.count(gate_name) == 0) log_cmd_error("Can't find gate module %s!\n", gate_name.c_str()); - if (design->modules.count(miter_name) != 0) + if (design->modules_.count(miter_name) != 0) log_cmd_error("There is already a module %s!\n", gate_name.c_str()); - RTLIL::Module *gold_module = design->modules.at(gold_name); - RTLIL::Module *gate_module = design->modules.at(gate_name); + RTLIL::Module *gold_module = design->modules_.at(gold_name); + RTLIL::Module *gate_module = design->modules_.at(gate_name); for (auto &it : gold_module->wires_) { RTLIL::Wire *w1 = it.second, *w2; @@ -113,7 +113,7 @@ static void create_miter_equiv(struct Pass *that, std::vector args, RTLIL::Module *miter_module = new RTLIL::Module; miter_module->name = miter_name; - design->modules[miter_name] = miter_module; + design->modules_[miter_name] = miter_module; RTLIL::Cell *gold_cell = miter_module->addCell("\\gold", gold_name); RTLIL::Cell *gate_cell = miter_module->addCell("\\gate", gate_name); diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 3e1c72224..dce312065 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -1141,7 +1141,7 @@ struct SatPass : public Pass { extra_args(args, argidx, design); RTLIL::Module *module = NULL; - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (design->selected(mod_it.second)) { if (module) log_cmd_error("Only one module must be selected for the SAT pass! (selected: %s and %s)\n", diff --git a/passes/sat/share.cc b/passes/sat/share.cc index facacf196..671a631dd 100644 --- a/passes/sat/share.cc +++ b/passes/sat/share.cc @@ -961,7 +961,7 @@ struct SharePass : public Pass { } extra_args(args, argidx, design); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (design->selected(mod_it.second)) ShareWorker(config, design, mod_it.second); } diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc index 01284656d..ffe241182 100644 --- a/passes/techmap/dfflibmap.cc +++ b/passes/techmap/dfflibmap.cc @@ -524,7 +524,7 @@ struct DfflibmapPass : public Pass { log(" final dff cell mappings:\n"); logmap_all(); - for (auto &it : design->modules) + for (auto &it : design->modules_) if (design->selected(it.second) && !it.second->get_bool_attribute("\\blackbox")) dfflibmap(design, it.second); diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index b66a11b85..8587f53b0 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -604,9 +604,9 @@ struct ExtractPass : public Pass { delete map; log_cmd_error("Can't saved design `%s'.\n", filename.c_str()+1); } - for (auto &it : saved_designs.at(filename.substr(1))->modules) - if (!map->modules.count(it.first)) - map->modules[it.first] = it.second->clone(); + for (auto &it : saved_designs.at(filename.substr(1))->modules_) + if (!map->modules_.count(it.first)) + map->modules_[it.first] = it.second->clone(); } else { @@ -632,7 +632,7 @@ struct ExtractPass : public Pass { log_header("Creating graphs for SubCircuit library.\n"); if (!mine_mode) - for (auto &mod_it : map->modules) { + for (auto &mod_it : map->modules_) { SubCircuit::Graph mod_graph; std::string graph_name = "needle_" + RTLIL::unescape_id(mod_it.first); log("Creating needle graph %s.\n", graph_name.c_str()); @@ -643,7 +643,7 @@ struct ExtractPass : public Pass { } } - for (auto &mod_it : design->modules) { + for (auto &mod_it : design->modules_) { SubCircuit::Graph mod_graph; std::string graph_name = "haystack_" + RTLIL::unescape_id(mod_it.first); log("Creating haystack graph %s.\n", graph_name.c_str()); @@ -725,7 +725,7 @@ struct ExtractPass : public Pass { RTLIL::Module *newMod = new RTLIL::Module; newMod->name = stringf("\\needle%05d_%s_%dx", needleCounter++, id2cstr(haystack_map.at(result.graphId)->name), result.totalMatchesAfterLimits); - map->modules[newMod->name] = newMod; + map->modules_[newMod->name] = newMod; int portCounter = 1; for (auto wire : wires) { diff --git a/passes/techmap/hilomap.cc b/passes/techmap/hilomap.cc index 309777876..a3261dccd 100644 --- a/passes/techmap/hilomap.cc +++ b/passes/techmap/hilomap.cc @@ -104,7 +104,7 @@ struct HilomapPass : public Pass { } extra_args(args, argidx, design); - for (auto &it : design->modules) + for (auto &it : design->modules_) { module = it.second; diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc index 6f7427f03..10627cd12 100644 --- a/passes/techmap/iopadmap.cc +++ b/passes/techmap/iopadmap.cc @@ -111,7 +111,7 @@ struct IopadmapPass : public Pass { } extra_args(args, argidx, design); - for (auto &it : design->modules) + for (auto &it : design->modules_) { RTLIL::Module *module = it.second; diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc index 8c7f64230..6def10081 100644 --- a/passes/techmap/simplemap.cc +++ b/passes/techmap/simplemap.cc @@ -435,7 +435,7 @@ struct SimplemapPass : public Pass { std::map mappers; simplemap_get_mappers(mappers); - for (auto &mod_it : design->modules) { + for (auto &mod_it : design->modules_) { if (!design->selected(mod_it.second)) continue; std::vector delete_cells; diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 86d9e73ae..32e18e08b 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -243,7 +243,7 @@ struct TechmapWorker for (auto &tpl_name : celltypeMap.at(cell->type)) { std::string derived_name = tpl_name; - RTLIL::Module *tpl = map->modules[tpl_name]; + RTLIL::Module *tpl = map->modules_[tpl_name]; std::map parameters = cell->parameters; if (tpl->get_bool_attribute("\\blackbox")) @@ -334,7 +334,7 @@ struct TechmapWorker } else { if (cell->parameters.size() != 0) { derived_name = tpl->derive(map, parameters); - tpl = map->modules[derived_name]; + tpl = map->modules_[derived_name]; log_continue = true; } techmap_cache[key] = tpl; @@ -592,15 +592,15 @@ struct TechmapPass : public Pass { } std::map modules_new; - for (auto &it : map->modules) { + for (auto &it : map->modules_) { if (it.first.substr(0, 2) == "\\$") it.second->name = it.first.substr(1); modules_new[it.second->name] = it.second; } - map->modules.swap(modules_new); + map->modules_.swap(modules_new); std::map> celltypeMap; - for (auto &it : map->modules) { + for (auto &it : map->modules_) { if (it.second->attributes.count("\\techmap_celltype") && !it.second->attributes.at("\\techmap_celltype").bits.empty()) { char *p = strdup(it.second->attributes.at("\\techmap_celltype").decode_string().c_str()); for (char *q = strtok(p, " \t\r\n"); q; q = strtok(NULL, " \t\r\n")) @@ -614,7 +614,7 @@ struct TechmapPass : public Pass { std::set handled_cells; while (did_something) { did_something = false; - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (worker.techmap_module(design, mod_it.second, map, handled_cells, celltypeMap, false)) did_something = true; if (did_something) @@ -653,12 +653,12 @@ struct FlattenPass : public Pass { TechmapWorker worker; std::map> celltypeMap; - for (auto &it : design->modules) + for (auto &it : design->modules_) celltypeMap[it.first].insert(it.first); RTLIL::Module *top_mod = NULL; if (design->full_selection()) - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (mod_it.second->get_bool_attribute("\\top")) top_mod = mod_it.second; @@ -670,7 +670,7 @@ struct FlattenPass : public Pass { if (worker.techmap_module(design, top_mod, design, handled_cells, celltypeMap, true)) did_something = true; } else { - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (worker.techmap_module(design, mod_it.second, design, handled_cells, celltypeMap, true)) did_something = true; } @@ -680,14 +680,14 @@ struct FlattenPass : public Pass { if (top_mod != NULL) { std::map new_modules; - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (mod_it.second == top_mod || mod_it.second->get_bool_attribute("\\blackbox")) { new_modules[mod_it.first] = mod_it.second; } else { log("Deleting now unused module %s.\n", RTLIL::id2cstr(mod_it.first)); delete mod_it.second; } - design->modules.swap(new_modules); + design->modules_.swap(new_modules); } log_pop(); -- cgit v1.2.3 From 49f72421d5ec499da5da713466e058aae2a67436 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 10:41:42 +0200 Subject: Using new obj iterator API in a few places --- passes/memory/memory_dff.cc | 26 +++++++++++--------------- passes/opt/opt_muxtree.cc | 23 +++++++++++------------ passes/proc/proc_arst.cc | 25 +++++++++++++++---------- passes/proc/proc_clean.cc | 16 ++++++++-------- passes/proc/proc_dff.cc | 12 ++++++------ passes/proc/proc_init.cc | 10 +++++----- passes/proc/proc_mux.cc | 10 +++++----- passes/proc/proc_rmdead.cc | 10 +++++----- passes/techmap/simplemap.cc | 20 +++++++++----------- passes/techmap/techmap.cc | 20 ++++++++++---------- 10 files changed, 85 insertions(+), 87 deletions(-) (limited to 'passes') diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index 9a1e96796..85249142e 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -38,10 +38,8 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI if (bit.wire == NULL) continue; - for (auto &cell_it : module->cells_) + for (auto cell : module->cells()) { - RTLIL::Cell *cell = cell_it.second; - if (cell->type != "$dff") continue; @@ -120,14 +118,12 @@ static void disconnect_dff(RTLIL::Module *module, RTLIL::SigSpec sig) RTLIL::SigSpec new_sig = module->addWire(sstr.str(), sig.size()); - for (auto &cell_it : module->cells_) { - RTLIL::Cell *cell = cell_it.second; + for (auto cell : module->cells()) if (cell->type == "$dff") { RTLIL::SigSpec new_q = cell->get("\\Q"); new_q.replace(sig, new_sig); cell->set("\\Q", new_q); } - } } static void handle_rd_cell(RTLIL::Module *module, RTLIL::Cell *cell) @@ -170,13 +166,13 @@ static void handle_rd_cell(RTLIL::Module *module, RTLIL::Cell *cell) static void handle_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_wr_only) { - for (auto &cell_it : module->cells_) { - if (!design->selected(module, cell_it.second)) + for (auto cell : module->cells()) { + if (!design->selected(module, cell)) continue; - if (cell_it.second->type == "$memwr" && !cell_it.second->parameters["\\CLK_ENABLE"].as_bool()) - handle_wr_cell(module, cell_it.second); - if (!flag_wr_only && cell_it.second->type == "$memrd" && !cell_it.second->parameters["\\CLK_ENABLE"].as_bool()) - handle_rd_cell(module, cell_it.second); + if (cell->type == "$memwr" && !cell->parameters["\\CLK_ENABLE"].as_bool()) + handle_wr_cell(module, cell); + if (!flag_wr_only && cell->type == "$memrd" && !cell->parameters["\\CLK_ENABLE"].as_bool()) + handle_rd_cell(module, cell); } } @@ -212,9 +208,9 @@ struct MemoryDffPass : public Pass { } extra_args(args, argidx, design); - for (auto &mod_it : design->modules_) - if (design->selected(mod_it.second)) - handle_module(design, mod_it.second, flag_wr_only); + for (auto mod : design->modules()) + if (design->selected(mod)) + handle_module(design, mod, flag_wr_only); } } MemoryDffPass; diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc index 82cc78bed..73baaf900 100644 --- a/passes/opt/opt_muxtree.cc +++ b/passes/opt/opt_muxtree.cc @@ -83,9 +83,8 @@ struct OptMuxtreeWorker // .ctrl_sigs // .input_sigs // .const_activated - for (auto &cell_it : module->cells_) + for (auto cell : module->cells()) { - RTLIL::Cell *cell = cell_it.second; if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux") { RTLIL::SigSpec sig_a = cell->get("\\A"); @@ -136,9 +135,9 @@ struct OptMuxtreeWorker } } } - for (auto &it : module->wires_) { - if (it.second->port_output) - for (int idx : sig2bits(RTLIL::SigSpec(it.second))) + for (auto wire : module->wires()) { + if (wire->port_output) + for (int idx : sig2bits(RTLIL::SigSpec(wire))) bit2info[idx].seen_non_mux = true; } @@ -423,16 +422,16 @@ struct OptMuxtreePass : public Pass { extra_args(args, 1, design); int total_count = 0; - for (auto &mod_it : design->modules_) { - if (!design->selected_whole_module(mod_it.first)) { - if (design->selected(mod_it.second)) - log("Skipping module %s as it is only partially selected.\n", id2cstr(mod_it.second->name)); + for (auto mod : design->modules()) { + if (!design->selected_whole_module(mod)) { + if (design->selected(mod)) + log("Skipping module %s as it is only partially selected.\n", log_id(mod)); continue; } - if (mod_it.second->processes.size() > 0) { - log("Skipping module %s as it contains processes.\n", id2cstr(mod_it.second->name)); + if (mod->processes.size() > 0) { + log("Skipping module %s as it contains processes.\n", log_id(mod)); } else { - OptMuxtreeWorker worker(design, mod_it.second); + OptMuxtreeWorker worker(design, mod); total_count += worker.removed_count; } } diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc index e84394770..676469fe2 100644 --- a/passes/proc/proc_arst.cc +++ b/passes/proc/proc_arst.cc @@ -33,20 +33,24 @@ static bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSp if (signal == ref) return true; - for (auto &cell_it : mod->cells_) { - RTLIL::Cell *cell = cell_it.second; + for (auto cell : mod->cells()) + { if (cell->type == "$reduce_or" && cell->get("\\Y") == signal) return check_signal(mod, cell->get("\\A"), ref, polarity); + if (cell->type == "$reduce_bool" && cell->get("\\Y") == signal) return check_signal(mod, cell->get("\\A"), ref, polarity); + if (cell->type == "$logic_not" && cell->get("\\Y") == signal) { polarity = !polarity; return check_signal(mod, cell->get("\\A"), ref, polarity); } + if (cell->type == "$not" && cell->get("\\Y") == signal) { polarity = !polarity; return check_signal(mod, cell->get("\\A"), ref, polarity); } + if ((cell->type == "$eq" || cell->type == "$eqx") && cell->get("\\Y") == signal) { if (cell->get("\\A").is_fully_const()) { if (!cell->get("\\A").as_bool()) @@ -59,6 +63,7 @@ static bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSp return check_signal(mod, cell->get("\\A"), ref, polarity); } } + if ((cell->type == "$ne" || cell->type == "$nex") && cell->get("\\Y") == signal) { if (cell->get("\\A").is_fully_const()) { if (cell->get("\\A").as_bool()) @@ -236,14 +241,14 @@ struct ProcArstPass : public Pass { extra_args(args, argidx, design); - for (auto &mod_it : design->modules_) - if (design->selected(mod_it.second)) { - SigMap assign_map(mod_it.second); - for (auto &proc_it : mod_it.second->processes) { - if (!design->selected(mod_it.second, proc_it.second)) + for (auto mod : design->modules()) + if (design->selected(mod)) { + SigMap assign_map(mod); + for (auto &proc_it : mod->processes) { + if (!design->selected(mod, proc_it.second)) continue; - proc_arst(mod_it.second, proc_it.second, assign_map); - if (global_arst.empty() || mod_it.second->wires_.count(global_arst) == 0) + proc_arst(mod, proc_it.second, assign_map); + if (global_arst.empty() || mod->wire(global_arst) == nullptr) continue; std::vector arst_actions; for (auto sync : proc_it.second->syncs) @@ -266,7 +271,7 @@ struct ProcArstPass : public Pass { if (!arst_actions.empty()) { RTLIL::SyncRule *sync = new RTLIL::SyncRule; sync->type = global_arst_neg ? RTLIL::SyncType::ST0 : RTLIL::SyncType::ST1; - sync->signal = mod_it.second->wires_.at(global_arst); + sync->signal = mod->wire(global_arst); sync->actions = arst_actions; proc_it.second->syncs.push_back(sync); } diff --git a/passes/proc/proc_clean.cc b/passes/proc/proc_clean.cc index 678d620be..e4c526632 100644 --- a/passes/proc/proc_clean.cc +++ b/passes/proc/proc_clean.cc @@ -149,23 +149,23 @@ struct ProcCleanPass : public Pass { extra_args(args, 1, design); - for (auto &mod_it : design->modules_) { + for (auto mod : design->modules()) { std::vector delme; - if (!design->selected(mod_it.second)) + if (!design->selected(mod)) continue; - for (auto &proc_it : mod_it.second->processes) { - if (!design->selected(mod_it.second, proc_it.second)) + for (auto &proc_it : mod->processes) { + if (!design->selected(mod, proc_it.second)) continue; - proc_clean(mod_it.second, proc_it.second, total_count); + proc_clean(mod, proc_it.second, total_count); if (proc_it.second->syncs.size() == 0 && proc_it.second->root_case.switches.size() == 0 && proc_it.second->root_case.actions.size() == 0) { - log("Removing empty process `%s.%s'.\n", mod_it.first.c_str(), proc_it.second->name.c_str()); + log("Removing empty process `%s.%s'.\n", log_id(mod), proc_it.second->name.c_str()); delme.push_back(proc_it.first); } } for (auto &id : delme) { - delete mod_it.second->processes[id]; - mod_it.second->processes.erase(id); + delete mod->processes[id]; + mod->processes.erase(id); } } diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index 7bd909a68..dc310bde0 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -371,12 +371,12 @@ struct ProcDffPass : public Pass { extra_args(args, 1, design); - for (auto &mod_it : design->modules_) - if (design->selected(mod_it.second)) { - ConstEval ce(mod_it.second); - for (auto &proc_it : mod_it.second->processes) - if (design->selected(mod_it.second, proc_it.second)) - proc_dff(mod_it.second, proc_it.second, ce); + for (auto mod : design->modules()) + if (design->selected(mod)) { + ConstEval ce(mod); + for (auto &proc_it : mod->processes) + if (design->selected(mod, proc_it.second)) + proc_dff(mod, proc_it.second, ce); } } } ProcDffPass; diff --git a/passes/proc/proc_init.cc b/passes/proc/proc_init.cc index 3607905f5..99498505f 100644 --- a/passes/proc/proc_init.cc +++ b/passes/proc/proc_init.cc @@ -101,11 +101,11 @@ struct ProcInitPass : public Pass { extra_args(args, 1, design); - for (auto &mod_it : design->modules_) - if (design->selected(mod_it.second)) - for (auto &proc_it : mod_it.second->processes) - if (design->selected(mod_it.second, proc_it.second)) - proc_init(mod_it.second, proc_it.second); + for (auto mod : design->modules()) + if (design->selected(mod)) + for (auto &proc_it : mod->processes) + if (design->selected(mod, proc_it.second)) + proc_init(mod, proc_it.second); } } ProcInitPass; diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc index bcbee6cfc..fb49182c2 100644 --- a/passes/proc/proc_mux.cc +++ b/passes/proc/proc_mux.cc @@ -276,11 +276,11 @@ struct ProcMuxPass : public Pass { extra_args(args, 1, design); - for (auto &mod_it : design->modules_) - if (design->selected(mod_it.second)) - for (auto &proc_it : mod_it.second->processes) - if (design->selected(mod_it.second, proc_it.second)) - proc_mux(mod_it.second, proc_it.second); + for (auto mod : design->modules()) + if (design->selected(mod)) + for (auto &proc_it : mod->processes) + if (design->selected(mod, proc_it.second)) + proc_mux(mod, proc_it.second); } } ProcMuxPass; diff --git a/passes/proc/proc_rmdead.cc b/passes/proc/proc_rmdead.cc index e7e4bbc54..9e5f413a2 100644 --- a/passes/proc/proc_rmdead.cc +++ b/passes/proc/proc_rmdead.cc @@ -79,18 +79,18 @@ struct ProcRmdeadPass : public Pass { extra_args(args, 1, design); int total_counter = 0; - for (auto &mod_it : design->modules_) { - if (!design->selected(mod_it.second)) + for (auto mod : design->modules()) { + if (!design->selected(mod)) continue; - for (auto &proc_it : mod_it.second->processes) { - if (!design->selected(mod_it.second, proc_it.second)) + for (auto &proc_it : mod->processes) { + if (!design->selected(mod, proc_it.second)) continue; int counter = 0; for (auto switch_it : proc_it.second->root_case.switches) proc_rmdead(switch_it, counter); if (counter > 0) log("Removed %d dead cases from process %s in module %s.\n", counter, - proc_it.first.c_str(), mod_it.first.c_str()); + proc_it.first.c_str(), log_id(mod)); total_counter += counter; } } diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc index 6def10081..b327ba832 100644 --- a/passes/techmap/simplemap.cc +++ b/passes/techmap/simplemap.cc @@ -435,21 +435,19 @@ struct SimplemapPass : public Pass { std::map mappers; simplemap_get_mappers(mappers); - for (auto &mod_it : design->modules_) { - if (!design->selected(mod_it.second)) + for (auto mod : design->modules()) { + if (!design->selected(mod)) continue; - std::vector delete_cells; - for (auto &cell_it : mod_it.second->cells_) { - if (mappers.count(cell_it.second->type) == 0) + std::vector cells = mod->cells(); + for (auto cell : cells) { + if (mappers.count(cell->type) == 0) continue; - if (!design->selected(mod_it.second, cell_it.second)) + if (!design->selected(mod, cell)) continue; - log("Mapping %s.%s (%s).\n", RTLIL::id2cstr(mod_it.first), RTLIL::id2cstr(cell_it.first), RTLIL::id2cstr(cell_it.second->type)); - mappers.at(cell_it.second->type)(mod_it.second, cell_it.second); - delete_cells.push_back(cell_it.second); + log("Mapping %s.%s (%s).\n", log_id(mod), log_id(cell), log_id(cell->type)); + mappers.at(cell->type)(mod, cell); + mod->remove(cell); } - for (auto c : delete_cells) - mod_it.second->remove(c); } } } SimplemapPass; diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 32e18e08b..bcae44091 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -658,9 +658,9 @@ struct FlattenPass : public Pass { RTLIL::Module *top_mod = NULL; if (design->full_selection()) - for (auto &mod_it : design->modules_) - if (mod_it.second->get_bool_attribute("\\top")) - top_mod = mod_it.second; + for (auto mod : design->modules()) + if (mod->get_bool_attribute("\\top")) + top_mod = mod; bool did_something = true; std::set handled_cells; @@ -670,8 +670,8 @@ struct FlattenPass : public Pass { if (worker.techmap_module(design, top_mod, design, handled_cells, celltypeMap, true)) did_something = true; } else { - for (auto &mod_it : design->modules_) - if (worker.techmap_module(design, mod_it.second, design, handled_cells, celltypeMap, true)) + for (auto mod : design->modules()) + if (worker.techmap_module(design, mod, design, handled_cells, celltypeMap, true)) did_something = true; } } @@ -680,12 +680,12 @@ struct FlattenPass : public Pass { if (top_mod != NULL) { std::map new_modules; - for (auto &mod_it : design->modules_) - if (mod_it.second == top_mod || mod_it.second->get_bool_attribute("\\blackbox")) { - new_modules[mod_it.first] = mod_it.second; + for (auto mod : design->modules()) + if (mod == top_mod || mod->get_bool_attribute("\\blackbox")) { + new_modules[mod->name] = mod; } else { - log("Deleting now unused module %s.\n", RTLIL::id2cstr(mod_it.first)); - delete mod_it.second; + log("Deleting now unused module %s.\n", log_id(mod)); + delete mod; } design->modules_.swap(new_modules); } -- cgit v1.2.3 From d878fcbdc76f4b612ba8578213f73f27585fc792 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 12:04:12 +0200 Subject: Added log_cmd_error_expection --- passes/fsm/fsm_export.cc | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'passes') diff --git a/passes/fsm/fsm_export.cc b/passes/fsm/fsm_export.cc index f84f372ac..f6f9faa9b 100644 --- a/passes/fsm/fsm_export.cc +++ b/passes/fsm/fsm_export.cc @@ -32,10 +32,7 @@ * Convert a signal into a KISS-compatible textual representation. */ std::string kiss_convert_signal(const RTLIL::SigSpec &sig) { - if (!sig.is_fully_const()) { - throw 0; - } - + log_assert(sig.is_fully_const()); return sig.as_const().as_string(); } -- cgit v1.2.3 From dbb3556e3f1e82a6b69d5e8714a0266c1d461c7c Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 13:19:05 +0200 Subject: Fixed a bug in opt_clean and some RTLIL API usage cleanups --- passes/opt/opt_clean.cc | 7 ++++--- passes/opt/opt_const.cc | 20 ++++++++++---------- 2 files changed, 14 insertions(+), 13 deletions(-) (limited to 'passes') diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index c219bc047..21bda6e4e 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -219,8 +219,8 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool } std::vector maybe_del_wires; - for (auto &it : module->wires_) { - RTLIL::Wire *wire = it.second; + for (auto wire : module->wires()) + { if ((!purge_mode && check_public_name(wire->name)) || wire->port_id != 0 || wire->get_bool_attribute("\\keep")) { RTLIL::SigSpec s1 = RTLIL::SigSpec(wire), s2 = s1; assign_map.apply(s2); @@ -244,6 +244,7 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool if (!used_signals.check_any(RTLIL::SigSpec(wire))) maybe_del_wires.push_back(wire); } + RTLIL::SigSpec sig = assign_map(RTLIL::SigSpec(wire)); if (!used_signals_nodrivers.check_any(sig)) { std::string unused_bits; @@ -269,7 +270,7 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool std::set del_wires; int del_wires_count = 0; - for (auto wire : del_wires) + for (auto wire : maybe_del_wires) if (!used_signals.check_any(RTLIL::SigSpec(wire))) { if (check_public_name(wire->name) && verbose) { log(" removing unused non-port wire %s.\n", wire->name.c_str()); diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index bfd0161bf..9a21bdcaf 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -37,20 +37,20 @@ static void replace_undriven(RTLIL::Design *design, RTLIL::Module *module) SigPool used_signals; SigPool all_signals; - for (auto &it : module->cells_) - for (auto &conn : it.second->connections()) { - if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first)) + for (auto cell : module->cells()) + for (auto &conn : cell->connections()) { + if (!ct.cell_known(cell->type) || ct.cell_output(cell->type, conn.first)) driven_signals.add(sigmap(conn.second)); - if (!ct.cell_known(it.second->type) || ct.cell_input(it.second->type, conn.first)) + if (!ct.cell_known(cell->type) || ct.cell_input(cell->type, conn.first)) used_signals.add(sigmap(conn.second)); } - for (auto &it : module->wires_) { - if (it.second->port_input) - driven_signals.add(sigmap(it.second)); - if (it.second->port_output) - used_signals.add(sigmap(it.second)); - all_signals.add(sigmap(it.second)); + for (auto wire : module->wires()) { + if (wire->port_input) + driven_signals.add(sigmap(wire)); + if (wire->port_output) + used_signals.add(sigmap(wire)); + all_signals.add(sigmap(wire)); } all_signals.del(driven_signals); -- cgit v1.2.3 From d07a871d35401b6b8628dd3f1df3b91149e827d5 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 14:50:25 +0200 Subject: Improved performance of opt_const on large modules --- passes/opt/opt_const.cc | 83 ++++++++++++++++++++++++++++++++----------------- 1 file changed, 54 insertions(+), 29 deletions(-) (limited to 'passes') diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index 9a21bdcaf..7578f1927 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -21,6 +21,7 @@ #include "kernel/register.h" #include "kernel/sigtools.h" #include "kernel/celltypes.h" +#include "kernel/toposort.h" #include "kernel/log.h" #include #include @@ -71,7 +72,7 @@ static void replace_undriven(RTLIL::Design *design, RTLIL::Module *module) } } -static void replace_cell(RTLIL::Module *module, RTLIL::Cell *cell, std::string info, std::string out_port, RTLIL::SigSpec out_val) +static void replace_cell(SigMap &assign_map, RTLIL::Module *module, RTLIL::Cell *cell, std::string info, std::string out_port, RTLIL::SigSpec out_val) { RTLIL::SigSpec Y = cell->get(out_port); out_val.extend_u0(Y.size(), false); @@ -80,7 +81,8 @@ static void replace_cell(RTLIL::Module *module, RTLIL::Cell *cell, std::string i cell->type.c_str(), cell->name.c_str(), info.c_str(), module->name.c_str(), log_signal(Y), log_signal(out_val)); // ILANG_BACKEND::dump_cell(stderr, "--> ", cell); - module->connect(RTLIL::SigSig(Y, out_val)); + assign_map.add(Y, out_val); + module->connect(Y, out_val); module->remove(cell); OPT_DID_SOMETHING = true; did_something = true; @@ -195,22 +197,45 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (!design->selected(module)) return; + CellTypes ct_combinational; + ct_combinational.setup_internals(); + ct_combinational.setup_stdcells(); + SigMap assign_map(module); std::map invert_map; - std::vector cells; - cells.reserve(module->cells_.size()); - for (auto &cell_it : module->cells_) - if (design->selected(module, cell_it.second)) { - if ((cell_it.second->type == "$_INV_" || cell_it.second->type == "$not" || cell_it.second->type == "$logic_not") && - cell_it.second->get("\\A").size() == 1 && cell_it.second->get("\\Y").size() == 1) - invert_map[assign_map(cell_it.second->get("\\Y"))] = assign_map(cell_it.second->get("\\A")); - cells.push_back(cell_it.second); + TopoSort cells; + std::map> cell_to_inbit; + std::map> outbit_to_cell; + + for (auto cell : module->cells()) + if (design->selected(module, cell) && cell->type[0] == '$') { + if ((cell->type == "$_INV_" || cell->type == "$not" || cell->type == "$logic_not") && + cell->get("\\A").size() == 1 && cell->get("\\Y").size() == 1) + invert_map[assign_map(cell->get("\\Y"))] = assign_map(cell->get("\\A")); + if (ct_combinational.cell_known(cell->type)) + for (auto &conn : cell->connections()) { + RTLIL::SigSpec sig = assign_map(conn.second); + sig.remove_const(); + if (ct_combinational.cell_input(cell->type, conn.first)) + cell_to_inbit[cell].insert(sig.begin(), sig.end()); + if (ct_combinational.cell_output(cell->type, conn.first)) + for (auto &bit : sig) + outbit_to_cell[bit].insert(cell); + } + cells.node(cell); } - for (auto cell : cells) + for (auto &it_right : cell_to_inbit) + for (auto &it_sigbit : it_right.second) + for (auto &it_left : outbit_to_cell[it_sigbit]) + cells.edge(it_left, it_right.first); + + cells.sort(); + + for (auto cell : cells.sorted) { -#define ACTION_DO(_p_, _s_) do { cover("opt.opt_const.action_" S__LINE__); replace_cell(module, cell, input.as_string(), _p_, _s_); goto next_cell; } while (0) +#define ACTION_DO(_p_, _s_) do { cover("opt.opt_const.action_" S__LINE__); replace_cell(assign_map, module, cell, input.as_string(), _p_, _s_); goto next_cell; } while (0) #define ACTION_DO_Y(_v_) ACTION_DO("\\Y", RTLIL::SigSpec(RTLIL::State::S ## _v_)) if (do_fine) @@ -304,13 +329,13 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (cell->type == "$logic_or" && (assign_map(cell->get("\\A")) == RTLIL::State::S1 || assign_map(cell->get("\\B")) == RTLIL::State::S1)) { cover("opt.opt_const.one_high"); - replace_cell(module, cell, "one high", "\\Y", RTLIL::State::S1); + replace_cell(assign_map, module, cell, "one high", "\\Y", RTLIL::State::S1); goto next_cell; } if (cell->type == "$logic_and" && (assign_map(cell->get("\\A")) == RTLIL::State::S0 || assign_map(cell->get("\\B")) == RTLIL::State::S0)) { cover("opt.opt_const.one_low"); - replace_cell(module, cell, "one low", "\\Y", RTLIL::State::S0); + replace_cell(assign_map, module, cell, "one low", "\\Y", RTLIL::State::S0); goto next_cell; } @@ -340,9 +365,9 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo "$neg", "$add", "$sub", "$mul", "$div", "$mod", "$pow", cell->type); if (cell->type == "$reduce_xor" || cell->type == "$reduce_xnor" || cell->type == "$lt" || cell->type == "$le" || cell->type == "$ge" || cell->type == "$gt") - replace_cell(module, cell, "x-bit in input", "\\Y", RTLIL::State::Sx); + replace_cell(assign_map, module, cell, "x-bit in input", "\\Y", RTLIL::State::Sx); else - replace_cell(module, cell, "x-bit in input", "\\Y", RTLIL::SigSpec(RTLIL::State::Sx, cell->get("\\Y").size())); + replace_cell(assign_map, module, cell, "x-bit in input", "\\Y", RTLIL::SigSpec(RTLIL::State::Sx, cell->get("\\Y").size())); goto next_cell; } } @@ -350,7 +375,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if ((cell->type == "$_INV_" || cell->type == "$not" || cell->type == "$logic_not") && cell->get("\\Y").size() == 1 && invert_map.count(assign_map(cell->get("\\A"))) != 0) { cover_list("opt.opt_const.invert.double", "$_INV_", "$not", "$logic_not", cell->type); - replace_cell(module, cell, "double_invert", "\\Y", invert_map.at(assign_map(cell->get("\\A")))); + replace_cell(assign_map, module, cell, "double_invert", "\\Y", invert_map.at(assign_map(cell->get("\\A")))); goto next_cell; } @@ -476,7 +501,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cover_list("opt.opt_const.eqneq.isneq", "$eq", "$ne", "$eqx", "$nex", cell->type); RTLIL::SigSpec new_y = RTLIL::SigSpec((cell->type == "$eq" || cell->type == "$eqx") ? RTLIL::State::S0 : RTLIL::State::S1); new_y.extend(cell->parameters["\\Y_WIDTH"].as_int(), false); - replace_cell(module, cell, "isneq", "\\Y", new_y); + replace_cell(assign_map, module, cell, "isneq", "\\Y", new_y); goto next_cell; } if (a[i] == b[i]) @@ -489,7 +514,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cover_list("opt.opt_const.eqneq.empty", "$eq", "$ne", "$eqx", "$nex", cell->type); RTLIL::SigSpec new_y = RTLIL::SigSpec((cell->type == "$eq" || cell->type == "$eqx") ? RTLIL::State::S1 : RTLIL::State::S0); new_y.extend(cell->parameters["\\Y_WIDTH"].as_int(), false); - replace_cell(module, cell, "empty", "\\Y", new_y); + replace_cell(assign_map, module, cell, "empty", "\\Y", new_y); goto next_cell; } @@ -607,7 +632,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->get("\\A") == RTLIL::SigSpec(0, 1) && cell->get("\\B") == RTLIL::SigSpec(1, 1)) { cover_list("opt.opt_const.mux_bool", "$mux", "$_MUX_", cell->type); - replace_cell(module, cell, "mux_bool", "\\Y", cell->get("\\S")); + replace_cell(assign_map, module, cell, "mux_bool", "\\Y", cell->get("\\S")); goto next_cell; } @@ -674,7 +699,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if ((cell->get("\\A").is_fully_undef() && cell->get("\\B").is_fully_undef()) || cell->get("\\S").is_fully_undef()) { cover_list("opt.opt_const.mux_undef", "$mux", "$pmux", cell->type); - replace_cell(module, cell, "mux_undef", "\\Y", cell->get("\\A")); + replace_cell(assign_map, module, cell, "mux_undef", "\\Y", cell->get("\\A")); goto next_cell; } for (int i = 0; i < cell->get("\\S").size(); i++) { @@ -693,12 +718,12 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo } if (new_s.size() == 0) { cover_list("opt.opt_const.mux_empty", "$mux", "$pmux", cell->type); - replace_cell(module, cell, "mux_empty", "\\Y", new_a); + replace_cell(assign_map, module, cell, "mux_empty", "\\Y", new_a); goto next_cell; } if (new_a == RTLIL::SigSpec(RTLIL::State::S0) && new_b == RTLIL::SigSpec(RTLIL::State::S1)) { cover_list("opt.opt_const.mux_sel01", "$mux", "$pmux", cell->type); - replace_cell(module, cell, "mux_sel01", "\\Y", new_s); + replace_cell(assign_map, module, cell, "mux_sel01", "\\Y", new_s); goto next_cell; } if (cell->get("\\S").size() != new_s.size()) { @@ -728,7 +753,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cell->parameters["\\A_SIGNED"].as_bool(), false, \ cell->parameters["\\Y_WIDTH"].as_int())); \ cover("opt.opt_const.const.$" #_t); \ - replace_cell(module, cell, stringf("%s", log_signal(a)), "\\Y", y); \ + replace_cell(assign_map, module, cell, stringf("%s", log_signal(a)), "\\Y", y); \ goto next_cell; \ } \ } @@ -743,7 +768,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cell->parameters["\\B_SIGNED"].as_bool(), \ cell->parameters["\\Y_WIDTH"].as_int())); \ cover("opt.opt_const.const.$" #_t); \ - replace_cell(module, cell, stringf("%s, %s", log_signal(a), log_signal(b)), "\\Y", y); \ + replace_cell(assign_map, module, cell, stringf("%s, %s", log_signal(a), log_signal(b)), "\\Y", y); \ goto next_cell; \ } \ } @@ -939,17 +964,17 @@ struct OptConstPass : public Pass { } extra_args(args, argidx, design); - for (auto &mod_it : design->modules_) + for (auto module : design->modules()) { if (undriven) - replace_undriven(design, mod_it.second); + replace_undriven(design, module); do { do { did_something = false; - replace_const_cells(design, mod_it.second, false, mux_undef, mux_bool, do_fine, keepdc); + replace_const_cells(design, module, false, mux_undef, mux_bool, do_fine, keepdc); } while (did_something); - replace_const_cells(design, mod_it.second, true, mux_undef, mux_bool, do_fine, keepdc); + replace_const_cells(design, module, true, mux_undef, mux_bool, do_fine, keepdc); } while (did_something); } -- cgit v1.2.3 From 77a1462f2d6602d5c46a2a15ca534550ec5bb9a4 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 15:13:29 +0200 Subject: Fixed bug in opt_clean --- passes/opt/opt_clean.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 21bda6e4e..76a905b2c 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -251,7 +251,7 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool for (int i = 0; i < SIZE(sig); i++) { if (sig[i].wire == NULL) continue; - if (!used_signals_nodrivers.check_any(sig)) { + if (!used_signals_nodrivers.check_any(sig[i])) { if (!unused_bits.empty()) unused_bits += " "; unused_bits += stringf("%zd", i); -- cgit v1.2.3 From 0c86d6106c3ff4cd7628b1206281eb6080f8bf51 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 15:38:02 +0200 Subject: Added SigPool::check(bit) --- passes/opt/opt_clean.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'passes') diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 76a905b2c..6c20bddbb 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -251,10 +251,10 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool for (int i = 0; i < SIZE(sig); i++) { if (sig[i].wire == NULL) continue; - if (!used_signals_nodrivers.check_any(sig[i])) { + if (!used_signals_nodrivers.check(sig[i])) { if (!unused_bits.empty()) unused_bits += " "; - unused_bits += stringf("%zd", i); + unused_bits += stringf("%d", i); } } if (unused_bits.empty() || wire->port_id != 0) -- cgit v1.2.3 From 5da343b7de8c4fd45695af68aaba3d5091d8e670 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 16:19:24 +0200 Subject: Added topological sorting to techmap --- passes/techmap/techmap.cc | 72 ++++++++++++++++++++++++++++++++++------------- 1 file changed, 52 insertions(+), 20 deletions(-) (limited to 'passes') diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index bcae44091..3595b7b53 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -20,6 +20,7 @@ #include "kernel/compatibility.h" #include "kernel/register.h" #include "kernel/sigtools.h" +#include "kernel/toposort.h" #include "kernel/log.h" #include #include @@ -221,25 +222,55 @@ struct TechmapWorker bool log_continue = false; bool did_something = false; - std::vector cell_names; SigMap sigmap(module); - for (auto &cell_it : module->cells_) - cell_names.push_back(cell_it.first); - for (auto &cell_name : cell_names) - { - if (module->cells_.count(cell_name) == 0) - continue; - - RTLIL::Cell *cell = module->cells_[cell_name]; + TopoSort cells; + std::map> cell_to_inbit; + std::map> outbit_to_cell; + for (auto cell : module->cells()) + { if (!design->selected(module, cell) || handled_cells.count(cell) > 0) continue; if (celltypeMap.count(cell->type) == 0) continue; + for (auto &conn : cell->connections()) + { + RTLIL::SigSpec sig = sigmap(conn.second); + sig.remove_const(); + + if (SIZE(sig) == 0) + continue; + + for (auto &tpl_name : celltypeMap.at(cell->type)) { + RTLIL::Module *tpl = map->modules_[tpl_name]; + RTLIL::Wire *port = tpl->wire(conn.first); + if (port && port->port_input) + cell_to_inbit[cell].insert(sig.begin(), sig.end()); + if (port && port->port_output) + for (auto &bit : sig) + outbit_to_cell[bit].insert(cell); + } + } + + cells.node(cell); + } + + for (auto &it_right : cell_to_inbit) + for (auto &it_sigbit : it_right.second) + for (auto &it_left : outbit_to_cell[it_sigbit]) + cells.edge(it_left, it_right.first); + + cells.sort(); + + for (auto cell : cells.sorted) + { + log_assert(handled_cells.count(cell) == 0); + log_assert(cell == module->cell(cell->name)); + for (auto &tpl_name : celltypeMap.at(cell->type)) { std::string derived_name = tpl_name; @@ -610,17 +641,18 @@ struct TechmapPass : public Pass { celltypeMap[it.first].insert(it.first); } - bool did_something = true; - std::set handled_cells; - while (did_something) { - did_something = false; - for (auto &mod_it : design->modules_) - if (worker.techmap_module(design, mod_it.second, map, handled_cells, celltypeMap, false)) - did_something = true; - if (did_something) - design->check(); - if (max_iter > 0 && --max_iter == 0) - break; + for (auto module : design->modules()) { + bool did_something = true; + std::set handled_cells; + while (did_something) { + did_something = false; + if (worker.techmap_module(design, module, map, handled_cells, celltypeMap, false)) + did_something = true; + if (did_something) + module->check(); + if (max_iter > 0 && --max_iter == 0) + break; + } } log("No more expansions possible.\n"); -- cgit v1.2.3 From 8b0f50792c404d70ae91e623f80c4e7f06d39429 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 21:13:23 +0200 Subject: Added techmap -extern --- passes/techmap/techmap.cc | 80 +++++++++++++++++++++++++++++++++++++---------- 1 file changed, 64 insertions(+), 16 deletions(-) (limited to 'passes') diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 3595b7b53..79e70a59c 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -58,6 +58,7 @@ struct TechmapWorker std::map simplemap_mappers; std::map>, RTLIL::Module*> techmap_cache; std::map techmap_do_cache; + std::set module_queue; struct TechmapWireData { RTLIL::Wire *wire; @@ -215,7 +216,7 @@ struct TechmapWorker } bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, std::set &handled_cells, - const std::map> &celltypeMap, bool flatten_mode) + const std::map> &celltypeMap, bool flatten_mode, bool extern_mode) { if (!design->selected(module)) return false; @@ -282,15 +283,24 @@ struct TechmapWorker if (!flatten_mode) { - if (tpl->get_bool_attribute("\\techmap_simplemap")) { - log("Mapping %s.%s (%s) with simplemap.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); - if (simplemap_mappers.count(cell->type) == 0) - log_error("No simplemap mapper for cell type %s found!\n", RTLIL::id2cstr(cell->type)); - simplemap_mappers.at(cell->type)(module, cell); - module->remove(cell); - cell = NULL; - did_something = true; - break; + if (tpl->get_bool_attribute("\\techmap_simplemap")) + { + if (extern_mode) + { + log("WARNING: Mapping simplat cell %s.%s (%s) in -extern mode is not supported yet.\n", log_id(module), log_id(cell), log_id(cell->type)); + break; + } + else + { + log("Mapping %s.%s (%s) with simplemap.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); + if (simplemap_mappers.count(cell->type) == 0) + log_error("No simplemap mapper for cell type %s found!\n", RTLIL::id2cstr(cell->type)); + simplemap_mappers.at(cell->type)(module, cell); + module->remove(cell); + cell = NULL; + did_something = true; + break; + } } for (auto conn : cell->connections()) { @@ -454,9 +464,33 @@ struct TechmapWorker log_continue = false; } - techmap_module_worker(design, module, cell, tpl, flatten_mode); + if (extern_mode) + { + std::string m_name = stringf("$extern:%s", log_id(tpl)); + + if (!design->module(m_name)) + { + RTLIL::Module *m = design->addModule(m_name); + tpl->cloneInto(m); + + for (auto cell : m->cells()) { + if (cell->type.substr(0, 2) == "\\$") + cell->type = cell->type.substr(1); + } + + module_queue.insert(m); + } + + log("Mapping %s.%s to imported %s.\n", log_id(module), log_id(cell), log_id(m_name)); + cell->type = m_name; + cell->parameters.clear(); + } + else + { + techmap_module_worker(design, module, cell, tpl, flatten_mode); + cell = NULL; + } did_something = true; - cell = NULL; break; } @@ -495,6 +529,10 @@ struct TechmapPass : public Pass { log(" yosys data files are). this is mainly used internally when techmap\n"); log(" is called from other commands.\n"); log("\n"); + log(" -extern\n"); + log(" load the cell implementations as separate modules into the design\n"); + log(" instead of inlining them.\n"); + log("\n"); log(" -max_iter \n"); log(" only run the specified number of iterations.\n"); log("\n"); @@ -576,6 +614,7 @@ struct TechmapPass : public Pass { std::vector map_files; std::string verilog_frontend = "verilog -ignore_redef"; + bool extern_mode = false; int max_iter = -1; size_t argidx; @@ -601,6 +640,10 @@ struct TechmapPass : public Pass { verilog_frontend += " -I " + args[++argidx]; continue; } + if (args[argidx] == "-extern") { + extern_mode = true; + continue; + } break; } extra_args(args, argidx, design); @@ -641,12 +684,17 @@ struct TechmapPass : public Pass { celltypeMap[it.first].insert(it.first); } - for (auto module : design->modules()) { + worker.module_queue = design->modules(); + while (!worker.module_queue.empty()) + { + RTLIL::Module *module = *worker.module_queue.begin(); + worker.module_queue.erase(module); + bool did_something = true; std::set handled_cells; while (did_something) { did_something = false; - if (worker.techmap_module(design, module, map, handled_cells, celltypeMap, false)) + if (worker.techmap_module(design, module, map, handled_cells, celltypeMap, false, extern_mode)) did_something = true; if (did_something) module->check(); @@ -699,11 +747,11 @@ struct FlattenPass : public Pass { while (did_something) { did_something = false; if (top_mod != NULL) { - if (worker.techmap_module(design, top_mod, design, handled_cells, celltypeMap, true)) + if (worker.techmap_module(design, top_mod, design, handled_cells, celltypeMap, true, false)) did_something = true; } else { for (auto mod : design->modules()) - if (worker.techmap_module(design, mod, design, handled_cells, celltypeMap, true)) + if (worker.techmap_module(design, mod, design, handled_cells, celltypeMap, true, false)) did_something = true; } } -- cgit v1.2.3 From 7bd2d1064f2eceddc3c93c121c4154a2f594a040 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 28 Jul 2014 11:08:55 +0200 Subject: Using log_assert() instead of assert() --- passes/abc/abc.cc | 9 ++++----- passes/cmds/scc.cc | 6 +++--- passes/cmds/select.cc | 2 +- passes/cmds/show.cc | 2 +- passes/fsm/fsm_expand.cc | 6 +++--- passes/fsm/fsm_extract.cc | 2 +- passes/hierarchy/hierarchy.cc | 4 ++-- passes/hierarchy/submod.cc | 2 +- passes/memory/memory_collect.cc | 23 +++++++++++------------ passes/memory/memory_dff.cc | 1 - passes/memory/memory_map.cc | 1 - passes/memory/memory_unpack.cc | 1 - passes/opt/opt_clean.cc | 3 +-- passes/opt/opt_const.cc | 3 +-- passes/opt/opt_muxtree.cc | 1 - passes/opt/opt_reduce.cc | 1 - passes/opt/opt_share.cc | 1 - passes/proc/proc_dff.cc | 3 +-- passes/proc/proc_init.cc | 2 +- passes/proc/proc_mux.cc | 13 ++++++------- passes/proc/proc_rmdead.cc | 1 - passes/sat/sat.cc | 2 +- passes/techmap/extract.cc | 3 +-- passes/techmap/simplemap.cc | 1 - passes/techmap/techmap.cc | 7 +++---- 25 files changed, 42 insertions(+), 58 deletions(-) (limited to 'passes') diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index 03fc9f937..d2be7dcf1 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -39,7 +39,6 @@ #include "kernel/log.h" #include #include -#include #include #include #include @@ -273,7 +272,7 @@ static void handle_loops() // log("Removing non-loop node %d from graph: %s\n", id, log_signal(signal_list[id].bit)); for (int id2 : edges[id]) { - assert(in_edges_count[id2] > 0); + log_assert(in_edges_count[id2] > 0); if (--in_edges_count[id2] == 0) workpool.insert(id2); } @@ -331,7 +330,7 @@ static void handle_loops() int id3 = map_signal(RTLIL::SigSpec(wire)); signal_list[id1].is_port = true; signal_list[id3].is_port = true; - assert(id3 == int(in_edges_count.size())); + log_assert(id3 == int(in_edges_count.size())); in_edges_count.push_back(0); workpool.insert(id3); @@ -778,7 +777,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std for (auto &c : conn.second.chunks()) { if (c.width == 0) continue; - assert(c.width == 1); + log_assert(c.width == 1); newsig.append(module->wires_[remap_name(c.wire->name)]); } cell->set(conn.first, newsig); @@ -831,7 +830,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std struct dirent **namelist; int n = scandir(tempdir_name, &namelist, 0, alphasort); - assert(n >= 0); + log_assert(n >= 0); for (int i = 0; i < n; i++) { if (strcmp(namelist[i]->d_name, ".") && strcmp(namelist[i]->d_name, "..")) { if (asprintf(&p, "%s/%s", tempdir_name, namelist[i]->d_name) < 0) log_abort(); diff --git a/passes/cmds/scc.cc b/passes/cmds/scc.cc index 1fa1b4c9c..8c039e3e9 100644 --- a/passes/cmds/scc.cc +++ b/passes/cmds/scc.cc @@ -51,7 +51,7 @@ struct SccWorker void run(RTLIL::Cell *cell, int depth, int maxDepth) { - assert(workQueue.count(cell) > 0); + log_assert(workQueue.count(cell) > 0); workQueue.erase(cell); cellLabels[cell] = std::pair(labelCounter, labelCounter); @@ -166,7 +166,7 @@ struct SccWorker while (workQueue.size() > 0) { RTLIL::Cell *cell = *workQueue.begin(); - assert(cellStack.size() == 0); + log_assert(cellStack.size() == 0); cellDepth.clear(); run(cell, 0, maxDepth); } @@ -290,7 +290,7 @@ struct SccPass : public Pass { } if (selectMode) { - assert(origSelectPos >= 0); + log_assert(origSelectPos >= 0); design->selection_stack[origSelectPos] = newSelection; design->selection_stack[origSelectPos].optimize(design); } diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index 85c52277c..bbfa396ba 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -1120,7 +1120,7 @@ struct SelectPass : public Pass { work_stack.pop_back(); } - assert(design->selection_stack.size() > 0); + log_assert(design->selection_stack.size() > 0); if (clear_mode) { design->selection_stack.back() = RTLIL::Selection(true); diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index 7ab1daf00..a2dd8051b 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -202,7 +202,7 @@ struct ShowWorker for (int i = int(sig.chunks().size())-1; i >= 0; i--) { const RTLIL::SigChunk &c = sig.chunks().at(i); net = gen_signode_simple(c, false); - assert(!net.empty()); + log_assert(!net.empty()); if (driver) { label_string += stringf(" %d:%d - %d:%d |", i, pos, pos-c.width+1, c.offset+c.width-1, c.offset); net_conn_map[net].in.insert(stringf("x%d:s%d", idx, i)); diff --git a/passes/fsm/fsm_expand.cc b/passes/fsm/fsm_expand.cc index f107366d6..2da4794eb 100644 --- a/passes/fsm/fsm_expand.cc +++ b/passes/fsm/fsm_expand.cc @@ -157,9 +157,9 @@ struct FsmExpand A.replace(input_sig, RTLIL::SigSpec(in_val)); B.replace(input_sig, RTLIL::SigSpec(in_val)); S.replace(input_sig, RTLIL::SigSpec(in_val)); - assert(A.is_fully_const()); - assert(B.is_fully_const()); - assert(S.is_fully_const()); + log_assert(A.is_fully_const()); + log_assert(B.is_fully_const()); + log_assert(S.is_fully_const()); truth_tab.push_back(ct.eval(cell, A.as_const(), B.as_const(), S.as_const())); } diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index 99352b10a..6da468321 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -109,7 +109,7 @@ static void find_transitions(ConstEval &ce, ConstEval &ce_nostop, FsmData &fsm_d RTLIL::SigSpec undef, constval; if (ce.eval(ctrl_out, undef) && ce.eval(dff_in, undef)) { - assert(ctrl_out.is_fully_const() && dff_in.is_fully_const()); + log_assert(ctrl_out.is_fully_const() && dff_in.is_fully_const()); FsmData::transition_t tr; tr.state_in = state_in; tr.state_out = states[ce.values_map(ce.assign_map(dff_in)).as_const()]; diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 8aec25eba..c869ec729 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -98,7 +98,7 @@ static void generate(RTLIL::Design *design, const std::vector &cell generate_port_decl_t d = decl; d.portname = portname; d.index = *indices.begin(); - assert(!indices.empty()); + log_assert(!indices.empty()); indices.erase(d.index); ports[d.index-1] = d; portwidths[d.portname] = std::max(portwidths[d.portname], 1); @@ -110,7 +110,7 @@ static void generate(RTLIL::Design *design, const std::vector &cell portnames.erase(portname); } - assert(indices.empty()); + log_assert(indices.empty()); RTLIL::Module *mod = new RTLIL::Module; mod->name = celltype; diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index d32b5e1d3..84c6b9161 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -171,7 +171,7 @@ struct SubmodWorker for (auto &conn : new_cell->connections_) for (auto &bit : conn.second) if (bit.wire != NULL) { - assert(wire_flags.count(bit.wire) > 0); + log_assert(wire_flags.count(bit.wire) > 0); bit.wire = wire_flags[bit.wire].new_wire; } log(" cell %s (%s)\n", new_cell->name.c_str(), new_cell->type.c_str()); diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc index d2803ae78..40c68abc1 100644 --- a/passes/memory/memory_collect.cc +++ b/passes/memory/memory_collect.cc @@ -22,7 +22,6 @@ #include #include #include -#include static bool memcells_cmp(RTLIL::Cell *a, RTLIL::Cell *b) { @@ -136,12 +135,12 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) mem->parameters["\\SIZE"] = RTLIL::Const(memory->size); mem->parameters["\\ABITS"] = RTLIL::Const(addr_bits); - assert(sig_wr_clk.size() == wr_ports); - assert(sig_wr_clk_enable.size() == wr_ports && sig_wr_clk_enable.is_fully_const()); - assert(sig_wr_clk_polarity.size() == wr_ports && sig_wr_clk_polarity.is_fully_const()); - assert(sig_wr_addr.size() == wr_ports * addr_bits); - assert(sig_wr_data.size() == wr_ports * memory->width); - assert(sig_wr_en.size() == wr_ports * memory->width); + log_assert(sig_wr_clk.size() == wr_ports); + log_assert(sig_wr_clk_enable.size() == wr_ports && sig_wr_clk_enable.is_fully_const()); + log_assert(sig_wr_clk_polarity.size() == wr_ports && sig_wr_clk_polarity.is_fully_const()); + log_assert(sig_wr_addr.size() == wr_ports * addr_bits); + log_assert(sig_wr_data.size() == wr_ports * memory->width); + log_assert(sig_wr_en.size() == wr_ports * memory->width); mem->parameters["\\WR_PORTS"] = RTLIL::Const(wr_ports); mem->parameters["\\WR_CLK_ENABLE"] = wr_ports ? sig_wr_clk_enable.as_const() : RTLIL::Const(0, 0); @@ -152,11 +151,11 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) mem->set("\\WR_DATA", sig_wr_data); mem->set("\\WR_EN", sig_wr_en); - assert(sig_rd_clk.size() == rd_ports); - assert(sig_rd_clk_enable.size() == rd_ports && sig_rd_clk_enable.is_fully_const()); - assert(sig_rd_clk_polarity.size() == rd_ports && sig_rd_clk_polarity.is_fully_const()); - assert(sig_rd_addr.size() == rd_ports * addr_bits); - assert(sig_rd_data.size() == rd_ports * memory->width); + log_assert(sig_rd_clk.size() == rd_ports); + log_assert(sig_rd_clk_enable.size() == rd_ports && sig_rd_clk_enable.is_fully_const()); + log_assert(sig_rd_clk_polarity.size() == rd_ports && sig_rd_clk_polarity.is_fully_const()); + log_assert(sig_rd_addr.size() == rd_ports * addr_bits); + log_assert(sig_rd_data.size() == rd_ports * memory->width); mem->parameters["\\RD_PORTS"] = RTLIL::Const(rd_ports); mem->parameters["\\RD_CLK_ENABLE"] = rd_ports ? sig_rd_clk_enable.as_const() : RTLIL::Const(0, 0); diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index 85249142e..325056170 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -20,7 +20,6 @@ #include "kernel/register.h" #include "kernel/log.h" #include -#include #include static void normalize_sig(RTLIL::Module *module, RTLIL::SigSpec &sig) diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index 53394b19a..49291656c 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -22,7 +22,6 @@ #include #include #include -#include static std::string genid(std::string name, std::string token1 = "", int i = -1, std::string token2 = "", int j = -1, std::string token3 = "", int k = -1, std::string token4 = "") { diff --git a/passes/memory/memory_unpack.cc b/passes/memory/memory_unpack.cc index d2b9c0eeb..cdf7db04b 100644 --- a/passes/memory/memory_unpack.cc +++ b/passes/memory/memory_unpack.cc @@ -22,7 +22,6 @@ #include #include #include -#include static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory) { diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 6c20bddbb..4182c6f5d 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -23,7 +23,6 @@ #include "kernel/log.h" #include "kernel/celltypes.h" #include -#include #include #include @@ -227,7 +226,7 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool if (!used_signals.check_any(s2) && wire->port_id == 0 && !wire->get_bool_attribute("\\keep")) { maybe_del_wires.push_back(wire); } else { - assert(SIZE(s1) == SIZE(s2)); + log_assert(SIZE(s1) == SIZE(s2)); RTLIL::SigSig new_conn; for (int i = 0; i < SIZE(s1); i++) if (s1[i] != s2[i]) { diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index 7578f1927..254fe5bb4 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -24,7 +24,6 @@ #include "kernel/toposort.h" #include "kernel/log.h" #include -#include #include #include @@ -495,7 +494,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo RTLIL::SigSpec new_a, new_b; - assert(SIZE(a) == SIZE(b)); + log_assert(SIZE(a) == SIZE(b)); for (int i = 0; i < SIZE(a); i++) { if (a[i].wire == NULL && b[i].wire == NULL && a[i] != b[i] && a[i].data <= RTLIL::State::S1 && b[i].data <= RTLIL::State::S1) { cover_list("opt.opt_const.eqneq.isneq", "$eq", "$ne", "$eqx", "$nex", cell->type); diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc index 73baaf900..de12542dc 100644 --- a/passes/opt/opt_muxtree.cc +++ b/passes/opt/opt_muxtree.cc @@ -23,7 +23,6 @@ #include "kernel/log.h" #include "kernel/celltypes.h" #include -#include #include #include diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc index b2b7cc8b9..8aadd1f23 100644 --- a/passes/opt/opt_reduce.cc +++ b/passes/opt/opt_reduce.cc @@ -24,7 +24,6 @@ #include "kernel/celltypes.h" #include "libs/sha1/sha1.h" #include -#include #include #include diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc index 45130229f..ad6e1a746 100644 --- a/passes/opt/opt_share.cc +++ b/passes/opt/opt_share.cc @@ -24,7 +24,6 @@ #include "kernel/celltypes.h" #include "libs/sha1/sha1.h" #include -#include #include #include diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index dc310bde0..91cafe3be 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -24,7 +24,6 @@ #include #include #include -#include static RTLIL::SigSpec find_any_lvalue(const RTLIL::Process *proc) { @@ -288,7 +287,7 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) inputs.append(it->signal); compare.append(it->type == RTLIL::SyncType::ST0 ? RTLIL::State::S1 : RTLIL::State::S0); } - assert(inputs.size() == compare.size()); + log_assert(inputs.size() == compare.size()); RTLIL::Cell *cell = mod->addCell(NEW_ID, "$ne"); cell->parameters["\\A_SIGNED"] = RTLIL::Const(false, 1); diff --git a/passes/proc/proc_init.cc b/passes/proc/proc_init.cc index 99498505f..c72840c02 100644 --- a/passes/proc/proc_init.cc +++ b/passes/proc/proc_init.cc @@ -25,7 +25,7 @@ static void proc_get_const(RTLIL::SigSpec &sig, RTLIL::CaseRule &rule) { - assert(rule.compare.size() == 0); + log_assert(rule.compare.size() == 0); while (1) { RTLIL::SigSpec tmp = sig; diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc index fb49182c2..e7661245e 100644 --- a/passes/proc/proc_mux.cc +++ b/passes/proc/proc_mux.cc @@ -23,7 +23,6 @@ #include #include #include -#include static RTLIL::SigSpec find_any_lvalue(const RTLIL::CaseRule *cs) { @@ -67,7 +66,7 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, RTLIL::SigSpec sig = signal; // get rid of don't-care bits - assert(sig.size() == comp.size()); + log_assert(sig.size() == comp.size()); for (int i = 0; i < comp.size(); i++) if (comp[i] == RTLIL::State::Sa) { sig.remove(i); @@ -125,7 +124,7 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector &compare, RTLIL::SigSpec when_signal, RTLIL::SigSpec else_signal, RTLIL::Cell *&last_mux_cell, RTLIL::SwitchRule *sw) { - assert(when_signal.size() == else_signal.size()); + log_assert(when_signal.size() == else_signal.size()); std::stringstream sstr; sstr << "$procmux$" << (RTLIL::autoidx++); @@ -138,7 +137,7 @@ static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw); if (ctrl_sig.size() == 0) return when_signal; - assert(ctrl_sig.size() == 1); + log_assert(ctrl_sig.size() == 1); // prepare multiplexer output signal RTLIL::Wire *result_wire = mod->addWire(sstr.str() + "_Y", when_signal.size()); @@ -159,11 +158,11 @@ static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, static void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector &compare, RTLIL::SigSpec when_signal, RTLIL::Cell *last_mux_cell, RTLIL::SwitchRule *sw) { - assert(last_mux_cell != NULL); - assert(when_signal.size() == last_mux_cell->get("\\A").size()); + log_assert(last_mux_cell != NULL); + log_assert(when_signal.size() == last_mux_cell->get("\\A").size()); RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw); - assert(ctrl_sig.size() == 1); + log_assert(ctrl_sig.size() == 1); last_mux_cell->type = "$pmux"; RTLIL::SigSpec new_s = last_mux_cell->get("\\S"); diff --git a/passes/proc/proc_rmdead.cc b/passes/proc/proc_rmdead.cc index 9e5f413a2..61844d5eb 100644 --- a/passes/proc/proc_rmdead.cc +++ b/passes/proc/proc_rmdead.cc @@ -23,7 +23,6 @@ #include #include #include -#include #include static void proc_rmdead(RTLIL::SwitchRule *sw, int &counter) diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index dce312065..430628e46 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -335,7 +335,7 @@ struct SatHelper int setup_proof(int timestep = -1) { - assert(prove.size() || prove_x.size() || prove_asserts); + log_assert(prove.size() || prove_x.size() || prove_asserts); RTLIL::SigSpec big_lhs, big_rhs; std::vector prove_bits; diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index 8587f53b0..9c5fa7f71 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -23,7 +23,6 @@ #include "libs/subcircuit/subcircuit.h" #include #include -#include #include #include @@ -100,7 +99,7 @@ namespace RTLIL::Cell *haystackCell = (RTLIL::Cell*) haystackUserData; if (!needleCell || !haystackCell) { - assert(!needleCell && !haystackCell); + log_assert(!needleCell && !haystackCell); return true; } diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc index b327ba832..5c3e4c68f 100644 --- a/passes/techmap/simplemap.cc +++ b/passes/techmap/simplemap.cc @@ -21,7 +21,6 @@ #include "kernel/sigtools.h" #include "kernel/log.h" #include -#include #include #include diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 79e70a59c..5a69baca5 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -23,7 +23,6 @@ #include "kernel/toposort.h" #include "kernel/log.h" #include -#include #include #include @@ -47,7 +46,7 @@ static void apply_prefix(std::string prefix, RTLIL::SigSpec &sig, RTLIL::Module if (chunk.wire != NULL) { std::string wire_name = chunk.wire->name; apply_prefix(prefix, wire_name); - assert(module->wires_.count(wire_name) > 0); + log_assert(module->wires_.count(wire_name) > 0); chunk.wire = module->wires_[wire_name]; } sig = chunks; @@ -167,7 +166,7 @@ struct TechmapWorker c.second.remove(c.first.size(), c.second.size() - c.first.size()); if (c.second.size() < c.first.size()) c.second.append(RTLIL::SigSpec(RTLIL::State::S0, c.first.size() - c.second.size())); - assert(c.first.size() == c.second.size()); + log_assert(c.first.size() == c.second.size()); if (flatten_mode) { // more conservative approach: // connect internal and external wires @@ -427,7 +426,7 @@ struct TechmapWorker const char *q = strrchr(p+1, '.'); q = q ? q : p+1; - assert(!strncmp(q, "_TECHMAP_DO_", 12)); + log_assert(!strncmp(q, "_TECHMAP_DO_", 12)); std::string new_name = data.wire->name.substr(0, q-p) + "_TECHMAP_DONE_" + data.wire->name.substr(q-p+12); while (tpl->wires_.count(new_name)) new_name += "_"; -- cgit v1.2.3 From 397b00252dc0c4af725614bd12fc299147ba8efa Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 29 Jul 2014 14:42:33 +0200 Subject: Added $shift and $shiftx cell types (needed for correct part select behavior) --- passes/memory/memory_share.cc | 2 ++ passes/opt/opt_const.cc | 16 +++++++++------- 2 files changed, 11 insertions(+), 7 deletions(-) (limited to 'passes') diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index e61661a20..b1629b7c4 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -695,6 +695,8 @@ struct MemoryShareWorker cone_ct.cell_types.erase("$shr"); cone_ct.cell_types.erase("$sshl"); cone_ct.cell_types.erase("$sshr"); + cone_ct.cell_types.erase("$shift"); + cone_ct.cell_types.erase("$shiftx"); modwalker.setup(design, module, &cone_ct); diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index 254fe5bb4..3e7487c39 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -338,7 +338,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo goto next_cell; } - if (cell->type == "$reduce_xor" || cell->type == "$reduce_xnor" || + if (cell->type == "$reduce_xor" || cell->type == "$reduce_xnor" || cell->type == "$shift" || cell->type == "$shiftx" || cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr" || cell->type == "$lt" || cell->type == "$le" || cell->type == "$ge" || cell->type == "$gt" || cell->type == "$neg" || cell->type == "$add" || cell->type == "$sub" || @@ -347,7 +347,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo RTLIL::SigSpec sig_a = assign_map(cell->get("\\A")); RTLIL::SigSpec sig_b = cell->has("\\B") ? assign_map(cell->get("\\B")) : RTLIL::SigSpec(); - if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr") + if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr" || cell->type == "$shift" || cell->type == "$shiftx") sig_a = RTLIL::SigSpec(); for (auto &bit : sig_a.to_sigbit_vector()) @@ -360,8 +360,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (0) { found_the_x_bit: - cover_list("opt.opt_const.xbit", "$reduce_xor", "$reduce_xnor", "$shl", "$shr", "$sshl", "$sshr", "$lt", "$le", "$ge", "$gt", - "$neg", "$add", "$sub", "$mul", "$div", "$mod", "$pow", cell->type); + cover_list("opt.opt_const.xbit", "$reduce_xor", "$reduce_xnor", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", + "$lt", "$le", "$ge", "$gt", "$neg", "$add", "$sub", "$mul", "$div", "$mod", "$pow", cell->type); if (cell->type == "$reduce_xor" || cell->type == "$reduce_xnor" || cell->type == "$lt" || cell->type == "$le" || cell->type == "$ge" || cell->type == "$gt") replace_cell(assign_map, module, cell, "x-bit in input", "\\Y", RTLIL::State::Sx); @@ -572,7 +572,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo identity_wrt_a = true; } - if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr") + if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr" || cell->type == "$shift" || cell->type == "$shiftx") { RTLIL::SigSpec b = assign_map(cell->get("\\B")); @@ -603,9 +603,9 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (identity_wrt_a || identity_wrt_b) { if (identity_wrt_a) - cover_list("opt.opt_const.identwrt.a", "$add", "$sub", "$or", "$xor", "$shl", "$shr", "$sshl", "$sshr", "$mul", "$div", cell->type); + cover_list("opt.opt_const.identwrt.a", "$add", "$sub", "$or", "$xor", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", "$mul", "$div", cell->type); if (identity_wrt_b) - cover_list("opt.opt_const.identwrt.b", "$add", "$sub", "$or", "$xor", "$shl", "$shr", "$sshl", "$sshr", "$mul", "$div", cell->type); + cover_list("opt.opt_const.identwrt.b", "$add", "$sub", "$or", "$xor", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", "$mul", "$div", cell->type); log("Replacing %s cell `%s' in module `%s' with identity for port %c.\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str(), identity_wrt_a ? 'A' : 'B'); @@ -792,6 +792,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo FOLD_2ARG_CELL(shr) FOLD_2ARG_CELL(sshl) FOLD_2ARG_CELL(sshr) + FOLD_2ARG_CELL(shift) + FOLD_2ARG_CELL(shiftx) FOLD_2ARG_CELL(lt) FOLD_2ARG_CELL(le) -- cgit v1.2.3 From 03c96f9ce7120adf1c9bab93485a3b4bf6493ae9 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 29 Jul 2014 16:06:27 +0200 Subject: Added "techmap -map %{design-name}" --- passes/techmap/extract.cc | 6 +++--- passes/techmap/techmap.cc | 23 ++++++++++++++++------- 2 files changed, 19 insertions(+), 10 deletions(-) (limited to 'passes') diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index 9c5fa7f71..19d323341 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -603,9 +603,9 @@ struct ExtractPass : public Pass { delete map; log_cmd_error("Can't saved design `%s'.\n", filename.c_str()+1); } - for (auto &it : saved_designs.at(filename.substr(1))->modules_) - if (!map->modules_.count(it.first)) - map->modules_[it.first] = it.second->clone(); + for (auto mod : saved_designs.at(filename.substr(1))->modules()) + if (!map->has(mod->name)) + map->add(mod->clone()); } else { diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 5a69baca5..0ae5220e0 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -656,13 +656,22 @@ struct TechmapPass : public Pass { Frontend::frontend_call(map, f, "", verilog_frontend); fclose(f); } else - for (auto &fn : map_files) { - FILE *f = fopen(fn.c_str(), "rt"); - if (f == NULL) - log_cmd_error("Can't open map file `%s'\n", fn.c_str()); - Frontend::frontend_call(map, f, fn, (fn.size() > 3 && fn.substr(fn.size()-3) == ".il") ? "ilang" : verilog_frontend); - fclose(f); - } + for (auto &fn : map_files) + if (fn.substr(0, 1) == "%") { + if (!saved_designs.count(fn.substr(1))) { + delete map; + log_cmd_error("Can't saved design `%s'.\n", fn.c_str()+1); + } + for (auto mod : saved_designs.at(fn.substr(1))->modules()) + if (!map->has(mod->name)) + map->add(mod->clone()); + } else { + FILE *f = fopen(fn.c_str(), "rt"); + if (f == NULL) + log_cmd_error("Can't open map file `%s'\n", fn.c_str()); + Frontend::frontend_call(map, f, fn, (fn.size() > 3 && fn.substr(fn.size()-3) == ".il") ? "ilang" : verilog_frontend); + fclose(f); + } std::map modules_new; for (auto &it : map->modules_) { -- cgit v1.2.3 From 77e2d39cd079ba98340f55f57e8a6462fb709442 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 29 Jul 2014 16:33:56 +0200 Subject: Allow "hierarchy -generate" for $__ cells --- passes/hierarchy/hierarchy.cc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index c869ec729..a1361c680 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -41,7 +41,9 @@ static void generate(RTLIL::Design *design, const std::vector &cell for (auto i2 : i1.second->cells_) { RTLIL::Cell *cell = i2.second; - if (cell->type[0] == '$' || design->modules_.count(cell->type) > 0) + if (design->has(cell->type)) + continue; + if (cell->type.substr(0, 1) == "$" && cell->type.substr(0, 3) != "$__") continue; for (auto &pattern : celltypes) if (!fnmatch(pattern.c_str(), RTLIL::unescape_id(cell->type).c_str(), FNM_NOESCAPE)) -- cgit v1.2.3 From e6df25bf740b259027541db3543a769ecfc92d4f Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 29 Jul 2014 21:12:50 +0200 Subject: Renamed "write_autotest" to "test_autotb" and moved to passes/tests/ --- passes/tests/Makefile.inc | 3 + passes/tests/test_autotb.cc | 335 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 338 insertions(+) create mode 100644 passes/tests/Makefile.inc create mode 100644 passes/tests/test_autotb.cc (limited to 'passes') diff --git a/passes/tests/Makefile.inc b/passes/tests/Makefile.inc new file mode 100644 index 000000000..6497f86e9 --- /dev/null +++ b/passes/tests/Makefile.inc @@ -0,0 +1,3 @@ + +OBJS += passes/tests/test_autotb.o + diff --git a/passes/tests/test_autotb.cc b/passes/tests/test_autotb.cc new file mode 100644 index 000000000..f121089b1 --- /dev/null +++ b/passes/tests/test_autotb.cc @@ -0,0 +1,335 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/register.h" +#include "kernel/log.h" +#include +#include + +#define NUM_ITER 1000 + +static std::string id(std::string internal_id) +{ + const char *str = internal_id.c_str(); + bool do_escape = false; + + if (*str == '\\') + str++; + + if ('0' <= *str && *str <= '9') + do_escape = true; + + for (int i = 0; str[i]; i++) { + if ('0' <= str[i] && str[i] <= '9') + continue; + if ('a' <= str[i] && str[i] <= 'z') + continue; + if ('A' <= str[i] && str[i] <= 'Z') + continue; + if (str[i] == '_') + continue; + do_escape = true; + break; + } + + if (do_escape) + return "\\" + std::string(str) + " "; + return std::string(str); +} + +static std::string idx(std::string str) +{ + if (str[0] == '\\') + return str.substr(1); + return str; +} + +static std::string idy(std::string str1, std::string str2 = std::string(), std::string str3 = std::string()) +{ + str1 = idx(str1); + if (!str2.empty()) + str1 += "_" + idx(str2); + if (!str3.empty()) + str1 += "_" + idx(str3); + return id(str1); +} + +static void autotest(FILE *f, RTLIL::Design *design) +{ + fprintf(f, "module testbench;\n\n"); + + fprintf(f, "integer i;\n\n"); + + fprintf(f, "reg [31:0] xorshift128_x = 123456789;\n"); + fprintf(f, "reg [31:0] xorshift128_y = 362436069;\n"); + fprintf(f, "reg [31:0] xorshift128_z = 521288629;\n"); + fprintf(f, "reg [31:0] xorshift128_w = 88675123;\n"); + fprintf(f, "reg [31:0] xorshift128_t;\n\n"); + fprintf(f, "task xorshift128;\n"); + fprintf(f, "begin\n"); + fprintf(f, "\txorshift128_t = xorshift128_x ^ (xorshift128_x << 11);\n"); + fprintf(f, "\txorshift128_x = xorshift128_y;\n"); + fprintf(f, "\txorshift128_y = xorshift128_z;\n"); + fprintf(f, "\txorshift128_z = xorshift128_w;\n"); + fprintf(f, "\txorshift128_w = xorshift128_w ^ (xorshift128_w >> 19) ^ xorshift128_t ^ (xorshift128_t >> 8);\n"); + fprintf(f, "end\n"); + fprintf(f, "endtask\n\n"); + + for (auto it = design->modules_.begin(); it != design->modules_.end(); it++) + { + std::map signal_in; + std::map signal_const; + std::map signal_clk; + std::map signal_out; + + RTLIL::Module *mod = it->second; + + if (mod->get_bool_attribute("\\gentb_skip")) + continue; + + int count_ports = 0; + log("Generating test bench for module `%s'.\n", it->first.c_str()); + for (auto it2 = mod->wires_.begin(); it2 != mod->wires_.end(); it2++) { + RTLIL::Wire *wire = it2->second; + if (wire->port_output) { + count_ports++; + signal_out[idy("sig", mod->name, wire->name)] = wire->width; + fprintf(f, "wire [%d:0] %s;\n", wire->width-1, idy("sig", mod->name, wire->name).c_str()); + } else if (wire->port_input) { + count_ports++; + bool is_clksignal = wire->get_bool_attribute("\\gentb_clock"); + for (auto it3 = mod->processes.begin(); it3 != mod->processes.end(); it3++) + for (auto it4 = it3->second->syncs.begin(); it4 != it3->second->syncs.end(); it4++) { + if ((*it4)->type == RTLIL::ST0 || (*it4)->type == RTLIL::ST1) + continue; + RTLIL::SigSpec &signal = (*it4)->signal; + for (auto &c : signal.chunks()) + if (c.wire == wire) + is_clksignal = true; + } + if (is_clksignal && wire->attributes.count("\\gentb_constant") == 0) { + signal_clk[idy("sig", mod->name, wire->name)] = wire->width; + } else { + signal_in[idy("sig", mod->name, wire->name)] = wire->width; + if (wire->attributes.count("\\gentb_constant") != 0) + signal_const[idy("sig", mod->name, wire->name)] = wire->attributes["\\gentb_constant"].as_string(); + } + fprintf(f, "reg [%d:0] %s;\n", wire->width-1, idy("sig", mod->name, wire->name).c_str()); + } + } + fprintf(f, "%s %s(\n", id(mod->name).c_str(), idy("uut", mod->name).c_str()); + for (auto it2 = mod->wires_.begin(); it2 != mod->wires_.end(); it2++) { + RTLIL::Wire *wire = it2->second; + if (wire->port_output || wire->port_input) + fprintf(f, "\t.%s(%s)%s\n", id(wire->name).c_str(), + idy("sig", mod->name, wire->name).c_str(), --count_ports ? "," : ""); + } + fprintf(f, ");\n\n"); + + fprintf(f, "task %s;\n", idy(mod->name, "reset").c_str()); + fprintf(f, "begin\n"); + int delay_counter = 0; + for (auto it = signal_in.begin(); it != signal_in.end(); it++) + fprintf(f, "\t%s <= #%d 0;\n", it->first.c_str(), ++delay_counter*2); + for (auto it = signal_clk.begin(); it != signal_clk.end(); it++) + fprintf(f, "\t%s <= #%d 0;\n", it->first.c_str(), ++delay_counter*2); + for (auto it = signal_clk.begin(); it != signal_clk.end(); it++) { + fprintf(f, "\t#100; %s <= 1;\n", it->first.c_str()); + fprintf(f, "\t#100; %s <= 0;\n", it->first.c_str()); + } + delay_counter = 0; + for (auto it = signal_in.begin(); it != signal_in.end(); it++) + fprintf(f, "\t%s <= #%d ~0;\n", it->first.c_str(), ++delay_counter*2); + for (auto it = signal_clk.begin(); it != signal_clk.end(); it++) { + fprintf(f, "\t#100; %s <= 1;\n", it->first.c_str()); + fprintf(f, "\t#100; %s <= 0;\n", it->first.c_str()); + } + delay_counter = 0; + for (auto it = signal_in.begin(); it != signal_in.end(); it++) { + if (signal_const.count(it->first) == 0) + continue; + fprintf(f, "\t%s <= #%d 'b%s;\n", it->first.c_str(), ++delay_counter*2, signal_const[it->first].c_str()); + } + fprintf(f, "end\n"); + fprintf(f, "endtask\n\n"); + + fprintf(f, "task %s;\n", idy(mod->name, "update_data").c_str()); + fprintf(f, "begin\n"); + delay_counter = 0; + for (auto it = signal_in.begin(); it != signal_in.end(); it++) { + if (signal_const.count(it->first) > 0) + continue; + fprintf(f, "\txorshift128;\n"); + fprintf(f, "\t%s <= #%d { xorshift128_x, xorshift128_y, xorshift128_z, xorshift128_w };\n", it->first.c_str(), ++delay_counter*2); + } + fprintf(f, "end\n"); + fprintf(f, "endtask\n\n"); + + fprintf(f, "task %s;\n", idy(mod->name, "update_clock").c_str()); + fprintf(f, "begin\n"); + if (signal_clk.size()) { + fprintf(f, "\txorshift128;\n"); + fprintf(f, "\t{"); + int total_clock_bits = 0; + for (auto it = signal_clk.begin(); it != signal_clk.end(); it++) { + fprintf(f, "%s %s", it == signal_clk.begin() ? "" : ",", it->first.c_str()); + total_clock_bits += it->second; + } + fprintf(f, " } = {"); + for (auto it = signal_clk.begin(); it != signal_clk.end(); it++) + fprintf(f, "%s %s", it == signal_clk.begin() ? "" : ",", it->first.c_str()); + fprintf(f, " } ^ (%d'b1 << (xorshift128_w %% %d));\n", total_clock_bits, total_clock_bits); + } + fprintf(f, "end\n"); + fprintf(f, "endtask\n\n"); + + char shorthand = 'A'; + std::vector header1; + std::string header2 = ""; + + fprintf(f, "task %s;\n", idy(mod->name, "print_status").c_str()); + fprintf(f, "begin\n"); + fprintf(f, "\t$display(\"#OUT# %%b %%b %%b %%t %%d\", {"); + if (signal_in.size()) + for (auto it = signal_in.begin(); it != signal_in.end(); it++) { + fprintf(f, "%s %s", it == signal_in.begin() ? "" : ",", it->first.c_str()); + int len = it->second; + if (len > 1) + header2 += "/", len--; + while (len > 1) + header2 += "-", len--; + if (len > 0) + header2 += shorthand, len--; + header1.push_back(" " + it->first); + header1.back()[0] = shorthand++; + } + else { + fprintf(f, " 1'bx"); + header2 += "#"; + } + fprintf(f, " }, {"); + header2 += " "; + if (signal_clk.size()) { + for (auto it = signal_clk.begin(); it != signal_clk.end(); it++) { + fprintf(f, "%s %s", it == signal_clk.begin() ? "" : ",", it->first.c_str()); + int len = it->second; + if (len > 1) + header2 += "/", len--; + while (len > 1) + header2 += "-", len--; + if (len > 0) + header2 += shorthand, len--; + header1.push_back(" " + it->first); + header1.back()[0] = shorthand++; + } + } else { + fprintf(f, " 1'bx"); + header2 += "#"; + } + fprintf(f, " }, {"); + header2 += " "; + if (signal_out.size()) { + for (auto it = signal_out.begin(); it != signal_out.end(); it++) { + fprintf(f, "%s %s", it == signal_out.begin() ? "" : ",", it->first.c_str()); + int len = it->second; + if (len > 1) + header2 += "/", len--; + while (len > 1) + header2 += "-", len--; + if (len > 0) + header2 += shorthand, len--; + header1.push_back(" " + it->first); + header1.back()[0] = shorthand++; + } + } else { + fprintf(f, " 1'bx"); + header2 += "#"; + } + fprintf(f, " }, $time, i);\n"); + fprintf(f, "end\n"); + fprintf(f, "endtask\n\n"); + + fprintf(f, "task %s;\n", idy(mod->name, "print_header").c_str()); + fprintf(f, "begin\n"); + fprintf(f, "\t$display(\"#OUT#\");\n"); + for (auto &hdr : header1) + fprintf(f, "\t$display(\"#OUT# %s\");\n", hdr.c_str()); + fprintf(f, "\t$display(\"#OUT#\");\n"); + fprintf(f, "\t$display(\"#OUT# %s\");\n", header2.c_str()); + fprintf(f, "end\n"); + fprintf(f, "endtask\n\n"); + + fprintf(f, "task %s;\n", idy(mod->name, "test").c_str()); + fprintf(f, "begin\n"); + fprintf(f, "\t$display(\"#OUT#\\n#OUT# ==== %s ====\");\n", idy(mod->name).c_str()); + fprintf(f, "\t%s;\n", idy(mod->name, "reset").c_str()); + fprintf(f, "\tfor (i=0; i<%d; i=i+1) begin\n", NUM_ITER); + fprintf(f, "\t\tif (i %% 20 == 0) %s;\n", idy(mod->name, "print_header").c_str()); + fprintf(f, "\t\t#100; %s;\n", idy(mod->name, "update_data").c_str()); + fprintf(f, "\t\t#100; %s;\n", idy(mod->name, "update_clock").c_str()); + fprintf(f, "\t\t#100; %s;\n", idy(mod->name, "print_status").c_str()); + fprintf(f, "\tend\n"); + fprintf(f, "end\n"); + fprintf(f, "endtask\n\n"); + } + + fprintf(f, "initial begin\n"); + fprintf(f, "\t// $dumpfile(\"testbench.vcd\");\n"); + fprintf(f, "\t// $dumpvars(0, testbench);\n"); + for (auto it = design->modules_.begin(); it != design->modules_.end(); it++) + if (!it->second->get_bool_attribute("\\gentb_skip")) + fprintf(f, "\t%s;\n", idy(it->first, "test").c_str()); + fprintf(f, "\t$finish;\n"); + fprintf(f, "end\n\n"); + + fprintf(f, "endmodule\n"); +} + +struct TestAutotbBackend : public Backend { + TestAutotbBackend() : Backend("=test_autotb", "generate simple test benches") { } + virtual void help() + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" test_autotb [filename]\n"); + log("\n"); + log("Automatically create primitive verilog test benches for all modules in the\n"); + log("design. The generated testbenches toggle the input pins of the module in\n"); + log("a semi-random manner and dumps the resulting output signals.\n"); + log("\n"); + log("This can be used to check the synthesis results for simple circuits by\n"); + log("comparing the testbench output for the input files and the synthesis results.\n"); + log("\n"); + log("The backend automatically detects clock signals. Additionally a signal can\n"); + log("be forced to be interpreted as clock signal by setting the attribute\n"); + log("'gentb_clock' on the signal.\n"); + log("\n"); + log("The attribute 'gentb_constant' can be used to force a signal to a constant\n"); + log("value after initialization. This can e.g. be used to force a reset signal\n"); + log("low in order to explore more inner states in a state machine.\n"); + log("\n"); + } + virtual void execute(FILE *&f, std::string filename, std::vector args, RTLIL::Design *design) + { + log_header("Executing TEST_AUTOTB backend (auto-generate pseudo-random test benches).\n"); + extra_args(f, filename, args, 1); + autotest(f, design); + } +} TestAutotbBackend; + -- cgit v1.2.3 From 273383692a50490f02a51d0c44ba63b9f557da4e Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 29 Jul 2014 22:05:00 +0200 Subject: Added "test_cell" command --- passes/tests/Makefile.inc | 1 + passes/tests/test_cell.cc | 184 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 185 insertions(+) create mode 100644 passes/tests/test_cell.cc (limited to 'passes') diff --git a/passes/tests/Makefile.inc b/passes/tests/Makefile.inc index 6497f86e9..a60cfe66a 100644 --- a/passes/tests/Makefile.inc +++ b/passes/tests/Makefile.inc @@ -1,3 +1,4 @@ OBJS += passes/tests/test_autotb.o +OBJS += passes/tests/test_cell.o diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc new file mode 100644 index 000000000..41671a8e6 --- /dev/null +++ b/passes/tests/test_cell.cc @@ -0,0 +1,184 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2014 Clifford Wolf + * Copyright (C) 2014 Johann Glaser + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/register.h" +#include "kernel/rtlil.h" +#include "kernel/log.h" + +static uint32_t xorshift32(uint32_t limit) { + static uint32_t x = 123456789; + x ^= x << 13; + x ^= x >> 17; + x ^= x << 5; + return x % limit; +} + +static void create_gold_module(RTLIL::Design *design, std::string cell_type, std::string cell_type_flags) +{ + RTLIL::Module *module = design->addModule("\\gold"); + RTLIL::Cell *cell = module->addCell("\\UUT", cell_type); + + if (cell_type_flags.find('A') != std::string::npos) { + RTLIL::Wire *wire = module->addWire("\\A"); + wire->width = 1 + xorshift32(8); + wire->port_input = true; + cell->set("\\A", wire); + } + + if (cell_type_flags.find('B') != std::string::npos) { + RTLIL::Wire *wire = module->addWire("\\B"); + if (cell_type_flags.find('h') != std::string::npos) + wire->width = 1 + xorshift32(6); + else + wire->width = 1 + xorshift32(8); + wire->port_input = true; + cell->set("\\B", wire); + } + + if (cell_type_flags.find('S') != std::string::npos && xorshift32(2)) { + if (cell_type_flags.find('A') != std::string::npos) + cell->parameters["\\A_SIGNED"] = true; + if (cell_type_flags.find('B') != std::string::npos) + cell->parameters["\\B_SIGNED"] = true; + } + + if (cell_type_flags.find('s') != std::string::npos) { + if (cell_type_flags.find('A') != std::string::npos && xorshift32(2)) + cell->parameters["\\A_SIGNED"] = true; + if (cell_type_flags.find('B') != std::string::npos && xorshift32(2)) + cell->parameters["\\B_SIGNED"] = true; + } + + if (cell_type_flags.find('Y') != std::string::npos) { + RTLIL::Wire *wire = module->addWire("\\Y"); + wire->width = 1 + xorshift32(8); + wire->port_output = true; + cell->set("\\Y", wire); + } + + module->fixup_ports(); + cell->fixup_parameters(); + cell->check(); +} + +struct TestCellPass : public Pass { + TestCellPass() : Pass("test_cell", "automatically test the implementation of a cell type") { } + virtual void help() + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" test_cell {cell-type}\n"); + log("\n"); + log("Tests the internal implementation of the given cell type (for example '$mux')\n"); + log("by comparing SAT solver, EVAL and TECHMAP implementations of the cell type..\n"); + log("\n"); + log("Run with '-all' instead of a cell type to run the test on all supported\n"); + log("cell types.\n"); + log("\n"); + } + virtual void execute(std::vector args, RTLIL::Design *current_design) + { + if (SIZE(args) != 2) + log_cmd_error("Expecting exactly one argument.\n"); + + std::map cell_types; + cell_types["$not"] = "ASY"; + cell_types["$pos"] = "ASY"; + cell_types["$bu0"] = "ASY"; + cell_types["$neg"] = "ASY"; + + cell_types["$and"] = "ABSY"; + cell_types["$or"] = "ABSY"; + cell_types["$xor"] = "ABSY"; + cell_types["$xnor"] = "ABSY"; + + cell_types["$reduce_and"] = "ASY"; + cell_types["$reduce_or"] = "ASY"; + cell_types["$reduce_xor"] = "ASY"; + cell_types["$reduce_xnor"] = "ASY"; + cell_types["$reduce_bool"] = "ASY"; + + cell_types["$shl"] = "ABshY"; + cell_types["$shr"] = "ABshY"; + cell_types["$sshl"] = "ABshY"; + cell_types["$sshr"] = "ABshY"; + // cell_types["$shift"] = "ABshY"; <-- FIXME + // cell_types["$shiftx"] = "ABshY"; + + cell_types["$lt"] = "ABSY"; + cell_types["$le"] = "ABSY"; + cell_types["$eq"] = "ABSY"; + cell_types["$ne"] = "ABSY"; + // cell_types["$eqx"] = "ABSY"; + // cell_types["$nex"] = "ABSY"; + cell_types["$ge"] = "ABSY"; + cell_types["$gt"] = "ABSY"; + + cell_types["$add"] = "ABSY"; + cell_types["$sub"] = "ABSY"; + cell_types["$mul"] = "ABSY"; + cell_types["$div"] = "ABSY"; + cell_types["$mod"] = "ABSY"; + // cell_types["$pow"] = "ABsY"; + + cell_types["$logic_not"] = "ASY"; + cell_types["$logic_and"] = "ABSY"; + cell_types["$logic_or"] = "ABSY"; + + // cell_types["$mux"] = "A"; + // cell_types["$pmux"] = "A"; + // cell_types["$slice"] = "A"; + // cell_types["$concat"] = "A"; + // cell_types["$safe_pmux"] = "A"; + // cell_types["$lut"] = "A"; + // cell_types["$assert"] = "A"; + + if (args[1] == "-all") { + for (auto &it : cell_types) + Pass::call(current_design, "test_cell " + it.first); + return; + } + + if (cell_types.count(args[1]) == 0) { + std::string cell_type_list; + int charcount = 100; + for (auto &it : cell_types) { + if (charcount > 60) { + cell_type_list += "\n" + it.first; + charcount = 0; + } else + cell_type_list += " " + it.first; + charcount += SIZE(it.first); + } + log_cmd_error("This cell type is currently not supported. Try one of these:%s\n", cell_type_list.c_str()); + } + + for (int i = 0; i < 100; i++) + { + RTLIL::Design *design = new RTLIL::Design; + create_gold_module(design, args[1], cell_types.at(args[1])); + Pass::call(design, "copy gold gate; techmap gate; opt gate; dump gold"); + Pass::call(design, "miter -equiv -flatten -ignore_gold_x gold gate miter"); + Pass::call(design, "sat -verify -enable_undef -prove trigger 0 miter"); + delete design; + } + } +} TestCellPass; + -- cgit v1.2.3 From ceecf5b1535cf2e567c144bdbe143c8ba66c69d7 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 30 Jul 2014 15:59:38 +0200 Subject: Improvements in test_cell --- passes/tests/test_cell.cc | 124 +++++++++++++++++++++++++++++++++------------- 1 file changed, 89 insertions(+), 35 deletions(-) (limited to 'passes') diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index 41671a8e6..d504cea94 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -18,9 +18,8 @@ * */ -#include "kernel/register.h" -#include "kernel/rtlil.h" -#include "kernel/log.h" +#include "kernel/yosys.h" +#include static uint32_t xorshift32(uint32_t limit) { static uint32_t x = 123456789; @@ -84,21 +83,52 @@ struct TestCellPass : public Pass { { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); - log(" test_cell {cell-type}\n"); + log(" test_cell [options] {cell-types}\n"); log("\n"); log("Tests the internal implementation of the given cell type (for example '$mux')\n"); - log("by comparing SAT solver, EVAL and TECHMAP implementations of the cell type..\n"); + log("by comparing SAT solver, EVAL and TECHMAP implementations of the cell types..\n"); log("\n"); - log("Run with '-all' instead of a cell type to run the test on all supported\n"); + log("Run with 'all' instead of a cell type to run the test on all supported\n"); log("cell types.\n"); log("\n"); + log(" -n {integer}\n"); + log(" create this number of cell instances and test them (default = 100).\n"); + log("\n"); + log(" -f {ilang_file}\n"); + log(" don't generate circuits. instead load the specified ilang file.\n"); + log("\n"); + log(" -map {filename}\n"); + log(" pass this option to techmap.\n"); + log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *current_design) + virtual void execute(std::vector args, RTLIL::Design*) { - if (SIZE(args) != 2) - log_cmd_error("Expecting exactly one argument.\n"); + int num_iter = 100; + std::string techmap_cmd = "techmap"; + std::string ilang_file; + + int argidx; + for (argidx = 1; argidx < SIZE(args); argidx++) + { + if (args[argidx] == "-n" && argidx+1 < SIZE(args)) { + num_iter = atoi(args[++argidx].c_str()); + continue; + } + if (args[argidx] == "-map" && argidx+1 < SIZE(args)) { + techmap_cmd += " -map " + args[++argidx]; + continue; + } + if (args[argidx] == "-f" && argidx+1 < SIZE(args)) { + ilang_file = args[++argidx]; + num_iter = 1; + continue; + } + break; + } std::map cell_types; + std::vector selected_cell_types; + cell_types["$not"] = "ASY"; cell_types["$pos"] = "ASY"; cell_types["$bu0"] = "ASY"; @@ -119,8 +149,8 @@ struct TestCellPass : public Pass { cell_types["$shr"] = "ABshY"; cell_types["$sshl"] = "ABshY"; cell_types["$sshr"] = "ABshY"; - // cell_types["$shift"] = "ABshY"; <-- FIXME - // cell_types["$shiftx"] = "ABshY"; + cell_types["$shift"] = "ABshY"; + cell_types["$shiftx"] = "ABshY"; cell_types["$lt"] = "ABSY"; cell_types["$le"] = "ABSY"; @@ -150,35 +180,59 @@ struct TestCellPass : public Pass { // cell_types["$lut"] = "A"; // cell_types["$assert"] = "A"; - if (args[1] == "-all") { - for (auto &it : cell_types) - Pass::call(current_design, "test_cell " + it.first); - return; - } + for (; argidx < SIZE(args); argidx++) + { + if (args[argidx].rfind("-", 0) == 0) + log_cmd_error("Unexpected option: %s\n", args[argidx].c_str()); + + if (args[argidx] == "all") { + for (auto &it : cell_types) + if (std::count(selected_cell_types.begin(), selected_cell_types.end(), it.first) == 0) + selected_cell_types.push_back(it.first); + continue; + } - if (cell_types.count(args[1]) == 0) { - std::string cell_type_list; - int charcount = 100; - for (auto &it : cell_types) { - if (charcount > 60) { - cell_type_list += "\n" + it.first; - charcount = 0; - } else - cell_type_list += " " + it.first; - charcount += SIZE(it.first); + if (cell_types.count(args[argidx]) == 0) { + std::string cell_type_list; + int charcount = 100; + for (auto &it : cell_types) { + if (charcount > 60) { + cell_type_list += "\n" + it.first; + charcount = 0; + } else + cell_type_list += " " + it.first; + charcount += SIZE(it.first); + } + log_cmd_error("The cell type `%s' is currently not supported. Try one of these:%s\n", + args[argidx].c_str(), cell_type_list.c_str()); } - log_cmd_error("This cell type is currently not supported. Try one of these:%s\n", cell_type_list.c_str()); + + if (std::count(selected_cell_types.begin(), selected_cell_types.end(), args[argidx]) == 0) + selected_cell_types.push_back(args[argidx]); } - for (int i = 0; i < 100; i++) - { - RTLIL::Design *design = new RTLIL::Design; - create_gold_module(design, args[1], cell_types.at(args[1])); - Pass::call(design, "copy gold gate; techmap gate; opt gate; dump gold"); - Pass::call(design, "miter -equiv -flatten -ignore_gold_x gold gate miter"); - Pass::call(design, "sat -verify -enable_undef -prove trigger 0 miter"); - delete design; + if (!ilang_file.empty()) { + if (!selected_cell_types.empty()) + log_cmd_error("Do not specify any cell types when using -f.\n"); + selected_cell_types.push_back("ilang"); } + + if (selected_cell_types.empty()) + log_cmd_error("No cell type to test specified.\n"); + + for (auto cell_type : selected_cell_types) + for (int i = 0; i < num_iter; i++) + { + RTLIL::Design *design = new RTLIL::Design; + if (cell_type == "ilang") + Frontend::frontend_call(design, NULL, std::string(), "ilang " + ilang_file); + else + create_gold_module(design, cell_type, cell_types.at(cell_type)); + Pass::call(design, stringf("copy gold gate; %s gate; opt gate", techmap_cmd.c_str())); + Pass::call(design, "miter -equiv -flatten -make_outputs -ignore_gold_x gold gate miter; dump gold"); + Pass::call(design, "sat -verify -enable_undef -prove trigger 0 -show-inputs -show-outputs miter"); + delete design; + } } } TestCellPass; -- cgit v1.2.3 From 6400ae36489a7ada5419d7bc502934f6d05e69bb Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 30 Jul 2014 19:59:29 +0200 Subject: Added write_file command --- passes/cmds/Makefile.inc | 1 + passes/cmds/write_file.cc | 76 +++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 77 insertions(+) create mode 100644 passes/cmds/write_file.cc (limited to 'passes') diff --git a/passes/cmds/Makefile.inc b/passes/cmds/Makefile.inc index 6ae4495a8..26c0ef8a9 100644 --- a/passes/cmds/Makefile.inc +++ b/passes/cmds/Makefile.inc @@ -16,6 +16,7 @@ OBJS += passes/cmds/splice.o OBJS += passes/cmds/scc.o OBJS += passes/cmds/log.o OBJS += passes/cmds/tee.o +OBJS += passes/cmds/write_file.o OBJS += passes/cmds/connwrappers.o OBJS += passes/cmds/cover.o diff --git a/passes/cmds/write_file.cc b/passes/cmds/write_file.cc new file mode 100644 index 000000000..a7cd7b438 --- /dev/null +++ b/passes/cmds/write_file.cc @@ -0,0 +1,76 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2014 Clifford Wolf + * Copyright (C) 2014 Johann Glaser + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" + +struct WriteFileFrontend : public Frontend { + WriteFileFrontend() : Frontend("=write_file", "write a text to a file") { } + virtual void help() + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" write_file [options] output_file [input_file]\n"); + log("\n"); + log("Write the text fron the input file to the output file.\n"); + log("\n"); + log(" -a\n"); + log(" Append to output file (instead of overwriting)\n"); + log("\n"); + log("\n"); + log("Inside a script the input file can also can a here-document:\n"); + log("\n"); + log(" write_file hello.txt < args, RTLIL::Design*) + { + bool append_mode = false; + std::string output_filename; + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) + { + if (args[argidx] == "-a") { + append_mode = true; + continue; + } + break; + } + + if (argidx < args.size() && args[argidx].rfind("-", 0) != 0) + output_filename = args[argidx++]; + else + log_cmd_error("Missing putput filename.\n"); + + extra_args(f, filename, args, argidx); + + FILE *of = fopen(output_filename.c_str(), append_mode ? "a" : "w"); + char buffer[64 * 1024]; + size_t bytes; + + while (0 < (bytes = fread(buffer, 1, sizeof(buffer), f))) + fwrite(buffer, bytes, 1, of); + + fclose(of); + } +} WriteFileFrontend; + -- cgit v1.2.3 From 254148910556d057ec296e4f8c44e92bdb8c09a3 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 30 Jul 2014 22:04:30 +0200 Subject: Added techmap CONSTMAP feature --- passes/techmap/techmap.cc | 129 ++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 119 insertions(+), 10 deletions(-) (limited to 'passes') diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 0ae5220e0..75b9dee9b 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -17,11 +17,11 @@ * */ -#include "kernel/compatibility.h" -#include "kernel/register.h" -#include "kernel/sigtools.h" +#include "kernel/yosys.h" #include "kernel/toposort.h" -#include "kernel/log.h" +#include "kernel/sigtools.h" +#include "libs/sha1/sha1.h" + #include #include #include @@ -66,6 +66,36 @@ struct TechmapWorker typedef std::map> TechmapWires; + std::string constmap_tpl_name(SigMap &sigmap, RTLIL::Module *tpl, RTLIL::Cell *cell, bool verbose) + { + std::string constmap_info; + std::map> connbits_map; + + for (auto conn : cell->connections()) + for (int i = 0; i < SIZE(conn.second); i++) { + RTLIL::SigBit bit = sigmap(conn.second[i]); + if (bit.wire == nullptr) { + if (verbose) + log(" Constant input on bit %d of port %s: %s\n", i, log_id(conn.first), log_signal(bit)); + constmap_info += stringf("|%s %d %d", log_id(conn.first), i, bit.data); + } else if (connbits_map.count(bit)) { + if (verbose) + log(" Bit %d of port %s and bit %d of port %s are connected.\n", i, log_id(conn.first), + connbits_map.at(bit).second, log_id(connbits_map.at(bit).first)); + constmap_info += stringf("|%s %d %s %d", log_id(conn.first), i, + log_id(connbits_map.at(bit).first), connbits_map.at(bit).second); + } else + connbits_map[bit] = std::pair(conn.first, i);stringf("%s %d", log_id(conn.first), i, bit.data); + } + + unsigned char hash[20]; + char hash_hex_string[41]; + sha1::calc(constmap_info.c_str(), constmap_info.size(), hash); + sha1::toHexString(hash, hash_hex_string); + + return stringf("$paramod$constmap$%s%s", hash_hex_string, tpl->name.c_str()); + } + TechmapWires techmap_find_special_wires(RTLIL::Module *module) { TechmapWires result; @@ -374,14 +404,19 @@ struct TechmapWorker } else { if (cell->parameters.size() != 0) { derived_name = tpl->derive(map, parameters); - tpl = map->modules_[derived_name]; + tpl = map->module(derived_name); log_continue = true; } techmap_cache[key] = tpl; } - if (flatten_mode) + if (flatten_mode) { techmap_do_cache[tpl] = true; + } else { + RTLIL::Module *constmapped_tpl = map->module(constmap_tpl_name(sigmap, tpl, cell, false)); + if (constmapped_tpl != nullptr) + tpl = constmapped_tpl; + } if (techmap_do_cache.count(tpl) == 0) { @@ -426,14 +461,80 @@ struct TechmapWorker const char *q = strrchr(p+1, '.'); q = q ? q : p+1; + std::string cmd_string = data.value.as_const().decode_string(); + + if (cmd_string.rfind("CONSTMAP; ", 0) == 0) + { + cmd_string = cmd_string.substr(strlen("CONSTMAP; ")); + + log("Analyzing pattern of constant bits for this cell:\n"); + std::string new_tpl_name = constmap_tpl_name(sigmap, tpl, cell, true); + log("Creating constmapped module `%s'.\n", log_id(new_tpl_name)); + log_assert(map->module(new_tpl_name) == nullptr); + + RTLIL::Module *new_tpl = map->addModule(new_tpl_name); + tpl->cloneInto(new_tpl); + + techmap_do_cache.erase(tpl); + techmap_do_cache[new_tpl] = true; + tpl = new_tpl; + + std::map port_new2old_map; + std::map port_connmap; + std::map cellbits_to_tplbits; + + for (auto wire : tpl->wires().to_vector()) + { + if (!wire->port_input || wire->port_output) + continue; + + std::string port_name = wire->name; + tpl->rename(wire, NEW_ID); + + RTLIL::Wire *new_wire = tpl->addWire(port_name, wire); + wire->port_input = false; + + for (int i = 0; i < wire->width; i++) { + port_new2old_map[RTLIL::SigBit(new_wire, i)] = RTLIL::SigBit(wire, i); + port_connmap[RTLIL::SigBit(wire, i)] = RTLIL::SigBit(new_wire, i); + } + } + + for (auto conn : cell->connections()) + for (int i = 0; i < SIZE(conn.second); i++) + { + RTLIL::SigBit bit = sigmap(conn.second[i]); + RTLIL::SigBit tplbit(tpl->wire(conn.first), i); + + if (bit.wire == nullptr) + { + RTLIL::SigBit oldbit = port_new2old_map.at(tplbit); + port_connmap.at(oldbit) = bit; + } + else if (cellbits_to_tplbits.count(bit)) + { + RTLIL::SigBit oldbit = port_new2old_map.at(tplbit); + port_connmap.at(oldbit) = cellbits_to_tplbits[bit]; + } + else + cellbits_to_tplbits[bit] = tplbit; + } + + RTLIL::SigSig port_conn; + for (auto &it : port_connmap) { + port_conn.first.append_bit(it.first); + port_conn.second.append_bit(it.second); + } + tpl->connect(port_conn); + } + + Pass::call_on_module(map, tpl, cmd_string); + log_assert(!strncmp(q, "_TECHMAP_DO_", 12)); std::string new_name = data.wire->name.substr(0, q-p) + "_TECHMAP_DONE_" + data.wire->name.substr(q-p+12); while (tpl->wires_.count(new_name)) new_name += "_"; - tpl->rename(data.wire, new_name); - - std::string cmd_string = data.value.as_const().decode_string(); - Pass::call_on_module(map, tpl, cmd_string); + tpl->rename(data.wire->name, new_name); keep_running = true; break; @@ -571,6 +672,14 @@ struct TechmapPass : public Pass { log(" wire to start out as non-constant and evaluate to a constant value\n"); log(" during processing of other _TECHMAP_DO_* commands.\n"); log("\n"); + log(" A _TECHMAP_DO_* command may start with the special token 'CONSTMAP; '.\n"); + log(" in this case techmap will create a copy for each distinct configuration\n"); + log(" of constant inputs and shorted inputs at this point and import the\n"); + log(" constant and connected bits into the map module. All further commands\n"); + log(" are executed in this copy. This is a very convenient way of creating\n"); + log(" optimizied specializations of techmap modules without using the special\n"); + log(" parameters described below.\n"); + log("\n"); log("In addition to this special wires, techmap also supports special parameters in\n"); log("modules in the map file:\n"); log("\n"); -- cgit v1.2.3 From 6ca0c569d92883b6eac1725204de90aee4af31bc Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 31 Jul 2014 02:21:41 +0200 Subject: Added "techmap -assert" --- passes/techmap/techmap.cc | 55 ++++++++++++++++++++++++++++++++++++----------- passes/tests/test_cell.cc | 2 +- 2 files changed, 43 insertions(+), 14 deletions(-) (limited to 'passes') diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 75b9dee9b..50936af0e 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -66,6 +66,17 @@ struct TechmapWorker typedef std::map> TechmapWires; + bool extern_mode; + bool assert_mode; + bool flatten_mode; + + TechmapWorker() + { + extern_mode = false; + assert_mode = false; + flatten_mode = false; + } + std::string constmap_tpl_name(SigMap &sigmap, RTLIL::Module *tpl, RTLIL::Cell *cell, bool verbose) { std::string constmap_info; @@ -131,7 +142,7 @@ struct TechmapWorker return result; } - void techmap_module_worker(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Cell *cell, RTLIL::Module *tpl, bool flatten_mode) + void techmap_module_worker(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Cell *cell, RTLIL::Module *tpl) { log("Mapping `%s.%s' using `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(tpl->name)); @@ -245,7 +256,7 @@ struct TechmapWorker } bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, std::set &handled_cells, - const std::map> &celltypeMap, bool flatten_mode, bool extern_mode) + const std::map> &celltypeMap) { if (!design->selected(module)) return false; @@ -264,8 +275,11 @@ struct TechmapWorker if (!design->selected(module, cell) || handled_cells.count(cell) > 0) continue; - if (celltypeMap.count(cell->type) == 0) + if (celltypeMap.count(cell->type) == 0) { + if (assert_mode && cell->type.back() != '_') + log_error("(ASSERT MODE) No matching template cell for type %s found.\n", log_id(cell->type)); continue; + } for (auto &conn : cell->connections()) { @@ -300,6 +314,7 @@ struct TechmapWorker { log_assert(handled_cells.count(cell) == 0); log_assert(cell == module->cell(cell->name)); + bool mapped_cell = false; for (auto &tpl_name : celltypeMap.at(cell->type)) { @@ -316,7 +331,7 @@ struct TechmapWorker { if (extern_mode) { - log("WARNING: Mapping simplat cell %s.%s (%s) in -extern mode is not supported yet.\n", log_id(module), log_id(cell), log_id(cell->type)); + log("WARNING: Mapping simplemap cell %s.%s (%s) in -extern mode is not supported yet.\n", log_id(module), log_id(cell), log_id(cell->type)); break; } else @@ -328,6 +343,7 @@ struct TechmapWorker module->remove(cell); cell = NULL; did_something = true; + mapped_cell = true; break; } } @@ -587,13 +603,17 @@ struct TechmapWorker } else { - techmap_module_worker(design, module, cell, tpl, flatten_mode); + techmap_module_worker(design, module, cell, tpl); cell = NULL; } did_something = true; + mapped_cell = true; break; } + if (assert_mode && !mapped_cell) + log_error("(ASSERT MODE) Failed to map cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type)); + handled_cells.insert(cell); } @@ -636,6 +656,11 @@ struct TechmapPass : public Pass { log(" -max_iter \n"); log(" only run the specified number of iterations.\n"); log("\n"); + log(" -assert\n"); + log(" this option will cause techmap to exit with an error if it can't map\n"); + log(" a selected cell. only cell types that end on an underscore are accepted\n"); + log(" as final cell types by this mode.\n"); + log("\n"); log(" -D , -I \n"); log(" this options are passed as-is to the verilog frontend for loading the\n"); log(" map file. Note that the verilog frontend is also called with the\n"); @@ -720,9 +745,11 @@ struct TechmapPass : public Pass { log_header("Executing TECHMAP pass (map to technology primitives).\n"); log_push(); + TechmapWorker worker; + simplemap_get_mappers(worker.simplemap_mappers); + std::vector map_files; std::string verilog_frontend = "verilog -ignore_redef"; - bool extern_mode = false; int max_iter = -1; size_t argidx; @@ -748,17 +775,18 @@ struct TechmapPass : public Pass { verilog_frontend += " -I " + args[++argidx]; continue; } + if (args[argidx] == "-assert") { + worker.assert_mode = true; + continue; + } if (args[argidx] == "-extern") { - extern_mode = true; + worker.extern_mode = true; continue; } break; } extra_args(args, argidx, design); - TechmapWorker worker; - simplemap_get_mappers(worker.simplemap_mappers); - RTLIL::Design *map = new RTLIL::Design; if (map_files.empty()) { FILE *f = fmemopen(stdcells_code, strlen(stdcells_code), "rt"); @@ -811,7 +839,7 @@ struct TechmapPass : public Pass { std::set handled_cells; while (did_something) { did_something = false; - if (worker.techmap_module(design, module, map, handled_cells, celltypeMap, false, extern_mode)) + if (worker.techmap_module(design, module, map, handled_cells, celltypeMap)) did_something = true; if (did_something) module->check(); @@ -848,6 +876,7 @@ struct FlattenPass : public Pass { extra_args(args, 1, design); TechmapWorker worker; + worker.flatten_mode = true; std::map> celltypeMap; for (auto &it : design->modules_) @@ -864,11 +893,11 @@ struct FlattenPass : public Pass { while (did_something) { did_something = false; if (top_mod != NULL) { - if (worker.techmap_module(design, top_mod, design, handled_cells, celltypeMap, true, false)) + if (worker.techmap_module(design, top_mod, design, handled_cells, celltypeMap)) did_something = true; } else { for (auto mod : design->modules()) - if (worker.techmap_module(design, mod, design, handled_cells, celltypeMap, true, false)) + if (worker.techmap_module(design, mod, design, handled_cells, celltypeMap)) did_something = true; } } diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index d504cea94..4034f120e 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -104,7 +104,7 @@ struct TestCellPass : public Pass { virtual void execute(std::vector args, RTLIL::Design*) { int num_iter = 100; - std::string techmap_cmd = "techmap"; + std::string techmap_cmd = "techmap -assert"; std::string ilang_file; int argidx; -- cgit v1.2.3 From 1202f7aa4bb0f9afde157ebc4701d64e7e38abd8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 31 Jul 2014 02:32:00 +0200 Subject: Renamed "stdcells.v" to "techmap.v" --- passes/techmap/.gitignore | 2 +- passes/techmap/Makefile.inc | 6 +++--- passes/techmap/techmap.cc | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) (limited to 'passes') diff --git a/passes/techmap/.gitignore b/passes/techmap/.gitignore index ca9d3942c..e6dcc6bc0 100644 --- a/passes/techmap/.gitignore +++ b/passes/techmap/.gitignore @@ -1 +1 @@ -stdcells.inc +techmap.inc diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc index e54c018aa..b49259a8a 100644 --- a/passes/techmap/Makefile.inc +++ b/passes/techmap/Makefile.inc @@ -10,16 +10,16 @@ OBJS += passes/techmap/hilomap.o OBJS += passes/techmap/extract.o endif -GENFILES += passes/techmap/stdcells.inc +GENFILES += passes/techmap/techmap.inc -passes/techmap/stdcells.inc: techlibs/common/stdcells.v +passes/techmap/techmap.inc: techlibs/common/techmap.v $(P) echo "// autogenerated from $<" > $@.new $(Q) echo "static char stdcells_code[] = {" >> $@.new $(Q) od -v -td1 -An $< | $(SED) -e 's/[0-9][0-9]*/&,/g' >> $@.new $(Q) echo "0};" >> $@.new $(Q) mv $@.new $@ -passes/techmap/techmap.o: passes/techmap/stdcells.inc +passes/techmap/techmap.o: passes/techmap/techmap.inc TARGETS += yosys-filterlib GENFILES += passes/techmap/filterlib.o diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 50936af0e..2aa59e61b 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -26,7 +26,7 @@ #include #include -#include "passes/techmap/stdcells.inc" +#include "passes/techmap/techmap.inc" // see simplemap.cc extern void simplemap_get_mappers(std::map &mappers); @@ -790,7 +790,7 @@ struct TechmapPass : public Pass { RTLIL::Design *map = new RTLIL::Design; if (map_files.empty()) { FILE *f = fmemopen(stdcells_code, strlen(stdcells_code), "rt"); - Frontend::frontend_call(map, f, "", verilog_frontend); + Frontend::frontend_call(map, f, "", verilog_frontend); fclose(f); } else for (auto &fn : map_files) -- cgit v1.2.3 From 1cb25c05b37b0172dbc50e140fe20f25d973dd8a Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 31 Jul 2014 13:19:47 +0200 Subject: Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace --- passes/abc/abc.cc | 4 ++-- passes/cmds/design.cc | 4 ++++ passes/fsm/fsm_extract.cc | 4 ++-- passes/memory/memory_collect.cc | 2 +- passes/memory/memory_dff.cc | 2 +- passes/memory/memory_map.cc | 2 +- passes/memory/memory_unpack.cc | 2 +- passes/proc/proc_dff.cc | 6 +++--- passes/proc/proc_mux.cc | 4 ++-- passes/techmap/extract.cc | 2 +- passes/techmap/techmap.cc | 2 +- 11 files changed, 19 insertions(+), 15 deletions(-) (limited to 'passes') diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index d2be7dcf1..d204e93c6 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -313,7 +313,7 @@ static void handle_loops() } std::stringstream sstr; - sstr << "$abcloop$" << (RTLIL::autoidx++); + sstr << "$abcloop$" << (autoidx++); RTLIL::Wire *wire = module->addWire(sstr.str()); bool first_line = true; @@ -400,7 +400,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std std::string liberty_file, std::string constr_file, bool cleanup, int lut_mode, bool dff_mode, std::string clk_str, bool keepff) { module = current_module; - map_autoidx = RTLIL::autoidx++; + map_autoidx = autoidx++; signal_map.clear(); signal_list.clear(); diff --git a/passes/cmds/design.cc b/passes/cmds/design.cc index bd1ee68f2..79695c635 100644 --- a/passes/cmds/design.cc +++ b/passes/cmds/design.cc @@ -22,6 +22,8 @@ #include "kernel/rtlil.h" #include "kernel/log.h" +YOSYS_NAMESPACE_BEGIN + std::map saved_designs; std::vector pushed_designs; @@ -249,3 +251,5 @@ struct DesignPass : public Pass { } } DesignPass; +YOSYS_NAMESPACE_END + diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index 6da468321..718f779b6 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -270,7 +270,7 @@ static void extract_fsm(RTLIL::Wire *wire) // create fsm cell - RTLIL::Cell *fsm_cell = module->addCell(stringf("$fsm$%s$%d", wire->name.c_str(), RTLIL::autoidx++), "$fsm"); + RTLIL::Cell *fsm_cell = module->addCell(stringf("$fsm$%s$%d", wire->name.c_str(), autoidx++), "$fsm"); fsm_cell->set("\\CLK", clk); fsm_cell->set("\\ARST", arst); fsm_cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity ? 1 : 0, 1); @@ -296,7 +296,7 @@ static void extract_fsm(RTLIL::Wire *wire) RTLIL::Cell *cell = module->cells_.at(cellport.first); RTLIL::SigSpec port_sig = assign_map(cell->get(cellport.second)); RTLIL::SigSpec unconn_sig = port_sig.extract(ctrl_out); - RTLIL::Wire *unconn_wire = module->addWire(stringf("$fsm_unconnect$%s$%d", log_signal(unconn_sig), RTLIL::autoidx++), unconn_sig.size()); + RTLIL::Wire *unconn_wire = module->addWire(stringf("$fsm_unconnect$%s$%d", log_signal(unconn_sig), autoidx++), unconn_sig.size()); port_sig.replace(unconn_sig, RTLIL::SigSpec(unconn_wire), &cell->connections_[cellport.second]); } } diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc index 40c68abc1..aecb7bd6c 100644 --- a/passes/memory/memory_collect.cc +++ b/passes/memory/memory_collect.cc @@ -126,7 +126,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) } std::stringstream sstr; - sstr << "$mem$" << memory->name << "$" << (RTLIL::autoidx++); + sstr << "$mem$" << memory->name << "$" << (autoidx++); RTLIL::Cell *mem = module->addCell(sstr.str(), "$mem"); mem->parameters["\\MEMID"] = RTLIL::Const(memory->name); diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index 325056170..6cbce781f 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -113,7 +113,7 @@ static void disconnect_dff(RTLIL::Module *module, RTLIL::SigSpec sig) sig.sort_and_unify(); std::stringstream sstr; - sstr << "$memory_dff_disconnected$" << (RTLIL::autoidx++); + sstr << "$memory_dff_disconnected$" << (autoidx++); RTLIL::SigSpec new_sig = module->addWire(sstr.str(), sig.size()); diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index 49291656c..0000bd507 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -41,7 +41,7 @@ static std::string genid(std::string name, std::string token1 = "", int i = -1, if (k >= 0) sstr << "[" << k << "]"; - sstr << token4 << "$" << (RTLIL::autoidx++); + sstr << token4 << "$" << (autoidx++); return sstr.str(); } diff --git a/passes/memory/memory_unpack.cc b/passes/memory/memory_unpack.cc index cdf7db04b..3f675edea 100644 --- a/passes/memory/memory_unpack.cc +++ b/passes/memory/memory_unpack.cc @@ -31,7 +31,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory) RTLIL::IdString mem_name = RTLIL::escape_id(memory->parameters.at("\\MEMID").decode_string()); while (module->memories.count(mem_name) != 0) - mem_name += stringf("_%d", RTLIL::autoidx++); + mem_name += stringf("_%d", autoidx++); RTLIL::Memory *mem = new RTLIL::Memory; mem->name = mem_name; diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index 91cafe3be..d894b442b 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -122,7 +122,7 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S } std::stringstream sstr; - sstr << "$procdff$" << (RTLIL::autoidx++); + sstr << "$procdff$" << (autoidx++); RTLIL::Cell *cell = mod->addCell(sstr.str(), "$dffsr"); cell->attributes = proc->attributes; @@ -144,7 +144,7 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec bool clk_polarity, bool set_polarity, RTLIL::SigSpec clk, RTLIL::SigSpec set, RTLIL::Process *proc) { std::stringstream sstr; - sstr << "$procdff$" << (RTLIL::autoidx++); + sstr << "$procdff$" << (autoidx++); RTLIL::SigSpec sig_set_inv = mod->addWire(NEW_ID, sig_in.size()); RTLIL::SigSpec sig_sr_set = mod->addWire(NEW_ID, sig_in.size()); @@ -191,7 +191,7 @@ static void gen_dff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::Const val_ bool clk_polarity, bool arst_polarity, RTLIL::SigSpec clk, RTLIL::SigSpec *arst, RTLIL::Process *proc) { std::stringstream sstr; - sstr << "$procdff$" << (RTLIL::autoidx++); + sstr << "$procdff$" << (autoidx++); RTLIL::Cell *cell = mod->addCell(sstr.str(), arst ? "$adff" : "$dff"); cell->attributes = proc->attributes; diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc index e7661245e..b18ce4925 100644 --- a/passes/proc/proc_mux.cc +++ b/passes/proc/proc_mux.cc @@ -57,7 +57,7 @@ static void extract_core_signal(const RTLIL::CaseRule *cs, RTLIL::SigSpec &sig) static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector &compare, RTLIL::SwitchRule *sw) { std::stringstream sstr; - sstr << "$procmux$" << (RTLIL::autoidx++); + sstr << "$procmux$" << (autoidx++); RTLIL::Wire *cmp_wire = mod->addWire(sstr.str() + "_CMP", 0); @@ -127,7 +127,7 @@ static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, log_assert(when_signal.size() == else_signal.size()); std::stringstream sstr; - sstr << "$procmux$" << (RTLIL::autoidx++); + sstr << "$procmux$" << (autoidx++); // the trivial cases if (compare.size() == 0 || when_signal == else_signal) diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index 19d323341..ed389f2fb 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -296,7 +296,7 @@ namespace SigSet> sig2port; // create new cell - RTLIL::Cell *cell = haystack->addCell(stringf("$extract$%s$%d", needle->name.c_str(), RTLIL::autoidx++), needle->name); + RTLIL::Cell *cell = haystack->addCell(stringf("$extract$%s$%d", needle->name.c_str(), autoidx++), needle->name); // create cell ports for (auto &it : needle->wires_) { diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 2aa59e61b..c2e5960ff 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -161,7 +161,7 @@ struct TechmapWorker for (auto &it : tpl->cells_) if (it.first == "\\_TECHMAP_REPLACE_") { orig_cell_name = cell->name; - module->rename(cell, stringf("$techmap%d", RTLIL::autoidx++) + cell->name); + module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name); break; } -- cgit v1.2.3 From e6d33513a5b809facc6e3e5e75d2248bfa94f82b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 31 Jul 2014 14:11:39 +0200 Subject: Added module->design and cell->module, wire->module pointers --- passes/abc/blifparse.cc | 2 +- passes/cmds/copy.cc | 5 +++-- passes/cmds/design.cc | 5 +++-- passes/hierarchy/hierarchy.cc | 2 +- passes/hierarchy/submod.cc | 2 +- passes/sat/miter.cc | 2 +- passes/techmap/extract.cc | 2 +- 7 files changed, 11 insertions(+), 9 deletions(-) (limited to 'passes') diff --git a/passes/abc/blifparse.cc b/passes/abc/blifparse.cc index 4bcbc0131..e10cb109f 100644 --- a/passes/abc/blifparse.cc +++ b/passes/abc/blifparse.cc @@ -60,7 +60,7 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name) int port_count = 0; module->name = "\\netlist"; - design->modules_[module->name] = module; + design->add(module); size_t buffer_size = 4096; char *buffer = (char*)malloc(buffer_size); diff --git a/passes/cmds/copy.cc b/passes/cmds/copy.cc index fc801f61f..be7758200 100644 --- a/passes/cmds/copy.cc +++ b/passes/cmds/copy.cc @@ -47,8 +47,9 @@ struct CopyPass : public Pass { if (design->modules_.count(trg_name) != 0) log_cmd_error("Target module name %s already exists.\n", trg_name.c_str()); - design->modules_[trg_name] = design->modules_.at(src_name)->clone(); - design->modules_[trg_name]->name = trg_name; + RTLIL::Module *new_mod = design->module(src_name)->clone(); + new_mod->name = trg_name; + design->add(new_mod); } } CopyPass; diff --git a/passes/cmds/design.cc b/passes/cmds/design.cc index 79695c635..41548f621 100644 --- a/passes/cmds/design.cc +++ b/passes/cmds/design.cc @@ -198,6 +198,7 @@ struct DesignPass : public Pass { delete copy_to_design->modules_.at(trg_name); copy_to_design->modules_[trg_name] = mod->clone(); copy_to_design->modules_[trg_name]->name = trg_name; + copy_to_design->modules_[trg_name]->design = copy_to_design; } } @@ -206,7 +207,7 @@ struct DesignPass : public Pass { RTLIL::Design *design_copy = new RTLIL::Design; for (auto &it : design->modules_) - design_copy->modules_[it.first] = it.second->clone(); + design_copy->add(it.second->clone()); design_copy->selection_stack = design->selection_stack; design_copy->selection_vars = design->selection_vars; @@ -242,7 +243,7 @@ struct DesignPass : public Pass { pushed_designs.pop_back(); for (auto &it : saved_design->modules_) - design->modules_[it.first] = it.second->clone(); + design->add(it.second->clone()); design->selection_stack = saved_design->selection_stack; design->selection_vars = saved_design->selection_vars; diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index a1361c680..67b57a94d 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -117,7 +117,7 @@ static void generate(RTLIL::Design *design, const std::vector &cell RTLIL::Module *mod = new RTLIL::Module; mod->name = celltype; mod->attributes["\\blackbox"] = RTLIL::Const(1); - design->modules_[mod->name] = mod; + design->add(mod); for (auto &decl : ports) { RTLIL::Wire *wire = mod->addWire(decl.portname, portwidths.at(decl.portname)); diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index 84c6b9161..d0c9f4b5a 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -105,7 +105,7 @@ struct SubmodWorker RTLIL::Module *new_mod = new RTLIL::Module; new_mod->name = submod.full_name; - design->modules_[new_mod->name] = new_mod; + design->add(new_mod); int port_counter = 1, auto_name_counter = 1; std::set all_wire_names; diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index 0f00e71a6..ffd9f1b62 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -113,7 +113,7 @@ static void create_miter_equiv(struct Pass *that, std::vector args, RTLIL::Module *miter_module = new RTLIL::Module; miter_module->name = miter_name; - design->modules_[miter_name] = miter_module; + design->add(miter_module); RTLIL::Cell *gold_cell = miter_module->addCell("\\gold", gold_name); RTLIL::Cell *gate_cell = miter_module->addCell("\\gate", gate_name); diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index ed389f2fb..060a87407 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -724,7 +724,7 @@ struct ExtractPass : public Pass { RTLIL::Module *newMod = new RTLIL::Module; newMod->name = stringf("\\needle%05d_%s_%dx", needleCounter++, id2cstr(haystack_map.at(result.graphId)->name), result.totalMatchesAfterLimits); - map->modules_[newMod->name] = newMod; + map->add(newMod); int portCounter = 1; for (auto wire : wires) { -- cgit v1.2.3 From b5a9e51b966abdfedc9309defa79b5141928e84a Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 31 Jul 2014 15:02:16 +0200 Subject: Added "trace" command --- passes/cmds/Makefile.inc | 1 + passes/cmds/tee.cc | 4 +- passes/cmds/trace.cc | 97 ++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 100 insertions(+), 2 deletions(-) create mode 100644 passes/cmds/trace.cc (limited to 'passes') diff --git a/passes/cmds/Makefile.inc b/passes/cmds/Makefile.inc index 26c0ef8a9..b55af9958 100644 --- a/passes/cmds/Makefile.inc +++ b/passes/cmds/Makefile.inc @@ -19,4 +19,5 @@ OBJS += passes/cmds/tee.o OBJS += passes/cmds/write_file.o OBJS += passes/cmds/connwrappers.o OBJS += passes/cmds/cover.o +OBJS += passes/cmds/trace.o diff --git a/passes/cmds/tee.cc b/passes/cmds/tee.cc index e2f69e599..6f80ef72c 100644 --- a/passes/cmds/tee.cc +++ b/passes/cmds/tee.cc @@ -73,11 +73,11 @@ struct TeePass : public Pass { try { std::vector new_args(args.begin() + argidx, args.end()); Pass::call(design, new_args); - } catch (int ex) { + } catch (log_cmd_error_expection) { for (auto cf : files_to_close) fclose(cf); log_files = backup_log_files; - throw ex; + throw log_cmd_error_expection(); } for (auto cf : files_to_close) diff --git a/passes/cmds/trace.cc b/passes/cmds/trace.cc new file mode 100644 index 000000000..b4bc45c20 --- /dev/null +++ b/passes/cmds/trace.cc @@ -0,0 +1,97 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2014 Clifford Wolf + * Copyright (C) 2014 Johann Glaser + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" + +PRIVATE_NAMESPACE_BEGIN + +struct TraceMonitor : public RTLIL::Monitor +{ + virtual void notify_module_add(RTLIL::Module *module) override + { + log("#TRACE# Module add: %s\n", log_id(module)); + } + + virtual void notify_module_del(RTLIL::Module *module) override + { + log("#TRACE# Module delete: %s\n", log_id(module)); + } + + virtual void notify_cell_connect(RTLIL::Cell *cell, const std::pair &conn) override + { + log("#TRACE# Cell connect: %s.%s.%s = %s\n", log_id(cell->module), log_id(cell), log_id(conn.first), log_signal(conn.second)); + } + + virtual void notify_connect(RTLIL::Module *module, const RTLIL::SigSig &sigsig) override + { + log("#TRACE# Connection in module %s: %s = %s\n", log_id(module), log_signal(sigsig.first), log_signal(sigsig.second)); + } + + virtual void notify_new_connections(RTLIL::Module *module, const std::vector &sigsig_vec) override + { + log("#TRACE# New connections in module %s:\n", log_id(module)); + for (auto &sigsig : sigsig_vec) + log("## %s = %s\n", log_signal(sigsig.first), log_signal(sigsig.second)); + } + + virtual void notify_blackout(RTLIL::Module *module) override + { + log("#TRACE# Blackout in module %s:\n", log_id(module)); + } +}; + +struct TracePass : public Pass { + TracePass() : Pass("trace", "redirect command output to file") { } + virtual void help() + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" trace cmd\n"); + log("\n"); + log("Execute the specified command, logging all changes the command performs on\n"); + log("the design in real time.\n"); + log("\n"); + } + virtual void execute(std::vector args, RTLIL::Design *design) + { + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) + { + // .. parse options .. + break; + } + + TraceMonitor monitor; + design->monitors.insert(&monitor); + + try { + std::vector new_args(args.begin() + argidx, args.end()); + Pass::call(design, new_args); + } catch (log_cmd_error_expection) { + design->monitors.erase(&monitor); + throw log_cmd_error_expection(); + } + + design->monitors.erase(&monitor); + } +} TracePass; + +PRIVATE_NAMESPACE_END + -- cgit v1.2.3 From cdae8abe16847c533171fed111beea7b52202cce Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 31 Jul 2014 16:38:54 +0200 Subject: Renamed port access function on RTLIL::Cell, added param access functions --- passes/abc/abc.cc | 64 ++++++------- passes/abc/blifparse.cc | 10 +- passes/cmds/add.cc | 4 +- passes/cmds/connect.cc | 2 +- passes/cmds/splice.cc | 14 +-- passes/fsm/fsm_detect.cc | 14 +-- passes/fsm/fsm_expand.cc | 54 +++++------ passes/fsm/fsm_extract.cc | 34 +++---- passes/fsm/fsm_map.cc | 48 +++++----- passes/fsm/fsm_opt.cc | 14 +-- passes/fsm/fsmdata.h | 4 +- passes/hierarchy/submod.cc | 2 +- passes/memory/memory_collect.cc | 28 +++--- passes/memory/memory_dff.cc | 38 ++++---- passes/memory/memory_map.cc | 70 +++++++------- passes/memory/memory_share.cc | 106 +++++++++++----------- passes/memory/memory_unpack.cc | 14 +-- passes/opt/opt_const.cc | 196 ++++++++++++++++++++-------------------- passes/opt/opt_muxtree.cc | 22 ++--- passes/opt/opt_reduce.cc | 80 ++++++++-------- passes/opt/opt_rmdff.cc | 36 ++++---- passes/opt/opt_share.cc | 6 +- passes/proc/proc_arst.cc | 44 ++++----- passes/proc/proc_dff.cc | 88 +++++++++--------- passes/proc/proc_mux.cc | 30 +++--- passes/sat/expose.cc | 48 +++++----- passes/sat/freduce.cc | 6 +- passes/sat/miter.cc | 56 ++++++------ passes/sat/share.cc | 84 ++++++++--------- passes/techmap/dfflibmap.cc | 2 +- passes/techmap/extract.cc | 12 +-- passes/techmap/hilomap.cc | 4 +- passes/techmap/iopadmap.cc | 8 +- passes/techmap/simplemap.cc | 170 +++++++++++++++++----------------- passes/tests/test_cell.cc | 6 +- 35 files changed, 709 insertions(+), 709 deletions(-) (limited to 'passes') diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index d204e93c6..4b2e82ca7 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -110,11 +110,11 @@ static void extract_cell(RTLIL::Cell *cell, bool keepff) { if (clk_polarity != (cell->type == "$_DFF_P_")) return; - if (clk_sig != assign_map(cell->get("\\C"))) + if (clk_sig != assign_map(cell->getPort("\\C"))) return; - RTLIL::SigSpec sig_d = cell->get("\\D"); - RTLIL::SigSpec sig_q = cell->get("\\Q"); + RTLIL::SigSpec sig_d = cell->getPort("\\D"); + RTLIL::SigSpec sig_q = cell->getPort("\\Q"); if (keepff) for (auto &c : sig_q.chunks()) @@ -132,8 +132,8 @@ static void extract_cell(RTLIL::Cell *cell, bool keepff) if (cell->type == "$_INV_") { - RTLIL::SigSpec sig_a = cell->get("\\A"); - RTLIL::SigSpec sig_y = cell->get("\\Y"); + RTLIL::SigSpec sig_a = cell->getPort("\\A"); + RTLIL::SigSpec sig_y = cell->getPort("\\Y"); assign_map.apply(sig_a); assign_map.apply(sig_y); @@ -146,9 +146,9 @@ static void extract_cell(RTLIL::Cell *cell, bool keepff) if (cell->type == "$_AND_" || cell->type == "$_OR_" || cell->type == "$_XOR_") { - RTLIL::SigSpec sig_a = cell->get("\\A"); - RTLIL::SigSpec sig_b = cell->get("\\B"); - RTLIL::SigSpec sig_y = cell->get("\\Y"); + RTLIL::SigSpec sig_a = cell->getPort("\\A"); + RTLIL::SigSpec sig_b = cell->getPort("\\B"); + RTLIL::SigSpec sig_y = cell->getPort("\\Y"); assign_map.apply(sig_a); assign_map.apply(sig_b); @@ -172,10 +172,10 @@ static void extract_cell(RTLIL::Cell *cell, bool keepff) if (cell->type == "$_MUX_") { - RTLIL::SigSpec sig_a = cell->get("\\A"); - RTLIL::SigSpec sig_b = cell->get("\\B"); - RTLIL::SigSpec sig_s = cell->get("\\S"); - RTLIL::SigSpec sig_y = cell->get("\\Y"); + RTLIL::SigSpec sig_a = cell->getPort("\\A"); + RTLIL::SigSpec sig_b = cell->getPort("\\B"); + RTLIL::SigSpec sig_s = cell->getPort("\\S"); + RTLIL::SigSpec sig_y = cell->getPort("\\Y"); assign_map.apply(sig_a); assign_map.apply(sig_b); @@ -467,7 +467,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std if (cell->type != "$_DFF_N_" && cell->type != "$_DFF_P_") continue; - std::pair key(cell->type == "$_DFF_P_", assign_map(cell->get("\\C"))); + std::pair key(cell->type == "$_DFF_P_", assign_map(cell->getPort("\\C"))); if (++dff_counters[key] > best_dff_counter) { best_dff_counter = dff_counters[key]; clk_polarity = key.first; @@ -700,48 +700,48 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std cell_stats[RTLIL::unescape_id(c->type)]++; if (c->type == "\\ZERO" || c->type == "\\ONE") { RTLIL::SigSig conn; - conn.first = RTLIL::SigSpec(module->wires_[remap_name(c->get("\\Y").as_wire()->name)]); + conn.first = RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]); conn.second = RTLIL::SigSpec(c->type == "\\ZERO" ? 0 : 1, 1); module->connect(conn); continue; } if (c->type == "\\BUF") { RTLIL::SigSig conn; - conn.first = RTLIL::SigSpec(module->wires_[remap_name(c->get("\\Y").as_wire()->name)]); - conn.second = RTLIL::SigSpec(module->wires_[remap_name(c->get("\\A").as_wire()->name)]); + conn.first = RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]); + conn.second = RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]); module->connect(conn); continue; } if (c->type == "\\INV") { RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_INV_"); - cell->set("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\A").as_wire()->name)])); - cell->set("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\Y").as_wire()->name)])); + cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)])); + cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)])); design->select(module, cell); continue; } if (c->type == "\\AND" || c->type == "\\OR" || c->type == "\\XOR") { RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_" + c->type.substr(1) + "_"); - cell->set("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\A").as_wire()->name)])); - cell->set("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\B").as_wire()->name)])); - cell->set("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\Y").as_wire()->name)])); + cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)])); + cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)])); + cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)])); design->select(module, cell); continue; } if (c->type == "\\MUX") { RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_MUX_"); - cell->set("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\A").as_wire()->name)])); - cell->set("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\B").as_wire()->name)])); - cell->set("\\S", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\S").as_wire()->name)])); - cell->set("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\Y").as_wire()->name)])); + cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)])); + cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)])); + cell->setPort("\\S", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\S").as_wire()->name)])); + cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)])); design->select(module, cell); continue; } if (c->type == "\\DFF") { log_assert(clk_sig.size() == 1); RTLIL::Cell *cell = module->addCell(remap_name(c->name), clk_polarity ? "$_DFF_P_" : "$_DFF_N_"); - cell->set("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\D").as_wire()->name)])); - cell->set("\\Q", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\Q").as_wire()->name)])); - cell->set("\\C", clk_sig); + cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)])); + cell->setPort("\\Q", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Q").as_wire()->name)])); + cell->setPort("\\C", clk_sig); design->select(module, cell); continue; } @@ -764,9 +764,9 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std if (c->type == "\\_dff_") { log_assert(clk_sig.size() == 1); RTLIL::Cell *cell = module->addCell(remap_name(c->name), clk_polarity ? "$_DFF_P_" : "$_DFF_N_"); - cell->set("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\D").as_wire()->name)])); - cell->set("\\Q", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\Q").as_wire()->name)])); - cell->set("\\C", clk_sig); + cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)])); + cell->setPort("\\Q", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Q").as_wire()->name)])); + cell->setPort("\\C", clk_sig); design->select(module, cell); continue; } @@ -780,7 +780,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std log_assert(c.width == 1); newsig.append(module->wires_[remap_name(c.wire->name)]); } - cell->set(conn.first, newsig); + cell->setPort(conn.first, newsig); } design->select(module, cell); } diff --git a/passes/abc/blifparse.cc b/passes/abc/blifparse.cc index e10cb109f..1891a7450 100644 --- a/passes/abc/blifparse.cc +++ b/passes/abc/blifparse.cc @@ -120,8 +120,8 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name) module->addWire(RTLIL::escape_id(q)); RTLIL::Cell *cell = module->addCell(NEW_ID, dff_name); - cell->set("\\D", module->wires_.at(RTLIL::escape_id(d))); - cell->set("\\Q", module->wires_.at(RTLIL::escape_id(q))); + cell->setPort("\\D", module->wires_.at(RTLIL::escape_id(d))); + cell->setPort("\\Q", module->wires_.at(RTLIL::escape_id(q))); continue; } @@ -140,7 +140,7 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name) *(q++) = 0; if (module->wires_.count(RTLIL::escape_id(q)) == 0) module->addWire(RTLIL::escape_id(q)); - cell->set(RTLIL::escape_id(p), module->wires_.at(RTLIL::escape_id(q))); + cell->setPort(RTLIL::escape_id(p), module->wires_.at(RTLIL::escape_id(q))); } continue; } @@ -196,8 +196,8 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name) RTLIL::Cell *cell = module->addCell(NEW_ID, "$lut"); cell->parameters["\\WIDTH"] = RTLIL::Const(input_sig.size()); cell->parameters["\\LUT"] = RTLIL::Const(RTLIL::State::Sx, 1 << input_sig.size()); - cell->set("\\I", input_sig); - cell->set("\\O", output_sig); + cell->setPort("\\I", input_sig); + cell->setPort("\\O", output_sig); lutptr = &cell->parameters.at("\\LUT"); lut_default_state = RTLIL::State::Sx; continue; diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc index 62995a49d..e3fde8559 100644 --- a/passes/cmds/add.cc +++ b/passes/cmds/add.cc @@ -72,10 +72,10 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n continue; if (mod->get_bool_attribute("\\blackbox")) continue; - if (it.second->has(name)) + if (it.second->hasPort(name)) continue; - it.second->set(name, wire); + it.second->setPort(name, wire); log("Added connection %s to cell %s.%s (%s).\n", name.c_str(), module->name.c_str(), it.first.c_str(), it.second->type.c_str()); } } diff --git a/passes/cmds/connect.cc b/passes/cmds/connect.cc index 3e13fd4d4..30c80f732 100644 --- a/passes/cmds/connect.cc +++ b/passes/cmds/connect.cc @@ -176,7 +176,7 @@ struct ConnectPass : public Pass { if (!RTLIL::SigSpec::parse_sel(sig, design, module, port_expr)) log_cmd_error("Failed to parse port expression `%s'.\n", port_expr.c_str()); - module->cells_.at(RTLIL::escape_id(port_cell))->set(RTLIL::escape_id(port_port), sigmap(sig)); + module->cells_.at(RTLIL::escape_id(port_cell))->setPort(RTLIL::escape_id(port_port), sigmap(sig)); } else log_cmd_error("Expected -set, -unset, or -port.\n"); diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc index 5fce2d6cb..07c6150cc 100644 --- a/passes/cmds/splice.cc +++ b/passes/cmds/splice.cc @@ -74,9 +74,9 @@ struct SpliceWorker cell->parameters["\\OFFSET"] = offset; cell->parameters["\\A_WIDTH"] = sig_a.size(); cell->parameters["\\Y_WIDTH"] = sig.size(); - cell->set("\\A", sig_a); - cell->set("\\Y", module->addWire(NEW_ID, sig.size())); - new_sig = cell->get("\\Y"); + cell->setPort("\\A", sig_a); + cell->setPort("\\Y", module->addWire(NEW_ID, sig.size())); + new_sig = cell->getPort("\\Y"); } sliced_signals_cache[sig] = new_sig; @@ -130,10 +130,10 @@ struct SpliceWorker RTLIL::Cell *cell = module->addCell(NEW_ID, "$concat"); cell->parameters["\\A_WIDTH"] = new_sig.size(); cell->parameters["\\B_WIDTH"] = sig2.size(); - cell->set("\\A", new_sig); - cell->set("\\B", sig2); - cell->set("\\Y", module->addWire(NEW_ID, new_sig.size() + sig2.size())); - new_sig = cell->get("\\Y"); + cell->setPort("\\A", new_sig); + cell->setPort("\\B", sig2); + cell->setPort("\\Y", module->addWire(NEW_ID, new_sig.size() + sig2.size())); + new_sig = cell->getPort("\\Y"); } spliced_signals_cache[sig] = new_sig; diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc index a619cf57d..6025de15b 100644 --- a/passes/fsm/fsm_detect.cc +++ b/passes/fsm/fsm_detect.cc @@ -52,8 +52,8 @@ static bool check_state_mux_tree(RTLIL::SigSpec old_sig, RTLIL::SigSpec sig, Sig for (auto &cellport : cellport_list) { if ((cellport.first->type != "$mux" && cellport.first->type != "$pmux" && cellport.first->type != "$safe_pmux") || cellport.second != "\\Y") return false; - RTLIL::SigSpec sig_a = assign_map(cellport.first->get("\\A")); - RTLIL::SigSpec sig_b = assign_map(cellport.first->get("\\B")); + RTLIL::SigSpec sig_a = assign_map(cellport.first->getPort("\\A")); + RTLIL::SigSpec sig_b = assign_map(cellport.first->getPort("\\B")); if (!check_state_mux_tree(old_sig, sig_a, recursion_monitor)) return false; for (int i = 0; i < sig_b.size(); i += sig_a.size()) @@ -80,14 +80,14 @@ static bool check_state_users(RTLIL::SigSpec sig) continue; if (cellport.second != "\\A" && cellport.second != "\\B") return false; - if (!cell->has("\\A") || !cell->has("\\B") || !cell->has("\\Y")) + if (!cell->hasPort("\\A") || !cell->hasPort("\\B") || !cell->hasPort("\\Y")) return false; for (auto &port_it : cell->connections()) if (port_it.first != "\\A" && port_it.first != "\\B" && port_it.first != "\\Y") return false; - if (assign_map(cell->get("\\A")) == sig && cell->get("\\B").is_fully_const()) + if (assign_map(cell->getPort("\\A")) == sig && cell->getPort("\\B").is_fully_const()) continue; - if (assign_map(cell->get("\\B")) == sig && cell->get("\\A").is_fully_const()) + if (assign_map(cell->getPort("\\B")) == sig && cell->getPort("\\A").is_fully_const()) continue; return false; } @@ -109,8 +109,8 @@ static void detect_fsm(RTLIL::Wire *wire) continue; muxtree_cells.clear(); SigPool recursion_monitor; - RTLIL::SigSpec sig_q = assign_map(cellport.first->get("\\Q")); - RTLIL::SigSpec sig_d = assign_map(cellport.first->get("\\D")); + RTLIL::SigSpec sig_q = assign_map(cellport.first->getPort("\\Q")); + RTLIL::SigSpec sig_d = assign_map(cellport.first->getPort("\\D")); if (sig_q == RTLIL::SigSpec(wire) && check_state_mux_tree(sig_q, sig_d, recursion_monitor) && check_state_users(sig_q)) { log("Found FSM state register %s in module %s.\n", wire->name.c_str(), module->name.c_str()); wire->attributes["\\fsm_encoding"] = RTLIL::Const("auto"); diff --git a/passes/fsm/fsm_expand.cc b/passes/fsm/fsm_expand.cc index 2da4794eb..670fae1d9 100644 --- a/passes/fsm/fsm_expand.cc +++ b/passes/fsm/fsm_expand.cc @@ -43,34 +43,34 @@ struct FsmExpand bool is_cell_merge_candidate(RTLIL::Cell *cell) { if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux") - if (cell->get("\\A").size() < 2) + if (cell->getPort("\\A").size() < 2) return true; RTLIL::SigSpec new_signals; - if (cell->has("\\A")) - new_signals.append(assign_map(cell->get("\\A"))); - if (cell->has("\\B")) - new_signals.append(assign_map(cell->get("\\B"))); - if (cell->has("\\S")) - new_signals.append(assign_map(cell->get("\\S"))); - if (cell->has("\\Y")) - new_signals.append(assign_map(cell->get("\\Y"))); + if (cell->hasPort("\\A")) + new_signals.append(assign_map(cell->getPort("\\A"))); + if (cell->hasPort("\\B")) + new_signals.append(assign_map(cell->getPort("\\B"))); + if (cell->hasPort("\\S")) + new_signals.append(assign_map(cell->getPort("\\S"))); + if (cell->hasPort("\\Y")) + new_signals.append(assign_map(cell->getPort("\\Y"))); new_signals.sort_and_unify(); new_signals.remove_const(); - new_signals.remove(assign_map(fsm_cell->get("\\CTRL_IN"))); - new_signals.remove(assign_map(fsm_cell->get("\\CTRL_OUT"))); + new_signals.remove(assign_map(fsm_cell->getPort("\\CTRL_IN"))); + new_signals.remove(assign_map(fsm_cell->getPort("\\CTRL_OUT"))); if (new_signals.size() > 3) return false; - if (cell->has("\\Y")) { - new_signals.append(assign_map(cell->get("\\Y"))); + if (cell->hasPort("\\Y")) { + new_signals.append(assign_map(cell->getPort("\\Y"))); new_signals.sort_and_unify(); new_signals.remove_const(); - new_signals.remove(assign_map(fsm_cell->get("\\CTRL_IN"))); - new_signals.remove(assign_map(fsm_cell->get("\\CTRL_OUT"))); + new_signals.remove(assign_map(fsm_cell->getPort("\\CTRL_IN"))); + new_signals.remove(assign_map(fsm_cell->getPort("\\CTRL_OUT"))); } if (new_signals.size() > 2) @@ -83,10 +83,10 @@ struct FsmExpand { std::vector cell_list; - for (auto c : sig2driver.find(assign_map(fsm_cell->get("\\CTRL_IN")))) + for (auto c : sig2driver.find(assign_map(fsm_cell->getPort("\\CTRL_IN")))) cell_list.push_back(c); - for (auto c : sig2user.find(assign_map(fsm_cell->get("\\CTRL_OUT")))) + for (auto c : sig2user.find(assign_map(fsm_cell->getPort("\\CTRL_OUT")))) cell_list.push_back(c); current_set.clear(); @@ -148,12 +148,12 @@ struct FsmExpand for (int i = 0; i < (1 << input_sig.size()); i++) { RTLIL::Const in_val(i, input_sig.size()); RTLIL::SigSpec A, B, S; - if (cell->has("\\A")) - A = assign_map(cell->get("\\A")); - if (cell->has("\\B")) - B = assign_map(cell->get("\\B")); - if (cell->has("\\S")) - S = assign_map(cell->get("\\S")); + if (cell->hasPort("\\A")) + A = assign_map(cell->getPort("\\A")); + if (cell->hasPort("\\B")) + B = assign_map(cell->getPort("\\B")); + if (cell->hasPort("\\S")) + S = assign_map(cell->getPort("\\S")); A.replace(input_sig, RTLIL::SigSpec(in_val)); B.replace(input_sig, RTLIL::SigSpec(in_val)); S.replace(input_sig, RTLIL::SigSpec(in_val)); @@ -167,14 +167,14 @@ struct FsmExpand fsm_data.copy_from_cell(fsm_cell); fsm_data.num_inputs += input_sig.size(); - RTLIL::SigSpec new_ctrl_in = fsm_cell->get("\\CTRL_IN"); + RTLIL::SigSpec new_ctrl_in = fsm_cell->getPort("\\CTRL_IN"); new_ctrl_in.append(input_sig); - fsm_cell->set("\\CTRL_IN", new_ctrl_in); + fsm_cell->setPort("\\CTRL_IN", new_ctrl_in); fsm_data.num_outputs += output_sig.size(); - RTLIL::SigSpec new_ctrl_out = fsm_cell->get("\\CTRL_OUT"); + RTLIL::SigSpec new_ctrl_out = fsm_cell->getPort("\\CTRL_OUT"); new_ctrl_out.append(output_sig); - fsm_cell->set("\\CTRL_OUT", new_ctrl_out); + fsm_cell->setPort("\\CTRL_OUT", new_ctrl_out); std::vector new_transition_table; for (auto &tr : fsm_data.transition_table) { diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index 718f779b6..cf2075fba 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -58,9 +58,9 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL log(" unexpected cell type %s (%s) found in state selection tree.\n", cell->type.c_str(), cell->name.c_str()); return false; } - RTLIL::SigSpec sig_a = assign_map(cell->get("\\A")); - RTLIL::SigSpec sig_b = assign_map(cell->get("\\B")); - RTLIL::SigSpec sig_s = assign_map(cell->get("\\S")); + RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A")); + RTLIL::SigSpec sig_b = assign_map(cell->getPort("\\B")); + RTLIL::SigSpec sig_s = assign_map(cell->getPort("\\S")); if (reset_state && RTLIL::SigSpec(*reset_state).is_fully_undef()) do { if (sig_a.is_fully_def()) @@ -183,12 +183,12 @@ static void extract_fsm(RTLIL::Wire *wire) if ((cell->type != "$dff" && cell->type != "$adff") || cellport.second != "\\Q") continue; log(" found %s cell for state register: %s\n", cell->type.c_str(), cell->name.c_str()); - RTLIL::SigSpec sig_q = assign_map(cell->get("\\Q")); - RTLIL::SigSpec sig_d = assign_map(cell->get("\\D")); - clk = cell->get("\\CLK"); + RTLIL::SigSpec sig_q = assign_map(cell->getPort("\\Q")); + RTLIL::SigSpec sig_d = assign_map(cell->getPort("\\D")); + clk = cell->getPort("\\CLK"); clk_polarity = cell->parameters["\\CLK_POLARITY"].as_bool(); if (cell->type == "$adff") { - arst = cell->get("\\ARST"); + arst = cell->getPort("\\ARST"); arst_polarity = cell->parameters["\\ARST_POLARITY"].as_bool(); reset_state = cell->parameters["\\ARST_VALUE"]; } @@ -224,9 +224,9 @@ static void extract_fsm(RTLIL::Wire *wire) sig2trigger.find(dff_out, cellport_list); for (auto &cellport : cellport_list) { RTLIL::Cell *cell = module->cells_.at(cellport.first); - RTLIL::SigSpec sig_a = assign_map(cell->get("\\A")); - RTLIL::SigSpec sig_b = assign_map(cell->get("\\B")); - RTLIL::SigSpec sig_y = assign_map(cell->get("\\Y")); + RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A")); + RTLIL::SigSpec sig_b = assign_map(cell->getPort("\\B")); + RTLIL::SigSpec sig_y = assign_map(cell->getPort("\\Y")); if (cellport.second == "\\A" && !sig_b.is_fully_const()) continue; if (cellport.second == "\\B" && !sig_a.is_fully_const()) @@ -271,12 +271,12 @@ static void extract_fsm(RTLIL::Wire *wire) // create fsm cell RTLIL::Cell *fsm_cell = module->addCell(stringf("$fsm$%s$%d", wire->name.c_str(), autoidx++), "$fsm"); - fsm_cell->set("\\CLK", clk); - fsm_cell->set("\\ARST", arst); + fsm_cell->setPort("\\CLK", clk); + fsm_cell->setPort("\\ARST", arst); fsm_cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity ? 1 : 0, 1); fsm_cell->parameters["\\ARST_POLARITY"] = RTLIL::Const(arst_polarity ? 1 : 0, 1); - fsm_cell->set("\\CTRL_IN", ctrl_in); - fsm_cell->set("\\CTRL_OUT", ctrl_out); + fsm_cell->setPort("\\CTRL_IN", ctrl_in); + fsm_cell->setPort("\\CTRL_OUT", ctrl_out); fsm_cell->parameters["\\NAME"] = RTLIL::Const(wire->name); fsm_cell->attributes = wire->attributes; fsm_data.copy_to_cell(fsm_cell); @@ -294,7 +294,7 @@ static void extract_fsm(RTLIL::Wire *wire) sig2driver.find(ctrl_out, cellport_list); for (auto &cellport : cellport_list) { RTLIL::Cell *cell = module->cells_.at(cellport.first); - RTLIL::SigSpec port_sig = assign_map(cell->get(cellport.second)); + RTLIL::SigSpec port_sig = assign_map(cell->getPort(cellport.second)); RTLIL::SigSpec unconn_sig = port_sig.extract(ctrl_out); RTLIL::Wire *unconn_wire = module->addWire(stringf("$fsm_unconnect$%s$%d", log_signal(unconn_sig), autoidx++), unconn_sig.size()); port_sig.replace(unconn_sig, RTLIL::SigSpec(unconn_wire), &cell->connections_[cellport.second]); @@ -347,8 +347,8 @@ struct FsmExtractPass : public Pass { assign_map.apply(sig); sig2driver.insert(sig, sig2driver_entry_t(cell_it.first, conn_it.first)); } - if (ct.cell_input(cell_it.second->type, conn_it.first) && cell_it.second->has("\\Y") && - cell_it.second->get("\\Y").size() == 1 && (conn_it.first == "\\A" || conn_it.first == "\\B")) { + if (ct.cell_input(cell_it.second->type, conn_it.first) && cell_it.second->hasPort("\\Y") && + cell_it.second->getPort("\\Y").size() == 1 && (conn_it.first == "\\A" || conn_it.first == "\\B")) { RTLIL::SigSpec sig = conn_it.second; assign_map.apply(sig); sig2trigger.insert(sig, sig2driver_entry_t(cell_it.first, conn_it.first)); diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc index 8b9ad6be7..99b736c1b 100644 --- a/passes/fsm/fsm_map.cc +++ b/passes/fsm/fsm_map.cc @@ -58,9 +58,9 @@ static void implement_pattern_cache(RTLIL::Module *module, std::mapaddCell(NEW_ID, "$eq"); - eq_cell->set("\\A", eq_sig_a); - eq_cell->set("\\B", eq_sig_b); - eq_cell->set("\\Y", RTLIL::SigSpec(eq_wire)); + eq_cell->setPort("\\A", eq_sig_a); + eq_cell->setPort("\\B", eq_sig_b); + eq_cell->setPort("\\Y", RTLIL::SigSpec(eq_wire)); eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false); eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false); eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(eq_sig_a.size()); @@ -80,8 +80,8 @@ static void implement_pattern_cache(RTLIL::Module *module, std::mapaddCell(NEW_ID, "$reduce_or"); - or_cell->set("\\A", or_sig); - or_cell->set("\\Y", RTLIL::SigSpec(or_wire)); + or_cell->setPort("\\A", or_sig); + or_cell->setPort("\\Y", RTLIL::SigSpec(or_wire)); or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false); or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(or_sig.size()); or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); @@ -96,9 +96,9 @@ static void implement_pattern_cache(RTLIL::Module *module, std::mapaddCell(NEW_ID, "$and"); - and_cell->set("\\A", and_sig.extract(0, 1)); - and_cell->set("\\B", and_sig.extract(1, 1)); - and_cell->set("\\Y", RTLIL::SigSpec(and_wire)); + and_cell->setPort("\\A", and_sig.extract(0, 1)); + and_cell->setPort("\\B", and_sig.extract(1, 1)); + and_cell->setPort("\\Y", RTLIL::SigSpec(and_wire)); and_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false); and_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false); and_cell->parameters["\\A_WIDTH"] = RTLIL::Const(1); @@ -119,8 +119,8 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map 1) { RTLIL::Cell *or_cell = module->addCell(NEW_ID, "$reduce_or"); - or_cell->set("\\A", cases_vector); - or_cell->set("\\Y", output); + or_cell->setPort("\\A", cases_vector); + or_cell->setPort("\\Y", output); or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false); or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cases_vector.size()); or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); @@ -138,8 +138,8 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) FsmData fsm_data; fsm_data.copy_from_cell(fsm_cell); - RTLIL::SigSpec ctrl_in = fsm_cell->get("\\CTRL_IN"); - RTLIL::SigSpec ctrl_out = fsm_cell->get("\\CTRL_OUT"); + RTLIL::SigSpec ctrl_in = fsm_cell->getPort("\\CTRL_IN"); + RTLIL::SigSpec ctrl_out = fsm_cell->getPort("\\CTRL_OUT"); // create state register @@ -151,7 +151,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) RTLIL::Wire *next_state_wire = module->addWire(NEW_ID, fsm_data.state_bits); RTLIL::Cell *state_dff = module->addCell(NEW_ID, ""); - if (fsm_cell->get("\\ARST").is_fully_const()) { + if (fsm_cell->getPort("\\ARST").is_fully_const()) { state_dff->type = "$dff"; } else { state_dff->type = "$adff"; @@ -160,13 +160,13 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) for (auto &bit : state_dff->parameters["\\ARST_VALUE"].bits) if (bit != RTLIL::State::S1) bit = RTLIL::State::S0; - state_dff->set("\\ARST", fsm_cell->get("\\ARST")); + state_dff->setPort("\\ARST", fsm_cell->getPort("\\ARST")); } state_dff->parameters["\\WIDTH"] = RTLIL::Const(fsm_data.state_bits); state_dff->parameters["\\CLK_POLARITY"] = fsm_cell->parameters["\\CLK_POLARITY"]; - state_dff->set("\\CLK", fsm_cell->get("\\CLK")); - state_dff->set("\\D", RTLIL::SigSpec(next_state_wire)); - state_dff->set("\\Q", RTLIL::SigSpec(state_wire)); + state_dff->setPort("\\CLK", fsm_cell->getPort("\\CLK")); + state_dff->setPort("\\D", RTLIL::SigSpec(next_state_wire)); + state_dff->setPort("\\Q", RTLIL::SigSpec(state_wire)); // decode state register @@ -194,9 +194,9 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) encoding_is_onehot = false; RTLIL::Cell *eq_cell = module->addCell(NEW_ID, "$eq"); - eq_cell->set("\\A", sig_a); - eq_cell->set("\\B", sig_b); - eq_cell->set("\\Y", RTLIL::SigSpec(state_onehot, i)); + eq_cell->setPort("\\A", sig_a); + eq_cell->setPort("\\B", sig_b); + eq_cell->setPort("\\Y", RTLIL::SigSpec(state_onehot, i)); eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false); eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false); eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_a.size()); @@ -260,10 +260,10 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) } RTLIL::Cell *mux_cell = module->addCell(NEW_ID, "$safe_pmux"); - mux_cell->set("\\A", sig_a); - mux_cell->set("\\B", sig_b); - mux_cell->set("\\S", sig_s); - mux_cell->set("\\Y", RTLIL::SigSpec(next_state_wire)); + mux_cell->setPort("\\A", sig_a); + mux_cell->setPort("\\B", sig_b); + mux_cell->setPort("\\S", sig_s); + mux_cell->setPort("\\Y", RTLIL::SigSpec(next_state_wire)); mux_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_a.size()); mux_cell->parameters["\\S_WIDTH"] = RTLIL::Const(sig_s.size()); } diff --git a/passes/fsm/fsm_opt.cc b/passes/fsm/fsm_opt.cc index 9d9156ae3..bcaa89bf0 100644 --- a/passes/fsm/fsm_opt.cc +++ b/passes/fsm/fsm_opt.cc @@ -52,7 +52,7 @@ struct FsmOpt void opt_const_and_unused_inputs() { - RTLIL::SigSpec ctrl_in = cell->get("\\CTRL_IN"); + RTLIL::SigSpec ctrl_in = cell->getPort("\\CTRL_IN"); std::vector ctrl_in_used(ctrl_in.size()); std::vector new_transition_table; @@ -73,15 +73,15 @@ struct FsmOpt for (int i = int(ctrl_in_used.size())-1; i >= 0; i--) { if (!ctrl_in_used[i]) { - log(" Removing unused input signal %s.\n", log_signal(cell->get("\\CTRL_IN").extract(i, 1))); + log(" Removing unused input signal %s.\n", log_signal(cell->getPort("\\CTRL_IN").extract(i, 1))); for (auto &tr : new_transition_table) { RTLIL::SigSpec tmp(tr.ctrl_in); tmp.remove(i, 1); tr.ctrl_in = tmp.as_const(); } - RTLIL::SigSpec new_ctrl_in = cell->get("\\CTRL_IN"); + RTLIL::SigSpec new_ctrl_in = cell->getPort("\\CTRL_IN"); new_ctrl_in.remove(i, 1); - cell->set("\\CTRL_IN", new_ctrl_in); + cell->setPort("\\CTRL_IN", new_ctrl_in); fsm_data.num_inputs--; } } @@ -93,12 +93,12 @@ struct FsmOpt void opt_unused_outputs() { for (int i = 0; i < fsm_data.num_outputs; i++) { - RTLIL::SigSpec sig = cell->get("\\CTRL_OUT").extract(i, 1); + RTLIL::SigSpec sig = cell->getPort("\\CTRL_OUT").extract(i, 1); if (signal_is_unused(sig)) { log(" Removing unused output signal %s.\n", log_signal(sig)); - RTLIL::SigSpec new_ctrl_out = cell->get("\\CTRL_OUT"); + RTLIL::SigSpec new_ctrl_out = cell->getPort("\\CTRL_OUT"); new_ctrl_out.remove(i, 1); - cell->set("\\CTRL_OUT", new_ctrl_out); + cell->setPort("\\CTRL_OUT", new_ctrl_out); for (auto &tr : fsm_data.transition_table) { RTLIL::SigSpec tmp(tr.ctrl_out); tmp.remove(i, 1); diff --git a/passes/fsm/fsmdata.h b/passes/fsm/fsmdata.h index 8f0e5d621..7a44dd452 100644 --- a/passes/fsm/fsmdata.h +++ b/passes/fsm/fsmdata.h @@ -141,13 +141,13 @@ struct FsmData log("\n"); log(" Input signals:\n"); - RTLIL::SigSpec sig_in = cell->get("\\CTRL_IN"); + RTLIL::SigSpec sig_in = cell->getPort("\\CTRL_IN"); for (int i = 0; i < SIZE(sig_in); i++) log(" %3d: %s\n", i, log_signal(sig_in[i])); log("\n"); log(" Output signals:\n"); - RTLIL::SigSpec sig_out = cell->get("\\CTRL_OUT"); + RTLIL::SigSpec sig_out = cell->getPort("\\CTRL_OUT"); for (int i = 0; i < SIZE(sig_out); i++) log(" %3d: %s\n", i, log_signal(sig_out[i])); diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index d0c9f4b5a..2a47002ef 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -185,7 +185,7 @@ struct SubmodWorker RTLIL::Wire *old_wire = it.first; RTLIL::Wire *new_wire = it.second.new_wire; if (new_wire->port_id > 0) - new_cell->set(new_wire->name, RTLIL::SigSpec(old_wire)); + new_cell->setPort(new_wire->name, RTLIL::SigSpec(old_wire)); } } diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc index aecb7bd6c..8887d1952 100644 --- a/passes/memory/memory_collect.cc +++ b/passes/memory/memory_collect.cc @@ -75,12 +75,12 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) wr_ports++; del_cells.push_back(cell); - RTLIL::SigSpec clk = cell->get("\\CLK"); + RTLIL::SigSpec clk = cell->getPort("\\CLK"); RTLIL::SigSpec clk_enable = RTLIL::SigSpec(cell->parameters["\\CLK_ENABLE"]); RTLIL::SigSpec clk_polarity = RTLIL::SigSpec(cell->parameters["\\CLK_POLARITY"]); - RTLIL::SigSpec addr = cell->get("\\ADDR"); - RTLIL::SigSpec data = cell->get("\\DATA"); - RTLIL::SigSpec en = cell->get("\\EN"); + RTLIL::SigSpec addr = cell->getPort("\\ADDR"); + RTLIL::SigSpec data = cell->getPort("\\DATA"); + RTLIL::SigSpec en = cell->getPort("\\EN"); clk.extend(1, false); clk_enable.extend(1, false); @@ -102,12 +102,12 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) rd_ports++; del_cells.push_back(cell); - RTLIL::SigSpec clk = cell->get("\\CLK"); + RTLIL::SigSpec clk = cell->getPort("\\CLK"); RTLIL::SigSpec clk_enable = RTLIL::SigSpec(cell->parameters["\\CLK_ENABLE"]); RTLIL::SigSpec clk_polarity = RTLIL::SigSpec(cell->parameters["\\CLK_POLARITY"]); RTLIL::SigSpec transparent = RTLIL::SigSpec(cell->parameters["\\TRANSPARENT"]); - RTLIL::SigSpec addr = cell->get("\\ADDR"); - RTLIL::SigSpec data = cell->get("\\DATA"); + RTLIL::SigSpec addr = cell->getPort("\\ADDR"); + RTLIL::SigSpec data = cell->getPort("\\DATA"); clk.extend(1, false); clk_enable.extend(1, false); @@ -146,10 +146,10 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) mem->parameters["\\WR_CLK_ENABLE"] = wr_ports ? sig_wr_clk_enable.as_const() : RTLIL::Const(0, 0); mem->parameters["\\WR_CLK_POLARITY"] = wr_ports ? sig_wr_clk_polarity.as_const() : RTLIL::Const(0, 0); - mem->set("\\WR_CLK", sig_wr_clk); - mem->set("\\WR_ADDR", sig_wr_addr); - mem->set("\\WR_DATA", sig_wr_data); - mem->set("\\WR_EN", sig_wr_en); + mem->setPort("\\WR_CLK", sig_wr_clk); + mem->setPort("\\WR_ADDR", sig_wr_addr); + mem->setPort("\\WR_DATA", sig_wr_data); + mem->setPort("\\WR_EN", sig_wr_en); log_assert(sig_rd_clk.size() == rd_ports); log_assert(sig_rd_clk_enable.size() == rd_ports && sig_rd_clk_enable.is_fully_const()); @@ -162,9 +162,9 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) mem->parameters["\\RD_CLK_POLARITY"] = rd_ports ? sig_rd_clk_polarity.as_const() : RTLIL::Const(0, 0); mem->parameters["\\RD_TRANSPARENT"] = rd_ports ? sig_rd_transparent.as_const() : RTLIL::Const(0, 0); - mem->set("\\RD_CLK", sig_rd_clk); - mem->set("\\RD_ADDR", sig_rd_addr); - mem->set("\\RD_DATA", sig_rd_data); + mem->setPort("\\RD_CLK", sig_rd_clk); + mem->setPort("\\RD_ADDR", sig_rd_addr); + mem->setPort("\\RD_DATA", sig_rd_data); for (auto c : del_cells) module->remove(c); diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index 6cbce781f..e92d726cc 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -43,21 +43,21 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI continue; if (clk != RTLIL::SigSpec(RTLIL::State::Sx)) { - if (cell->get("\\CLK") != clk) + if (cell->getPort("\\CLK") != clk) continue; if (cell->parameters["\\CLK_POLARITY"].as_bool() != clk_polarity) continue; } - RTLIL::SigSpec q_norm = cell->get(after ? "\\D" : "\\Q"); + RTLIL::SigSpec q_norm = cell->getPort(after ? "\\D" : "\\Q"); normalize_sig(module, q_norm); - RTLIL::SigSpec d = q_norm.extract(bit, &cell->get(after ? "\\Q" : "\\D")); + RTLIL::SigSpec d = q_norm.extract(bit, &cell->getPort(after ? "\\Q" : "\\D")); if (d.size() != 1) continue; bit = d; - clk = cell->get("\\CLK"); + clk = cell->getPort("\\CLK"); clk_polarity = cell->parameters["\\CLK_POLARITY"].as_bool(); goto replaced_this_bit; } @@ -76,29 +76,29 @@ static void handle_wr_cell(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::SigSpec clk = RTLIL::SigSpec(RTLIL::State::Sx); bool clk_polarity = 0; - RTLIL::SigSpec sig_addr = cell->get("\\ADDR"); + RTLIL::SigSpec sig_addr = cell->getPort("\\ADDR"); if (!find_sig_before_dff(module, sig_addr, clk, clk_polarity)) { log("no (compatible) $dff for address input found.\n"); return; } - RTLIL::SigSpec sig_data = cell->get("\\DATA"); + RTLIL::SigSpec sig_data = cell->getPort("\\DATA"); if (!find_sig_before_dff(module, sig_data, clk, clk_polarity)) { log("no (compatible) $dff for data input found.\n"); return; } - RTLIL::SigSpec sig_en = cell->get("\\EN"); + RTLIL::SigSpec sig_en = cell->getPort("\\EN"); if (!find_sig_before_dff(module, sig_en, clk, clk_polarity)) { log("no (compatible) $dff for enable input found.\n"); return; } if (clk != RTLIL::SigSpec(RTLIL::State::Sx)) { - cell->set("\\CLK", clk); - cell->set("\\ADDR", sig_addr); - cell->set("\\DATA", sig_data); - cell->set("\\EN", sig_en); + cell->setPort("\\CLK", clk); + cell->setPort("\\ADDR", sig_addr); + cell->setPort("\\DATA", sig_data); + cell->setPort("\\EN", sig_en); cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1); cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity); log("merged $dff to cell.\n"); @@ -119,9 +119,9 @@ static void disconnect_dff(RTLIL::Module *module, RTLIL::SigSpec sig) for (auto cell : module->cells()) if (cell->type == "$dff") { - RTLIL::SigSpec new_q = cell->get("\\Q"); + RTLIL::SigSpec new_q = cell->getPort("\\Q"); new_q.replace(sig, new_sig); - cell->set("\\Q", new_q); + cell->setPort("\\Q", new_q); } } @@ -132,13 +132,13 @@ static void handle_rd_cell(RTLIL::Module *module, RTLIL::Cell *cell) bool clk_polarity = 0; RTLIL::SigSpec clk_data = RTLIL::SigSpec(RTLIL::State::Sx); - RTLIL::SigSpec sig_data = cell->get("\\DATA"); + RTLIL::SigSpec sig_data = cell->getPort("\\DATA"); if (find_sig_before_dff(module, sig_data, clk_data, clk_polarity, true) && clk_data != RTLIL::SigSpec(RTLIL::State::Sx)) { disconnect_dff(module, sig_data); - cell->set("\\CLK", clk_data); - cell->set("\\DATA", sig_data); + cell->setPort("\\CLK", clk_data); + cell->setPort("\\DATA", sig_data); cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1); cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity); cell->parameters["\\TRANSPARENT"] = RTLIL::Const(0); @@ -147,12 +147,12 @@ static void handle_rd_cell(RTLIL::Module *module, RTLIL::Cell *cell) } RTLIL::SigSpec clk_addr = RTLIL::SigSpec(RTLIL::State::Sx); - RTLIL::SigSpec sig_addr = cell->get("\\ADDR"); + RTLIL::SigSpec sig_addr = cell->getPort("\\ADDR"); if (find_sig_before_dff(module, sig_addr, clk_addr, clk_polarity) && clk_addr != RTLIL::SigSpec(RTLIL::State::Sx)) { - cell->set("\\CLK", clk_addr); - cell->set("\\ADDR", sig_addr); + cell->setPort("\\CLK", clk_addr); + cell->setPort("\\ADDR", sig_addr); cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1); cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity); cell->parameters["\\TRANSPARENT"] = RTLIL::Const(1); diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index 0000bd507..f1917b972 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -61,20 +61,20 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) } // all write ports must share the same clock - RTLIL::SigSpec clocks = cell->get("\\WR_CLK"); + RTLIL::SigSpec clocks = cell->getPort("\\WR_CLK"); RTLIL::Const clocks_pol = cell->parameters["\\WR_CLK_POLARITY"]; RTLIL::Const clocks_en = cell->parameters["\\WR_CLK_ENABLE"]; RTLIL::SigSpec refclock; RTLIL::State refclock_pol = RTLIL::State::Sx; for (int i = 0; i < clocks.size(); i++) { - RTLIL::SigSpec wr_en = cell->get("\\WR_EN").extract(i * mem_width, mem_width); + RTLIL::SigSpec wr_en = cell->getPort("\\WR_EN").extract(i * mem_width, mem_width); if (wr_en.is_fully_const() && !wr_en.as_bool()) { static_ports.insert(i); continue; } if (clocks_en.bits[i] != RTLIL::State::S1) { - RTLIL::SigSpec wr_addr = cell->get("\\WR_ADDR").extract(i*mem_abits, mem_abits); - RTLIL::SigSpec wr_data = cell->get("\\WR_DATA").extract(i*mem_width, mem_width); + RTLIL::SigSpec wr_addr = cell->getPort("\\WR_ADDR").extract(i*mem_abits, mem_abits); + RTLIL::SigSpec wr_data = cell->getPort("\\WR_DATA").extract(i*mem_width, mem_width); if (wr_addr.is_fully_const()) { // FIXME: Actually we should check for wr_en.is_fully_const() also and // create a $adff cell with this ports wr_en input as reset pin when wr_en @@ -119,15 +119,15 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"]; if (clocks_pol.bits.size() > 0) { c->parameters["\\CLK_POLARITY"] = RTLIL::Const(clocks_pol.bits[0]); - c->set("\\CLK", clocks.extract(0, 1)); + c->setPort("\\CLK", clocks.extract(0, 1)); } else { c->parameters["\\CLK_POLARITY"] = RTLIL::Const(RTLIL::State::S1); - c->set("\\CLK", RTLIL::SigSpec(RTLIL::State::S0)); + c->setPort("\\CLK", RTLIL::SigSpec(RTLIL::State::S0)); } RTLIL::Wire *w_in = module->addWire(genid(cell->name, "", i, "$d"), mem_width); data_reg_in.push_back(RTLIL::SigSpec(w_in)); - c->set("\\D", data_reg_in.back()); + c->setPort("\\D", data_reg_in.back()); std::string w_out_name = stringf("%s[%d]", cell->parameters["\\MEMID"].decode_string().c_str(), i); if (module->wires_.count(w_out_name) > 0) @@ -137,7 +137,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) w_out->start_offset = mem_offset; data_reg_out.push_back(RTLIL::SigSpec(w_out)); - c->set("\\Q", data_reg_out.back()); + c->setPort("\\Q", data_reg_out.back()); } } @@ -147,10 +147,10 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) for (int i = 0; i < cell->parameters["\\RD_PORTS"].as_int(); i++) { - RTLIL::SigSpec rd_addr = cell->get("\\RD_ADDR").extract(i*mem_abits, mem_abits); + RTLIL::SigSpec rd_addr = cell->getPort("\\RD_ADDR").extract(i*mem_abits, mem_abits); std::vector rd_signals; - rd_signals.push_back(cell->get("\\RD_DATA").extract(i*mem_width, mem_width)); + rd_signals.push_back(cell->getPort("\\RD_DATA").extract(i*mem_width, mem_width)); if (cell->parameters["\\RD_CLK_ENABLE"].bits[i] == RTLIL::State::S1) { @@ -159,13 +159,13 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdreg", i), "$dff"); c->parameters["\\WIDTH"] = RTLIL::Const(mem_abits); c->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]); - c->set("\\CLK", cell->get("\\RD_CLK").extract(i, 1)); - c->set("\\D", rd_addr); + c->setPort("\\CLK", cell->getPort("\\RD_CLK").extract(i, 1)); + c->setPort("\\D", rd_addr); count_dff++; RTLIL::Wire *w = module->addWire(genid(cell->name, "$rdreg", i, "$q"), mem_abits); - c->set("\\Q", RTLIL::SigSpec(w)); + c->setPort("\\Q", RTLIL::SigSpec(w)); rd_addr = RTLIL::SigSpec(w); } else @@ -173,15 +173,15 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdreg", i), "$dff"); c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"]; c->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]); - c->set("\\CLK", cell->get("\\RD_CLK").extract(i, 1)); - c->set("\\Q", rd_signals.back()); + c->setPort("\\CLK", cell->getPort("\\RD_CLK").extract(i, 1)); + c->setPort("\\Q", rd_signals.back()); count_dff++; RTLIL::Wire *w = module->addWire(genid(cell->name, "$rdreg", i, "$d"), mem_width); rd_signals.clear(); rd_signals.push_back(RTLIL::SigSpec(w)); - c->set("\\D", rd_signals.back()); + c->setPort("\\D", rd_signals.back()); } } @@ -193,15 +193,15 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) { RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdmux", i, "", j, "", k), "$mux"); c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"]; - c->set("\\Y", rd_signals[k]); - c->set("\\S", rd_addr.extract(mem_abits-j-1, 1)); + c->setPort("\\Y", rd_signals[k]); + c->setPort("\\S", rd_addr.extract(mem_abits-j-1, 1)); count_mux++; - c->set("\\A", module->addWire(genid(cell->name, "$rdmux", i, "", j, "", k, "$a"), mem_width)); - c->set("\\B", module->addWire(genid(cell->name, "$rdmux", i, "", j, "", k, "$b"), mem_width)); + c->setPort("\\A", module->addWire(genid(cell->name, "$rdmux", i, "", j, "", k, "$a"), mem_width)); + c->setPort("\\B", module->addWire(genid(cell->name, "$rdmux", i, "", j, "", k, "$b"), mem_width)); - next_rd_signals.push_back(c->get("\\A")); - next_rd_signals.push_back(c->get("\\B")); + next_rd_signals.push_back(c->getPort("\\A")); + next_rd_signals.push_back(c->getPort("\\B")); } next_rd_signals.swap(rd_signals); @@ -222,9 +222,9 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) for (int j = 0; j < cell->parameters["\\WR_PORTS"].as_int(); j++) { - RTLIL::SigSpec wr_addr = cell->get("\\WR_ADDR").extract(j*mem_abits, mem_abits); - RTLIL::SigSpec wr_data = cell->get("\\WR_DATA").extract(j*mem_width, mem_width); - RTLIL::SigSpec wr_en = cell->get("\\WR_EN").extract(j*mem_width, mem_width); + RTLIL::SigSpec wr_addr = cell->getPort("\\WR_ADDR").extract(j*mem_abits, mem_abits); + RTLIL::SigSpec wr_data = cell->getPort("\\WR_DATA").extract(j*mem_width, mem_width); + RTLIL::SigSpec wr_en = cell->getPort("\\WR_EN").extract(j*mem_width, mem_width); RTLIL::Cell *c = module->addCell(genid(cell->name, "$wreq", i, "", j), "$eq"); c->parameters["\\A_SIGNED"] = RTLIL::Const(0); @@ -232,12 +232,12 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) c->parameters["\\A_WIDTH"] = cell->parameters["\\ABITS"]; c->parameters["\\B_WIDTH"] = cell->parameters["\\ABITS"]; c->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - c->set("\\A", RTLIL::SigSpec(i, mem_abits)); - c->set("\\B", wr_addr); + c->setPort("\\A", RTLIL::SigSpec(i, mem_abits)); + c->setPort("\\B", wr_addr); count_wrmux++; RTLIL::Wire *w_seladdr = module->addWire(genid(cell->name, "$wreq", i, "", j, "$y")); - c->set("\\Y", w_seladdr); + c->setPort("\\Y", w_seladdr); int wr_offset = 0; while (wr_offset < wr_en.size()) @@ -262,21 +262,21 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) c->parameters["\\A_WIDTH"] = RTLIL::Const(1); c->parameters["\\B_WIDTH"] = RTLIL::Const(1); c->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - c->set("\\A", w); - c->set("\\B", wr_bit); + c->setPort("\\A", w); + c->setPort("\\B", wr_bit); w = module->addWire(genid(cell->name, "$wren", i, "", j, "", wr_offset, "$y")); - c->set("\\Y", RTLIL::SigSpec(w)); + c->setPort("\\Y", RTLIL::SigSpec(w)); } c = module->addCell(genid(cell->name, "$wrmux", i, "", j, "", wr_offset), "$mux"); c->parameters["\\WIDTH"] = wr_width; - c->set("\\A", sig.extract(wr_offset, wr_width)); - c->set("\\B", wr_data.extract(wr_offset, wr_width)); - c->set("\\S", RTLIL::SigSpec(w)); + c->setPort("\\A", sig.extract(wr_offset, wr_width)); + c->setPort("\\B", wr_data.extract(wr_offset, wr_width)); + c->setPort("\\S", RTLIL::SigSpec(w)); w = module->addWire(genid(cell->name, "$wrmux", i, "", j, "", wr_offset, "$y"), wr_width); - c->set("\\Y", w); + c->setPort("\\Y", w); sig.replace(wr_offset, w); wr_offset += wr_width; diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index b1629b7c4..b6e7cc835 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -64,18 +64,18 @@ struct MemoryShareWorker RTLIL::Cell *cell = sig_to_mux.at(sig).first; int bit_idx = sig_to_mux.at(sig).second; - std::vector sig_a = sigmap(cell->get("\\A")); - std::vector sig_b = sigmap(cell->get("\\B")); - std::vector sig_s = sigmap(cell->get("\\S")); - std::vector sig_y = sigmap(cell->get("\\Y")); + std::vector sig_a = sigmap(cell->getPort("\\A")); + std::vector sig_b = sigmap(cell->getPort("\\B")); + std::vector sig_s = sigmap(cell->getPort("\\S")); + std::vector sig_y = sigmap(cell->getPort("\\Y")); log_assert(sig_y.at(bit_idx) == sig); for (int i = 0; i < int(sig_s.size()); i++) if (state.count(sig_s[i]) && state.at(sig_s[i]) == true) { if (find_data_feedback(async_rd_bits, sig_b.at(bit_idx + i*sig_y.size()), state, conditions)) { - RTLIL::SigSpec new_b = cell->get("\\B"); + RTLIL::SigSpec new_b = cell->getPort("\\B"); new_b.replace(bit_idx + i*sig_y.size(), RTLIL::State::Sx); - cell->set("\\B", new_b); + cell->setPort("\\B", new_b); } return false; } @@ -90,9 +90,9 @@ struct MemoryShareWorker new_state[sig_s[i]] = true; if (find_data_feedback(async_rd_bits, sig_b.at(bit_idx + i*sig_y.size()), new_state, conditions)) { - RTLIL::SigSpec new_b = cell->get("\\B"); + RTLIL::SigSpec new_b = cell->getPort("\\B"); new_b.replace(bit_idx + i*sig_y.size(), RTLIL::State::Sx); - cell->set("\\B", new_b); + cell->setPort("\\B", new_b); } } @@ -101,9 +101,9 @@ struct MemoryShareWorker new_state[sig_s[i]] = false; if (find_data_feedback(async_rd_bits, sig_a.at(bit_idx), new_state, conditions)) { - RTLIL::SigSpec new_a = cell->get("\\A"); + RTLIL::SigSpec new_a = cell->getPort("\\A"); new_a.replace(bit_idx, RTLIL::State::Sx); - cell->set("\\A", new_a); + cell->setPort("\\A", new_a); } return false; @@ -150,10 +150,10 @@ struct MemoryShareWorker if (cell->type == "$mux" || cell->type == "$pmux") { - std::vector sig_a = sigmap(cell->get("\\A")); - std::vector sig_b = sigmap(cell->get("\\B")); - std::vector sig_s = sigmap(cell->get("\\S")); - std::vector sig_y = sigmap(cell->get("\\Y")); + std::vector sig_a = sigmap(cell->getPort("\\A")); + std::vector sig_b = sigmap(cell->getPort("\\B")); + std::vector sig_s = sigmap(cell->getPort("\\S")); + std::vector sig_y = sigmap(cell->getPort("\\Y")); non_feedback_nets.insert(sig_s.begin(), sig_s.end()); @@ -200,8 +200,8 @@ struct MemoryShareWorker if (cell->parameters.at("\\CLK_ENABLE").as_bool()) continue; - RTLIL::SigSpec sig_addr = sigmap(cell->get("\\ADDR")); - std::vector sig_data = sigmap(cell->get("\\DATA")); + RTLIL::SigSpec sig_addr = sigmap(cell->getPort("\\ADDR")); + std::vector sig_data = sigmap(cell->getPort("\\DATA")); for (int i = 0; i < int(sig_data.size()); i++) if (non_feedback_nets.count(sig_data[i])) @@ -221,14 +221,14 @@ struct MemoryShareWorker for (auto cell : wr_ports) { - RTLIL::SigSpec sig_addr = sigmap_xmux(cell->get("\\ADDR")); + RTLIL::SigSpec sig_addr = sigmap_xmux(cell->getPort("\\ADDR")); if (!async_rd_bits.count(sig_addr)) continue; log(" Analyzing write port %s.\n", log_id(cell)); - std::vector cell_data = cell->get("\\DATA"); - std::vector cell_en = cell->get("\\EN"); + std::vector cell_data = cell->getPort("\\DATA"); + std::vector cell_en = cell->getPort("\\EN"); int created_conditions = 0; for (int i = 0; i < int(cell_data.size()); i++) @@ -248,7 +248,7 @@ struct MemoryShareWorker if (created_conditions) { log(" Added enable logic for %d different cases.\n", created_conditions); - cell->set("\\EN", cell_en); + cell->setPort("\\EN", cell_en); } } } @@ -366,15 +366,15 @@ struct MemoryShareWorker for (int i = 0; i < int(wr_ports.size()); i++) { RTLIL::Cell *cell = wr_ports.at(i); - RTLIL::SigSpec addr = sigmap_xmux(cell->get("\\ADDR")); + RTLIL::SigSpec addr = sigmap_xmux(cell->getPort("\\ADDR")); if (cell->parameters.at("\\CLK_ENABLE").as_bool() != cache_clk_enable || - (cache_clk_enable && (sigmap(cell->get("\\CLK")) != cache_clk || + (cache_clk_enable && (sigmap(cell->getPort("\\CLK")) != cache_clk || cell->parameters.at("\\CLK_POLARITY").as_bool() != cache_clk_polarity))) { cache_clk_enable = cell->parameters.at("\\CLK_ENABLE").as_bool(); cache_clk_polarity = cell->parameters.at("\\CLK_POLARITY").as_bool(); - cache_clk = sigmap(cell->get("\\CLK")); + cache_clk = sigmap(cell->getPort("\\CLK")); last_port_by_addr.clear(); if (cache_clk_enable) @@ -386,7 +386,7 @@ struct MemoryShareWorker log(" Port %d (%s) has addr %s.\n", i, log_id(cell), log_signal(addr)); log(" Active bits: "); - std::vector en_bits = sigmap(cell->get("\\EN")); + std::vector en_bits = sigmap(cell->getPort("\\EN")); active_bits_on_port.push_back(std::vector(en_bits.size())); for (int k = int(en_bits.size())-1; k >= 0; k--) { active_bits_on_port[i][k] = en_bits[k].wire != NULL || en_bits[k].data != RTLIL::State::S0; @@ -408,13 +408,13 @@ struct MemoryShareWorker // Force this ports addr input to addr directly (skip don't care muxes) - cell->set("\\ADDR", addr); + cell->setPort("\\ADDR", addr); // If any of the ports between `last_i' and `i' write to the same address, this // will have priority over whatever `last_i` wrote. So we need to revisit those // ports and mask the EN bits accordingly. - RTLIL::SigSpec merged_en = sigmap(wr_ports[last_i]->get("\\EN")); + RTLIL::SigSpec merged_en = sigmap(wr_ports[last_i]->getPort("\\EN")); for (int j = last_i+1; j < i; j++) { @@ -429,20 +429,20 @@ struct MemoryShareWorker found_overlapping_bits_i_j: log(" Creating collosion-detect logic for port %d.\n", j); RTLIL::SigSpec is_same_addr = module->addWire(NEW_ID); - module->addEq(NEW_ID, addr, wr_ports[j]->get("\\ADDR"), is_same_addr); - merged_en = mask_en_grouped(is_same_addr, merged_en, sigmap(wr_ports[j]->get("\\EN"))); + module->addEq(NEW_ID, addr, wr_ports[j]->getPort("\\ADDR"), is_same_addr); + merged_en = mask_en_grouped(is_same_addr, merged_en, sigmap(wr_ports[j]->getPort("\\EN"))); } } // Then we need to merge the (masked) EN and the DATA signals. - RTLIL::SigSpec merged_data = wr_ports[last_i]->get("\\DATA"); + RTLIL::SigSpec merged_data = wr_ports[last_i]->getPort("\\DATA"); if (found_overlapping_bits) { log(" Creating logic for merging DATA and EN ports.\n"); - merge_en_data(merged_en, merged_data, sigmap(cell->get("\\EN")), sigmap(cell->get("\\DATA"))); + merge_en_data(merged_en, merged_data, sigmap(cell->getPort("\\EN")), sigmap(cell->getPort("\\DATA"))); } else { - RTLIL::SigSpec cell_en = sigmap(cell->get("\\EN")); - RTLIL::SigSpec cell_data = sigmap(cell->get("\\DATA")); + RTLIL::SigSpec cell_en = sigmap(cell->getPort("\\EN")); + RTLIL::SigSpec cell_data = sigmap(cell->getPort("\\DATA")); for (int k = 0; k < int(en_bits.size()); k++) if (!active_bits_on_port[last_i][k]) { merged_en.replace(k, cell_en.extract(k, 1)); @@ -452,14 +452,14 @@ struct MemoryShareWorker // Connect the new EN and DATA signals and remove the old write port. - cell->set("\\EN", merged_en); - cell->set("\\DATA", merged_data); + cell->setPort("\\EN", merged_en); + cell->setPort("\\DATA", merged_data); module->remove(wr_ports[last_i]); wr_ports[last_i] = NULL; log(" Active bits: "); - std::vector en_bits = sigmap(cell->get("\\EN")); + std::vector en_bits = sigmap(cell->getPort("\\EN")); active_bits_on_port.push_back(std::vector(en_bits.size())); for (int k = int(en_bits.size())-1; k >= 0; k--) log("%c", active_bits_on_port[i][k] ? '1' : '0'); @@ -498,7 +498,7 @@ struct MemoryShareWorker std::set considered_port_pairs; for (int i = 0; i < int(wr_ports.size()); i++) { - std::vector bits = modwalker.sigmap(wr_ports[i]->get("\\EN")); + std::vector bits = modwalker.sigmap(wr_ports[i]->getPort("\\EN")); for (auto bit : bits) if (bit == RTLIL::State::S1) goto port_is_always_active; @@ -518,12 +518,12 @@ struct MemoryShareWorker RTLIL::Cell *cell = wr_ports.at(i); if (cell->parameters.at("\\CLK_ENABLE").as_bool() != cache_clk_enable || - (cache_clk_enable && (sigmap(cell->get("\\CLK")) != cache_clk || + (cache_clk_enable && (sigmap(cell->getPort("\\CLK")) != cache_clk || cell->parameters.at("\\CLK_POLARITY").as_bool() != cache_clk_polarity))) { cache_clk_enable = cell->parameters.at("\\CLK_ENABLE").as_bool(); cache_clk_polarity = cell->parameters.at("\\CLK_POLARITY").as_bool(); - cache_clk = sigmap(cell->get("\\CLK")); + cache_clk = sigmap(cell->getPort("\\CLK")); } else if (i > 0 && considered_ports.count(i-1) && considered_ports.count(i)) considered_port_pairs.insert(i); @@ -551,7 +551,7 @@ struct MemoryShareWorker for (int i = 0; i < int(wr_ports.size()); i++) if (considered_port_pairs.count(i) || considered_port_pairs.count(i+1)) { - RTLIL::SigSpec sig = modwalker.sigmap(wr_ports[i]->get("\\EN")); + RTLIL::SigSpec sig = modwalker.sigmap(wr_ports[i]->getPort("\\EN")); port_to_sat_variable[i] = ez.expression(ez.OpOr, satgen.importSigSpec(sig)); std::vector bits = sig; @@ -594,18 +594,18 @@ struct MemoryShareWorker log(" Merging port %d into port %d.\n", i-1, i); port_to_sat_variable.at(i) = ez.OR(port_to_sat_variable.at(i-1), port_to_sat_variable.at(i)); - RTLIL::SigSpec last_addr = wr_ports[i-1]->get("\\ADDR"); - RTLIL::SigSpec last_data = wr_ports[i-1]->get("\\DATA"); - std::vector last_en = modwalker.sigmap(wr_ports[i-1]->get("\\EN")); + RTLIL::SigSpec last_addr = wr_ports[i-1]->getPort("\\ADDR"); + RTLIL::SigSpec last_data = wr_ports[i-1]->getPort("\\DATA"); + std::vector last_en = modwalker.sigmap(wr_ports[i-1]->getPort("\\EN")); - RTLIL::SigSpec this_addr = wr_ports[i]->get("\\ADDR"); - RTLIL::SigSpec this_data = wr_ports[i]->get("\\DATA"); - std::vector this_en = modwalker.sigmap(wr_ports[i]->get("\\EN")); + RTLIL::SigSpec this_addr = wr_ports[i]->getPort("\\ADDR"); + RTLIL::SigSpec this_data = wr_ports[i]->getPort("\\DATA"); + std::vector this_en = modwalker.sigmap(wr_ports[i]->getPort("\\EN")); RTLIL::SigBit this_en_active = module->ReduceOr(NEW_ID, this_en); - wr_ports[i]->set("\\ADDR", module->Mux(NEW_ID, last_addr, this_addr, this_en_active)); - wr_ports[i]->set("\\DATA", module->Mux(NEW_ID, last_data, this_data, this_en_active)); + wr_ports[i]->setPort("\\ADDR", module->Mux(NEW_ID, last_addr, this_addr, this_en_active)); + wr_ports[i]->setPort("\\DATA", module->Mux(NEW_ID, last_data, this_data, this_en_active)); std::map, int> groups_en; RTLIL::SigSpec grouped_last_en, grouped_this_en, en; @@ -623,7 +623,7 @@ struct MemoryShareWorker } module->addMux(NEW_ID, grouped_last_en, grouped_this_en, this_en_active, grouped_en); - wr_ports[i]->set("\\EN", en); + wr_ports[i]->setPort("\\EN", en); module->remove(wr_ports[i-1]); wr_ports[i-1] = NULL; @@ -662,18 +662,18 @@ struct MemoryShareWorker if (cell->type == "$mux") { - RTLIL::SigSpec sig_a = sigmap_xmux(cell->get("\\A")); - RTLIL::SigSpec sig_b = sigmap_xmux(cell->get("\\B")); + RTLIL::SigSpec sig_a = sigmap_xmux(cell->getPort("\\A")); + RTLIL::SigSpec sig_b = sigmap_xmux(cell->getPort("\\B")); if (sig_a.is_fully_undef()) - sigmap_xmux.add(cell->get("\\Y"), sig_b); + sigmap_xmux.add(cell->getPort("\\Y"), sig_b); else if (sig_b.is_fully_undef()) - sigmap_xmux.add(cell->get("\\Y"), sig_a); + sigmap_xmux.add(cell->getPort("\\Y"), sig_a); } if (cell->type == "$mux" || cell->type == "$pmux") { - std::vector sig_y = sigmap(cell->get("\\Y")); + std::vector sig_y = sigmap(cell->getPort("\\Y")); for (int i = 0; i < int(sig_y.size()); i++) sig_to_mux[sig_y[i]] = std::pair(cell, i); } diff --git a/passes/memory/memory_unpack.cc b/passes/memory/memory_unpack.cc index 3f675edea..68e9a9697 100644 --- a/passes/memory/memory_unpack.cc +++ b/passes/memory/memory_unpack.cc @@ -53,9 +53,9 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory) cell->parameters["\\CLK_ENABLE"] = RTLIL::SigSpec(memory->parameters.at("\\RD_CLK_ENABLE")).extract(i, 1).as_const(); cell->parameters["\\CLK_POLARITY"] = RTLIL::SigSpec(memory->parameters.at("\\RD_CLK_POLARITY")).extract(i, 1).as_const(); cell->parameters["\\TRANSPARENT"] = RTLIL::SigSpec(memory->parameters.at("\\RD_TRANSPARENT")).extract(i, 1).as_const(); - cell->set("\\CLK", memory->get("\\RD_CLK").extract(i, 1)); - cell->set("\\ADDR", memory->get("\\RD_ADDR").extract(i*abits, abits)); - cell->set("\\DATA", memory->get("\\RD_DATA").extract(i*mem->width, mem->width)); + cell->setPort("\\CLK", memory->getPort("\\RD_CLK").extract(i, 1)); + cell->setPort("\\ADDR", memory->getPort("\\RD_ADDR").extract(i*abits, abits)); + cell->setPort("\\DATA", memory->getPort("\\RD_DATA").extract(i*mem->width, mem->width)); } for (int i = 0; i < num_wr_ports; i++) @@ -67,10 +67,10 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory) cell->parameters["\\CLK_ENABLE"] = RTLIL::SigSpec(memory->parameters.at("\\WR_CLK_ENABLE")).extract(i, 1).as_const(); cell->parameters["\\CLK_POLARITY"] = RTLIL::SigSpec(memory->parameters.at("\\WR_CLK_POLARITY")).extract(i, 1).as_const(); cell->parameters["\\PRIORITY"] = i; - cell->set("\\CLK", memory->get("\\WR_CLK").extract(i, 1)); - cell->set("\\EN", memory->get("\\WR_EN").extract(i*mem->width, mem->width)); - cell->set("\\ADDR", memory->get("\\WR_ADDR").extract(i*abits, abits)); - cell->set("\\DATA", memory->get("\\WR_DATA").extract(i*mem->width, mem->width)); + cell->setPort("\\CLK", memory->getPort("\\WR_CLK").extract(i, 1)); + cell->setPort("\\EN", memory->getPort("\\WR_EN").extract(i*mem->width, mem->width)); + cell->setPort("\\ADDR", memory->getPort("\\WR_ADDR").extract(i*abits, abits)); + cell->setPort("\\DATA", memory->getPort("\\WR_DATA").extract(i*mem->width, mem->width)); } module->remove(memory); diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index 3e7487c39..5dab5ecab 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -73,7 +73,7 @@ static void replace_undriven(RTLIL::Design *design, RTLIL::Module *module) static void replace_cell(SigMap &assign_map, RTLIL::Module *module, RTLIL::Cell *cell, std::string info, std::string out_port, RTLIL::SigSpec out_val) { - RTLIL::SigSpec Y = cell->get(out_port); + RTLIL::SigSpec Y = cell->getPort(out_port); out_val.extend_u0(Y.size(), false); log("Replacing %s cell `%s' (%s) in module `%s' with constant driver `%s = %s'.\n", @@ -89,14 +89,14 @@ static void replace_cell(SigMap &assign_map, RTLIL::Module *module, RTLIL::Cell static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutative, bool extend_u0, SigMap &sigmap) { - std::string b_name = cell->has("\\B") ? "\\B" : "\\A"; + std::string b_name = cell->hasPort("\\B") ? "\\B" : "\\A"; bool a_signed = cell->parameters.at("\\A_SIGNED").as_bool(); bool b_signed = cell->parameters.at(b_name + "_SIGNED").as_bool(); - RTLIL::SigSpec sig_a = sigmap(cell->get("\\A")); - RTLIL::SigSpec sig_b = sigmap(cell->get(b_name)); - RTLIL::SigSpec sig_y = sigmap(cell->get("\\Y")); + RTLIL::SigSpec sig_a = sigmap(cell->getPort("\\A")); + RTLIL::SigSpec sig_b = sigmap(cell->getPort(b_name)); + RTLIL::SigSpec sig_y = sigmap(cell->getPort("\\Y")); if (extend_u0) { sig_a.extend_u0(sig_y.size(), a_signed); @@ -161,17 +161,17 @@ static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool com RTLIL::Cell *c = module->addCell(NEW_ID, cell->type); - c->set("\\A", new_a); + c->setPort("\\A", new_a); c->parameters["\\A_WIDTH"] = new_a.size(); c->parameters["\\A_SIGNED"] = false; if (b_name == "\\B") { - c->set("\\B", new_b); + c->setPort("\\B", new_b); c->parameters["\\B_WIDTH"] = new_b.size(); c->parameters["\\B_SIGNED"] = false; } - c->set("\\Y", new_y); + c->setPort("\\Y", new_y); c->parameters["\\Y_WIDTH"] = new_y->width; c->check(); @@ -210,8 +210,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo for (auto cell : module->cells()) if (design->selected(module, cell) && cell->type[0] == '$') { if ((cell->type == "$_INV_" || cell->type == "$not" || cell->type == "$logic_not") && - cell->get("\\A").size() == 1 && cell->get("\\Y").size() == 1) - invert_map[assign_map(cell->get("\\Y"))] = assign_map(cell->get("\\A")); + cell->getPort("\\A").size() == 1 && cell->getPort("\\Y").size() == 1) + invert_map[assign_map(cell->getPort("\\Y"))] = assign_map(cell->getPort("\\A")); if (ct_combinational.cell_known(cell->type)) for (auto &conn : cell->connections()) { RTLIL::SigSpec sig = assign_map(conn.second); @@ -246,7 +246,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (cell->type == "$reduce_and") { - RTLIL::SigSpec sig_a = assign_map(cell->get("\\A")); + RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A")); RTLIL::State new_a = RTLIL::State::S1; for (auto &bit : sig_a.to_sigbit_vector()) @@ -264,7 +264,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cover("opt.opt_const.fine.$reduce_and"); log("Replacing port A of %s cell `%s' in module `%s' with constant driver: %s -> %s\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a)); - cell->set("\\A", sig_a = new_a); + cell->setPort("\\A", sig_a = new_a); cell->parameters.at("\\A_WIDTH") = 1; OPT_DID_SOMETHING = true; did_something = true; @@ -273,7 +273,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (cell->type == "$logic_not" || cell->type == "$logic_and" || cell->type == "$logic_or" || cell->type == "$reduce_or" || cell->type == "$reduce_bool") { - RTLIL::SigSpec sig_a = assign_map(cell->get("\\A")); + RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A")); RTLIL::State new_a = RTLIL::State::S0; for (auto &bit : sig_a.to_sigbit_vector()) @@ -291,7 +291,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cover_list("opt.opt_const.fine.A", "$logic_not", "$logic_and", "$logic_or", "$reduce_or", "$reduce_bool", cell->type); log("Replacing port A of %s cell `%s' in module `%s' with constant driver: %s -> %s\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a)); - cell->set("\\A", sig_a = new_a); + cell->setPort("\\A", sig_a = new_a); cell->parameters.at("\\A_WIDTH") = 1; OPT_DID_SOMETHING = true; did_something = true; @@ -300,7 +300,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (cell->type == "$logic_and" || cell->type == "$logic_or") { - RTLIL::SigSpec sig_b = assign_map(cell->get("\\B")); + RTLIL::SigSpec sig_b = assign_map(cell->getPort("\\B")); RTLIL::State new_b = RTLIL::State::S0; for (auto &bit : sig_b.to_sigbit_vector()) @@ -318,7 +318,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cover_list("opt.opt_const.fine.B", "$logic_and", "$logic_or", cell->type); log("Replacing port B of %s cell `%s' in module `%s' with constant driver: %s -> %s\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_b), log_signal(new_b)); - cell->set("\\B", sig_b = new_b); + cell->setPort("\\B", sig_b = new_b); cell->parameters.at("\\B_WIDTH") = 1; OPT_DID_SOMETHING = true; did_something = true; @@ -326,13 +326,13 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo } } - if (cell->type == "$logic_or" && (assign_map(cell->get("\\A")) == RTLIL::State::S1 || assign_map(cell->get("\\B")) == RTLIL::State::S1)) { + if (cell->type == "$logic_or" && (assign_map(cell->getPort("\\A")) == RTLIL::State::S1 || assign_map(cell->getPort("\\B")) == RTLIL::State::S1)) { cover("opt.opt_const.one_high"); replace_cell(assign_map, module, cell, "one high", "\\Y", RTLIL::State::S1); goto next_cell; } - if (cell->type == "$logic_and" && (assign_map(cell->get("\\A")) == RTLIL::State::S0 || assign_map(cell->get("\\B")) == RTLIL::State::S0)) { + if (cell->type == "$logic_and" && (assign_map(cell->getPort("\\A")) == RTLIL::State::S0 || assign_map(cell->getPort("\\B")) == RTLIL::State::S0)) { cover("opt.opt_const.one_low"); replace_cell(assign_map, module, cell, "one low", "\\Y", RTLIL::State::S0); goto next_cell; @@ -344,8 +344,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cell->type == "$neg" || cell->type == "$add" || cell->type == "$sub" || cell->type == "$mul" || cell->type == "$div" || cell->type == "$mod" || cell->type == "$pow") { - RTLIL::SigSpec sig_a = assign_map(cell->get("\\A")); - RTLIL::SigSpec sig_b = cell->has("\\B") ? assign_map(cell->get("\\B")) : RTLIL::SigSpec(); + RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A")); + RTLIL::SigSpec sig_b = cell->hasPort("\\B") ? assign_map(cell->getPort("\\B")) : RTLIL::SigSpec(); if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr" || cell->type == "$shift" || cell->type == "$shiftx") sig_a = RTLIL::SigSpec(); @@ -366,31 +366,31 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cell->type == "$lt" || cell->type == "$le" || cell->type == "$ge" || cell->type == "$gt") replace_cell(assign_map, module, cell, "x-bit in input", "\\Y", RTLIL::State::Sx); else - replace_cell(assign_map, module, cell, "x-bit in input", "\\Y", RTLIL::SigSpec(RTLIL::State::Sx, cell->get("\\Y").size())); + replace_cell(assign_map, module, cell, "x-bit in input", "\\Y", RTLIL::SigSpec(RTLIL::State::Sx, cell->getPort("\\Y").size())); goto next_cell; } } - if ((cell->type == "$_INV_" || cell->type == "$not" || cell->type == "$logic_not") && cell->get("\\Y").size() == 1 && - invert_map.count(assign_map(cell->get("\\A"))) != 0) { + if ((cell->type == "$_INV_" || cell->type == "$not" || cell->type == "$logic_not") && cell->getPort("\\Y").size() == 1 && + invert_map.count(assign_map(cell->getPort("\\A"))) != 0) { cover_list("opt.opt_const.invert.double", "$_INV_", "$not", "$logic_not", cell->type); - replace_cell(assign_map, module, cell, "double_invert", "\\Y", invert_map.at(assign_map(cell->get("\\A")))); + replace_cell(assign_map, module, cell, "double_invert", "\\Y", invert_map.at(assign_map(cell->getPort("\\A")))); goto next_cell; } - if ((cell->type == "$_MUX_" || cell->type == "$mux") && invert_map.count(assign_map(cell->get("\\S"))) != 0) { + if ((cell->type == "$_MUX_" || cell->type == "$mux") && invert_map.count(assign_map(cell->getPort("\\S"))) != 0) { cover_list("opt.opt_const.invert.muxsel", "$_MUX_", "$mux", cell->type); - RTLIL::SigSpec tmp = cell->get("\\A"); - cell->set("\\A", cell->get("\\B")); - cell->set("\\B", tmp); - cell->set("\\S", invert_map.at(assign_map(cell->get("\\S")))); + RTLIL::SigSpec tmp = cell->getPort("\\A"); + cell->setPort("\\A", cell->getPort("\\B")); + cell->setPort("\\B", tmp); + cell->setPort("\\S", invert_map.at(assign_map(cell->getPort("\\S")))); OPT_DID_SOMETHING = true; did_something = true; goto next_cell; } if (cell->type == "$_INV_") { - RTLIL::SigSpec input = cell->get("\\A"); + RTLIL::SigSpec input = cell->getPort("\\A"); assign_map.apply(input); if (input.match("1")) ACTION_DO_Y(0); if (input.match("0")) ACTION_DO_Y(1); @@ -399,8 +399,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (cell->type == "$_AND_") { RTLIL::SigSpec input; - input.append(cell->get("\\B")); - input.append(cell->get("\\A")); + input.append(cell->getPort("\\B")); + input.append(cell->getPort("\\A")); assign_map.apply(input); if (input.match(" 0")) ACTION_DO_Y(0); if (input.match("0 ")) ACTION_DO_Y(0); @@ -418,8 +418,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (cell->type == "$_OR_") { RTLIL::SigSpec input; - input.append(cell->get("\\B")); - input.append(cell->get("\\A")); + input.append(cell->getPort("\\B")); + input.append(cell->getPort("\\A")); assign_map.apply(input); if (input.match(" 1")) ACTION_DO_Y(1); if (input.match("1 ")) ACTION_DO_Y(1); @@ -437,8 +437,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (cell->type == "$_XOR_") { RTLIL::SigSpec input; - input.append(cell->get("\\B")); - input.append(cell->get("\\A")); + input.append(cell->getPort("\\B")); + input.append(cell->getPort("\\A")); assign_map.apply(input); if (input.match("00")) ACTION_DO_Y(0); if (input.match("01")) ACTION_DO_Y(1); @@ -452,9 +452,9 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (cell->type == "$_MUX_") { RTLIL::SigSpec input; - input.append(cell->get("\\S")); - input.append(cell->get("\\B")); - input.append(cell->get("\\A")); + input.append(cell->getPort("\\S")); + input.append(cell->getPort("\\B")); + input.append(cell->getPort("\\A")); assign_map.apply(input); if (input.extract(2, 1) == input.extract(1, 1)) ACTION_DO("\\Y", input.extract(2, 1)); @@ -464,9 +464,9 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (input.match("10 ")) { cover("opt.opt_const.mux_to_inv"); cell->type = "$_INV_"; - cell->set("\\A", input.extract(0, 1)); - cell->unset("\\B"); - cell->unset("\\S"); + cell->setPort("\\A", input.extract(0, 1)); + cell->unsetPort("\\B"); + cell->unsetPort("\\S"); goto next_cell; } if (input.match("11 ")) ACTION_DO_Y(1); @@ -483,8 +483,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (cell->type == "$eq" || cell->type == "$ne" || cell->type == "$eqx" || cell->type == "$nex") { - RTLIL::SigSpec a = cell->get("\\A"); - RTLIL::SigSpec b = cell->get("\\B"); + RTLIL::SigSpec a = cell->getPort("\\A"); + RTLIL::SigSpec b = cell->getPort("\\B"); if (cell->parameters["\\A_WIDTH"].as_int() != cell->parameters["\\B_WIDTH"].as_int()) { int width = std::max(cell->parameters["\\A_WIDTH"].as_int(), cell->parameters["\\B_WIDTH"].as_int()); @@ -519,8 +519,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (new_a.size() < a.size() || new_b.size() < b.size()) { cover_list("opt.opt_const.eqneq.resize", "$eq", "$ne", "$eqx", "$nex", cell->type); - cell->set("\\A", new_a); - cell->set("\\B", new_b); + cell->setPort("\\A", new_a); + cell->setPort("\\B", new_b); cell->parameters["\\A_WIDTH"] = new_a.size(); cell->parameters["\\B_WIDTH"] = new_b.size(); } @@ -529,26 +529,26 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if ((cell->type == "$eq" || cell->type == "$ne") && cell->parameters["\\Y_WIDTH"].as_int() == 1 && cell->parameters["\\A_WIDTH"].as_int() == 1 && cell->parameters["\\B_WIDTH"].as_int() == 1) { - RTLIL::SigSpec a = assign_map(cell->get("\\A")); - RTLIL::SigSpec b = assign_map(cell->get("\\B")); + RTLIL::SigSpec a = assign_map(cell->getPort("\\A")); + RTLIL::SigSpec b = assign_map(cell->getPort("\\B")); if (a.is_fully_const()) { cover_list("opt.opt_const.eqneq.swapconst", "$eq", "$ne", cell->type); - RTLIL::SigSpec tmp = cell->get("\\A"); - cell->set("\\A", cell->get("\\B")); - cell->set("\\B", tmp); + RTLIL::SigSpec tmp = cell->getPort("\\A"); + cell->setPort("\\A", cell->getPort("\\B")); + cell->setPort("\\B", tmp); } if (b.is_fully_const()) { if (b.as_bool() == (cell->type == "$eq")) { RTLIL::SigSpec input = b; - ACTION_DO("\\Y", cell->get("\\A")); + ACTION_DO("\\Y", cell->getPort("\\A")); } else { cover_list("opt.opt_const.eqneq.isnot", "$eq", "$ne", cell->type); cell->type = "$not"; cell->parameters.erase("\\B_WIDTH"); cell->parameters.erase("\\B_SIGNED"); - cell->unset("\\B"); + cell->unsetPort("\\B"); } goto next_cell; } @@ -562,8 +562,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (cell->type == "$add" || cell->type == "$sub" || cell->type == "$or" || cell->type == "$xor") { - RTLIL::SigSpec a = assign_map(cell->get("\\A")); - RTLIL::SigSpec b = assign_map(cell->get("\\B")); + RTLIL::SigSpec a = assign_map(cell->getPort("\\A")); + RTLIL::SigSpec b = assign_map(cell->getPort("\\B")); if (cell->type != "$sub" && a.is_fully_const() && a.as_bool() == false) identity_wrt_b = true; @@ -574,7 +574,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr" || cell->type == "$shift" || cell->type == "$shiftx") { - RTLIL::SigSpec b = assign_map(cell->get("\\B")); + RTLIL::SigSpec b = assign_map(cell->getPort("\\B")); if (b.is_fully_const() && b.as_bool() == false) identity_wrt_a = true, identity_bu0 = true; @@ -582,8 +582,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (cell->type == "$mul") { - RTLIL::SigSpec a = assign_map(cell->get("\\A")); - RTLIL::SigSpec b = assign_map(cell->get("\\B")); + RTLIL::SigSpec a = assign_map(cell->getPort("\\A")); + RTLIL::SigSpec b = assign_map(cell->getPort("\\B")); if (a.is_fully_const() && a.size() <= 32 && a.as_int() == 1) identity_wrt_b = true; @@ -594,7 +594,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (cell->type == "$div") { - RTLIL::SigSpec b = assign_map(cell->get("\\B")); + RTLIL::SigSpec b = assign_map(cell->getPort("\\B")); if (b.is_fully_const() && b.size() <= 32 && b.as_int() == 1) identity_wrt_a = true; @@ -611,13 +611,13 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cell->type.c_str(), cell->name.c_str(), module->name.c_str(), identity_wrt_a ? 'A' : 'B'); if (!identity_wrt_a) { - cell->set("\\A", cell->get("\\B")); + cell->setPort("\\A", cell->getPort("\\B")); cell->parameters.at("\\A_WIDTH") = cell->parameters.at("\\B_WIDTH"); cell->parameters.at("\\A_SIGNED") = cell->parameters.at("\\B_SIGNED"); } cell->type = identity_bu0 ? "$bu0" : "$pos"; - cell->unset("\\B"); + cell->unsetPort("\\B"); cell->parameters.erase("\\B_WIDTH"); cell->parameters.erase("\\B_SIGNED"); cell->check(); @@ -629,18 +629,18 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo } if (mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && - cell->get("\\A") == RTLIL::SigSpec(0, 1) && cell->get("\\B") == RTLIL::SigSpec(1, 1)) { + cell->getPort("\\A") == RTLIL::SigSpec(0, 1) && cell->getPort("\\B") == RTLIL::SigSpec(1, 1)) { cover_list("opt.opt_const.mux_bool", "$mux", "$_MUX_", cell->type); - replace_cell(assign_map, module, cell, "mux_bool", "\\Y", cell->get("\\S")); + replace_cell(assign_map, module, cell, "mux_bool", "\\Y", cell->getPort("\\S")); goto next_cell; } if (mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && - cell->get("\\A") == RTLIL::SigSpec(1, 1) && cell->get("\\B") == RTLIL::SigSpec(0, 1)) { + cell->getPort("\\A") == RTLIL::SigSpec(1, 1) && cell->getPort("\\B") == RTLIL::SigSpec(0, 1)) { cover_list("opt.opt_const.mux_invert", "$mux", "$_MUX_", cell->type); - cell->set("\\A", cell->get("\\S")); - cell->unset("\\B"); - cell->unset("\\S"); + cell->setPort("\\A", cell->getPort("\\S")); + cell->unsetPort("\\B"); + cell->unsetPort("\\S"); if (cell->type == "$mux") { cell->parameters["\\A_WIDTH"] = cell->parameters["\\WIDTH"]; cell->parameters["\\Y_WIDTH"] = cell->parameters["\\WIDTH"]; @@ -654,10 +654,10 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo goto next_cell; } - if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->get("\\A") == RTLIL::SigSpec(0, 1)) { + if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->getPort("\\A") == RTLIL::SigSpec(0, 1)) { cover_list("opt.opt_const.mux_and", "$mux", "$_MUX_", cell->type); - cell->set("\\A", cell->get("\\S")); - cell->unset("\\S"); + cell->setPort("\\A", cell->getPort("\\S")); + cell->unsetPort("\\S"); if (cell->type == "$mux") { cell->parameters["\\A_WIDTH"] = cell->parameters["\\WIDTH"]; cell->parameters["\\B_WIDTH"] = cell->parameters["\\WIDTH"]; @@ -673,10 +673,10 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo goto next_cell; } - if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->get("\\B") == RTLIL::SigSpec(1, 1)) { + if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->getPort("\\B") == RTLIL::SigSpec(1, 1)) { cover_list("opt.opt_const.mux_or", "$mux", "$_MUX_", cell->type); - cell->set("\\B", cell->get("\\S")); - cell->unset("\\S"); + cell->setPort("\\B", cell->getPort("\\S")); + cell->unsetPort("\\S"); if (cell->type == "$mux") { cell->parameters["\\A_WIDTH"] = cell->parameters["\\WIDTH"]; cell->parameters["\\B_WIDTH"] = cell->parameters["\\WIDTH"]; @@ -694,22 +694,22 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (mux_undef && (cell->type == "$mux" || cell->type == "$pmux")) { RTLIL::SigSpec new_a, new_b, new_s; - int width = cell->get("\\A").size(); - if ((cell->get("\\A").is_fully_undef() && cell->get("\\B").is_fully_undef()) || - cell->get("\\S").is_fully_undef()) { + int width = cell->getPort("\\A").size(); + if ((cell->getPort("\\A").is_fully_undef() && cell->getPort("\\B").is_fully_undef()) || + cell->getPort("\\S").is_fully_undef()) { cover_list("opt.opt_const.mux_undef", "$mux", "$pmux", cell->type); - replace_cell(assign_map, module, cell, "mux_undef", "\\Y", cell->get("\\A")); + replace_cell(assign_map, module, cell, "mux_undef", "\\Y", cell->getPort("\\A")); goto next_cell; } - for (int i = 0; i < cell->get("\\S").size(); i++) { - RTLIL::SigSpec old_b = cell->get("\\B").extract(i*width, width); - RTLIL::SigSpec old_s = cell->get("\\S").extract(i, 1); + for (int i = 0; i < cell->getPort("\\S").size(); i++) { + RTLIL::SigSpec old_b = cell->getPort("\\B").extract(i*width, width); + RTLIL::SigSpec old_s = cell->getPort("\\S").extract(i, 1); if (old_b.is_fully_undef() || old_s.is_fully_undef()) continue; new_b.append(old_b); new_s.append(old_s); } - new_a = cell->get("\\A"); + new_a = cell->getPort("\\A"); if (new_a.is_fully_undef() && new_s.size() > 0) { new_a = new_b.extract((new_s.size()-1)*width, width); new_b = new_b.extract(0, (new_s.size()-1)*width); @@ -725,11 +725,11 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo replace_cell(assign_map, module, cell, "mux_sel01", "\\Y", new_s); goto next_cell; } - if (cell->get("\\S").size() != new_s.size()) { + if (cell->getPort("\\S").size() != new_s.size()) { cover_list("opt.opt_const.mux_reduce", "$mux", "$pmux", cell->type); - cell->set("\\A", new_a); - cell->set("\\B", new_b); - cell->set("\\S", new_s); + cell->setPort("\\A", new_a); + cell->setPort("\\B", new_b); + cell->setPort("\\S", new_s); if (new_s.size() > 1) { cell->type = "$pmux"; cell->parameters["\\S_WIDTH"] = new_s.size(); @@ -744,7 +744,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo #define FOLD_1ARG_CELL(_t) \ if (cell->type == "$" #_t) { \ - RTLIL::SigSpec a = cell->get("\\A"); \ + RTLIL::SigSpec a = cell->getPort("\\A"); \ assign_map.apply(a); \ if (a.is_fully_const()) { \ RTLIL::Const dummy_arg(RTLIL::State::S0, 1); \ @@ -758,8 +758,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo } #define FOLD_2ARG_CELL(_t) \ if (cell->type == "$" #_t) { \ - RTLIL::SigSpec a = cell->get("\\A"); \ - RTLIL::SigSpec b = cell->get("\\B"); \ + RTLIL::SigSpec a = cell->getPort("\\A"); \ + RTLIL::SigSpec b = cell->getPort("\\B"); \ assign_map.apply(a), assign_map.apply(b); \ if (a.is_fully_const() && b.is_fully_const()) { \ RTLIL::SigSpec y(RTLIL::const_ ## _t(a.as_const(), b.as_const(), \ @@ -815,13 +815,13 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo // be very conservative with optimizing $mux cells as we do not want to break mux trees if (cell->type == "$mux") { - RTLIL::SigSpec input = assign_map(cell->get("\\S")); - RTLIL::SigSpec inA = assign_map(cell->get("\\A")); - RTLIL::SigSpec inB = assign_map(cell->get("\\B")); + RTLIL::SigSpec input = assign_map(cell->getPort("\\S")); + RTLIL::SigSpec inA = assign_map(cell->getPort("\\A")); + RTLIL::SigSpec inB = assign_map(cell->getPort("\\B")); if (input.is_fully_const()) - ACTION_DO("\\Y", input.as_bool() ? cell->get("\\B") : cell->get("\\A")); + ACTION_DO("\\Y", input.as_bool() ? cell->getPort("\\B") : cell->getPort("\\A")); else if (inA == inB) - ACTION_DO("\\Y", cell->get("\\A")); + ACTION_DO("\\Y", cell->getPort("\\A")); } if (!keepdc && cell->type == "$mul") @@ -830,9 +830,9 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo bool b_signed = cell->parameters["\\B_SIGNED"].as_bool(); bool swapped_ab = false; - RTLIL::SigSpec sig_a = assign_map(cell->get("\\A")); - RTLIL::SigSpec sig_b = assign_map(cell->get("\\B")); - RTLIL::SigSpec sig_y = assign_map(cell->get("\\Y")); + RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A")); + RTLIL::SigSpec sig_b = assign_map(cell->getPort("\\B")); + RTLIL::SigSpec sig_y = assign_map(cell->getPort("\\Y")); if (sig_b.is_fully_const() && sig_b.size() <= 32) std::swap(sig_a, sig_b), std::swap(a_signed, b_signed), swapped_ab = true; @@ -868,7 +868,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo a_val, cell->name.c_str(), module->name.c_str(), i); if (!swapped_ab) { - cell->set("\\A", cell->get("\\B")); + cell->setPort("\\A", cell->getPort("\\B")); cell->parameters["\\A_WIDTH"] = cell->parameters["\\B_WIDTH"]; cell->parameters["\\A_SIGNED"] = cell->parameters["\\B_SIGNED"]; } @@ -881,7 +881,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cell->type = "$shl"; cell->parameters["\\B_WIDTH"] = SIZE(new_b); cell->parameters["\\B_SIGNED"] = false; - cell->set("\\B", new_b); + cell->setPort("\\B", new_b); cell->check(); OPT_DID_SOMETHING = true; diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc index de12542dc..2660b33d4 100644 --- a/passes/opt/opt_muxtree.cc +++ b/passes/opt/opt_muxtree.cc @@ -86,10 +86,10 @@ struct OptMuxtreeWorker { if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux") { - RTLIL::SigSpec sig_a = cell->get("\\A"); - RTLIL::SigSpec sig_b = cell->get("\\B"); - RTLIL::SigSpec sig_s = cell->get("\\S"); - RTLIL::SigSpec sig_y = cell->get("\\Y"); + RTLIL::SigSpec sig_a = cell->getPort("\\A"); + RTLIL::SigSpec sig_b = cell->getPort("\\B"); + RTLIL::SigSpec sig_s = cell->getPort("\\S"); + RTLIL::SigSpec sig_y = cell->getPort("\\Y"); muxinfo_t muxinfo; muxinfo.cell = cell; @@ -192,10 +192,10 @@ struct OptMuxtreeWorker continue; } - RTLIL::SigSpec sig_a = mi.cell->get("\\A"); - RTLIL::SigSpec sig_b = mi.cell->get("\\B"); - RTLIL::SigSpec sig_s = mi.cell->get("\\S"); - RTLIL::SigSpec sig_y = mi.cell->get("\\Y"); + RTLIL::SigSpec sig_a = mi.cell->getPort("\\A"); + RTLIL::SigSpec sig_b = mi.cell->getPort("\\B"); + RTLIL::SigSpec sig_s = mi.cell->getPort("\\S"); + RTLIL::SigSpec sig_y = mi.cell->getPort("\\Y"); RTLIL::SigSpec sig_ports = sig_b; sig_ports.append(sig_a); @@ -220,9 +220,9 @@ struct OptMuxtreeWorker } } - mi.cell->set("\\A", new_sig_a); - mi.cell->set("\\B", new_sig_b); - mi.cell->set("\\S", new_sig_s); + mi.cell->setPort("\\A", new_sig_a); + mi.cell->setPort("\\B", new_sig_b); + mi.cell->setPort("\\S", new_sig_s); if (new_sig_s.size() == 1) { mi.cell->type = "$mux"; mi.cell->parameters.erase("\\S_WIDTH"); diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc index 8aadd1f23..80ec89744 100644 --- a/passes/opt/opt_reduce.cc +++ b/passes/opt/opt_reduce.cc @@ -42,7 +42,7 @@ struct OptReduceWorker return; cells.erase(cell); - RTLIL::SigSpec sig_a = assign_map(cell->get("\\A")); + RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A")); std::set new_sig_a_bits; for (auto &bit : sig_a.to_sigbit_set()) @@ -72,8 +72,8 @@ struct OptReduceWorker for (auto child_cell : drivers.find(bit)) { if (child_cell->type == cell->type) { opt_reduce(cells, drivers, child_cell); - if (child_cell->get("\\Y")[0] == bit) { - std::set child_sig_a_bits = assign_map(child_cell->get("\\A")).to_sigbit_set(); + if (child_cell->getPort("\\Y")[0] == bit) { + std::set child_sig_a_bits = assign_map(child_cell->getPort("\\A")).to_sigbit_set(); new_sig_a_bits.insert(child_sig_a_bits.begin(), child_sig_a_bits.end()); } else new_sig_a_bits.insert(RTLIL::State::S0); @@ -86,23 +86,23 @@ struct OptReduceWorker RTLIL::SigSpec new_sig_a(new_sig_a_bits); - if (new_sig_a != sig_a || sig_a.size() != cell->get("\\A").size()) { + if (new_sig_a != sig_a || sig_a.size() != cell->getPort("\\A").size()) { log(" New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a)); did_something = true; OPT_DID_SOMETHING = true; total_count++; } - cell->set("\\A", new_sig_a); + cell->setPort("\\A", new_sig_a); cell->parameters["\\A_WIDTH"] = RTLIL::Const(new_sig_a.size()); return; } void opt_mux(RTLIL::Cell *cell) { - RTLIL::SigSpec sig_a = assign_map(cell->get("\\A")); - RTLIL::SigSpec sig_b = assign_map(cell->get("\\B")); - RTLIL::SigSpec sig_s = assign_map(cell->get("\\S")); + RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A")); + RTLIL::SigSpec sig_b = assign_map(cell->getPort("\\B")); + RTLIL::SigSpec sig_s = assign_map(cell->getPort("\\S")); RTLIL::SigSpec new_sig_b, new_sig_s; std::set handled_sig; @@ -124,14 +124,14 @@ struct OptReduceWorker if (this_s.size() > 1) { RTLIL::Cell *reduce_or_cell = module->addCell(NEW_ID, "$reduce_or"); - reduce_or_cell->set("\\A", this_s); + reduce_or_cell->setPort("\\A", this_s); reduce_or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); reduce_or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(this_s.size()); reduce_or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); RTLIL::Wire *reduce_or_wire = module->addWire(NEW_ID); this_s = RTLIL::SigSpec(reduce_or_wire); - reduce_or_cell->set("\\Y", this_s); + reduce_or_cell->setPort("\\Y", this_s); } new_sig_b.append(this_b); @@ -148,14 +148,14 @@ struct OptReduceWorker if (new_sig_s.size() == 0) { - module->connect(RTLIL::SigSig(cell->get("\\Y"), cell->get("\\A"))); - assign_map.add(cell->get("\\Y"), cell->get("\\A")); + module->connect(RTLIL::SigSig(cell->getPort("\\Y"), cell->getPort("\\A"))); + assign_map.add(cell->getPort("\\Y"), cell->getPort("\\A")); module->remove(cell); } else { - cell->set("\\B", new_sig_b); - cell->set("\\S", new_sig_s); + cell->setPort("\\B", new_sig_b); + cell->setPort("\\S", new_sig_s); if (new_sig_s.size() > 1) { cell->parameters["\\S_WIDTH"] = RTLIL::Const(new_sig_s.size()); } else { @@ -167,9 +167,9 @@ struct OptReduceWorker void opt_mux_bits(RTLIL::Cell *cell) { - std::vector sig_a = assign_map(cell->get("\\A")).to_sigbit_vector(); - std::vector sig_b = assign_map(cell->get("\\B")).to_sigbit_vector(); - std::vector sig_y = assign_map(cell->get("\\Y")).to_sigbit_vector(); + std::vector sig_a = assign_map(cell->getPort("\\A")).to_sigbit_vector(); + std::vector sig_b = assign_map(cell->getPort("\\B")).to_sigbit_vector(); + std::vector sig_y = assign_map(cell->getPort("\\Y")).to_sigbit_vector(); std::vector new_sig_y; RTLIL::SigSig old_sig_conn; @@ -210,29 +210,29 @@ struct OptReduceWorker if (new_sig_y.size() != sig_y.size()) { log(" Consolidated identical input bits for %s cell %s:\n", cell->type.c_str(), cell->name.c_str()); - log(" Old ports: A=%s, B=%s, Y=%s\n", log_signal(cell->get("\\A")), - log_signal(cell->get("\\B")), log_signal(cell->get("\\Y"))); + log(" Old ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort("\\A")), + log_signal(cell->getPort("\\B")), log_signal(cell->getPort("\\Y"))); - cell->set("\\A", RTLIL::SigSpec()); + cell->setPort("\\A", RTLIL::SigSpec()); for (auto &in_tuple : consolidated_in_tuples) { - RTLIL::SigSpec new_a = cell->get("\\A"); + RTLIL::SigSpec new_a = cell->getPort("\\A"); new_a.append(in_tuple.at(0)); - cell->set("\\A", new_a); + cell->setPort("\\A", new_a); } - cell->set("\\B", RTLIL::SigSpec()); - for (int i = 1; i <= cell->get("\\S").size(); i++) + cell->setPort("\\B", RTLIL::SigSpec()); + for (int i = 1; i <= cell->getPort("\\S").size(); i++) for (auto &in_tuple : consolidated_in_tuples) { - RTLIL::SigSpec new_b = cell->get("\\B"); + RTLIL::SigSpec new_b = cell->getPort("\\B"); new_b.append(in_tuple.at(i)); - cell->set("\\B", new_b); + cell->setPort("\\B", new_b); } cell->parameters["\\WIDTH"] = RTLIL::Const(new_sig_y.size()); - cell->set("\\Y", new_sig_y); + cell->setPort("\\Y", new_sig_y); - log(" New ports: A=%s, B=%s, Y=%s\n", log_signal(cell->get("\\A")), - log_signal(cell->get("\\B")), log_signal(cell->get("\\Y"))); + log(" New ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort("\\A")), + log_signal(cell->getPort("\\B")), log_signal(cell->getPort("\\Y"))); log(" New connections: %s = %s\n", log_signal(old_sig_conn.first), log_signal(old_sig_conn.second)); module->connect(old_sig_conn); @@ -256,14 +256,14 @@ struct OptReduceWorker for (auto &cell_it : module->cells_) { RTLIL::Cell *cell = cell_it.second; if (cell->type == "$mem") - mem_wren_sigs.add(assign_map(cell->get("\\WR_EN"))); + mem_wren_sigs.add(assign_map(cell->getPort("\\WR_EN"))); if (cell->type == "$memwr") - mem_wren_sigs.add(assign_map(cell->get("\\EN"))); + mem_wren_sigs.add(assign_map(cell->getPort("\\EN"))); } for (auto &cell_it : module->cells_) { RTLIL::Cell *cell = cell_it.second; - if (cell->type == "$dff" && mem_wren_sigs.check_any(assign_map(cell->get("\\Q")))) - mem_wren_sigs.add(assign_map(cell->get("\\D"))); + if (cell->type == "$dff" && mem_wren_sigs.check_any(assign_map(cell->getPort("\\Q")))) + mem_wren_sigs.add(assign_map(cell->getPort("\\D"))); } bool keep_expanding_mem_wren_sigs = true; @@ -271,12 +271,12 @@ struct OptReduceWorker keep_expanding_mem_wren_sigs = false; for (auto &cell_it : module->cells_) { RTLIL::Cell *cell = cell_it.second; - if (cell->type == "$mux" && mem_wren_sigs.check_any(assign_map(cell->get("\\Y")))) { - if (!mem_wren_sigs.check_all(assign_map(cell->get("\\A"))) || - !mem_wren_sigs.check_all(assign_map(cell->get("\\B")))) + if (cell->type == "$mux" && mem_wren_sigs.check_any(assign_map(cell->getPort("\\Y")))) { + if (!mem_wren_sigs.check_all(assign_map(cell->getPort("\\A"))) || + !mem_wren_sigs.check_all(assign_map(cell->getPort("\\B")))) keep_expanding_mem_wren_sigs = true; - mem_wren_sigs.add(assign_map(cell->get("\\A"))); - mem_wren_sigs.add(assign_map(cell->get("\\B"))); + mem_wren_sigs.add(assign_map(cell->getPort("\\A"))); + mem_wren_sigs.add(assign_map(cell->getPort("\\B"))); } } } @@ -298,7 +298,7 @@ struct OptReduceWorker RTLIL::Cell *cell = cell_it.second; if (cell->type != type || !design->selected(module, cell)) continue; - drivers.insert(assign_map(cell->get("\\Y")), cell); + drivers.insert(assign_map(cell->getPort("\\Y")), cell); cells.insert(cell); } @@ -320,7 +320,7 @@ struct OptReduceWorker { // this optimization is to aggressive for most coarse-grain applications. // but we always want it for multiplexers driving write enable ports. - if (do_fine || mem_wren_sigs.check_any(assign_map(cell->get("\\Y")))) + if (do_fine || mem_wren_sigs.check_any(assign_map(cell->getPort("\\Y")))) opt_mux_bits(cell); opt_mux(cell); diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc index b01778b5e..c1e33caf3 100644 --- a/passes/opt/opt_rmdff.cc +++ b/passes/opt/opt_rmdff.cc @@ -33,34 +33,34 @@ static bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) RTLIL::Const val_cp, val_rp, val_rv; if (dff->type == "$_DFF_N_" || dff->type == "$_DFF_P_") { - sig_d = dff->get("\\D"); - sig_q = dff->get("\\Q"); - sig_c = dff->get("\\C"); + sig_d = dff->getPort("\\D"); + sig_q = dff->getPort("\\Q"); + sig_c = dff->getPort("\\C"); val_cp = RTLIL::Const(dff->type == "$_DFF_P_", 1); } else if (dff->type.substr(0,6) == "$_DFF_" && dff->type.substr(9) == "_" && (dff->type[6] == 'N' || dff->type[6] == 'P') && (dff->type[7] == 'N' || dff->type[7] == 'P') && (dff->type[8] == '0' || dff->type[8] == '1')) { - sig_d = dff->get("\\D"); - sig_q = dff->get("\\Q"); - sig_c = dff->get("\\C"); - sig_r = dff->get("\\R"); + sig_d = dff->getPort("\\D"); + sig_q = dff->getPort("\\Q"); + sig_c = dff->getPort("\\C"); + sig_r = dff->getPort("\\R"); val_cp = RTLIL::Const(dff->type[6] == 'P', 1); val_rp = RTLIL::Const(dff->type[7] == 'P', 1); val_rv = RTLIL::Const(dff->type[8] == '1', 1); } else if (dff->type == "$dff") { - sig_d = dff->get("\\D"); - sig_q = dff->get("\\Q"); - sig_c = dff->get("\\CLK"); + sig_d = dff->getPort("\\D"); + sig_q = dff->getPort("\\Q"); + sig_c = dff->getPort("\\CLK"); val_cp = RTLIL::Const(dff->parameters["\\CLK_POLARITY"].as_bool(), 1); } else if (dff->type == "$adff") { - sig_d = dff->get("\\D"); - sig_q = dff->get("\\Q"); - sig_c = dff->get("\\CLK"); - sig_r = dff->get("\\ARST"); + sig_d = dff->getPort("\\D"); + sig_q = dff->getPort("\\Q"); + sig_c = dff->getPort("\\CLK"); + sig_r = dff->getPort("\\ARST"); val_cp = RTLIL::Const(dff->parameters["\\CLK_POLARITY"].as_bool(), 1); val_rp = RTLIL::Const(dff->parameters["\\ARST_POLARITY"].as_bool(), 1); val_rv = dff->parameters["\\ARST_VALUE"]; @@ -85,8 +85,8 @@ static bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) std::set muxes; mux_drivers.find(sig_d, muxes); for (auto mux : muxes) { - RTLIL::SigSpec sig_a = assign_map(mux->get("\\A")); - RTLIL::SigSpec sig_b = assign_map(mux->get("\\B")); + RTLIL::SigSpec sig_a = assign_map(mux->getPort("\\A")); + RTLIL::SigSpec sig_b = assign_map(mux->getPort("\\B")); if (sig_a == sig_q && sig_b.is_fully_const()) { RTLIL::SigSig conn(sig_q, sig_b); mod->connect(conn); @@ -181,8 +181,8 @@ struct OptRmdffPass : public Pass { std::vector dff_list; for (auto &it : mod_it.second->cells_) { if (it.second->type == "$mux" || it.second->type == "$pmux") { - if (it.second->get("\\A").size() == it.second->get("\\B").size()) - mux_drivers.insert(assign_map(it.second->get("\\Y")), it.second); + if (it.second->getPort("\\A").size() == it.second->getPort("\\B").size()) + mux_drivers.insert(assign_map(it.second->getPort("\\Y")), it.second); continue; } if (!design->selected(mod_it.second, it.second)) diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc index ad6e1a746..26d19414a 100644 --- a/passes/opt/opt_share.cc +++ b/passes/opt/opt_share.cc @@ -179,8 +179,8 @@ struct OptShareWorker } if (cell1->type.substr(0, 1) == "$" && conn1.count("\\Q") != 0) { - std::vector q1 = dff_init_map(cell1->get("\\Q")).to_sigbit_vector(); - std::vector q2 = dff_init_map(cell2->get("\\Q")).to_sigbit_vector(); + std::vector q1 = dff_init_map(cell1->getPort("\\Q")).to_sigbit_vector(); + std::vector q2 = dff_init_map(cell2->getPort("\\Q")).to_sigbit_vector(); for (size_t i = 0; i < q1.size(); i++) if ((q1.at(i).wire == NULL || q2.at(i).wire == NULL) && q1.at(i) != q2.at(i)) { lt = q1.at(i) < q2.at(i); @@ -262,7 +262,7 @@ struct OptShareWorker log(" Cell `%s' is identical to cell `%s'.\n", cell->name.c_str(), sharemap[cell]->name.c_str()); for (auto &it : cell->connections()) { if (ct.cell_output(cell->type, it.first)) { - RTLIL::SigSpec other_sig = sharemap[cell]->get(it.first); + RTLIL::SigSpec other_sig = sharemap[cell]->getPort(it.first); log(" Redirecting output %s: %s = %s\n", it.first.c_str(), log_signal(it.second), log_signal(other_sig)); module->connect(RTLIL::SigSig(it.second, other_sig)); diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc index 676469fe2..f11b328f0 100644 --- a/passes/proc/proc_arst.cc +++ b/passes/proc/proc_arst.cc @@ -35,45 +35,45 @@ static bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSp for (auto cell : mod->cells()) { - if (cell->type == "$reduce_or" && cell->get("\\Y") == signal) - return check_signal(mod, cell->get("\\A"), ref, polarity); + if (cell->type == "$reduce_or" && cell->getPort("\\Y") == signal) + return check_signal(mod, cell->getPort("\\A"), ref, polarity); - if (cell->type == "$reduce_bool" && cell->get("\\Y") == signal) - return check_signal(mod, cell->get("\\A"), ref, polarity); + if (cell->type == "$reduce_bool" && cell->getPort("\\Y") == signal) + return check_signal(mod, cell->getPort("\\A"), ref, polarity); - if (cell->type == "$logic_not" && cell->get("\\Y") == signal) { + if (cell->type == "$logic_not" && cell->getPort("\\Y") == signal) { polarity = !polarity; - return check_signal(mod, cell->get("\\A"), ref, polarity); + return check_signal(mod, cell->getPort("\\A"), ref, polarity); } - if (cell->type == "$not" && cell->get("\\Y") == signal) { + if (cell->type == "$not" && cell->getPort("\\Y") == signal) { polarity = !polarity; - return check_signal(mod, cell->get("\\A"), ref, polarity); + return check_signal(mod, cell->getPort("\\A"), ref, polarity); } - if ((cell->type == "$eq" || cell->type == "$eqx") && cell->get("\\Y") == signal) { - if (cell->get("\\A").is_fully_const()) { - if (!cell->get("\\A").as_bool()) + if ((cell->type == "$eq" || cell->type == "$eqx") && cell->getPort("\\Y") == signal) { + if (cell->getPort("\\A").is_fully_const()) { + if (!cell->getPort("\\A").as_bool()) polarity = !polarity; - return check_signal(mod, cell->get("\\B"), ref, polarity); + return check_signal(mod, cell->getPort("\\B"), ref, polarity); } - if (cell->get("\\B").is_fully_const()) { - if (!cell->get("\\B").as_bool()) + if (cell->getPort("\\B").is_fully_const()) { + if (!cell->getPort("\\B").as_bool()) polarity = !polarity; - return check_signal(mod, cell->get("\\A"), ref, polarity); + return check_signal(mod, cell->getPort("\\A"), ref, polarity); } } - if ((cell->type == "$ne" || cell->type == "$nex") && cell->get("\\Y") == signal) { - if (cell->get("\\A").is_fully_const()) { - if (cell->get("\\A").as_bool()) + if ((cell->type == "$ne" || cell->type == "$nex") && cell->getPort("\\Y") == signal) { + if (cell->getPort("\\A").is_fully_const()) { + if (cell->getPort("\\A").as_bool()) polarity = !polarity; - return check_signal(mod, cell->get("\\B"), ref, polarity); + return check_signal(mod, cell->getPort("\\B"), ref, polarity); } - if (cell->get("\\B").is_fully_const()) { - if (cell->get("\\B").as_bool()) + if (cell->getPort("\\B").is_fully_const()) { + if (cell->getPort("\\B").as_bool()) polarity = !polarity; - return check_signal(mod, cell->get("\\A"), ref, polarity); + return check_signal(mod, cell->getPort("\\A"), ref, polarity); } } } diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index d894b442b..e69e8023d 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -76,8 +76,8 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.size()); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - cell->set("\\A", sync_low_signals); - cell->set("\\Y", sync_low_signals = mod->addWire(NEW_ID)); + cell->setPort("\\A", sync_low_signals); + cell->setPort("\\Y", sync_low_signals = mod->addWire(NEW_ID)); } if (sync_low_signals.size() > 0) { @@ -85,9 +85,9 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.size()); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - cell->set("\\A", sync_low_signals); - cell->set("\\Y", mod->addWire(NEW_ID)); - sync_high_signals.append(cell->get("\\Y")); + cell->setPort("\\A", sync_low_signals); + cell->setPort("\\Y", mod->addWire(NEW_ID)); + sync_high_signals.append(cell->getPort("\\Y")); } if (sync_high_signals.size() > 1) { @@ -95,30 +95,30 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_high_signals.size()); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - cell->set("\\A", sync_high_signals); - cell->set("\\Y", sync_high_signals = mod->addWire(NEW_ID)); + cell->setPort("\\A", sync_high_signals); + cell->setPort("\\Y", sync_high_signals = mod->addWire(NEW_ID)); } RTLIL::Cell *inv_cell = mod->addCell(NEW_ID, "$not"); inv_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); inv_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_d.size()); inv_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_d.size()); - inv_cell->set("\\A", sync_value); - inv_cell->set("\\Y", sync_value_inv = mod->addWire(NEW_ID, sig_d.size())); + inv_cell->setPort("\\A", sync_value); + inv_cell->setPort("\\Y", sync_value_inv = mod->addWire(NEW_ID, sig_d.size())); RTLIL::Cell *mux_set_cell = mod->addCell(NEW_ID, "$mux"); mux_set_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size()); - mux_set_cell->set("\\A", sig_sr_set); - mux_set_cell->set("\\B", sync_value); - mux_set_cell->set("\\S", sync_high_signals); - mux_set_cell->set("\\Y", sig_sr_set = mod->addWire(NEW_ID, sig_d.size())); + mux_set_cell->setPort("\\A", sig_sr_set); + mux_set_cell->setPort("\\B", sync_value); + mux_set_cell->setPort("\\S", sync_high_signals); + mux_set_cell->setPort("\\Y", sig_sr_set = mod->addWire(NEW_ID, sig_d.size())); RTLIL::Cell *mux_clr_cell = mod->addCell(NEW_ID, "$mux"); mux_clr_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size()); - mux_clr_cell->set("\\A", sig_sr_clr); - mux_clr_cell->set("\\B", sync_value_inv); - mux_clr_cell->set("\\S", sync_high_signals); - mux_clr_cell->set("\\Y", sig_sr_clr = mod->addWire(NEW_ID, sig_d.size())); + mux_clr_cell->setPort("\\A", sig_sr_clr); + mux_clr_cell->setPort("\\B", sync_value_inv); + mux_clr_cell->setPort("\\S", sync_high_signals); + mux_clr_cell->setPort("\\Y", sig_sr_clr = mod->addWire(NEW_ID, sig_d.size())); } std::stringstream sstr; @@ -130,11 +130,11 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1); cell->parameters["\\SET_POLARITY"] = RTLIL::Const(true, 1); cell->parameters["\\CLR_POLARITY"] = RTLIL::Const(true, 1); - cell->set("\\D", sig_d); - cell->set("\\Q", sig_q); - cell->set("\\CLK", clk); - cell->set("\\SET", sig_sr_set); - cell->set("\\CLR", sig_sr_clr); + cell->setPort("\\D", sig_d); + cell->setPort("\\Q", sig_q); + cell->setPort("\\CLK", clk); + cell->setPort("\\SET", sig_sr_set); + cell->setPort("\\CLR", sig_sr_clr); log(" created %s cell `%s' with %s edge clock and multiple level-sensitive resets.\n", cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative"); @@ -154,22 +154,22 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec inv_set->parameters["\\A_SIGNED"] = RTLIL::Const(0); inv_set->parameters["\\A_WIDTH"] = RTLIL::Const(sig_in.size()); inv_set->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_in.size()); - inv_set->set("\\A", sig_set); - inv_set->set("\\Y", sig_set_inv); + inv_set->setPort("\\A", sig_set); + inv_set->setPort("\\Y", sig_set_inv); RTLIL::Cell *mux_sr_set = mod->addCell(NEW_ID, "$mux"); mux_sr_set->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size()); - mux_sr_set->set(set_polarity ? "\\A" : "\\B", RTLIL::Const(0, sig_in.size())); - mux_sr_set->set(set_polarity ? "\\B" : "\\A", sig_set); - mux_sr_set->set("\\Y", sig_sr_set); - mux_sr_set->set("\\S", set); + mux_sr_set->setPort(set_polarity ? "\\A" : "\\B", RTLIL::Const(0, sig_in.size())); + mux_sr_set->setPort(set_polarity ? "\\B" : "\\A", sig_set); + mux_sr_set->setPort("\\Y", sig_sr_set); + mux_sr_set->setPort("\\S", set); RTLIL::Cell *mux_sr_clr = mod->addCell(NEW_ID, "$mux"); mux_sr_clr->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size()); - mux_sr_clr->set(set_polarity ? "\\A" : "\\B", RTLIL::Const(0, sig_in.size())); - mux_sr_clr->set(set_polarity ? "\\B" : "\\A", sig_set_inv); - mux_sr_clr->set("\\Y", sig_sr_clr); - mux_sr_clr->set("\\S", set); + mux_sr_clr->setPort(set_polarity ? "\\A" : "\\B", RTLIL::Const(0, sig_in.size())); + mux_sr_clr->setPort(set_polarity ? "\\B" : "\\A", sig_set_inv); + mux_sr_clr->setPort("\\Y", sig_sr_clr); + mux_sr_clr->setPort("\\S", set); RTLIL::Cell *cell = mod->addCell(sstr.str(), "$dffsr"); cell->attributes = proc->attributes; @@ -177,11 +177,11 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1); cell->parameters["\\SET_POLARITY"] = RTLIL::Const(true, 1); cell->parameters["\\CLR_POLARITY"] = RTLIL::Const(true, 1); - cell->set("\\D", sig_in); - cell->set("\\Q", sig_out); - cell->set("\\CLK", clk); - cell->set("\\SET", sig_sr_set); - cell->set("\\CLR", sig_sr_clr); + cell->setPort("\\D", sig_in); + cell->setPort("\\Q", sig_out); + cell->setPort("\\CLK", clk); + cell->setPort("\\SET", sig_sr_set); + cell->setPort("\\CLR", sig_sr_clr); log(" created %s cell `%s' with %s edge clock and %s level non-const reset.\n", cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative", set_polarity ? "positive" : "negative"); @@ -203,11 +203,11 @@ static void gen_dff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::Const val_ } cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1); - cell->set("\\D", sig_in); - cell->set("\\Q", sig_out); + cell->setPort("\\D", sig_in); + cell->setPort("\\Q", sig_out); if (arst) - cell->set("\\ARST", *arst); - cell->set("\\CLK", clk); + cell->setPort("\\ARST", *arst); + cell->setPort("\\CLK", clk); log(" created %s cell `%s' with %s edge clock", cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative"); if (arst) @@ -295,9 +295,9 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) cell->parameters["\\A_WIDTH"] = RTLIL::Const(inputs.size()); cell->parameters["\\B_WIDTH"] = RTLIL::Const(inputs.size()); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - cell->set("\\A", inputs); - cell->set("\\B", compare); - cell->set("\\Y", sync_level->signal); + cell->setPort("\\A", inputs); + cell->setPort("\\B", compare); + cell->setPort("\\Y", sync_level->signal); many_async_rules.clear(); } diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc index b18ce4925..c00b00a2a 100644 --- a/passes/proc/proc_mux.cc +++ b/passes/proc/proc_mux.cc @@ -92,9 +92,9 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(comp.size()); eq_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - eq_cell->set("\\A", sig); - eq_cell->set("\\B", comp); - eq_cell->set("\\Y", RTLIL::SigSpec(cmp_wire, cmp_wire->width++)); + eq_cell->setPort("\\A", sig); + eq_cell->setPort("\\B", comp); + eq_cell->setPort("\\Y", RTLIL::SigSpec(cmp_wire, cmp_wire->width++)); } } @@ -115,8 +115,8 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, any_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cmp_wire->width); any_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - any_cell->set("\\A", cmp_wire); - any_cell->set("\\Y", RTLIL::SigSpec(ctrl_wire)); + any_cell->setPort("\\A", cmp_wire); + any_cell->setPort("\\Y", RTLIL::SigSpec(ctrl_wire)); } return RTLIL::SigSpec(ctrl_wire); @@ -147,10 +147,10 @@ static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, mux_cell->attributes = sw->attributes; mux_cell->parameters["\\WIDTH"] = RTLIL::Const(when_signal.size()); - mux_cell->set("\\A", else_signal); - mux_cell->set("\\B", when_signal); - mux_cell->set("\\S", ctrl_sig); - mux_cell->set("\\Y", RTLIL::SigSpec(result_wire)); + mux_cell->setPort("\\A", else_signal); + mux_cell->setPort("\\B", when_signal); + mux_cell->setPort("\\S", ctrl_sig); + mux_cell->setPort("\\Y", RTLIL::SigSpec(result_wire)); last_mux_cell = mux_cell; return RTLIL::SigSpec(result_wire); @@ -159,21 +159,21 @@ static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, static void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector &compare, RTLIL::SigSpec when_signal, RTLIL::Cell *last_mux_cell, RTLIL::SwitchRule *sw) { log_assert(last_mux_cell != NULL); - log_assert(when_signal.size() == last_mux_cell->get("\\A").size()); + log_assert(when_signal.size() == last_mux_cell->getPort("\\A").size()); RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw); log_assert(ctrl_sig.size() == 1); last_mux_cell->type = "$pmux"; - RTLIL::SigSpec new_s = last_mux_cell->get("\\S"); + RTLIL::SigSpec new_s = last_mux_cell->getPort("\\S"); new_s.append(ctrl_sig); - last_mux_cell->set("\\S", new_s); + last_mux_cell->setPort("\\S", new_s); - RTLIL::SigSpec new_b = last_mux_cell->get("\\B"); + RTLIL::SigSpec new_b = last_mux_cell->getPort("\\B"); new_b.append(when_signal); - last_mux_cell->set("\\B", new_b); + last_mux_cell->setPort("\\B", new_b); - last_mux_cell->parameters["\\S_WIDTH"] = last_mux_cell->get("\\S").size(); + last_mux_cell->parameters["\\S_WIDTH"] = last_mux_cell->getPort("\\S").size(); } static RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, RTLIL::CaseRule *cs, const RTLIL::SigSpec &sig, const RTLIL::SigSpec &defval) diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc index f2b89b000..25b9e1d11 100644 --- a/passes/sat/expose.cc +++ b/passes/sat/expose.cc @@ -83,8 +83,8 @@ static void find_dff_wires(std::set &dff_wires, RTLIL::Module *modu SigPool dffsignals; for (auto &it : module->cells_) { - if (ct.cell_known(it.second->type) && it.second->has("\\Q")) - dffsignals.add(sigmap(it.second->get("\\Q"))); + if (ct.cell_known(it.second->type) && it.second->hasPort("\\Q")) + dffsignals.add(sigmap(it.second->getPort("\\Q"))); } for (auto &it : module->wires_) { @@ -113,10 +113,10 @@ static void create_dff_dq_map(std::map &map, RTLIL: info.cell = it.second; if (info.cell->type == "$dff") { - info.bit_clk = sigmap(info.cell->get("\\CLK")).to_single_sigbit(); + info.bit_clk = sigmap(info.cell->getPort("\\CLK")).to_single_sigbit(); info.clk_polarity = info.cell->parameters.at("\\CLK_POLARITY").as_bool(); - std::vector sig_d = sigmap(info.cell->get("\\D")).to_sigbit_vector(); - std::vector sig_q = sigmap(info.cell->get("\\Q")).to_sigbit_vector(); + std::vector sig_d = sigmap(info.cell->getPort("\\D")).to_sigbit_vector(); + std::vector sig_q = sigmap(info.cell->getPort("\\Q")).to_sigbit_vector(); for (size_t i = 0; i < sig_d.size(); i++) { info.bit_d = sig_d.at(i); bit_info[sig_q.at(i)] = info; @@ -125,12 +125,12 @@ static void create_dff_dq_map(std::map &map, RTLIL: } if (info.cell->type == "$adff") { - info.bit_clk = sigmap(info.cell->get("\\CLK")).to_single_sigbit(); - info.bit_arst = sigmap(info.cell->get("\\ARST")).to_single_sigbit(); + info.bit_clk = sigmap(info.cell->getPort("\\CLK")).to_single_sigbit(); + info.bit_arst = sigmap(info.cell->getPort("\\ARST")).to_single_sigbit(); info.clk_polarity = info.cell->parameters.at("\\CLK_POLARITY").as_bool(); info.arst_polarity = info.cell->parameters.at("\\ARST_POLARITY").as_bool(); - std::vector sig_d = sigmap(info.cell->get("\\D")).to_sigbit_vector(); - std::vector sig_q = sigmap(info.cell->get("\\Q")).to_sigbit_vector(); + std::vector sig_d = sigmap(info.cell->getPort("\\D")).to_sigbit_vector(); + std::vector sig_q = sigmap(info.cell->getPort("\\Q")).to_sigbit_vector(); std::vector arst_value = info.cell->parameters.at("\\ARST_VALUE").bits; for (size_t i = 0; i < sig_d.size(); i++) { info.bit_d = sig_d.at(i); @@ -141,21 +141,21 @@ static void create_dff_dq_map(std::map &map, RTLIL: } if (info.cell->type == "$_DFF_N_" || info.cell->type == "$_DFF_P_") { - info.bit_clk = sigmap(info.cell->get("\\C")).to_single_sigbit(); + info.bit_clk = sigmap(info.cell->getPort("\\C")).to_single_sigbit(); info.clk_polarity = info.cell->type == "$_DFF_P_"; - info.bit_d = sigmap(info.cell->get("\\D")).to_single_sigbit(); - bit_info[sigmap(info.cell->get("\\Q")).to_single_sigbit()] = info; + info.bit_d = sigmap(info.cell->getPort("\\D")).to_single_sigbit(); + bit_info[sigmap(info.cell->getPort("\\Q")).to_single_sigbit()] = info; continue; } if (info.cell->type.size() == 10 && info.cell->type.substr(0, 6) == "$_DFF_") { - info.bit_clk = sigmap(info.cell->get("\\C")).to_single_sigbit(); - info.bit_arst = sigmap(info.cell->get("\\R")).to_single_sigbit(); + info.bit_clk = sigmap(info.cell->getPort("\\C")).to_single_sigbit(); + info.bit_arst = sigmap(info.cell->getPort("\\R")).to_single_sigbit(); info.clk_polarity = info.cell->type[6] == 'P'; info.arst_polarity = info.cell->type[7] == 'P'; info.arst_value = info.cell->type[0] == '1' ? RTLIL::State::S1 : RTLIL::State::S0; - info.bit_d = sigmap(info.cell->get("\\D")).to_single_sigbit(); - bit_info[sigmap(info.cell->get("\\Q")).to_single_sigbit()] = info; + info.bit_d = sigmap(info.cell->getPort("\\D")).to_single_sigbit(); + bit_info[sigmap(info.cell->getPort("\\Q")).to_single_sigbit()] = info; continue; } } @@ -504,11 +504,11 @@ struct ExposePass : public Pass { for (auto &cell_name : info.cells) { RTLIL::Cell *cell = module->cells_.at(cell_name); - std::vector cell_q_bits = sigmap(cell->get("\\Q")).to_sigbit_vector(); + std::vector cell_q_bits = sigmap(cell->getPort("\\Q")).to_sigbit_vector(); for (auto &bit : cell_q_bits) if (wire_bits_set.count(bit)) bit = RTLIL::SigBit(wire_dummy_q, wire_dummy_q->width++); - cell->set("\\Q", cell_q_bits); + cell->setPort("\\Q", cell_q_bits); } RTLIL::Wire *wire_q = add_new_wire(module, wire->name + sep + "q", wire->width); @@ -540,8 +540,8 @@ struct ExposePass : public Pass { c->parameters["\\A_SIGNED"] = 0; c->parameters["\\A_WIDTH"] = 1; c->parameters["\\Y_WIDTH"] = 1; - c->set("\\A", info.sig_clk); - c->set("\\Y", wire_c); + c->setPort("\\A", info.sig_clk); + c->setPort("\\Y", wire_c); } if (info.sig_arst != RTLIL::State::Sm) @@ -556,8 +556,8 @@ struct ExposePass : public Pass { c->parameters["\\A_SIGNED"] = 0; c->parameters["\\A_WIDTH"] = 1; c->parameters["\\Y_WIDTH"] = 1; - c->set("\\A", info.sig_arst); - c->set("\\Y", wire_r); + c->setPort("\\A", info.sig_arst); + c->setPort("\\Y", wire_r); } RTLIL::Wire *wire_v = add_new_wire(module, wire->name + sep + "v", wire->width); @@ -602,8 +602,8 @@ struct ExposePass : public Pass { log("New module port: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name), RTLIL::id2cstr(cell->type)); RTLIL::SigSpec sig; - if (cell->has(p->name)) - sig = cell->get(p->name); + if (cell->hasPort(p->name)) + sig = cell->getPort(p->name); sig.extend(w->width); if (w->port_input) module->connect(RTLIL::SigSig(sig, w)); diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index ad304c723..7b9fb2072 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -624,7 +624,7 @@ struct FreduceWorker bits_full_total += outputs.size(); } if (inv_mode && it.second->type == "$_INV_") - inv_pairs.insert(std::pair(sigmap(it.second->get("\\A")), sigmap(it.second->get("\\Y")))); + inv_pairs.insert(std::pair(sigmap(it.second->getPort("\\A")), sigmap(it.second->getPort("\\Y")))); } int bits_count = 0; @@ -719,8 +719,8 @@ struct FreduceWorker inv_sig = module->addWire(NEW_ID); RTLIL::Cell *inv_cell = module->addCell(NEW_ID, "$_INV_"); - inv_cell->set("\\A", grp[0].bit); - inv_cell->set("\\Y", inv_sig); + inv_cell->setPort("\\A", grp[0].bit); + inv_cell->setPort("\\Y", inv_sig); } module->connect(RTLIL::SigSig(grp[i].bit, inv_sig)); diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index ffd9f1b62..1475b855e 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -129,8 +129,8 @@ static void create_miter_equiv(struct Pass *that, std::vector args, RTLIL::Wire *w2 = miter_module->addWire("\\in_" + RTLIL::unescape_id(w1->name), w1->width); w2->port_input = true; - gold_cell->set(w1->name, w2); - gate_cell->set(w1->name, w2); + gold_cell->setPort(w1->name, w2); + gate_cell->setPort(w1->name, w2); } if (w1->port_output) @@ -141,8 +141,8 @@ static void create_miter_equiv(struct Pass *that, std::vector args, RTLIL::Wire *w2_gate = miter_module->addWire("\\gate_" + RTLIL::unescape_id(w1->name), w1->width); w2_gate->port_output = flag_make_outputs; - gold_cell->set(w1->name, w2_gold); - gate_cell->set(w1->name, w2_gate); + gold_cell->setPort(w1->name, w2_gold); + gate_cell->setPort(w1->name, w2_gate); RTLIL::SigSpec this_condition; @@ -156,9 +156,9 @@ static void create_miter_equiv(struct Pass *that, std::vector args, eqx_cell->parameters["\\Y_WIDTH"] = 1; eqx_cell->parameters["\\A_SIGNED"] = 0; eqx_cell->parameters["\\B_SIGNED"] = 0; - eqx_cell->set("\\A", RTLIL::SigSpec(w2_gold, i)); - eqx_cell->set("\\B", RTLIL::State::Sx); - eqx_cell->set("\\Y", gold_x.extract(i, 1)); + eqx_cell->setPort("\\A", RTLIL::SigSpec(w2_gold, i)); + eqx_cell->setPort("\\B", RTLIL::State::Sx); + eqx_cell->setPort("\\Y", gold_x.extract(i, 1)); } RTLIL::SigSpec gold_masked = miter_module->addWire(NEW_ID, w2_gold->width); @@ -170,9 +170,9 @@ static void create_miter_equiv(struct Pass *that, std::vector args, or_gold_cell->parameters["\\Y_WIDTH"] = w2_gold->width; or_gold_cell->parameters["\\A_SIGNED"] = 0; or_gold_cell->parameters["\\B_SIGNED"] = 0; - or_gold_cell->set("\\A", w2_gold); - or_gold_cell->set("\\B", gold_x); - or_gold_cell->set("\\Y", gold_masked); + or_gold_cell->setPort("\\A", w2_gold); + or_gold_cell->setPort("\\B", gold_x); + or_gold_cell->setPort("\\Y", gold_masked); RTLIL::Cell *or_gate_cell = miter_module->addCell(NEW_ID, "$or"); or_gate_cell->parameters["\\A_WIDTH"] = w2_gate->width; @@ -180,9 +180,9 @@ static void create_miter_equiv(struct Pass *that, std::vector args, or_gate_cell->parameters["\\Y_WIDTH"] = w2_gate->width; or_gate_cell->parameters["\\A_SIGNED"] = 0; or_gate_cell->parameters["\\B_SIGNED"] = 0; - or_gate_cell->set("\\A", w2_gate); - or_gate_cell->set("\\B", gold_x); - or_gate_cell->set("\\Y", gate_masked); + or_gate_cell->setPort("\\A", w2_gate); + or_gate_cell->setPort("\\B", gold_x); + or_gate_cell->setPort("\\Y", gate_masked); RTLIL::Cell *eq_cell = miter_module->addCell(NEW_ID, "$eqx"); eq_cell->parameters["\\A_WIDTH"] = w2_gold->width; @@ -190,10 +190,10 @@ static void create_miter_equiv(struct Pass *that, std::vector args, eq_cell->parameters["\\Y_WIDTH"] = 1; eq_cell->parameters["\\A_SIGNED"] = 0; eq_cell->parameters["\\B_SIGNED"] = 0; - eq_cell->set("\\A", gold_masked); - eq_cell->set("\\B", gate_masked); - eq_cell->set("\\Y", miter_module->addWire(NEW_ID)); - this_condition = eq_cell->get("\\Y"); + eq_cell->setPort("\\A", gold_masked); + eq_cell->setPort("\\B", gate_masked); + eq_cell->setPort("\\Y", miter_module->addWire(NEW_ID)); + this_condition = eq_cell->getPort("\\Y"); } else { @@ -203,10 +203,10 @@ static void create_miter_equiv(struct Pass *that, std::vector args, eq_cell->parameters["\\Y_WIDTH"] = 1; eq_cell->parameters["\\A_SIGNED"] = 0; eq_cell->parameters["\\B_SIGNED"] = 0; - eq_cell->set("\\A", w2_gold); - eq_cell->set("\\B", w2_gate); - eq_cell->set("\\Y", miter_module->addWire(NEW_ID)); - this_condition = eq_cell->get("\\Y"); + eq_cell->setPort("\\A", w2_gold); + eq_cell->setPort("\\B", w2_gate); + eq_cell->setPort("\\Y", miter_module->addWire(NEW_ID)); + this_condition = eq_cell->getPort("\\Y"); } if (flag_make_outcmp) @@ -225,15 +225,15 @@ static void create_miter_equiv(struct Pass *that, std::vector args, reduce_cell->parameters["\\A_WIDTH"] = all_conditions.size(); reduce_cell->parameters["\\Y_WIDTH"] = 1; reduce_cell->parameters["\\A_SIGNED"] = 0; - reduce_cell->set("\\A", all_conditions); - reduce_cell->set("\\Y", miter_module->addWire(NEW_ID)); - all_conditions = reduce_cell->get("\\Y"); + reduce_cell->setPort("\\A", all_conditions); + reduce_cell->setPort("\\Y", miter_module->addWire(NEW_ID)); + all_conditions = reduce_cell->getPort("\\Y"); } if (flag_make_assert) { RTLIL::Cell *assert_cell = miter_module->addCell(NEW_ID, "$assert"); - assert_cell->set("\\A", all_conditions); - assert_cell->set("\\EN", RTLIL::SigSpec(1, 1)); + assert_cell->setPort("\\A", all_conditions); + assert_cell->setPort("\\EN", RTLIL::SigSpec(1, 1)); } RTLIL::Wire *w_trigger = miter_module->addWire("\\trigger"); @@ -244,8 +244,8 @@ static void create_miter_equiv(struct Pass *that, std::vector args, not_cell->parameters["\\A_WIDTH"] = all_conditions.size(); not_cell->parameters["\\Y_WIDTH"] = w_trigger->width; not_cell->parameters["\\A_SIGNED"] = 0; - not_cell->set("\\A", all_conditions); - not_cell->set("\\Y", w_trigger); + not_cell->setPort("\\A", all_conditions); + not_cell->setPort("\\Y", w_trigger); miter_module->fixup_ports(); diff --git a/passes/sat/share.cc b/passes/sat/share.cc index 671a631dd..1041227ed 100644 --- a/passes/sat/share.cc +++ b/passes/sat/share.cc @@ -77,7 +77,7 @@ struct ShareWorker for (auto &pbit : portbits) { if (pbit.cell->type == "$mux" || pbit.cell->type == "$pmux") { - std::set bits = modwalker.sigmap(pbit.cell->get("\\S")).to_sigbit_set(); + std::set bits = modwalker.sigmap(pbit.cell->getPort("\\S")).to_sigbit_set(); terminal_bits.insert(bits.begin(), bits.end()); queue_bits.insert(bits.begin(), bits.end()); visited_cells.insert(pbit.cell); @@ -256,11 +256,11 @@ struct ShareWorker if (c1->parameters.at("\\A_SIGNED").as_bool() != c2->parameters.at("\\A_SIGNED").as_bool()) { RTLIL::Cell *unsigned_cell = c1->parameters.at("\\A_SIGNED").as_bool() ? c2 : c1; - if (unsigned_cell->get("\\A").to_sigbit_vector().back() != RTLIL::State::S0) { + if (unsigned_cell->getPort("\\A").to_sigbit_vector().back() != RTLIL::State::S0) { unsigned_cell->parameters.at("\\A_WIDTH") = unsigned_cell->parameters.at("\\A_WIDTH").as_int() + 1; - RTLIL::SigSpec new_a = unsigned_cell->get("\\A"); + RTLIL::SigSpec new_a = unsigned_cell->getPort("\\A"); new_a.append_bit(RTLIL::State::S0); - unsigned_cell->set("\\A", new_a); + unsigned_cell->setPort("\\A", new_a); } unsigned_cell->parameters.at("\\A_SIGNED") = true; unsigned_cell->check(); @@ -269,17 +269,17 @@ struct ShareWorker bool a_signed = c1->parameters.at("\\A_SIGNED").as_bool(); log_assert(a_signed == c2->parameters.at("\\A_SIGNED").as_bool()); - RTLIL::SigSpec a1 = c1->get("\\A"); - RTLIL::SigSpec y1 = c1->get("\\Y"); + RTLIL::SigSpec a1 = c1->getPort("\\A"); + RTLIL::SigSpec y1 = c1->getPort("\\Y"); - RTLIL::SigSpec a2 = c2->get("\\A"); - RTLIL::SigSpec y2 = c2->get("\\Y"); + RTLIL::SigSpec a2 = c2->getPort("\\A"); + RTLIL::SigSpec y2 = c2->getPort("\\Y"); int a_width = std::max(a1.size(), a2.size()); int y_width = std::max(y1.size(), y2.size()); - if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->get("\\Y"); - if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->get("\\Y"); + if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->getPort("\\Y"); + if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->getPort("\\Y"); RTLIL::SigSpec a = module->Mux(NEW_ID, a2, a1, act); RTLIL::Wire *y = module->addWire(NEW_ID, y_width); @@ -288,8 +288,8 @@ struct ShareWorker supercell->parameters["\\A_SIGNED"] = a_signed; supercell->parameters["\\A_WIDTH"] = a_width; supercell->parameters["\\Y_WIDTH"] = y_width; - supercell->set("\\A", a); - supercell->set("\\Y", y); + supercell->setPort("\\A", a); + supercell->setPort("\\Y", y); RTLIL::SigSpec new_y1(y, 0, y1.size()); RTLIL::SigSpec new_y2(y, 0, y2.size()); @@ -314,9 +314,9 @@ struct ShareWorker if (score_flipped < score_unflipped) { - RTLIL::SigSpec tmp = c2->get("\\A"); - c2->set("\\A", c2->get("\\B")); - c2->set("\\B", tmp); + RTLIL::SigSpec tmp = c2->getPort("\\A"); + c2->setPort("\\A", c2->getPort("\\B")); + c2->setPort("\\B", tmp); std::swap(c2->parameters.at("\\A_WIDTH"), c2->parameters.at("\\B_WIDTH")); std::swap(c2->parameters.at("\\A_SIGNED"), c2->parameters.at("\\B_SIGNED")); @@ -328,11 +328,11 @@ struct ShareWorker { RTLIL::Cell *unsigned_cell = c1->parameters.at("\\A_SIGNED").as_bool() ? c2 : c1; - if (unsigned_cell->get("\\A").to_sigbit_vector().back() != RTLIL::State::S0) { + if (unsigned_cell->getPort("\\A").to_sigbit_vector().back() != RTLIL::State::S0) { unsigned_cell->parameters.at("\\A_WIDTH") = unsigned_cell->parameters.at("\\A_WIDTH").as_int() + 1; - RTLIL::SigSpec new_a = unsigned_cell->get("\\A"); + RTLIL::SigSpec new_a = unsigned_cell->getPort("\\A"); new_a.append_bit(RTLIL::State::S0); - unsigned_cell->set("\\A", new_a); + unsigned_cell->setPort("\\A", new_a); } unsigned_cell->parameters.at("\\A_SIGNED") = true; modified_src_cells = true; @@ -341,11 +341,11 @@ struct ShareWorker if (c1->parameters.at("\\B_SIGNED").as_bool() != c2->parameters.at("\\B_SIGNED").as_bool()) { RTLIL::Cell *unsigned_cell = c1->parameters.at("\\B_SIGNED").as_bool() ? c2 : c1; - if (unsigned_cell->get("\\B").to_sigbit_vector().back() != RTLIL::State::S0) { + if (unsigned_cell->getPort("\\B").to_sigbit_vector().back() != RTLIL::State::S0) { unsigned_cell->parameters.at("\\B_WIDTH") = unsigned_cell->parameters.at("\\B_WIDTH").as_int() + 1; - RTLIL::SigSpec new_b = unsigned_cell->get("\\B"); + RTLIL::SigSpec new_b = unsigned_cell->getPort("\\B"); new_b.append_bit(RTLIL::State::S0); - unsigned_cell->set("\\B", new_b); + unsigned_cell->setPort("\\B", new_b); } unsigned_cell->parameters.at("\\B_SIGNED") = true; modified_src_cells = true; @@ -365,13 +365,13 @@ struct ShareWorker if (c1->type == "$shl" || c1->type == "$shr" || c1->type == "$sshl" || c1->type == "$sshr") b_signed = false; - RTLIL::SigSpec a1 = c1->get("\\A"); - RTLIL::SigSpec b1 = c1->get("\\B"); - RTLIL::SigSpec y1 = c1->get("\\Y"); + RTLIL::SigSpec a1 = c1->getPort("\\A"); + RTLIL::SigSpec b1 = c1->getPort("\\B"); + RTLIL::SigSpec y1 = c1->getPort("\\Y"); - RTLIL::SigSpec a2 = c2->get("\\A"); - RTLIL::SigSpec b2 = c2->get("\\B"); - RTLIL::SigSpec y2 = c2->get("\\Y"); + RTLIL::SigSpec a2 = c2->getPort("\\A"); + RTLIL::SigSpec b2 = c2->getPort("\\B"); + RTLIL::SigSpec y2 = c2->getPort("\\Y"); int a_width = std::max(a1.size(), a2.size()); int b_width = std::max(b1.size(), b2.size()); @@ -381,20 +381,20 @@ struct ShareWorker { a_width = std::max(y_width, a_width); - if (a1.size() < y1.size()) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, y1.size()), true)->get("\\Y"); - if (a2.size() < y2.size()) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, y2.size()), true)->get("\\Y"); + if (a1.size() < y1.size()) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, y1.size()), true)->getPort("\\Y"); + if (a2.size() < y2.size()) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, y2.size()), true)->getPort("\\Y"); - if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), false)->get("\\Y"); - if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), false)->get("\\Y"); + if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), false)->getPort("\\Y"); + if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), false)->getPort("\\Y"); } else { - if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->get("\\Y"); - if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->get("\\Y"); + if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->getPort("\\Y"); + if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->getPort("\\Y"); } - if (b1.size() != b_width) b1 = module->addPos(NEW_ID, b1, module->addWire(NEW_ID, b_width), b_signed)->get("\\Y"); - if (b2.size() != b_width) b2 = module->addPos(NEW_ID, b2, module->addWire(NEW_ID, b_width), b_signed)->get("\\Y"); + if (b1.size() != b_width) b1 = module->addPos(NEW_ID, b1, module->addWire(NEW_ID, b_width), b_signed)->getPort("\\Y"); + if (b2.size() != b_width) b2 = module->addPos(NEW_ID, b2, module->addWire(NEW_ID, b_width), b_signed)->getPort("\\Y"); RTLIL::SigSpec a = module->Mux(NEW_ID, a2, a1, act); RTLIL::SigSpec b = module->Mux(NEW_ID, b2, b1, act); @@ -406,9 +406,9 @@ struct ShareWorker supercell->parameters["\\A_WIDTH"] = a_width; supercell->parameters["\\B_WIDTH"] = b_width; supercell->parameters["\\Y_WIDTH"] = y_width; - supercell->set("\\A", a); - supercell->set("\\B", b); - supercell->set("\\Y", y); + supercell->setPort("\\A", a); + supercell->setPort("\\B", b); + supercell->setPort("\\Y", y); supercell->check(); RTLIL::SigSpec new_y1(y, 0, y1.size()); @@ -447,7 +447,7 @@ struct ShareWorker for (auto &bit : pbits) { if ((bit.cell->type == "$mux" || bit.cell->type == "$pmux") && bit.port == "\\S") - forbidden_controls_cache[cell].insert(bit.cell->get("\\S").extract(bit.offset, 1)); + forbidden_controls_cache[cell].insert(bit.cell->getPort("\\S").extract(bit.offset, 1)); consumer_cells.insert(bit.cell); } @@ -541,9 +541,9 @@ struct ShareWorker std::set used_in_b_parts; int width = c->parameters.at("\\WIDTH").as_int(); - std::vector sig_a = modwalker.sigmap(c->get("\\A")); - std::vector sig_b = modwalker.sigmap(c->get("\\B")); - std::vector sig_s = modwalker.sigmap(c->get("\\S")); + std::vector sig_a = modwalker.sigmap(c->getPort("\\A")); + std::vector sig_b = modwalker.sigmap(c->getPort("\\B")); + std::vector sig_s = modwalker.sigmap(c->getPort("\\S")); for (auto &bit : sig_a) if (cell_out_bits.count(bit)) diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc index ffe241182..7712d18b9 100644 --- a/passes/techmap/dfflibmap.cc +++ b/passes/techmap/dfflibmap.cc @@ -418,7 +418,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module) } else if (port.second != 0) log_abort(); - new_cell->set("\\" + port.first, sig); + new_cell->setPort("\\" + port.first, sig); } stats[stringf(" mapped %%d %s cells to %s cells.\n", cell_type.c_str(), new_cell->type.c_str())]++; diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index 060a87407..53bc00daf 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -127,7 +127,7 @@ namespace for (auto &conn : needleCell->connections()) { RTLIL::SigSpec needleSig = conn.second; - RTLIL::SigSpec haystackSig = haystackCell->get(portMapping.at(conn.first)); + RTLIL::SigSpec haystackSig = haystackCell->getPort(portMapping.at(conn.first)); for (int i = 0; i < std::min(needleSig.size(), haystackSig.size()); i++) { RTLIL::Wire *needleWire = needleSig[i].wire, *haystackWire = haystackSig[i].wire; @@ -304,7 +304,7 @@ namespace if (wire->port_id > 0) { for (int i = 0; i < wire->width; i++) sig2port.insert(sigmap(RTLIL::SigSpec(wire, i)), std::pair(wire->name, i)); - cell->set(wire->name, RTLIL::SigSpec(RTLIL::State::Sz, wire->width)); + cell->setPort(wire->name, RTLIL::SigSpec(RTLIL::State::Sz, wire->width)); } } @@ -323,10 +323,10 @@ namespace if (mapping.portMapping.count(conn.first) > 0 && sig2port.has(sigmap(sig))) { for (int i = 0; i < sig.size(); i++) for (auto &port : sig2port.find(sig[i])) { - RTLIL::SigSpec bitsig = haystack_cell->get(mapping.portMapping[conn.first]).extract(i, 1); - RTLIL::SigSpec new_sig = cell->get(port.first); + RTLIL::SigSpec bitsig = haystack_cell->getPort(mapping.portMapping[conn.first]).extract(i, 1); + RTLIL::SigSpec new_sig = cell->getPort(port.first); new_sig.replace(port.second, bitsig); - cell->set(port.first, new_sig); + cell->setPort(port.first, new_sig); } } } @@ -742,7 +742,7 @@ struct ExtractPass : public Pass { for (auto &chunk : chunks) if (chunk.wire != NULL) chunk.wire = newMod->wires_.at(chunk.wire->name); - newCell->set(conn.first, chunks); + newCell->setPort(conn.first, chunks); } } } diff --git a/passes/techmap/hilomap.cc b/passes/techmap/hilomap.cc index a3261dccd..784c4cf31 100644 --- a/passes/techmap/hilomap.cc +++ b/passes/techmap/hilomap.cc @@ -35,7 +35,7 @@ void hilomap_worker(RTLIL::SigSpec &sig) if (!singleton_mode || last_hi == RTLIL::State::Sm) { last_hi = module->addWire(NEW_ID); RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(hicell_celltype)); - cell->set(RTLIL::escape_id(hicell_portname), last_hi); + cell->setPort(RTLIL::escape_id(hicell_portname), last_hi); } bit = last_hi; } @@ -43,7 +43,7 @@ void hilomap_worker(RTLIL::SigSpec &sig) if (!singleton_mode || last_lo == RTLIL::State::Sm) { last_lo = module->addWire(NEW_ID); RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(locell_celltype)); - cell->set(RTLIL::escape_id(locell_portname), last_lo); + cell->setPort(RTLIL::escape_id(locell_portname), last_lo); } bit = last_lo; } diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc index 10627cd12..194e06a4a 100644 --- a/passes/techmap/iopadmap.cc +++ b/passes/techmap/iopadmap.cc @@ -172,9 +172,9 @@ struct IopadmapPass : public Pass { for (int i = 0; i < wire->width; i++) { RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype)); - cell->set(RTLIL::escape_id(portname), RTLIL::SigSpec(wire, i)); + cell->setPort(RTLIL::escape_id(portname), RTLIL::SigSpec(wire, i)); if (!portname2.empty()) - cell->set(RTLIL::escape_id(portname2), RTLIL::SigSpec(new_wire, i)); + cell->setPort(RTLIL::escape_id(portname2), RTLIL::SigSpec(new_wire, i)); if (!widthparam.empty()) cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(1); if (!nameparam.empty()) @@ -185,9 +185,9 @@ struct IopadmapPass : public Pass { else { RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype)); - cell->set(RTLIL::escape_id(portname), RTLIL::SigSpec(wire)); + cell->setPort(RTLIL::escape_id(portname), RTLIL::SigSpec(wire)); if (!portname2.empty()) - cell->set(RTLIL::escape_id(portname2), RTLIL::SigSpec(new_wire)); + cell->setPort(RTLIL::escape_id(portname2), RTLIL::SigSpec(new_wire)); if (!widthparam.empty()) cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(wire->width); if (!nameparam.empty()) diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc index 5c3e4c68f..f1f334f6e 100644 --- a/passes/techmap/simplemap.cc +++ b/passes/techmap/simplemap.cc @@ -28,22 +28,22 @@ extern void simplemap_get_mappers(std::mapget("\\A"); - RTLIL::SigSpec sig_y = cell->get("\\Y"); + RTLIL::SigSpec sig_a = cell->getPort("\\A"); + RTLIL::SigSpec sig_y = cell->getPort("\\Y"); sig_a.extend(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool()); for (int i = 0; i < SIZE(sig_y); i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, "$_INV_"); - gate->set("\\A", sig_a[i]); - gate->set("\\Y", sig_y[i]); + gate->setPort("\\A", sig_a[i]); + gate->setPort("\\Y", sig_y[i]); } } static void simplemap_pos(RTLIL::Module *module, RTLIL::Cell *cell) { - RTLIL::SigSpec sig_a = cell->get("\\A"); - RTLIL::SigSpec sig_y = cell->get("\\Y"); + RTLIL::SigSpec sig_a = cell->getPort("\\A"); + RTLIL::SigSpec sig_y = cell->getPort("\\Y"); sig_a.extend(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool()); @@ -52,8 +52,8 @@ static void simplemap_pos(RTLIL::Module *module, RTLIL::Cell *cell) static void simplemap_bu0(RTLIL::Module *module, RTLIL::Cell *cell) { - RTLIL::SigSpec sig_a = cell->get("\\A"); - RTLIL::SigSpec sig_y = cell->get("\\Y"); + RTLIL::SigSpec sig_a = cell->getPort("\\A"); + RTLIL::SigSpec sig_y = cell->getPort("\\Y"); sig_a.extend_u0(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool()); @@ -62,9 +62,9 @@ static void simplemap_bu0(RTLIL::Module *module, RTLIL::Cell *cell) static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell) { - RTLIL::SigSpec sig_a = cell->get("\\A"); - RTLIL::SigSpec sig_b = cell->get("\\B"); - RTLIL::SigSpec sig_y = cell->get("\\Y"); + RTLIL::SigSpec sig_a = cell->getPort("\\A"); + RTLIL::SigSpec sig_b = cell->getPort("\\B"); + RTLIL::SigSpec sig_y = cell->getPort("\\Y"); sig_a.extend_u0(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool()); sig_b.extend_u0(SIZE(sig_y), cell->parameters.at("\\B_SIGNED").as_bool()); @@ -75,8 +75,8 @@ static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell) for (int i = 0; i < SIZE(sig_y); i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, "$_INV_"); - gate->set("\\A", sig_t[i]); - gate->set("\\Y", sig_y[i]); + gate->setPort("\\A", sig_t[i]); + gate->setPort("\\Y", sig_y[i]); } sig_y = sig_t; @@ -91,16 +91,16 @@ static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell) for (int i = 0; i < SIZE(sig_y); i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); - gate->set("\\A", sig_a[i]); - gate->set("\\B", sig_b[i]); - gate->set("\\Y", sig_y[i]); + gate->setPort("\\A", sig_a[i]); + gate->setPort("\\B", sig_b[i]); + gate->setPort("\\Y", sig_y[i]); } } static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) { - RTLIL::SigSpec sig_a = cell->get("\\A"); - RTLIL::SigSpec sig_y = cell->get("\\Y"); + RTLIL::SigSpec sig_a = cell->getPort("\\A"); + RTLIL::SigSpec sig_y = cell->getPort("\\Y"); if (sig_y.size() == 0) return; @@ -141,9 +141,9 @@ static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) } RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); - gate->set("\\A", sig_a[i]); - gate->set("\\B", sig_a[i+1]); - gate->set("\\Y", sig_t[i/2]); + gate->setPort("\\A", sig_a[i]); + gate->setPort("\\B", sig_a[i+1]); + gate->setPort("\\Y", sig_t[i/2]); last_output_cell = gate; } @@ -153,8 +153,8 @@ static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) if (cell->type == "$reduce_xnor") { RTLIL::SigSpec sig_t = module->addWire(NEW_ID); RTLIL::Cell *gate = module->addCell(NEW_ID, "$_INV_"); - gate->set("\\A", sig_a); - gate->set("\\Y", sig_t); + gate->setPort("\\A", sig_a); + gate->setPort("\\Y", sig_t); last_output_cell = gate; sig_a = sig_t; } @@ -162,7 +162,7 @@ static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) if (last_output_cell == NULL) { module->connect(RTLIL::SigSig(sig_y, sig_a)); } else { - last_output_cell->set("\\Y", sig_y); + last_output_cell->setPort("\\Y", sig_y); } } @@ -180,9 +180,9 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig) } RTLIL::Cell *gate = module->addCell(NEW_ID, "$_OR_"); - gate->set("\\A", sig[i]); - gate->set("\\B", sig[i+1]); - gate->set("\\Y", sig_t[i/2]); + gate->setPort("\\A", sig[i]); + gate->setPort("\\B", sig[i+1]); + gate->setPort("\\Y", sig_t[i/2]); } sig = sig_t; @@ -194,10 +194,10 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig) static void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell) { - RTLIL::SigSpec sig_a = cell->get("\\A"); + RTLIL::SigSpec sig_a = cell->getPort("\\A"); logic_reduce(module, sig_a); - RTLIL::SigSpec sig_y = cell->get("\\Y"); + RTLIL::SigSpec sig_y = cell->getPort("\\Y"); if (sig_y.size() == 0) return; @@ -208,19 +208,19 @@ static void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell) } RTLIL::Cell *gate = module->addCell(NEW_ID, "$_INV_"); - gate->set("\\A", sig_a); - gate->set("\\Y", sig_y); + gate->setPort("\\A", sig_a); + gate->setPort("\\Y", sig_y); } static void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell) { - RTLIL::SigSpec sig_a = cell->get("\\A"); + RTLIL::SigSpec sig_a = cell->getPort("\\A"); logic_reduce(module, sig_a); - RTLIL::SigSpec sig_b = cell->get("\\B"); + RTLIL::SigSpec sig_b = cell->getPort("\\B"); logic_reduce(module, sig_b); - RTLIL::SigSpec sig_y = cell->get("\\Y"); + RTLIL::SigSpec sig_y = cell->getPort("\\Y"); if (sig_y.size() == 0) return; @@ -236,39 +236,39 @@ static void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell) log_assert(!gate_type.empty()); RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); - gate->set("\\A", sig_a); - gate->set("\\B", sig_b); - gate->set("\\Y", sig_y); + gate->setPort("\\A", sig_a); + gate->setPort("\\B", sig_b); + gate->setPort("\\Y", sig_y); } static void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell) { - RTLIL::SigSpec sig_a = cell->get("\\A"); - RTLIL::SigSpec sig_b = cell->get("\\B"); - RTLIL::SigSpec sig_y = cell->get("\\Y"); + RTLIL::SigSpec sig_a = cell->getPort("\\A"); + RTLIL::SigSpec sig_b = cell->getPort("\\B"); + RTLIL::SigSpec sig_y = cell->getPort("\\Y"); for (int i = 0; i < SIZE(sig_y); i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, "$_MUX_"); - gate->set("\\A", sig_a[i]); - gate->set("\\B", sig_b[i]); - gate->set("\\S", cell->get("\\S")); - gate->set("\\Y", sig_y[i]); + gate->setPort("\\A", sig_a[i]); + gate->setPort("\\B", sig_b[i]); + gate->setPort("\\S", cell->getPort("\\S")); + gate->setPort("\\Y", sig_y[i]); } } static void simplemap_slice(RTLIL::Module *module, RTLIL::Cell *cell) { int offset = cell->parameters.at("\\OFFSET").as_int(); - RTLIL::SigSpec sig_a = cell->get("\\A"); - RTLIL::SigSpec sig_y = cell->get("\\Y"); + RTLIL::SigSpec sig_a = cell->getPort("\\A"); + RTLIL::SigSpec sig_y = cell->getPort("\\Y"); module->connect(RTLIL::SigSig(sig_y, sig_a.extract(offset, sig_y.size()))); } static void simplemap_concat(RTLIL::Module *module, RTLIL::Cell *cell) { - RTLIL::SigSpec sig_ab = cell->get("\\A"); - sig_ab.append(cell->get("\\B")); - RTLIL::SigSpec sig_y = cell->get("\\Y"); + RTLIL::SigSpec sig_ab = cell->getPort("\\A"); + sig_ab.append(cell->getPort("\\B")); + RTLIL::SigSpec sig_y = cell->getPort("\\Y"); module->connect(RTLIL::SigSig(sig_y, sig_ab)); } @@ -278,17 +278,17 @@ static void simplemap_sr(RTLIL::Module *module, RTLIL::Cell *cell) char set_pol = cell->parameters.at("\\SET_POLARITY").as_bool() ? 'P' : 'N'; char clr_pol = cell->parameters.at("\\CLR_POLARITY").as_bool() ? 'P' : 'N'; - RTLIL::SigSpec sig_s = cell->get("\\SET"); - RTLIL::SigSpec sig_r = cell->get("\\CLR"); - RTLIL::SigSpec sig_q = cell->get("\\Q"); + RTLIL::SigSpec sig_s = cell->getPort("\\SET"); + RTLIL::SigSpec sig_r = cell->getPort("\\CLR"); + RTLIL::SigSpec sig_q = cell->getPort("\\Q"); std::string gate_type = stringf("$_SR_%c%c_", set_pol, clr_pol); for (int i = 0; i < width; i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); - gate->set("\\S", sig_s[i]); - gate->set("\\R", sig_r[i]); - gate->set("\\Q", sig_q[i]); + gate->setPort("\\S", sig_s[i]); + gate->setPort("\\R", sig_r[i]); + gate->setPort("\\Q", sig_q[i]); } } @@ -297,17 +297,17 @@ static void simplemap_dff(RTLIL::Module *module, RTLIL::Cell *cell) int width = cell->parameters.at("\\WIDTH").as_int(); char clk_pol = cell->parameters.at("\\CLK_POLARITY").as_bool() ? 'P' : 'N'; - RTLIL::SigSpec sig_clk = cell->get("\\CLK"); - RTLIL::SigSpec sig_d = cell->get("\\D"); - RTLIL::SigSpec sig_q = cell->get("\\Q"); + RTLIL::SigSpec sig_clk = cell->getPort("\\CLK"); + RTLIL::SigSpec sig_d = cell->getPort("\\D"); + RTLIL::SigSpec sig_q = cell->getPort("\\Q"); std::string gate_type = stringf("$_DFF_%c_", clk_pol); for (int i = 0; i < width; i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); - gate->set("\\C", sig_clk); - gate->set("\\D", sig_d[i]); - gate->set("\\Q", sig_q[i]); + gate->setPort("\\C", sig_clk); + gate->setPort("\\D", sig_d[i]); + gate->setPort("\\Q", sig_q[i]); } } @@ -318,21 +318,21 @@ static void simplemap_dffsr(RTLIL::Module *module, RTLIL::Cell *cell) char set_pol = cell->parameters.at("\\SET_POLARITY").as_bool() ? 'P' : 'N'; char clr_pol = cell->parameters.at("\\CLR_POLARITY").as_bool() ? 'P' : 'N'; - RTLIL::SigSpec sig_clk = cell->get("\\CLK"); - RTLIL::SigSpec sig_s = cell->get("\\SET"); - RTLIL::SigSpec sig_r = cell->get("\\CLR"); - RTLIL::SigSpec sig_d = cell->get("\\D"); - RTLIL::SigSpec sig_q = cell->get("\\Q"); + RTLIL::SigSpec sig_clk = cell->getPort("\\CLK"); + RTLIL::SigSpec sig_s = cell->getPort("\\SET"); + RTLIL::SigSpec sig_r = cell->getPort("\\CLR"); + RTLIL::SigSpec sig_d = cell->getPort("\\D"); + RTLIL::SigSpec sig_q = cell->getPort("\\Q"); std::string gate_type = stringf("$_DFFSR_%c%c%c_", clk_pol, set_pol, clr_pol); for (int i = 0; i < width; i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); - gate->set("\\C", sig_clk); - gate->set("\\S", sig_s[i]); - gate->set("\\R", sig_r[i]); - gate->set("\\D", sig_d[i]); - gate->set("\\Q", sig_q[i]); + gate->setPort("\\C", sig_clk); + gate->setPort("\\S", sig_s[i]); + gate->setPort("\\R", sig_r[i]); + gate->setPort("\\D", sig_d[i]); + gate->setPort("\\Q", sig_q[i]); } } @@ -346,20 +346,20 @@ static void simplemap_adff(RTLIL::Module *module, RTLIL::Cell *cell) while (int(rst_val.size()) < width) rst_val.push_back(RTLIL::State::S0); - RTLIL::SigSpec sig_clk = cell->get("\\CLK"); - RTLIL::SigSpec sig_rst = cell->get("\\ARST"); - RTLIL::SigSpec sig_d = cell->get("\\D"); - RTLIL::SigSpec sig_q = cell->get("\\Q"); + RTLIL::SigSpec sig_clk = cell->getPort("\\CLK"); + RTLIL::SigSpec sig_rst = cell->getPort("\\ARST"); + RTLIL::SigSpec sig_d = cell->getPort("\\D"); + RTLIL::SigSpec sig_q = cell->getPort("\\Q"); std::string gate_type_0 = stringf("$_DFF_%c%c0_", clk_pol, rst_pol); std::string gate_type_1 = stringf("$_DFF_%c%c1_", clk_pol, rst_pol); for (int i = 0; i < width; i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, rst_val.at(i) == RTLIL::State::S1 ? gate_type_1 : gate_type_0); - gate->set("\\C", sig_clk); - gate->set("\\R", sig_rst); - gate->set("\\D", sig_d[i]); - gate->set("\\Q", sig_q[i]); + gate->setPort("\\C", sig_clk); + gate->setPort("\\R", sig_rst); + gate->setPort("\\D", sig_d[i]); + gate->setPort("\\Q", sig_q[i]); } } @@ -368,17 +368,17 @@ static void simplemap_dlatch(RTLIL::Module *module, RTLIL::Cell *cell) int width = cell->parameters.at("\\WIDTH").as_int(); char en_pol = cell->parameters.at("\\EN_POLARITY").as_bool() ? 'P' : 'N'; - RTLIL::SigSpec sig_en = cell->get("\\EN"); - RTLIL::SigSpec sig_d = cell->get("\\D"); - RTLIL::SigSpec sig_q = cell->get("\\Q"); + RTLIL::SigSpec sig_en = cell->getPort("\\EN"); + RTLIL::SigSpec sig_d = cell->getPort("\\D"); + RTLIL::SigSpec sig_q = cell->getPort("\\Q"); std::string gate_type = stringf("$_DLATCH_%c_", en_pol); for (int i = 0; i < width; i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); - gate->set("\\E", sig_en); - gate->set("\\D", sig_d[i]); - gate->set("\\Q", sig_q[i]); + gate->setPort("\\E", sig_en); + gate->setPort("\\D", sig_d[i]); + gate->setPort("\\Q", sig_q[i]); } } diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index 4034f120e..946490135 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -38,7 +38,7 @@ static void create_gold_module(RTLIL::Design *design, std::string cell_type, std RTLIL::Wire *wire = module->addWire("\\A"); wire->width = 1 + xorshift32(8); wire->port_input = true; - cell->set("\\A", wire); + cell->setPort("\\A", wire); } if (cell_type_flags.find('B') != std::string::npos) { @@ -48,7 +48,7 @@ static void create_gold_module(RTLIL::Design *design, std::string cell_type, std else wire->width = 1 + xorshift32(8); wire->port_input = true; - cell->set("\\B", wire); + cell->setPort("\\B", wire); } if (cell_type_flags.find('S') != std::string::npos && xorshift32(2)) { @@ -69,7 +69,7 @@ static void create_gold_module(RTLIL::Design *design, std::string cell_type, std RTLIL::Wire *wire = module->addWire("\\Y"); wire->width = 1 + xorshift32(8); wire->port_output = true; - cell->set("\\Y", wire); + cell->setPort("\\Y", wire); } module->fixup_ports(); -- cgit v1.2.3 From 32a1cc3efdad7953af1805b245f2a0292698633a Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 31 Jul 2014 23:30:18 +0200 Subject: Renamed modwalker.h to modtools.h --- passes/memory/memory_share.cc | 11 ++++++----- passes/sat/share.cc | 11 ++++++----- 2 files changed, 12 insertions(+), 10 deletions(-) (limited to 'passes') diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index b6e7cc835..fde6ea007 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -17,13 +17,12 @@ * */ -#include "kernel/rtlil.h" +#include "kernel/yosys.h" #include "kernel/satgen.h" #include "kernel/sigtools.h" -#include "kernel/modwalker.h" -#include "kernel/register.h" -#include "kernel/log.h" -#include +#include "kernel/modtools.h" + +PRIVATE_NAMESPACE_BEGIN static bool memcells_cmp(RTLIL::Cell *a, RTLIL::Cell *b) { @@ -742,3 +741,5 @@ struct MemorySharePass : public Pass { } } MemorySharePass; +PRIVATE_NAMESPACE_END + diff --git a/passes/sat/share.cc b/passes/sat/share.cc index 1041227ed..ea7a9f631 100644 --- a/passes/sat/share.cc +++ b/passes/sat/share.cc @@ -17,13 +17,12 @@ * */ -#include "kernel/rtlil.h" +#include "kernel/yosys.h" #include "kernel/satgen.h" #include "kernel/sigtools.h" -#include "kernel/modwalker.h" -#include "kernel/register.h" -#include "kernel/log.h" -#include +#include "kernel/modtools.h" + +PRIVATE_NAMESPACE_BEGIN struct ShareWorkerConfig { @@ -967,3 +966,5 @@ struct SharePass : public Pass { } } SharePass; +PRIVATE_NAMESPACE_END + -- cgit v1.2.3 From 03ef9a75c64f79596d6c931a1401184c33f9346b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 1 Aug 2014 03:55:51 +0200 Subject: Added "test_autotb -n " option --- passes/tests/test_autotb.cc | 36 +++++++++++++++++++++++++++--------- 1 file changed, 27 insertions(+), 9 deletions(-) (limited to 'passes') diff --git a/passes/tests/test_autotb.cc b/passes/tests/test_autotb.cc index f121089b1..844bcbc9c 100644 --- a/passes/tests/test_autotb.cc +++ b/passes/tests/test_autotb.cc @@ -17,12 +17,12 @@ * */ -#include "kernel/register.h" -#include "kernel/log.h" +#include "kernel/yosys.h" #include #include +#include -#define NUM_ITER 1000 +PRIVATE_NAMESPACE_BEGIN static std::string id(std::string internal_id) { @@ -70,7 +70,7 @@ static std::string idy(std::string str1, std::string str2 = std::string(), std:: return id(str1); } -static void autotest(FILE *f, RTLIL::Design *design) +static void autotest(FILE *f, RTLIL::Design *design, int num_iter) { fprintf(f, "module testbench;\n\n"); @@ -79,7 +79,7 @@ static void autotest(FILE *f, RTLIL::Design *design) fprintf(f, "reg [31:0] xorshift128_x = 123456789;\n"); fprintf(f, "reg [31:0] xorshift128_y = 362436069;\n"); fprintf(f, "reg [31:0] xorshift128_z = 521288629;\n"); - fprintf(f, "reg [31:0] xorshift128_w = 88675123;\n"); + fprintf(f, "reg [31:0] xorshift128_w = %u; // <-- seed value\n", int(time(NULL))); fprintf(f, "reg [31:0] xorshift128_t;\n\n"); fprintf(f, "task xorshift128;\n"); fprintf(f, "begin\n"); @@ -279,7 +279,7 @@ static void autotest(FILE *f, RTLIL::Design *design) fprintf(f, "begin\n"); fprintf(f, "\t$display(\"#OUT#\\n#OUT# ==== %s ====\");\n", idy(mod->name).c_str()); fprintf(f, "\t%s;\n", idy(mod->name, "reset").c_str()); - fprintf(f, "\tfor (i=0; i<%d; i=i+1) begin\n", NUM_ITER); + fprintf(f, "\tfor (i=0; i<%d; i=i+1) begin\n", num_iter); fprintf(f, "\t\tif (i %% 20 == 0) %s;\n", idy(mod->name, "print_header").c_str()); fprintf(f, "\t\t#100; %s;\n", idy(mod->name, "update_data").c_str()); fprintf(f, "\t\t#100; %s;\n", idy(mod->name, "update_clock").c_str()); @@ -307,7 +307,7 @@ struct TestAutotbBackend : public Backend { { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); - log(" test_autotb [filename]\n"); + log(" test_autotb [options] [filename]\n"); log("\n"); log("Automatically create primitive verilog test benches for all modules in the\n"); log("design. The generated testbenches toggle the input pins of the module in\n"); @@ -324,12 +324,30 @@ struct TestAutotbBackend : public Backend { log("value after initialization. This can e.g. be used to force a reset signal\n"); log("low in order to explore more inner states in a state machine.\n"); log("\n"); + log(" -n \n"); + log(" number of iterations the test bench shuld run (default = 1000)\n"); + log("\n"); } virtual void execute(FILE *&f, std::string filename, std::vector args, RTLIL::Design *design) { + int num_iter = 1000; + log_header("Executing TEST_AUTOTB backend (auto-generate pseudo-random test benches).\n"); - extra_args(f, filename, args, 1); - autotest(f, design); + + int argidx; + for (argidx = 1; argidx < SIZE(args); argidx++) + { + if (args[argidx] == "-n" && argidx+1 < SIZE(args)) { + num_iter = atoi(args[++argidx].c_str()); + continue; + } + break; + } + + extra_args(f, filename, args, argidx); + autotest(f, design, num_iter); } } TestAutotbBackend; +PRIVATE_NAMESPACE_END + -- cgit v1.2.3 From d13eb7e0999def2da03eb6ddef805145f7fd9c9a Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 1 Aug 2014 16:53:15 +0200 Subject: Added ModIndex helper class, some changes to RTLIL::Monitor --- passes/cmds/trace.cc | 6 +++--- passes/memory/memory_share.cc | 5 ++--- 2 files changed, 5 insertions(+), 6 deletions(-) (limited to 'passes') diff --git a/passes/cmds/trace.cc b/passes/cmds/trace.cc index b4bc45c20..6a5ea346e 100644 --- a/passes/cmds/trace.cc +++ b/passes/cmds/trace.cc @@ -34,9 +34,9 @@ struct TraceMonitor : public RTLIL::Monitor log("#TRACE# Module delete: %s\n", log_id(module)); } - virtual void notify_cell_connect(RTLIL::Cell *cell, const std::pair &conn) override + virtual void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, RTLIL::SigSpec &sig) override { - log("#TRACE# Cell connect: %s.%s.%s = %s\n", log_id(cell->module), log_id(cell), log_id(conn.first), log_signal(conn.second)); + log("#TRACE# Cell connect: %s.%s.%s = %s (was: %s)\n", log_id(cell->module), log_id(cell), log_id(port), log_signal(sig), log_signal(old_sig)); } virtual void notify_connect(RTLIL::Module *module, const RTLIL::SigSig &sigsig) override @@ -44,7 +44,7 @@ struct TraceMonitor : public RTLIL::Monitor log("#TRACE# Connection in module %s: %s = %s\n", log_id(module), log_signal(sigsig.first), log_signal(sigsig.second)); } - virtual void notify_new_connections(RTLIL::Module *module, const std::vector &sigsig_vec) override + virtual void notify_connect(RTLIL::Module *module, const std::vector &sigsig_vec) override { log("#TRACE# New connections in module %s:\n", log_id(module)); for (auto &sigsig : sigsig_vec) diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index fde6ea007..ace6eeaf1 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -735,9 +735,8 @@ struct MemorySharePass : public Pass { virtual void execute(std::vector args, RTLIL::Design *design) { log_header("Executing MEMORY_SHARE pass (consolidating $memrc/$memwr cells).\n"); extra_args(args, 1, design); - for (auto &mod_it : design->modules_) - if (design->selected(mod_it.second)) - MemoryShareWorker(design, mod_it.second); + for (auto module : design->selected_modules()) + MemoryShareWorker(design, module); } } MemorySharePass; -- cgit v1.2.3 From bd74ed7da467de11128c57c4c424febe4a7e2f39 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 1 Aug 2014 19:01:10 +0200 Subject: Replaced sha1 implementation --- passes/opt/opt_reduce.cc | 1 - passes/opt/opt_share.cc | 7 +------ passes/techmap/techmap.cc | 7 +------ 3 files changed, 2 insertions(+), 13 deletions(-) (limited to 'passes') diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc index 80ec89744..f947e9724 100644 --- a/passes/opt/opt_reduce.cc +++ b/passes/opt/opt_reduce.cc @@ -22,7 +22,6 @@ #include "kernel/sigtools.h" #include "kernel/log.h" #include "kernel/celltypes.h" -#include "libs/sha1/sha1.h" #include #include #include diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc index 26d19414a..3532b124e 100644 --- a/passes/opt/opt_share.cc +++ b/passes/opt/opt_share.cc @@ -107,12 +107,7 @@ struct OptShareWorker hash_string += "\n"; } - unsigned char hash[20]; - char hash_hex_string[41]; - sha1::calc(hash_string.c_str(), hash_string.size(), hash); - sha1::toHexString(hash, hash_hex_string); - cell_hash_cache[cell] = hash_hex_string; - + cell_hash_cache[cell] = sha1(hash_string); return cell_hash_cache[cell]; } #endif diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index c2e5960ff..1f812e52f 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -99,12 +99,7 @@ struct TechmapWorker connbits_map[bit] = std::pair(conn.first, i);stringf("%s %d", log_id(conn.first), i, bit.data); } - unsigned char hash[20]; - char hash_hex_string[41]; - sha1::calc(constmap_info.c_str(), constmap_info.size(), hash); - sha1::toHexString(hash, hash_hex_string); - - return stringf("$paramod$constmap$%s%s", hash_hex_string, tpl->name.c_str()); + return stringf("$paramod$constmap:%s%s", sha1(constmap_info).c_str(), tpl->name.c_str()); } TechmapWires techmap_find_special_wires(RTLIL::Module *module) -- cgit v1.2.3 From 14412e6c957a34381c33740426b35f7b90a446be Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 2 Aug 2014 00:45:25 +0200 Subject: Preparations for RTLIL::IdString redesign: cleanup of existing code --- passes/abc/abc.cc | 2 +- passes/cmds/delete.cc | 6 +++--- passes/cmds/design.cc | 2 +- passes/cmds/select.cc | 4 ++-- 4 files changed, 7 insertions(+), 7 deletions(-) (limited to 'passes') diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index 4b2e82ca7..196643578 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -193,7 +193,7 @@ static void extract_cell(RTLIL::Cell *cell, bool keepff) } } -static std::string remap_name(std::string abc_name) +static std::string remap_name(RTLIL::IdString abc_name) { std::stringstream sstr; sstr << "$abc$" << map_autoidx << "$" << abc_name.substr(1); diff --git a/passes/cmds/delete.cc b/passes/cmds/delete.cc index 67b4d939f..2a91bc9ea 100644 --- a/passes/cmds/delete.cc +++ b/passes/cmds/delete.cc @@ -64,7 +64,7 @@ struct DeletePass : public Pass { } extra_args(args, argidx, design); - std::vector delete_mods; + std::vector delete_mods; for (auto &mod_it : design->modules_) { @@ -92,8 +92,8 @@ struct DeletePass : public Pass { std::set delete_wires; std::set delete_cells; - std::set delete_procs; - std::set delete_mems; + std::set delete_procs; + std::set delete_mems; for (auto &it : module->wires_) if (design->selected(module, it.second)) diff --git a/passes/cmds/design.cc b/passes/cmds/design.cc index 41548f621..260e7b5d9 100644 --- a/passes/cmds/design.cc +++ b/passes/cmds/design.cc @@ -192,7 +192,7 @@ struct DesignPass : public Pass { for (auto mod : copy_src_modules) { - std::string trg_name = as_name.empty() ? mod->name : RTLIL::escape_id(as_name); + std::string trg_name = as_name.empty() ? std::string(mod->name) : RTLIL::escape_id(as_name); if (copy_to_design->modules_.count(trg_name)) delete copy_to_design->modules_.at(trg_name); diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index bbfa396ba..35ca2f474 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -547,7 +547,7 @@ static void select_filter_active_mod(RTLIL::Design *design, RTLIL::Selection &se return; } - std::vector del_list; + std::vector del_list; for (auto mod_name : sel.selected_modules) if (mod_name != design->selected_active_module) del_list.push_back(mod_name); @@ -1322,7 +1322,7 @@ struct CdPass : public Pass { template static int log_matches(const char *title, std::string pattern, T list) { - std::vector matches; + std::vector matches; for (auto &it : list) if (pattern.empty() || match_ids(it.first, pattern)) -- cgit v1.2.3 From b9bd22b8c8d46284fba4d4c1cbd09092a9ccc5c3 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 2 Aug 2014 13:11:01 +0200 Subject: More cleanups related to RTLIL::IdString usage --- passes/cmds/connwrappers.cc | 6 ++--- passes/cmds/show.cc | 24 +++++++++++--------- passes/cmds/splice.cc | 8 +++---- passes/cmds/splitnets.cc | 2 +- passes/fsm/fsm_detect.cc | 2 +- passes/fsm/fsm_export.cc | 2 +- passes/fsm/fsm_extract.cc | 4 ++-- passes/hierarchy/hierarchy.cc | 30 ++++++++++++------------- passes/hierarchy/submod.cc | 10 ++++----- passes/memory/memory_collect.cc | 8 +++---- passes/memory/memory_map.cc | 4 ++-- passes/memory/memory_unpack.cc | 6 ++--- passes/opt/opt_clean.cc | 7 +++--- passes/opt/opt_const.cc | 42 +++++++++++++++++----------------- passes/opt/opt_rmdff.cc | 2 +- passes/opt/opt_share.cc | 8 +++---- passes/proc/proc_clean.cc | 2 +- passes/sat/eval.cc | 2 +- passes/sat/expose.cc | 50 ++++++++++++++++++++--------------------- passes/sat/sat.cc | 6 ++--- passes/sat/share.cc | 4 ++-- passes/techmap/dfflibmap.cc | 4 ++-- passes/techmap/extract.cc | 30 ++++++++++++------------- passes/techmap/simplemap.cc | 6 ++--- passes/techmap/techmap.cc | 36 ++++++++++++++--------------- passes/tests/test_autotb.cc | 44 ++++++++++++++++++------------------ 26 files changed, 176 insertions(+), 173 deletions(-) (limited to 'passes') diff --git a/passes/cmds/connwrappers.cc b/passes/cmds/connwrappers.cc index 5125ff5e2..aac117169 100644 --- a/passes/cmds/connwrappers.cc +++ b/passes/cmds/connwrappers.cc @@ -30,8 +30,8 @@ struct ConnwrappersWorker bool is_signed; }; - std::set decl_celltypes; - std::map, portdecl_t> decls; + std::set decl_celltypes; + std::map, portdecl_t> decls; void add_port(std::string celltype, std::string portname, std::string widthparam, std::string signparam) { @@ -76,7 +76,7 @@ struct ConnwrappersWorker for (auto &conn : cell->connections()) { - std::pair key(cell->type, conn.first); + std::pair key(cell->type, conn.first); if (!decls.count(key)) continue; diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index a2dd8051b..bbc0ff44f 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -111,7 +111,7 @@ struct ShowWorker return stringf("style=\"setlinewidth(3)\", label=\"<%d>\"", bits); } - const char *findColor(std::string member_name) + const char *findColor(RTLIL::IdString member_name) { for (auto &s : color_selections) if (s.second.selected_member(module->name, member_name)) { @@ -121,20 +121,22 @@ struct ShowWorker return ""; } - const char *findLabel(std::string member_name) + const char *findLabel(RTLIL::IdString member_name) { for (auto &s : label_selections) - if (s.second.selected_member(module->name, RTLIL::escape_id(member_name))) + if (s.second.selected_member(module->name, member_name)) return escape(s.first); return escape(member_name, true); } - const char *escape(std::string id, bool is_name = false) + const char *escape(RTLIL::IdString id, bool is_name = false) { - if (id.size() == 0) + std::string id_str = id.str(); + + if (id_str.size() == 0) return ""; - if (id[0] == '$' && is_name) { + if (id_str[0] == '$' && is_name) { if (enumerateIds) { if (autonames.count(id) == 0) { autonames[id] = autonames.size() + 1; @@ -142,17 +144,17 @@ struct ShowWorker } id = stringf("_%d_", autonames[id]); } else if (abbreviateIds) { - const char *p = id.c_str(); + const char *p = id_str.c_str(); const char *q = strrchr(p, '$'); - id = std::string(q); + id_str = std::string(q); } } - if (id[0] == '\\') - id = id.substr(1); + if (id_str[0] == '\\') + id_str = id_str.substr(1); std::string str; - for (char ch : id) { + for (char ch : id_str) { if (ch == '\\' || ch == '"') str += "\\"; str += ch; diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc index 07c6150cc..ca71f7d8d 100644 --- a/passes/cmds/splice.cc +++ b/passes/cmds/splice.cc @@ -33,8 +33,8 @@ struct SpliceWorker bool sel_by_wire; bool sel_any_bit; bool no_outputs; - std::set ports; - std::set no_ports; + std::set ports; + std::set no_ports; CellTypes ct; SigMap sigmap; @@ -224,7 +224,7 @@ struct SpliceWorker for (auto &it : rework_wires) { - std::string orig_name = it.first->name; + RTLIL::IdString orig_name = it.first->name; module->rename(it.first, NEW_ID); RTLIL::Wire *new_port = module->addWire(orig_name, it.first); @@ -283,7 +283,7 @@ struct SplicePass : public Pass { bool sel_by_wire = false; bool sel_any_bit = false; bool no_outputs = false; - std::set ports, no_ports; + std::set ports, no_ports; size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc index 6b1dbe13c..a3daf2398 100644 --- a/passes/cmds/splitnets.cc +++ b/passes/cmds/splitnets.cc @@ -28,7 +28,7 @@ struct SplitnetsWorker void append_wire(RTLIL::Module *module, RTLIL::Wire *wire, int offset, int width, std::string format) { - std::string new_wire_name = wire->name; + std::string new_wire_name = wire->name.str(); if (format.size() > 0) new_wire_name += format.substr(0, 1); diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc index 6025de15b..5675dff50 100644 --- a/passes/fsm/fsm_detect.cc +++ b/passes/fsm/fsm_detect.cc @@ -26,7 +26,7 @@ static RTLIL::Module *module; static SigMap assign_map; -typedef std::pair sig2driver_entry_t; +typedef std::pair sig2driver_entry_t; static SigSet sig2driver, sig2user; static std::set muxtree_cells; static SigPool sig_at_port; diff --git a/passes/fsm/fsm_export.cc b/passes/fsm/fsm_export.cc index f6f9faa9b..97ccf91ea 100644 --- a/passes/fsm/fsm_export.cc +++ b/passes/fsm/fsm_export.cc @@ -62,7 +62,7 @@ void write_kiss2(struct RTLIL::Module *module, struct RTLIL::Cell *cell, std::st } else { kiss_name.assign(module->name); - kiss_name.append('-' + cell->name + ".kiss2"); + kiss_name.append('-' + cell->name.str() + ".kiss2"); } log("\n"); diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index cf2075fba..5e71c1f0c 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -31,7 +31,7 @@ static RTLIL::Module *module; static SigMap assign_map; -typedef std::pair sig2driver_entry_t; +typedef std::pair sig2driver_entry_t; static SigSet sig2driver, sig2trigger; static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL::SigSpec &ctrl, std::map &states, RTLIL::Const *reset_state = NULL) @@ -277,7 +277,7 @@ static void extract_fsm(RTLIL::Wire *wire) fsm_cell->parameters["\\ARST_POLARITY"] = RTLIL::Const(arst_polarity ? 1 : 0, 1); fsm_cell->setPort("\\CTRL_IN", ctrl_in); fsm_cell->setPort("\\CTRL_OUT", ctrl_out); - fsm_cell->parameters["\\NAME"] = RTLIL::Const(wire->name); + fsm_cell->parameters["\\NAME"] = RTLIL::Const(wire->name.str()); fsm_cell->attributes = wire->attributes; fsm_data.copy_to_cell(fsm_cell); diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 67b57a94d..28b4ad990 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -35,7 +35,7 @@ namespace { static void generate(RTLIL::Design *design, const std::vector &celltypes, const std::vector &portdecls) { - std::set found_celltypes; + std::set found_celltypes; for (auto i1 : design->modules_) for (auto i2 : i1.second->cells_) @@ -52,9 +52,9 @@ static void generate(RTLIL::Design *design, const std::vector &cell for (auto &celltype : found_celltypes) { - std::set portnames; - std::set parameters; - std::map portwidths; + std::set portnames; + std::set parameters; + std::map portwidths; log("Generate module for cell type %s:\n", celltype.c_str()); for (auto i1 : design->modules_) @@ -94,7 +94,7 @@ static void generate(RTLIL::Design *design, const std::vector &cell } while (portnames.size() > 0) { - std::string portname = *portnames.begin(); + RTLIL::IdString portname = *portnames.begin(); for (auto &decl : portdecls) if (decl.index == 0 && !fnmatch(decl.portname.c_str(), RTLIL::unescape_id(portname).c_str(), FNM_NOESCAPE)) { generate_port_decl_t d = decl; @@ -144,20 +144,20 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla RTLIL::Cell *cell = cell_it.second; if (cell->type.substr(0, 7) == "$array:") { - int pos_idx = cell->type.find_first_of(':'); - int pos_num = cell->type.find_first_of(':', pos_idx + 1); - int pos_type = cell->type.find_first_of(':', pos_num + 1); - int idx = atoi(cell->type.substr(pos_idx + 1, pos_num).c_str()); - int num = atoi(cell->type.substr(pos_num + 1, pos_type).c_str()); + int pos_idx = cell->type.str().find_first_of(':'); + int pos_num = cell->type.str().find_first_of(':', pos_idx + 1); + int pos_type = cell->type.str().find_first_of(':', pos_num + 1); + int idx = atoi(cell->type.str().substr(pos_idx + 1, pos_num).c_str()); + int num = atoi(cell->type.str().substr(pos_num + 1, pos_type).c_str()); array_cells[cell] = std::pair(idx, num); - cell->type = cell->type.substr(pos_type + 1); + cell->type = cell->type.str().substr(pos_type + 1); } if (design->modules_.count(cell->type) == 0) { - if (design->modules_.count("$abstract" + cell->type)) + if (design->modules_.count("$abstract" + cell->type.str())) { - cell->type = design->modules_.at("$abstract" + cell->type)->derive(design, cell->parameters); + cell->type = design->modules_.at("$abstract" + cell->type.str())->derive(design, cell->parameters); cell->parameters.clear(); did_something = true; continue; @@ -220,7 +220,7 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla for (auto &conn : cell->connections_) { int conn_size = conn.second.size(); - std::string portname = conn.first; + RTLIL::IdString portname = conn.first; if (portname.substr(0, 1) == "$") { int port_id = atoi(portname.substr(1).c_str()); for (auto &wire_it : mod->wires_) @@ -447,7 +447,7 @@ struct HierarchyPass : public Pass { bool did_something_once = false; while (did_something) { did_something = false; - std::vector modnames; + std::vector modnames; modnames.reserve(design->modules_.size()); for (auto &mod_it : design->modules_) modnames.push_back(mod_it.first); diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index 2a47002ef..89f45e025 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -108,7 +108,7 @@ struct SubmodWorker design->add(new_mod); int port_counter = 1, auto_name_counter = 1; - std::set all_wire_names; + std::set all_wire_names; for (auto &it : wire_flags) { all_wire_names.insert(it.first->name); } @@ -134,7 +134,7 @@ struct SubmodWorker if (flags.is_int_driven && flags.is_ext_driven) new_wire_port_input = true, new_wire_port_output = true; - std::string new_wire_name = wire->name; + std::string new_wire_name = wire->name.str(); if (new_wire_port_input || new_wire_port_output) { while (new_wire_name[0] == '$') { std::string next_wire_name = stringf("\\n%d", auto_name_counter++); @@ -228,7 +228,7 @@ struct SubmodWorker if (submodules.count(submod_str) == 0) { submodules[submod_str].name = submod_str; - submodules[submod_str].full_name = module->name + "_" + submod_str; + submodules[submod_str].full_name = module->name.str() + "_" + submod_str; while (design->modules_.count(submodules[submod_str].full_name) != 0 || module->count_id(submodules[submod_str].full_name) != 0) submodules[submod_str].full_name += "_"; @@ -306,12 +306,12 @@ struct SubmodPass : public Pass { Pass::call(design, "opt_clean"); log_header("Continuing SUBMOD pass.\n"); - std::set handled_modules; + std::set handled_modules; bool did_something = true; while (did_something) { did_something = false; - std::vector queued_modules; + std::vector queued_modules; for (auto &mod_it : design->modules_) if (handled_modules.count(mod_it.first) == 0 && design->selected_whole_module(mod_it.first)) queued_modules.push_back(mod_it.first); diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc index 8887d1952..471a7d53a 100644 --- a/passes/memory/memory_collect.cc +++ b/passes/memory/memory_collect.cc @@ -62,7 +62,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) for (auto &cell_it : module->cells_) { RTLIL::Cell *cell = cell_it.second; - if ((cell->type == "$memwr" || cell->type == "$memrd") && cell->parameters["\\MEMID"].decode_string() == memory->name) + if ((cell->type == "$memwr" || cell->type == "$memrd") && memory->name == cell->parameters["\\MEMID"].decode_string()) memcells.push_back(cell); } @@ -70,7 +70,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) for (auto cell : memcells) { - if (cell->type == "$memwr" && cell->parameters["\\MEMID"].decode_string() == memory->name) + if (cell->type == "$memwr" && memory->name == cell->parameters["\\MEMID"].decode_string()) { wr_ports++; del_cells.push_back(cell); @@ -97,7 +97,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) sig_wr_en.append(en); } - if (cell->type == "$memrd" && cell->parameters["\\MEMID"].decode_string() == memory->name) + if (cell->type == "$memrd" && memory->name == cell->parameters["\\MEMID"].decode_string()) { rd_ports++; del_cells.push_back(cell); @@ -129,7 +129,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) sstr << "$mem$" << memory->name << "$" << (autoidx++); RTLIL::Cell *mem = module->addCell(sstr.str(), "$mem"); - mem->parameters["\\MEMID"] = RTLIL::Const(memory->name); + mem->parameters["\\MEMID"] = RTLIL::Const(memory->name.str()); mem->parameters["\\WIDTH"] = RTLIL::Const(memory->width); mem->parameters["\\OFFSET"] = RTLIL::Const(memory->start_offset); mem->parameters["\\SIZE"] = RTLIL::Const(memory->size); diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index f1917b972..8dc66f2cd 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -23,10 +23,10 @@ #include #include -static std::string genid(std::string name, std::string token1 = "", int i = -1, std::string token2 = "", int j = -1, std::string token3 = "", int k = -1, std::string token4 = "") +static std::string genid(RTLIL::IdString name, std::string token1 = "", int i = -1, std::string token2 = "", int j = -1, std::string token3 = "", int k = -1, std::string token4 = "") { std::stringstream sstr; - sstr << "$memory" << name << token1; + sstr << "$memory" << name.str() << token1; if (i >= 0) sstr << "[" << i << "]"; diff --git a/passes/memory/memory_unpack.cc b/passes/memory/memory_unpack.cc index 68e9a9697..5a4c4eac9 100644 --- a/passes/memory/memory_unpack.cc +++ b/passes/memory/memory_unpack.cc @@ -31,7 +31,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory) RTLIL::IdString mem_name = RTLIL::escape_id(memory->parameters.at("\\MEMID").decode_string()); while (module->memories.count(mem_name) != 0) - mem_name += stringf("_%d", autoidx++); + mem_name = mem_name.str() + stringf("_%d", autoidx++); RTLIL::Memory *mem = new RTLIL::Memory; mem->name = mem_name; @@ -47,7 +47,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory) for (int i = 0; i < num_rd_ports; i++) { RTLIL::Cell *cell = module->addCell(NEW_ID, "$memrd"); - cell->parameters["\\MEMID"] = mem_name; + cell->parameters["\\MEMID"] = mem_name.str(); cell->parameters["\\ABITS"] = memory->parameters.at("\\ABITS"); cell->parameters["\\WIDTH"] = memory->parameters.at("\\WIDTH"); cell->parameters["\\CLK_ENABLE"] = RTLIL::SigSpec(memory->parameters.at("\\RD_CLK_ENABLE")).extract(i, 1).as_const(); @@ -61,7 +61,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory) for (int i = 0; i < num_wr_ports; i++) { RTLIL::Cell *cell = module->addCell(NEW_ID, "$memwr"); - cell->parameters["\\MEMID"] = mem_name; + cell->parameters["\\MEMID"] = mem_name.str(); cell->parameters["\\ABITS"] = memory->parameters.at("\\ABITS"); cell->parameters["\\WIDTH"] = memory->parameters.at("\\WIDTH"); cell->parameters["\\CLK_ENABLE"] = RTLIL::SigSpec(memory->parameters.at("\\WR_CLK_ENABLE")).extract(i, 1).as_const(); diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 4182c6f5d..c620531e3 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -139,11 +139,12 @@ static bool compare_signals(RTLIL::SigBit &s1, RTLIL::SigBit &s2, SigPool ®s, static bool check_public_name(RTLIL::IdString id) { - if (id[0] == '$') + const std::string &id_str = id.str(); + if (id_str[0] == '$') return false; - if (id.substr(0, 2) == "\\_" && (id[id.size()-1] == '_' || id.find("_[") != std::string::npos)) + if (id_str.substr(0, 2) == "\\_" && (id_str[id_str.size()-1] == '_' || id_str.find("_[") != std::string::npos)) return false; - if (id.find(".$") != std::string::npos) + if (id_str.find(".$") != std::string::npos) return false; return true; } diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index 5dab5ecab..a13bb09cb 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -183,7 +183,7 @@ static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool com log("\n"); } - cover_list("opt.opt_const.fine.group", "$not", "$pos", "$bu0", "$and", "$or", "$xor", "$xnor", cell->type); + cover_list("opt.opt_const.fine.group", "$not", "$pos", "$bu0", "$and", "$or", "$xor", "$xnor", cell->type.str()); module->remove(cell); OPT_DID_SOMETHING = true; @@ -288,7 +288,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo } if (new_a != RTLIL::State::Sm && RTLIL::SigSpec(new_a) != sig_a) { - cover_list("opt.opt_const.fine.A", "$logic_not", "$logic_and", "$logic_or", "$reduce_or", "$reduce_bool", cell->type); + cover_list("opt.opt_const.fine.A", "$logic_not", "$logic_and", "$logic_or", "$reduce_or", "$reduce_bool", cell->type.str()); log("Replacing port A of %s cell `%s' in module `%s' with constant driver: %s -> %s\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a)); cell->setPort("\\A", sig_a = new_a); @@ -315,7 +315,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo } if (new_b != RTLIL::State::Sm && RTLIL::SigSpec(new_b) != sig_b) { - cover_list("opt.opt_const.fine.B", "$logic_and", "$logic_or", cell->type); + cover_list("opt.opt_const.fine.B", "$logic_and", "$logic_or", cell->type.str()); log("Replacing port B of %s cell `%s' in module `%s' with constant driver: %s -> %s\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_b), log_signal(new_b)); cell->setPort("\\B", sig_b = new_b); @@ -361,7 +361,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (0) { found_the_x_bit: cover_list("opt.opt_const.xbit", "$reduce_xor", "$reduce_xnor", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", - "$lt", "$le", "$ge", "$gt", "$neg", "$add", "$sub", "$mul", "$div", "$mod", "$pow", cell->type); + "$lt", "$le", "$ge", "$gt", "$neg", "$add", "$sub", "$mul", "$div", "$mod", "$pow", cell->type.str()); if (cell->type == "$reduce_xor" || cell->type == "$reduce_xnor" || cell->type == "$lt" || cell->type == "$le" || cell->type == "$ge" || cell->type == "$gt") replace_cell(assign_map, module, cell, "x-bit in input", "\\Y", RTLIL::State::Sx); @@ -373,13 +373,13 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if ((cell->type == "$_INV_" || cell->type == "$not" || cell->type == "$logic_not") && cell->getPort("\\Y").size() == 1 && invert_map.count(assign_map(cell->getPort("\\A"))) != 0) { - cover_list("opt.opt_const.invert.double", "$_INV_", "$not", "$logic_not", cell->type); + cover_list("opt.opt_const.invert.double", "$_INV_", "$not", "$logic_not", cell->type.str()); replace_cell(assign_map, module, cell, "double_invert", "\\Y", invert_map.at(assign_map(cell->getPort("\\A")))); goto next_cell; } if ((cell->type == "$_MUX_" || cell->type == "$mux") && invert_map.count(assign_map(cell->getPort("\\S"))) != 0) { - cover_list("opt.opt_const.invert.muxsel", "$_MUX_", "$mux", cell->type); + cover_list("opt.opt_const.invert.muxsel", "$_MUX_", "$mux", cell->type.str()); RTLIL::SigSpec tmp = cell->getPort("\\A"); cell->setPort("\\A", cell->getPort("\\B")); cell->setPort("\\B", tmp); @@ -497,7 +497,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo log_assert(SIZE(a) == SIZE(b)); for (int i = 0; i < SIZE(a); i++) { if (a[i].wire == NULL && b[i].wire == NULL && a[i] != b[i] && a[i].data <= RTLIL::State::S1 && b[i].data <= RTLIL::State::S1) { - cover_list("opt.opt_const.eqneq.isneq", "$eq", "$ne", "$eqx", "$nex", cell->type); + cover_list("opt.opt_const.eqneq.isneq", "$eq", "$ne", "$eqx", "$nex", cell->type.str()); RTLIL::SigSpec new_y = RTLIL::SigSpec((cell->type == "$eq" || cell->type == "$eqx") ? RTLIL::State::S0 : RTLIL::State::S1); new_y.extend(cell->parameters["\\Y_WIDTH"].as_int(), false); replace_cell(assign_map, module, cell, "isneq", "\\Y", new_y); @@ -510,7 +510,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo } if (new_a.size() == 0) { - cover_list("opt.opt_const.eqneq.empty", "$eq", "$ne", "$eqx", "$nex", cell->type); + cover_list("opt.opt_const.eqneq.empty", "$eq", "$ne", "$eqx", "$nex", cell->type.str()); RTLIL::SigSpec new_y = RTLIL::SigSpec((cell->type == "$eq" || cell->type == "$eqx") ? RTLIL::State::S1 : RTLIL::State::S0); new_y.extend(cell->parameters["\\Y_WIDTH"].as_int(), false); replace_cell(assign_map, module, cell, "empty", "\\Y", new_y); @@ -518,7 +518,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo } if (new_a.size() < a.size() || new_b.size() < b.size()) { - cover_list("opt.opt_const.eqneq.resize", "$eq", "$ne", "$eqx", "$nex", cell->type); + cover_list("opt.opt_const.eqneq.resize", "$eq", "$ne", "$eqx", "$nex", cell->type.str()); cell->setPort("\\A", new_a); cell->setPort("\\B", new_b); cell->parameters["\\A_WIDTH"] = new_a.size(); @@ -533,7 +533,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo RTLIL::SigSpec b = assign_map(cell->getPort("\\B")); if (a.is_fully_const()) { - cover_list("opt.opt_const.eqneq.swapconst", "$eq", "$ne", cell->type); + cover_list("opt.opt_const.eqneq.swapconst", "$eq", "$ne", cell->type.str()); RTLIL::SigSpec tmp = cell->getPort("\\A"); cell->setPort("\\A", cell->getPort("\\B")); cell->setPort("\\B", tmp); @@ -544,7 +544,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo RTLIL::SigSpec input = b; ACTION_DO("\\Y", cell->getPort("\\A")); } else { - cover_list("opt.opt_const.eqneq.isnot", "$eq", "$ne", cell->type); + cover_list("opt.opt_const.eqneq.isnot", "$eq", "$ne", cell->type.str()); cell->type = "$not"; cell->parameters.erase("\\B_WIDTH"); cell->parameters.erase("\\B_SIGNED"); @@ -603,9 +603,9 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (identity_wrt_a || identity_wrt_b) { if (identity_wrt_a) - cover_list("opt.opt_const.identwrt.a", "$add", "$sub", "$or", "$xor", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", "$mul", "$div", cell->type); + cover_list("opt.opt_const.identwrt.a", "$add", "$sub", "$or", "$xor", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", "$mul", "$div", cell->type.str()); if (identity_wrt_b) - cover_list("opt.opt_const.identwrt.b", "$add", "$sub", "$or", "$xor", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", "$mul", "$div", cell->type); + cover_list("opt.opt_const.identwrt.b", "$add", "$sub", "$or", "$xor", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", "$mul", "$div", cell->type.str()); log("Replacing %s cell `%s' in module `%s' with identity for port %c.\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str(), identity_wrt_a ? 'A' : 'B'); @@ -630,14 +630,14 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->getPort("\\A") == RTLIL::SigSpec(0, 1) && cell->getPort("\\B") == RTLIL::SigSpec(1, 1)) { - cover_list("opt.opt_const.mux_bool", "$mux", "$_MUX_", cell->type); + cover_list("opt.opt_const.mux_bool", "$mux", "$_MUX_", cell->type.str()); replace_cell(assign_map, module, cell, "mux_bool", "\\Y", cell->getPort("\\S")); goto next_cell; } if (mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->getPort("\\A") == RTLIL::SigSpec(1, 1) && cell->getPort("\\B") == RTLIL::SigSpec(0, 1)) { - cover_list("opt.opt_const.mux_invert", "$mux", "$_MUX_", cell->type); + cover_list("opt.opt_const.mux_invert", "$mux", "$_MUX_", cell->type.str()); cell->setPort("\\A", cell->getPort("\\S")); cell->unsetPort("\\B"); cell->unsetPort("\\S"); @@ -655,7 +655,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo } if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->getPort("\\A") == RTLIL::SigSpec(0, 1)) { - cover_list("opt.opt_const.mux_and", "$mux", "$_MUX_", cell->type); + cover_list("opt.opt_const.mux_and", "$mux", "$_MUX_", cell->type.str()); cell->setPort("\\A", cell->getPort("\\S")); cell->unsetPort("\\S"); if (cell->type == "$mux") { @@ -674,7 +674,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo } if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->getPort("\\B") == RTLIL::SigSpec(1, 1)) { - cover_list("opt.opt_const.mux_or", "$mux", "$_MUX_", cell->type); + cover_list("opt.opt_const.mux_or", "$mux", "$_MUX_", cell->type.str()); cell->setPort("\\B", cell->getPort("\\S")); cell->unsetPort("\\S"); if (cell->type == "$mux") { @@ -697,7 +697,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo int width = cell->getPort("\\A").size(); if ((cell->getPort("\\A").is_fully_undef() && cell->getPort("\\B").is_fully_undef()) || cell->getPort("\\S").is_fully_undef()) { - cover_list("opt.opt_const.mux_undef", "$mux", "$pmux", cell->type); + cover_list("opt.opt_const.mux_undef", "$mux", "$pmux", cell->type.str()); replace_cell(assign_map, module, cell, "mux_undef", "\\Y", cell->getPort("\\A")); goto next_cell; } @@ -716,17 +716,17 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo new_s = new_s.extract(0, new_s.size()-1); } if (new_s.size() == 0) { - cover_list("opt.opt_const.mux_empty", "$mux", "$pmux", cell->type); + cover_list("opt.opt_const.mux_empty", "$mux", "$pmux", cell->type.str()); replace_cell(assign_map, module, cell, "mux_empty", "\\Y", new_a); goto next_cell; } if (new_a == RTLIL::SigSpec(RTLIL::State::S0) && new_b == RTLIL::SigSpec(RTLIL::State::S1)) { - cover_list("opt.opt_const.mux_sel01", "$mux", "$pmux", cell->type); + cover_list("opt.opt_const.mux_sel01", "$mux", "$pmux", cell->type.str()); replace_cell(assign_map, module, cell, "mux_sel01", "\\Y", new_s); goto next_cell; } if (cell->getPort("\\S").size() != new_s.size()) { - cover_list("opt.opt_const.mux_reduce", "$mux", "$pmux", cell->type); + cover_list("opt.opt_const.mux_reduce", "$mux", "$pmux", cell->type.str()); cell->setPort("\\A", new_a); cell->setPort("\\B", new_b); cell->setPort("\\S", new_s); diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc index c1e33caf3..bbf94d3b4 100644 --- a/passes/opt/opt_rmdff.cc +++ b/passes/opt/opt_rmdff.cc @@ -178,7 +178,7 @@ struct OptRmdffPass : public Pass { dff_init_map.add(it.second, it.second->attributes.at("\\init")); mux_drivers.clear(); - std::vector dff_list; + std::vector dff_list; for (auto &it : mod_it.second->cells_) { if (it.second->type == "$mux" || it.second->type == "$pmux") { if (it.second->getPort("\\A").size() == it.second->getPort("\\B").size()) diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc index 3532b124e..eb970329d 100644 --- a/passes/opt/opt_share.cc +++ b/passes/opt/opt_share.cc @@ -60,10 +60,10 @@ struct OptShareWorker if (cell_hash_cache.count(cell) > 0) return cell_hash_cache[cell]; - std::string hash_string = cell->type + "\n"; + std::string hash_string = cell->type.str() + "\n"; for (auto &it : cell->parameters) - hash_string += "P " + it.first + "=" + it.second.as_string() + "\n"; + hash_string += "P " + it.first.str() + "=" + it.second.as_string() + "\n"; const std::map *conn = &cell->connections(); std::map alt_conn; @@ -95,10 +95,10 @@ struct OptShareWorker continue; RTLIL::SigSpec sig = it.second; assign_map.apply(sig); - hash_string += "C " + it.first + "="; + hash_string += "C " + it.first.str() + "="; for (auto &chunk : sig.chunks()) { if (chunk.wire) - hash_string += "{" + chunk.wire->name + " " + + hash_string += "{" + chunk.wire->name.str() + " " + int_to_hash_string(chunk.offset) + " " + int_to_hash_string(chunk.width) + "}"; else diff --git a/passes/proc/proc_clean.cc b/passes/proc/proc_clean.cc index e4c526632..13be0ddb6 100644 --- a/passes/proc/proc_clean.cc +++ b/passes/proc/proc_clean.cc @@ -150,7 +150,7 @@ struct ProcCleanPass : public Pass { extra_args(args, 1, design); for (auto mod : design->modules()) { - std::vector delme; + std::vector delme; if (!design->selected(mod)) continue; for (auto &proc_it : mod->processes) { diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc index 8a2dd929b..f07ad943c 100644 --- a/passes/sat/eval.cc +++ b/passes/sat/eval.cc @@ -471,7 +471,7 @@ struct EvalPass : public Pass { if (shows.size() == 0) { for (auto &it : module->wires_) if (it.second->port_output) - shows.push_back(it.second->name); + shows.push_back(it.second->name.str()); } if (tables.empty()) diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc index 25b9e1d11..affd685e4 100644 --- a/passes/sat/expose.cc +++ b/passes/sat/expose.cc @@ -27,7 +27,7 @@ struct dff_map_info_t { RTLIL::SigSpec sig_d, sig_clk, sig_arst; bool clk_polarity, arst_polarity; RTLIL::Const arst_value; - std::vector cells; + std::vector cells; }; struct dff_map_bit_info_t { @@ -37,7 +37,7 @@ struct dff_map_bit_info_t { RTLIL::Cell *cell; }; -static bool consider_wire(RTLIL::Wire *wire, std::map &dff_dq_map) +static bool consider_wire(RTLIL::Wire *wire, std::map &dff_dq_map) { if (wire->name[0] == '$' || dff_dq_map.count(wire->name)) return false; @@ -46,7 +46,7 @@ static bool consider_wire(RTLIL::Wire *wire, std::map &dff_cells, RTLIL::Cell *cell) +static bool consider_cell(RTLIL::Design *design, std::set &dff_cells, RTLIL::Cell *cell) { if (cell->name[0] == '$' || dff_cells.count(cell->name)) return false; @@ -73,7 +73,7 @@ static bool compare_cells(RTLIL::Cell *cell1, RTLIL::Cell *cell2) return true; } -static void find_dff_wires(std::set &dff_wires, RTLIL::Module *module) +static void find_dff_wires(std::set &dff_wires, RTLIL::Module *module) { CellTypes ct; ct.setup_internals_mem(); @@ -93,7 +93,7 @@ static void find_dff_wires(std::set &dff_wires, RTLIL::Module *modu } } -static void create_dff_dq_map(std::map &map, RTLIL::Design *design, RTLIL::Module *module) +static void create_dff_dq_map(std::map &map, RTLIL::Design *design, RTLIL::Module *module) { std::map bit_info; SigMap sigmap(module); @@ -160,7 +160,7 @@ static void create_dff_dq_map(std::map &map, RTLIL: } } - std::map empty_dq_map; + std::map empty_dq_map; for (auto &it : module->wires_) { if (!consider_wire(it.second, empty_dq_map)) @@ -208,7 +208,7 @@ static void create_dff_dq_map(std::map &map, RTLIL: } } -static RTLIL::Wire *add_new_wire(RTLIL::Module *module, std::string name, int width = 1) +static RTLIL::Wire *add_new_wire(RTLIL::Module *module, RTLIL::IdString name, int width = 1) { if (module->count_id(name)) log_error("Attempting to create wire %s, but a wire of this name exists already! Hint: Try another value for -sep.\n", log_id(name)); @@ -294,13 +294,13 @@ struct ExposePass : public Pass { CellTypes ct(design); - std::map> dff_dq_maps; - std::map> dff_cells; + std::map> dff_dq_maps; + std::map> dff_cells; if (flag_evert_dff) { RTLIL::Module *first_module = NULL; - std::set shared_dff_wires; + std::set shared_dff_wires; for (auto &mod_it : design->modules_) { @@ -317,7 +317,7 @@ struct ExposePass : public Pass { shared_dff_wires.insert(it.first); first_module = mod_it.second; } else { - std::set new_shared_dff_wires; + std::set new_shared_dff_wires; for (auto &it : shared_dff_wires) { if (!dff_dq_maps[mod_it.second].count(it)) continue; @@ -332,7 +332,7 @@ struct ExposePass : public Pass { if (flag_shared) for (auto &map_it : dff_dq_maps) { - std::map new_map; + std::map new_map; for (auto &it : map_it.second) if (shared_dff_wires.count(it.first)) new_map[it.first] = it.second; @@ -345,8 +345,8 @@ struct ExposePass : public Pass { dff_cells[it1.first].insert(it3); } - std::set shared_wires, shared_cells; - std::set used_names; + std::set shared_wires, shared_cells; + std::set used_names; if (flag_shared) { @@ -359,7 +359,7 @@ struct ExposePass : public Pass { if (!design->selected(module)) continue; - std::set dff_wires; + std::set dff_wires; if (flag_dff) find_dff_wires(dff_wires, module); @@ -379,7 +379,7 @@ struct ExposePass : public Pass { } else { - std::vector delete_shared_wires, delete_shared_cells; + std::vector delete_shared_wires, delete_shared_cells; for (auto &it : shared_wires) { @@ -441,7 +441,7 @@ struct ExposePass : public Pass { if (!design->selected(module)) continue; - std::set dff_wires; + std::set dff_wires; if (flag_dff && !flag_shared) find_dff_wires(dff_wires, module); @@ -467,7 +467,7 @@ struct ExposePass : public Pass { } if (flag_cut) { - RTLIL::Wire *in_wire = add_new_wire(module, it.second->name + sep + "i", it.second->width); + RTLIL::Wire *in_wire = add_new_wire(module, it.second->name.str() + sep + "i", it.second->width); in_wire->port_input = true; out_to_in_map.add(sigmap(it.second), in_wire); } @@ -511,7 +511,7 @@ struct ExposePass : public Pass { cell->setPort("\\Q", cell_q_bits); } - RTLIL::Wire *wire_q = add_new_wire(module, wire->name + sep + "q", wire->width); + RTLIL::Wire *wire_q = add_new_wire(module, wire->name.str() + sep + "q", wire->width); wire_q->port_input = true; log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_q->name)); @@ -525,12 +525,12 @@ struct ExposePass : public Pass { } module->connect(connect_q); - RTLIL::Wire *wire_d = add_new_wire(module, wire->name + sep + "d", wire->width); + RTLIL::Wire *wire_d = add_new_wire(module, wire->name.str() + sep + "d", wire->width); wire_d->port_output = true; log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_d->name)); module->connect(RTLIL::SigSig(wire_d, info.sig_d)); - RTLIL::Wire *wire_c = add_new_wire(module, wire->name + sep + "c"); + RTLIL::Wire *wire_c = add_new_wire(module, wire->name.str() + sep + "c"); wire_c->port_output = true; log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_c->name)); if (info.clk_polarity) { @@ -546,7 +546,7 @@ struct ExposePass : public Pass { if (info.sig_arst != RTLIL::State::Sm) { - RTLIL::Wire *wire_r = add_new_wire(module, wire->name + sep + "r"); + RTLIL::Wire *wire_r = add_new_wire(module, wire->name.str() + sep + "r"); wire_r->port_output = true; log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_r->name)); if (info.arst_polarity) { @@ -560,7 +560,7 @@ struct ExposePass : public Pass { c->setPort("\\Y", wire_r); } - RTLIL::Wire *wire_v = add_new_wire(module, wire->name + sep + "v", wire->width); + RTLIL::Wire *wire_v = add_new_wire(module, wire->name.str() + sep + "v", wire->width); wire_v->port_output = true; log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_v->name)); module->connect(RTLIL::SigSig(wire_v, info.arst_value)); @@ -593,7 +593,7 @@ struct ExposePass : public Pass { if (!p->port_input && !p->port_output) continue; - RTLIL::Wire *w = add_new_wire(module, cell->name + sep + RTLIL::unescape_id(p->name), p->width); + RTLIL::Wire *w = add_new_wire(module, cell->name.str() + sep + RTLIL::unescape_id(p->name), p->width); if (p->port_input) w->port_output = true; if (p->port_output) @@ -615,7 +615,7 @@ struct ExposePass : public Pass { { for (auto &it : cell->connections()) { - RTLIL::Wire *w = add_new_wire(module, cell->name + sep + RTLIL::unescape_id(it.first), it.second.size()); + RTLIL::Wire *w = add_new_wire(module, cell->name.str() + sep + RTLIL::unescape_id(it.first), it.second.size()); if (ct.cell_input(cell->type, it.first)) w->port_output = true; if (ct.cell_output(cell->type, it.first)) diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 430628e46..fd3d405a7 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -1160,19 +1160,19 @@ struct SatPass : public Pass { if (set_def_inputs) { for (auto &it : module->wires_) if (it.second->port_input) - sets_def.push_back(it.second->name); + sets_def.push_back(it.second->name.str()); } if (show_inputs) { for (auto &it : module->wires_) if (it.second->port_input) - shows.push_back(it.second->name); + shows.push_back(it.second->name.str()); } if (show_outputs) { for (auto &it : module->wires_) if (it.second->port_output) - shows.push_back(it.second->name); + shows.push_back(it.second->name.str()); } if (tempinduct) diff --git a/passes/sat/share.cc b/passes/sat/share.cc index ea7a9f631..4484d6771 100644 --- a/passes/sat/share.cc +++ b/passes/sat/share.cc @@ -29,13 +29,13 @@ struct ShareWorkerConfig bool opt_force; bool opt_aggressive; bool opt_fast; - std::set generic_uni_ops, generic_bin_ops, generic_cbin_ops; + std::set generic_uni_ops, generic_bin_ops, generic_cbin_ops; }; struct ShareWorker { ShareWorkerConfig config; - std::set generic_ops; + std::set generic_ops; RTLIL::Design *design; RTLIL::Module *module; diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc index 7712d18b9..16518b7df 100644 --- a/passes/techmap/dfflibmap.cc +++ b/passes/techmap/dfflibmap.cc @@ -29,7 +29,7 @@ struct cell_mapping { std::string cell_name; std::map ports; }; -static std::map cell_mappings; +static std::map cell_mappings; static void logmap(std::string dff) { @@ -319,7 +319,7 @@ static bool expand_cellmap(std::string pattern, std::string inv) bool return_status = false; for (auto &it : cell_mappings) { - std::string from = it.first, to = it.first; + std::string from = it.first.str(), to = it.first.str(); if (from.size() != pattern.size()) continue; for (size_t i = 0; i < from.size(); i++) { diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index 53bc00daf..6ebac265c 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -34,7 +34,7 @@ namespace { public: bool ignore_parameters; - std::set> ignored_parameters; + std::set> ignored_parameters; std::set cell_attr, wire_attr; SubCircuitSolver() : ignore_parameters(false) @@ -106,10 +106,10 @@ namespace if (!ignore_parameters) { std::map needle_param, haystack_param; for (auto &it : needleCell->parameters) - if (!ignored_parameters.count(std::pair(needleCell->type, it.first))) + if (!ignored_parameters.count(std::pair(needleCell->type, it.first))) needle_param[it.first] = unified_param(needleCell->type, it.first, it.second); for (auto &it : haystackCell->parameters) - if (!ignored_parameters.count(std::pair(haystackCell->type, it.first))) + if (!ignored_parameters.count(std::pair(haystackCell->type, it.first))) haystack_param[it.first] = unified_param(haystackCell->type, it.first, it.second); if (needle_param != haystack_param) return false; @@ -127,7 +127,7 @@ namespace for (auto &conn : needleCell->connections()) { RTLIL::SigSpec needleSig = conn.second; - RTLIL::SigSpec haystackSig = haystackCell->getPort(portMapping.at(conn.first)); + RTLIL::SigSpec haystackSig = haystackCell->getPort(portMapping.at(conn.first.str())); for (int i = 0; i < std::min(needleSig.size(), haystackSig.size()); i++) { RTLIL::Wire *needleWire = needleSig[i].wire, *haystackWire = haystackSig[i].wire; @@ -201,14 +201,14 @@ namespace if (sel && !sel->selected(mod, cell)) continue; - std::string type = cell->type; + std::string type = cell->type.str(); if (sel == NULL && type.substr(0, 2) == "\\$") type = type.substr(1); - graph.createNode(cell->name, type, (void*)cell); + graph.createNode(cell->name.str(), type, (void*)cell); for (auto &conn : cell->connections()) { - graph.createPort(cell->name, conn.first, conn.second.size()); + graph.createPort(cell->name.str(), conn.first.str(), conn.second.size()); if (split && split->count(std::pair(cell->type, conn.first)) > 0) continue; @@ -226,9 +226,9 @@ namespace if (bit == RTLIL::State::S0) node = "$const$0"; if (bit == RTLIL::State::S1) node = "$const$1"; if (bit == RTLIL::State::Sz) node = "$const$z"; - graph.createConnection(cell->name, conn.first, i, node, "\\Y", 0); + graph.createConnection(cell->name.str(), conn.first.str(), i, node, "\\Y", 0); } else - graph.createConstant(cell->name, conn.first, i, int(bit.data)); + graph.createConstant(cell->name.str(), conn.first.str(), i, int(bit.data)); continue; } @@ -246,7 +246,7 @@ namespace } bit_ref_t &bit_ref = sig_bit_ref[bit]; - graph.createConnection(bit_ref.cell, bit_ref.port, bit_ref.bit, cell->name, conn.first, i); + graph.createConnection(bit_ref.cell, bit_ref.port, bit_ref.bit, cell->name.str(), conn.first.str(), i); } } } @@ -293,7 +293,7 @@ namespace RTLIL::Cell *replace(RTLIL::Module *needle, RTLIL::Module *haystack, SubCircuit::Solver::Result &match) { SigMap sigmap(needle); - SigSet> sig2port; + SigSet> sig2port; // create new cell RTLIL::Cell *cell = haystack->addCell(stringf("$extract$%s$%d", needle->name.c_str(), autoidx++), needle->name); @@ -303,7 +303,7 @@ namespace RTLIL::Wire *wire = it.second; if (wire->port_id > 0) { for (int i = 0; i < wire->width; i++) - sig2port.insert(sigmap(RTLIL::SigSpec(wire, i)), std::pair(wire->name, i)); + sig2port.insert(sigmap(RTLIL::SigSpec(wire, i)), std::pair(wire->name, i)); cell->setPort(wire->name, RTLIL::SigSpec(RTLIL::State::Sz, wire->width)); } } @@ -320,10 +320,10 @@ namespace for (auto &conn : needle_cell->connections()) { RTLIL::SigSpec sig = sigmap(conn.second); - if (mapping.portMapping.count(conn.first) > 0 && sig2port.has(sigmap(sig))) { + if (mapping.portMapping.count(conn.first.str()) > 0 && sig2port.has(sigmap(sig))) { for (int i = 0; i < sig.size(); i++) for (auto &port : sig2port.find(sig[i])) { - RTLIL::SigSpec bitsig = haystack_cell->getPort(mapping.portMapping[conn.first]).extract(i, 1); + RTLIL::SigSpec bitsig = haystack_cell->getPort(mapping.portMapping[conn.first.str()]).extract(i, 1); RTLIL::SigSpec new_sig = cell->getPort(port.first); new_sig.replace(port.second, bitsig); cell->setPort(port.first, new_sig); @@ -561,7 +561,7 @@ struct ExtractPass : public Pass { continue; } if (args[argidx] == "-ignore_param" && argidx+2 < args.size()) { - solver.ignored_parameters.insert(std::pair(RTLIL::escape_id(args[argidx+1]), RTLIL::escape_id(args[argidx+2]))); + solver.ignored_parameters.insert(std::pair(RTLIL::escape_id(args[argidx+1]), RTLIL::escape_id(args[argidx+2]))); argidx += 2; continue; } diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc index f1f334f6e..960578b06 100644 --- a/passes/techmap/simplemap.cc +++ b/passes/techmap/simplemap.cc @@ -24,7 +24,7 @@ #include #include -extern void simplemap_get_mappers(std::map &mappers); +extern void simplemap_get_mappers(std::map &mappers); static void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell) { @@ -382,7 +382,7 @@ static void simplemap_dlatch(RTLIL::Module *module, RTLIL::Cell *cell) } } -void simplemap_get_mappers(std::map &mappers) +void simplemap_get_mappers(std::map &mappers) { mappers["$not"] = simplemap_not; mappers["$pos"] = simplemap_pos; @@ -431,7 +431,7 @@ struct SimplemapPass : public Pass { log_header("Executing SIMPLEMAP pass (map simple cells to gate primitives).\n"); extra_args(args, 1, design); - std::map mappers; + std::map mappers; simplemap_get_mappers(mappers); for (auto mod : design->modules()) { diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 1f812e52f..2bcd3003e 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -29,7 +29,7 @@ #include "passes/techmap/techmap.inc" // see simplemap.cc -extern void simplemap_get_mappers(std::map &mappers); +extern void simplemap_get_mappers(std::map &mappers); static void apply_prefix(std::string prefix, std::string &id) { @@ -44,7 +44,7 @@ static void apply_prefix(std::string prefix, RTLIL::SigSpec &sig, RTLIL::Module std::vector chunks = sig; for (auto &chunk : chunks) if (chunk.wire != NULL) { - std::string wire_name = chunk.wire->name; + std::string wire_name = chunk.wire->name.str(); apply_prefix(prefix, wire_name); log_assert(module->wires_.count(wire_name) > 0); chunk.wire = module->wires_[wire_name]; @@ -54,7 +54,7 @@ static void apply_prefix(std::string prefix, RTLIL::SigSpec &sig, RTLIL::Module struct TechmapWorker { - std::map simplemap_mappers; + std::map simplemap_mappers; std::map>, RTLIL::Module*> techmap_cache; std::map techmap_do_cache; std::set module_queue; @@ -80,7 +80,7 @@ struct TechmapWorker std::string constmap_tpl_name(SigMap &sigmap, RTLIL::Module *tpl, RTLIL::Cell *cell, bool verbose) { std::string constmap_info; - std::map> connbits_map; + std::map> connbits_map; for (auto conn : cell->connections()) for (int i = 0; i < SIZE(conn.second); i++) { @@ -96,7 +96,7 @@ struct TechmapWorker constmap_info += stringf("|%s %d %s %d", log_id(conn.first), i, log_id(connbits_map.at(bit).first), connbits_map.at(bit).second); } else - connbits_map[bit] = std::pair(conn.first, i);stringf("%s %d", log_id(conn.first), i, bit.data); + connbits_map[bit] = std::pair(conn.first, i);stringf("%s %d", log_id(conn.first), i, bit.data); } return stringf("$paramod$constmap:%s%s", sha1(constmap_info).c_str(), tpl->name.c_str()); @@ -156,7 +156,7 @@ struct TechmapWorker for (auto &it : tpl->cells_) if (it.first == "\\_TECHMAP_REPLACE_") { orig_cell_name = cell->name; - module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name); + module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name.str()); break; } @@ -165,8 +165,8 @@ struct TechmapWorker for (auto &it : tpl->wires_) { if (it.second->port_id > 0) positional_ports[stringf("$%d", it.second->port_id)] = it.first; - std::string w_name = it.second->name; - apply_prefix(cell->name, w_name); + std::string w_name = it.second->name.str(); + apply_prefix(cell->name.str(), w_name); RTLIL::Wire *w = module->addWire(w_name, it.second); w->port_input = false; w->port_output = false; @@ -192,11 +192,11 @@ struct TechmapWorker if (w->port_output) { c.first = it.second; c.second = RTLIL::SigSpec(w); - apply_prefix(cell->name, c.second, module); + apply_prefix(cell->name.str(), c.second, module); } else { c.first = RTLIL::SigSpec(w); c.second = it.second; - apply_prefix(cell->name, c.first, module); + apply_prefix(cell->name.str(), c.first, module); } if (c.second.size() > c.first.size()) c.second.remove(c.first.size(), c.second.size() - c.first.size()); @@ -219,12 +219,12 @@ struct TechmapWorker for (auto &it : tpl->cells_) { - RTLIL::IdString c_name = it.second->name; + std::string c_name = it.second->name.str(); if (!flatten_mode && c_name == "\\_TECHMAP_REPLACE_") c_name = orig_cell_name; else - apply_prefix(cell->name, c_name); + apply_prefix(cell->name.str(), c_name); RTLIL::Cell *c = module->addCell(c_name, it.second); design->select(module, c); @@ -233,15 +233,15 @@ struct TechmapWorker c->type = c->type.substr(1); for (auto &it2 : c->connections_) { - apply_prefix(cell->name, it2.second, module); + apply_prefix(cell->name.str(), it2.second, module); port_signal_map.apply(it2.second); } } for (auto &it : tpl->connections()) { RTLIL::SigSig c = it; - apply_prefix(cell->name, c.first, module); - apply_prefix(cell->name, c.second, module); + apply_prefix(cell->name.str(), c.first, module); + apply_prefix(cell->name.str(), c.second, module); port_signal_map.apply(c.first); port_signal_map.apply(c.second); module->connect(c); @@ -271,7 +271,7 @@ struct TechmapWorker continue; if (celltypeMap.count(cell->type) == 0) { - if (assert_mode && cell->type.back() != '_') + if (assert_mode && cell->type.str().back() != '_') log_error("(ASSERT MODE) No matching template cell for type %s found.\n", log_id(cell->type)); continue; } @@ -313,7 +313,7 @@ struct TechmapWorker for (auto &tpl_name : celltypeMap.at(cell->type)) { - std::string derived_name = tpl_name; + RTLIL::IdString derived_name = tpl_name; RTLIL::Module *tpl = map->modules_[tpl_name]; std::map parameters = cell->parameters; @@ -499,7 +499,7 @@ struct TechmapWorker if (!wire->port_input || wire->port_output) continue; - std::string port_name = wire->name; + RTLIL::IdString port_name = wire->name; tpl->rename(wire, NEW_ID); RTLIL::Wire *new_wire = tpl->addWire(port_name, wire); diff --git a/passes/tests/test_autotb.cc b/passes/tests/test_autotb.cc index 844bcbc9c..d26002277 100644 --- a/passes/tests/test_autotb.cc +++ b/passes/tests/test_autotb.cc @@ -109,8 +109,8 @@ static void autotest(FILE *f, RTLIL::Design *design, int num_iter) RTLIL::Wire *wire = it2->second; if (wire->port_output) { count_ports++; - signal_out[idy("sig", mod->name, wire->name)] = wire->width; - fprintf(f, "wire [%d:0] %s;\n", wire->width-1, idy("sig", mod->name, wire->name).c_str()); + signal_out[idy("sig", mod->name.str(), wire->name.str())] = wire->width; + fprintf(f, "wire [%d:0] %s;\n", wire->width-1, idy("sig", mod->name.str(), wire->name.str()).c_str()); } else if (wire->port_input) { count_ports++; bool is_clksignal = wire->get_bool_attribute("\\gentb_clock"); @@ -124,25 +124,25 @@ static void autotest(FILE *f, RTLIL::Design *design, int num_iter) is_clksignal = true; } if (is_clksignal && wire->attributes.count("\\gentb_constant") == 0) { - signal_clk[idy("sig", mod->name, wire->name)] = wire->width; + signal_clk[idy("sig", mod->name.str(), wire->name.str())] = wire->width; } else { - signal_in[idy("sig", mod->name, wire->name)] = wire->width; + signal_in[idy("sig", mod->name.str(), wire->name.str())] = wire->width; if (wire->attributes.count("\\gentb_constant") != 0) - signal_const[idy("sig", mod->name, wire->name)] = wire->attributes["\\gentb_constant"].as_string(); + signal_const[idy("sig", mod->name.str(), wire->name.str())] = wire->attributes["\\gentb_constant"].as_string(); } - fprintf(f, "reg [%d:0] %s;\n", wire->width-1, idy("sig", mod->name, wire->name).c_str()); + fprintf(f, "reg [%d:0] %s;\n", wire->width-1, idy("sig", mod->name.str(), wire->name.str()).c_str()); } } - fprintf(f, "%s %s(\n", id(mod->name).c_str(), idy("uut", mod->name).c_str()); + fprintf(f, "%s %s(\n", id(mod->name.str()).c_str(), idy("uut", mod->name.str()).c_str()); for (auto it2 = mod->wires_.begin(); it2 != mod->wires_.end(); it2++) { RTLIL::Wire *wire = it2->second; if (wire->port_output || wire->port_input) - fprintf(f, "\t.%s(%s)%s\n", id(wire->name).c_str(), - idy("sig", mod->name, wire->name).c_str(), --count_ports ? "," : ""); + fprintf(f, "\t.%s(%s)%s\n", id(wire->name.str()).c_str(), + idy("sig", mod->name.str(), wire->name.str()).c_str(), --count_ports ? "," : ""); } fprintf(f, ");\n\n"); - fprintf(f, "task %s;\n", idy(mod->name, "reset").c_str()); + fprintf(f, "task %s;\n", idy(mod->name.str(), "reset").c_str()); fprintf(f, "begin\n"); int delay_counter = 0; for (auto it = signal_in.begin(); it != signal_in.end(); it++) @@ -169,7 +169,7 @@ static void autotest(FILE *f, RTLIL::Design *design, int num_iter) fprintf(f, "end\n"); fprintf(f, "endtask\n\n"); - fprintf(f, "task %s;\n", idy(mod->name, "update_data").c_str()); + fprintf(f, "task %s;\n", idy(mod->name.str(), "update_data").c_str()); fprintf(f, "begin\n"); delay_counter = 0; for (auto it = signal_in.begin(); it != signal_in.end(); it++) { @@ -181,7 +181,7 @@ static void autotest(FILE *f, RTLIL::Design *design, int num_iter) fprintf(f, "end\n"); fprintf(f, "endtask\n\n"); - fprintf(f, "task %s;\n", idy(mod->name, "update_clock").c_str()); + fprintf(f, "task %s;\n", idy(mod->name.str(), "update_clock").c_str()); fprintf(f, "begin\n"); if (signal_clk.size()) { fprintf(f, "\txorshift128;\n"); @@ -203,7 +203,7 @@ static void autotest(FILE *f, RTLIL::Design *design, int num_iter) std::vector header1; std::string header2 = ""; - fprintf(f, "task %s;\n", idy(mod->name, "print_status").c_str()); + fprintf(f, "task %s;\n", idy(mod->name.str(), "print_status").c_str()); fprintf(f, "begin\n"); fprintf(f, "\t$display(\"#OUT# %%b %%b %%b %%t %%d\", {"); if (signal_in.size()) @@ -265,7 +265,7 @@ static void autotest(FILE *f, RTLIL::Design *design, int num_iter) fprintf(f, "end\n"); fprintf(f, "endtask\n\n"); - fprintf(f, "task %s;\n", idy(mod->name, "print_header").c_str()); + fprintf(f, "task %s;\n", idy(mod->name.str(), "print_header").c_str()); fprintf(f, "begin\n"); fprintf(f, "\t$display(\"#OUT#\");\n"); for (auto &hdr : header1) @@ -275,15 +275,15 @@ static void autotest(FILE *f, RTLIL::Design *design, int num_iter) fprintf(f, "end\n"); fprintf(f, "endtask\n\n"); - fprintf(f, "task %s;\n", idy(mod->name, "test").c_str()); + fprintf(f, "task %s;\n", idy(mod->name.str(), "test").c_str()); fprintf(f, "begin\n"); - fprintf(f, "\t$display(\"#OUT#\\n#OUT# ==== %s ====\");\n", idy(mod->name).c_str()); - fprintf(f, "\t%s;\n", idy(mod->name, "reset").c_str()); + fprintf(f, "\t$display(\"#OUT#\\n#OUT# ==== %s ====\");\n", idy(mod->name.str()).c_str()); + fprintf(f, "\t%s;\n", idy(mod->name.str(), "reset").c_str()); fprintf(f, "\tfor (i=0; i<%d; i=i+1) begin\n", num_iter); - fprintf(f, "\t\tif (i %% 20 == 0) %s;\n", idy(mod->name, "print_header").c_str()); - fprintf(f, "\t\t#100; %s;\n", idy(mod->name, "update_data").c_str()); - fprintf(f, "\t\t#100; %s;\n", idy(mod->name, "update_clock").c_str()); - fprintf(f, "\t\t#100; %s;\n", idy(mod->name, "print_status").c_str()); + fprintf(f, "\t\tif (i %% 20 == 0) %s;\n", idy(mod->name.str(), "print_header").c_str()); + fprintf(f, "\t\t#100; %s;\n", idy(mod->name.str(), "update_data").c_str()); + fprintf(f, "\t\t#100; %s;\n", idy(mod->name.str(), "update_clock").c_str()); + fprintf(f, "\t\t#100; %s;\n", idy(mod->name.str(), "print_status").c_str()); fprintf(f, "\tend\n"); fprintf(f, "end\n"); fprintf(f, "endtask\n\n"); @@ -294,7 +294,7 @@ static void autotest(FILE *f, RTLIL::Design *design, int num_iter) fprintf(f, "\t// $dumpvars(0, testbench);\n"); for (auto it = design->modules_.begin(); it != design->modules_.end(); it++) if (!it->second->get_bool_attribute("\\gentb_skip")) - fprintf(f, "\t%s;\n", idy(it->first, "test").c_str()); + fprintf(f, "\t%s;\n", idy(it->first.str(), "test").c_str()); fprintf(f, "\t$finish;\n"); fprintf(f, "end\n\n"); -- cgit v1.2.3 From 8fd1c269ac7322f21408c1f99e7e4c275789c056 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 2 Aug 2014 15:12:16 +0200 Subject: Fixed a performance bug in opt_reduce --- passes/opt/opt_reduce.cc | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'passes') diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc index f947e9724..5f3c4d29e 100644 --- a/passes/opt/opt_reduce.cc +++ b/passes/opt/opt_reduce.cc @@ -368,8 +368,12 @@ struct OptReducePass : public Pass { for (auto &mod_it : design->modules_) { if (!design->selected(mod_it.second)) continue; - OptReduceWorker worker(design, mod_it.second, do_fine); - total_count += worker.total_count; + do { + OptReduceWorker worker(design, mod_it.second, do_fine); + total_count += worker.total_count; + if (worker.total_count == 0) + break; + } while (1); } log("Performed a total of %d changes.\n", total_count); -- cgit v1.2.3 From 768eb846c4473040dc07bf62ce631c8a21474ae8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 2 Aug 2014 16:03:18 +0200 Subject: More bugfixes related to new RTLIL::IdString --- passes/cmds/select.cc | 6 +++--- passes/hierarchy/hierarchy.cc | 2 +- passes/sat/miter.cc | 6 +++--- passes/techmap/extract.cc | 2 +- passes/techmap/techmap.cc | 8 +++++--- 5 files changed, 13 insertions(+), 11 deletions(-) (limited to 'passes') diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index 35ca2f474..b4f4d26ae 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -490,7 +490,7 @@ static void select_op_expand(RTLIL::Design *design, std::string arg, char mode) for (auto i2 : i1.second) limits.insert(i2); } else - log_cmd_error("Selection %s is not defined!\n", RTLIL::id2cstr(str)); + log_cmd_error("Selection %s is not defined!\n", RTLIL::unescape_id(str).c_str()); } else limits.insert(RTLIL::escape_id(str)); } @@ -654,7 +654,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg) if (design->selection_vars.count(set_name) > 0) work_stack.push_back(design->selection_vars[set_name]); else - log_cmd_error("Selection @%s is not defined!\n", RTLIL::id2cstr(set_name)); + log_cmd_error("Selection @%s is not defined!\n", RTLIL::unescape_id(set_name).c_str()); select_filter_active_mod(design, work_stack.back()); return; } @@ -1315,7 +1315,7 @@ struct CdPass : public Pass { return; } - log_cmd_error("No such module `%s' found!\n", RTLIL::id2cstr(modname)); + log_cmd_error("No such module `%s' found!\n", RTLIL::unescape_id(modname).c_str()); } } CdPass; diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 28b4ad990..50b4989df 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -28,7 +28,7 @@ namespace { struct generate_port_decl_t { bool input, output; - std::string portname; + RTLIL::IdString portname; int index; }; } diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index 1475b855e..e51c92f9f 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -59,9 +59,9 @@ static void create_miter_equiv(struct Pass *that, std::vector args, if (argidx+3 != args.size() || args[argidx].substr(0, 1) == "-") that->cmd_error(args, argidx, "command argument error"); - std::string gold_name = RTLIL::escape_id(args[argidx++]); - std::string gate_name = RTLIL::escape_id(args[argidx++]); - std::string miter_name = RTLIL::escape_id(args[argidx++]); + RTLIL::IdString gold_name = RTLIL::escape_id(args[argidx++]); + RTLIL::IdString gate_name = RTLIL::escape_id(args[argidx++]); + RTLIL::IdString miter_name = RTLIL::escape_id(args[argidx++]); if (design->modules_.count(gold_name) == 0) log_cmd_error("Can't find gold module %s!\n", gold_name.c_str()); diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index 6ebac265c..06af2923b 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -700,7 +700,7 @@ struct ExtractPass : public Pass { log("\nFrequent SubCircuit with %d nodes and %d matches:\n", int(result.nodes.size()), result.totalMatchesAfterLimits); log(" primary match in %s:", id2cstr(haystack_map.at(result.graphId)->name)); for (auto &node : result.nodes) - log(" %s", id2cstr(node.nodeId)); + log(" %s", RTLIL::unescape_id(node.nodeId).c_str()); log("\n"); for (auto &it : result.matchesPerGraph) log(" matches in %s: %d\n", id2cstr(haystack_map.at(it.first)->name), it.second); diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 2bcd3003e..374fa9bf2 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -57,7 +57,7 @@ struct TechmapWorker std::map simplemap_mappers; std::map>, RTLIL::Module*> techmap_cache; std::map techmap_do_cache; - std::set module_queue; + std::set> module_queue; struct TechmapWireData { RTLIL::Wire *wire; @@ -479,7 +479,7 @@ struct TechmapWorker cmd_string = cmd_string.substr(strlen("CONSTMAP; ")); log("Analyzing pattern of constant bits for this cell:\n"); - std::string new_tpl_name = constmap_tpl_name(sigmap, tpl, cell, true); + RTLIL::IdString new_tpl_name = constmap_tpl_name(sigmap, tpl, cell, true); log("Creating constmapped module `%s'.\n", log_id(new_tpl_name)); log_assert(map->module(new_tpl_name) == nullptr); @@ -824,7 +824,9 @@ struct TechmapPass : public Pass { celltypeMap[it.first].insert(it.first); } - worker.module_queue = design->modules(); + for (auto module : design->modules()) + worker.module_queue.insert(module); + while (!worker.module_queue.empty()) { RTLIL::Module *module = *worker.module_queue.begin(); -- cgit v1.2.3 From 04727c7e0fb4c00b38999da192e4ada2a6f9474a Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 2 Aug 2014 18:58:40 +0200 Subject: No implicit conversion from IdString to anything else --- passes/abc/abc.cc | 2 +- passes/cmds/design.cc | 2 +- passes/cmds/select.cc | 4 ++-- passes/cmds/show.cc | 2 +- passes/fsm/fsm_export.cc | 2 +- passes/memory/memory_collect.cc | 2 +- passes/techmap/extract.cc | 4 ++-- passes/techmap/techmap.cc | 2 +- 8 files changed, 10 insertions(+), 10 deletions(-) (limited to 'passes') diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index 196643578..77419e616 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -303,7 +303,7 @@ static void handle_loops() id1 = id2; else if (edges[id1].size() > edges[id2].size()) continue; - else if (w1->name > w2->name) + else if (w2->name < w1->name) id1 = id2; } diff --git a/passes/cmds/design.cc b/passes/cmds/design.cc index 260e7b5d9..9f800c31f 100644 --- a/passes/cmds/design.cc +++ b/passes/cmds/design.cc @@ -192,7 +192,7 @@ struct DesignPass : public Pass { for (auto mod : copy_src_modules) { - std::string trg_name = as_name.empty() ? std::string(mod->name) : RTLIL::escape_id(as_name); + std::string trg_name = as_name.empty() ? mod->name.str() : RTLIL::escape_id(as_name); if (copy_to_design->modules_.count(trg_name)) delete copy_to_design->modules_.at(trg_name); diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index b4f4d26ae..2d49e85ed 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -1080,7 +1080,7 @@ struct SelectPass : public Pass { RTLIL::IdString mod_name = RTLIL::escape_id(args[++argidx]); if (design->modules_.count(mod_name) == 0) log_cmd_error("No such module: %s\n", id2cstr(mod_name)); - design->selected_active_module = mod_name; + design->selected_active_module = mod_name.str(); got_module = true; continue; } @@ -1304,7 +1304,7 @@ struct CdPass : public Pass { if (design->modules_.count(design->selected_active_module) > 0) module = design->modules_.at(design->selected_active_module); if (module != NULL && module->cells_.count(modname) > 0) - modname = module->cells_.at(modname)->type; + modname = module->cells_.at(modname)->type.str(); } if (design->modules_.count(modname) > 0) { diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index bbc0ff44f..cbc4725f7 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -322,7 +322,7 @@ struct ShowWorker else if (it.second->port_output) all_sinks.insert(stringf("n%d", id2num(it.first))); } else { - wires_on_demand[stringf("n%d", id2num(it.first))] = it.first; + wires_on_demand[stringf("n%d", id2num(it.first))] = it.first.str(); } } diff --git a/passes/fsm/fsm_export.cc b/passes/fsm/fsm_export.cc index 97ccf91ea..cb762dc1a 100644 --- a/passes/fsm/fsm_export.cc +++ b/passes/fsm/fsm_export.cc @@ -61,7 +61,7 @@ void write_kiss2(struct RTLIL::Module *module, struct RTLIL::Cell *cell, std::st kiss_name.assign(attr_it->second.decode_string()); } else { - kiss_name.assign(module->name); + kiss_name.assign(module->name.str()); kiss_name.append('-' + cell->name.str() + ".kiss2"); } diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc index 471a7d53a..9c670f00f 100644 --- a/passes/memory/memory_collect.cc +++ b/passes/memory/memory_collect.cc @@ -126,7 +126,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) } std::stringstream sstr; - sstr << "$mem$" << memory->name << "$" << (autoidx++); + sstr << "$mem$" << memory->name.str() << "$" << (autoidx++); RTLIL::Cell *mem = module->addCell(sstr.str(), "$mem"); mem->parameters["\\MEMID"] = RTLIL::Const(memory->name.str()); diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index 06af2923b..985d51e50 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -240,8 +240,8 @@ namespace if (sig_bit_ref.count(bit) == 0) { bit_ref_t &bit_ref = sig_bit_ref[bit]; - bit_ref.cell = cell->name; - bit_ref.port = conn.first; + bit_ref.cell = cell->name.str(); + bit_ref.port = conn.first.str(); bit_ref.bit = i; } diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 374fa9bf2..c639cc48d 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -155,7 +155,7 @@ struct TechmapWorker if (!flatten_mode) for (auto &it : tpl->cells_) if (it.first == "\\_TECHMAP_REPLACE_") { - orig_cell_name = cell->name; + orig_cell_name = cell->name.str(); module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name.str()); break; } -- cgit v1.2.3 From 8e7361f128ce00a742412931efcf7cbe5795a39a Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 2 Aug 2014 19:08:02 +0200 Subject: Removed at() method from RTLIL::IdString --- passes/sat/expose.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc index affd685e4..e856fdf76 100644 --- a/passes/sat/expose.cc +++ b/passes/sat/expose.cc @@ -50,7 +50,7 @@ static bool consider_cell(RTLIL::Design *design, std::set &dff_ { if (cell->name[0] == '$' || dff_cells.count(cell->name)) return false; - if (cell->type.at(0) == '\\' && !design->modules_.count(cell->type)) + if (cell->type[0] == '\\' && !design->modules_.count(cell->type)) return false; return true; } -- cgit v1.2.3 From b6acbc82e6a2954d453188a9997da2a30731ddac Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 2 Aug 2014 20:54:30 +0200 Subject: Bugfix in "techmap -extern" --- passes/techmap/techmap.cc | 1 + 1 file changed, 1 insertion(+) (limited to 'passes') diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index c639cc48d..74a515506 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -504,6 +504,7 @@ struct TechmapWorker RTLIL::Wire *new_wire = tpl->addWire(port_name, wire); wire->port_input = false; + wire->port_id = 0; for (int i = 0; i < wire->width; i++) { port_new2old_map[RTLIL::SigBit(new_wire, i)] = RTLIL::SigBit(wire, i); -- cgit v1.2.3 From 08ec33a5e573e0a59d2c1375e4e302a8485a6302 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 2 Aug 2014 21:55:13 +0200 Subject: Implemented simplemap support for "techmap -extern" --- passes/techmap/techmap.cc | 45 ++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 40 insertions(+), 5 deletions(-) (limited to 'passes') diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 74a515506..4a9a78918 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -326,8 +326,40 @@ struct TechmapWorker { if (extern_mode) { - log("WARNING: Mapping simplemap cell %s.%s (%s) in -extern mode is not supported yet.\n", log_id(module), log_id(cell), log_id(cell->type)); - break; + std::string m_name = stringf("$extern:simplemap:%s", log_id(cell->type)); + + for (auto &c : cell->parameters) + m_name += stringf(":%s=%s", log_id(c.first), log_signal(c.second)); + + RTLIL::Module *simplemap_module = design->module(m_name); + + if (simplemap_module == nullptr) + { + simplemap_module = design->addModule(m_name); + RTLIL::Cell *simplemap_cell = simplemap_module->addCell(cell->type, cell); + + int port_counter = 1; + for (auto &c : simplemap_cell->connections_) { + RTLIL::Wire *w = simplemap_module->addWire(c.first, SIZE(c.second)); + if (w->name == "\\Y" || w->name == "\\Q") + w->port_output = true; + else + w->port_input = true; + w->port_id = port_counter++; + c.second = w; + } + + simplemap_module->check(); + + log("Creating %s with simplemap.\n", log_id(simplemap_module)); + if (simplemap_mappers.count(simplemap_cell->type) == 0) + log_error("No simplemap mapper for cell type %s found!\n", RTLIL::id2cstr(simplemap_cell->type)); + simplemap_mappers.at(simplemap_cell->type)(simplemap_module, simplemap_cell); + simplemap_module->remove(simplemap_cell); + } + + cell->type = m_name; + cell->parameters.clear(); } else { @@ -337,10 +369,11 @@ struct TechmapWorker simplemap_mappers.at(cell->type)(module, cell); module->remove(cell); cell = NULL; - did_something = true; - mapped_cell = true; - break; } + + did_something = true; + mapped_cell = true; + break; } for (auto conn : cell->connections()) { @@ -538,6 +571,8 @@ struct TechmapWorker port_conn.second.append_bit(it.second); } tpl->connect(port_conn); + + tpl->check(); } Pass::call_on_module(map, tpl, cmd_string); -- cgit v1.2.3 From 9bb5298c104e83fef52d345772175be40301c7e3 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 3 Aug 2014 12:40:23 +0200 Subject: Fixes in show command (related to new IdString) --- passes/cmds/show.cc | 38 ++++++++++++++++++-------------------- 1 file changed, 18 insertions(+), 20 deletions(-) (limited to 'passes') diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index cbc4725f7..c15feb7b5 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -111,7 +111,7 @@ struct ShowWorker return stringf("style=\"setlinewidth(3)\", label=\"<%d>\"", bits); } - const char *findColor(RTLIL::IdString member_name) + const char *findColor(std::string member_name) { for (auto &s : color_selections) if (s.second.selected_member(module->name, member_name)) { @@ -121,7 +121,7 @@ struct ShowWorker return ""; } - const char *findLabel(RTLIL::IdString member_name) + const char *findLabel(std::string member_name) { for (auto &s : label_selections) if (s.second.selected_member(module->name, member_name)) @@ -129,14 +129,12 @@ struct ShowWorker return escape(member_name, true); } - const char *escape(RTLIL::IdString id, bool is_name = false) + const char *escape(std::string id, bool is_name = false) { - std::string id_str = id.str(); - - if (id_str.size() == 0) + if (id.size() == 0) return ""; - if (id_str[0] == '$' && is_name) { + if (id[0] == '$' && is_name) { if (enumerateIds) { if (autonames.count(id) == 0) { autonames[id] = autonames.size() + 1; @@ -144,17 +142,17 @@ struct ShowWorker } id = stringf("_%d_", autonames[id]); } else if (abbreviateIds) { - const char *p = id_str.c_str(); + const char *p = id.c_str(); const char *q = strrchr(p, '$'); - id_str = std::string(q); + id = std::string(q); } } - if (id_str[0] == '\\') - id_str = id_str.substr(1); + if (id[0] == '\\') + id = id.substr(1); std::string str; - for (char ch : id_str) { + for (char ch : id) { if (ch == '\\' || ch == '"') str += "\\"; str += ch; @@ -298,9 +296,9 @@ struct ShowWorker dot_id2num_store.clear(); net_conn_map.clear(); - fprintf(f, "digraph \"%s\" {\n", escape(module->name)); + fprintf(f, "digraph \"%s\" {\n", escape(module->name.str())); if (!notitle) - fprintf(f, "label=\"%s\";\n", escape(module->name)); + fprintf(f, "label=\"%s\";\n", escape(module->name.str())); fprintf(f, "rankdir=\"LR\";\n"); fprintf(f, "remincross=true;\n"); @@ -315,7 +313,7 @@ struct ShowWorker shape = "octagon"; if (it.first[0] == '\\') { fprintf(f, "n%d [ shape=%s, label=\"%s\", %s, fontcolor=\"black\" ];\n", - id2num(it.first), shape, findLabel(it.first), + id2num(it.first), shape, findLabel(it.first.str()), nextColor(RTLIL::SigSpec(it.second), "color=\"black\"").c_str()); if (it.second->port_input) all_sources.insert(stringf("n%d", id2num(it.first))); @@ -356,14 +354,14 @@ struct ShowWorker std::string label_string = "{{"; for (auto &p : in_ports) - label_string += stringf(" %s|", id2num(p), escape(p)); + label_string += stringf(" %s|", id2num(p), escape(p.str())); if (label_string[label_string.size()-1] == '|') label_string = label_string.substr(0, label_string.size()-1); - label_string += stringf("}|%s\\n%s|{", findLabel(it.first), escape(it.second->type)); + label_string += stringf("}|%s\\n%s|{", findLabel(it.first.str()), escape(it.second->type.str())); for (auto &p : out_ports) - label_string += stringf(" %s|", id2num(p), escape(p)); + label_string += stringf(" %s|", id2num(p), escape(p.str())); if (label_string[label_string.size()-1] == '|') label_string = label_string.substr(0, label_string.size()-1); @@ -382,7 +380,7 @@ struct ShowWorker else #endif fprintf(f, "c%d [ shape=record, label=\"%s\"%s ];\n%s", - id2num(it.first), label_string.c_str(), findColor(it.first), code.c_str()); + id2num(it.first), label_string.c_str(), findColor(it.first.str()), code.c_str()); } for (auto &it : module->processes) @@ -420,7 +418,7 @@ struct ShowWorker std::string proc_src = RTLIL::unescape_id(proc->name); if (proc->attributes.count("\\src") > 0) proc_src = proc->attributes.at("\\src").decode_string(); - fprintf(f, "p%d [shape=box, style=rounded, label=\"PROC %s\\n%s\"];\n", pidx, findLabel(proc->name), proc_src.c_str()); + fprintf(f, "p%d [shape=box, style=rounded, label=\"PROC %s\\n%s\"];\n", pidx, findLabel(proc->name.str()), proc_src.c_str()); } for (auto &conn : module->connections()) -- cgit v1.2.3 From 014a41fcf3463fae881413b4b366c2c2a6fb20de Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 3 Aug 2014 12:40:43 +0200 Subject: Implemented recursive techmap --- passes/techmap/techmap.cc | 78 +++++++++++++++++++++++++++++++++++++---------- 1 file changed, 62 insertions(+), 16 deletions(-) (limited to 'passes') diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 4a9a78918..29ce96766 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -69,12 +69,14 @@ struct TechmapWorker bool extern_mode; bool assert_mode; bool flatten_mode; + bool recursive_mode; TechmapWorker() { extern_mode = false; assert_mode = false; flatten_mode = false; + recursive_mode = false; } std::string constmap_tpl_name(SigMap &sigmap, RTLIL::Module *tpl, RTLIL::Cell *cell, bool verbose) @@ -139,8 +141,6 @@ struct TechmapWorker void techmap_module_worker(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Cell *cell, RTLIL::Module *tpl) { - log("Mapping `%s.%s' using `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(tpl->name)); - if (tpl->memories.size() != 0) log_error("Technology map yielded memories -> this is not supported.\n"); @@ -251,8 +251,10 @@ struct TechmapWorker } bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, std::set &handled_cells, - const std::map> &celltypeMap) + const std::map> &celltypeMap, bool in_recursion) { + std::string mapmsg_prefix = in_recursion ? "Recursively mapping" : "Mapping"; + if (!design->selected(module)) return false; @@ -270,9 +272,13 @@ struct TechmapWorker if (!design->selected(module, cell) || handled_cells.count(cell) > 0) continue; - if (celltypeMap.count(cell->type) == 0) { - if (assert_mode && cell->type.str().back() != '_') - log_error("(ASSERT MODE) No matching template cell for type %s found.\n", log_id(cell->type)); + std::string cell_type = cell->type.str(); + if (in_recursion && cell_type.substr(0, 2) == "\\$") + cell_type = cell_type.substr(1); + + if (celltypeMap.count(cell_type) == 0) { + if (assert_mode && cell_type.back() != '_') + log_error("(ASSERT MODE) No matching template cell for type %s found.\n", log_id(cell_type)); continue; } @@ -284,7 +290,7 @@ struct TechmapWorker if (SIZE(sig) == 0) continue; - for (auto &tpl_name : celltypeMap.at(cell->type)) { + for (auto &tpl_name : celltypeMap.at(cell_type)) { RTLIL::Module *tpl = map->modules_[tpl_name]; RTLIL::Wire *port = tpl->wire(conn.first); if (port && port->port_input) @@ -311,7 +317,11 @@ struct TechmapWorker log_assert(cell == module->cell(cell->name)); bool mapped_cell = false; - for (auto &tpl_name : celltypeMap.at(cell->type)) + std::string cell_type = cell->type.str(); + if (in_recursion && cell_type.substr(0, 2) == "\\$") + cell_type = cell_type.substr(1); + + for (auto &tpl_name : celltypeMap.at(cell_type)) { RTLIL::IdString derived_name = tpl_name; RTLIL::Module *tpl = map->modules_[tpl_name]; @@ -324,7 +334,9 @@ struct TechmapWorker { if (tpl->get_bool_attribute("\\techmap_simplemap")) { - if (extern_mode) + cell->type = cell_type; + + if (extern_mode && !in_recursion) { std::string m_name = stringf("$extern:simplemap:%s", log_id(cell->type)); @@ -358,12 +370,13 @@ struct TechmapWorker simplemap_module->remove(simplemap_cell); } - cell->type = m_name; + log("%s %s.%s (%s) to %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(simplemap_module)); + cell->type = simplemap_module->name; cell->parameters.clear(); } else { - log("Mapping %s.%s (%s) with simplemap.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); + log("%s %s.%s (%s) with simplemap.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type)); if (simplemap_mappers.count(cell->type) == 0) log_error("No simplemap mapper for cell type %s found!\n", RTLIL::id2cstr(cell->type)); simplemap_mappers.at(cell->type)(module, cell); @@ -507,6 +520,7 @@ struct TechmapWorker std::string cmd_string = data.value.as_const().decode_string(); + restart_eval_cmd_string: if (cmd_string.rfind("CONSTMAP; ", 0) == 0) { cmd_string = cmd_string.substr(strlen("CONSTMAP; ")); @@ -573,6 +587,14 @@ struct TechmapWorker tpl->connect(port_conn); tpl->check(); + goto restart_eval_cmd_string; + } + + if (cmd_string.rfind("RECURSION; ", 0) == 0) + { + cmd_string = cmd_string.substr(strlen("RECURSION; ")); + while (techmap_module(map, tpl, map, handled_cells, celltypeMap, true)) { } + goto restart_eval_cmd_string; } Pass::call_on_module(map, tpl, cmd_string); @@ -601,6 +623,14 @@ struct TechmapWorker for (auto &it : techmap_wire_names) log_error("Techmap special wire %s disappeared. This is considered a fatal error.\n", RTLIL::id2cstr(it)); + + if (recursive_mode) { + if (log_continue) { + log_header("Continuing TECHMAP pass.\n"); + log_continue = false; + } + while (techmap_module(map, tpl, map, handled_cells, celltypeMap, true)) { } + } } if (techmap_do_cache.at(tpl) == false) @@ -611,7 +641,7 @@ struct TechmapWorker log_continue = false; } - if (extern_mode) + if (extern_mode && !in_recursion) { std::string m_name = stringf("$extern:%s", log_id(tpl)); @@ -628,12 +658,13 @@ struct TechmapWorker module_queue.insert(m); } - log("Mapping %s.%s to imported %s.\n", log_id(module), log_id(cell), log_id(m_name)); + log("%s %s.%s to imported %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(m_name)); cell->type = m_name; cell->parameters.clear(); } else { + log("%s %s.%s using %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(tpl)); techmap_module_worker(design, module, cell, tpl); cell = NULL; } @@ -687,6 +718,11 @@ struct TechmapPass : public Pass { log(" -max_iter \n"); log(" only run the specified number of iterations.\n"); log("\n"); + log(" -recursive\n"); + log(" instead of the iterative breadth-first algorithm use a recursive\n"); + log(" depth-first algorithm. both methods should yield equivialent results,\n"); + log(" but may differ in performance.\n"); + log("\n"); log(" -assert\n"); log(" this option will cause techmap to exit with an error if it can't map\n"); log(" a selected cell. only cell types that end on an underscore are accepted\n"); @@ -736,6 +772,12 @@ struct TechmapPass : public Pass { log(" optimizied specializations of techmap modules without using the special\n"); log(" parameters described below.\n"); log("\n"); + log(" A _TECHMAP_DO_* command may start with the special token 'RECURSION; '.\n"); + log(" then techmap will recursively replace the cells in the module with their\n"); + log(" implementation. This is not affected by the -max_iter option.\n"); + log("\n"); + log(" It is possible to combine both prefixes to 'RECURSION; CONSTMAP; '.\n"); + log("\n"); log("In addition to this special wires, techmap also supports special parameters in\n"); log("modules in the map file:\n"); log("\n"); @@ -814,6 +856,10 @@ struct TechmapPass : public Pass { worker.extern_mode = true; continue; } + if (args[argidx] == "-recursive") { + worker.recursive_mode = true; + continue; + } break; } extra_args(args, argidx, design); @@ -872,7 +918,7 @@ struct TechmapPass : public Pass { std::set handled_cells; while (did_something) { did_something = false; - if (worker.techmap_module(design, module, map, handled_cells, celltypeMap)) + if (worker.techmap_module(design, module, map, handled_cells, celltypeMap, false)) did_something = true; if (did_something) module->check(); @@ -926,11 +972,11 @@ struct FlattenPass : public Pass { while (did_something) { did_something = false; if (top_mod != NULL) { - if (worker.techmap_module(design, top_mod, design, handled_cells, celltypeMap)) + if (worker.techmap_module(design, top_mod, design, handled_cells, celltypeMap, false)) did_something = true; } else { for (auto mod : design->modules()) - if (worker.techmap_module(design, mod, design, handled_cells, celltypeMap)) + if (worker.techmap_module(design, mod, design, handled_cells, celltypeMap, false)) did_something = true; } } -- cgit v1.2.3 From 0b02f6ca30a7bb5c3c8c34908aab8b8aa821c113 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 3 Aug 2014 15:02:05 +0200 Subject: Added "wreduce" command (work in progress) --- passes/cmds/Makefile.inc | 1 + passes/cmds/wreduce.cc | 252 +++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 253 insertions(+) create mode 100644 passes/cmds/wreduce.cc (limited to 'passes') diff --git a/passes/cmds/Makefile.inc b/passes/cmds/Makefile.inc index b55af9958..d6e45f2d1 100644 --- a/passes/cmds/Makefile.inc +++ b/passes/cmds/Makefile.inc @@ -20,4 +20,5 @@ OBJS += passes/cmds/write_file.o OBJS += passes/cmds/connwrappers.o OBJS += passes/cmds/cover.o OBJS += passes/cmds/trace.o +OBJS += passes/cmds/wreduce.o diff --git a/passes/cmds/wreduce.cc b/passes/cmds/wreduce.cc new file mode 100644 index 000000000..39881a831 --- /dev/null +++ b/passes/cmds/wreduce.cc @@ -0,0 +1,252 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" +#include "kernel/sigtools.h" +#include "kernel/modtools.h" + +#include + +USING_YOSYS_NAMESPACE +using namespace RTLIL; + +PRIVATE_NAMESPACE_BEGIN + +struct WreduceConfig +{ + std::set supported_cell_types; + + WreduceConfig() + { + supported_cell_types.insert("$not"); + supported_cell_types.insert("$pos"); + supported_cell_types.insert("$bu0"); + supported_cell_types.insert("$neg"); + + supported_cell_types.insert("$and"); + supported_cell_types.insert("$or"); + supported_cell_types.insert("$xor"); + supported_cell_types.insert("$xnor"); + + supported_cell_types.insert("$shl"); + supported_cell_types.insert("$shr"); + supported_cell_types.insert("$sshl"); + supported_cell_types.insert("$sshr"); + supported_cell_types.insert("$shift"); + supported_cell_types.insert("$shiftx"); + + supported_cell_types.insert("$lt"); + supported_cell_types.insert("$le"); + supported_cell_types.insert("$eq"); + supported_cell_types.insert("$ne"); + supported_cell_types.insert("$eqx"); + supported_cell_types.insert("$nex"); + supported_cell_types.insert("$ge"); + supported_cell_types.insert("$gt"); + + supported_cell_types.insert("$add"); + supported_cell_types.insert("$sub"); + // supported_cell_types.insert("$mul"); + // supported_cell_types.insert("$div"); + // supported_cell_types.insert("$mod"); + // supported_cell_types.insert("$pow"); + + // supported_cell_types.insert("$mux"); + // supported_cell_types.insert("$pmux"); + // supported_cell_types.insert("$safe_pmux"); + } +}; + +struct WreduceWorker +{ + WreduceConfig *config; + Module *module; + ModIndex mi; + + std::set> work_queue_cells; + std::set work_queue_bits; + SigMap constmap; + + WreduceWorker(WreduceConfig *config, Module *module) : + config(config), module(module), mi(module) { } + + void run_reduce_inport(Cell *cell, char port) + { + bool is_signed = cell->getParam(stringf("\\%c_SIGNED", port)).as_bool(); + SigSpec sig = mi.sigmap(cell->getPort(stringf("\\%c", port))); + + int bits_removed = 0; + if (is_signed) { + while (SIZE(sig) > 1 && constmap(sig[SIZE(sig)-1]) == constmap(sig[SIZE(sig)-2])) + work_queue_bits.insert(sig[SIZE(sig)-1]), sig.remove(SIZE(sig)-1), bits_removed++; + } else { + while (SIZE(sig) > 1 && constmap(sig[SIZE(sig)-1]) == S0) + work_queue_bits.insert(sig[SIZE(sig)-1]), sig.remove(SIZE(sig)-1), bits_removed++; + } + + if (bits_removed) { + log("Removed top %d bits (of %d) from port %c of cell %s.%s (%s).\n", + bits_removed, SIZE(sig) + bits_removed, port, log_id(module), log_id(cell), log_id(cell->type)); + cell->setPort(stringf("\\%c", port), sig); + } + } + + void run_cell(Cell *cell) + { + if (config->supported_cell_types.count(cell->type) == 0) + return; + + if (cell->type == ID("$shl") || cell->type == ID("$shr") || cell->type == ID("$sshl") || cell->type == ID("$sshr")) + cell->setParam("\\B_SIGNED", false); + + if (cell->hasParam("\\A_SIGNED")) + run_reduce_inport(cell, 'A'); + + if (cell->hasParam("\\B_SIGNED")) + run_reduce_inport(cell, 'B'); + + SigSpec sig = mi.sigmap(cell->getPort("\\Y")); + + int bits_removed = 0; + while (SIZE(sig) > 0) { + auto info = mi.query(sig[SIZE(sig)-1]); + if (info->is_output || SIZE(info->ports) > 1) + break; + sig.remove(SIZE(sig)-1); + bits_removed++; + } + + if (cell->type == ID("$not") || cell->type == ID("$pos") || cell->type == ID("$bu0") || cell->type == ID("$neg") || + cell->type == ID("$and") || cell->type == ID("$or") || cell->type == ID("$xor") || cell->type == ID("$xnor") || + cell->type == ID("$add") || cell->type == ID("$sub") || cell->type == ID("$mul")) + { + bool is_signed = cell->getParam("\\A_SIGNED").as_bool(); + + int a_size = 0, b_size = 0; + if (cell->hasPort("\\A")) a_size = SIZE(cell->getPort("\\A")); + if (cell->hasPort("\\B")) b_size = SIZE(cell->getPort("\\B")); + + while (SIZE(sig) > 1 && SIZE(sig) > std::max(a_size, b_size)) { + module->connect(sig[SIZE(sig)-1], is_signed ? sig[SIZE(sig)-2] : S0); + sig.remove(SIZE(sig)-1); + bits_removed++; + } + } + + if (bits_removed) { + log("Removed top %d bits (of %d) from port Y of cell %s.%s (%s).\n", + bits_removed, SIZE(sig) + bits_removed, log_id(module), log_id(cell), log_id(cell->type)); + cell->setPort("\\Y", sig); + } + + cell->fixup_parameters(); + } + + void run() + { + for (auto c : module->selected_cells()) + work_queue_cells.insert(c); + + while (!work_queue_cells.empty()) + { + work_queue_bits.clear(); + for (auto c : work_queue_cells) + run_cell(c); + + work_queue_cells.clear(); + for (auto bit : work_queue_bits) + for (auto port : mi.query_ports(bit)) + work_queue_cells.insert(port.cell); + } + + std::set removed_wire_bits; + + for (auto w : module->selected_wires()) + { + int bits_removed = 0; + while (w->width > 0) { + SigBit bit(w, w->width-1); + auto info = mi.query(bit); + if (info == nullptr || (!info->is_output && !info->is_input && !SIZE(info->ports))) { + removed_wire_bits.insert(bit); + bits_removed++; + w->width--; + continue; + } + break; + } + if (bits_removed) + log("Removed top %d bits (of %d) from wire %s.%s.\n", + bits_removed, SIZE(w) + bits_removed, log_id(module), log_id(w)); + } + + if (!removed_wire_bits.empty()) { + std::vector new_conn = module->connections(); + for (auto &ss : new_conn) { + SigSig new_ss; + for (int i = 0; i < SIZE(ss.first); i++) + if (!removed_wire_bits.count(ss.first[i]) && !removed_wire_bits.count(ss.second[i])) { + new_ss.first.append_bit(ss.first[i]); + new_ss.second.append_bit(ss.second[i]); + } + ss = std::move(new_ss); + } + module->new_connections(new_conn); + } + } +}; + +struct WreducePass : public Pass { + WreducePass() : Pass("wreduce", "reduce the word size of operations is possible") { } + virtual void help() + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" wreduce [options] [selection]\n"); + log("\n"); + log("This command reduces the word size of operations.\n"); + log("\n"); + } + virtual void execute(std::vector args, Design *design) + { + WreduceConfig config; + + log_header("Executing WREDCUE pass (reducing word size of cells).\n"); + + log_error("FIXME: This command is under construction.\n"); + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) { + break; + } + extra_args(args, argidx, design); + + for (auto module : design->selected_modules()) + { + if (module->has_processes_warn()) + continue; + + WreduceWorker worker(&config, module); + worker.run(); + } + } +} WreducePass; + +PRIVATE_NAMESPACE_END + -- cgit v1.2.3 From 027376515ac56251c82eedd961a9ffb2cc15a5a1 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 3 Aug 2014 20:02:42 +0200 Subject: Progress in "wreduce" pass --- passes/cmds/wreduce.cc | 59 ++++++++++++++------------------------------------ 1 file changed, 16 insertions(+), 43 deletions(-) (limited to 'passes') diff --git a/passes/cmds/wreduce.cc b/passes/cmds/wreduce.cc index 39881a831..bd0b315e7 100644 --- a/passes/cmds/wreduce.cc +++ b/passes/cmds/wreduce.cc @@ -124,17 +124,19 @@ struct WreduceWorker SigSpec sig = mi.sigmap(cell->getPort("\\Y")); int bits_removed = 0; - while (SIZE(sig) > 0) { + while (SIZE(sig) > 0) + { auto info = mi.query(sig[SIZE(sig)-1]); + if (info->is_output || SIZE(info->ports) > 1) break; + sig.remove(SIZE(sig)-1); bits_removed++; } - if (cell->type == ID("$not") || cell->type == ID("$pos") || cell->type == ID("$bu0") || cell->type == ID("$neg") || - cell->type == ID("$and") || cell->type == ID("$or") || cell->type == ID("$xor") || cell->type == ID("$xnor") || - cell->type == ID("$add") || cell->type == ID("$sub") || cell->type == ID("$mul")) + if (cell->type == ID("$pos") || cell->type == ID("$bu0") || cell->type == ID("$add") || cell->type == ID("$mul") || + cell->type == ID("$and") || cell->type == ID("$or") || cell->type == ID("$xor")) { bool is_signed = cell->getParam("\\A_SIGNED").as_bool(); @@ -142,7 +144,15 @@ struct WreduceWorker if (cell->hasPort("\\A")) a_size = SIZE(cell->getPort("\\A")); if (cell->hasPort("\\B")) b_size = SIZE(cell->getPort("\\B")); - while (SIZE(sig) > 1 && SIZE(sig) > std::max(a_size, b_size)) { + int max_y_size = std::max(a_size, b_size); + + if (cell->type == "$add") + max_y_size++; + + if (cell->type == "$mul") + max_y_size = a_size + b_size; + + while (SIZE(sig) > 1 && SIZE(sig) > max_y_size) { module->connect(sig[SIZE(sig)-1], is_signed ? sig[SIZE(sig)-2] : S0); sig.remove(SIZE(sig)-1); bits_removed++; @@ -174,41 +184,6 @@ struct WreduceWorker for (auto port : mi.query_ports(bit)) work_queue_cells.insert(port.cell); } - - std::set removed_wire_bits; - - for (auto w : module->selected_wires()) - { - int bits_removed = 0; - while (w->width > 0) { - SigBit bit(w, w->width-1); - auto info = mi.query(bit); - if (info == nullptr || (!info->is_output && !info->is_input && !SIZE(info->ports))) { - removed_wire_bits.insert(bit); - bits_removed++; - w->width--; - continue; - } - break; - } - if (bits_removed) - log("Removed top %d bits (of %d) from wire %s.%s.\n", - bits_removed, SIZE(w) + bits_removed, log_id(module), log_id(w)); - } - - if (!removed_wire_bits.empty()) { - std::vector new_conn = module->connections(); - for (auto &ss : new_conn) { - SigSig new_ss; - for (int i = 0; i < SIZE(ss.first); i++) - if (!removed_wire_bits.count(ss.first[i]) && !removed_wire_bits.count(ss.second[i])) { - new_ss.first.append_bit(ss.first[i]); - new_ss.second.append_bit(ss.second[i]); - } - ss = std::move(new_ss); - } - module->new_connections(new_conn); - } } }; @@ -227,9 +202,7 @@ struct WreducePass : public Pass { { WreduceConfig config; - log_header("Executing WREDCUE pass (reducing word size of cells).\n"); - - log_error("FIXME: This command is under construction.\n"); + log_header("Executing WREDUCE pass (reducing word size of cells).\n"); size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { -- cgit v1.2.3 From c7f99be3be828606cafc7d35b3612f5344065736 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 3 Aug 2014 20:19:50 +0200 Subject: Fixed "share" for memory read ports --- passes/sat/share.cc | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'passes') diff --git a/passes/sat/share.cc b/passes/sat/share.cc index 4484d6771..0c88b4d3c 100644 --- a/passes/sat/share.cc +++ b/passes/sat/share.cc @@ -419,6 +419,13 @@ struct ShareWorker return supercell; } + if (c1->type == "$memrd") + { + RTLIL::Cell *supercell = module->addCell(NEW_ID, c1); + module->connect(c2->getPort("\\DATA"), supercell->getPort("\\DATA")); + return supercell; + } + log_abort(); } -- cgit v1.2.3 From ebbbe7fc8360ca0bd8f840d3df1b77ab2fb569b6 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 4 Aug 2014 15:08:35 +0200 Subject: Added RTLIL::IdString::in(...) --- passes/cmds/wreduce.cc | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'passes') diff --git a/passes/cmds/wreduce.cc b/passes/cmds/wreduce.cc index bd0b315e7..9cef14f48 100644 --- a/passes/cmds/wreduce.cc +++ b/passes/cmds/wreduce.cc @@ -109,10 +109,10 @@ struct WreduceWorker void run_cell(Cell *cell) { - if (config->supported_cell_types.count(cell->type) == 0) + if (!cell->type.in(config->supported_cell_types)) return; - if (cell->type == ID("$shl") || cell->type == ID("$shr") || cell->type == ID("$sshl") || cell->type == ID("$sshr")) + if (cell->type.in("$shl", "$shr", "$sshl", "$sshr")) cell->setParam("\\B_SIGNED", false); if (cell->hasParam("\\A_SIGNED")) @@ -135,8 +135,7 @@ struct WreduceWorker bits_removed++; } - if (cell->type == ID("$pos") || cell->type == ID("$bu0") || cell->type == ID("$add") || cell->type == ID("$mul") || - cell->type == ID("$and") || cell->type == ID("$or") || cell->type == ID("$xor")) + if (cell->type.in("$pos", "$bu0", "$add", "$mul", "$and", "$or", "$xor")) { bool is_signed = cell->getParam("\\A_SIGNED").as_bool(); -- cgit v1.2.3 From 0bb694221832f250977437f29365bc5e17c4cd09 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 4 Aug 2014 15:33:51 +0200 Subject: Added "show -signed" --- passes/cmds/show.cc | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) (limited to 'passes') diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index c15feb7b5..4f6b811bc 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -45,6 +45,7 @@ struct ShowWorker RTLIL::Module *module; uint32_t currentColor; bool genWidthLabels; + bool genSignedLabels; bool stretchIO; bool enumerateIds; bool abbreviateIds; @@ -354,7 +355,9 @@ struct ShowWorker std::string label_string = "{{"; for (auto &p : in_ports) - label_string += stringf(" %s|", id2num(p), escape(p.str())); + label_string += stringf(" %s%s|", id2num(p), escape(p.str()), + genSignedLabels && it.second->hasParam(p.str() + "_SIGNED") && + it.second->getParam(p.str() + "_SIGNED").as_bool() ? "*" : ""); if (label_string[label_string.size()-1] == '|') label_string = label_string.substr(0, label_string.size()-1); @@ -487,12 +490,12 @@ struct ShowWorker fprintf(f, "}\n"); } - ShowWorker(FILE *f, RTLIL::Design *design, std::vector &libs, uint32_t colorSeed, - bool genWidthLabels, bool stretchIO, bool enumerateIds, bool abbreviateIds, bool notitle, + ShowWorker(FILE *f, RTLIL::Design *design, std::vector &libs, uint32_t colorSeed, bool genWidthLabels, + bool genSignedLabels, bool stretchIO, bool enumerateIds, bool abbreviateIds, bool notitle, const std::vector> &color_selections, const std::vector> &label_selections) : f(f), design(design), currentColor(colorSeed), genWidthLabels(genWidthLabels), - stretchIO(stretchIO), enumerateIds(enumerateIds), abbreviateIds(abbreviateIds), + genSignedLabels(genSignedLabels), stretchIO(stretchIO), enumerateIds(enumerateIds), abbreviateIds(abbreviateIds), notitle(notitle), color_selections(color_selections), label_selections(label_selections) { ct.setup_internals(); @@ -572,6 +575,10 @@ struct ShowPass : public Pass { log(" -width\n"); log(" annotate busses with a label indicating the width of the bus.\n"); log("\n"); + log(" -signed\n"); + log(" mark ports (A, B) that are declarted as signed (using the [AB]_SIGNED\n"); + log(" cell parameter) with an asterisk next to the port name.\n"); + log("\n"); log(" -stretch\n"); log(" stretch the graph so all inputs are on the left side and all outputs\n"); log(" (including inout ports) are on the right side.\n"); @@ -610,6 +617,7 @@ struct ShowPass : public Pass { std::vector libs; uint32_t colorSeed = 0; bool flag_width = false; + bool flag_signed = false; bool flag_stretch = false; bool flag_pause = false; bool flag_enum = false; @@ -664,6 +672,10 @@ struct ShowPass : public Pass { flag_width= true; continue; } + if (arg == "-signed") { + flag_signed= true; + continue; + } if (arg == "-stretch") { flag_stretch= true; continue; @@ -727,7 +739,7 @@ struct ShowPass : public Pass { delete lib; log_cmd_error("Can't open dot file `%s' for writing.\n", dot_file.c_str()); } - ShowWorker worker(f, design, libs, colorSeed, flag_width, flag_stretch, flag_enum, flag_abbeviate, flag_notitle, color_selections, label_selections); + ShowWorker worker(f, design, libs, colorSeed, flag_width, flag_signed, flag_stretch, flag_enum, flag_abbeviate, flag_notitle, color_selections, label_selections); fclose(f); for (auto lib : libs) -- cgit v1.2.3 From 1c182cedb7a42174d6eafbbc84951a27775da15d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 5 Aug 2014 12:49:53 +0200 Subject: Added mux support to wreduce command --- passes/cmds/wreduce.cc | 118 ++++++++++++++++++++++++++++++++++--------------- 1 file changed, 82 insertions(+), 36 deletions(-) (limited to 'passes') diff --git a/passes/cmds/wreduce.cc b/passes/cmds/wreduce.cc index 9cef14f48..b90843ef9 100644 --- a/passes/cmds/wreduce.cc +++ b/passes/cmds/wreduce.cc @@ -28,48 +28,23 @@ using namespace RTLIL; PRIVATE_NAMESPACE_BEGIN +static inline std::set &operator<<(std::set &set, IdString id) { + set.insert(id); + return set; +} + struct WreduceConfig { std::set supported_cell_types; WreduceConfig() { - supported_cell_types.insert("$not"); - supported_cell_types.insert("$pos"); - supported_cell_types.insert("$bu0"); - supported_cell_types.insert("$neg"); - - supported_cell_types.insert("$and"); - supported_cell_types.insert("$or"); - supported_cell_types.insert("$xor"); - supported_cell_types.insert("$xnor"); - - supported_cell_types.insert("$shl"); - supported_cell_types.insert("$shr"); - supported_cell_types.insert("$sshl"); - supported_cell_types.insert("$sshr"); - supported_cell_types.insert("$shift"); - supported_cell_types.insert("$shiftx"); - - supported_cell_types.insert("$lt"); - supported_cell_types.insert("$le"); - supported_cell_types.insert("$eq"); - supported_cell_types.insert("$ne"); - supported_cell_types.insert("$eqx"); - supported_cell_types.insert("$nex"); - supported_cell_types.insert("$ge"); - supported_cell_types.insert("$gt"); - - supported_cell_types.insert("$add"); - supported_cell_types.insert("$sub"); - // supported_cell_types.insert("$mul"); - // supported_cell_types.insert("$div"); - // supported_cell_types.insert("$mod"); - // supported_cell_types.insert("$pow"); - - // supported_cell_types.insert("$mux"); - // supported_cell_types.insert("$pmux"); - // supported_cell_types.insert("$safe_pmux"); + supported_cell_types << "$not" << "$pos" << "$bu0" << "$neg"; + supported_cell_types << "$and" << "$or" << "$xor" << "$xnor"; + supported_cell_types << "$shl" << "$shr" << "$sshl" << "$sshr" << "$shift" << "$shiftx"; + supported_cell_types << "$lt" << "$le" << "$eq" << "$ne" << "$eqx" << "$nex" << "$ge" << "$gt"; + supported_cell_types << "$add" << "$sub"; // << "$mul" << "$div" << "$mod" << "$pow" + supported_cell_types << "$mux" << "$pmux" << "$safe_pmux"; } }; @@ -86,6 +61,72 @@ struct WreduceWorker WreduceWorker(WreduceConfig *config, Module *module) : config(config), module(module), mi(module) { } + void run_cell_mux(Cell *cell) + { + SigSpec sig_a = mi.sigmap(cell->getPort("\\A")); + SigSpec sig_b = mi.sigmap(cell->getPort("\\B")); + SigSpec sig_s = mi.sigmap(cell->getPort("\\S")); + SigSpec sig_y = mi.sigmap(cell->getPort("\\Y")); + std::vector bits_removed; + + for (int i = SIZE(sig_y)-1; i >= 0; i--) + { + auto info = mi.query(sig_y[i]); + if (!info->is_output && SIZE(info->ports) <= 1) { + bits_removed.push_back(Sx); + continue; + } + + SigBit ref = sig_a[i]; + for (int k = 0; k < SIZE(sig_s); k++) { + if (ref != Sx && sig_b[k*SIZE(sig_a) + i] != Sx && ref != sig_b[k*SIZE(sig_a) + i]) + goto no_match_ab; + if (sig_b[k*SIZE(sig_a) + i] != Sx) + ref = sig_b[k*SIZE(sig_a) + i]; + } + if (0) + no_match_ab: + break; + bits_removed.push_back(ref); + } + + if (!bits_removed.empty()) + { + SigSpec sig_removed; + for (int i = SIZE(bits_removed)-1; i >= 0; i--) + sig_removed.append_bit(bits_removed[i]); + + log("Removed top %d bits (of %d) from mux cell %s.%s (%s).\n", + SIZE(sig_removed), SIZE(sig_y), log_id(module), log_id(cell), log_id(cell->type)); + + int n_removed = SIZE(sig_removed); + int n_kept = SIZE(sig_y) - SIZE(sig_removed); + + SigSpec new_work_queue_bits; + new_work_queue_bits.append(sig_a.extract(n_kept, n_removed)); + new_work_queue_bits.append(sig_y.extract(n_kept, n_removed)); + + SigSpec new_sig_a = sig_a.extract(0, n_kept); + SigSpec new_sig_y = sig_y.extract(0, n_kept); + SigSpec new_sig_b; + + for (int k = 0; k < SIZE(sig_s); k++) { + new_sig_b.append(sig_b.extract(k*SIZE(sig_a), n_kept)); + new_work_queue_bits.append(sig_b.extract(k*SIZE(sig_a) + n_kept, n_removed)); + } + + for (auto bit : new_work_queue_bits) + work_queue_bits.insert(bit); + + cell->setPort("\\A", new_sig_a); + cell->setPort("\\B", new_sig_b); + cell->setPort("\\Y", new_sig_y); + cell->fixup_parameters(); + + module->connect(sig_y.extract(n_kept, n_removed), sig_removed); + } + } + void run_reduce_inport(Cell *cell, char port) { bool is_signed = cell->getParam(stringf("\\%c_SIGNED", port)).as_bool(); @@ -112,6 +153,11 @@ struct WreduceWorker if (!cell->type.in(config->supported_cell_types)) return; + if (cell->type.in("$mux", "$pmux", "$safe_pmux")) { + run_cell_mux(cell); + return; + } + if (cell->type.in("$shl", "$shr", "$sshl", "$sshr")) cell->setParam("\\B_SIGNED", false); -- cgit v1.2.3 From d3b1a29708fc9cfd793180763484125a5f978d1a Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 5 Aug 2014 13:11:04 +0200 Subject: Cleanups and improvements in wreduce pass --- passes/cmds/wreduce.cc | 124 ++++++++++++++++++++++++++++++------------------- 1 file changed, 77 insertions(+), 47 deletions(-) (limited to 'passes') diff --git a/passes/cmds/wreduce.cc b/passes/cmds/wreduce.cc index b90843ef9..ce24e09b2 100644 --- a/passes/cmds/wreduce.cc +++ b/passes/cmds/wreduce.cc @@ -61,8 +61,10 @@ struct WreduceWorker WreduceWorker(WreduceConfig *config, Module *module) : config(config), module(module), mi(module) { } - void run_cell_mux(Cell *cell) + bool run_cell_mux(Cell *cell) { + // Reduce size of MUX if inputs agree on a value for a bit or a output bit is unused + SigSpec sig_a = mi.sigmap(cell->getPort("\\A")); SigSpec sig_b = mi.sigmap(cell->getPort("\\B")); SigSpec sig_s = mi.sigmap(cell->getPort("\\S")); @@ -90,49 +92,60 @@ struct WreduceWorker bits_removed.push_back(ref); } - if (!bits_removed.empty()) - { - SigSpec sig_removed; - for (int i = SIZE(bits_removed)-1; i >= 0; i--) - sig_removed.append_bit(bits_removed[i]); + if (bits_removed.empty()) + return false; - log("Removed top %d bits (of %d) from mux cell %s.%s (%s).\n", - SIZE(sig_removed), SIZE(sig_y), log_id(module), log_id(cell), log_id(cell->type)); + SigSpec sig_removed; + for (int i = SIZE(bits_removed)-1; i >= 0; i--) + sig_removed.append_bit(bits_removed[i]); - int n_removed = SIZE(sig_removed); - int n_kept = SIZE(sig_y) - SIZE(sig_removed); + log("Removed top %d bits (of %d) from mux cell %s.%s (%s).\n", + SIZE(sig_removed), SIZE(sig_y), log_id(module), log_id(cell), log_id(cell->type)); - SigSpec new_work_queue_bits; - new_work_queue_bits.append(sig_a.extract(n_kept, n_removed)); - new_work_queue_bits.append(sig_y.extract(n_kept, n_removed)); + int n_removed = SIZE(sig_removed); + int n_kept = SIZE(sig_y) - SIZE(sig_removed); - SigSpec new_sig_a = sig_a.extract(0, n_kept); - SigSpec new_sig_y = sig_y.extract(0, n_kept); - SigSpec new_sig_b; + SigSpec new_work_queue_bits; + new_work_queue_bits.append(sig_a.extract(n_kept, n_removed)); + new_work_queue_bits.append(sig_y.extract(n_kept, n_removed)); - for (int k = 0; k < SIZE(sig_s); k++) { - new_sig_b.append(sig_b.extract(k*SIZE(sig_a), n_kept)); - new_work_queue_bits.append(sig_b.extract(k*SIZE(sig_a) + n_kept, n_removed)); - } + SigSpec new_sig_a = sig_a.extract(0, n_kept); + SigSpec new_sig_y = sig_y.extract(0, n_kept); + SigSpec new_sig_b; - for (auto bit : new_work_queue_bits) - work_queue_bits.insert(bit); + for (int k = 0; k < SIZE(sig_s); k++) { + new_sig_b.append(sig_b.extract(k*SIZE(sig_a), n_kept)); + new_work_queue_bits.append(sig_b.extract(k*SIZE(sig_a) + n_kept, n_removed)); + } - cell->setPort("\\A", new_sig_a); - cell->setPort("\\B", new_sig_b); - cell->setPort("\\Y", new_sig_y); - cell->fixup_parameters(); + for (auto bit : new_work_queue_bits) + work_queue_bits.insert(bit); - module->connect(sig_y.extract(n_kept, n_removed), sig_removed); - } + cell->setPort("\\A", new_sig_a); + cell->setPort("\\B", new_sig_b); + cell->setPort("\\Y", new_sig_y); + cell->fixup_parameters(); + + module->connect(sig_y.extract(n_kept, n_removed), sig_removed); + return true; } - void run_reduce_inport(Cell *cell, char port) + bool run_reduce_inport(Cell *cell, char port, int max_port_size) { bool is_signed = cell->getParam(stringf("\\%c_SIGNED", port)).as_bool(); SigSpec sig = mi.sigmap(cell->getPort(stringf("\\%c", port))); + if (port == 'B' && cell->type.in("$shl", "$shr", "$sshl", "$sshr")) + is_signed = false; + int bits_removed = 0; + if (SIZE(sig) > max_port_size) { + bits_removed = SIZE(sig) - max_port_size; + for (auto bit : sig.extract(max_port_size, bits_removed)) + work_queue_bits.insert(bit); + sig = sig.extract(0, max_port_size); + } + if (is_signed) { while (SIZE(sig) > 1 && constmap(sig[SIZE(sig)-1]) == constmap(sig[SIZE(sig)-2])) work_queue_bits.insert(sig[SIZE(sig)-1]), sig.remove(SIZE(sig)-1), bits_removed++; @@ -141,31 +154,44 @@ struct WreduceWorker work_queue_bits.insert(sig[SIZE(sig)-1]), sig.remove(SIZE(sig)-1), bits_removed++; } - if (bits_removed) { - log("Removed top %d bits (of %d) from port %c of cell %s.%s (%s).\n", - bits_removed, SIZE(sig) + bits_removed, port, log_id(module), log_id(cell), log_id(cell->type)); - cell->setPort(stringf("\\%c", port), sig); - } + if (bits_removed == 0) + return false; + + log("Removed top %d bits (of %d) from port %c of cell %s.%s (%s).\n", + bits_removed, SIZE(sig) + bits_removed, port, log_id(module), log_id(cell), log_id(cell->type)); + cell->setPort(stringf("\\%c", port), sig); + return true; } - void run_cell(Cell *cell) + bool run_cell(Cell *cell) { + bool did_something = false; + if (!cell->type.in(config->supported_cell_types)) - return; + return false; + + if (cell->type.in("$mux", "$pmux", "$safe_pmux")) + return run_cell_mux(cell); + - if (cell->type.in("$mux", "$pmux", "$safe_pmux")) { - run_cell_mux(cell); - return; + // Reduce size of ports A and B based on constant input bits and size of output port + + int max_port_a_size = cell->hasPort("\\A") ? SIZE(cell->getPort("\\A")) : -1; + int max_port_b_size = cell->hasPort("\\B") ? SIZE(cell->getPort("\\B")) : -1; + + if (cell->type.in("$not", "$pos", "$bu0", "$neg", "$and", "$or", "$xor", "$add", "$sub")) { + max_port_a_size = std::min(max_port_a_size, SIZE(cell->getPort("\\Y"))); + max_port_b_size = std::min(max_port_b_size, SIZE(cell->getPort("\\Y"))); } - if (cell->type.in("$shl", "$shr", "$sshl", "$sshr")) - cell->setParam("\\B_SIGNED", false); + if (max_port_a_size >= 0) + did_something = run_reduce_inport(cell, 'A', max_port_a_size) || did_something; + + if (max_port_b_size >= 0) + did_something = run_reduce_inport(cell, 'B', max_port_b_size) || did_something; - if (cell->hasParam("\\A_SIGNED")) - run_reduce_inport(cell, 'A'); - if (cell->hasParam("\\B_SIGNED")) - run_reduce_inport(cell, 'B'); + // Reduce size of port Y based on sizes for A and B and unused bits in Y SigSpec sig = mi.sigmap(cell->getPort("\\Y")); @@ -208,9 +234,13 @@ struct WreduceWorker log("Removed top %d bits (of %d) from port Y of cell %s.%s (%s).\n", bits_removed, SIZE(sig) + bits_removed, log_id(module), log_id(cell), log_id(cell->type)); cell->setPort("\\Y", sig); + did_something = true; } - cell->fixup_parameters(); + if (did_something) + cell->fixup_parameters(); + + return did_something; } void run() @@ -222,7 +252,7 @@ struct WreduceWorker { work_queue_bits.clear(); for (auto c : work_queue_cells) - run_cell(c); + while (run_cell(c)) { } work_queue_cells.clear(); for (auto bit : work_queue_bits) -- cgit v1.2.3 From 523df7314502e2674df5287289dcf8eb204c17ac Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 5 Aug 2014 14:47:03 +0200 Subject: Added support for truncating of wires to wreduce pass --- passes/cmds/wreduce.cc | 44 ++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 40 insertions(+), 4 deletions(-) (limited to 'passes') diff --git a/passes/cmds/wreduce.cc b/passes/cmds/wreduce.cc index ce24e09b2..27571eb0d 100644 --- a/passes/cmds/wreduce.cc +++ b/passes/cmds/wreduce.cc @@ -21,8 +21,6 @@ #include "kernel/sigtools.h" #include "kernel/modtools.h" -#include - USING_YOSYS_NAMESPACE using namespace RTLIL; @@ -243,6 +241,14 @@ struct WreduceWorker return did_something; } + static int count_nontrivial_wire_attrs(RTLIL::Wire *w) + { + int count = w->attributes.size(); + count -= w->attributes.count("\\src"); + count -= w->attributes.count("\\unused_bits"); + return count; + } + void run() { for (auto c : module->selected_cells()) @@ -257,7 +263,32 @@ struct WreduceWorker work_queue_cells.clear(); for (auto bit : work_queue_bits) for (auto port : mi.query_ports(bit)) - work_queue_cells.insert(port.cell); + if (module->selected(port.cell)) + work_queue_cells.insert(port.cell); + } + + for (auto w : module->selected_wires()) + { + int unused_top_bits = 0; + + if (w->port_id > 0 || count_nontrivial_wire_attrs(w) > 0) + continue; + + for (int i = SIZE(w)-1; i >= 0; i--) { + SigBit bit(w, i); + auto info = mi.query(bit); + if (info && (info->is_input || info->is_output || SIZE(info->ports) > 0)) + break; + unused_top_bits++; + } + + if (0 < unused_top_bits && unused_top_bits < SIZE(w)) { + log("Removed top %d bits (of %d) from wire %s.%s.\n", unused_top_bits, SIZE(w), log_id(module), log_id(w)); + Wire *nw = module->addWire(NEW_ID, w); + nw->width = SIZE(w) - unused_top_bits; + module->connect(nw, SigSpec(w).extract(0, SIZE(nw))); + module->swap_names(w, nw); + } } } }; @@ -270,7 +301,12 @@ struct WreducePass : public Pass { log("\n"); log(" wreduce [options] [selection]\n"); log("\n"); - log("This command reduces the word size of operations.\n"); + log("This command reduces the word size of operations. For example it will replace\n"); + log("the 32 bit adders in the following code with adders of more appropriate widths:\n"); + log("\n"); + log(" module test(input [3:0] a, b, c, output [7:0] y);\n"); + log(" assign y = a + b + c + 1;\n"); + log(" endmodule\n"); log("\n"); } virtual void execute(std::vector args, Design *design) -- cgit v1.2.3 From 5b3dc07b9a571771afbe356e30046633037b9814 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 5 Aug 2014 16:53:53 +0200 Subject: Removed old "constmap" from wreduce code --- passes/cmds/wreduce.cc | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'passes') diff --git a/passes/cmds/wreduce.cc b/passes/cmds/wreduce.cc index 27571eb0d..1d296da54 100644 --- a/passes/cmds/wreduce.cc +++ b/passes/cmds/wreduce.cc @@ -54,7 +54,6 @@ struct WreduceWorker std::set> work_queue_cells; std::set work_queue_bits; - SigMap constmap; WreduceWorker(WreduceConfig *config, Module *module) : config(config), module(module), mi(module) { } @@ -145,10 +144,10 @@ struct WreduceWorker } if (is_signed) { - while (SIZE(sig) > 1 && constmap(sig[SIZE(sig)-1]) == constmap(sig[SIZE(sig)-2])) + while (SIZE(sig) > 1 && sig[SIZE(sig)-1] == sig[SIZE(sig)-2]) work_queue_bits.insert(sig[SIZE(sig)-1]), sig.remove(SIZE(sig)-1), bits_removed++; } else { - while (SIZE(sig) > 1 && constmap(sig[SIZE(sig)-1]) == S0) + while (SIZE(sig) > 1 && sig[SIZE(sig)-1] == S0) work_queue_bits.insert(sig[SIZE(sig)-1]), sig.remove(SIZE(sig)-1), bits_removed++; } -- cgit v1.2.3 From 2501abe1ee47610e5fb2b541c1fc0c648617da20 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 5 Aug 2014 19:01:41 +0200 Subject: Various fixes and improvements in wreduce pass --- passes/cmds/wreduce.cc | 76 +++++++++++++++++++++++++++++++------------------- 1 file changed, 47 insertions(+), 29 deletions(-) (limited to 'passes') diff --git a/passes/cmds/wreduce.cc b/passes/cmds/wreduce.cc index 1d296da54..6723a57fe 100644 --- a/passes/cmds/wreduce.cc +++ b/passes/cmds/wreduce.cc @@ -58,7 +58,7 @@ struct WreduceWorker WreduceWorker(WreduceConfig *config, Module *module) : config(config), module(module), mi(module) { } - bool run_cell_mux(Cell *cell) + void run_cell_mux(Cell *cell) { // Reduce size of MUX if inputs agree on a value for a bit or a output bit is unused @@ -90,12 +90,19 @@ struct WreduceWorker } if (bits_removed.empty()) - return false; + return; SigSpec sig_removed; for (int i = SIZE(bits_removed)-1; i >= 0; i--) sig_removed.append_bit(bits_removed[i]); + if (SIZE(bits_removed) == SIZE(sig_y)) { + log("Removed cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type)); + module->connect(sig_y, sig_removed); + module->remove(cell); + return; + } + log("Removed top %d bits (of %d) from mux cell %s.%s (%s).\n", SIZE(sig_removed), SIZE(sig_y), log_id(module), log_id(cell), log_id(cell->type)); @@ -124,16 +131,15 @@ struct WreduceWorker cell->fixup_parameters(); module->connect(sig_y.extract(n_kept, n_removed), sig_removed); - return true; } - bool run_reduce_inport(Cell *cell, char port, int max_port_size) + void run_reduce_inport(Cell *cell, char port, int max_port_size, bool &port_signed, bool &did_something) { - bool is_signed = cell->getParam(stringf("\\%c_SIGNED", port)).as_bool(); + port_signed = cell->getParam(stringf("\\%c_SIGNED", port)).as_bool(); SigSpec sig = mi.sigmap(cell->getPort(stringf("\\%c", port))); if (port == 'B' && cell->type.in("$shl", "$shr", "$sshl", "$sshr")) - is_signed = false; + port_signed = false; int bits_removed = 0; if (SIZE(sig) > max_port_size) { @@ -143,7 +149,7 @@ struct WreduceWorker sig = sig.extract(0, max_port_size); } - if (is_signed) { + if (port_signed) { while (SIZE(sig) > 1 && sig[SIZE(sig)-1] == sig[SIZE(sig)-2]) work_queue_bits.insert(sig[SIZE(sig)-1]), sig.remove(SIZE(sig)-1), bits_removed++; } else { @@ -151,21 +157,20 @@ struct WreduceWorker work_queue_bits.insert(sig[SIZE(sig)-1]), sig.remove(SIZE(sig)-1), bits_removed++; } - if (bits_removed == 0) - return false; - - log("Removed top %d bits (of %d) from port %c of cell %s.%s (%s).\n", - bits_removed, SIZE(sig) + bits_removed, port, log_id(module), log_id(cell), log_id(cell->type)); - cell->setPort(stringf("\\%c", port), sig); - return true; + if (bits_removed) { + log("Removed top %d bits (of %d) from port %c of cell %s.%s (%s).\n", + bits_removed, SIZE(sig) + bits_removed, port, log_id(module), log_id(cell), log_id(cell->type)); + cell->setPort(stringf("\\%c", port), sig); + did_something = true; + } } - bool run_cell(Cell *cell) + void run_cell(Cell *cell) { bool did_something = false; if (!cell->type.in(config->supported_cell_types)) - return false; + return; if (cell->type.in("$mux", "$pmux", "$safe_pmux")) return run_cell_mux(cell); @@ -181,11 +186,14 @@ struct WreduceWorker max_port_b_size = std::min(max_port_b_size, SIZE(cell->getPort("\\Y"))); } + bool port_a_signed = false; + bool port_b_signed = false; + if (max_port_a_size >= 0) - did_something = run_reduce_inport(cell, 'A', max_port_a_size) || did_something; + run_reduce_inport(cell, 'A', max_port_a_size, port_a_signed, did_something); if (max_port_b_size >= 0) - did_something = run_reduce_inport(cell, 'B', max_port_b_size) || did_something; + run_reduce_inport(cell, 'B', max_port_b_size, port_b_signed, did_something); // Reduce size of port Y based on sizes for A and B and unused bits in Y @@ -193,15 +201,19 @@ struct WreduceWorker SigSpec sig = mi.sigmap(cell->getPort("\\Y")); int bits_removed = 0; - while (SIZE(sig) > 0) - { - auto info = mi.query(sig[SIZE(sig)-1]); + if (port_a_signed && cell->type == "$shr") { + // do not reduce size of output on $shr cells with signed A inputs + } else { + while (SIZE(sig) > 0) + { + auto info = mi.query(sig[SIZE(sig)-1]); - if (info->is_output || SIZE(info->ports) > 1) - break; + if (info->is_output || SIZE(info->ports) > 1) + break; - sig.remove(SIZE(sig)-1); - bits_removed++; + sig.remove(SIZE(sig)-1); + bits_removed++; + } } if (cell->type.in("$pos", "$bu0", "$add", "$mul", "$and", "$or", "$xor")) @@ -227,6 +239,12 @@ struct WreduceWorker } } + if (SIZE(sig) == 0) { + log("Removed cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type)); + module->remove(cell); + return; + } + if (bits_removed) { log("Removed top %d bits (of %d) from port Y of cell %s.%s (%s).\n", bits_removed, SIZE(sig) + bits_removed, log_id(module), log_id(cell), log_id(cell->type)); @@ -234,10 +252,10 @@ struct WreduceWorker did_something = true; } - if (did_something) + if (did_something) { cell->fixup_parameters(); - - return did_something; + run_cell(cell); + } } static int count_nontrivial_wire_attrs(RTLIL::Wire *w) @@ -257,7 +275,7 @@ struct WreduceWorker { work_queue_bits.clear(); for (auto c : work_queue_cells) - while (run_cell(c)) { } + run_cell(c); work_queue_cells.clear(); for (auto bit : work_queue_bits) -- cgit v1.2.3 From b4f10e342cf400bd2f392a588f28de069ba0f9d8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 6 Aug 2014 14:31:38 +0200 Subject: Various improvements in memory_dff pass --- passes/memory/memory_dff.cc | 43 ++++++++++++++++++++++--------------------- 1 file changed, 22 insertions(+), 21 deletions(-) (limited to 'passes') diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index e92d726cc..cdd0b85e2 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -28,7 +28,7 @@ static void normalize_sig(RTLIL::Module *module, RTLIL::SigSpec &sig) sig.replace(conn.first, conn.second); } -static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::SigSpec &clk, bool &clk_polarity, bool after = false) +static bool find_sig_before_dff(RTLIL::Module *module, std::vector &dff_cells, RTLIL::SigSpec &sig, RTLIL::SigSpec &clk, bool &clk_polarity, bool after = false) { normalize_sig(module, sig); @@ -37,11 +37,8 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI if (bit.wire == NULL) continue; - for (auto cell : module->cells()) + for (auto cell : dff_cells) { - if (cell->type != "$dff") - continue; - if (clk != RTLIL::SigSpec(RTLIL::State::Sx)) { if (cell->getPort("\\CLK") != clk) continue; @@ -69,7 +66,7 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI return true; } -static void handle_wr_cell(RTLIL::Module *module, RTLIL::Cell *cell) +static void handle_wr_cell(RTLIL::Module *module, std::vector &dff_cells, RTLIL::Cell *cell) { log("Checking cell `%s' in module `%s': ", cell->name.c_str(), module->name.c_str()); @@ -77,19 +74,19 @@ static void handle_wr_cell(RTLIL::Module *module, RTLIL::Cell *cell) bool clk_polarity = 0; RTLIL::SigSpec sig_addr = cell->getPort("\\ADDR"); - if (!find_sig_before_dff(module, sig_addr, clk, clk_polarity)) { + if (!find_sig_before_dff(module, dff_cells, sig_addr, clk, clk_polarity)) { log("no (compatible) $dff for address input found.\n"); return; } RTLIL::SigSpec sig_data = cell->getPort("\\DATA"); - if (!find_sig_before_dff(module, sig_data, clk, clk_polarity)) { + if (!find_sig_before_dff(module, dff_cells, sig_data, clk, clk_polarity)) { log("no (compatible) $dff for data input found.\n"); return; } RTLIL::SigSpec sig_en = cell->getPort("\\EN"); - if (!find_sig_before_dff(module, sig_en, clk, clk_polarity)) { + if (!find_sig_before_dff(module, dff_cells, sig_en, clk, clk_polarity)) { log("no (compatible) $dff for enable input found.\n"); return; } @@ -102,6 +99,7 @@ static void handle_wr_cell(RTLIL::Module *module, RTLIL::Cell *cell) cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1); cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity); log("merged $dff to cell.\n"); + return; } log("no (compatible) $dff found.\n"); @@ -125,7 +123,7 @@ static void disconnect_dff(RTLIL::Module *module, RTLIL::SigSpec sig) } } -static void handle_rd_cell(RTLIL::Module *module, RTLIL::Cell *cell) +static void handle_rd_cell(RTLIL::Module *module, std::vector &dff_cells, RTLIL::Cell *cell) { log("Checking cell `%s' in module `%s': ", cell->name.c_str(), module->name.c_str()); @@ -133,7 +131,7 @@ static void handle_rd_cell(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::SigSpec clk_data = RTLIL::SigSpec(RTLIL::State::Sx); RTLIL::SigSpec sig_data = cell->getPort("\\DATA"); - if (find_sig_before_dff(module, sig_data, clk_data, clk_polarity, true) && + if (find_sig_before_dff(module, dff_cells, sig_data, clk_data, clk_polarity, true) && clk_data != RTLIL::SigSpec(RTLIL::State::Sx)) { disconnect_dff(module, sig_data); @@ -148,7 +146,7 @@ static void handle_rd_cell(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::SigSpec clk_addr = RTLIL::SigSpec(RTLIL::State::Sx); RTLIL::SigSpec sig_addr = cell->getPort("\\ADDR"); - if (find_sig_before_dff(module, sig_addr, clk_addr, clk_polarity) && + if (find_sig_before_dff(module, dff_cells, sig_addr, clk_addr, clk_polarity) && clk_addr != RTLIL::SigSpec(RTLIL::State::Sx)) { cell->setPort("\\CLK", clk_addr); @@ -163,15 +161,19 @@ static void handle_rd_cell(RTLIL::Module *module, RTLIL::Cell *cell) log("no (compatible) $dff found.\n"); } -static void handle_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_wr_only) +static void handle_module(RTLIL::Module *module, bool flag_wr_only) { - for (auto cell : module->cells()) { - if (!design->selected(module, cell)) - continue; + std::vector dff_cells; + + for (auto cell : module->cells()) + if (cell->type == "$dff") + dff_cells.push_back(cell); + + for (auto cell : module->selected_cells()) { if (cell->type == "$memwr" && !cell->parameters["\\CLK_ENABLE"].as_bool()) - handle_wr_cell(module, cell); + handle_wr_cell(module, dff_cells, cell); if (!flag_wr_only && cell->type == "$memrd" && !cell->parameters["\\CLK_ENABLE"].as_bool()) - handle_rd_cell(module, cell); + handle_rd_cell(module, dff_cells, cell); } } @@ -207,9 +209,8 @@ struct MemoryDffPass : public Pass { } extra_args(args, argidx, design); - for (auto mod : design->modules()) - if (design->selected(mod)) - handle_module(design, mod, flag_wr_only); + for (auto mod : design->selected_modules()) + handle_module(mod, flag_wr_only); } } MemoryDffPass; -- cgit v1.2.3 From c55eb8f8a6c83514c5d46c6992c6c6fa1069a889 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 7 Aug 2014 16:42:35 +0200 Subject: Use "-keepdc" in "miter -equiv -flatten" --- passes/sat/miter.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'passes') diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index e51c92f9f..b3adefb92 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -251,7 +251,7 @@ static void create_miter_equiv(struct Pass *that, std::vector args, if (flag_flatten) { log_push(); - Pass::call_on_module(design, miter_module, "flatten; opt_const -undriven;;"); + Pass::call_on_module(design, miter_module, "flatten; opt_const -keepdc -undriven;;"); log_pop(); } } @@ -285,7 +285,7 @@ struct MiterPass : public Pass { log(" also create an 'assert' cell that checks if trigger is always low.\n"); log("\n"); log(" -flatten\n"); - log(" call 'flatten; opt_const -undriven;;' on the miter circuit.\n"); + log(" call 'flatten; opt_const -keepdc -undriven;;' on the miter circuit.\n"); log("\n"); } virtual void execute(std::vector args, RTLIL::Design *design) -- cgit v1.2.3 From 0b8b8d41eb07fd048cbe68acfe4b724e314bbb41 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 7 Aug 2014 22:37:01 +0200 Subject: Fixed build with gcc-4.6 --- passes/cmds/trace.cc | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'passes') diff --git a/passes/cmds/trace.cc b/passes/cmds/trace.cc index 6a5ea346e..09293a86b 100644 --- a/passes/cmds/trace.cc +++ b/passes/cmds/trace.cc @@ -24,34 +24,34 @@ PRIVATE_NAMESPACE_BEGIN struct TraceMonitor : public RTLIL::Monitor { - virtual void notify_module_add(RTLIL::Module *module) override + virtual void notify_module_add(RTLIL::Module *module) OVERRIDE { log("#TRACE# Module add: %s\n", log_id(module)); } - virtual void notify_module_del(RTLIL::Module *module) override + virtual void notify_module_del(RTLIL::Module *module) OVERRIDE { log("#TRACE# Module delete: %s\n", log_id(module)); } - virtual void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, RTLIL::SigSpec &sig) override + virtual void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, RTLIL::SigSpec &sig) OVERRIDE { log("#TRACE# Cell connect: %s.%s.%s = %s (was: %s)\n", log_id(cell->module), log_id(cell), log_id(port), log_signal(sig), log_signal(old_sig)); } - virtual void notify_connect(RTLIL::Module *module, const RTLIL::SigSig &sigsig) override + virtual void notify_connect(RTLIL::Module *module, const RTLIL::SigSig &sigsig) OVERRIDE { log("#TRACE# Connection in module %s: %s = %s\n", log_id(module), log_signal(sigsig.first), log_signal(sigsig.second)); } - virtual void notify_connect(RTLIL::Module *module, const std::vector &sigsig_vec) override + virtual void notify_connect(RTLIL::Module *module, const std::vector &sigsig_vec) OVERRIDE { log("#TRACE# New connections in module %s:\n", log_id(module)); for (auto &sigsig : sigsig_vec) log("## %s = %s\n", log_signal(sigsig.first), log_signal(sigsig.second)); } - virtual void notify_blackout(RTLIL::Module *module) override + virtual void notify_blackout(RTLIL::Module *module) OVERRIDE { log("#TRACE# Blackout in module %s:\n", log_id(module)); } -- cgit v1.2.3 From 622ebab6710815324fa7250554b56f673862b479 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 8 Aug 2014 13:11:54 +0200 Subject: Added "sat -prove-skip" --- passes/sat/sat.cc | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) (limited to 'passes') diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index fd3d405a7..c6da4bb42 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -917,6 +917,9 @@ struct SatPass : public Pass { log(" -prove-asserts\n"); log(" Prove that all asserts in the design hold.\n"); log("\n"); + log(" -prove-skip \n"); + log(" Do not enforce the prove-condition for the first time steps.\n"); + log("\n"); log(" -maxsteps \n"); log(" Set a maximum length for the induction.\n"); log("\n"); @@ -945,7 +948,7 @@ struct SatPass : public Pass { std::map>> sets_at; std::map> unsets_at, sets_def_at, sets_any_undef_at, sets_all_undef_at; std::vector shows, sets_def, sets_any_undef, sets_all_undef; - int loopcount = 0, seq_len = 0, maxsteps = 0, initsteps = 0, timeout = 0; + int loopcount = 0, seq_len = 0, maxsteps = 0, initsteps = 0, timeout = 0, prove_skip = 0; bool verify = false, fail_on_timeout = false, enable_undef = false, set_def_inputs = false; bool ignore_div_by_zero = false, set_init_undef = false, set_init_zero = false, max_undef = false; bool tempinduct = false, prove_asserts = false, show_inputs = false, show_outputs = false; @@ -1059,6 +1062,10 @@ struct SatPass : public Pass { prove_asserts = true; continue; } + if (args[argidx] == "-prove-skip" && argidx+1 < args.size()) { + prove_skip = atoi(args[++argidx].c_str()); + continue; + } if (args[argidx] == "-seq" && argidx+1 < args.size()) { seq_len = atoi(args[++argidx].c_str()); continue; @@ -1154,6 +1161,12 @@ struct SatPass : public Pass { if (!prove.size() && !prove_x.size() && !prove_asserts && tempinduct) log_cmd_error("Got -tempinduct but nothing to prove!\n"); + if (prove_skip && tempinduct) + log_cmd_error("Options -prove-skip and -tempinduct don't work with each other.\n"); + + if (prove_skip >= seq_len && prove_skip > 0) + log_cmd_error("The value of -prove-skip must be smaller than the one of -seq.\n"); + if (set_init_undef + set_init_zero + set_init_def > 1) log_cmd_error("The options -set-init-undef, -set-init-def, and -set-init-zero are exclusive!\n"); @@ -1359,7 +1372,8 @@ struct SatPass : public Pass { for (int timestep = 1; timestep <= seq_len; timestep++) { sathelper.setup(timestep); if (sathelper.prove.size() || sathelper.prove_x.size() || sathelper.prove_asserts) - prove_bits.push_back(sathelper.setup_proof(timestep)); + if (timestep > prove_skip) + prove_bits.push_back(sathelper.setup_proof(timestep)); } if (sathelper.prove.size() || sathelper.prove_x.size() || sathelper.prove_asserts) sathelper.ez.assume(sathelper.ez.NOT(sathelper.ez.expression(ezSAT::OpAnd, prove_bits))); -- cgit v1.2.3 From 7c94024fc32778cb6c789fc46a7bfbbcc7109e89 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 8 Aug 2014 13:47:20 +0200 Subject: Fixed fsm_extract for wreduced muxes --- passes/fsm/fsm_extract.cc | 33 +++++++++++++++++++++++++-------- 1 file changed, 25 insertions(+), 8 deletions(-) (limited to 'passes') diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index 5e71c1f0c..7533b4a33 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -52,33 +52,50 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL std::set cellport_list; sig2driver.find(sig, cellport_list); - for (auto &cellport : cellport_list) { + for (auto &cellport : cellport_list) + { RTLIL::Cell *cell = module->cells_.at(cellport.first); if ((cell->type != "$mux" && cell->type != "$pmux" && cell->type != "$safe_pmux") || cellport.second != "\\Y") { log(" unexpected cell type %s (%s) found in state selection tree.\n", cell->type.c_str(), cell->name.c_str()); return false; } + RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A")); RTLIL::SigSpec sig_b = assign_map(cell->getPort("\\B")); RTLIL::SigSpec sig_s = assign_map(cell->getPort("\\S")); + RTLIL::SigSpec sig_y = assign_map(cell->getPort("\\Y")); + + RTLIL::SigSpec sig_aa = sig; + sig_aa.replace(sig_y, sig_a); + + RTLIL::SigSpec sig_bb; + for (int i = 0; i < SIZE(sig_b)/SIZE(sig_a); i++) { + RTLIL::SigSpec s = sig; + s.replace(sig_y, sig_b.extract(i*SIZE(sig_a), SIZE(sig_a))); + sig_bb.append(s); + } + if (reset_state && RTLIL::SigSpec(*reset_state).is_fully_undef()) do { - if (sig_a.is_fully_def()) - *reset_state = sig_a.as_const(); - else if (sig_b.is_fully_def()) - *reset_state = sig_b.as_const(); + if (sig_aa.is_fully_def()) + *reset_state = sig_aa.as_const(); + else if (sig_bb.is_fully_def()) + *reset_state = sig_bb.as_const(); else break; log(" found reset state: %s (guessed from mux tree)\n", log_signal(*reset_state)); } while (0); + if (ctrl.extract(sig_s).size() == 0) { log(" found ctrl input: %s\n", log_signal(sig_s)); ctrl.append(sig_s); } - if (!find_states(sig_a, dff_out, ctrl, states)) + + if (!find_states(sig_aa, dff_out, ctrl, states)) return false; - for (int i = 0; i < sig_b.size()/sig_a.size(); i++) { - if (!find_states(sig_b.extract(i*sig_a.size(), sig_a.size()), dff_out, ctrl, states)) + + for (int i = 0; i < SIZE(sig_bb)/SIZE(sig_aa); i++) { + if (!find_states(sig_bb.extract(i*SIZE(sig_aa), SIZE(sig_aa)), dff_out, ctrl, states)) return false; } } -- cgit v1.2.3 From cb6ca08a53bfaa1b76798e6220bb1b267d49b235 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 8 Aug 2014 14:24:09 +0200 Subject: Fixed sharing of reduce operator --- passes/sat/share.cc | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'passes') diff --git a/passes/sat/share.cc b/passes/sat/share.cc index 0c88b4d3c..7141cea2a 100644 --- a/passes/sat/share.cc +++ b/passes/sat/share.cc @@ -252,6 +252,19 @@ struct ShareWorker if (config.generic_uni_ops.count(c1->type)) { + if (c1->type.in("$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool") && c1->getParam("\\A_WIDTH").as_int() != c2->getParam("\\A_WIDTH").as_int()) + { + RTLIL::SigBit extbit = c1->type == "$reduce_and" ? RTLIL::State::S1 : RTLIL::State::S0; + while (c1->getParam("\\A_WIDTH").as_int() < c2->getParam("\\A_WIDTH").as_int()) { + c1->setParam("\\A_WIDTH", c1->getParam("\\A_WIDTH").as_int() + 1); + c1->setPort("\\A", {extbit, c1->getPort("\\A")}); + } + while (c2->getParam("\\A_WIDTH").as_int() < c1->getParam("\\A_WIDTH").as_int()) { + c2->setParam("\\A_WIDTH", c2->getParam("\\A_WIDTH").as_int() + 1); + c2->setPort("\\A", {extbit, c2->getPort("\\A")}); + } + } + if (c1->parameters.at("\\A_SIGNED").as_bool() != c2->parameters.at("\\A_SIGNED").as_bool()) { RTLIL::Cell *unsigned_cell = c1->parameters.at("\\A_SIGNED").as_bool() ? c2 : c1; -- cgit v1.2.3 From 7067c43ec09cca176ad72378aa9ad868171c2471 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 8 Aug 2014 14:49:06 +0200 Subject: Fixed "fsm -export" --- passes/fsm/fsm.cc | 6 +++--- passes/fsm/fsm_export.cc | 5 ++--- 2 files changed, 5 insertions(+), 6 deletions(-) (limited to 'passes') diff --git a/passes/fsm/fsm.cc b/passes/fsm/fsm.cc index 13e90910b..2fae76091 100644 --- a/passes/fsm/fsm.cc +++ b/passes/fsm/fsm.cc @@ -127,12 +127,12 @@ struct FsmPass : public Pass { Pass::call(design, "fsm_recode" + fm_set_fsm_file_opt + encoding_opt); Pass::call(design, "fsm_info"); - if (!flag_nomap) - Pass::call(design, "fsm_map"); - if (flag_export) Pass::call(design, "fsm_export"); + if (!flag_nomap) + Pass::call(design, "fsm_map"); + log_pop(); } } FsmPass; diff --git a/passes/fsm/fsm_export.cc b/passes/fsm/fsm_export.cc index cb762dc1a..b4a6b3f7b 100644 --- a/passes/fsm/fsm_export.cc +++ b/passes/fsm/fsm_export.cc @@ -56,13 +56,12 @@ void write_kiss2(struct RTLIL::Module *module, struct RTLIL::Cell *cell, std::st attr_it = cell->attributes.find("\\fsm_export"); if (!filename.empty()) { - kiss_name.assign(filename); + kiss_name.assign(filename); } else if (attr_it != cell->attributes.end() && attr_it->second.decode_string() != "") { kiss_name.assign(attr_it->second.decode_string()); } else { - kiss_name.assign(module->name.str()); - kiss_name.append('-' + cell->name.str() + ".kiss2"); + kiss_name.assign(log_id(module) + std::string("-") + log_id(cell) + ".kiss2"); } log("\n"); -- cgit v1.2.3 From 58ac605470aed3b2a537b4f99ac17a199f8b5233 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 8 Aug 2014 14:55:11 +0200 Subject: Another fsm_extract bugfix --- passes/fsm/fsm_extract.cc | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'passes') diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index 7533b4a33..ebe3073de 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -231,6 +231,10 @@ static void extract_fsm(RTLIL::Wire *wire) log(" fsm extraction failed: state selection tree is not closed.\n"); return; } + if (SIZE(states) <= 1) { + log(" fsm extraction failed: at least two states are required.\n"); + return; + } // find control outputs // (add the state signals to the list of control outputs. if everything goes right, this signals -- cgit v1.2.3 From 2faef8973830e553b1730c07d327c8d76d412e1c Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 9 Aug 2014 14:49:51 +0200 Subject: Some improvements in fsm_opt and fsm_map for FSM with unreachable states --- passes/fsm/fsm_map.cc | 107 +++++++++++++++++++++++++++----------------------- passes/fsm/fsm_opt.cc | 44 +++++++++++++++++++++ 2 files changed, 101 insertions(+), 50 deletions(-) (limited to 'passes') diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc index 99b736c1b..b3750de08 100644 --- a/passes/fsm/fsm_map.cc +++ b/passes/fsm/fsm_map.cc @@ -207,65 +207,72 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) // generate next_state signal - RTLIL::Wire *next_state_onehot = module->addWire(NEW_ID, fsm_data.state_table.size()); - - for (size_t i = 0; i < fsm_data.state_table.size(); i++) + if (SIZE(fsm_data.state_table) == 1) { - std::map> pattern_cache; - std::set fullstate_cache; + module->connect(next_state_wire, fsm_data.state_table.front()); + } + else + { + RTLIL::Wire *next_state_onehot = module->addWire(NEW_ID, fsm_data.state_table.size()); - for (size_t j = 0; j < fsm_data.state_table.size(); j++) - fullstate_cache.insert(j); + for (size_t i = 0; i < fsm_data.state_table.size(); i++) + { + std::map> pattern_cache; + std::set fullstate_cache; - for (auto &tr : fsm_data.transition_table) { - if (tr.state_out == int(i)) - pattern_cache[tr.ctrl_in].insert(tr.state_in); - else - fullstate_cache.erase(tr.state_in); - } + for (size_t j = 0; j < fsm_data.state_table.size(); j++) + fullstate_cache.insert(j); - implement_pattern_cache(module, pattern_cache, fullstate_cache, fsm_data.state_table.size(), state_onehot, ctrl_in, RTLIL::SigSpec(next_state_onehot, i)); - } + for (auto &tr : fsm_data.transition_table) { + if (tr.state_out == int(i)) + pattern_cache[tr.ctrl_in].insert(tr.state_in); + else + fullstate_cache.erase(tr.state_in); + } - if (encoding_is_onehot) - { - RTLIL::SigSpec next_state_sig(RTLIL::State::Sm, next_state_wire->width); - for (size_t i = 0; i < fsm_data.state_table.size(); i++) { - RTLIL::Const state = fsm_data.state_table[i]; - int bit_idx = -1; - for (size_t j = 0; j < state.bits.size(); j++) - if (state.bits[j] == RTLIL::State::S1) - bit_idx = j; - if (bit_idx >= 0) - next_state_sig.replace(bit_idx, RTLIL::SigSpec(next_state_onehot, i)); + implement_pattern_cache(module, pattern_cache, fullstate_cache, fsm_data.state_table.size(), state_onehot, ctrl_in, RTLIL::SigSpec(next_state_onehot, i)); } - log_assert(!next_state_sig.has_marked_bits()); - module->connect(RTLIL::SigSig(next_state_wire, next_state_sig)); - } - else - { - RTLIL::SigSpec sig_a, sig_b, sig_s; - int reset_state = fsm_data.reset_state; - if (reset_state < 0) - reset_state = 0; - - for (size_t i = 0; i < fsm_data.state_table.size(); i++) { - RTLIL::Const state = fsm_data.state_table[i]; - if (int(i) == fsm_data.reset_state) { - sig_a = RTLIL::SigSpec(state); - } else { - sig_b.append(RTLIL::SigSpec(state)); - sig_s.append(RTLIL::SigSpec(next_state_onehot, i)); + + if (encoding_is_onehot) + { + RTLIL::SigSpec next_state_sig(RTLIL::State::Sm, next_state_wire->width); + for (size_t i = 0; i < fsm_data.state_table.size(); i++) { + RTLIL::Const state = fsm_data.state_table[i]; + int bit_idx = -1; + for (size_t j = 0; j < state.bits.size(); j++) + if (state.bits[j] == RTLIL::State::S1) + bit_idx = j; + if (bit_idx >= 0) + next_state_sig.replace(bit_idx, RTLIL::SigSpec(next_state_onehot, i)); } + log_assert(!next_state_sig.has_marked_bits()); + module->connect(RTLIL::SigSig(next_state_wire, next_state_sig)); } + else + { + RTLIL::SigSpec sig_a, sig_b, sig_s; + int reset_state = fsm_data.reset_state; + if (reset_state < 0) + reset_state = 0; + + for (size_t i = 0; i < fsm_data.state_table.size(); i++) { + RTLIL::Const state = fsm_data.state_table[i]; + if (int(i) == fsm_data.reset_state) { + sig_a = RTLIL::SigSpec(state); + } else { + sig_b.append(RTLIL::SigSpec(state)); + sig_s.append(RTLIL::SigSpec(next_state_onehot, i)); + } + } - RTLIL::Cell *mux_cell = module->addCell(NEW_ID, "$safe_pmux"); - mux_cell->setPort("\\A", sig_a); - mux_cell->setPort("\\B", sig_b); - mux_cell->setPort("\\S", sig_s); - mux_cell->setPort("\\Y", RTLIL::SigSpec(next_state_wire)); - mux_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_a.size()); - mux_cell->parameters["\\S_WIDTH"] = RTLIL::Const(sig_s.size()); + RTLIL::Cell *mux_cell = module->addCell(NEW_ID, "$safe_pmux"); + mux_cell->setPort("\\A", sig_a); + mux_cell->setPort("\\B", sig_b); + mux_cell->setPort("\\S", sig_s); + mux_cell->setPort("\\Y", RTLIL::SigSpec(next_state_wire)); + mux_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_a.size()); + mux_cell->parameters["\\S_WIDTH"] = RTLIL::Const(sig_s.size()); + } } // Generate ctrl_out signal diff --git a/passes/fsm/fsm_opt.cc b/passes/fsm/fsm_opt.cc index bcaa89bf0..a0e1885ec 100644 --- a/passes/fsm/fsm_opt.cc +++ b/passes/fsm/fsm_opt.cc @@ -30,6 +30,48 @@ struct FsmOpt FsmData fsm_data; RTLIL::Cell *cell; RTLIL::Module *module; + + void opt_unreachable_states() + { + while (1) + { + std::set unreachable_states; + std::vector new_transition_table; + std::vector new_state_table; + std::map old_to_new_state; + + for (int i = 0; i < SIZE(fsm_data.state_table); i++) + if (i != fsm_data.reset_state) + unreachable_states.insert(i); + + for (auto &trans : fsm_data.transition_table) + unreachable_states.erase(trans.state_out); + + if (unreachable_states.empty()) + break; + + for (int i = 0; i < SIZE(fsm_data.state_table); i++) { + if (unreachable_states.count(i)) { + log(" Removing unreachable state %s.\n", log_signal(fsm_data.state_table[i])); + continue; + } + old_to_new_state[i] = SIZE(new_state_table); + new_state_table.push_back(fsm_data.state_table[i]); + } + + for (auto trans : fsm_data.transition_table) { + if (unreachable_states.count(trans.state_in)) + continue; + trans.state_in = old_to_new_state.at(trans.state_in); + trans.state_out = old_to_new_state.at(trans.state_out); + new_transition_table.push_back(trans); + } + + new_transition_table.swap(fsm_data.transition_table); + new_state_table.swap(fsm_data.state_table); + fsm_data.reset_state = old_to_new_state.at(fsm_data.reset_state); + } + } bool signal_is_unused(RTLIL::SigSpec sig) { @@ -253,6 +295,8 @@ struct FsmOpt this->cell = cell; this->module = module; + opt_unreachable_states(); + opt_unused_outputs(); opt_alias_inputs(); -- cgit v1.2.3 From b9811d5aff7ca31daa214386a041af0865813813 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 9 Aug 2014 15:17:54 +0200 Subject: Do not share any $reduce_* cells (its complicated and not worth it anyways) --- passes/sat/share.cc | 19 ------------------- 1 file changed, 19 deletions(-) (limited to 'passes') diff --git a/passes/sat/share.cc b/passes/sat/share.cc index 7141cea2a..065b90d3e 100644 --- a/passes/sat/share.cc +++ b/passes/sat/share.cc @@ -252,19 +252,6 @@ struct ShareWorker if (config.generic_uni_ops.count(c1->type)) { - if (c1->type.in("$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool") && c1->getParam("\\A_WIDTH").as_int() != c2->getParam("\\A_WIDTH").as_int()) - { - RTLIL::SigBit extbit = c1->type == "$reduce_and" ? RTLIL::State::S1 : RTLIL::State::S0; - while (c1->getParam("\\A_WIDTH").as_int() < c2->getParam("\\A_WIDTH").as_int()) { - c1->setParam("\\A_WIDTH", c1->getParam("\\A_WIDTH").as_int() + 1); - c1->setPort("\\A", {extbit, c1->getPort("\\A")}); - } - while (c2->getParam("\\A_WIDTH").as_int() < c1->getParam("\\A_WIDTH").as_int()) { - c2->setParam("\\A_WIDTH", c2->getParam("\\A_WIDTH").as_int() + 1); - c2->setPort("\\A", {extbit, c2->getPort("\\A")}); - } - } - if (c1->parameters.at("\\A_SIGNED").as_bool() != c2->parameters.at("\\A_SIGNED").as_bool()) { RTLIL::Cell *unsigned_cell = c1->parameters.at("\\A_SIGNED").as_bool() ? c2 : c1; @@ -923,12 +910,6 @@ struct SharePass : public Pass { // config.generic_uni_ops.insert("$bu0"); config.generic_uni_ops.insert("$neg"); - config.generic_uni_ops.insert("$reduce_and"); - config.generic_uni_ops.insert("$reduce_or"); - config.generic_uni_ops.insert("$reduce_xor"); - config.generic_uni_ops.insert("$reduce_xnor"); - config.generic_uni_ops.insert("$reduce_bool"); - config.generic_cbin_ops.insert("$and"); config.generic_cbin_ops.insert("$or"); config.generic_cbin_ops.insert("$xor"); -- cgit v1.2.3 From 9d4362990f514ffd2aad3170ec7382f21b8bca67 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 9 Aug 2014 17:07:20 +0200 Subject: Fixed "share" for complex scenarios with never-active cells --- passes/sat/share.cc | 28 ++++++++++++++++++++++------ 1 file changed, 22 insertions(+), 6 deletions(-) (limited to 'passes') diff --git a/passes/sat/share.cc b/passes/sat/share.cc index 065b90d3e..5f3cf4214 100644 --- a/passes/sat/share.cc +++ b/passes/sat/share.cc @@ -685,12 +685,13 @@ struct ShareWorker RTLIL::SigSpec cell_activation_signals = bits_from_activation_patterns(cell_activation_patterns); if (cell_activation_patterns.empty()) { - log (" Cell is never active. Sharing is pointless, we simply remove it.\n"); + log(" Cell is never active. Sharing is pointless, we simply remove it.\n"); + cells_to_remove.insert(cell); continue; } if (cell_activation_patterns.count(std::pair())) { - log (" Cell is always active. Therefore no sharing is possible.\n"); + log(" Cell is always active. Therefore no sharing is possible.\n"); continue; } @@ -717,13 +718,15 @@ struct ShareWorker RTLIL::SigSpec other_cell_activation_signals = bits_from_activation_patterns(other_cell_activation_patterns); if (other_cell_activation_patterns.empty()) { - log (" Cell is never active. Sharing is pointless, we simply remove it.\n"); + log(" Cell is never active. Sharing is pointless, we simply remove it.\n"); shareable_cells.erase(other_cell); + cells_to_remove.insert(other_cell); continue; } if (other_cell_activation_patterns.count(std::pair())) { - log (" Cell is always active. Therefore no sharing is possible.\n"); + log(" Cell is always active. Therefore no sharing is possible.\n"); + shareable_cells.erase(other_cell); continue; } @@ -750,8 +753,6 @@ struct ShareWorker optimize_activation_patterns(filtered_other_cell_activation_patterns); ezDefaultSAT ez; - ez.non_incremental(); - SatGen satgen(&ez, &modwalker.sigmap); std::set sat_cells; @@ -798,6 +799,21 @@ struct ShareWorker break; } + if (!ez.solve(ez.expression(ez.OpOr, cell_active))) { + log(" According to the SAT solver the cell %s is never active. Sharing is pointless, we simply remove it.\n", log_id(cell)); + cells_to_remove.insert(cell); + break; + } + + if (!ez.solve(ez.expression(ez.OpOr, other_cell_active))) { + log(" According to the SAT solver the cell %s is never active. Sharing is pointless, we simply remove it.\n", log_id(other_cell)); + cells_to_remove.insert(other_cell); + shareable_cells.erase(other_cell); + continue; + } + + ez.non_incremental(); + all_ctrl_signals.sort_and_unify(); std::vector sat_model = satgen.importSigSpec(all_ctrl_signals); std::vector sat_model_values; -- cgit v1.2.3 From 788bd02f970859bb67c5dbb7b503f23904257f7b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 10 Aug 2014 12:04:02 +0200 Subject: Fixed FSM mapping for multiple reset-like signals --- passes/fsm/fsm_map.cc | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc index b3750de08..048cf7e5f 100644 --- a/passes/fsm/fsm_map.cc +++ b/passes/fsm/fsm_map.cc @@ -25,6 +25,20 @@ #include "fsmdata.h" #include +static bool pattern_is_subset(const RTLIL::Const &super_pattern, const RTLIL::Const &sub_pattern) +{ + log_assert(SIZE(super_pattern.bits) == SIZE(sub_pattern.bits)); + for (int i = 0; i < SIZE(super_pattern.bits); i++) + if (sub_pattern.bits[i] == RTLIL::State::S0 || sub_pattern.bits[i] == RTLIL::State::S1) { + if (super_pattern.bits[i] == RTLIL::State::S0 || super_pattern.bits[i] == RTLIL::State::S1) { + if (super_pattern.bits[i] != sub_pattern.bits[i]) + return false; + } else + return false; + } + return true; +} + static void implement_pattern_cache(RTLIL::Module *module, std::map> &pattern_cache, std::set &fullstate_cache, int num_states, RTLIL::Wire *state_onehot, RTLIL::SigSpec &ctrl_in, RTLIL::SigSpec output) { RTLIL::SigSpec cases_vector; @@ -68,7 +82,13 @@ static void implement_pattern_cache(RTLIL::Module *module, std::mapparameters["\\Y_WIDTH"] = RTLIL::Const(1); } - if (or_sig.size() < num_states-int(fullstate_cache.size())) + std::set complete_in_state_cache = it.second; + + for (auto &it2 : pattern_cache) + if (pattern_is_subset(pattern, it2.first)) + complete_in_state_cache.insert(it2.second.begin(), it2.second.end()); + + if (SIZE(complete_in_state_cache) < num_states) { if (or_sig.size() == 1) { -- cgit v1.2.3 From 9d353fc543295db7d6f4b4ba60c2b66a509b3ee2 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 12 Aug 2014 17:35:22 +0200 Subject: Fixed handling of constant-true branches in proc_clean --- passes/proc/proc_clean.cc | 3 ++- passes/proc/proc_rmdead.cc | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) (limited to 'passes') diff --git a/passes/proc/proc_clean.cc b/passes/proc/proc_clean.cc index 13be0ddb6..1e3dd9ce7 100644 --- a/passes/proc/proc_clean.cc +++ b/passes/proc/proc_clean.cc @@ -59,7 +59,8 @@ void proc_clean_switch(RTLIL::SwitchRule *sw, RTLIL::CaseRule *parent, bool &did sw->signal = RTLIL::SigSpec(); } - if (sw->cases.size() == 1 && (sw->signal.size() == 0 || sw->cases[0]->compare.empty())) + if (parent->switches.front() == sw && sw->cases.size() == 1 && + (sw->signal.size() == 0 || sw->cases[0]->compare.empty())) { did_something = true; for (auto &action : sw->cases[0]->actions) diff --git a/passes/proc/proc_rmdead.cc b/passes/proc/proc_rmdead.cc index 61844d5eb..fe3532da8 100644 --- a/passes/proc/proc_rmdead.cc +++ b/passes/proc/proc_rmdead.cc @@ -31,7 +31,7 @@ static void proc_rmdead(RTLIL::SwitchRule *sw, int &counter) for (size_t i = 0; i < sw->cases.size(); i++) { - bool is_default = sw->cases[i]->compare.size() == 0 && !pool.empty(); + bool is_default = SIZE(sw->cases[i]->compare) == 0 && (!pool.empty() || SIZE(sw->signal) == 0); for (size_t j = 0; j < sw->cases[i]->compare.size(); j++) { RTLIL::SigSpec sig = sw->cases[i]->compare[j]; -- cgit v1.2.3 From 28bc7aeb9345377d7815ad5ae9a941e55409bc4b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 13 Aug 2014 13:40:29 +0200 Subject: Filter ANSI escape sequences from ABC output --- passes/abc/abc.cc | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'passes') diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index 77419e616..b9baea38b 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -639,10 +639,25 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std log("ABC: %s", logbuf); #else bool got_cr = false; + int escape_seq_state = 0; std::string linebuf; char logbuf[1024]; while (fgets(logbuf, 1024, f) != NULL) for (char *p = logbuf; *p; p++) { + if (escape_seq_state == 0 && *p == '\033') { + escape_seq_state = 1; + continue; + } + if (escape_seq_state == 1) { + escape_seq_state = *p == '[' ? 2 : 0; + continue; + } + if (escape_seq_state == 2) { + if ((*p < '0' || '9' < *p) && *p != ';') + escape_seq_state = 0; + continue; + } + escape_seq_state = 0; if (*p == '\r') { got_cr = true; continue; -- cgit v1.2.3 From 996c06f64dcb1619584c88d101c5ba258b2b26af Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 14 Aug 2014 11:05:25 +0200 Subject: Added "abc -D" for setting delay target --- passes/abc/abc.cc | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) (limited to 'passes') diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index b9baea38b..e7da6ed4a 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -29,8 +29,8 @@ // Kahn, Arthur B. (1962), "Topological sorting of large networks", Communications of the ACM 5 (11): 558–562, doi:10.1145/368996.369025 // http://en.wikipedia.org/wiki/Topological_sorting -#define ABC_COMMAND_LIB "strash; scorr -v; ifraig -v; retime -v; strash; dch -vf; map -v" -#define ABC_COMMAND_CTR "strash; scorr -v; ifraig -v; retime -v; strash; dch -vf; map -v; buffer -v; upsize -v; dnsize -v; stime -p" +#define ABC_COMMAND_LIB "strash; scorr -v; ifraig -v; retime -v {D}; strash; dch -vf; map -v {D}" +#define ABC_COMMAND_CTR "strash; scorr -v; ifraig -v; retime -v {D}; strash; dch -vf; map -v {D}; buffer -v; upsize -v {D}; dnsize -v {D}; stime -p" #define ABC_COMMAND_LUT "strash; scorr -v; ifraig -v; retime -v; strash; dch -vf; if -v" #define ABC_COMMAND_DFL "strash; scorr -v; ifraig -v; retime -v; strash; dch -vf; map -v" @@ -397,7 +397,8 @@ static std::string fold_abc_cmd(std::string str) } static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::string script_file, std::string exe_file, - std::string liberty_file, std::string constr_file, bool cleanup, int lut_mode, bool dff_mode, std::string clk_str, bool keepff) + std::string liberty_file, std::string constr_file, bool cleanup, int lut_mode, bool dff_mode, std::string clk_str, + bool keepff, std::string delay_target) { module = current_module; map_autoidx = autoidx++; @@ -435,6 +436,10 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std abc_command = constr_file.empty() ? ABC_COMMAND_LIB : ABC_COMMAND_CTR; else abc_command = ABC_COMMAND_DFL; + + for (size_t pos = abc_command.find("{D}"); pos != std::string::npos; pos = abc_command.find("{D}", pos)) + abc_command = abc_command.substr(0, pos) + delay_target + abc_command.substr(pos+3); + abc_command = add_echos_to_abc_cmd(abc_command); if (abc_command.size() > 128) { @@ -915,6 +920,10 @@ struct AbcPass : public Pass { log(" drive the primary inputs and the set_load statement sets the load in\n"); log(" femtofarads for each primary output.\n"); log("\n"); + log(" -D \n"); + log(" set delay target. the string {D} in the default scripts above is\n"); + log(" replaced by this option when used, and an empty string otherwise.\n"); + log("\n"); log(" -lut \n"); log(" generate netlist using luts of (max) the specified width.\n"); log("\n"); @@ -951,7 +960,7 @@ struct AbcPass : public Pass { log_push(); std::string exe_file = proc_self_dirname() + "yosys-abc"; - std::string script_file, liberty_file, constr_file, clk_str; + std::string script_file, liberty_file, constr_file, clk_str, delay_target; bool dff_mode = false, keepff = false, cleanup = true; int lut_mode = 0; @@ -985,6 +994,10 @@ struct AbcPass : public Pass { constr_file = std::string(pwd) + "/" + constr_file; continue; } + if (arg == "-D" && argidx+1 < args.size()) { + delay_target = "-D " + args[++argidx]; + continue; + } if (arg == "-lut" && argidx+1 < args.size()) { lut_mode = atoi(args[++argidx].c_str()); continue; @@ -1019,7 +1032,7 @@ struct AbcPass : public Pass { if (mod_it.second->processes.size() > 0) log("Skipping module %s as it contains processes.\n", mod_it.second->name.c_str()); else - abc_module(design, mod_it.second, script_file, exe_file, liberty_file, constr_file, cleanup, lut_mode, dff_mode, clk_str, keepff); + abc_module(design, mod_it.second, script_file, exe_file, liberty_file, constr_file, cleanup, lut_mode, dff_mode, clk_str, keepff, delay_target); } assign_map.clear(); -- cgit v1.2.3 From 28cf48e31f049f8343023de46cd916ac47fcfc5d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 14 Aug 2014 11:22:45 +0200 Subject: Some improvements in FSM mapping and recoding --- passes/fsm/fsm_map.cc | 2 +- passes/fsm/fsm_recode.cc | 22 +++++++++++++++------- 2 files changed, 16 insertions(+), 8 deletions(-) (limited to 'passes') diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc index 048cf7e5f..60580eb46 100644 --- a/passes/fsm/fsm_map.cc +++ b/passes/fsm/fsm_map.cc @@ -285,7 +285,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) } } - RTLIL::Cell *mux_cell = module->addCell(NEW_ID, "$safe_pmux"); + RTLIL::Cell *mux_cell = module->addCell(NEW_ID, "$pmux"); mux_cell->setPort("\\A", sig_a); mux_cell->setPort("\\B", sig_b); mux_cell->setPort("\\S", sig_s); diff --git a/passes/fsm/fsm_recode.cc b/passes/fsm/fsm_recode.cc index 40fed130e..9c0da0a37 100644 --- a/passes/fsm/fsm_recode.cc +++ b/passes/fsm/fsm_recode.cc @@ -53,10 +53,10 @@ static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fs std::string encoding = cell->attributes.count("\\fsm_encoding") ? cell->attributes.at("\\fsm_encoding").decode_string() : "auto"; log("Recoding FSM `%s' from module `%s' using `%s' encoding:\n", cell->name.c_str(), module->name.c_str(), encoding.c_str()); - if (encoding != "none" && encoding != "one-hot" && encoding != "binary") { - if (encoding != "auto") - log(" unkown encoding `%s': using auto (%s) instead.\n", encoding.c_str(), default_encoding.c_str()); - encoding = default_encoding; + + if (encoding != "none" && encoding != "one-hot" && encoding != "binary" && encoding != "auto") { + log(" unkown encoding `%s': using auto instead.\n", encoding.c_str()); + encoding = "auto"; } if (encoding == "none") { @@ -70,10 +70,18 @@ static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fs if (fm_set_fsm_file != NULL) fm_set_fsm_print(cell, module, fsm_data, "r", fm_set_fsm_file); + if (encoding == "auto") { + if (!default_encoding.empty()) + encoding = default_encoding; + else + encoding = SIZE(fsm_data.state_table) < 32 ? "one-hot" : "binary"; + log(" mapping auto encoding to `%s` for this FSM.\n", encoding.c_str()); + } + if (encoding == "one-hot") { fsm_data.state_bits = fsm_data.state_table.size(); } else - if (encoding == "auto" || encoding == "binary") { + if (encoding == "binary") { fsm_data.state_bits = ceil(log2(fsm_data.state_table.size())); } else log_error("FSM encoding `%s' is not supported!\n", encoding.c_str()); @@ -88,7 +96,7 @@ static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fs new_code = RTLIL::Const(RTLIL::State::Sa, fsm_data.state_bits); new_code.bits[state_idx] = RTLIL::State::S1; } else - if (encoding == "auto" || encoding == "binary") { + if (encoding == "binary") { new_code = RTLIL::Const(state_idx, fsm_data.state_bits); } else log_abort(); @@ -124,7 +132,7 @@ struct FsmRecodePass : public Pass { virtual void execute(std::vector args, RTLIL::Design *design) { FILE *fm_set_fsm_file = NULL; - std::string default_encoding = "one-hot"; + std::string default_encoding; log_header("Executing FSM_RECODE pass (re-assigning FSM state encoding).\n"); size_t argidx; -- cgit v1.2.3 From 13f2f36884fa3e4a8329dab2556af7000cb085df Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 14 Aug 2014 11:39:46 +0200 Subject: RIP $safe_pmux --- passes/cmds/wreduce.cc | 4 ++-- passes/fsm/fsm_detect.cc | 2 +- passes/fsm/fsm_expand.cc | 2 +- passes/fsm/fsm_extract.cc | 2 +- passes/opt/opt_muxtree.cc | 2 +- passes/opt/opt_reduce.cc | 2 +- passes/opt/opt_share.cc | 1 - passes/tests/test_cell.cc | 1 - 8 files changed, 7 insertions(+), 9 deletions(-) (limited to 'passes') diff --git a/passes/cmds/wreduce.cc b/passes/cmds/wreduce.cc index 6723a57fe..2269859d1 100644 --- a/passes/cmds/wreduce.cc +++ b/passes/cmds/wreduce.cc @@ -42,7 +42,7 @@ struct WreduceConfig supported_cell_types << "$shl" << "$shr" << "$sshl" << "$sshr" << "$shift" << "$shiftx"; supported_cell_types << "$lt" << "$le" << "$eq" << "$ne" << "$eqx" << "$nex" << "$ge" << "$gt"; supported_cell_types << "$add" << "$sub"; // << "$mul" << "$div" << "$mod" << "$pow" - supported_cell_types << "$mux" << "$pmux" << "$safe_pmux"; + supported_cell_types << "$mux" << "$pmux"; } }; @@ -172,7 +172,7 @@ struct WreduceWorker if (!cell->type.in(config->supported_cell_types)) return; - if (cell->type.in("$mux", "$pmux", "$safe_pmux")) + if (cell->type.in("$mux", "$pmux")) return run_cell_mux(cell); diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc index 5675dff50..2c846a4cf 100644 --- a/passes/fsm/fsm_detect.cc +++ b/passes/fsm/fsm_detect.cc @@ -50,7 +50,7 @@ static bool check_state_mux_tree(RTLIL::SigSpec old_sig, RTLIL::SigSpec sig, Sig std::set cellport_list; sig2driver.find(sig, cellport_list); for (auto &cellport : cellport_list) { - if ((cellport.first->type != "$mux" && cellport.first->type != "$pmux" && cellport.first->type != "$safe_pmux") || cellport.second != "\\Y") + if ((cellport.first->type != "$mux" && cellport.first->type != "$pmux") || cellport.second != "\\Y") return false; RTLIL::SigSpec sig_a = assign_map(cellport.first->getPort("\\A")); RTLIL::SigSpec sig_b = assign_map(cellport.first->getPort("\\B")); diff --git a/passes/fsm/fsm_expand.cc b/passes/fsm/fsm_expand.cc index 670fae1d9..77821326d 100644 --- a/passes/fsm/fsm_expand.cc +++ b/passes/fsm/fsm_expand.cc @@ -42,7 +42,7 @@ struct FsmExpand bool is_cell_merge_candidate(RTLIL::Cell *cell) { - if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux") + if (cell->type == "$mux" || cell->type == "$pmux") if (cell->getPort("\\A").size() < 2) return true; diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index ebe3073de..871478dee 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -55,7 +55,7 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL for (auto &cellport : cellport_list) { RTLIL::Cell *cell = module->cells_.at(cellport.first); - if ((cell->type != "$mux" && cell->type != "$pmux" && cell->type != "$safe_pmux") || cellport.second != "\\Y") { + if ((cell->type != "$mux" && cell->type != "$pmux") || cellport.second != "\\Y") { log(" unexpected cell type %s (%s) found in state selection tree.\n", cell->type.c_str(), cell->name.c_str()); return false; } diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc index 2660b33d4..daa063812 100644 --- a/passes/opt/opt_muxtree.cc +++ b/passes/opt/opt_muxtree.cc @@ -84,7 +84,7 @@ struct OptMuxtreeWorker // .const_activated for (auto cell : module->cells()) { - if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux") + if (cell->type == "$mux" || cell->type == "$pmux") { RTLIL::SigSpec sig_a = cell->getPort("\\A"); RTLIL::SigSpec sig_b = cell->getPort("\\B"); diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc index 5f3c4d29e..e2b4243d1 100644 --- a/passes/opt/opt_reduce.cc +++ b/passes/opt/opt_reduce.cc @@ -312,7 +312,7 @@ struct OptReduceWorker std::vector cells; for (auto &it : module->cells_) - if ((it.second->type == "$mux" || it.second->type == "$pmux" || it.second->type == "$safe_pmux") && design->selected(module, it.second)) + if ((it.second->type == "$mux" || it.second->type == "$pmux") && design->selected(module, it.second)) cells.push_back(it.second); for (auto cell : cells) diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc index eb970329d..e9a5e7fde 100644 --- a/passes/opt/opt_share.cc +++ b/passes/opt/opt_share.cc @@ -224,7 +224,6 @@ struct OptShareWorker if (mode_nomux) { ct.cell_types.erase("$mux"); ct.cell_types.erase("$pmux"); - ct.cell_types.erase("$safe_pmux"); } log("Finding identical cells in module `%s'.\n", module->name.c_str()); diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index 946490135..94d5d27b1 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -176,7 +176,6 @@ struct TestCellPass : public Pass { // cell_types["$pmux"] = "A"; // cell_types["$slice"] = "A"; // cell_types["$concat"] = "A"; - // cell_types["$safe_pmux"] = "A"; // cell_types["$lut"] = "A"; // cell_types["$assert"] = "A"; -- cgit v1.2.3 From 1bf7a18fec76cf46a5b8710a75371e23b68d147d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 14 Aug 2014 16:13:42 +0200 Subject: Added module->ports --- passes/abc/blifparse.cc | 3 +-- passes/hierarchy/hierarchy.cc | 2 ++ passes/hierarchy/submod.cc | 7 +++---- passes/techmap/extract.cc | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) (limited to 'passes') diff --git a/passes/abc/blifparse.cc b/passes/abc/blifparse.cc index 1891a7450..bc8f343a5 100644 --- a/passes/abc/blifparse.cc +++ b/passes/abc/blifparse.cc @@ -58,7 +58,6 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name) RTLIL::Const *lutptr = NULL; RTLIL::State lut_default_state = RTLIL::State::Sx; - int port_count = 0; module->name = "\\netlist"; design->add(module); @@ -91,6 +90,7 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name) continue; if (!strcmp(cmd, ".end")) { + module->fixup_ports(); free(buffer); return design; } @@ -99,7 +99,6 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name) char *p; while ((p = strtok(NULL, " \t\r\n")) != NULL) { RTLIL::Wire *wire = module->addWire(stringf("\\%s", p)); - wire->port_id = ++port_count; if (!strcmp(cmd, ".inputs")) wire->port_input = true; else diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 50b4989df..2f28afb25 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -126,6 +126,8 @@ static void generate(RTLIL::Design *design, const std::vector &cell wire->port_output = decl.output; } + mod->fixup_ports(); + for (auto ¶ : parameters) log(" ignoring parameter %s.\n", RTLIL::id2cstr(para)); diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index 89f45e025..1b03ab555 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -106,7 +106,7 @@ struct SubmodWorker RTLIL::Module *new_mod = new RTLIL::Module; new_mod->name = submod.full_name; design->add(new_mod); - int port_counter = 1, auto_name_counter = 1; + int auto_name_counter = 1; std::set all_wire_names; for (auto &it : wire_flags) { @@ -151,9 +151,6 @@ struct SubmodWorker new_wire->start_offset = wire->start_offset; new_wire->attributes = wire->attributes; - if (new_wire->port_input || new_wire->port_output) - new_wire->port_id = port_counter++; - if (new_wire->port_input && new_wire->port_output) log(" signal %s: inout %s\n", wire->name.c_str(), new_wire->name.c_str()); else if (new_wire->port_input) @@ -166,6 +163,8 @@ struct SubmodWorker flags.new_wire = new_wire; } + new_mod->fixup_ports(); + for (RTLIL::Cell *cell : submod.cells) { RTLIL::Cell *new_cell = new_mod->addCell(cell->name, cell); for (auto &conn : new_cell->connections_) diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index 985d51e50..ebf4d77fc 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -726,14 +726,14 @@ struct ExtractPass : public Pass { newMod->name = stringf("\\needle%05d_%s_%dx", needleCounter++, id2cstr(haystack_map.at(result.graphId)->name), result.totalMatchesAfterLimits); map->add(newMod); - int portCounter = 1; for (auto wire : wires) { RTLIL::Wire *newWire = newMod->addWire(wire->name, wire->width); - newWire->port_id = portCounter++; newWire->port_input = true; newWire->port_output = true; } + newMod->fixup_ports(); + for (auto cell : cells) { RTLIL::Cell *newCell = newMod->addCell(cell->name, cell->type); newCell->parameters = cell->parameters; -- cgit v1.2.3 From d320e750877a6cf8d5993da6d2cd121fe5b4d78e Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 15 Aug 2014 02:00:53 +0200 Subject: document "techmap -map %" --- passes/techmap/techmap.cc | 3 +++ 1 file changed, 3 insertions(+) (limited to 'passes') diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 29ce96766..a7f91e862 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -706,6 +706,9 @@ struct TechmapPass : public Pass { log(" transforms the internal RTL cells to the internal gate\n"); log(" library.\n"); log("\n"); + log(" -map %%\n"); + log(" like -map above, but with an in-memory design instead of a file.\n"); + log("\n"); log(" -share_map filename\n"); log(" like -map, but look for the file in the share directory (where the\n"); log(" yosys data files are). this is mainly used internally when techmap\n"); -- cgit v1.2.3 From ca8711644975c128d45fd8e9434439c1266c00ac Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 15 Aug 2014 02:40:46 +0200 Subject: More idstring sort_by_* helpers and fixed tpl ordering in techmap --- passes/fsm/fsm_expand.cc | 8 ++++---- passes/opt/opt_clean.cc | 4 ++-- passes/techmap/techmap.cc | 6 +++--- 3 files changed, 9 insertions(+), 9 deletions(-) (limited to 'passes') diff --git a/passes/fsm/fsm_expand.cc b/passes/fsm/fsm_expand.cc index 77821326d..d13643911 100644 --- a/passes/fsm/fsm_expand.cc +++ b/passes/fsm/fsm_expand.cc @@ -30,12 +30,12 @@ struct FsmExpand RTLIL::Module *module; RTLIL::Cell *fsm_cell; SigMap assign_map; - SigSet> sig2driver, sig2user; + SigSet> sig2driver, sig2user; CellTypes ct; - std::set> merged_set; - std::set> current_set; - std::set> no_candidate_set; + std::set> merged_set; + std::set> current_set; + std::set> no_candidate_set; bool already_optimized; int limit_transitions; diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index c620531e3..d47e4513e 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -34,7 +34,7 @@ static int count_rm_cells, count_rm_wires; static void rmunused_module_cells(RTLIL::Module *module, bool verbose) { SigMap assign_map(module); - std::set> queue, unused; + std::set> queue, unused; SigSet wire2driver; for (auto &it : module->cells_) { @@ -65,7 +65,7 @@ static void rmunused_module_cells(RTLIL::Module *module, bool verbose) while (queue.size() > 0) { - std::set> new_queue; + std::set> new_queue; for (auto cell : queue) unused.erase(cell); for (auto cell : queue) { diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index a7f91e862..59173393c 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -251,7 +251,7 @@ struct TechmapWorker } bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, std::set &handled_cells, - const std::map> &celltypeMap, bool in_recursion) + const std::map> &celltypeMap, bool in_recursion) { std::string mapmsg_prefix = in_recursion ? "Recursively mapping" : "Mapping"; @@ -898,7 +898,7 @@ struct TechmapPass : public Pass { } map->modules_.swap(modules_new); - std::map> celltypeMap; + std::map> celltypeMap; for (auto &it : map->modules_) { if (it.second->attributes.count("\\techmap_celltype") && !it.second->attributes.at("\\techmap_celltype").bits.empty()) { char *p = strdup(it.second->attributes.at("\\techmap_celltype").decode_string().c_str()); @@ -960,7 +960,7 @@ struct FlattenPass : public Pass { TechmapWorker worker; worker.flatten_mode = true; - std::map> celltypeMap; + std::map> celltypeMap; for (auto &it : design->modules_) celltypeMap[it.first].insert(it.first); -- cgit v1.2.3 From f092b5014895dc5dc62b8103fcedf94cfa9f85a8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 15 Aug 2014 14:11:40 +0200 Subject: Renamed $_INV_ cell type to $_NOT_ --- passes/abc/abc.cc | 4 ++-- passes/opt/opt_const.cc | 12 ++++++------ passes/sat/freduce.cc | 4 ++-- passes/techmap/dfflibmap.cc | 2 +- passes/techmap/simplemap.cc | 8 ++++---- 5 files changed, 15 insertions(+), 15 deletions(-) (limited to 'passes') diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index e7da6ed4a..2b1d49810 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -130,7 +130,7 @@ static void extract_cell(RTLIL::Cell *cell, bool keepff) return; } - if (cell->type == "$_INV_") + if (cell->type == "$_NOT_") { RTLIL::SigSpec sig_a = cell->getPort("\\A"); RTLIL::SigSpec sig_y = cell->getPort("\\Y"); @@ -733,7 +733,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std continue; } if (c->type == "\\INV") { - RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_INV_"); + RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_NOT_"); cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)])); cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)])); design->select(module, cell); diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index a13bb09cb..9af1e6bdf 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -209,7 +209,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo for (auto cell : module->cells()) if (design->selected(module, cell) && cell->type[0] == '$') { - if ((cell->type == "$_INV_" || cell->type == "$not" || cell->type == "$logic_not") && + if ((cell->type == "$_NOT_" || cell->type == "$not" || cell->type == "$logic_not") && cell->getPort("\\A").size() == 1 && cell->getPort("\\Y").size() == 1) invert_map[assign_map(cell->getPort("\\Y"))] = assign_map(cell->getPort("\\A")); if (ct_combinational.cell_known(cell->type)) @@ -371,9 +371,9 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo } } - if ((cell->type == "$_INV_" || cell->type == "$not" || cell->type == "$logic_not") && cell->getPort("\\Y").size() == 1 && + if ((cell->type == "$_NOT_" || cell->type == "$not" || cell->type == "$logic_not") && cell->getPort("\\Y").size() == 1 && invert_map.count(assign_map(cell->getPort("\\A"))) != 0) { - cover_list("opt.opt_const.invert.double", "$_INV_", "$not", "$logic_not", cell->type.str()); + cover_list("opt.opt_const.invert.double", "$_NOT_", "$not", "$logic_not", cell->type.str()); replace_cell(assign_map, module, cell, "double_invert", "\\Y", invert_map.at(assign_map(cell->getPort("\\A")))); goto next_cell; } @@ -389,7 +389,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo goto next_cell; } - if (cell->type == "$_INV_") { + if (cell->type == "$_NOT_") { RTLIL::SigSpec input = cell->getPort("\\A"); assign_map.apply(input); if (input.match("1")) ACTION_DO_Y(0); @@ -463,7 +463,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (input.match("01 ")) ACTION_DO("\\Y", input.extract(0, 1)); if (input.match("10 ")) { cover("opt.opt_const.mux_to_inv"); - cell->type = "$_INV_"; + cell->type = "$_NOT_"; cell->setPort("\\A", input.extract(0, 1)); cell->unsetPort("\\B"); cell->unsetPort("\\S"); @@ -648,7 +648,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cell->parameters.erase("\\WIDTH"); cell->type = "$not"; } else - cell->type = "$_INV_"; + cell->type = "$_NOT_"; OPT_DID_SOMETHING = true; did_something = true; goto next_cell; diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index 7b9fb2072..bfed0005d 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -623,7 +623,7 @@ struct FreduceWorker batches.push_back(outputs); bits_full_total += outputs.size(); } - if (inv_mode && it.second->type == "$_INV_") + if (inv_mode && it.second->type == "$_NOT_") inv_pairs.insert(std::pair(sigmap(it.second->getPort("\\A")), sigmap(it.second->getPort("\\Y")))); } @@ -718,7 +718,7 @@ struct FreduceWorker { inv_sig = module->addWire(NEW_ID); - RTLIL::Cell *inv_cell = module->addCell(NEW_ID, "$_INV_"); + RTLIL::Cell *inv_cell = module->addCell(NEW_ID, "$_NOT_"); inv_cell->setPort("\\A", grp[0].bit); inv_cell->setPort("\\Y", inv_sig); } diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc index 16518b7df..6ce771ac4 100644 --- a/passes/techmap/dfflibmap.cc +++ b/passes/techmap/dfflibmap.cc @@ -411,7 +411,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module) } else if ('a' <= port.second && port.second <= 'z') { sig = cell_connections[std::string("\\") + char(port.second - ('a' - 'A'))]; - sig = module->InvGate(NEW_ID, sig); + sig = module->NotGate(NEW_ID, sig); } else if (port.second == '0' || port.second == '1') { sig = RTLIL::SigSpec(port.second == '0' ? 0 : 1, 1); diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc index 960578b06..f5d9bbeef 100644 --- a/passes/techmap/simplemap.cc +++ b/passes/techmap/simplemap.cc @@ -34,7 +34,7 @@ static void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell) sig_a.extend(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool()); for (int i = 0; i < SIZE(sig_y); i++) { - RTLIL::Cell *gate = module->addCell(NEW_ID, "$_INV_"); + RTLIL::Cell *gate = module->addCell(NEW_ID, "$_NOT_"); gate->setPort("\\A", sig_a[i]); gate->setPort("\\Y", sig_y[i]); } @@ -74,7 +74,7 @@ static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::SigSpec sig_t = module->addWire(NEW_ID, SIZE(sig_y)); for (int i = 0; i < SIZE(sig_y); i++) { - RTLIL::Cell *gate = module->addCell(NEW_ID, "$_INV_"); + RTLIL::Cell *gate = module->addCell(NEW_ID, "$_NOT_"); gate->setPort("\\A", sig_t[i]); gate->setPort("\\Y", sig_y[i]); } @@ -152,7 +152,7 @@ static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) if (cell->type == "$reduce_xnor") { RTLIL::SigSpec sig_t = module->addWire(NEW_ID); - RTLIL::Cell *gate = module->addCell(NEW_ID, "$_INV_"); + RTLIL::Cell *gate = module->addCell(NEW_ID, "$_NOT_"); gate->setPort("\\A", sig_a); gate->setPort("\\Y", sig_t); last_output_cell = gate; @@ -207,7 +207,7 @@ static void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell) sig_y = sig_y.extract(0, 1); } - RTLIL::Cell *gate = module->addCell(NEW_ID, "$_INV_"); + RTLIL::Cell *gate = module->addCell(NEW_ID, "$_NOT_"); gate->setPort("\\A", sig_a); gate->setPort("\\Y", sig_y); } -- cgit v1.2.3 From b64b38eea2e9a7de30d6045f069c86bf4446134f Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 15 Aug 2014 14:18:40 +0200 Subject: Renamed $lut ports to follow A-Y naming scheme --- passes/abc/blifparse.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'passes') diff --git a/passes/abc/blifparse.cc b/passes/abc/blifparse.cc index bc8f343a5..1fbb5720d 100644 --- a/passes/abc/blifparse.cc +++ b/passes/abc/blifparse.cc @@ -195,8 +195,8 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name) RTLIL::Cell *cell = module->addCell(NEW_ID, "$lut"); cell->parameters["\\WIDTH"] = RTLIL::Const(input_sig.size()); cell->parameters["\\LUT"] = RTLIL::Const(RTLIL::State::Sx, 1 << input_sig.size()); - cell->setPort("\\I", input_sig); - cell->setPort("\\O", output_sig); + cell->setPort("\\A", input_sig); + cell->setPort("\\Y", output_sig); lutptr = &cell->parameters.at("\\LUT"); lut_default_state = RTLIL::State::Sx; continue; -- cgit v1.2.3 From 674f421b476295d3376ec00644181fc9be02ccaf Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 15 Aug 2014 14:29:42 +0200 Subject: Bugfix in iopadmap --- passes/techmap/iopadmap.cc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc index 194e06a4a..9cd23ce6f 100644 --- a/passes/techmap/iopadmap.cc +++ b/passes/techmap/iopadmap.cc @@ -164,8 +164,10 @@ struct IopadmapPass : public Pass { log("Mapping port %s.%s using %s.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name), celltype.c_str()); RTLIL::Wire *new_wire = NULL; - if (!portname2.empty()) + if (!portname2.empty()) { new_wire = module->addWire(NEW_ID, wire); + module->swap_names(new_wire, wire); + } if (flag_bits) { -- cgit v1.2.3 From eb17fbade5ef89983993d1e9d47da5f8a2fb32c3 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 16 Aug 2014 15:34:15 +0200 Subject: Added "opt -fast" --- passes/opt/opt.cc | 64 ++++++++++++++++++++++++++++++++++++++----------------- 1 file changed, 45 insertions(+), 19 deletions(-) (limited to 'passes') diff --git a/passes/opt/opt.cc b/passes/opt/opt.cc index 33e1507bc..b6d36f0e3 100644 --- a/passes/opt/opt.cc +++ b/passes/opt/opt.cc @@ -37,7 +37,7 @@ struct OptPass : public Pass { log("a series of trivial optimizations and cleanups. This pass executes the other\n"); log("passes in the following order:\n"); log("\n"); - log(" opt_const\n"); + log(" opt_const [-mux_undef] [-mux_bool] [-undriven] [-fine] [-keepdc]\n"); log(" opt_share -nomux\n"); log("\n"); log(" do\n"); @@ -49,15 +49,26 @@ struct OptPass : public Pass { log(" opt_const [-mux_undef] [-mux_bool] [-undriven] [-fine] [-keepdc]\n"); log(" while \n"); log("\n"); + log("When called with -fast the following script is used instead:\n"); + log("\n"); + log(" do\n"); + log(" opt_const [-mux_undef] [-mux_bool] [-undriven] [-fine] [-keepdc]\n"); + log(" opt_share\n"); + log(" opt_rmdff\n"); + log(" opt_clean [-purge]\n"); + log(" while \n"); + log("\n"); log("Note: Options in square brackets (such as [-keepdc]) are passed through to\n"); log("the opt_* commands when given to 'opt'.\n"); log("\n"); + log("\n"); } virtual void execute(std::vector args, RTLIL::Design *design) { std::string opt_clean_args; std::string opt_const_args; std::string opt_reduce_args; + bool fast_mode = false; log_header("Executing OPT pass (performing simple optimizations).\n"); log_push(); @@ -89,32 +100,47 @@ struct OptPass : public Pass { opt_const_args += " -keepdc"; continue; } + if (args[argidx] == "-fast") { + fast_mode = true; + continue; + } break; } extra_args(args, argidx, design); - log_header("Optimizing in-memory representation of design.\n"); - design->optimize(); - - Pass::call(design, "opt_const"); - Pass::call(design, "opt_share -nomux"); - while (1) { - OPT_DID_SOMETHING = false; - Pass::call(design, "opt_muxtree"); - Pass::call(design, "opt_reduce" + opt_reduce_args); - Pass::call(design, "opt_share"); - Pass::call(design, "opt_rmdff"); + if (fast_mode) + { + while (1) { + Pass::call(design, "opt_const" + opt_const_args); + Pass::call(design, "opt_share"); + OPT_DID_SOMETHING = false; + Pass::call(design, "opt_rmdff"); + if (OPT_DID_SOMETHING == false) + break; + Pass::call(design, "opt_clean" + opt_clean_args); + log_header("Rerunning OPT passes. (Removed registers in this run.)\n"); + } Pass::call(design, "opt_clean" + opt_clean_args); + } + else + { Pass::call(design, "opt_const" + opt_const_args); - if (OPT_DID_SOMETHING == false) - break; - log_header("Rerunning OPT passes. (Maybe there is more to do..)\n"); + Pass::call(design, "opt_share -nomux"); + while (1) { + OPT_DID_SOMETHING = false; + Pass::call(design, "opt_muxtree"); + Pass::call(design, "opt_reduce" + opt_reduce_args); + Pass::call(design, "opt_share"); + Pass::call(design, "opt_rmdff"); + Pass::call(design, "opt_clean" + opt_clean_args); + Pass::call(design, "opt_const" + opt_const_args); + if (OPT_DID_SOMETHING == false) + break; + log_header("Rerunning OPT passes. (Maybe there is more to do..)\n"); + } } - log_header("Optimizing in-memory representation of design.\n"); - design->optimize(); - - log_header("Finished OPT passes. (There is nothing left to do.)\n"); + log_header(fast_mode ? "Finished fast OPT passes." : "Finished OPT passes. (There is nothing left to do.)\n"); log_pop(); } } OptPass; -- cgit v1.2.3 From 47c2637a961839f1eb1a0386f7e54d94be50bc10 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 16 Aug 2014 18:18:30 +0200 Subject: Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_ --- passes/abc/abc.cc | 186 ++++++++++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 161 insertions(+), 25 deletions(-) (limited to 'passes') diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index 2b1d49810..fd56668cf 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -48,11 +48,30 @@ #include "blifparse.h" +enum class gate_type_t { + G_NONE, + G_FF, + G_NOT, + G_AND, + G_NAND, + G_OR, + G_NOR, + G_XOR, + G_XNOR, + G_MUX, + G_AOI3, + G_OAI3, + G_AOI4, + G_OAI4 +}; + +#define G(_name) gate_type_t::G_ ## _name + struct gate_t { int id; - char type; - int in1, in2, in3; + gate_type_t type; + int in1, in2, in3, in4; bool is_port; RTLIL::SigBit bit; }; @@ -66,17 +85,18 @@ static std::map signal_map; static bool clk_polarity; static RTLIL::SigSpec clk_sig; -static int map_signal(RTLIL::SigBit bit, char gate_type = -1, int in1 = -1, int in2 = -1, int in3 = -1) +static int map_signal(RTLIL::SigBit bit, gate_type_t gate_type = G(NONE), int in1 = -1, int in2 = -1, int in3 = -1, int in4 = -1) { assign_map.apply(bit); if (signal_map.count(bit) == 0) { gate_t gate; gate.id = signal_list.size(); - gate.type = -1; + gate.type = G(NONE); gate.in1 = -1; gate.in2 = -1; gate.in3 = -1; + gate.in4 = -1; gate.is_port = false; gate.bit = bit; signal_list.push_back(gate); @@ -85,7 +105,7 @@ static int map_signal(RTLIL::SigBit bit, char gate_type = -1, int in1 = -1, int gate_t &gate = signal_list[signal_map[bit]]; - if (gate_type >= 0) + if (gate_type != G(NONE)) gate.type = gate_type; if (in1 >= 0) gate.in1 = in1; @@ -93,6 +113,8 @@ static int map_signal(RTLIL::SigBit bit, char gate_type = -1, int in1 = -1, int gate.in2 = in2; if (in3 >= 0) gate.in3 = in3; + if (in4 >= 0) + gate.in4 = in4; return gate.id; } @@ -124,7 +146,7 @@ static void extract_cell(RTLIL::Cell *cell, bool keepff) assign_map.apply(sig_d); assign_map.apply(sig_q); - map_signal(sig_q, 'f', map_signal(sig_d)); + map_signal(sig_q, G(FF), map_signal(sig_d)); module->remove(cell); return; @@ -138,13 +160,13 @@ static void extract_cell(RTLIL::Cell *cell, bool keepff) assign_map.apply(sig_a); assign_map.apply(sig_y); - map_signal(sig_y, 'n', map_signal(sig_a)); + map_signal(sig_y, G(NOT), map_signal(sig_a)); module->remove(cell); return; } - if (cell->type == "$_AND_" || cell->type == "$_OR_" || cell->type == "$_XOR_") + if (cell->type.in("$_AND_", "$_NAND_", "$_OR_", "$_NOR", "$_XOR_", "$_XNOR_")) { RTLIL::SigSpec sig_a = cell->getPort("\\A"); RTLIL::SigSpec sig_b = cell->getPort("\\B"); @@ -158,11 +180,17 @@ static void extract_cell(RTLIL::Cell *cell, bool keepff) int mapped_b = map_signal(sig_b); if (cell->type == "$_AND_") - map_signal(sig_y, 'a', mapped_a, mapped_b); + map_signal(sig_y, G(AND), mapped_a, mapped_b); + else if (cell->type == "$_NAND_") + map_signal(sig_y, G(NAND), mapped_a, mapped_b); else if (cell->type == "$_OR_") - map_signal(sig_y, 'o', mapped_a, mapped_b); + map_signal(sig_y, G(OR), mapped_a, mapped_b); + else if (cell->type == "$_NOR_") + map_signal(sig_y, G(NOR), mapped_a, mapped_b); else if (cell->type == "$_XOR_") - map_signal(sig_y, 'x', mapped_a, mapped_b); + map_signal(sig_y, G(XOR), mapped_a, mapped_b); + else if (cell->type == "$_XNOR_") + map_signal(sig_y, G(XNOR), mapped_a, mapped_b); else log_abort(); @@ -186,7 +214,54 @@ static void extract_cell(RTLIL::Cell *cell, bool keepff) int mapped_b = map_signal(sig_b); int mapped_s = map_signal(sig_s); - map_signal(sig_y, 'm', mapped_a, mapped_b, mapped_s); + map_signal(sig_y, G(MUX), mapped_a, mapped_b, mapped_s); + + module->remove(cell); + return; + } + + if (cell->type.in("$_AOI3_", "$_OAI3_")) + { + RTLIL::SigSpec sig_a = cell->getPort("\\A"); + RTLIL::SigSpec sig_b = cell->getPort("\\B"); + RTLIL::SigSpec sig_c = cell->getPort("\\C"); + RTLIL::SigSpec sig_y = cell->getPort("\\Y"); + + assign_map.apply(sig_a); + assign_map.apply(sig_b); + assign_map.apply(sig_c); + assign_map.apply(sig_y); + + int mapped_a = map_signal(sig_a); + int mapped_b = map_signal(sig_b); + int mapped_c = map_signal(sig_c); + + map_signal(sig_y, cell->type == "$_AOI3_" ? G(AOI3) : G(OAI3), mapped_a, mapped_b, mapped_c); + + module->remove(cell); + return; + } + + if (cell->type.in("$_AOI4_", "$_OAI4_")) + { + RTLIL::SigSpec sig_a = cell->getPort("\\A"); + RTLIL::SigSpec sig_b = cell->getPort("\\B"); + RTLIL::SigSpec sig_c = cell->getPort("\\C"); + RTLIL::SigSpec sig_d = cell->getPort("\\D"); + RTLIL::SigSpec sig_y = cell->getPort("\\Y"); + + assign_map.apply(sig_a); + assign_map.apply(sig_b); + assign_map.apply(sig_c); + assign_map.apply(sig_d); + assign_map.apply(sig_y); + + int mapped_a = map_signal(sig_a); + int mapped_b = map_signal(sig_b); + int mapped_c = map_signal(sig_c); + int mapped_d = map_signal(sig_d); + + map_signal(sig_y, cell->type == "$_AOI4_" ? G(AOI4) : G(OAI4), mapped_a, mapped_b, mapped_c, mapped_d); module->remove(cell); return; @@ -244,7 +319,7 @@ static void handle_loops() // dot_f = fopen("test.dot", "w"); for (auto &g : signal_list) { - if (g.type == -1 || g.type == 'f') { + if (g.type == G(NONE) || g.type == G(FF)) { workpool.insert(g.id); } else { if (g.in1 >= 0) { @@ -259,6 +334,10 @@ static void handle_loops() edges[g.in3].insert(g.id); in_edges_count[g.id]++; } + if (g.in4 >= 0 && g.in4 != g.in3 && g.in4 != g.in2 && g.in4 != g.in1) { + edges[g.in4].insert(g.id); + in_edges_count[g.id]++; + } } } @@ -341,6 +420,8 @@ static void handle_loops() signal_list[id2].in2 = id3; if (signal_list[id2].in3 == id1) signal_list[id2].in3 = id3; + if (signal_list[id2].in4 == id1) + signal_list[id2].in4 = id3; } edges[id1].swap(edges[id3]); @@ -521,7 +602,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std int count_input = 0; fprintf(f, ".inputs"); for (auto &si : signal_list) { - if (!si.is_port || si.type >= 0) + if (!si.is_port || si.type != G(NONE)) continue; fprintf(f, " n%d", si.id); count_input++; @@ -533,7 +614,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std int count_output = 0; fprintf(f, ".outputs"); for (auto &si : signal_list) { - if (!si.is_port || si.type < 0) + if (!si.is_port || si.type == G(NONE)) continue; fprintf(f, " n%d", si.id); count_output++; @@ -553,29 +634,58 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std int count_gates = 0; for (auto &si : signal_list) { - if (si.type == 'n') { + if (si.type == G(NOT)) { fprintf(f, ".names n%d n%d\n", si.in1, si.id); fprintf(f, "0 1\n"); - } else if (si.type == 'a') { + } else if (si.type == G(AND)) { fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id); fprintf(f, "11 1\n"); - } else if (si.type == 'o') { + } else if (si.type == G(NAND)) { + fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id); + fprintf(f, "0- 1\n"); + fprintf(f, "-0 1\n"); + } else if (si.type == G(OR)) { fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id); fprintf(f, "-1 1\n"); fprintf(f, "1- 1\n"); - } else if (si.type == 'x') { + } else if (si.type == G(NOR)) { + fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id); + fprintf(f, "00 1\n"); + } else if (si.type == G(XOR)) { fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id); fprintf(f, "01 1\n"); fprintf(f, "10 1\n"); - } else if (si.type == 'm') { + } else if (si.type == G(XNOR)) { + fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id); + fprintf(f, "00 1\n"); + fprintf(f, "11 1\n"); + } else if (si.type == G(MUX)) { fprintf(f, ".names n%d n%d n%d n%d\n", si.in1, si.in2, si.in3, si.id); fprintf(f, "1-0 1\n"); fprintf(f, "-11 1\n"); - } else if (si.type == 'f') { + } else if (si.type == G(AOI3)) { + fprintf(f, ".names n%d n%d n%d n%d\n", si.in1, si.in2, si.in3, si.id); + fprintf(f, "-00 1\n"); + fprintf(f, "0-0 1\n"); + } else if (si.type == G(OAI3)) { + fprintf(f, ".names n%d n%d n%d n%d\n", si.in1, si.in2, si.in3, si.id); + fprintf(f, "00- 1\n"); + fprintf(f, "--0 1\n"); + } else if (si.type == G(AOI4)) { + fprintf(f, ".names n%d n%d n%d n%d n%d\n", si.in1, si.in2, si.in3, si.in4, si.id); + fprintf(f, "-0-0 1\n"); + fprintf(f, "-00- 1\n"); + fprintf(f, "0--0 1\n"); + fprintf(f, "0-0- 1\n"); + } else if (si.type == G(OAI4)) { + fprintf(f, ".names n%d n%d n%d n%d n%d\n", si.in1, si.in2, si.in3, si.in4, si.id); + fprintf(f, "00-- 1\n"); + fprintf(f, "--00 1\n"); + } else if (si.type == G(FF)) { fprintf(f, ".latch n%d n%d\n", si.in1, si.id); - } else if (si.type >= 0) + } else if (si.type != G(NONE)) log_abort(); - if (si.type >= 0) + if (si.type != G(NONE)) count_gates++; } @@ -599,9 +709,16 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std fprintf(f, "GATE BUF 1 Y=A; PIN * NONINV 1 999 1 0 1 0\n"); fprintf(f, "GATE INV 1 Y=!A; PIN * INV 1 999 1 0 1 0\n"); fprintf(f, "GATE AND 1 Y=A*B; PIN * NONINV 1 999 1 0 1 0\n"); + fprintf(f, "GATE NAND 1 Y=!(A*B); PIN * INV 1 999 1 0 1 0\n"); fprintf(f, "GATE OR 1 Y=A+B; PIN * NONINV 1 999 1 0 1 0\n"); + fprintf(f, "GATE NOR 1 Y=!(A+B); PIN * INV 1 999 1 0 1 0\n"); fprintf(f, "GATE XOR 1 Y=(A*!B)+(!A*B); PIN * UNKNOWN 1 999 1 0 1 0\n"); + fprintf(f, "GATE XNOR 1 Y=(A*B)+(!A*!B); PIN * UNKNOWN 1 999 1 0 1 0\n"); fprintf(f, "GATE MUX 1 Y=(A*B)+(S*B)+(!S*A); PIN * UNKNOWN 1 999 1 0 1 0\n"); + fprintf(f, "GATE AOI3 1 Y=!((A*B)+C); PIN * INV 1 999 1 0 1 0\n"); + fprintf(f, "GATE OAI3 1 Y=!((A+B)*C); PIN * INV 1 999 1 0 1 0\n"); + fprintf(f, "GATE AOI4 1 Y=!((A*B)+(C*D)); PIN * INV 1 999 1 0 1 0\n"); + fprintf(f, "GATE OAI4 1 Y=!((A+B)*(C+D)); PIN * INV 1 999 1 0 1 0\n"); fclose(f); free(p); @@ -739,7 +856,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std design->select(module, cell); continue; } - if (c->type == "\\AND" || c->type == "\\OR" || c->type == "\\XOR") { + if (c->type == "\\AND" || c->type == "\\OR" || c->type == "\\XOR" || c->type == "\\NAND" || c->type == "\\NOR" || c->type == "\\XNOR") { RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_" + c->type.substr(1) + "_"); cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)])); cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)])); @@ -756,6 +873,25 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std design->select(module, cell); continue; } + if (c->type == "\\AOI3" || c->type == "\\OAI3") { + RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_" + c->type.substr(1) + "_"); + cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)])); + cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)])); + cell->setPort("\\C", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\C").as_wire()->name)])); + cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)])); + design->select(module, cell); + continue; + } + if (c->type == "\\AOI4" || c->type == "\\OAI4") { + RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_" + c->type.substr(1) + "_"); + cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)])); + cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)])); + cell->setPort("\\C", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\C").as_wire()->name)])); + cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)])); + cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)])); + design->select(module, cell); + continue; + } if (c->type == "\\DFF") { log_assert(clk_sig.size() == 1); RTLIL::Cell *cell = module->addCell(remap_name(c->name), clk_polarity ? "$_DFF_P_" : "$_DFF_N_"); @@ -822,7 +958,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std char buffer[100]; snprintf(buffer, 100, "\\n%d", si.id); RTLIL::SigSig conn; - if (si.type >= 0) { + if (si.type != G(NONE)) { conn.first = si.bit; conn.second = RTLIL::SigSpec(module->wires_[remap_name(buffer)]); out_wires++; -- cgit v1.2.3 From 3b9157f9a605b5ae2f535c4da932891e504dc57e Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 16 Aug 2014 19:44:31 +0200 Subject: Added "test_cell -s " --- passes/tests/test_cell.cc | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) (limited to 'passes') diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index 94d5d27b1..a4b8be0c1 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -21,12 +21,13 @@ #include "kernel/yosys.h" #include +static uint32_t xorshift32_state = 123456789; + static uint32_t xorshift32(uint32_t limit) { - static uint32_t x = 123456789; - x ^= x << 13; - x ^= x >> 17; - x ^= x << 5; - return x % limit; + xorshift32_state ^= xorshift32_state << 13; + xorshift32_state ^= xorshift32_state >> 17; + xorshift32_state ^= xorshift32_state << 5; + return xorshift32_state % limit; } static void create_gold_module(RTLIL::Design *design, std::string cell_type, std::string cell_type_flags) @@ -94,6 +95,9 @@ struct TestCellPass : public Pass { log(" -n {integer}\n"); log(" create this number of cell instances and test them (default = 100).\n"); log("\n"); + log(" -s {positive_integer}\n"); + log(" use this value as rng seed value (default = unix time).\n"); + log("\n"); log(" -f {ilang_file}\n"); log(" don't generate circuits. instead load the specified ilang file.\n"); log("\n"); @@ -106,6 +110,7 @@ struct TestCellPass : public Pass { int num_iter = 100; std::string techmap_cmd = "techmap -assert"; std::string ilang_file; + xorshift32_state = 0; int argidx; for (argidx = 1; argidx < SIZE(args); argidx++) @@ -114,6 +119,10 @@ struct TestCellPass : public Pass { num_iter = atoi(args[++argidx].c_str()); continue; } + if (args[argidx] == "-s" && argidx+1 < SIZE(args)) { + xorshift32_state = atoi(args[++argidx].c_str()); + continue; + } if (args[argidx] == "-map" && argidx+1 < SIZE(args)) { techmap_cmd += " -map " + args[++argidx]; continue; @@ -126,6 +135,9 @@ struct TestCellPass : public Pass { break; } + if (xorshift32_state == 0) + xorshift32_state = time(NULL); + std::map cell_types; std::vector selected_cell_types; -- cgit v1.2.3 From 7f734ecc098a2a113ced835cefc9d4e1982f08d0 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 16 Aug 2014 23:50:36 +0200 Subject: Added module->uniquify() --- passes/cmds/splitnets.cc | 5 +---- passes/fsm/fsm_map.cc | 6 +----- 2 files changed, 2 insertions(+), 9 deletions(-) (limited to 'passes') diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc index a3daf2398..cef0a272e 100644 --- a/passes/cmds/splitnets.cc +++ b/passes/cmds/splitnets.cc @@ -46,10 +46,7 @@ struct SplitnetsWorker if (format.size() > 1) new_wire_name += format.substr(1, 1); - while (module->count_id(new_wire_name) > 0) - new_wire_name += "_"; - - RTLIL::Wire *new_wire = module->addWire(new_wire_name, width); + RTLIL::Wire *new_wire = module->addWire(module->uniquify(new_wire_name), width); new_wire->port_id = wire->port_id; new_wire->port_input = wire->port_input; new_wire->port_output = wire->port_output; diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc index 60580eb46..ab6d5671d 100644 --- a/passes/fsm/fsm_map.cc +++ b/passes/fsm/fsm_map.cc @@ -163,11 +163,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) // create state register - std::string state_wire_name = fsm_cell->parameters["\\NAME"].decode_string(); - while (module->count_id(state_wire_name) > 0) - state_wire_name += "_"; - - RTLIL::Wire *state_wire = module->addWire(state_wire_name, fsm_data.state_bits); + RTLIL::Wire *state_wire = module->addWire(module->uniquify(fsm_cell->parameters["\\NAME"].decode_string()), fsm_data.state_bits); RTLIL::Wire *next_state_wire = module->addWire(NEW_ID, fsm_data.state_bits); RTLIL::Cell *state_dff = module->addCell(NEW_ID, ""); -- cgit v1.2.3 From 410d043dd86a2ca1f6c56a3e2a4d175dc0af8739 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 17 Aug 2014 00:55:35 +0200 Subject: Renamed toposort.h to utils.h --- passes/opt/opt_const.cc | 2 +- passes/techmap/techmap.cc | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'passes') diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index 9af1e6bdf..58a7f7dfd 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -21,7 +21,7 @@ #include "kernel/register.h" #include "kernel/sigtools.h" #include "kernel/celltypes.h" -#include "kernel/toposort.h" +#include "kernel/utils.h" #include "kernel/log.h" #include #include diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 59173393c..d9d8ddd6a 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -18,7 +18,7 @@ */ #include "kernel/yosys.h" -#include "kernel/toposort.h" +#include "kernel/utils.h" #include "kernel/sigtools.h" #include "libs/sha1/sha1.h" -- cgit v1.2.3 From a3494fa9ed32d7ff2b826dfc921e3a0139158880 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 22 Aug 2014 13:58:36 +0200 Subject: Added "plugin" command --- passes/cmds/Makefile.inc | 1 + passes/cmds/plugin.cc | 117 +++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 118 insertions(+) create mode 100644 passes/cmds/plugin.cc (limited to 'passes') diff --git a/passes/cmds/Makefile.inc b/passes/cmds/Makefile.inc index d6e45f2d1..4cf61150e 100644 --- a/passes/cmds/Makefile.inc +++ b/passes/cmds/Makefile.inc @@ -21,4 +21,5 @@ OBJS += passes/cmds/connwrappers.o OBJS += passes/cmds/cover.o OBJS += passes/cmds/trace.o OBJS += passes/cmds/wreduce.o +OBJS += passes/cmds/plugin.o diff --git a/passes/cmds/plugin.cc b/passes/cmds/plugin.cc new file mode 100644 index 000000000..c73684f1b --- /dev/null +++ b/passes/cmds/plugin.cc @@ -0,0 +1,117 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2014 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" +#include + +YOSYS_NAMESPACE_BEGIN + +std::map loaded_plugins; +std::map loaded_plugin_aliases; + +void load_plugin(std::string filename, std::vector aliases) +{ + if (filename.find('/') == std::string::npos) + filename = "./" + filename; + + if (!loaded_plugins.count(filename)) { + void *hdl = dlopen(filename.c_str(), RTLD_LAZY|RTLD_LOCAL); + if (hdl == NULL) + log_cmd_error("Can't load module `%s': %s\n", filename.c_str(), dlerror()); + loaded_plugins[filename] = hdl; + Pass::init_register(); + } + + for (auto &alias : aliases) + loaded_plugin_aliases[alias] = filename; +} + +struct PluginPass : public Pass { + PluginPass() : Pass("plugin", "load and list loaded plugins") { } + virtual void help() + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" plugin [options]\n"); + log("\n"); + log("Load and list loaded plugins.\n"); + log("\n"); + log(" -i \n"); + log(" Load (install) the specified plugin.\n"); + log("\n"); + log(" -a \n"); + log(" Register the specified alias name for the loaded plugin\n"); + log("\n"); + log(" -l\n"); + log(" List loaded plugins\n"); + log("\n"); + } + virtual void execute(std::vector args, RTLIL::Design *design) + { + std::string plugin_filename; + std::vector plugin_aliases; + bool list_mode = false; + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) + { + if ((args[argidx] == "-i") && argidx+1 < args.size() && plugin_filename.empty()) { + plugin_filename = args[++argidx]; + continue; + } + if ((args[argidx] == "-a") && argidx+1 < args.size()) { + plugin_aliases.push_back(args[++argidx]); + continue; + } + if (args[argidx] == "-l") { + list_mode = true; + continue; + } + break; + } + extra_args(args, argidx, design, false); + + if (!plugin_filename.empty()) + load_plugin(plugin_filename, plugin_aliases); + + if (list_mode) + { + log("\n"); + if (loaded_plugins.empty()) + log("No plugins loaded.\n"); + else + log("Loaded plugins:\n"); + + for (auto &it : loaded_plugins) + log(" %s\n", it.first.c_str()); + + if (!loaded_plugin_aliases.empty()) { + log("\n"); + int max_alias_len = 1; + for (auto &it : loaded_plugin_aliases) + max_alias_len = std::max(max_alias_len, SIZE(it.first)); + for (auto &it : loaded_plugin_aliases) + log("Alias: %-*s %s\n", max_alias_len, it.first.c_str(), it.second.c_str()); + } + } + } +} PluginPass; + +YOSYS_NAMESPACE_END + -- cgit v1.2.3 From 98442e019d745f1d61983c071decfa3ebc1ff0cf Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 22 Aug 2014 16:09:13 +0200 Subject: Added emscripten (emcc) support to build system and some build fixes --- passes/cmds/plugin.cc | 9 ++++++++- passes/cmds/show.cc | 9 ++++++++- 2 files changed, 16 insertions(+), 2 deletions(-) (limited to 'passes') diff --git a/passes/cmds/plugin.cc b/passes/cmds/plugin.cc index c73684f1b..4e8234d16 100644 --- a/passes/cmds/plugin.cc +++ b/passes/cmds/plugin.cc @@ -18,7 +18,10 @@ */ #include "kernel/yosys.h" -#include + +#ifdef YOSYS_ENABLE_PLUGINS +# include +#endif YOSYS_NAMESPACE_BEGIN @@ -27,6 +30,7 @@ std::map loaded_plugin_aliases; void load_plugin(std::string filename, std::vector aliases) { +#ifdef YOSYS_ENABLE_PLUGINS if (filename.find('/') == std::string::npos) filename = "./" + filename; @@ -40,6 +44,9 @@ void load_plugin(std::string filename, std::vector aliases) for (auto &alias : aliases) loaded_plugin_aliases[alias] = filename; +#else + log_error("This version of yosys is built without plugin support.\n"); +#endif } struct PluginPass : public Pass { diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index 4f6b811bc..fc6e972ee 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -22,7 +22,10 @@ #include "kernel/log.h" #include #include -#include + +#ifdef YOSYS_ENABLE_READLINE +# include +#endif using RTLIL::id2cstr; @@ -770,6 +773,7 @@ struct ShowPass : public Pass { } if (flag_pause) { + #ifdef YOSYS_ENABLE_READLINE char *input = NULL; while ((input = readline("Press ENTER to continue (or type 'shell' to open a shell)> ")) != NULL) { if (input[strspn(input, " \t\r\n")] == 0) @@ -780,6 +784,9 @@ struct ShowPass : public Pass { break; } } + #else + log_cmd_error("This version of yosys is built without readline support => 'show -pause' is not available.\n"); + #endif } log_pop(); -- cgit v1.2.3 From fff12c719fc2d61e36e85f27080a4043078b0929 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 22 Aug 2014 17:20:28 +0200 Subject: Added "stat -width" --- passes/cmds/stat.cc | 41 +++++++++++++++++++++++++++++++++++++---- 1 file changed, 37 insertions(+), 4 deletions(-) (limited to 'passes') diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc index fabc80ec0..dea24227f 100644 --- a/passes/cmds/stat.cc +++ b/passes/cmds/stat.cc @@ -63,7 +63,7 @@ namespace #undef X } - statdata_t(RTLIL::Design *design, RTLIL::Module *mod) + statdata_t(RTLIL::Design *design, RTLIL::Module *mod, bool width_mode) { #define X(_name) _name = 0; STAT_INT_MEMBERS @@ -90,11 +90,35 @@ namespace num_memory_bits += it.second->width * it.second->size; } - for (auto &it : mod->cells_) { + for (auto &it : mod->cells_) + { if (!design->selected(mod, it.second)) continue; + + RTLIL::IdString cell_type = it.second->type; + + if (width_mode) + { + if (cell_type.in("$not", "$pos", "$bu0", "$neg", + "$logic_not", "$logic_and", "$logic_or", + "$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool", + "$lut", "$and", "$or", "$xor", "$xnor", + "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", + "$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt", + "$add", "$sub", "$mul", "$div", "$mod", "$pow")) { + int width_a = it.second->hasPort("\\A") ? SIZE(it.second->getPort("\\A")) : 0; + int width_b = it.second->hasPort("\\B") ? SIZE(it.second->getPort("\\B")) : 0; + int width_y = it.second->hasPort("\\Y") ? SIZE(it.second->getPort("\\Y")) : 0; + cell_type = stringf("%s_%d", cell_type.c_str(), std::max({width_a, width_b, width_y})); + } + else if (cell_type.in("$mux", "$pmux")) + cell_type = stringf("%s_%d", cell_type.c_str(), SIZE(it.second->getPort("\\Y"))); + else if (cell_type.in("$sr", "$dff", "$dffsr", "$adff", "$dlatch", "$dlatchsr")) + cell_type = stringf("%s_%d", cell_type.c_str(), SIZE(it.second->getPort("\\Q"))); + } + num_cells++; - num_cells_by_type[it.second->type]++; + num_cells_by_type[cell_type]++; } for (auto &it : mod->processes) { @@ -154,17 +178,26 @@ struct StatPass : public Pass { log(" selected and a module has the 'top' attribute set, this module is used\n"); log(" default value for this option.\n"); log("\n"); + log(" -width\n"); + log(" annotate internal cell types with their word width.\n"); + log(" e.g. $add_8 for an 8 bit wide $add cell.\n"); + log("\n"); } virtual void execute(std::vector args, RTLIL::Design *design) { log_header("Printing statistics.\n"); + bool width_mode = false; RTLIL::Module *top_mod = NULL; std::map mod_stat; size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { + if (args[argidx] == "-width") { + width_mode = true; + continue; + } if (args[argidx] == "-top" && argidx+1 < args.size()) { if (design->modules_.count(RTLIL::escape_id(args[argidx+1])) == 0) log_cmd_error("Can't find module %s.\n", args[argidx+1].c_str()); @@ -184,7 +217,7 @@ struct StatPass : public Pass { if (it.second->get_bool_attribute("\\top")) top_mod = it.second; - statdata_t data(design, it.second); + statdata_t data(design, it.second, width_mode); mod_stat[it.first] = data; log("\n"); -- cgit v1.2.3 From 5dce303a2a2c27d50e99856b6f33467798e13020 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 23 Aug 2014 13:54:21 +0200 Subject: Changed backend-api from FILE to std::ostream --- passes/techmap/extract.cc | 9 ++- passes/tests/test_autotb.cc | 186 ++++++++++++++++++++++---------------------- 2 files changed, 98 insertions(+), 97 deletions(-) (limited to 'passes') diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index ebf4d77fc..eaa0f9fa3 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -747,11 +747,12 @@ struct ExtractPass : public Pass { } } - FILE *f = fopen(mine_outfile.c_str(), "wt"); - if (f == NULL) + std::ofstream f; + f.open(mine_outfile.c_str(), std::ofstream::trunc); + if (f.fail()) log_error("Can't open output file `%s'.\n", mine_outfile.c_str()); - Backend::backend_call(map, f, mine_outfile, "ilang"); - fclose(f); + Backend::backend_call(map, &f, mine_outfile, "ilang"); + f.close(); } delete map; diff --git a/passes/tests/test_autotb.cc b/passes/tests/test_autotb.cc index d26002277..eed0f75f9 100644 --- a/passes/tests/test_autotb.cc +++ b/passes/tests/test_autotb.cc @@ -70,26 +70,26 @@ static std::string idy(std::string str1, std::string str2 = std::string(), std:: return id(str1); } -static void autotest(FILE *f, RTLIL::Design *design, int num_iter) +static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter) { - fprintf(f, "module testbench;\n\n"); + f << stringf("module testbench;\n\n"); - fprintf(f, "integer i;\n\n"); + f << stringf("integer i;\n\n"); - fprintf(f, "reg [31:0] xorshift128_x = 123456789;\n"); - fprintf(f, "reg [31:0] xorshift128_y = 362436069;\n"); - fprintf(f, "reg [31:0] xorshift128_z = 521288629;\n"); - fprintf(f, "reg [31:0] xorshift128_w = %u; // <-- seed value\n", int(time(NULL))); - fprintf(f, "reg [31:0] xorshift128_t;\n\n"); - fprintf(f, "task xorshift128;\n"); - fprintf(f, "begin\n"); - fprintf(f, "\txorshift128_t = xorshift128_x ^ (xorshift128_x << 11);\n"); - fprintf(f, "\txorshift128_x = xorshift128_y;\n"); - fprintf(f, "\txorshift128_y = xorshift128_z;\n"); - fprintf(f, "\txorshift128_z = xorshift128_w;\n"); - fprintf(f, "\txorshift128_w = xorshift128_w ^ (xorshift128_w >> 19) ^ xorshift128_t ^ (xorshift128_t >> 8);\n"); - fprintf(f, "end\n"); - fprintf(f, "endtask\n\n"); + f << stringf("reg [31:0] xorshift128_x = 123456789;\n"); + f << stringf("reg [31:0] xorshift128_y = 362436069;\n"); + f << stringf("reg [31:0] xorshift128_z = 521288629;\n"); + f << stringf("reg [31:0] xorshift128_w = %u; // <-- seed value\n", int(time(NULL))); + f << stringf("reg [31:0] xorshift128_t;\n\n"); + f << stringf("task xorshift128;\n"); + f << stringf("begin\n"); + f << stringf("\txorshift128_t = xorshift128_x ^ (xorshift128_x << 11);\n"); + f << stringf("\txorshift128_x = xorshift128_y;\n"); + f << stringf("\txorshift128_y = xorshift128_z;\n"); + f << stringf("\txorshift128_z = xorshift128_w;\n"); + f << stringf("\txorshift128_w = xorshift128_w ^ (xorshift128_w >> 19) ^ xorshift128_t ^ (xorshift128_t >> 8);\n"); + f << stringf("end\n"); + f << stringf("endtask\n\n"); for (auto it = design->modules_.begin(); it != design->modules_.end(); it++) { @@ -110,7 +110,7 @@ static void autotest(FILE *f, RTLIL::Design *design, int num_iter) if (wire->port_output) { count_ports++; signal_out[idy("sig", mod->name.str(), wire->name.str())] = wire->width; - fprintf(f, "wire [%d:0] %s;\n", wire->width-1, idy("sig", mod->name.str(), wire->name.str()).c_str()); + f << stringf("wire [%d:0] %s;\n", wire->width-1, idy("sig", mod->name.str(), wire->name.str()).c_str()); } else if (wire->port_input) { count_ports++; bool is_clksignal = wire->get_bool_attribute("\\gentb_clock"); @@ -130,85 +130,85 @@ static void autotest(FILE *f, RTLIL::Design *design, int num_iter) if (wire->attributes.count("\\gentb_constant") != 0) signal_const[idy("sig", mod->name.str(), wire->name.str())] = wire->attributes["\\gentb_constant"].as_string(); } - fprintf(f, "reg [%d:0] %s;\n", wire->width-1, idy("sig", mod->name.str(), wire->name.str()).c_str()); + f << stringf("reg [%d:0] %s;\n", wire->width-1, idy("sig", mod->name.str(), wire->name.str()).c_str()); } } - fprintf(f, "%s %s(\n", id(mod->name.str()).c_str(), idy("uut", mod->name.str()).c_str()); + f << stringf("%s %s(\n", id(mod->name.str()).c_str(), idy("uut", mod->name.str()).c_str()); for (auto it2 = mod->wires_.begin(); it2 != mod->wires_.end(); it2++) { RTLIL::Wire *wire = it2->second; if (wire->port_output || wire->port_input) - fprintf(f, "\t.%s(%s)%s\n", id(wire->name.str()).c_str(), + f << stringf("\t.%s(%s)%s\n", id(wire->name.str()).c_str(), idy("sig", mod->name.str(), wire->name.str()).c_str(), --count_ports ? "," : ""); } - fprintf(f, ");\n\n"); + f << stringf(");\n\n"); - fprintf(f, "task %s;\n", idy(mod->name.str(), "reset").c_str()); - fprintf(f, "begin\n"); + f << stringf("task %s;\n", idy(mod->name.str(), "reset").c_str()); + f << stringf("begin\n"); int delay_counter = 0; for (auto it = signal_in.begin(); it != signal_in.end(); it++) - fprintf(f, "\t%s <= #%d 0;\n", it->first.c_str(), ++delay_counter*2); + f << stringf("\t%s <= #%d 0;\n", it->first.c_str(), ++delay_counter*2); for (auto it = signal_clk.begin(); it != signal_clk.end(); it++) - fprintf(f, "\t%s <= #%d 0;\n", it->first.c_str(), ++delay_counter*2); + f << stringf("\t%s <= #%d 0;\n", it->first.c_str(), ++delay_counter*2); for (auto it = signal_clk.begin(); it != signal_clk.end(); it++) { - fprintf(f, "\t#100; %s <= 1;\n", it->first.c_str()); - fprintf(f, "\t#100; %s <= 0;\n", it->first.c_str()); + f << stringf("\t#100; %s <= 1;\n", it->first.c_str()); + f << stringf("\t#100; %s <= 0;\n", it->first.c_str()); } delay_counter = 0; for (auto it = signal_in.begin(); it != signal_in.end(); it++) - fprintf(f, "\t%s <= #%d ~0;\n", it->first.c_str(), ++delay_counter*2); + f << stringf("\t%s <= #%d ~0;\n", it->first.c_str(), ++delay_counter*2); for (auto it = signal_clk.begin(); it != signal_clk.end(); it++) { - fprintf(f, "\t#100; %s <= 1;\n", it->first.c_str()); - fprintf(f, "\t#100; %s <= 0;\n", it->first.c_str()); + f << stringf("\t#100; %s <= 1;\n", it->first.c_str()); + f << stringf("\t#100; %s <= 0;\n", it->first.c_str()); } delay_counter = 0; for (auto it = signal_in.begin(); it != signal_in.end(); it++) { if (signal_const.count(it->first) == 0) continue; - fprintf(f, "\t%s <= #%d 'b%s;\n", it->first.c_str(), ++delay_counter*2, signal_const[it->first].c_str()); + f << stringf("\t%s <= #%d 'b%s;\n", it->first.c_str(), ++delay_counter*2, signal_const[it->first].c_str()); } - fprintf(f, "end\n"); - fprintf(f, "endtask\n\n"); + f << stringf("end\n"); + f << stringf("endtask\n\n"); - fprintf(f, "task %s;\n", idy(mod->name.str(), "update_data").c_str()); - fprintf(f, "begin\n"); + f << stringf("task %s;\n", idy(mod->name.str(), "update_data").c_str()); + f << stringf("begin\n"); delay_counter = 0; for (auto it = signal_in.begin(); it != signal_in.end(); it++) { if (signal_const.count(it->first) > 0) continue; - fprintf(f, "\txorshift128;\n"); - fprintf(f, "\t%s <= #%d { xorshift128_x, xorshift128_y, xorshift128_z, xorshift128_w };\n", it->first.c_str(), ++delay_counter*2); + f << stringf("\txorshift128;\n"); + f << stringf("\t%s <= #%d { xorshift128_x, xorshift128_y, xorshift128_z, xorshift128_w };\n", it->first.c_str(), ++delay_counter*2); } - fprintf(f, "end\n"); - fprintf(f, "endtask\n\n"); + f << stringf("end\n"); + f << stringf("endtask\n\n"); - fprintf(f, "task %s;\n", idy(mod->name.str(), "update_clock").c_str()); - fprintf(f, "begin\n"); + f << stringf("task %s;\n", idy(mod->name.str(), "update_clock").c_str()); + f << stringf("begin\n"); if (signal_clk.size()) { - fprintf(f, "\txorshift128;\n"); - fprintf(f, "\t{"); + f << stringf("\txorshift128;\n"); + f << stringf("\t{"); int total_clock_bits = 0; for (auto it = signal_clk.begin(); it != signal_clk.end(); it++) { - fprintf(f, "%s %s", it == signal_clk.begin() ? "" : ",", it->first.c_str()); + f << stringf("%s %s", it == signal_clk.begin() ? "" : ",", it->first.c_str()); total_clock_bits += it->second; } - fprintf(f, " } = {"); + f << stringf(" } = {"); for (auto it = signal_clk.begin(); it != signal_clk.end(); it++) - fprintf(f, "%s %s", it == signal_clk.begin() ? "" : ",", it->first.c_str()); - fprintf(f, " } ^ (%d'b1 << (xorshift128_w %% %d));\n", total_clock_bits, total_clock_bits); + f << stringf("%s %s", it == signal_clk.begin() ? "" : ",", it->first.c_str()); + f << stringf(" } ^ (%d'b1 << (xorshift128_w %% %d));\n", total_clock_bits, total_clock_bits); } - fprintf(f, "end\n"); - fprintf(f, "endtask\n\n"); + f << stringf("end\n"); + f << stringf("endtask\n\n"); char shorthand = 'A'; std::vector header1; std::string header2 = ""; - fprintf(f, "task %s;\n", idy(mod->name.str(), "print_status").c_str()); - fprintf(f, "begin\n"); - fprintf(f, "\t$display(\"#OUT# %%b %%b %%b %%t %%d\", {"); + f << stringf("task %s;\n", idy(mod->name.str(), "print_status").c_str()); + f << stringf("begin\n"); + f << stringf("\t$display(\"#OUT# %%b %%b %%b %%t %%d\", {"); if (signal_in.size()) for (auto it = signal_in.begin(); it != signal_in.end(); it++) { - fprintf(f, "%s %s", it == signal_in.begin() ? "" : ",", it->first.c_str()); + f << stringf("%s %s", it == signal_in.begin() ? "" : ",", it->first.c_str()); int len = it->second; if (len > 1) header2 += "/", len--; @@ -220,14 +220,14 @@ static void autotest(FILE *f, RTLIL::Design *design, int num_iter) header1.back()[0] = shorthand++; } else { - fprintf(f, " 1'bx"); + f << stringf(" 1'bx"); header2 += "#"; } - fprintf(f, " }, {"); + f << stringf(" }, {"); header2 += " "; if (signal_clk.size()) { for (auto it = signal_clk.begin(); it != signal_clk.end(); it++) { - fprintf(f, "%s %s", it == signal_clk.begin() ? "" : ",", it->first.c_str()); + f << stringf("%s %s", it == signal_clk.begin() ? "" : ",", it->first.c_str()); int len = it->second; if (len > 1) header2 += "/", len--; @@ -239,14 +239,14 @@ static void autotest(FILE *f, RTLIL::Design *design, int num_iter) header1.back()[0] = shorthand++; } } else { - fprintf(f, " 1'bx"); + f << stringf(" 1'bx"); header2 += "#"; } - fprintf(f, " }, {"); + f << stringf(" }, {"); header2 += " "; if (signal_out.size()) { for (auto it = signal_out.begin(); it != signal_out.end(); it++) { - fprintf(f, "%s %s", it == signal_out.begin() ? "" : ",", it->first.c_str()); + f << stringf("%s %s", it == signal_out.begin() ? "" : ",", it->first.c_str()); int len = it->second; if (len > 1) header2 += "/", len--; @@ -258,47 +258,47 @@ static void autotest(FILE *f, RTLIL::Design *design, int num_iter) header1.back()[0] = shorthand++; } } else { - fprintf(f, " 1'bx"); + f << stringf(" 1'bx"); header2 += "#"; } - fprintf(f, " }, $time, i);\n"); - fprintf(f, "end\n"); - fprintf(f, "endtask\n\n"); + f << stringf(" }, $time, i);\n"); + f << stringf("end\n"); + f << stringf("endtask\n\n"); - fprintf(f, "task %s;\n", idy(mod->name.str(), "print_header").c_str()); - fprintf(f, "begin\n"); - fprintf(f, "\t$display(\"#OUT#\");\n"); + f << stringf("task %s;\n", idy(mod->name.str(), "print_header").c_str()); + f << stringf("begin\n"); + f << stringf("\t$display(\"#OUT#\");\n"); for (auto &hdr : header1) - fprintf(f, "\t$display(\"#OUT# %s\");\n", hdr.c_str()); - fprintf(f, "\t$display(\"#OUT#\");\n"); - fprintf(f, "\t$display(\"#OUT# %s\");\n", header2.c_str()); - fprintf(f, "end\n"); - fprintf(f, "endtask\n\n"); + f << stringf("\t$display(\"#OUT# %s\");\n", hdr.c_str()); + f << stringf("\t$display(\"#OUT#\");\n"); + f << stringf("\t$display(\"#OUT# %s\");\n", header2.c_str()); + f << stringf("end\n"); + f << stringf("endtask\n\n"); - fprintf(f, "task %s;\n", idy(mod->name.str(), "test").c_str()); - fprintf(f, "begin\n"); - fprintf(f, "\t$display(\"#OUT#\\n#OUT# ==== %s ====\");\n", idy(mod->name.str()).c_str()); - fprintf(f, "\t%s;\n", idy(mod->name.str(), "reset").c_str()); - fprintf(f, "\tfor (i=0; i<%d; i=i+1) begin\n", num_iter); - fprintf(f, "\t\tif (i %% 20 == 0) %s;\n", idy(mod->name.str(), "print_header").c_str()); - fprintf(f, "\t\t#100; %s;\n", idy(mod->name.str(), "update_data").c_str()); - fprintf(f, "\t\t#100; %s;\n", idy(mod->name.str(), "update_clock").c_str()); - fprintf(f, "\t\t#100; %s;\n", idy(mod->name.str(), "print_status").c_str()); - fprintf(f, "\tend\n"); - fprintf(f, "end\n"); - fprintf(f, "endtask\n\n"); + f << stringf("task %s;\n", idy(mod->name.str(), "test").c_str()); + f << stringf("begin\n"); + f << stringf("\t$display(\"#OUT#\\n#OUT# ==== %s ====\");\n", idy(mod->name.str()).c_str()); + f << stringf("\t%s;\n", idy(mod->name.str(), "reset").c_str()); + f << stringf("\tfor (i=0; i<%d; i=i+1) begin\n", num_iter); + f << stringf("\t\tif (i %% 20 == 0) %s;\n", idy(mod->name.str(), "print_header").c_str()); + f << stringf("\t\t#100; %s;\n", idy(mod->name.str(), "update_data").c_str()); + f << stringf("\t\t#100; %s;\n", idy(mod->name.str(), "update_clock").c_str()); + f << stringf("\t\t#100; %s;\n", idy(mod->name.str(), "print_status").c_str()); + f << stringf("\tend\n"); + f << stringf("end\n"); + f << stringf("endtask\n\n"); } - fprintf(f, "initial begin\n"); - fprintf(f, "\t// $dumpfile(\"testbench.vcd\");\n"); - fprintf(f, "\t// $dumpvars(0, testbench);\n"); + f << stringf("initial begin\n"); + f << stringf("\t// $dumpfile(\"testbench.vcd\");\n"); + f << stringf("\t// $dumpvars(0, testbench);\n"); for (auto it = design->modules_.begin(); it != design->modules_.end(); it++) if (!it->second->get_bool_attribute("\\gentb_skip")) - fprintf(f, "\t%s;\n", idy(it->first.str(), "test").c_str()); - fprintf(f, "\t$finish;\n"); - fprintf(f, "end\n\n"); + f << stringf("\t%s;\n", idy(it->first.str(), "test").c_str()); + f << stringf("\t$finish;\n"); + f << stringf("end\n\n"); - fprintf(f, "endmodule\n"); + f << stringf("endmodule\n"); } struct TestAutotbBackend : public Backend { @@ -328,7 +328,7 @@ struct TestAutotbBackend : public Backend { log(" number of iterations the test bench shuld run (default = 1000)\n"); log("\n"); } - virtual void execute(FILE *&f, std::string filename, std::vector args, RTLIL::Design *design) + virtual void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) { int num_iter = 1000; @@ -345,7 +345,7 @@ struct TestAutotbBackend : public Backend { } extra_args(f, filename, args, argidx); - autotest(f, design, num_iter); + autotest(*f, design, num_iter); } } TestAutotbBackend; -- cgit v1.2.3 From 19cff41eb4261b20374058f16807a229af46f304 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 23 Aug 2014 15:03:55 +0200 Subject: Changed frontend-api from FILE to std::istream --- passes/cmds/show.cc | 8 ++++---- passes/cmds/write_file.cc | 4 ++-- passes/techmap/dfflibmap.cc | 7 ++++--- passes/techmap/extract.cc | 9 +++++---- passes/techmap/libparse.cc | 40 ++++++++++++++++++++++++---------------- passes/techmap/libparse.h | 4 ++-- passes/techmap/techmap.cc | 13 ++++++------- 7 files changed, 47 insertions(+), 38 deletions(-) (limited to 'passes') diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index fc6e972ee..3468eae78 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -720,13 +720,13 @@ struct ShowPass : public Pass { } for (auto filename : libfiles) { - FILE *f = fopen(filename.c_str(), "rt"); - if (f == NULL) + std::ifstream f; + f.open(filename.c_str()); + if (f.fail()) log_error("Can't open lib file `%s'.\n", filename.c_str()); RTLIL::Design *lib = new RTLIL::Design; - Frontend::frontend_call(lib, f, filename, (filename.size() > 3 && filename.substr(filename.size()-3) == ".il") ? "ilang" : "verilog"); + Frontend::frontend_call(lib, &f, filename, (filename.size() > 3 && filename.substr(filename.size()-3) == ".il") ? "ilang" : "verilog"); libs.push_back(lib); - fclose(f); } if (libs.size() > 0) diff --git a/passes/cmds/write_file.cc b/passes/cmds/write_file.cc index a7cd7b438..813e215ba 100644 --- a/passes/cmds/write_file.cc +++ b/passes/cmds/write_file.cc @@ -41,7 +41,7 @@ struct WriteFileFrontend : public Frontend { log(" EOT\n"); log("\n"); } - virtual void execute(FILE *&f, std::string filename, std::vector args, RTLIL::Design*) + virtual void execute(std::istream *&f, std::string filename, std::vector args, RTLIL::Design*) { bool append_mode = false; std::string output_filename; @@ -67,7 +67,7 @@ struct WriteFileFrontend : public Frontend { char buffer[64 * 1024]; size_t bytes; - while (0 < (bytes = fread(buffer, 1, sizeof(buffer), f))) + while (0 < (bytes = f->readsome(buffer, sizeof(buffer)))) fwrite(buffer, bytes, 1, of); fclose(of); diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc index 6ce771ac4..7e39040c4 100644 --- a/passes/techmap/dfflibmap.cc +++ b/passes/techmap/dfflibmap.cc @@ -463,11 +463,12 @@ struct DfflibmapPass : public Pass { if (liberty_file.empty()) log_cmd_error("Missing `-liberty liberty_file' option!\n"); - FILE *f = fopen(liberty_file.c_str(), "r"); - if (f == NULL) + std::ifstream f; + f.open(liberty_file.c_str()); + if (f.fail()) log_cmd_error("Can't open liberty file `%s': %s\n", liberty_file.c_str(), strerror(errno)); LibertyParser libparser(f); - fclose(f); + f.close(); find_cell(libparser.ast, "$_DFF_N_", false, false, false, false); find_cell(libparser.ast, "$_DFF_P_", true, false, false, false); diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index eaa0f9fa3..221e9e49d 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -609,13 +609,14 @@ struct ExtractPass : public Pass { } else { - FILE *f = fopen(filename.c_str(), "rt"); - if (f == NULL) { + std::ifstream f; + f.open(filename.c_str()); + if (f.fail()) { delete map; log_cmd_error("Can't open map file `%s'.\n", filename.c_str()); } - Frontend::frontend_call(map, f, filename, (filename.size() > 3 && filename.substr(filename.size()-3) == ".il") ? "ilang" : "verilog"); - fclose(f); + Frontend::frontend_call(map, &f, filename, (filename.size() > 3 && filename.substr(filename.size()-3) == ".il") ? "ilang" : "verilog"); + f.close(); if (filename.size() <= 3 || filename.substr(filename.size()-3) != ".il") { Pass::call(map, "proc"); diff --git a/passes/techmap/libparse.cc b/passes/techmap/libparse.cc index 2ff551537..612fa1117 100644 --- a/passes/techmap/libparse.cc +++ b/passes/techmap/libparse.cc @@ -21,6 +21,10 @@ #include #include +#include +#include +#include + #ifndef FILTERLIB #include "kernel/log.h" #endif @@ -85,19 +89,19 @@ int LibertyParser::lexer(std::string &str) int c; do { - c = fgetc(f); + c = f.get(); } while (c == ' ' || c == '\t' || c == '\r'); if (('a' <= c && c <= 'z') || ('A' <= c && c <= 'Z') || ('0' <= c && c <= '9') || c == '_' || c == '-' || c == '+' || c == '.') { str = c; while (1) { - c = fgetc(f); + c = f.get(); if (('a' <= c && c <= 'z') || ('A' <= c && c <= 'Z') || ('0' <= c && c <= '9') || c == '_' || c == '-' || c == '+' || c == '.') str += c; else break; } - ungetc(c, f); + f.unget(); // fprintf(stderr, "LEX: identifier >>%s<<\n", str.c_str()); return 'v'; } @@ -105,7 +109,7 @@ int LibertyParser::lexer(std::string &str) if (c == '"') { str = c; while (1) { - c = fgetc(f); + c = f.get(); if (c == '\n') line++; str += c; @@ -117,34 +121,34 @@ int LibertyParser::lexer(std::string &str) } if (c == '/') { - c = fgetc(f); + c = f.get(); if (c == '*') { int last_c = 0; while (c > 0 && (last_c != '*' || c != '/')) { last_c = c; - c = fgetc(f); + c = f.get(); if (c == '\n') line++; } return lexer(str); } else if (c == '/') { while (c > 0 && c != '\n') - c = fgetc(f); + c = f.get(); line++; return lexer(str); } - ungetc(c, f); + f.unget(); // fprintf(stderr, "LEX: char >>/<<\n"); return '/'; } if (c == '\\') { - c = fgetc(f); + c = f.get(); if (c == '\r') - c = fgetc(f); + c = f.get(); if (c == '\n') return lexer(str); - ungetc(c, f); + f.unget(); return '\\'; } @@ -608,16 +612,20 @@ int main(int argc, char **argv) } } - FILE *f = stdin; + std::istream *f = &std::cin; + if (argc == 3) { - f = fopen(argv[2], "r"); - if (f == NULL) { + std::ifstream *ff = new std::ifstream; + ff->open(argv[2]); + if (ff->fail()) { + delete ff; fprintf(stderr, "Can't open liberty file `%s'.\n", argv[2]); usage(); } + f = ff; } - LibertyParser parser(f); + LibertyParser parser(*f); if (parser.ast) { if (flag_verilogsim) gen_verilogsim(parser.ast); @@ -626,7 +634,7 @@ int main(int argc, char **argv) } if (argc == 3) - fclose(f); + delete f; return 0; } diff --git a/passes/techmap/libparse.h b/passes/techmap/libparse.h index eff268bbb..247487424 100644 --- a/passes/techmap/libparse.h +++ b/passes/techmap/libparse.h @@ -41,10 +41,10 @@ namespace PASS_DFFLIBMAP struct LibertyParser { - FILE *f; + std::istream &f; int line; LibertyAst *ast; - LibertyParser(FILE *f) : f(f), line(1), ast(parse()) {} + LibertyParser(std::istream &f) : f(f), line(1), ast(parse()) {} ~LibertyParser() { if (ast) delete ast; } int lexer(std::string &str); LibertyAst *parse(); diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index d9d8ddd6a..beacdfa6f 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -869,9 +869,8 @@ struct TechmapPass : public Pass { RTLIL::Design *map = new RTLIL::Design; if (map_files.empty()) { - FILE *f = fmemopen(stdcells_code, strlen(stdcells_code), "rt"); - Frontend::frontend_call(map, f, "", verilog_frontend); - fclose(f); + std::istringstream f(stdcells_code); + Frontend::frontend_call(map, &f, "", verilog_frontend); } else for (auto &fn : map_files) if (fn.substr(0, 1) == "%") { @@ -883,11 +882,11 @@ struct TechmapPass : public Pass { if (!map->has(mod->name)) map->add(mod->clone()); } else { - FILE *f = fopen(fn.c_str(), "rt"); - if (f == NULL) + std::ifstream f; + f.open(fn.c_str()); + if (f.fail()) log_cmd_error("Can't open map file `%s'\n", fn.c_str()); - Frontend::frontend_call(map, f, fn, (fn.size() > 3 && fn.substr(fn.size()-3) == ".il") ? "ilang" : verilog_frontend); - fclose(f); + Frontend::frontend_call(map, &f, fn, (fn.size() > 3 && fn.substr(fn.size()-3) == ".il") ? "ilang" : verilog_frontend); } std::map modules_new; -- cgit v1.2.3 From c642dd0b3eb1390b6c1acd39c1f19797da27b190 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 23 Aug 2014 15:32:00 +0200 Subject: Only call proc_share_dirname() in techmap when necessary --- passes/techmap/techmap.cc | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'passes') diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index beacdfa6f..660f1b388 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -829,14 +829,13 @@ struct TechmapPass : public Pass { int max_iter = -1; size_t argidx; - std::string proc_share_path = proc_share_dirname(); for (argidx = 1; argidx < args.size(); argidx++) { if (args[argidx] == "-map" && argidx+1 < args.size()) { map_files.push_back(args[++argidx]); continue; } if (args[argidx] == "-share_map" && argidx+1 < args.size()) { - map_files.push_back(proc_share_path + args[++argidx]); + map_files.push_back(proc_share_dirname() + args[++argidx]); continue; } if (args[argidx] == "-max_iter" && argidx+1 < args.size()) { -- cgit v1.2.3 From 9c5a63c52c24f0570557b4bf7340b41666cf44b6 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 24 Aug 2014 13:27:40 +0200 Subject: azonenberg: Make dump_vcd save model when temporal induction fails due to step limit --- passes/sat/sat.cc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'passes') diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index c6da4bb42..08ae9e929 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -1320,6 +1320,8 @@ struct SatPass : public Pass { } log("\nReached maximum number of time steps -> proof failed.\n"); + if(!vcd_file_name.empty()) + inductstep.dump_model_to_vcd(vcd_file_name); print_proof_failed(); tip_failed: -- cgit v1.2.3 From 641501203c534b00a0ae3ad6844f8759d6bc8549 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 24 Aug 2014 15:14:45 +0200 Subject: Added some additional log messages to opt_const --- passes/opt/opt_const.cc | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index 58a7f7dfd..c4f4bba3f 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -79,7 +79,7 @@ static void replace_cell(SigMap &assign_map, RTLIL::Module *module, RTLIL::Cell log("Replacing %s cell `%s' (%s) in module `%s' with constant driver `%s = %s'.\n", cell->type.c_str(), cell->name.c_str(), info.c_str(), module->name.c_str(), log_signal(Y), log_signal(out_val)); - // ILANG_BACKEND::dump_cell(stderr, "--> ", cell); + // log_cell(cell); assign_map.add(Y, out_val); module->connect(Y, out_val); module->remove(cell); @@ -380,6 +380,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if ((cell->type == "$_MUX_" || cell->type == "$mux") && invert_map.count(assign_map(cell->getPort("\\S"))) != 0) { cover_list("opt.opt_const.invert.muxsel", "$_MUX_", "$mux", cell->type.str()); + log("Optimizing away select inverter for %s cell `%s' in module `%s'.\n", log_id(cell->type), log_id(cell), log_id(module)); RTLIL::SigSpec tmp = cell->getPort("\\A"); cell->setPort("\\A", cell->getPort("\\B")); cell->setPort("\\B", tmp); @@ -545,10 +546,13 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo ACTION_DO("\\Y", cell->getPort("\\A")); } else { cover_list("opt.opt_const.eqneq.isnot", "$eq", "$ne", cell->type.str()); + log("Replacing %s cell `%s' in module `%s' with inverter.\n", log_id(cell->type), log_id(cell), log_id(module)); cell->type = "$not"; cell->parameters.erase("\\B_WIDTH"); cell->parameters.erase("\\B_SIGNED"); cell->unsetPort("\\B"); + OPT_DID_SOMETHING = true; + did_something = true; } goto next_cell; } @@ -638,6 +642,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->getPort("\\A") == RTLIL::SigSpec(1, 1) && cell->getPort("\\B") == RTLIL::SigSpec(0, 1)) { cover_list("opt.opt_const.mux_invert", "$mux", "$_MUX_", cell->type.str()); + log("Replacing %s cell `%s' in module `%s' with inverter.\n", log_id(cell->type), log_id(cell), log_id(module)); cell->setPort("\\A", cell->getPort("\\S")); cell->unsetPort("\\B"); cell->unsetPort("\\S"); @@ -656,6 +661,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->getPort("\\A") == RTLIL::SigSpec(0, 1)) { cover_list("opt.opt_const.mux_and", "$mux", "$_MUX_", cell->type.str()); + log("Replacing %s cell `%s' in module `%s' with and-gate.\n", log_id(cell->type), log_id(cell), log_id(module)); cell->setPort("\\A", cell->getPort("\\S")); cell->unsetPort("\\S"); if (cell->type == "$mux") { @@ -675,6 +681,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->getPort("\\B") == RTLIL::SigSpec(1, 1)) { cover_list("opt.opt_const.mux_or", "$mux", "$_MUX_", cell->type.str()); + log("Replacing %s cell `%s' in module `%s' with or-gate.\n", log_id(cell->type), log_id(cell), log_id(module)); cell->setPort("\\B", cell->getPort("\\S")); cell->unsetPort("\\S"); if (cell->type == "$mux") { @@ -727,6 +734,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo } if (cell->getPort("\\S").size() != new_s.size()) { cover_list("opt.opt_const.mux_reduce", "$mux", "$pmux", cell->type.str()); + log("Optimized away %d select inputs of %s cell `%s' in module `%s'.\n", + SIZE(cell->getPort("\\S")) - SIZE(new_s), log_id(cell->type), log_id(cell), log_id(module)); cell->setPort("\\A", new_a); cell->setPort("\\B", new_b); cell->setPort("\\S", new_s); -- cgit v1.2.3 From 7bbbe3580d249d8abab55ab4ef2703bf3dc51a3c Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 24 Aug 2014 17:08:07 +0200 Subject: Optimize shift ops with constant rhs in opt_const --- passes/opt/opt_const.cc | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) (limited to 'passes') diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index c4f4bba3f..a602cf5fd 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -558,6 +558,41 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo } } + if (cell->type.in("$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx") && assign_map(cell->getPort("\\B")).is_fully_const()) + { + bool sign_ext = cell->type == "$sshr" && cell->getParam("\\A_SIGNED").as_bool(); + int shift_bits = assign_map(cell->getPort("\\B")).as_int(cell->type.in("$shift", "$shiftx") && cell->getParam("\\B_SIGNED").as_bool()); + + if (cell->type.in("$shl", "$sshl")) + shift_bits *= -1; + + RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A")); + RTLIL::SigSpec sig_y(cell->type == "$shiftx" ? RTLIL::State::Sx : RTLIL::State::S0, cell->getParam("\\Y_WIDTH").as_int()); + + if (SIZE(sig_a) < SIZE(sig_y)) + sig_a.extend(SIZE(sig_y), cell->getParam("\\A_SIGNED").as_bool()); + + for (int i = 0; i < SIZE(sig_y); i++) { + int idx = i + shift_bits; + if (0 <= idx && idx < SIZE(sig_a)) + sig_y[i] = sig_a[idx]; + else if (SIZE(sig_a) <= idx && sign_ext) + sig_y[i] = sig_a[SIZE(sig_a)-1]; + } + + cover_list("opt.opt_const.constshift", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", cell->type.str()); + + log("Replacing %s cell `%s' (B=%s, SHR=%d) in module `%s' with fixed wiring: %s\n", + log_id(cell->type), log_id(cell), log_signal(assign_map(cell->getPort("\\B"))), shift_bits, log_id(module), log_signal(sig_y)); + + module->connect(cell->getPort("\\Y"), sig_y); + module->remove(cell); + + OPT_DID_SOMETHING = true; + did_something = true; + goto next_cell; + } + if (!keepdc) { bool identity_bu0 = false; -- cgit v1.2.3 From 084685f4805e643c4799abcbfe114ab8c1138b72 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 26 Aug 2014 12:51:08 +0200 Subject: Implemented "rename -enumerate -pattern" --- passes/cmds/rename.cc | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) (limited to 'passes') diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc index 3a6008721..91de364fe 100644 --- a/passes/cmds/rename.cc +++ b/passes/cmds/rename.cc @@ -58,10 +58,12 @@ struct RenamePass : public Pass { log("by this command.\n"); log("\n"); log("\n"); - log(" rename -enumerate [selection]\n"); + log(" rename -enumerate [-pattern ] [selection]\n"); log("\n"); log("Assign short auto-generated names to all selected wires and cells with private\n"); - log("names.\n"); + log("names. The -pattern option can be used to set the pattern for the new names.\n"); + log("The character %% in the pattern is replaced with a integer number. The default\n"); + log("pattern is '_%%_'.\n"); log("\n"); log(" rename -hide [selection]\n"); log("\n"); @@ -71,6 +73,7 @@ struct RenamePass : public Pass { } virtual void execute(std::vector args, RTLIL::Design *design) { + std::string pattern_prefix = "_", pattern_suffix = "_"; bool flag_enumerate = false; bool flag_hide = false; bool got_mode = false; @@ -89,6 +92,12 @@ struct RenamePass : public Pass { got_mode = true; continue; } + if (arg == "-pattern" && argidx+1 < args.size() && args[argidx+1].find('%') != std::string::npos) { + int pos = args[++argidx].find('%'); + pattern_prefix = args[argidx].substr(0, pos); + pattern_suffix = args[argidx].substr(pos+1); + continue; + } break; } @@ -107,7 +116,7 @@ struct RenamePass : public Pass { std::map new_wires; for (auto &it : module->wires_) { if (it.first[0] == '$' && design->selected(module, it.second)) - do it.second->name = stringf("\\_%d_", counter++); + do it.second->name = stringf("\\%s%d%s", pattern_prefix.c_str(), counter++, pattern_suffix.c_str()); while (module->count_id(it.second->name) > 0); new_wires[it.second->name] = it.second; } @@ -116,7 +125,7 @@ struct RenamePass : public Pass { std::map new_cells; for (auto &it : module->cells_) { if (it.first[0] == '$' && design->selected(module, it.second)) - do it.second->name = stringf("\\_%d_", counter++); + do it.second->name = stringf("\\%s%d%s", pattern_prefix.c_str(), counter++, pattern_suffix.c_str()); while (module->count_id(it.second->name) > 0); new_cells[it.second->name] = it.second; } -- cgit v1.2.3 From d148b0af0d5d1a039b13b9e610859a2e55da945e Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 27 Aug 2014 19:44:12 +0200 Subject: Fixed inserting of Q-inverters in dfflibmap --- passes/techmap/dfflibmap.cc | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'passes') diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc index 7e39040c4..07993b868 100644 --- a/passes/techmap/dfflibmap.cc +++ b/passes/techmap/dfflibmap.cc @@ -409,6 +409,11 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module) if ('A' <= port.second && port.second <= 'Z') { sig = cell_connections[std::string("\\") + port.second]; } else + if (port.second == 'q') { + RTLIL::SigSpec old_sig = cell_connections[std::string("\\") + char(port.second - ('a' - 'A'))]; + sig = module->addWire(NEW_ID, SIZE(old_sig)); + module->addNotGate(NEW_ID, sig, old_sig); + } else if ('a' <= port.second && port.second <= 'z') { sig = cell_connections[std::string("\\") + char(port.second - ('a' - 'A'))]; sig = module->NotGate(NEW_ID, sig); -- cgit v1.2.3 From ab019b0bd505ccd63ba1d45013fa163134f6e13b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 30 Aug 2014 14:11:57 +0200 Subject: Improved handling of $pmux cells in fsm_extract --- passes/fsm/fsm_extract.cc | 95 +++++++++++++++++++++++++++++++++++++---------- 1 file changed, 75 insertions(+), 20 deletions(-) (limited to 'passes') diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index 871478dee..d1d73db6d 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -33,6 +33,7 @@ static RTLIL::Module *module; static SigMap assign_map; typedef std::pair sig2driver_entry_t; static SigSet sig2driver, sig2trigger; +static std::map> exclusive_ctrls; static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL::SigSpec &ctrl, std::map &states, RTLIL::Const *reset_state = NULL) { @@ -43,7 +44,7 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL assign_map.apply(sig); if (sig.is_fully_const()) { - if (states.count(sig.as_const()) == 0) { + if (sig.is_fully_def() && states.count(sig.as_const()) == 0) { log(" found state code: %s\n", log_signal(sig)); states[sig.as_const()] = -1; } @@ -123,18 +124,41 @@ static RTLIL::Const sig2const(ConstEval &ce, RTLIL::SigSpec sig, RTLIL::State no static void find_transitions(ConstEval &ce, ConstEval &ce_nostop, FsmData &fsm_data, std::map &states, int state_in, RTLIL::SigSpec ctrl_in, RTLIL::SigSpec ctrl_out, RTLIL::SigSpec dff_in, RTLIL::SigSpec dont_care) { + bool undef_bit_in_next_state_mode = false; RTLIL::SigSpec undef, constval; - if (ce.eval(ctrl_out, undef) && ce.eval(dff_in, undef)) { + if (ce.eval(ctrl_out, undef) && ce.eval(dff_in, undef)) + { + if (0) { +undef_bit_in_next_state: + for (auto &bit : dff_in) + if (bit.wire != nullptr) bit = RTLIL::Sm; + for (auto &bit : ctrl_out) + if (bit.wire != nullptr) bit = RTLIL::Sm; + undef_bit_in_next_state_mode = true; + } + log_assert(ctrl_out.is_fully_const() && dff_in.is_fully_const()); + FsmData::transition_t tr; - tr.state_in = state_in; - tr.state_out = states[ce.values_map(ce.assign_map(dff_in)).as_const()]; tr.ctrl_in = sig2const(ce, ctrl_in, RTLIL::State::Sa, dont_care); tr.ctrl_out = sig2const(ce, ctrl_out, RTLIL::State::Sx); + RTLIL::Const log_state_in = RTLIL::Const(RTLIL::State::Sx, fsm_data.state_bits); if (state_in >= 0) - log_state_in = fsm_data.state_table[tr.state_in]; + log_state_in = fsm_data.state_table.at(state_in); + + if (states.count(ce.values_map(ce.assign_map(dff_in)).as_const()) == 0) { + log(" transition: %10s %s -> INVALID_STATE(%s) %s %s\n", + log_signal(log_state_in), log_signal(tr.ctrl_in), + log_signal(ce.values_map(ce.assign_map(dff_in))), log_signal(tr.ctrl_out), + undef_bit_in_next_state_mode ? " SHORTENED" : ""); + return; + } + + tr.state_in = state_in; + tr.state_out = states.at(ce.values_map(ce.assign_map(dff_in)).as_const()); + if (dff_in.is_fully_def()) { fsm_data.transition_table.push_back(tr); log(" transition: %10s %s -> %10s %s\n", @@ -148,6 +172,10 @@ static void find_transitions(ConstEval &ce, ConstEval &ce_nostop, FsmData &fsm_d return; } + for (auto &bit : dff_in) + if (bit == RTLIL::Sx) + goto undef_bit_in_next_state; + log_assert(undef.size() > 0); log_assert(ce.stop_signals.check_all(undef)); @@ -159,21 +187,39 @@ static void find_transitions(ConstEval &ce, ConstEval &ce_nostop, FsmData &fsm_d ce.push(); dont_care.append(undef); ce.set(undef, constval.as_const()); + if (exclusive_ctrls.count(undef) && constval == RTLIL::S1) + for (auto &bit : exclusive_ctrls.at(undef)) { + RTLIL::SigSpec bitval = bit; + if (ce.eval(bitval) && bitval != RTLIL::S0) + goto found_contradiction_1; + else + ce.set(bit, RTLIL::S0); + } find_transitions(ce, ce_nostop, fsm_data, states, state_in, ctrl_in, ctrl_out, dff_in, dont_care); + found_contradiction_1: ce.pop(); } else { ce.push(), ce_nostop.push(); - ce.set(undef, RTLIL::Const(0, 1)); - ce_nostop.set(undef, RTLIL::Const(0, 1)); + ce.set(undef, RTLIL::S0); + ce_nostop.set(undef, RTLIL::S0); find_transitions(ce, ce_nostop, fsm_data, states, state_in, ctrl_in, ctrl_out, dff_in, dont_care); ce.pop(), ce_nostop.pop(); ce.push(), ce_nostop.push(); - ce.set(undef, RTLIL::Const(1, 1)); - ce_nostop.set(undef, RTLIL::Const(1, 1)); + ce.set(undef, RTLIL::S1); + ce_nostop.set(undef, RTLIL::S1); + if (exclusive_ctrls.count(undef)) + for (auto &bit : exclusive_ctrls.at(undef)) { + RTLIL::SigSpec bitval = bit; + if ((ce.eval(bitval) || ce_nostop.eval(bitval)) && bitval != RTLIL::S0) + goto found_contradiction_2; + else + ce.set(bit, RTLIL::S0), ce_nostop.set(bit, RTLIL::S0); + } find_transitions(ce, ce_nostop, fsm_data, states, state_in, ctrl_in, ctrl_out, dff_in, dont_care); + found_contradiction_2: ce.pop(), ce_nostop.pop(); } } @@ -188,8 +234,8 @@ static void extract_fsm(RTLIL::Wire *wire) RTLIL::SigSpec dff_in(RTLIL::State::Sm, wire->width); RTLIL::Const reset_state(RTLIL::State::Sx, wire->width); - RTLIL::SigSpec clk = RTLIL::SigSpec(0, 1); - RTLIL::SigSpec arst = RTLIL::SigSpec(0, 1); + RTLIL::SigSpec clk = RTLIL::S0; + RTLIL::SigSpec arst = RTLIL::S0; bool clk_polarity = true; bool arst_polarity = true; @@ -294,8 +340,8 @@ static void extract_fsm(RTLIL::Wire *wire) RTLIL::Cell *fsm_cell = module->addCell(stringf("$fsm$%s$%d", wire->name.c_str(), autoidx++), "$fsm"); fsm_cell->setPort("\\CLK", clk); fsm_cell->setPort("\\ARST", arst); - fsm_cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity ? 1 : 0, 1); - fsm_cell->parameters["\\ARST_POLARITY"] = RTLIL::Const(arst_polarity ? 1 : 0, 1); + fsm_cell->parameters["\\CLK_POLARITY"] = clk_polarity ? RTLIL::S1 : RTLIL::S0; + fsm_cell->parameters["\\ARST_POLARITY"] = arst_polarity ? RTLIL::S1 : RTLIL::S0; fsm_cell->setPort("\\CTRL_IN", ctrl_in); fsm_cell->setPort("\\CTRL_OUT", ctrl_out); fsm_cell->parameters["\\NAME"] = RTLIL::Const(wire->name.str()); @@ -361,20 +407,29 @@ struct FsmExtractPass : public Pass { sig2driver.clear(); sig2trigger.clear(); - for (auto &cell_it : module->cells_) - for (auto &conn_it : cell_it.second->connections()) { - if (ct.cell_output(cell_it.second->type, conn_it.first) || !ct.cell_known(cell_it.second->type)) { + exclusive_ctrls.clear(); + for (auto cell : module->cells()) { + for (auto &conn_it : cell->connections()) { + if (ct.cell_output(cell->type, conn_it.first) || !ct.cell_known(cell->type)) { RTLIL::SigSpec sig = conn_it.second; assign_map.apply(sig); - sig2driver.insert(sig, sig2driver_entry_t(cell_it.first, conn_it.first)); + sig2driver.insert(sig, sig2driver_entry_t(cell->name, conn_it.first)); } - if (ct.cell_input(cell_it.second->type, conn_it.first) && cell_it.second->hasPort("\\Y") && - cell_it.second->getPort("\\Y").size() == 1 && (conn_it.first == "\\A" || conn_it.first == "\\B")) { + if (ct.cell_input(cell->type, conn_it.first) && cell->hasPort("\\Y") && + cell->getPort("\\Y").size() == 1 && (conn_it.first == "\\A" || conn_it.first == "\\B")) { RTLIL::SigSpec sig = conn_it.second; assign_map.apply(sig); - sig2trigger.insert(sig, sig2driver_entry_t(cell_it.first, conn_it.first)); + sig2trigger.insert(sig, sig2driver_entry_t(cell->name, conn_it.first)); } } + if (cell->type == "$pmux") { + RTLIL::SigSpec sel_sig = assign_map(cell->getPort("\\S")); + for (auto &bit1 : sel_sig) + for (auto &bit2 : sel_sig) + if (bit1 != bit2) + exclusive_ctrls[bit1].insert(bit2); + } + } std::vector wire_list; for (auto &wire_it : module->wires_) -- cgit v1.2.3 From f910481f35109d7333088ac79bb25729e516fa00 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 30 Aug 2014 14:34:49 +0200 Subject: Using $pmux info in fsm_extract to optimize transition ctrl_in patterns --- passes/fsm/fsm_extract.cc | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'passes') diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index d1d73db6d..451f00fcb 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -144,6 +144,16 @@ undef_bit_in_next_state: tr.ctrl_in = sig2const(ce, ctrl_in, RTLIL::State::Sa, dont_care); tr.ctrl_out = sig2const(ce, ctrl_out, RTLIL::State::Sx); + std::map ctrl_in_bit_indices; + for (int i = 0; i < SIZE(ctrl_in); i++) + ctrl_in_bit_indices[ctrl_in[i]] = i; + + for (auto &it : ctrl_in_bit_indices) + if (tr.ctrl_in.bits.at(it.second) == RTLIL::S1 && exclusive_ctrls.count(it.first) != 0) + for (auto &dc_bit : exclusive_ctrls.at(it.first)) + if (ctrl_in_bit_indices.count(dc_bit)) + tr.ctrl_in.bits.at(ctrl_in_bit_indices.at(dc_bit)) = RTLIL::State::Sa; + RTLIL::Const log_state_in = RTLIL::Const(RTLIL::State::Sx, fsm_data.state_bits); if (state_in >= 0) log_state_in = fsm_data.state_table.at(state_in); -- cgit v1.2.3 From 3a7d5d188d4b9cfeb225e0f5dea07ee7a40eceed Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 30 Aug 2014 14:43:06 +0200 Subject: Don't change existing binary FSM encoding if it is already optimal --- passes/fsm/fsm_recode.cc | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/fsm/fsm_recode.cc b/passes/fsm/fsm_recode.cc index 9c0da0a37..ea10cdf80 100644 --- a/passes/fsm/fsm_recode.cc +++ b/passes/fsm/fsm_recode.cc @@ -82,7 +82,12 @@ static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fs fsm_data.state_bits = fsm_data.state_table.size(); } else if (encoding == "binary") { - fsm_data.state_bits = ceil(log2(fsm_data.state_table.size())); + int new_num_state_bits = ceil(log2(fsm_data.state_table.size())); + if (fsm_data.state_bits == new_num_state_bits) { + log(" existing encoding is already a packed binary encoding.\n"); + return; + } + fsm_data.state_bits = new_num_state_bits; } else log_error("FSM encoding `%s' is not supported!\n", encoding.c_str()); -- cgit v1.2.3 From 66763fad4e3f93b11fbc72acd94174a56084ad17 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 30 Aug 2014 17:39:08 +0200 Subject: Using worker class in memory_map --- passes/memory/memory_map.cc | 457 ++++++++++++++++++++++---------------------- 1 file changed, 231 insertions(+), 226 deletions(-) (limited to 'passes') diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index 8dc66f2cd..878994679 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -23,283 +23,289 @@ #include #include -static std::string genid(RTLIL::IdString name, std::string token1 = "", int i = -1, std::string token2 = "", int j = -1, std::string token3 = "", int k = -1, std::string token4 = "") +struct MemoryMapWorker { - std::stringstream sstr; - sstr << "$memory" << name.str() << token1; - - if (i >= 0) - sstr << "[" << i << "]"; + RTLIL::Design *design; + RTLIL::Module *module; - sstr << token2; + std::string genid(RTLIL::IdString name, std::string token1 = "", int i = -1, std::string token2 = "", int j = -1, std::string token3 = "", int k = -1, std::string token4 = "") + { + std::stringstream sstr; + sstr << "$memory" << name.str() << token1; + + if (i >= 0) + sstr << "[" << i << "]"; - if (j >= 0) - sstr << "[" << j << "]"; + sstr << token2; - sstr << token3; + if (j >= 0) + sstr << "[" << j << "]"; - if (k >= 0) - sstr << "[" << k << "]"; + sstr << token3; - sstr << token4 << "$" << (autoidx++); - return sstr.str(); -} + if (k >= 0) + sstr << "[" << k << "]"; -static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) -{ - std::set static_ports; - std::map static_cells_map; - int mem_size = cell->parameters["\\SIZE"].as_int(); - int mem_width = cell->parameters["\\WIDTH"].as_int(); - int mem_offset = cell->parameters["\\OFFSET"].as_int(); - int mem_abits = cell->parameters["\\ABITS"].as_int(); - - // delete unused memory cell - if (cell->parameters["\\RD_PORTS"].as_int() == 0 && cell->parameters["\\WR_PORTS"].as_int() == 0) { - module->remove(cell); - return; + sstr << token4 << "$" << (autoidx++); + return sstr.str(); } - // all write ports must share the same clock - RTLIL::SigSpec clocks = cell->getPort("\\WR_CLK"); - RTLIL::Const clocks_pol = cell->parameters["\\WR_CLK_POLARITY"]; - RTLIL::Const clocks_en = cell->parameters["\\WR_CLK_ENABLE"]; - RTLIL::SigSpec refclock; - RTLIL::State refclock_pol = RTLIL::State::Sx; - for (int i = 0; i < clocks.size(); i++) { - RTLIL::SigSpec wr_en = cell->getPort("\\WR_EN").extract(i * mem_width, mem_width); - if (wr_en.is_fully_const() && !wr_en.as_bool()) { - static_ports.insert(i); - continue; + void handle_cell(RTLIL::Cell *cell) + { + std::set static_ports; + std::map static_cells_map; + int mem_size = cell->parameters["\\SIZE"].as_int(); + int mem_width = cell->parameters["\\WIDTH"].as_int(); + int mem_offset = cell->parameters["\\OFFSET"].as_int(); + int mem_abits = cell->parameters["\\ABITS"].as_int(); + + // delete unused memory cell + if (cell->parameters["\\RD_PORTS"].as_int() == 0 && cell->parameters["\\WR_PORTS"].as_int() == 0) { + module->remove(cell); + return; } - if (clocks_en.bits[i] != RTLIL::State::S1) { - RTLIL::SigSpec wr_addr = cell->getPort("\\WR_ADDR").extract(i*mem_abits, mem_abits); - RTLIL::SigSpec wr_data = cell->getPort("\\WR_DATA").extract(i*mem_width, mem_width); - if (wr_addr.is_fully_const()) { - // FIXME: Actually we should check for wr_en.is_fully_const() also and - // create a $adff cell with this ports wr_en input as reset pin when wr_en - // is not a simple static 1. - static_cells_map[wr_addr.as_int()] = wr_data; + + // all write ports must share the same clock + RTLIL::SigSpec clocks = cell->getPort("\\WR_CLK"); + RTLIL::Const clocks_pol = cell->parameters["\\WR_CLK_POLARITY"]; + RTLIL::Const clocks_en = cell->parameters["\\WR_CLK_ENABLE"]; + RTLIL::SigSpec refclock; + RTLIL::State refclock_pol = RTLIL::State::Sx; + for (int i = 0; i < clocks.size(); i++) { + RTLIL::SigSpec wr_en = cell->getPort("\\WR_EN").extract(i * mem_width, mem_width); + if (wr_en.is_fully_const() && !wr_en.as_bool()) { static_ports.insert(i); continue; } - log("Not mapping memory cell %s in module %s (write port %d has no clock).\n", - cell->name.c_str(), module->name.c_str(), i); - return; - } - if (refclock.size() == 0) { - refclock = clocks.extract(i, 1); - refclock_pol = clocks_pol.bits[i]; - } - if (clocks.extract(i, 1) != refclock || clocks_pol.bits[i] != refclock_pol) { - log("Not mapping memory cell %s in module %s (write clock %d is incompatible with other clocks).\n", - cell->name.c_str(), module->name.c_str(), i); - return; + if (clocks_en.bits[i] != RTLIL::State::S1) { + RTLIL::SigSpec wr_addr = cell->getPort("\\WR_ADDR").extract(i*mem_abits, mem_abits); + RTLIL::SigSpec wr_data = cell->getPort("\\WR_DATA").extract(i*mem_width, mem_width); + if (wr_addr.is_fully_const()) { + // FIXME: Actually we should check for wr_en.is_fully_const() also and + // create a $adff cell with this ports wr_en input as reset pin when wr_en + // is not a simple static 1. + static_cells_map[wr_addr.as_int()] = wr_data; + static_ports.insert(i); + continue; + } + log("Not mapping memory cell %s in module %s (write port %d has no clock).\n", + cell->name.c_str(), module->name.c_str(), i); + return; + } + if (refclock.size() == 0) { + refclock = clocks.extract(i, 1); + refclock_pol = clocks_pol.bits[i]; + } + if (clocks.extract(i, 1) != refclock || clocks_pol.bits[i] != refclock_pol) { + log("Not mapping memory cell %s in module %s (write clock %d is incompatible with other clocks).\n", + cell->name.c_str(), module->name.c_str(), i); + return; + } } - } - log("Mapping memory cell %s in module %s:\n", cell->name.c_str(), module->name.c_str()); + log("Mapping memory cell %s in module %s:\n", cell->name.c_str(), module->name.c_str()); - std::vector data_reg_in; - std::vector data_reg_out; + std::vector data_reg_in; + std::vector data_reg_out; - int count_static = 0; + int count_static = 0; - for (int i = 0; i < mem_size; i++) - { - if (static_cells_map.count(i) > 0) + for (int i = 0; i < mem_size; i++) { - data_reg_in.push_back(RTLIL::SigSpec(RTLIL::State::Sz, mem_width)); - data_reg_out.push_back(static_cells_map[i]); - count_static++; - } - else - { - RTLIL::Cell *c = module->addCell(genid(cell->name, "", i), "$dff"); - c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"]; - if (clocks_pol.bits.size() > 0) { - c->parameters["\\CLK_POLARITY"] = RTLIL::Const(clocks_pol.bits[0]); - c->setPort("\\CLK", clocks.extract(0, 1)); - } else { - c->parameters["\\CLK_POLARITY"] = RTLIL::Const(RTLIL::State::S1); - c->setPort("\\CLK", RTLIL::SigSpec(RTLIL::State::S0)); + if (static_cells_map.count(i) > 0) + { + data_reg_in.push_back(RTLIL::SigSpec(RTLIL::State::Sz, mem_width)); + data_reg_out.push_back(static_cells_map[i]); + count_static++; } + else + { + RTLIL::Cell *c = module->addCell(genid(cell->name, "", i), "$dff"); + c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"]; + if (clocks_pol.bits.size() > 0) { + c->parameters["\\CLK_POLARITY"] = RTLIL::Const(clocks_pol.bits[0]); + c->setPort("\\CLK", clocks.extract(0, 1)); + } else { + c->parameters["\\CLK_POLARITY"] = RTLIL::Const(RTLIL::State::S1); + c->setPort("\\CLK", RTLIL::SigSpec(RTLIL::State::S0)); + } - RTLIL::Wire *w_in = module->addWire(genid(cell->name, "", i, "$d"), mem_width); - data_reg_in.push_back(RTLIL::SigSpec(w_in)); - c->setPort("\\D", data_reg_in.back()); + RTLIL::Wire *w_in = module->addWire(genid(cell->name, "", i, "$d"), mem_width); + data_reg_in.push_back(RTLIL::SigSpec(w_in)); + c->setPort("\\D", data_reg_in.back()); - std::string w_out_name = stringf("%s[%d]", cell->parameters["\\MEMID"].decode_string().c_str(), i); - if (module->wires_.count(w_out_name) > 0) - w_out_name = genid(cell->name, "", i, "$q"); + std::string w_out_name = stringf("%s[%d]", cell->parameters["\\MEMID"].decode_string().c_str(), i); + if (module->wires_.count(w_out_name) > 0) + w_out_name = genid(cell->name, "", i, "$q"); - RTLIL::Wire *w_out = module->addWire(w_out_name, mem_width); - w_out->start_offset = mem_offset; + RTLIL::Wire *w_out = module->addWire(w_out_name, mem_width); + w_out->start_offset = mem_offset; - data_reg_out.push_back(RTLIL::SigSpec(w_out)); - c->setPort("\\Q", data_reg_out.back()); + data_reg_out.push_back(RTLIL::SigSpec(w_out)); + c->setPort("\\Q", data_reg_out.back()); + } } - } - - log(" created %d $dff cells and %d static cells of width %d.\n", mem_size-count_static, count_static, mem_width); - int count_dff = 0, count_mux = 0, count_wrmux = 0; - - for (int i = 0; i < cell->parameters["\\RD_PORTS"].as_int(); i++) - { - RTLIL::SigSpec rd_addr = cell->getPort("\\RD_ADDR").extract(i*mem_abits, mem_abits); + log(" created %d $dff cells and %d static cells of width %d.\n", mem_size-count_static, count_static, mem_width); - std::vector rd_signals; - rd_signals.push_back(cell->getPort("\\RD_DATA").extract(i*mem_width, mem_width)); + int count_dff = 0, count_mux = 0, count_wrmux = 0; - if (cell->parameters["\\RD_CLK_ENABLE"].bits[i] == RTLIL::State::S1) + for (int i = 0; i < cell->parameters["\\RD_PORTS"].as_int(); i++) { - if (cell->parameters["\\RD_TRANSPARENT"].bits[i] == RTLIL::State::S1) - { - RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdreg", i), "$dff"); - c->parameters["\\WIDTH"] = RTLIL::Const(mem_abits); - c->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]); - c->setPort("\\CLK", cell->getPort("\\RD_CLK").extract(i, 1)); - c->setPort("\\D", rd_addr); - count_dff++; + RTLIL::SigSpec rd_addr = cell->getPort("\\RD_ADDR").extract(i*mem_abits, mem_abits); - RTLIL::Wire *w = module->addWire(genid(cell->name, "$rdreg", i, "$q"), mem_abits); + std::vector rd_signals; + rd_signals.push_back(cell->getPort("\\RD_DATA").extract(i*mem_width, mem_width)); - c->setPort("\\Q", RTLIL::SigSpec(w)); - rd_addr = RTLIL::SigSpec(w); - } - else + if (cell->parameters["\\RD_CLK_ENABLE"].bits[i] == RTLIL::State::S1) { - RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdreg", i), "$dff"); - c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"]; - c->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]); - c->setPort("\\CLK", cell->getPort("\\RD_CLK").extract(i, 1)); - c->setPort("\\Q", rd_signals.back()); - count_dff++; + if (cell->parameters["\\RD_TRANSPARENT"].bits[i] == RTLIL::State::S1) + { + RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdreg", i), "$dff"); + c->parameters["\\WIDTH"] = RTLIL::Const(mem_abits); + c->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]); + c->setPort("\\CLK", cell->getPort("\\RD_CLK").extract(i, 1)); + c->setPort("\\D", rd_addr); + count_dff++; - RTLIL::Wire *w = module->addWire(genid(cell->name, "$rdreg", i, "$d"), mem_width); + RTLIL::Wire *w = module->addWire(genid(cell->name, "$rdreg", i, "$q"), mem_abits); - rd_signals.clear(); - rd_signals.push_back(RTLIL::SigSpec(w)); - c->setPort("\\D", rd_signals.back()); + c->setPort("\\Q", RTLIL::SigSpec(w)); + rd_addr = RTLIL::SigSpec(w); + } + else + { + RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdreg", i), "$dff"); + c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"]; + c->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]); + c->setPort("\\CLK", cell->getPort("\\RD_CLK").extract(i, 1)); + c->setPort("\\Q", rd_signals.back()); + count_dff++; + + RTLIL::Wire *w = module->addWire(genid(cell->name, "$rdreg", i, "$d"), mem_width); + + rd_signals.clear(); + rd_signals.push_back(RTLIL::SigSpec(w)); + c->setPort("\\D", rd_signals.back()); + } } - } - - for (int j = 0; j < mem_abits; j++) - { - std::vector next_rd_signals; - for (size_t k = 0; k < rd_signals.size(); k++) + for (int j = 0; j < mem_abits; j++) { - RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdmux", i, "", j, "", k), "$mux"); - c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"]; - c->setPort("\\Y", rd_signals[k]); - c->setPort("\\S", rd_addr.extract(mem_abits-j-1, 1)); - count_mux++; + std::vector next_rd_signals; - c->setPort("\\A", module->addWire(genid(cell->name, "$rdmux", i, "", j, "", k, "$a"), mem_width)); - c->setPort("\\B", module->addWire(genid(cell->name, "$rdmux", i, "", j, "", k, "$b"), mem_width)); - - next_rd_signals.push_back(c->getPort("\\A")); - next_rd_signals.push_back(c->getPort("\\B")); - } + for (size_t k = 0; k < rd_signals.size(); k++) + { + RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdmux", i, "", j, "", k), "$mux"); + c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"]; + c->setPort("\\Y", rd_signals[k]); + c->setPort("\\S", rd_addr.extract(mem_abits-j-1, 1)); + count_mux++; - next_rd_signals.swap(rd_signals); - } + c->setPort("\\A", module->addWire(genid(cell->name, "$rdmux", i, "", j, "", k, "$a"), mem_width)); + c->setPort("\\B", module->addWire(genid(cell->name, "$rdmux", i, "", j, "", k, "$b"), mem_width)); - for (int j = 0; j < mem_size; j++) - module->connect(RTLIL::SigSig(rd_signals[j], data_reg_out[j])); - } + next_rd_signals.push_back(c->getPort("\\A")); + next_rd_signals.push_back(c->getPort("\\B")); + } - log(" read interface: %d $dff and %d $mux cells.\n", count_dff, count_mux); + next_rd_signals.swap(rd_signals); + } - for (int i = 0; i < mem_size; i++) - { - if (static_cells_map.count(i) > 0) - continue; + for (int j = 0; j < mem_size; j++) + module->connect(RTLIL::SigSig(rd_signals[j], data_reg_out[j])); + } - RTLIL::SigSpec sig = data_reg_out[i]; + log(" read interface: %d $dff and %d $mux cells.\n", count_dff, count_mux); - for (int j = 0; j < cell->parameters["\\WR_PORTS"].as_int(); j++) + for (int i = 0; i < mem_size; i++) { - RTLIL::SigSpec wr_addr = cell->getPort("\\WR_ADDR").extract(j*mem_abits, mem_abits); - RTLIL::SigSpec wr_data = cell->getPort("\\WR_DATA").extract(j*mem_width, mem_width); - RTLIL::SigSpec wr_en = cell->getPort("\\WR_EN").extract(j*mem_width, mem_width); - - RTLIL::Cell *c = module->addCell(genid(cell->name, "$wreq", i, "", j), "$eq"); - c->parameters["\\A_SIGNED"] = RTLIL::Const(0); - c->parameters["\\B_SIGNED"] = RTLIL::Const(0); - c->parameters["\\A_WIDTH"] = cell->parameters["\\ABITS"]; - c->parameters["\\B_WIDTH"] = cell->parameters["\\ABITS"]; - c->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - c->setPort("\\A", RTLIL::SigSpec(i, mem_abits)); - c->setPort("\\B", wr_addr); - count_wrmux++; - - RTLIL::Wire *w_seladdr = module->addWire(genid(cell->name, "$wreq", i, "", j, "$y")); - c->setPort("\\Y", w_seladdr); - - int wr_offset = 0; - while (wr_offset < wr_en.size()) - { - int wr_width = 1; - RTLIL::SigSpec wr_bit = wr_en.extract(wr_offset, 1); - - while (wr_offset + wr_width < wr_en.size()) { - RTLIL::SigSpec next_wr_bit = wr_en.extract(wr_offset + wr_width, 1); - if (next_wr_bit != wr_bit) - break; - wr_width++; - } + if (static_cells_map.count(i) > 0) + continue; - RTLIL::Wire *w = w_seladdr; + RTLIL::SigSpec sig = data_reg_out[i]; - if (wr_bit != RTLIL::SigSpec(1, 1)) + for (int j = 0; j < cell->parameters["\\WR_PORTS"].as_int(); j++) + { + RTLIL::SigSpec wr_addr = cell->getPort("\\WR_ADDR").extract(j*mem_abits, mem_abits); + RTLIL::SigSpec wr_data = cell->getPort("\\WR_DATA").extract(j*mem_width, mem_width); + RTLIL::SigSpec wr_en = cell->getPort("\\WR_EN").extract(j*mem_width, mem_width); + + RTLIL::Cell *c = module->addCell(genid(cell->name, "$wreq", i, "", j), "$eq"); + c->parameters["\\A_SIGNED"] = RTLIL::Const(0); + c->parameters["\\B_SIGNED"] = RTLIL::Const(0); + c->parameters["\\A_WIDTH"] = cell->parameters["\\ABITS"]; + c->parameters["\\B_WIDTH"] = cell->parameters["\\ABITS"]; + c->parameters["\\Y_WIDTH"] = RTLIL::Const(1); + c->setPort("\\A", RTLIL::SigSpec(i, mem_abits)); + c->setPort("\\B", wr_addr); + count_wrmux++; + + RTLIL::Wire *w_seladdr = module->addWire(genid(cell->name, "$wreq", i, "", j, "$y")); + c->setPort("\\Y", w_seladdr); + + int wr_offset = 0; + while (wr_offset < wr_en.size()) { - c = module->addCell(genid(cell->name, "$wren", i, "", j, "", wr_offset), "$and"); - c->parameters["\\A_SIGNED"] = RTLIL::Const(0); - c->parameters["\\B_SIGNED"] = RTLIL::Const(0); - c->parameters["\\A_WIDTH"] = RTLIL::Const(1); - c->parameters["\\B_WIDTH"] = RTLIL::Const(1); - c->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - c->setPort("\\A", w); - c->setPort("\\B", wr_bit); - - w = module->addWire(genid(cell->name, "$wren", i, "", j, "", wr_offset, "$y")); - c->setPort("\\Y", RTLIL::SigSpec(w)); + int wr_width = 1; + RTLIL::SigSpec wr_bit = wr_en.extract(wr_offset, 1); + + while (wr_offset + wr_width < wr_en.size()) { + RTLIL::SigSpec next_wr_bit = wr_en.extract(wr_offset + wr_width, 1); + if (next_wr_bit != wr_bit) + break; + wr_width++; + } + + RTLIL::Wire *w = w_seladdr; + + if (wr_bit != RTLIL::SigSpec(1, 1)) + { + c = module->addCell(genid(cell->name, "$wren", i, "", j, "", wr_offset), "$and"); + c->parameters["\\A_SIGNED"] = RTLIL::Const(0); + c->parameters["\\B_SIGNED"] = RTLIL::Const(0); + c->parameters["\\A_WIDTH"] = RTLIL::Const(1); + c->parameters["\\B_WIDTH"] = RTLIL::Const(1); + c->parameters["\\Y_WIDTH"] = RTLIL::Const(1); + c->setPort("\\A", w); + c->setPort("\\B", wr_bit); + + w = module->addWire(genid(cell->name, "$wren", i, "", j, "", wr_offset, "$y")); + c->setPort("\\Y", RTLIL::SigSpec(w)); + } + + c = module->addCell(genid(cell->name, "$wrmux", i, "", j, "", wr_offset), "$mux"); + c->parameters["\\WIDTH"] = wr_width; + c->setPort("\\A", sig.extract(wr_offset, wr_width)); + c->setPort("\\B", wr_data.extract(wr_offset, wr_width)); + c->setPort("\\S", RTLIL::SigSpec(w)); + + w = module->addWire(genid(cell->name, "$wrmux", i, "", j, "", wr_offset, "$y"), wr_width); + c->setPort("\\Y", w); + + sig.replace(wr_offset, w); + wr_offset += wr_width; } - - c = module->addCell(genid(cell->name, "$wrmux", i, "", j, "", wr_offset), "$mux"); - c->parameters["\\WIDTH"] = wr_width; - c->setPort("\\A", sig.extract(wr_offset, wr_width)); - c->setPort("\\B", wr_data.extract(wr_offset, wr_width)); - c->setPort("\\S", RTLIL::SigSpec(w)); - - w = module->addWire(genid(cell->name, "$wrmux", i, "", j, "", wr_offset, "$y"), wr_width); - c->setPort("\\Y", w); - - sig.replace(wr_offset, w); - wr_offset += wr_width; } - } - module->connect(RTLIL::SigSig(data_reg_in[i], sig)); - } + module->connect(RTLIL::SigSig(data_reg_in[i], sig)); + } - log(" write interface: %d blocks of $eq, $and and $mux cells.\n", count_wrmux); + log(" write interface: %d blocks of $eq, $and and $mux cells.\n", count_wrmux); - module->remove(cell); -} + module->remove(cell); + } -static void handle_module(RTLIL::Design *design, RTLIL::Module *module) -{ - std::vector cells; - for (auto &it : module->cells_) - if (it.second->type == "$mem" && design->selected(module, it.second)) - cells.push_back(it.second); - for (auto cell : cells) - handle_cell(module, cell); -} + MemoryMapWorker(RTLIL::Design *design, RTLIL::Module *module) : design(design), module(module) + { + std::vector cells; + for (auto cell : module->selected_cells()) + if (cell->type == "$mem" && design->selected(module, cell)) + cells.push_back(cell); + for (auto cell : cells) + handle_cell(cell); + } +}; struct MemoryMapPass : public Pass { MemoryMapPass() : Pass("memory_map", "translate multiport memories to basic cells") { } @@ -316,9 +322,8 @@ struct MemoryMapPass : public Pass { virtual void execute(std::vector args, RTLIL::Design *design) { log_header("Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).\n"); extra_args(args, 1, design); - for (auto &mod_it : design->modules_) - if (design->selected(mod_it.second)) - handle_module(design, mod_it.second); + for (auto mod : design->selected_modules()) + MemoryMapWorker(design, mod); } } MemoryMapPass; -- cgit v1.2.3 From 6ff46323a30d710a9518cffb8c2ae9a5621b7bfc Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 30 Aug 2014 18:18:15 +0200 Subject: Improved write address decoder generation memory_map --- passes/memory/memory_map.cc | 44 ++++++++++++++++++++++++++++---------------- 1 file changed, 28 insertions(+), 16 deletions(-) (limited to 'passes') diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index 878994679..eecb6f35d 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -28,6 +28,8 @@ struct MemoryMapWorker RTLIL::Design *design; RTLIL::Module *module; + std::map, RTLIL::SigBit> decoder_cache; + std::string genid(RTLIL::IdString name, std::string token1 = "", int i = -1, std::string token2 = "", int j = -1, std::string token3 = "", int k = -1, std::string token4 = "") { std::stringstream sstr; @@ -50,6 +52,27 @@ struct MemoryMapWorker return sstr.str(); } + RTLIL::Wire *addr_decode(RTLIL::SigSpec addr_sig, RTLIL::SigSpec addr_val) + { + std::pair key(addr_sig, addr_val); + log_assert(SIZE(addr_sig) == SIZE(addr_val)); + + if (decoder_cache.count(key) == 0) { + if (SIZE(addr_sig) < 2) { + decoder_cache[key] = module->Eq(NEW_ID, addr_sig, addr_val); + } else { + int split_at = SIZE(addr_sig) / 2; + RTLIL::SigBit left_eq = addr_decode(addr_sig.extract(0, split_at), addr_val.extract(0, split_at)); + RTLIL::SigBit right_eq = addr_decode(addr_sig.extract(split_at, SIZE(addr_sig) - split_at), addr_val.extract(split_at, SIZE(addr_val) - split_at)); + decoder_cache[key] = module->And(NEW_ID, left_eq, right_eq); + } + } + + RTLIL::SigBit bit = decoder_cache.at(key); + log_assert(bit.wire != nullptr && SIZE(bit.wire) == 1); + return bit.wire; + } + void handle_cell(RTLIL::Cell *cell) { std::set static_ports; @@ -230,19 +253,7 @@ struct MemoryMapWorker RTLIL::SigSpec wr_addr = cell->getPort("\\WR_ADDR").extract(j*mem_abits, mem_abits); RTLIL::SigSpec wr_data = cell->getPort("\\WR_DATA").extract(j*mem_width, mem_width); RTLIL::SigSpec wr_en = cell->getPort("\\WR_EN").extract(j*mem_width, mem_width); - - RTLIL::Cell *c = module->addCell(genid(cell->name, "$wreq", i, "", j), "$eq"); - c->parameters["\\A_SIGNED"] = RTLIL::Const(0); - c->parameters["\\B_SIGNED"] = RTLIL::Const(0); - c->parameters["\\A_WIDTH"] = cell->parameters["\\ABITS"]; - c->parameters["\\B_WIDTH"] = cell->parameters["\\ABITS"]; - c->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - c->setPort("\\A", RTLIL::SigSpec(i, mem_abits)); - c->setPort("\\B", wr_addr); - count_wrmux++; - - RTLIL::Wire *w_seladdr = module->addWire(genid(cell->name, "$wreq", i, "", j, "$y")); - c->setPort("\\Y", w_seladdr); + RTLIL::Wire *w_seladdr = addr_decode(wr_addr, RTLIL::SigSpec(i, mem_abits)); int wr_offset = 0; while (wr_offset < wr_en.size()) @@ -261,7 +272,7 @@ struct MemoryMapWorker if (wr_bit != RTLIL::SigSpec(1, 1)) { - c = module->addCell(genid(cell->name, "$wren", i, "", j, "", wr_offset), "$and"); + RTLIL::Cell *c = module->addCell(genid(cell->name, "$wren", i, "", j, "", wr_offset), "$and"); c->parameters["\\A_SIGNED"] = RTLIL::Const(0); c->parameters["\\B_SIGNED"] = RTLIL::Const(0); c->parameters["\\A_WIDTH"] = RTLIL::Const(1); @@ -274,7 +285,7 @@ struct MemoryMapWorker c->setPort("\\Y", RTLIL::SigSpec(w)); } - c = module->addCell(genid(cell->name, "$wrmux", i, "", j, "", wr_offset), "$mux"); + RTLIL::Cell *c = module->addCell(genid(cell->name, "$wrmux", i, "", j, "", wr_offset), "$mux"); c->parameters["\\WIDTH"] = wr_width; c->setPort("\\A", sig.extract(wr_offset, wr_width)); c->setPort("\\B", wr_data.extract(wr_offset, wr_width)); @@ -285,13 +296,14 @@ struct MemoryMapWorker sig.replace(wr_offset, w); wr_offset += wr_width; + count_wrmux++; } } module->connect(RTLIL::SigSig(data_reg_in[i], sig)); } - log(" write interface: %d blocks of $eq, $and and $mux cells.\n", count_wrmux); + log(" write interface: %d write mux blocks.\n", count_wrmux); module->remove(cell); } -- cgit v1.2.3 From 2a1b08aeb34b7d5f2df1a43c9ef1f99abacb9cae Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 30 Aug 2014 19:37:12 +0200 Subject: Added design->scratchpad --- passes/opt/opt.cc | 11 ++++------- passes/opt/opt_clean.cc | 7 +++---- passes/opt/opt_const.cc | 20 +++----------------- passes/opt/opt_muxtree.cc | 4 ++-- passes/opt/opt_reduce.cc | 6 ++---- passes/opt/opt_rmdff.cc | 5 +++-- passes/opt/opt_share.cc | 4 ++-- passes/opt/opt_status.h | 26 -------------------------- 8 files changed, 19 insertions(+), 64 deletions(-) delete mode 100644 passes/opt/opt_status.h (limited to 'passes') diff --git a/passes/opt/opt.cc b/passes/opt/opt.cc index b6d36f0e3..b20521d1e 100644 --- a/passes/opt/opt.cc +++ b/passes/opt/opt.cc @@ -17,14 +17,11 @@ * */ -#include "opt_status.h" #include "kernel/register.h" #include "kernel/log.h" #include #include -bool OPT_DID_SOMETHING; - struct OptPass : public Pass { OptPass() : Pass("opt", "perform simple optimizations") { } virtual void help() @@ -113,9 +110,9 @@ struct OptPass : public Pass { while (1) { Pass::call(design, "opt_const" + opt_const_args); Pass::call(design, "opt_share"); - OPT_DID_SOMETHING = false; + design->scratchpad_unset("opt.did_something"); Pass::call(design, "opt_rmdff"); - if (OPT_DID_SOMETHING == false) + if (design->scratchpad_get_bool("opt.did_something") == false) break; Pass::call(design, "opt_clean" + opt_clean_args); log_header("Rerunning OPT passes. (Removed registers in this run.)\n"); @@ -127,14 +124,14 @@ struct OptPass : public Pass { Pass::call(design, "opt_const" + opt_const_args); Pass::call(design, "opt_share -nomux"); while (1) { - OPT_DID_SOMETHING = false; + design->scratchpad_unset("opt.did_something"); Pass::call(design, "opt_muxtree"); Pass::call(design, "opt_reduce" + opt_reduce_args); Pass::call(design, "opt_share"); Pass::call(design, "opt_rmdff"); Pass::call(design, "opt_clean" + opt_clean_args); Pass::call(design, "opt_const" + opt_const_args); - if (OPT_DID_SOMETHING == false) + if (design->scratchpad_get_bool("opt.did_something") == false) break; log_header("Rerunning OPT passes. (Maybe there is more to do..)\n"); } diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index d47e4513e..cc4fe4cc8 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -17,7 +17,6 @@ * */ -#include "opt_status.h" #include "kernel/register.h" #include "kernel/sigtools.h" #include "kernel/log.h" @@ -88,7 +87,7 @@ static void rmunused_module_cells(RTLIL::Module *module, bool verbose) for (auto cell : unused) { if (verbose) log(" removing unused `%s' cell `%s'.\n", cell->type.c_str(), cell->name.c_str()); - OPT_DID_SOMETHING = true; + module->design->scratchpad_set_bool("opt.did_something", true); module->remove(cell); count_rm_cells++; } @@ -406,9 +405,9 @@ struct CleanPass : public Pass { for (auto &mod_it : design->modules_) { if (design->selected_whole_module(mod_it.first) && mod_it.second->processes.size() == 0) do { - OPT_DID_SOMETHING = false; + design->scratchpad_unset("opt.did_something"); rmunused_module(mod_it.second, purge_mode, false); - } while (OPT_DID_SOMETHING); + } while (design->scratchpad_get_bool("opt.did_something")); } if (count_rm_cells > 0 || count_rm_wires > 0) diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index a602cf5fd..ad6961872 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -17,7 +17,6 @@ * */ -#include "opt_status.h" #include "kernel/register.h" #include "kernel/sigtools.h" #include "kernel/celltypes.h" @@ -67,7 +66,7 @@ static void replace_undriven(RTLIL::Design *design, RTLIL::Module *module) log("Setting undriven signal in %s to undef: %s\n", RTLIL::id2cstr(module->name), log_signal(c)); module->connect(RTLIL::SigSig(c, RTLIL::SigSpec(RTLIL::State::Sx, c.width))); - OPT_DID_SOMETHING = true; + did_something = true; } } @@ -83,7 +82,6 @@ static void replace_cell(SigMap &assign_map, RTLIL::Module *module, RTLIL::Cell assign_map.add(Y, out_val); module->connect(Y, out_val); module->remove(cell); - OPT_DID_SOMETHING = true; did_something = true; } @@ -186,7 +184,6 @@ static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool com cover_list("opt.opt_const.fine.group", "$not", "$pos", "$bu0", "$and", "$or", "$xor", "$xnor", cell->type.str()); module->remove(cell); - OPT_DID_SOMETHING = true; did_something = true; return true; } @@ -266,7 +263,6 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a)); cell->setPort("\\A", sig_a = new_a); cell->parameters.at("\\A_WIDTH") = 1; - OPT_DID_SOMETHING = true; did_something = true; } } @@ -293,7 +289,6 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a)); cell->setPort("\\A", sig_a = new_a); cell->parameters.at("\\A_WIDTH") = 1; - OPT_DID_SOMETHING = true; did_something = true; } } @@ -320,7 +315,6 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_b), log_signal(new_b)); cell->setPort("\\B", sig_b = new_b); cell->parameters.at("\\B_WIDTH") = 1; - OPT_DID_SOMETHING = true; did_something = true; } } @@ -385,7 +379,6 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cell->setPort("\\A", cell->getPort("\\B")); cell->setPort("\\B", tmp); cell->setPort("\\S", invert_map.at(assign_map(cell->getPort("\\S")))); - OPT_DID_SOMETHING = true; did_something = true; goto next_cell; } @@ -551,7 +544,6 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cell->parameters.erase("\\B_WIDTH"); cell->parameters.erase("\\B_SIGNED"); cell->unsetPort("\\B"); - OPT_DID_SOMETHING = true; did_something = true; } goto next_cell; @@ -588,7 +580,6 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo module->connect(cell->getPort("\\Y"), sig_y); module->remove(cell); - OPT_DID_SOMETHING = true; did_something = true; goto next_cell; } @@ -661,7 +652,6 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cell->parameters.erase("\\B_SIGNED"); cell->check(); - OPT_DID_SOMETHING = true; did_something = true; goto next_cell; } @@ -689,7 +679,6 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cell->type = "$not"; } else cell->type = "$_NOT_"; - OPT_DID_SOMETHING = true; did_something = true; goto next_cell; } @@ -709,7 +698,6 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cell->type = "$and"; } else cell->type = "$_AND_"; - OPT_DID_SOMETHING = true; did_something = true; goto next_cell; } @@ -729,7 +717,6 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cell->type = "$or"; } else cell->type = "$_OR_"; - OPT_DID_SOMETHING = true; did_something = true; goto next_cell; } @@ -781,7 +768,6 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cell->type = "$mux"; cell->parameters.erase("\\S_WIDTH"); } - OPT_DID_SOMETHING = true; did_something = true; } } @@ -895,7 +881,6 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size()))); module->remove(cell); - OPT_DID_SOMETHING = true; did_something = true; goto next_cell; } @@ -928,7 +913,6 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cell->setPort("\\B", new_b); cell->check(); - OPT_DID_SOMETHING = true; did_something = true; goto next_cell; } @@ -1018,6 +1002,8 @@ struct OptConstPass : public Pass { do { did_something = false; replace_const_cells(design, module, false, mux_undef, mux_bool, do_fine, keepdc); + if (did_something) + design->scratchpad_set_bool("opt.did_something", true); } while (did_something); replace_const_cells(design, module, true, mux_undef, mux_bool, do_fine, keepdc); } while (did_something); diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc index daa063812..2c5dcf668 100644 --- a/passes/opt/opt_muxtree.cc +++ b/passes/opt/opt_muxtree.cc @@ -17,7 +17,6 @@ * */ -#include "opt_status.h" #include "kernel/register.h" #include "kernel/sigtools.h" #include "kernel/log.h" @@ -179,7 +178,6 @@ struct OptMuxtreeWorker } else { log(" dead port %zd/%zd on %s %s.\n", port_idx+1, mi.ports.size(), mi.cell->type.c_str(), mi.cell->name.c_str()); - OPT_DID_SOMETHING = true; removed_count++; } } @@ -434,6 +432,8 @@ struct OptMuxtreePass : public Pass { total_count += worker.removed_count; } } + if (total_count) + design->scratchpad_set_bool("opt.did_something", true); log("Removed %d multiplexer ports.\n", total_count); } } OptMuxtreePass; diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc index e2b4243d1..e9e2bb399 100644 --- a/passes/opt/opt_reduce.cc +++ b/passes/opt/opt_reduce.cc @@ -17,7 +17,6 @@ * */ -#include "opt_status.h" #include "kernel/register.h" #include "kernel/sigtools.h" #include "kernel/log.h" @@ -88,7 +87,6 @@ struct OptReduceWorker if (new_sig_a != sig_a || sig_a.size() != cell->getPort("\\A").size()) { log(" New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a)); did_something = true; - OPT_DID_SOMETHING = true; total_count++; } @@ -141,7 +139,6 @@ struct OptReduceWorker if (new_sig_s.size() != sig_s.size()) { log(" New ctrl vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_s)); did_something = true; - OPT_DID_SOMETHING = true; total_count++; } @@ -238,7 +235,6 @@ struct OptReduceWorker module->check(); did_something = true; - OPT_DID_SOMETHING = true; total_count++; } } @@ -376,6 +372,8 @@ struct OptReducePass : public Pass { } while (1); } + if (total_count) + design->scratchpad_set_bool("opt.did_something", true); log("Performed a total of %d changes.\n", total_count); } } OptReducePass; diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc index bbf94d3b4..48f406f65 100644 --- a/passes/opt/opt_rmdff.cc +++ b/passes/opt/opt_rmdff.cc @@ -17,7 +17,6 @@ * */ -#include "opt_status.h" #include "kernel/register.h" #include "kernel/sigtools.h" #include "kernel/log.h" @@ -142,7 +141,6 @@ static bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) delete_dff: log("Removing %s (%s) from module %s.\n", dff->name.c_str(), dff->type.c_str(), mod->name.c_str()); - OPT_DID_SOMETHING = true; mod->remove(dff); return true; } @@ -210,6 +208,9 @@ struct OptRmdffPass : public Pass { assign_map.clear(); mux_drivers.clear(); + + if (total_count) + design->scratchpad_set_bool("opt.did_something", true); log("Replaced %d DFF cells.\n", total_count); } } OptRmdffPass; diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc index e9a5e7fde..66f5e630c 100644 --- a/passes/opt/opt_share.cc +++ b/passes/opt/opt_share.cc @@ -17,7 +17,6 @@ * */ -#include "opt_status.h" #include "kernel/register.h" #include "kernel/sigtools.h" #include "kernel/log.h" @@ -265,7 +264,6 @@ struct OptShareWorker } log(" Removing %s cell `%s' from module `%s'.\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str()); module->remove(cell); - OPT_DID_SOMETHING = true; total_count++; } else { sharemap[cell] = cell; @@ -315,6 +313,8 @@ struct OptSharePass : public Pass { total_count += worker.total_count; } + if (total_count) + design->scratchpad_set_bool("opt.did_something", true); log("Removed a total of %d cells.\n", total_count); } } OptSharePass; diff --git a/passes/opt/opt_status.h b/passes/opt/opt_status.h deleted file mode 100644 index 3d12baa7d..000000000 --- a/passes/opt/opt_status.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2012 Clifford Wolf - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -#ifndef OPT_STATUS_H -#define OPT_STATUS_H - -extern bool OPT_DID_SOMETHING; - -#endif - -- cgit v1.2.3 From 8649b57b6f4c3a4322acaf73f5c02d5119629c1e Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 31 Aug 2014 17:06:36 +0200 Subject: Added $lut support in test_cell, techmap, satgen --- passes/tests/test_cell.cc | 33 ++++++++++++++++++++++++++++----- 1 file changed, 28 insertions(+), 5 deletions(-) (limited to 'passes') diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index a4b8be0c1..4a2af304d 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -30,20 +30,41 @@ static uint32_t xorshift32(uint32_t limit) { return xorshift32_state % limit; } -static void create_gold_module(RTLIL::Design *design, std::string cell_type, std::string cell_type_flags) +static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type, std::string cell_type_flags) { RTLIL::Module *module = design->addModule("\\gold"); RTLIL::Cell *cell = module->addCell("\\UUT", cell_type); + RTLIL::Wire *wire; + + if (cell_type == "$lut") + { + int width = 1 + xorshift32(6); + + wire = module->addWire("\\A"); + wire->width = width; + wire->port_input = true; + cell->setPort("\\A", wire); + + wire = module->addWire("\\Y"); + wire->port_output = true; + cell->setPort("\\Y", wire); + + RTLIL::SigSpec config; + for (int i = 0; i < (1 << width); i++) + config.append(xorshift32(2) ? RTLIL::S1 : RTLIL::S0); + + cell->setParam("\\LUT", config.as_const()); + } if (cell_type_flags.find('A') != std::string::npos) { - RTLIL::Wire *wire = module->addWire("\\A"); + wire = module->addWire("\\A"); wire->width = 1 + xorshift32(8); wire->port_input = true; cell->setPort("\\A", wire); } if (cell_type_flags.find('B') != std::string::npos) { - RTLIL::Wire *wire = module->addWire("\\B"); + wire = module->addWire("\\B"); if (cell_type_flags.find('h') != std::string::npos) wire->width = 1 + xorshift32(6); else @@ -67,7 +88,7 @@ static void create_gold_module(RTLIL::Design *design, std::string cell_type, std } if (cell_type_flags.find('Y') != std::string::npos) { - RTLIL::Wire *wire = module->addWire("\\Y"); + wire = module->addWire("\\Y"); wire->width = 1 + xorshift32(8); wire->port_output = true; cell->setPort("\\Y", wire); @@ -188,9 +209,11 @@ struct TestCellPass : public Pass { // cell_types["$pmux"] = "A"; // cell_types["$slice"] = "A"; // cell_types["$concat"] = "A"; - // cell_types["$lut"] = "A"; // cell_types["$assert"] = "A"; + cell_types["$lut"] = "*"; + // cell_types["$alu"] = "*"; + for (; argidx < SIZE(args); argidx++) { if (args[argidx].rfind("-", 0) == 0) -- cgit v1.2.3 From e3664066d5684af444c5a1edb02b9e7543cba38d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 31 Aug 2014 18:08:42 +0200 Subject: Added eval testing to test_cell --- passes/tests/test_cell.cc | 88 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 88 insertions(+) (limited to 'passes') diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index 4a2af304d..d9554bcf7 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -19,6 +19,7 @@ */ #include "kernel/yosys.h" +#include "kernel/consteval.h" #include static uint32_t xorshift32_state = 123456789; @@ -99,6 +100,92 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type, cell->check(); } +static void run_eval_test(RTLIL::Design *design) +{ + RTLIL::Module *gold_mod = design->module("\\gold"); + RTLIL::Module *gate_mod = design->module("\\gate"); + ConstEval gold_ce(gold_mod), gate_ce(gate_mod); + + log("Eval testing: "); + + for (int i = 0; i < 64; i++) + { + log("."); + gold_ce.clear(); + gate_ce.clear(); + + for (auto port : gold_mod->ports) + { + RTLIL::Wire *gold_wire = gold_mod->wire(port); + RTLIL::Wire *gate_wire = gate_mod->wire(port); + + log_assert(gold_wire != nullptr); + log_assert(gate_wire != nullptr); + log_assert(gold_wire->port_input == gate_wire->port_input); + log_assert(SIZE(gold_wire) == SIZE(gate_wire)); + + if (!gold_wire->port_input) + continue; + + RTLIL::Const in_value; + for (int i = 0; i < SIZE(gold_wire); i++) + in_value.bits.push_back(xorshift32(2) ? RTLIL::S1 : RTLIL::S0); + + if (xorshift32(4) == 0) { + int inv_chance = 1 + xorshift32(8); + for (int i = 0; i < SIZE(gold_wire); i++) + if (xorshift32(inv_chance) == 0) + in_value.bits[i] = RTLIL::Sx; + } + + // log("%s: %s\n", log_id(gold_wire), log_signal(in_value)); + + gold_ce.set(gold_wire, in_value); + gate_ce.set(gate_wire, in_value); + } + + for (auto port : gold_mod->ports) + { + RTLIL::Wire *gold_wire = gold_mod->wire(port); + RTLIL::Wire *gate_wire = gate_mod->wire(port); + + log_assert(gold_wire != nullptr); + log_assert(gate_wire != nullptr); + log_assert(gold_wire->port_output == gate_wire->port_output); + log_assert(SIZE(gold_wire) == SIZE(gate_wire)); + + if (!gold_wire->port_output) + continue; + + RTLIL::SigSpec gold_outval(gold_wire); + RTLIL::SigSpec gate_outval(gate_wire); + + if (!gold_ce.eval(gold_outval)) + log_error("Failed to eval %s in gold module.\n", log_id(gold_wire)); + + if (!gate_ce.eval(gate_outval)) + log_error("Failed to eval %s in gate module.\n", log_id(gate_wire)); + + bool gold_gate_mismatch = false; + for (int i = 0; i < SIZE(gold_wire); i++) { + if (gold_outval[i] == RTLIL::Sx) + continue; + if (gold_outval[i] == gate_outval[i]) + continue; + gold_gate_mismatch = true; + break; + } + + if (gold_gate_mismatch) + log_error("Mismatch in output %s: gold:%s != gate:%s\n", log_id(gate_wire), log_signal(gold_outval), log_signal(gate_outval)); + + // log("%s: %s\n", log_id(gold_wire), log_signal(gold_outval)); + } + } + + log(" ok.\n"); +} + struct TestCellPass : public Pass { TestCellPass() : Pass("test_cell", "automatically test the implementation of a cell type") { } virtual void help() @@ -265,6 +352,7 @@ struct TestCellPass : public Pass { Pass::call(design, stringf("copy gold gate; %s gate; opt gate", techmap_cmd.c_str())); Pass::call(design, "miter -equiv -flatten -make_outputs -ignore_gold_x gold gate miter; dump gold"); Pass::call(design, "sat -verify -enable_undef -prove trigger 0 -show-inputs -show-outputs miter"); + run_eval_test(design); delete design; } } -- cgit v1.2.3 From e07698818dfe3c8e5f87b13090c7e70d22189e2a Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 1 Sep 2014 11:36:02 +0200 Subject: Using std::vector instead of RTLIL::Const for RTLIL::SigChunk::data --- passes/opt/opt_share.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc index 66f5e630c..4b76a5a2d 100644 --- a/passes/opt/opt_share.cc +++ b/passes/opt/opt_share.cc @@ -101,7 +101,7 @@ struct OptShareWorker int_to_hash_string(chunk.offset) + " " + int_to_hash_string(chunk.width) + "}"; else - hash_string += chunk.data.as_string(); + hash_string += RTLIL::Const(chunk.data).as_string(); } hash_string += "\n"; } -- cgit v1.2.3 From d5148f2e013a7c0e4cced043d0a01a7fb0d3f069 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 1 Sep 2014 11:45:26 +0200 Subject: Moved "share" and "wreduce" to passes/opt/ --- passes/cmds/Makefile.inc | 1 - passes/cmds/wreduce.cc | 353 ----------------- passes/opt/Makefile.inc | 2 + passes/opt/share.cc | 987 +++++++++++++++++++++++++++++++++++++++++++++++ passes/opt/wreduce.cc | 353 +++++++++++++++++ passes/sat/Makefile.inc | 1 - passes/sat/share.cc | 987 ----------------------------------------------- 7 files changed, 1342 insertions(+), 1342 deletions(-) delete mode 100644 passes/cmds/wreduce.cc create mode 100644 passes/opt/share.cc create mode 100644 passes/opt/wreduce.cc delete mode 100644 passes/sat/share.cc (limited to 'passes') diff --git a/passes/cmds/Makefile.inc b/passes/cmds/Makefile.inc index 4cf61150e..eba61d1df 100644 --- a/passes/cmds/Makefile.inc +++ b/passes/cmds/Makefile.inc @@ -20,6 +20,5 @@ OBJS += passes/cmds/write_file.o OBJS += passes/cmds/connwrappers.o OBJS += passes/cmds/cover.o OBJS += passes/cmds/trace.o -OBJS += passes/cmds/wreduce.o OBJS += passes/cmds/plugin.o diff --git a/passes/cmds/wreduce.cc b/passes/cmds/wreduce.cc deleted file mode 100644 index 2269859d1..000000000 --- a/passes/cmds/wreduce.cc +++ /dev/null @@ -1,353 +0,0 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2012 Clifford Wolf - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -#include "kernel/yosys.h" -#include "kernel/sigtools.h" -#include "kernel/modtools.h" - -USING_YOSYS_NAMESPACE -using namespace RTLIL; - -PRIVATE_NAMESPACE_BEGIN - -static inline std::set &operator<<(std::set &set, IdString id) { - set.insert(id); - return set; -} - -struct WreduceConfig -{ - std::set supported_cell_types; - - WreduceConfig() - { - supported_cell_types << "$not" << "$pos" << "$bu0" << "$neg"; - supported_cell_types << "$and" << "$or" << "$xor" << "$xnor"; - supported_cell_types << "$shl" << "$shr" << "$sshl" << "$sshr" << "$shift" << "$shiftx"; - supported_cell_types << "$lt" << "$le" << "$eq" << "$ne" << "$eqx" << "$nex" << "$ge" << "$gt"; - supported_cell_types << "$add" << "$sub"; // << "$mul" << "$div" << "$mod" << "$pow" - supported_cell_types << "$mux" << "$pmux"; - } -}; - -struct WreduceWorker -{ - WreduceConfig *config; - Module *module; - ModIndex mi; - - std::set> work_queue_cells; - std::set work_queue_bits; - - WreduceWorker(WreduceConfig *config, Module *module) : - config(config), module(module), mi(module) { } - - void run_cell_mux(Cell *cell) - { - // Reduce size of MUX if inputs agree on a value for a bit or a output bit is unused - - SigSpec sig_a = mi.sigmap(cell->getPort("\\A")); - SigSpec sig_b = mi.sigmap(cell->getPort("\\B")); - SigSpec sig_s = mi.sigmap(cell->getPort("\\S")); - SigSpec sig_y = mi.sigmap(cell->getPort("\\Y")); - std::vector bits_removed; - - for (int i = SIZE(sig_y)-1; i >= 0; i--) - { - auto info = mi.query(sig_y[i]); - if (!info->is_output && SIZE(info->ports) <= 1) { - bits_removed.push_back(Sx); - continue; - } - - SigBit ref = sig_a[i]; - for (int k = 0; k < SIZE(sig_s); k++) { - if (ref != Sx && sig_b[k*SIZE(sig_a) + i] != Sx && ref != sig_b[k*SIZE(sig_a) + i]) - goto no_match_ab; - if (sig_b[k*SIZE(sig_a) + i] != Sx) - ref = sig_b[k*SIZE(sig_a) + i]; - } - if (0) - no_match_ab: - break; - bits_removed.push_back(ref); - } - - if (bits_removed.empty()) - return; - - SigSpec sig_removed; - for (int i = SIZE(bits_removed)-1; i >= 0; i--) - sig_removed.append_bit(bits_removed[i]); - - if (SIZE(bits_removed) == SIZE(sig_y)) { - log("Removed cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type)); - module->connect(sig_y, sig_removed); - module->remove(cell); - return; - } - - log("Removed top %d bits (of %d) from mux cell %s.%s (%s).\n", - SIZE(sig_removed), SIZE(sig_y), log_id(module), log_id(cell), log_id(cell->type)); - - int n_removed = SIZE(sig_removed); - int n_kept = SIZE(sig_y) - SIZE(sig_removed); - - SigSpec new_work_queue_bits; - new_work_queue_bits.append(sig_a.extract(n_kept, n_removed)); - new_work_queue_bits.append(sig_y.extract(n_kept, n_removed)); - - SigSpec new_sig_a = sig_a.extract(0, n_kept); - SigSpec new_sig_y = sig_y.extract(0, n_kept); - SigSpec new_sig_b; - - for (int k = 0; k < SIZE(sig_s); k++) { - new_sig_b.append(sig_b.extract(k*SIZE(sig_a), n_kept)); - new_work_queue_bits.append(sig_b.extract(k*SIZE(sig_a) + n_kept, n_removed)); - } - - for (auto bit : new_work_queue_bits) - work_queue_bits.insert(bit); - - cell->setPort("\\A", new_sig_a); - cell->setPort("\\B", new_sig_b); - cell->setPort("\\Y", new_sig_y); - cell->fixup_parameters(); - - module->connect(sig_y.extract(n_kept, n_removed), sig_removed); - } - - void run_reduce_inport(Cell *cell, char port, int max_port_size, bool &port_signed, bool &did_something) - { - port_signed = cell->getParam(stringf("\\%c_SIGNED", port)).as_bool(); - SigSpec sig = mi.sigmap(cell->getPort(stringf("\\%c", port))); - - if (port == 'B' && cell->type.in("$shl", "$shr", "$sshl", "$sshr")) - port_signed = false; - - int bits_removed = 0; - if (SIZE(sig) > max_port_size) { - bits_removed = SIZE(sig) - max_port_size; - for (auto bit : sig.extract(max_port_size, bits_removed)) - work_queue_bits.insert(bit); - sig = sig.extract(0, max_port_size); - } - - if (port_signed) { - while (SIZE(sig) > 1 && sig[SIZE(sig)-1] == sig[SIZE(sig)-2]) - work_queue_bits.insert(sig[SIZE(sig)-1]), sig.remove(SIZE(sig)-1), bits_removed++; - } else { - while (SIZE(sig) > 1 && sig[SIZE(sig)-1] == S0) - work_queue_bits.insert(sig[SIZE(sig)-1]), sig.remove(SIZE(sig)-1), bits_removed++; - } - - if (bits_removed) { - log("Removed top %d bits (of %d) from port %c of cell %s.%s (%s).\n", - bits_removed, SIZE(sig) + bits_removed, port, log_id(module), log_id(cell), log_id(cell->type)); - cell->setPort(stringf("\\%c", port), sig); - did_something = true; - } - } - - void run_cell(Cell *cell) - { - bool did_something = false; - - if (!cell->type.in(config->supported_cell_types)) - return; - - if (cell->type.in("$mux", "$pmux")) - return run_cell_mux(cell); - - - // Reduce size of ports A and B based on constant input bits and size of output port - - int max_port_a_size = cell->hasPort("\\A") ? SIZE(cell->getPort("\\A")) : -1; - int max_port_b_size = cell->hasPort("\\B") ? SIZE(cell->getPort("\\B")) : -1; - - if (cell->type.in("$not", "$pos", "$bu0", "$neg", "$and", "$or", "$xor", "$add", "$sub")) { - max_port_a_size = std::min(max_port_a_size, SIZE(cell->getPort("\\Y"))); - max_port_b_size = std::min(max_port_b_size, SIZE(cell->getPort("\\Y"))); - } - - bool port_a_signed = false; - bool port_b_signed = false; - - if (max_port_a_size >= 0) - run_reduce_inport(cell, 'A', max_port_a_size, port_a_signed, did_something); - - if (max_port_b_size >= 0) - run_reduce_inport(cell, 'B', max_port_b_size, port_b_signed, did_something); - - - // Reduce size of port Y based on sizes for A and B and unused bits in Y - - SigSpec sig = mi.sigmap(cell->getPort("\\Y")); - - int bits_removed = 0; - if (port_a_signed && cell->type == "$shr") { - // do not reduce size of output on $shr cells with signed A inputs - } else { - while (SIZE(sig) > 0) - { - auto info = mi.query(sig[SIZE(sig)-1]); - - if (info->is_output || SIZE(info->ports) > 1) - break; - - sig.remove(SIZE(sig)-1); - bits_removed++; - } - } - - if (cell->type.in("$pos", "$bu0", "$add", "$mul", "$and", "$or", "$xor")) - { - bool is_signed = cell->getParam("\\A_SIGNED").as_bool(); - - int a_size = 0, b_size = 0; - if (cell->hasPort("\\A")) a_size = SIZE(cell->getPort("\\A")); - if (cell->hasPort("\\B")) b_size = SIZE(cell->getPort("\\B")); - - int max_y_size = std::max(a_size, b_size); - - if (cell->type == "$add") - max_y_size++; - - if (cell->type == "$mul") - max_y_size = a_size + b_size; - - while (SIZE(sig) > 1 && SIZE(sig) > max_y_size) { - module->connect(sig[SIZE(sig)-1], is_signed ? sig[SIZE(sig)-2] : S0); - sig.remove(SIZE(sig)-1); - bits_removed++; - } - } - - if (SIZE(sig) == 0) { - log("Removed cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type)); - module->remove(cell); - return; - } - - if (bits_removed) { - log("Removed top %d bits (of %d) from port Y of cell %s.%s (%s).\n", - bits_removed, SIZE(sig) + bits_removed, log_id(module), log_id(cell), log_id(cell->type)); - cell->setPort("\\Y", sig); - did_something = true; - } - - if (did_something) { - cell->fixup_parameters(); - run_cell(cell); - } - } - - static int count_nontrivial_wire_attrs(RTLIL::Wire *w) - { - int count = w->attributes.size(); - count -= w->attributes.count("\\src"); - count -= w->attributes.count("\\unused_bits"); - return count; - } - - void run() - { - for (auto c : module->selected_cells()) - work_queue_cells.insert(c); - - while (!work_queue_cells.empty()) - { - work_queue_bits.clear(); - for (auto c : work_queue_cells) - run_cell(c); - - work_queue_cells.clear(); - for (auto bit : work_queue_bits) - for (auto port : mi.query_ports(bit)) - if (module->selected(port.cell)) - work_queue_cells.insert(port.cell); - } - - for (auto w : module->selected_wires()) - { - int unused_top_bits = 0; - - if (w->port_id > 0 || count_nontrivial_wire_attrs(w) > 0) - continue; - - for (int i = SIZE(w)-1; i >= 0; i--) { - SigBit bit(w, i); - auto info = mi.query(bit); - if (info && (info->is_input || info->is_output || SIZE(info->ports) > 0)) - break; - unused_top_bits++; - } - - if (0 < unused_top_bits && unused_top_bits < SIZE(w)) { - log("Removed top %d bits (of %d) from wire %s.%s.\n", unused_top_bits, SIZE(w), log_id(module), log_id(w)); - Wire *nw = module->addWire(NEW_ID, w); - nw->width = SIZE(w) - unused_top_bits; - module->connect(nw, SigSpec(w).extract(0, SIZE(nw))); - module->swap_names(w, nw); - } - } - } -}; - -struct WreducePass : public Pass { - WreducePass() : Pass("wreduce", "reduce the word size of operations is possible") { } - virtual void help() - { - // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| - log("\n"); - log(" wreduce [options] [selection]\n"); - log("\n"); - log("This command reduces the word size of operations. For example it will replace\n"); - log("the 32 bit adders in the following code with adders of more appropriate widths:\n"); - log("\n"); - log(" module test(input [3:0] a, b, c, output [7:0] y);\n"); - log(" assign y = a + b + c + 1;\n"); - log(" endmodule\n"); - log("\n"); - } - virtual void execute(std::vector args, Design *design) - { - WreduceConfig config; - - log_header("Executing WREDUCE pass (reducing word size of cells).\n"); - - size_t argidx; - for (argidx = 1; argidx < args.size(); argidx++) { - break; - } - extra_args(args, argidx, design); - - for (auto module : design->selected_modules()) - { - if (module->has_processes_warn()) - continue; - - WreduceWorker worker(&config, module); - worker.run(); - } - } -} WreducePass; - -PRIVATE_NAMESPACE_END - diff --git a/passes/opt/Makefile.inc b/passes/opt/Makefile.inc index 9dfb32c87..3a8d27f93 100644 --- a/passes/opt/Makefile.inc +++ b/passes/opt/Makefile.inc @@ -6,4 +6,6 @@ OBJS += passes/opt/opt_reduce.o OBJS += passes/opt/opt_rmdff.o OBJS += passes/opt/opt_clean.o OBJS += passes/opt/opt_const.o +OBJS += passes/opt/share.o +OBJS += passes/opt/wreduce.o diff --git a/passes/opt/share.cc b/passes/opt/share.cc new file mode 100644 index 000000000..5f3cf4214 --- /dev/null +++ b/passes/opt/share.cc @@ -0,0 +1,987 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" +#include "kernel/satgen.h" +#include "kernel/sigtools.h" +#include "kernel/modtools.h" + +PRIVATE_NAMESPACE_BEGIN + +struct ShareWorkerConfig +{ + bool opt_force; + bool opt_aggressive; + bool opt_fast; + std::set generic_uni_ops, generic_bin_ops, generic_cbin_ops; +}; + +struct ShareWorker +{ + ShareWorkerConfig config; + std::set generic_ops; + + RTLIL::Design *design; + RTLIL::Module *module; + + CellTypes fwd_ct, cone_ct; + ModWalker modwalker; + + std::set cells_to_remove; + std::set recursion_state; + + + // ------------------------------------------------------------------------------ + // Find terminal bits -- i.e. bits that do not (exclusively) feed into a mux tree + // ------------------------------------------------------------------------------ + + std::set terminal_bits; + + void find_terminal_bits() + { + std::set queue_bits; + std::set visited_cells; + + queue_bits.insert(modwalker.signal_outputs.begin(), modwalker.signal_outputs.end()); + + for (auto &it : module->cells_) + if (!fwd_ct.cell_known(it.second->type)) { + std::set &bits = modwalker.cell_inputs[it.second]; + queue_bits.insert(bits.begin(), bits.end()); + } + + terminal_bits.insert(queue_bits.begin(), queue_bits.end()); + + while (!queue_bits.empty()) + { + std::set portbits; + modwalker.get_drivers(portbits, queue_bits); + queue_bits.clear(); + + for (auto &pbit : portbits) { + if (pbit.cell->type == "$mux" || pbit.cell->type == "$pmux") { + std::set bits = modwalker.sigmap(pbit.cell->getPort("\\S")).to_sigbit_set(); + terminal_bits.insert(bits.begin(), bits.end()); + queue_bits.insert(bits.begin(), bits.end()); + visited_cells.insert(pbit.cell); + } + if (fwd_ct.cell_known(pbit.cell->type) && visited_cells.count(pbit.cell) == 0) { + std::set &bits = modwalker.cell_inputs[pbit.cell]; + terminal_bits.insert(bits.begin(), bits.end()); + queue_bits.insert(bits.begin(), bits.end()); + visited_cells.insert(pbit.cell); + } + } + } + } + + + // --------------------------------------------------- + // Find shareable cells and compatible groups of cells + // --------------------------------------------------- + + std::set shareable_cells; + + void find_shareable_cells() + { + for (auto &it : module->cells_) + { + RTLIL::Cell *cell = it.second; + + if (!design->selected(module, cell) || !modwalker.ct.cell_known(cell->type)) + continue; + + for (auto &bit : modwalker.cell_outputs[cell]) + if (terminal_bits.count(bit)) + goto not_a_muxed_cell; + + if (0) + not_a_muxed_cell: + continue; + + if (config.opt_force) { + shareable_cells.insert(cell); + continue; + } + + if (cell->type == "$memrd") { + if (!cell->parameters.at("\\CLK_ENABLE").as_bool()) + shareable_cells.insert(cell); + continue; + } + + if (cell->type == "$mul" || cell->type == "$div" || cell->type == "$mod") { + if (config.opt_aggressive || cell->parameters.at("\\Y_WIDTH").as_int() >= 4) + shareable_cells.insert(cell); + continue; + } + + if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr") { + if (config.opt_aggressive || cell->parameters.at("\\Y_WIDTH").as_int() >= 8) + shareable_cells.insert(cell); + continue; + } + + if (generic_ops.count(cell->type)) { + if (config.opt_aggressive || cell->parameters.at("\\Y_WIDTH").as_int() >= 10) + shareable_cells.insert(cell); + continue; + } + } + } + + bool is_shareable_pair(RTLIL::Cell *c1, RTLIL::Cell *c2) + { + if (c1->type != c2->type) + return false; + + if (c1->type == "$memrd") + { + if (c1->parameters.at("\\MEMID").decode_string() != c2->parameters.at("\\MEMID").decode_string()) + return false; + + return true; + } + + if (config.generic_uni_ops.count(c1->type)) + { + if (!config.opt_aggressive) + { + int a1_width = c1->parameters.at("\\A_WIDTH").as_int(); + int y1_width = c1->parameters.at("\\Y_WIDTH").as_int(); + + int a2_width = c2->parameters.at("\\A_WIDTH").as_int(); + int y2_width = c2->parameters.at("\\Y_WIDTH").as_int(); + + if (std::max(a1_width, a2_width) > 2 * std::min(a1_width, a2_width)) return false; + if (std::max(y1_width, y2_width) > 2 * std::min(y1_width, y2_width)) return false; + } + + return true; + } + + if (config.generic_bin_ops.count(c1->type)) + { + if (!config.opt_aggressive) + { + int a1_width = c1->parameters.at("\\A_WIDTH").as_int(); + int b1_width = c1->parameters.at("\\B_WIDTH").as_int(); + int y1_width = c1->parameters.at("\\Y_WIDTH").as_int(); + + int a2_width = c2->parameters.at("\\A_WIDTH").as_int(); + int b2_width = c2->parameters.at("\\B_WIDTH").as_int(); + int y2_width = c2->parameters.at("\\Y_WIDTH").as_int(); + + if (std::max(a1_width, a2_width) > 2 * std::min(a1_width, a2_width)) return false; + if (std::max(b1_width, b2_width) > 2 * std::min(b1_width, b2_width)) return false; + if (std::max(y1_width, y2_width) > 2 * std::min(y1_width, y2_width)) return false; + } + + return true; + } + + if (config.generic_cbin_ops.count(c1->type)) + { + if (!config.opt_aggressive) + { + int a1_width = c1->parameters.at("\\A_WIDTH").as_int(); + int b1_width = c1->parameters.at("\\B_WIDTH").as_int(); + int y1_width = c1->parameters.at("\\Y_WIDTH").as_int(); + + int a2_width = c2->parameters.at("\\A_WIDTH").as_int(); + int b2_width = c2->parameters.at("\\B_WIDTH").as_int(); + int y2_width = c2->parameters.at("\\Y_WIDTH").as_int(); + + int min1_width = std::min(a1_width, b1_width); + int max1_width = std::max(a1_width, b1_width); + + int min2_width = std::min(a2_width, b2_width); + int max2_width = std::max(a2_width, b2_width); + + if (std::max(min1_width, min2_width) > 2 * std::min(min1_width, min2_width)) return false; + if (std::max(max1_width, max2_width) > 2 * std::min(max1_width, max2_width)) return false; + if (std::max(y1_width, y2_width) > 2 * std::min(y1_width, y2_width)) return false; + } + + return true; + } + + for (auto &it : c1->parameters) + if (c2->parameters.count(it.first) == 0 || c2->parameters.at(it.first) != it.second) + return false; + + for (auto &it : c2->parameters) + if (c1->parameters.count(it.first) == 0 || c1->parameters.at(it.first) != it.second) + return false; + + return true; + } + + void find_shareable_partners(std::vector &results, RTLIL::Cell *cell) + { + results.clear(); + for (auto c : shareable_cells) + if (c != cell && is_shareable_pair(c, cell)) + results.push_back(c); + } + + + // ----------------------- + // Create replacement cell + // ----------------------- + + RTLIL::Cell *make_supercell(RTLIL::Cell *c1, RTLIL::Cell *c2, RTLIL::SigSpec act) + { + log_assert(c1->type == c2->type); + + if (config.generic_uni_ops.count(c1->type)) + { + if (c1->parameters.at("\\A_SIGNED").as_bool() != c2->parameters.at("\\A_SIGNED").as_bool()) + { + RTLIL::Cell *unsigned_cell = c1->parameters.at("\\A_SIGNED").as_bool() ? c2 : c1; + if (unsigned_cell->getPort("\\A").to_sigbit_vector().back() != RTLIL::State::S0) { + unsigned_cell->parameters.at("\\A_WIDTH") = unsigned_cell->parameters.at("\\A_WIDTH").as_int() + 1; + RTLIL::SigSpec new_a = unsigned_cell->getPort("\\A"); + new_a.append_bit(RTLIL::State::S0); + unsigned_cell->setPort("\\A", new_a); + } + unsigned_cell->parameters.at("\\A_SIGNED") = true; + unsigned_cell->check(); + } + + bool a_signed = c1->parameters.at("\\A_SIGNED").as_bool(); + log_assert(a_signed == c2->parameters.at("\\A_SIGNED").as_bool()); + + RTLIL::SigSpec a1 = c1->getPort("\\A"); + RTLIL::SigSpec y1 = c1->getPort("\\Y"); + + RTLIL::SigSpec a2 = c2->getPort("\\A"); + RTLIL::SigSpec y2 = c2->getPort("\\Y"); + + int a_width = std::max(a1.size(), a2.size()); + int y_width = std::max(y1.size(), y2.size()); + + if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->getPort("\\Y"); + if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->getPort("\\Y"); + + RTLIL::SigSpec a = module->Mux(NEW_ID, a2, a1, act); + RTLIL::Wire *y = module->addWire(NEW_ID, y_width); + + RTLIL::Cell *supercell = module->addCell(NEW_ID, c1->type); + supercell->parameters["\\A_SIGNED"] = a_signed; + supercell->parameters["\\A_WIDTH"] = a_width; + supercell->parameters["\\Y_WIDTH"] = y_width; + supercell->setPort("\\A", a); + supercell->setPort("\\Y", y); + + RTLIL::SigSpec new_y1(y, 0, y1.size()); + RTLIL::SigSpec new_y2(y, 0, y2.size()); + + module->connect(RTLIL::SigSig(y1, new_y1)); + module->connect(RTLIL::SigSig(y2, new_y2)); + + return supercell; + } + + if (config.generic_bin_ops.count(c1->type) || config.generic_cbin_ops.count(c1->type)) + { + bool modified_src_cells = false; + + if (config.generic_cbin_ops.count(c1->type)) + { + int score_unflipped = std::max(c1->parameters.at("\\A_WIDTH").as_int(), c2->parameters.at("\\A_WIDTH").as_int()) + + std::max(c1->parameters.at("\\B_WIDTH").as_int(), c2->parameters.at("\\B_WIDTH").as_int()); + + int score_flipped = std::max(c1->parameters.at("\\A_WIDTH").as_int(), c2->parameters.at("\\B_WIDTH").as_int()) + + std::max(c1->parameters.at("\\B_WIDTH").as_int(), c2->parameters.at("\\A_WIDTH").as_int()); + + if (score_flipped < score_unflipped) + { + RTLIL::SigSpec tmp = c2->getPort("\\A"); + c2->setPort("\\A", c2->getPort("\\B")); + c2->setPort("\\B", tmp); + + std::swap(c2->parameters.at("\\A_WIDTH"), c2->parameters.at("\\B_WIDTH")); + std::swap(c2->parameters.at("\\A_SIGNED"), c2->parameters.at("\\B_SIGNED")); + modified_src_cells = true; + } + } + + if (c1->parameters.at("\\A_SIGNED").as_bool() != c2->parameters.at("\\A_SIGNED").as_bool()) + + { + RTLIL::Cell *unsigned_cell = c1->parameters.at("\\A_SIGNED").as_bool() ? c2 : c1; + if (unsigned_cell->getPort("\\A").to_sigbit_vector().back() != RTLIL::State::S0) { + unsigned_cell->parameters.at("\\A_WIDTH") = unsigned_cell->parameters.at("\\A_WIDTH").as_int() + 1; + RTLIL::SigSpec new_a = unsigned_cell->getPort("\\A"); + new_a.append_bit(RTLIL::State::S0); + unsigned_cell->setPort("\\A", new_a); + } + unsigned_cell->parameters.at("\\A_SIGNED") = true; + modified_src_cells = true; + } + + if (c1->parameters.at("\\B_SIGNED").as_bool() != c2->parameters.at("\\B_SIGNED").as_bool()) + { + RTLIL::Cell *unsigned_cell = c1->parameters.at("\\B_SIGNED").as_bool() ? c2 : c1; + if (unsigned_cell->getPort("\\B").to_sigbit_vector().back() != RTLIL::State::S0) { + unsigned_cell->parameters.at("\\B_WIDTH") = unsigned_cell->parameters.at("\\B_WIDTH").as_int() + 1; + RTLIL::SigSpec new_b = unsigned_cell->getPort("\\B"); + new_b.append_bit(RTLIL::State::S0); + unsigned_cell->setPort("\\B", new_b); + } + unsigned_cell->parameters.at("\\B_SIGNED") = true; + modified_src_cells = true; + } + + if (modified_src_cells) { + c1->check(); + c2->check(); + } + + bool a_signed = c1->parameters.at("\\A_SIGNED").as_bool(); + bool b_signed = c1->parameters.at("\\B_SIGNED").as_bool(); + + log_assert(a_signed == c2->parameters.at("\\A_SIGNED").as_bool()); + log_assert(b_signed == c2->parameters.at("\\B_SIGNED").as_bool()); + + if (c1->type == "$shl" || c1->type == "$shr" || c1->type == "$sshl" || c1->type == "$sshr") + b_signed = false; + + RTLIL::SigSpec a1 = c1->getPort("\\A"); + RTLIL::SigSpec b1 = c1->getPort("\\B"); + RTLIL::SigSpec y1 = c1->getPort("\\Y"); + + RTLIL::SigSpec a2 = c2->getPort("\\A"); + RTLIL::SigSpec b2 = c2->getPort("\\B"); + RTLIL::SigSpec y2 = c2->getPort("\\Y"); + + int a_width = std::max(a1.size(), a2.size()); + int b_width = std::max(b1.size(), b2.size()); + int y_width = std::max(y1.size(), y2.size()); + + if (c1->type == "$shr" && a_signed) + { + a_width = std::max(y_width, a_width); + + if (a1.size() < y1.size()) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, y1.size()), true)->getPort("\\Y"); + if (a2.size() < y2.size()) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, y2.size()), true)->getPort("\\Y"); + + if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), false)->getPort("\\Y"); + if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), false)->getPort("\\Y"); + } + else + { + if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->getPort("\\Y"); + if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->getPort("\\Y"); + } + + if (b1.size() != b_width) b1 = module->addPos(NEW_ID, b1, module->addWire(NEW_ID, b_width), b_signed)->getPort("\\Y"); + if (b2.size() != b_width) b2 = module->addPos(NEW_ID, b2, module->addWire(NEW_ID, b_width), b_signed)->getPort("\\Y"); + + RTLIL::SigSpec a = module->Mux(NEW_ID, a2, a1, act); + RTLIL::SigSpec b = module->Mux(NEW_ID, b2, b1, act); + RTLIL::Wire *y = module->addWire(NEW_ID, y_width); + + RTLIL::Cell *supercell = module->addCell(NEW_ID, c1->type); + supercell->parameters["\\A_SIGNED"] = a_signed; + supercell->parameters["\\B_SIGNED"] = b_signed; + supercell->parameters["\\A_WIDTH"] = a_width; + supercell->parameters["\\B_WIDTH"] = b_width; + supercell->parameters["\\Y_WIDTH"] = y_width; + supercell->setPort("\\A", a); + supercell->setPort("\\B", b); + supercell->setPort("\\Y", y); + supercell->check(); + + RTLIL::SigSpec new_y1(y, 0, y1.size()); + RTLIL::SigSpec new_y2(y, 0, y2.size()); + + module->connect(RTLIL::SigSig(y1, new_y1)); + module->connect(RTLIL::SigSig(y2, new_y2)); + + return supercell; + } + + if (c1->type == "$memrd") + { + RTLIL::Cell *supercell = module->addCell(NEW_ID, c1); + module->connect(c2->getPort("\\DATA"), supercell->getPort("\\DATA")); + return supercell; + } + + log_abort(); + } + + + // ------------------------------------------- + // Finding forbidden control inputs for a cell + // ------------------------------------------- + + std::map> forbidden_controls_cache; + + const std::set &find_forbidden_controls(RTLIL::Cell *cell) + { + if (recursion_state.count(cell)) { + static std::set empty_controls_set; + return empty_controls_set; + } + + if (forbidden_controls_cache.count(cell)) + return forbidden_controls_cache.at(cell); + + std::set pbits; + std::set consumer_cells; + + modwalker.get_consumers(pbits, modwalker.cell_outputs[cell]); + + for (auto &bit : pbits) { + if ((bit.cell->type == "$mux" || bit.cell->type == "$pmux") && bit.port == "\\S") + forbidden_controls_cache[cell].insert(bit.cell->getPort("\\S").extract(bit.offset, 1)); + consumer_cells.insert(bit.cell); + } + + recursion_state.insert(cell); + + for (auto c : consumer_cells) + if (fwd_ct.cell_known(c->type)) { + const std::set &bits = find_forbidden_controls(c); + forbidden_controls_cache[cell].insert(bits.begin(), bits.end()); + } + + log_assert(recursion_state.count(cell)); + recursion_state.erase(cell); + + return forbidden_controls_cache[cell]; + } + + + // -------------------------------------------------------- + // Finding control inputs and activation pattern for a cell + // -------------------------------------------------------- + + std::map>> activation_patterns_cache; + + bool sort_check_activation_pattern(std::pair &p) + { + std::map p_bits; + + std::vector p_first_bits = p.first; + for (int i = 0; i < SIZE(p_first_bits); i++) { + RTLIL::SigBit b = p_first_bits[i]; + RTLIL::State v = p.second.bits[i]; + if (p_bits.count(b) && p_bits.at(b) != v) + return false; + p_bits[b] = v; + } + + p.first = RTLIL::SigSpec(); + p.second.bits.clear(); + + for (auto &it : p_bits) { + p.first.append_bit(it.first); + p.second.bits.push_back(it.second); + } + + return true; + } + + void optimize_activation_patterns(std::set> & /* patterns */) + { + // TODO: Remove patterns that are contained in other patterns + // TODO: Consolidate pairs of patterns that only differ in the value for one signal bit + } + + const std::set> &find_cell_activation_patterns(RTLIL::Cell *cell, const char *indent) + { + if (recursion_state.count(cell)) { + static std::set> empty_patterns_set; + return empty_patterns_set; + } + + if (activation_patterns_cache.count(cell)) + return activation_patterns_cache.at(cell); + + const std::set &cell_out_bits = modwalker.cell_outputs[cell]; + std::set driven_cells, driven_data_muxes; + + for (auto &bit : cell_out_bits) + { + if (terminal_bits.count(bit)) { + // Terminal cells are always active: unconditional activation pattern + activation_patterns_cache[cell].insert(std::pair()); + return activation_patterns_cache.at(cell); + } + for (auto &pbit : modwalker.signal_consumers[bit]) { + log_assert(fwd_ct.cell_known(pbit.cell->type)); + if ((pbit.cell->type == "$mux" || pbit.cell->type == "$pmux") && (pbit.port == "\\A" || pbit.port == "\\B")) + driven_data_muxes.insert(pbit.cell); + else + driven_cells.insert(pbit.cell); + } + } + + recursion_state.insert(cell); + + for (auto c : driven_data_muxes) + { + const std::set> &c_patterns = find_cell_activation_patterns(c, indent); + + bool used_in_a = false; + std::set used_in_b_parts; + + int width = c->parameters.at("\\WIDTH").as_int(); + std::vector sig_a = modwalker.sigmap(c->getPort("\\A")); + std::vector sig_b = modwalker.sigmap(c->getPort("\\B")); + std::vector sig_s = modwalker.sigmap(c->getPort("\\S")); + + for (auto &bit : sig_a) + if (cell_out_bits.count(bit)) + used_in_a = true; + + for (int i = 0; i < SIZE(sig_b); i++) + if (cell_out_bits.count(sig_b[i])) + used_in_b_parts.insert(i / width); + + if (used_in_a) + for (auto p : c_patterns) { + for (int i = 0; i < SIZE(sig_s); i++) + p.first.append_bit(sig_s[i]), p.second.bits.push_back(RTLIL::State::S0); + if (sort_check_activation_pattern(p)) + activation_patterns_cache[cell].insert(p); + } + + for (int idx : used_in_b_parts) + for (auto p : c_patterns) { + p.first.append_bit(sig_s[idx]), p.second.bits.push_back(RTLIL::State::S1); + if (sort_check_activation_pattern(p)) + activation_patterns_cache[cell].insert(p); + } + } + + for (auto c : driven_cells) { + const std::set> &c_patterns = find_cell_activation_patterns(c, indent); + activation_patterns_cache[cell].insert(c_patterns.begin(), c_patterns.end()); + } + + log_assert(recursion_state.count(cell)); + recursion_state.erase(cell); + + optimize_activation_patterns(activation_patterns_cache[cell]); + if (activation_patterns_cache[cell].empty()) { + log("%sFound cell that is never activated: %s\n", indent, log_id(cell)); + RTLIL::SigSpec cell_outputs = modwalker.cell_outputs[cell]; + module->connect(RTLIL::SigSig(cell_outputs, RTLIL::SigSpec(RTLIL::State::Sx, cell_outputs.size()))); + cells_to_remove.insert(cell); + } + + return activation_patterns_cache[cell]; + } + + RTLIL::SigSpec bits_from_activation_patterns(const std::set> &activation_patterns) + { + std::set all_bits; + for (auto &it : activation_patterns) { + std::vector bits = it.first; + all_bits.insert(bits.begin(), bits.end()); + } + + RTLIL::SigSpec signal; + for (auto &bit : all_bits) + signal.append_bit(bit); + + return signal; + } + + void filter_activation_patterns(std::set> &out, + const std::set> &in, const std::set &filter_bits) + { + for (auto &p : in) + { + std::vector p_first = p.first; + std::pair new_p; + + for (int i = 0; i < SIZE(p_first); i++) + if (filter_bits.count(p_first[i]) == 0) { + new_p.first.append_bit(p_first[i]); + new_p.second.bits.push_back(p.second.bits.at(i)); + } + + out.insert(new_p); + } + } + + RTLIL::SigSpec make_cell_activation_logic(const std::set> &activation_patterns) + { + RTLIL::Wire *all_cases_wire = module->addWire(NEW_ID, 0); + for (auto &p : activation_patterns) { + all_cases_wire->width++; + module->addEq(NEW_ID, p.first, p.second, RTLIL::SigSpec(all_cases_wire, all_cases_wire->width - 1)); + } + if (all_cases_wire->width == 1) + return all_cases_wire; + return module->ReduceOr(NEW_ID, all_cases_wire); + } + + + // ------------- + // Setup and run + // ------------- + + ShareWorker(ShareWorkerConfig config, RTLIL::Design *design, RTLIL::Module *module) : + config(config), design(design), module(module) + { + generic_ops.insert(config.generic_uni_ops.begin(), config.generic_uni_ops.end()); + generic_ops.insert(config.generic_bin_ops.begin(), config.generic_bin_ops.end()); + generic_ops.insert(config.generic_cbin_ops.begin(), config.generic_cbin_ops.end()); + + fwd_ct.setup_internals(); + + cone_ct.setup_internals(); + cone_ct.cell_types.erase("$mul"); + cone_ct.cell_types.erase("$mod"); + cone_ct.cell_types.erase("$div"); + cone_ct.cell_types.erase("$pow"); + cone_ct.cell_types.erase("$shl"); + cone_ct.cell_types.erase("$shr"); + cone_ct.cell_types.erase("$sshl"); + cone_ct.cell_types.erase("$sshr"); + + modwalker.setup(design, module); + + find_terminal_bits(); + find_shareable_cells(); + + if (shareable_cells.size() < 2) + return; + + log("Found %d cells in module %s that may be considered for resource sharing.\n", + SIZE(shareable_cells), log_id(module)); + + while (!shareable_cells.empty()) + { + RTLIL::Cell *cell = *shareable_cells.begin(); + shareable_cells.erase(cell); + + log(" Analyzing resource sharing options for %s:\n", log_id(cell)); + + const std::set> &cell_activation_patterns = find_cell_activation_patterns(cell, " "); + RTLIL::SigSpec cell_activation_signals = bits_from_activation_patterns(cell_activation_patterns); + + if (cell_activation_patterns.empty()) { + log(" Cell is never active. Sharing is pointless, we simply remove it.\n"); + cells_to_remove.insert(cell); + continue; + } + + if (cell_activation_patterns.count(std::pair())) { + log(" Cell is always active. Therefore no sharing is possible.\n"); + continue; + } + + log(" Found %d activation_patterns using ctrl signal %s.\n", SIZE(cell_activation_patterns), log_signal(cell_activation_signals)); + + std::vector candidates; + find_shareable_partners(candidates, cell); + + if (candidates.empty()) { + log(" No candidates found.\n"); + continue; + } + + log(" Found %d candidates:", SIZE(candidates)); + for (auto c : candidates) + log(" %s", log_id(c)); + log("\n"); + + for (auto other_cell : candidates) + { + log(" Analyzing resource sharing with %s:\n", log_id(other_cell)); + + const std::set> &other_cell_activation_patterns = find_cell_activation_patterns(other_cell, " "); + RTLIL::SigSpec other_cell_activation_signals = bits_from_activation_patterns(other_cell_activation_patterns); + + if (other_cell_activation_patterns.empty()) { + log(" Cell is never active. Sharing is pointless, we simply remove it.\n"); + shareable_cells.erase(other_cell); + cells_to_remove.insert(other_cell); + continue; + } + + if (other_cell_activation_patterns.count(std::pair())) { + log(" Cell is always active. Therefore no sharing is possible.\n"); + shareable_cells.erase(other_cell); + continue; + } + + log(" Found %d activation_patterns using ctrl signal %s.\n", + SIZE(other_cell_activation_patterns), log_signal(other_cell_activation_signals)); + + const std::set &cell_forbidden_controls = find_forbidden_controls(cell); + const std::set &other_cell_forbidden_controls = find_forbidden_controls(other_cell); + + std::set union_forbidden_controls; + union_forbidden_controls.insert(cell_forbidden_controls.begin(), cell_forbidden_controls.end()); + union_forbidden_controls.insert(other_cell_forbidden_controls.begin(), other_cell_forbidden_controls.end()); + + if (!union_forbidden_controls.empty()) + log(" Forbidden control signals for this pair of cells: %s\n", log_signal(union_forbidden_controls)); + + std::set> filtered_cell_activation_patterns; + std::set> filtered_other_cell_activation_patterns; + + filter_activation_patterns(filtered_cell_activation_patterns, cell_activation_patterns, union_forbidden_controls); + filter_activation_patterns(filtered_other_cell_activation_patterns, other_cell_activation_patterns, union_forbidden_controls); + + optimize_activation_patterns(filtered_cell_activation_patterns); + optimize_activation_patterns(filtered_other_cell_activation_patterns); + + ezDefaultSAT ez; + SatGen satgen(&ez, &modwalker.sigmap); + + std::set sat_cells; + std::set bits_queue; + + std::vector cell_active, other_cell_active; + RTLIL::SigSpec all_ctrl_signals; + + for (auto &p : filtered_cell_activation_patterns) { + log(" Activation pattern for cell %s: %s = %s\n", log_id(cell), log_signal(p.first), log_signal(p.second)); + cell_active.push_back(ez.vec_eq(satgen.importSigSpec(p.first), satgen.importSigSpec(p.second))); + all_ctrl_signals.append(p.first); + } + + for (auto &p : filtered_other_cell_activation_patterns) { + log(" Activation pattern for cell %s: %s = %s\n", log_id(other_cell), log_signal(p.first), log_signal(p.second)); + other_cell_active.push_back(ez.vec_eq(satgen.importSigSpec(p.first), satgen.importSigSpec(p.second))); + all_ctrl_signals.append(p.first); + } + + for (auto &bit : cell_activation_signals.to_sigbit_vector()) + bits_queue.insert(bit); + + for (auto &bit : other_cell_activation_signals.to_sigbit_vector()) + bits_queue.insert(bit); + + while (!bits_queue.empty()) + { + std::set portbits; + modwalker.get_drivers(portbits, bits_queue); + bits_queue.clear(); + + for (auto &pbit : portbits) + if (sat_cells.count(pbit.cell) == 0 && cone_ct.cell_known(pbit.cell->type)) { + if (config.opt_fast && modwalker.cell_outputs[pbit.cell].size() >= 4) + continue; + // log(" Adding cell %s (%s) to SAT problem.\n", log_id(pbit.cell), log_id(pbit.cell->type)); + bits_queue.insert(modwalker.cell_inputs[pbit.cell].begin(), modwalker.cell_inputs[pbit.cell].end()); + satgen.importCell(pbit.cell); + sat_cells.insert(pbit.cell); + } + + if (config.opt_fast && sat_cells.size() > 100) + break; + } + + if (!ez.solve(ez.expression(ez.OpOr, cell_active))) { + log(" According to the SAT solver the cell %s is never active. Sharing is pointless, we simply remove it.\n", log_id(cell)); + cells_to_remove.insert(cell); + break; + } + + if (!ez.solve(ez.expression(ez.OpOr, other_cell_active))) { + log(" According to the SAT solver the cell %s is never active. Sharing is pointless, we simply remove it.\n", log_id(other_cell)); + cells_to_remove.insert(other_cell); + shareable_cells.erase(other_cell); + continue; + } + + ez.non_incremental(); + + all_ctrl_signals.sort_and_unify(); + std::vector sat_model = satgen.importSigSpec(all_ctrl_signals); + std::vector sat_model_values; + + ez.assume(ez.AND(ez.expression(ez.OpOr, cell_active), ez.expression(ez.OpOr, other_cell_active))); + + log(" Size of SAT problem: %d cells, %d variables, %d clauses\n", + SIZE(sat_cells), ez.numCnfVariables(), ez.numCnfClauses()); + + if (ez.solve(sat_model, sat_model_values)) { + log(" According to the SAT solver this pair of cells can not be shared.\n"); + log(" Model from SAT solver: %s = %d'", log_signal(all_ctrl_signals), SIZE(sat_model_values)); + for (int i = SIZE(sat_model_values)-1; i >= 0; i--) + log("%c", sat_model_values[i] ? '1' : '0'); + log("\n"); + continue; + } + + log(" According to the SAT solver this pair of cells can be shared.\n"); + shareable_cells.erase(other_cell); + + int cell_select_score = 0; + int other_cell_select_score = 0; + + for (auto &p : filtered_cell_activation_patterns) + cell_select_score += p.first.size(); + + for (auto &p : filtered_other_cell_activation_patterns) + other_cell_select_score += p.first.size(); + + RTLIL::Cell *supercell; + if (cell_select_score <= other_cell_select_score) { + RTLIL::SigSpec act = make_cell_activation_logic(filtered_cell_activation_patterns); + supercell = make_supercell(cell, other_cell, act); + log(" Activation signal for %s: %s\n", log_id(cell), log_signal(act)); + } else { + RTLIL::SigSpec act = make_cell_activation_logic(filtered_other_cell_activation_patterns); + supercell = make_supercell(other_cell, cell, act); + log(" Activation signal for %s: %s\n", log_id(other_cell), log_signal(act)); + } + + log(" New cell: %s (%s)\n", log_id(supercell), log_id(supercell->type)); + + std::set> supercell_activation_patterns; + supercell_activation_patterns.insert(filtered_cell_activation_patterns.begin(), filtered_cell_activation_patterns.end()); + supercell_activation_patterns.insert(filtered_other_cell_activation_patterns.begin(), filtered_other_cell_activation_patterns.end()); + optimize_activation_patterns(supercell_activation_patterns); + activation_patterns_cache[supercell] = supercell_activation_patterns; + shareable_cells.insert(supercell); + + cells_to_remove.insert(cell); + cells_to_remove.insert(other_cell); + break; + } + } + + if (!cells_to_remove.empty()) { + log("Removing %d cells in module %s:\n", SIZE(cells_to_remove), log_id(module)); + for (auto c : cells_to_remove) { + log(" Removing cell %s (%s).\n", log_id(c), log_id(c->type)); + module->remove(c); + } + } + + log_assert(recursion_state.empty()); + } +}; + +struct SharePass : public Pass { + SharePass() : Pass("share", "perform sat-based resource sharing") { } + virtual void help() + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" share [options] [selection]\n"); + log("\n"); + log("This pass merges shareable resources into a single resource. A SAT solver\n"); + log("is used to determine if two resources are share-able.\n"); + log("\n"); + log(" -force\n"); + log(" Per default the selection of cells that is considered for sharing is\n"); + log(" narrowed using a list of cell types. With this option all selected\n"); + log(" cells are considered for resource sharing.\n"); + log("\n"); + log(" IMPORTANT NOTE: If the -all option is used then no cells with internal\n"); + log(" state must be selected!\n"); + log("\n"); + log(" -aggressive\n"); + log(" Per default some heuristics are used to reduce the number of cells\n"); + log(" considered for resource sharing to only large resources. This options\n"); + log(" turns this heuristics off, resulting in much more cells being considered\n"); + log(" for resource sharing.\n"); + log("\n"); + log(" -fast\n"); + log(" Only consider the simple part of the control logic in SAT solving, resulting\n"); + log(" in much easier SAT problems at the cost of maybe missing some oportunities\n"); + log(" for resource sharing.\n"); + log("\n"); + } + virtual void execute(std::vector args, RTLIL::Design *design) + { + ShareWorkerConfig config; + + config.opt_force = false; + config.opt_aggressive = false; + config.opt_fast = false; + + config.generic_uni_ops.insert("$not"); + // config.generic_uni_ops.insert("$pos"); + // config.generic_uni_ops.insert("$bu0"); + config.generic_uni_ops.insert("$neg"); + + config.generic_cbin_ops.insert("$and"); + config.generic_cbin_ops.insert("$or"); + config.generic_cbin_ops.insert("$xor"); + config.generic_cbin_ops.insert("$xnor"); + + config.generic_bin_ops.insert("$shl"); + config.generic_bin_ops.insert("$shr"); + config.generic_bin_ops.insert("$sshl"); + config.generic_bin_ops.insert("$sshr"); + + config.generic_bin_ops.insert("$lt"); + config.generic_bin_ops.insert("$le"); + config.generic_bin_ops.insert("$eq"); + config.generic_bin_ops.insert("$ne"); + config.generic_bin_ops.insert("$eqx"); + config.generic_bin_ops.insert("$nex"); + config.generic_bin_ops.insert("$ge"); + config.generic_bin_ops.insert("$gt"); + + config.generic_cbin_ops.insert("$add"); + config.generic_cbin_ops.insert("$mul"); + + config.generic_bin_ops.insert("$sub"); + config.generic_bin_ops.insert("$div"); + config.generic_bin_ops.insert("$mod"); + // config.generic_bin_ops.insert("$pow"); + + config.generic_uni_ops.insert("$logic_not"); + config.generic_cbin_ops.insert("$logic_and"); + config.generic_cbin_ops.insert("$logic_or"); + + log_header("Executing SHARE pass (SAT-based resource sharing).\n"); + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) { + if (args[argidx] == "-force") { + config.opt_force = true; + continue; + } + if (args[argidx] == "-aggressive") { + config.opt_aggressive = true; + continue; + } + if (args[argidx] == "-fast") { + config.opt_fast = true; + continue; + } + break; + } + extra_args(args, argidx, design); + + for (auto &mod_it : design->modules_) + if (design->selected(mod_it.second)) + ShareWorker(config, design, mod_it.second); + } +} SharePass; + +PRIVATE_NAMESPACE_END + diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc new file mode 100644 index 000000000..2269859d1 --- /dev/null +++ b/passes/opt/wreduce.cc @@ -0,0 +1,353 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" +#include "kernel/sigtools.h" +#include "kernel/modtools.h" + +USING_YOSYS_NAMESPACE +using namespace RTLIL; + +PRIVATE_NAMESPACE_BEGIN + +static inline std::set &operator<<(std::set &set, IdString id) { + set.insert(id); + return set; +} + +struct WreduceConfig +{ + std::set supported_cell_types; + + WreduceConfig() + { + supported_cell_types << "$not" << "$pos" << "$bu0" << "$neg"; + supported_cell_types << "$and" << "$or" << "$xor" << "$xnor"; + supported_cell_types << "$shl" << "$shr" << "$sshl" << "$sshr" << "$shift" << "$shiftx"; + supported_cell_types << "$lt" << "$le" << "$eq" << "$ne" << "$eqx" << "$nex" << "$ge" << "$gt"; + supported_cell_types << "$add" << "$sub"; // << "$mul" << "$div" << "$mod" << "$pow" + supported_cell_types << "$mux" << "$pmux"; + } +}; + +struct WreduceWorker +{ + WreduceConfig *config; + Module *module; + ModIndex mi; + + std::set> work_queue_cells; + std::set work_queue_bits; + + WreduceWorker(WreduceConfig *config, Module *module) : + config(config), module(module), mi(module) { } + + void run_cell_mux(Cell *cell) + { + // Reduce size of MUX if inputs agree on a value for a bit or a output bit is unused + + SigSpec sig_a = mi.sigmap(cell->getPort("\\A")); + SigSpec sig_b = mi.sigmap(cell->getPort("\\B")); + SigSpec sig_s = mi.sigmap(cell->getPort("\\S")); + SigSpec sig_y = mi.sigmap(cell->getPort("\\Y")); + std::vector bits_removed; + + for (int i = SIZE(sig_y)-1; i >= 0; i--) + { + auto info = mi.query(sig_y[i]); + if (!info->is_output && SIZE(info->ports) <= 1) { + bits_removed.push_back(Sx); + continue; + } + + SigBit ref = sig_a[i]; + for (int k = 0; k < SIZE(sig_s); k++) { + if (ref != Sx && sig_b[k*SIZE(sig_a) + i] != Sx && ref != sig_b[k*SIZE(sig_a) + i]) + goto no_match_ab; + if (sig_b[k*SIZE(sig_a) + i] != Sx) + ref = sig_b[k*SIZE(sig_a) + i]; + } + if (0) + no_match_ab: + break; + bits_removed.push_back(ref); + } + + if (bits_removed.empty()) + return; + + SigSpec sig_removed; + for (int i = SIZE(bits_removed)-1; i >= 0; i--) + sig_removed.append_bit(bits_removed[i]); + + if (SIZE(bits_removed) == SIZE(sig_y)) { + log("Removed cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type)); + module->connect(sig_y, sig_removed); + module->remove(cell); + return; + } + + log("Removed top %d bits (of %d) from mux cell %s.%s (%s).\n", + SIZE(sig_removed), SIZE(sig_y), log_id(module), log_id(cell), log_id(cell->type)); + + int n_removed = SIZE(sig_removed); + int n_kept = SIZE(sig_y) - SIZE(sig_removed); + + SigSpec new_work_queue_bits; + new_work_queue_bits.append(sig_a.extract(n_kept, n_removed)); + new_work_queue_bits.append(sig_y.extract(n_kept, n_removed)); + + SigSpec new_sig_a = sig_a.extract(0, n_kept); + SigSpec new_sig_y = sig_y.extract(0, n_kept); + SigSpec new_sig_b; + + for (int k = 0; k < SIZE(sig_s); k++) { + new_sig_b.append(sig_b.extract(k*SIZE(sig_a), n_kept)); + new_work_queue_bits.append(sig_b.extract(k*SIZE(sig_a) + n_kept, n_removed)); + } + + for (auto bit : new_work_queue_bits) + work_queue_bits.insert(bit); + + cell->setPort("\\A", new_sig_a); + cell->setPort("\\B", new_sig_b); + cell->setPort("\\Y", new_sig_y); + cell->fixup_parameters(); + + module->connect(sig_y.extract(n_kept, n_removed), sig_removed); + } + + void run_reduce_inport(Cell *cell, char port, int max_port_size, bool &port_signed, bool &did_something) + { + port_signed = cell->getParam(stringf("\\%c_SIGNED", port)).as_bool(); + SigSpec sig = mi.sigmap(cell->getPort(stringf("\\%c", port))); + + if (port == 'B' && cell->type.in("$shl", "$shr", "$sshl", "$sshr")) + port_signed = false; + + int bits_removed = 0; + if (SIZE(sig) > max_port_size) { + bits_removed = SIZE(sig) - max_port_size; + for (auto bit : sig.extract(max_port_size, bits_removed)) + work_queue_bits.insert(bit); + sig = sig.extract(0, max_port_size); + } + + if (port_signed) { + while (SIZE(sig) > 1 && sig[SIZE(sig)-1] == sig[SIZE(sig)-2]) + work_queue_bits.insert(sig[SIZE(sig)-1]), sig.remove(SIZE(sig)-1), bits_removed++; + } else { + while (SIZE(sig) > 1 && sig[SIZE(sig)-1] == S0) + work_queue_bits.insert(sig[SIZE(sig)-1]), sig.remove(SIZE(sig)-1), bits_removed++; + } + + if (bits_removed) { + log("Removed top %d bits (of %d) from port %c of cell %s.%s (%s).\n", + bits_removed, SIZE(sig) + bits_removed, port, log_id(module), log_id(cell), log_id(cell->type)); + cell->setPort(stringf("\\%c", port), sig); + did_something = true; + } + } + + void run_cell(Cell *cell) + { + bool did_something = false; + + if (!cell->type.in(config->supported_cell_types)) + return; + + if (cell->type.in("$mux", "$pmux")) + return run_cell_mux(cell); + + + // Reduce size of ports A and B based on constant input bits and size of output port + + int max_port_a_size = cell->hasPort("\\A") ? SIZE(cell->getPort("\\A")) : -1; + int max_port_b_size = cell->hasPort("\\B") ? SIZE(cell->getPort("\\B")) : -1; + + if (cell->type.in("$not", "$pos", "$bu0", "$neg", "$and", "$or", "$xor", "$add", "$sub")) { + max_port_a_size = std::min(max_port_a_size, SIZE(cell->getPort("\\Y"))); + max_port_b_size = std::min(max_port_b_size, SIZE(cell->getPort("\\Y"))); + } + + bool port_a_signed = false; + bool port_b_signed = false; + + if (max_port_a_size >= 0) + run_reduce_inport(cell, 'A', max_port_a_size, port_a_signed, did_something); + + if (max_port_b_size >= 0) + run_reduce_inport(cell, 'B', max_port_b_size, port_b_signed, did_something); + + + // Reduce size of port Y based on sizes for A and B and unused bits in Y + + SigSpec sig = mi.sigmap(cell->getPort("\\Y")); + + int bits_removed = 0; + if (port_a_signed && cell->type == "$shr") { + // do not reduce size of output on $shr cells with signed A inputs + } else { + while (SIZE(sig) > 0) + { + auto info = mi.query(sig[SIZE(sig)-1]); + + if (info->is_output || SIZE(info->ports) > 1) + break; + + sig.remove(SIZE(sig)-1); + bits_removed++; + } + } + + if (cell->type.in("$pos", "$bu0", "$add", "$mul", "$and", "$or", "$xor")) + { + bool is_signed = cell->getParam("\\A_SIGNED").as_bool(); + + int a_size = 0, b_size = 0; + if (cell->hasPort("\\A")) a_size = SIZE(cell->getPort("\\A")); + if (cell->hasPort("\\B")) b_size = SIZE(cell->getPort("\\B")); + + int max_y_size = std::max(a_size, b_size); + + if (cell->type == "$add") + max_y_size++; + + if (cell->type == "$mul") + max_y_size = a_size + b_size; + + while (SIZE(sig) > 1 && SIZE(sig) > max_y_size) { + module->connect(sig[SIZE(sig)-1], is_signed ? sig[SIZE(sig)-2] : S0); + sig.remove(SIZE(sig)-1); + bits_removed++; + } + } + + if (SIZE(sig) == 0) { + log("Removed cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type)); + module->remove(cell); + return; + } + + if (bits_removed) { + log("Removed top %d bits (of %d) from port Y of cell %s.%s (%s).\n", + bits_removed, SIZE(sig) + bits_removed, log_id(module), log_id(cell), log_id(cell->type)); + cell->setPort("\\Y", sig); + did_something = true; + } + + if (did_something) { + cell->fixup_parameters(); + run_cell(cell); + } + } + + static int count_nontrivial_wire_attrs(RTLIL::Wire *w) + { + int count = w->attributes.size(); + count -= w->attributes.count("\\src"); + count -= w->attributes.count("\\unused_bits"); + return count; + } + + void run() + { + for (auto c : module->selected_cells()) + work_queue_cells.insert(c); + + while (!work_queue_cells.empty()) + { + work_queue_bits.clear(); + for (auto c : work_queue_cells) + run_cell(c); + + work_queue_cells.clear(); + for (auto bit : work_queue_bits) + for (auto port : mi.query_ports(bit)) + if (module->selected(port.cell)) + work_queue_cells.insert(port.cell); + } + + for (auto w : module->selected_wires()) + { + int unused_top_bits = 0; + + if (w->port_id > 0 || count_nontrivial_wire_attrs(w) > 0) + continue; + + for (int i = SIZE(w)-1; i >= 0; i--) { + SigBit bit(w, i); + auto info = mi.query(bit); + if (info && (info->is_input || info->is_output || SIZE(info->ports) > 0)) + break; + unused_top_bits++; + } + + if (0 < unused_top_bits && unused_top_bits < SIZE(w)) { + log("Removed top %d bits (of %d) from wire %s.%s.\n", unused_top_bits, SIZE(w), log_id(module), log_id(w)); + Wire *nw = module->addWire(NEW_ID, w); + nw->width = SIZE(w) - unused_top_bits; + module->connect(nw, SigSpec(w).extract(0, SIZE(nw))); + module->swap_names(w, nw); + } + } + } +}; + +struct WreducePass : public Pass { + WreducePass() : Pass("wreduce", "reduce the word size of operations is possible") { } + virtual void help() + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" wreduce [options] [selection]\n"); + log("\n"); + log("This command reduces the word size of operations. For example it will replace\n"); + log("the 32 bit adders in the following code with adders of more appropriate widths:\n"); + log("\n"); + log(" module test(input [3:0] a, b, c, output [7:0] y);\n"); + log(" assign y = a + b + c + 1;\n"); + log(" endmodule\n"); + log("\n"); + } + virtual void execute(std::vector args, Design *design) + { + WreduceConfig config; + + log_header("Executing WREDUCE pass (reducing word size of cells).\n"); + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) { + break; + } + extra_args(args, argidx, design); + + for (auto module : design->selected_modules()) + { + if (module->has_processes_warn()) + continue; + + WreduceWorker worker(&config, module); + worker.run(); + } + } +} WreducePass; + +PRIVATE_NAMESPACE_END + diff --git a/passes/sat/Makefile.inc b/passes/sat/Makefile.inc index 9aa806429..4fa6bf0d4 100644 --- a/passes/sat/Makefile.inc +++ b/passes/sat/Makefile.inc @@ -4,5 +4,4 @@ OBJS += passes/sat/freduce.o OBJS += passes/sat/eval.o OBJS += passes/sat/miter.o OBJS += passes/sat/expose.o -OBJS += passes/sat/share.o diff --git a/passes/sat/share.cc b/passes/sat/share.cc deleted file mode 100644 index 5f3cf4214..000000000 --- a/passes/sat/share.cc +++ /dev/null @@ -1,987 +0,0 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2012 Clifford Wolf - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -#include "kernel/yosys.h" -#include "kernel/satgen.h" -#include "kernel/sigtools.h" -#include "kernel/modtools.h" - -PRIVATE_NAMESPACE_BEGIN - -struct ShareWorkerConfig -{ - bool opt_force; - bool opt_aggressive; - bool opt_fast; - std::set generic_uni_ops, generic_bin_ops, generic_cbin_ops; -}; - -struct ShareWorker -{ - ShareWorkerConfig config; - std::set generic_ops; - - RTLIL::Design *design; - RTLIL::Module *module; - - CellTypes fwd_ct, cone_ct; - ModWalker modwalker; - - std::set cells_to_remove; - std::set recursion_state; - - - // ------------------------------------------------------------------------------ - // Find terminal bits -- i.e. bits that do not (exclusively) feed into a mux tree - // ------------------------------------------------------------------------------ - - std::set terminal_bits; - - void find_terminal_bits() - { - std::set queue_bits; - std::set visited_cells; - - queue_bits.insert(modwalker.signal_outputs.begin(), modwalker.signal_outputs.end()); - - for (auto &it : module->cells_) - if (!fwd_ct.cell_known(it.second->type)) { - std::set &bits = modwalker.cell_inputs[it.second]; - queue_bits.insert(bits.begin(), bits.end()); - } - - terminal_bits.insert(queue_bits.begin(), queue_bits.end()); - - while (!queue_bits.empty()) - { - std::set portbits; - modwalker.get_drivers(portbits, queue_bits); - queue_bits.clear(); - - for (auto &pbit : portbits) { - if (pbit.cell->type == "$mux" || pbit.cell->type == "$pmux") { - std::set bits = modwalker.sigmap(pbit.cell->getPort("\\S")).to_sigbit_set(); - terminal_bits.insert(bits.begin(), bits.end()); - queue_bits.insert(bits.begin(), bits.end()); - visited_cells.insert(pbit.cell); - } - if (fwd_ct.cell_known(pbit.cell->type) && visited_cells.count(pbit.cell) == 0) { - std::set &bits = modwalker.cell_inputs[pbit.cell]; - terminal_bits.insert(bits.begin(), bits.end()); - queue_bits.insert(bits.begin(), bits.end()); - visited_cells.insert(pbit.cell); - } - } - } - } - - - // --------------------------------------------------- - // Find shareable cells and compatible groups of cells - // --------------------------------------------------- - - std::set shareable_cells; - - void find_shareable_cells() - { - for (auto &it : module->cells_) - { - RTLIL::Cell *cell = it.second; - - if (!design->selected(module, cell) || !modwalker.ct.cell_known(cell->type)) - continue; - - for (auto &bit : modwalker.cell_outputs[cell]) - if (terminal_bits.count(bit)) - goto not_a_muxed_cell; - - if (0) - not_a_muxed_cell: - continue; - - if (config.opt_force) { - shareable_cells.insert(cell); - continue; - } - - if (cell->type == "$memrd") { - if (!cell->parameters.at("\\CLK_ENABLE").as_bool()) - shareable_cells.insert(cell); - continue; - } - - if (cell->type == "$mul" || cell->type == "$div" || cell->type == "$mod") { - if (config.opt_aggressive || cell->parameters.at("\\Y_WIDTH").as_int() >= 4) - shareable_cells.insert(cell); - continue; - } - - if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr") { - if (config.opt_aggressive || cell->parameters.at("\\Y_WIDTH").as_int() >= 8) - shareable_cells.insert(cell); - continue; - } - - if (generic_ops.count(cell->type)) { - if (config.opt_aggressive || cell->parameters.at("\\Y_WIDTH").as_int() >= 10) - shareable_cells.insert(cell); - continue; - } - } - } - - bool is_shareable_pair(RTLIL::Cell *c1, RTLIL::Cell *c2) - { - if (c1->type != c2->type) - return false; - - if (c1->type == "$memrd") - { - if (c1->parameters.at("\\MEMID").decode_string() != c2->parameters.at("\\MEMID").decode_string()) - return false; - - return true; - } - - if (config.generic_uni_ops.count(c1->type)) - { - if (!config.opt_aggressive) - { - int a1_width = c1->parameters.at("\\A_WIDTH").as_int(); - int y1_width = c1->parameters.at("\\Y_WIDTH").as_int(); - - int a2_width = c2->parameters.at("\\A_WIDTH").as_int(); - int y2_width = c2->parameters.at("\\Y_WIDTH").as_int(); - - if (std::max(a1_width, a2_width) > 2 * std::min(a1_width, a2_width)) return false; - if (std::max(y1_width, y2_width) > 2 * std::min(y1_width, y2_width)) return false; - } - - return true; - } - - if (config.generic_bin_ops.count(c1->type)) - { - if (!config.opt_aggressive) - { - int a1_width = c1->parameters.at("\\A_WIDTH").as_int(); - int b1_width = c1->parameters.at("\\B_WIDTH").as_int(); - int y1_width = c1->parameters.at("\\Y_WIDTH").as_int(); - - int a2_width = c2->parameters.at("\\A_WIDTH").as_int(); - int b2_width = c2->parameters.at("\\B_WIDTH").as_int(); - int y2_width = c2->parameters.at("\\Y_WIDTH").as_int(); - - if (std::max(a1_width, a2_width) > 2 * std::min(a1_width, a2_width)) return false; - if (std::max(b1_width, b2_width) > 2 * std::min(b1_width, b2_width)) return false; - if (std::max(y1_width, y2_width) > 2 * std::min(y1_width, y2_width)) return false; - } - - return true; - } - - if (config.generic_cbin_ops.count(c1->type)) - { - if (!config.opt_aggressive) - { - int a1_width = c1->parameters.at("\\A_WIDTH").as_int(); - int b1_width = c1->parameters.at("\\B_WIDTH").as_int(); - int y1_width = c1->parameters.at("\\Y_WIDTH").as_int(); - - int a2_width = c2->parameters.at("\\A_WIDTH").as_int(); - int b2_width = c2->parameters.at("\\B_WIDTH").as_int(); - int y2_width = c2->parameters.at("\\Y_WIDTH").as_int(); - - int min1_width = std::min(a1_width, b1_width); - int max1_width = std::max(a1_width, b1_width); - - int min2_width = std::min(a2_width, b2_width); - int max2_width = std::max(a2_width, b2_width); - - if (std::max(min1_width, min2_width) > 2 * std::min(min1_width, min2_width)) return false; - if (std::max(max1_width, max2_width) > 2 * std::min(max1_width, max2_width)) return false; - if (std::max(y1_width, y2_width) > 2 * std::min(y1_width, y2_width)) return false; - } - - return true; - } - - for (auto &it : c1->parameters) - if (c2->parameters.count(it.first) == 0 || c2->parameters.at(it.first) != it.second) - return false; - - for (auto &it : c2->parameters) - if (c1->parameters.count(it.first) == 0 || c1->parameters.at(it.first) != it.second) - return false; - - return true; - } - - void find_shareable_partners(std::vector &results, RTLIL::Cell *cell) - { - results.clear(); - for (auto c : shareable_cells) - if (c != cell && is_shareable_pair(c, cell)) - results.push_back(c); - } - - - // ----------------------- - // Create replacement cell - // ----------------------- - - RTLIL::Cell *make_supercell(RTLIL::Cell *c1, RTLIL::Cell *c2, RTLIL::SigSpec act) - { - log_assert(c1->type == c2->type); - - if (config.generic_uni_ops.count(c1->type)) - { - if (c1->parameters.at("\\A_SIGNED").as_bool() != c2->parameters.at("\\A_SIGNED").as_bool()) - { - RTLIL::Cell *unsigned_cell = c1->parameters.at("\\A_SIGNED").as_bool() ? c2 : c1; - if (unsigned_cell->getPort("\\A").to_sigbit_vector().back() != RTLIL::State::S0) { - unsigned_cell->parameters.at("\\A_WIDTH") = unsigned_cell->parameters.at("\\A_WIDTH").as_int() + 1; - RTLIL::SigSpec new_a = unsigned_cell->getPort("\\A"); - new_a.append_bit(RTLIL::State::S0); - unsigned_cell->setPort("\\A", new_a); - } - unsigned_cell->parameters.at("\\A_SIGNED") = true; - unsigned_cell->check(); - } - - bool a_signed = c1->parameters.at("\\A_SIGNED").as_bool(); - log_assert(a_signed == c2->parameters.at("\\A_SIGNED").as_bool()); - - RTLIL::SigSpec a1 = c1->getPort("\\A"); - RTLIL::SigSpec y1 = c1->getPort("\\Y"); - - RTLIL::SigSpec a2 = c2->getPort("\\A"); - RTLIL::SigSpec y2 = c2->getPort("\\Y"); - - int a_width = std::max(a1.size(), a2.size()); - int y_width = std::max(y1.size(), y2.size()); - - if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->getPort("\\Y"); - if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->getPort("\\Y"); - - RTLIL::SigSpec a = module->Mux(NEW_ID, a2, a1, act); - RTLIL::Wire *y = module->addWire(NEW_ID, y_width); - - RTLIL::Cell *supercell = module->addCell(NEW_ID, c1->type); - supercell->parameters["\\A_SIGNED"] = a_signed; - supercell->parameters["\\A_WIDTH"] = a_width; - supercell->parameters["\\Y_WIDTH"] = y_width; - supercell->setPort("\\A", a); - supercell->setPort("\\Y", y); - - RTLIL::SigSpec new_y1(y, 0, y1.size()); - RTLIL::SigSpec new_y2(y, 0, y2.size()); - - module->connect(RTLIL::SigSig(y1, new_y1)); - module->connect(RTLIL::SigSig(y2, new_y2)); - - return supercell; - } - - if (config.generic_bin_ops.count(c1->type) || config.generic_cbin_ops.count(c1->type)) - { - bool modified_src_cells = false; - - if (config.generic_cbin_ops.count(c1->type)) - { - int score_unflipped = std::max(c1->parameters.at("\\A_WIDTH").as_int(), c2->parameters.at("\\A_WIDTH").as_int()) + - std::max(c1->parameters.at("\\B_WIDTH").as_int(), c2->parameters.at("\\B_WIDTH").as_int()); - - int score_flipped = std::max(c1->parameters.at("\\A_WIDTH").as_int(), c2->parameters.at("\\B_WIDTH").as_int()) + - std::max(c1->parameters.at("\\B_WIDTH").as_int(), c2->parameters.at("\\A_WIDTH").as_int()); - - if (score_flipped < score_unflipped) - { - RTLIL::SigSpec tmp = c2->getPort("\\A"); - c2->setPort("\\A", c2->getPort("\\B")); - c2->setPort("\\B", tmp); - - std::swap(c2->parameters.at("\\A_WIDTH"), c2->parameters.at("\\B_WIDTH")); - std::swap(c2->parameters.at("\\A_SIGNED"), c2->parameters.at("\\B_SIGNED")); - modified_src_cells = true; - } - } - - if (c1->parameters.at("\\A_SIGNED").as_bool() != c2->parameters.at("\\A_SIGNED").as_bool()) - - { - RTLIL::Cell *unsigned_cell = c1->parameters.at("\\A_SIGNED").as_bool() ? c2 : c1; - if (unsigned_cell->getPort("\\A").to_sigbit_vector().back() != RTLIL::State::S0) { - unsigned_cell->parameters.at("\\A_WIDTH") = unsigned_cell->parameters.at("\\A_WIDTH").as_int() + 1; - RTLIL::SigSpec new_a = unsigned_cell->getPort("\\A"); - new_a.append_bit(RTLIL::State::S0); - unsigned_cell->setPort("\\A", new_a); - } - unsigned_cell->parameters.at("\\A_SIGNED") = true; - modified_src_cells = true; - } - - if (c1->parameters.at("\\B_SIGNED").as_bool() != c2->parameters.at("\\B_SIGNED").as_bool()) - { - RTLIL::Cell *unsigned_cell = c1->parameters.at("\\B_SIGNED").as_bool() ? c2 : c1; - if (unsigned_cell->getPort("\\B").to_sigbit_vector().back() != RTLIL::State::S0) { - unsigned_cell->parameters.at("\\B_WIDTH") = unsigned_cell->parameters.at("\\B_WIDTH").as_int() + 1; - RTLIL::SigSpec new_b = unsigned_cell->getPort("\\B"); - new_b.append_bit(RTLIL::State::S0); - unsigned_cell->setPort("\\B", new_b); - } - unsigned_cell->parameters.at("\\B_SIGNED") = true; - modified_src_cells = true; - } - - if (modified_src_cells) { - c1->check(); - c2->check(); - } - - bool a_signed = c1->parameters.at("\\A_SIGNED").as_bool(); - bool b_signed = c1->parameters.at("\\B_SIGNED").as_bool(); - - log_assert(a_signed == c2->parameters.at("\\A_SIGNED").as_bool()); - log_assert(b_signed == c2->parameters.at("\\B_SIGNED").as_bool()); - - if (c1->type == "$shl" || c1->type == "$shr" || c1->type == "$sshl" || c1->type == "$sshr") - b_signed = false; - - RTLIL::SigSpec a1 = c1->getPort("\\A"); - RTLIL::SigSpec b1 = c1->getPort("\\B"); - RTLIL::SigSpec y1 = c1->getPort("\\Y"); - - RTLIL::SigSpec a2 = c2->getPort("\\A"); - RTLIL::SigSpec b2 = c2->getPort("\\B"); - RTLIL::SigSpec y2 = c2->getPort("\\Y"); - - int a_width = std::max(a1.size(), a2.size()); - int b_width = std::max(b1.size(), b2.size()); - int y_width = std::max(y1.size(), y2.size()); - - if (c1->type == "$shr" && a_signed) - { - a_width = std::max(y_width, a_width); - - if (a1.size() < y1.size()) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, y1.size()), true)->getPort("\\Y"); - if (a2.size() < y2.size()) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, y2.size()), true)->getPort("\\Y"); - - if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), false)->getPort("\\Y"); - if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), false)->getPort("\\Y"); - } - else - { - if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->getPort("\\Y"); - if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->getPort("\\Y"); - } - - if (b1.size() != b_width) b1 = module->addPos(NEW_ID, b1, module->addWire(NEW_ID, b_width), b_signed)->getPort("\\Y"); - if (b2.size() != b_width) b2 = module->addPos(NEW_ID, b2, module->addWire(NEW_ID, b_width), b_signed)->getPort("\\Y"); - - RTLIL::SigSpec a = module->Mux(NEW_ID, a2, a1, act); - RTLIL::SigSpec b = module->Mux(NEW_ID, b2, b1, act); - RTLIL::Wire *y = module->addWire(NEW_ID, y_width); - - RTLIL::Cell *supercell = module->addCell(NEW_ID, c1->type); - supercell->parameters["\\A_SIGNED"] = a_signed; - supercell->parameters["\\B_SIGNED"] = b_signed; - supercell->parameters["\\A_WIDTH"] = a_width; - supercell->parameters["\\B_WIDTH"] = b_width; - supercell->parameters["\\Y_WIDTH"] = y_width; - supercell->setPort("\\A", a); - supercell->setPort("\\B", b); - supercell->setPort("\\Y", y); - supercell->check(); - - RTLIL::SigSpec new_y1(y, 0, y1.size()); - RTLIL::SigSpec new_y2(y, 0, y2.size()); - - module->connect(RTLIL::SigSig(y1, new_y1)); - module->connect(RTLIL::SigSig(y2, new_y2)); - - return supercell; - } - - if (c1->type == "$memrd") - { - RTLIL::Cell *supercell = module->addCell(NEW_ID, c1); - module->connect(c2->getPort("\\DATA"), supercell->getPort("\\DATA")); - return supercell; - } - - log_abort(); - } - - - // ------------------------------------------- - // Finding forbidden control inputs for a cell - // ------------------------------------------- - - std::map> forbidden_controls_cache; - - const std::set &find_forbidden_controls(RTLIL::Cell *cell) - { - if (recursion_state.count(cell)) { - static std::set empty_controls_set; - return empty_controls_set; - } - - if (forbidden_controls_cache.count(cell)) - return forbidden_controls_cache.at(cell); - - std::set pbits; - std::set consumer_cells; - - modwalker.get_consumers(pbits, modwalker.cell_outputs[cell]); - - for (auto &bit : pbits) { - if ((bit.cell->type == "$mux" || bit.cell->type == "$pmux") && bit.port == "\\S") - forbidden_controls_cache[cell].insert(bit.cell->getPort("\\S").extract(bit.offset, 1)); - consumer_cells.insert(bit.cell); - } - - recursion_state.insert(cell); - - for (auto c : consumer_cells) - if (fwd_ct.cell_known(c->type)) { - const std::set &bits = find_forbidden_controls(c); - forbidden_controls_cache[cell].insert(bits.begin(), bits.end()); - } - - log_assert(recursion_state.count(cell)); - recursion_state.erase(cell); - - return forbidden_controls_cache[cell]; - } - - - // -------------------------------------------------------- - // Finding control inputs and activation pattern for a cell - // -------------------------------------------------------- - - std::map>> activation_patterns_cache; - - bool sort_check_activation_pattern(std::pair &p) - { - std::map p_bits; - - std::vector p_first_bits = p.first; - for (int i = 0; i < SIZE(p_first_bits); i++) { - RTLIL::SigBit b = p_first_bits[i]; - RTLIL::State v = p.second.bits[i]; - if (p_bits.count(b) && p_bits.at(b) != v) - return false; - p_bits[b] = v; - } - - p.first = RTLIL::SigSpec(); - p.second.bits.clear(); - - for (auto &it : p_bits) { - p.first.append_bit(it.first); - p.second.bits.push_back(it.second); - } - - return true; - } - - void optimize_activation_patterns(std::set> & /* patterns */) - { - // TODO: Remove patterns that are contained in other patterns - // TODO: Consolidate pairs of patterns that only differ in the value for one signal bit - } - - const std::set> &find_cell_activation_patterns(RTLIL::Cell *cell, const char *indent) - { - if (recursion_state.count(cell)) { - static std::set> empty_patterns_set; - return empty_patterns_set; - } - - if (activation_patterns_cache.count(cell)) - return activation_patterns_cache.at(cell); - - const std::set &cell_out_bits = modwalker.cell_outputs[cell]; - std::set driven_cells, driven_data_muxes; - - for (auto &bit : cell_out_bits) - { - if (terminal_bits.count(bit)) { - // Terminal cells are always active: unconditional activation pattern - activation_patterns_cache[cell].insert(std::pair()); - return activation_patterns_cache.at(cell); - } - for (auto &pbit : modwalker.signal_consumers[bit]) { - log_assert(fwd_ct.cell_known(pbit.cell->type)); - if ((pbit.cell->type == "$mux" || pbit.cell->type == "$pmux") && (pbit.port == "\\A" || pbit.port == "\\B")) - driven_data_muxes.insert(pbit.cell); - else - driven_cells.insert(pbit.cell); - } - } - - recursion_state.insert(cell); - - for (auto c : driven_data_muxes) - { - const std::set> &c_patterns = find_cell_activation_patterns(c, indent); - - bool used_in_a = false; - std::set used_in_b_parts; - - int width = c->parameters.at("\\WIDTH").as_int(); - std::vector sig_a = modwalker.sigmap(c->getPort("\\A")); - std::vector sig_b = modwalker.sigmap(c->getPort("\\B")); - std::vector sig_s = modwalker.sigmap(c->getPort("\\S")); - - for (auto &bit : sig_a) - if (cell_out_bits.count(bit)) - used_in_a = true; - - for (int i = 0; i < SIZE(sig_b); i++) - if (cell_out_bits.count(sig_b[i])) - used_in_b_parts.insert(i / width); - - if (used_in_a) - for (auto p : c_patterns) { - for (int i = 0; i < SIZE(sig_s); i++) - p.first.append_bit(sig_s[i]), p.second.bits.push_back(RTLIL::State::S0); - if (sort_check_activation_pattern(p)) - activation_patterns_cache[cell].insert(p); - } - - for (int idx : used_in_b_parts) - for (auto p : c_patterns) { - p.first.append_bit(sig_s[idx]), p.second.bits.push_back(RTLIL::State::S1); - if (sort_check_activation_pattern(p)) - activation_patterns_cache[cell].insert(p); - } - } - - for (auto c : driven_cells) { - const std::set> &c_patterns = find_cell_activation_patterns(c, indent); - activation_patterns_cache[cell].insert(c_patterns.begin(), c_patterns.end()); - } - - log_assert(recursion_state.count(cell)); - recursion_state.erase(cell); - - optimize_activation_patterns(activation_patterns_cache[cell]); - if (activation_patterns_cache[cell].empty()) { - log("%sFound cell that is never activated: %s\n", indent, log_id(cell)); - RTLIL::SigSpec cell_outputs = modwalker.cell_outputs[cell]; - module->connect(RTLIL::SigSig(cell_outputs, RTLIL::SigSpec(RTLIL::State::Sx, cell_outputs.size()))); - cells_to_remove.insert(cell); - } - - return activation_patterns_cache[cell]; - } - - RTLIL::SigSpec bits_from_activation_patterns(const std::set> &activation_patterns) - { - std::set all_bits; - for (auto &it : activation_patterns) { - std::vector bits = it.first; - all_bits.insert(bits.begin(), bits.end()); - } - - RTLIL::SigSpec signal; - for (auto &bit : all_bits) - signal.append_bit(bit); - - return signal; - } - - void filter_activation_patterns(std::set> &out, - const std::set> &in, const std::set &filter_bits) - { - for (auto &p : in) - { - std::vector p_first = p.first; - std::pair new_p; - - for (int i = 0; i < SIZE(p_first); i++) - if (filter_bits.count(p_first[i]) == 0) { - new_p.first.append_bit(p_first[i]); - new_p.second.bits.push_back(p.second.bits.at(i)); - } - - out.insert(new_p); - } - } - - RTLIL::SigSpec make_cell_activation_logic(const std::set> &activation_patterns) - { - RTLIL::Wire *all_cases_wire = module->addWire(NEW_ID, 0); - for (auto &p : activation_patterns) { - all_cases_wire->width++; - module->addEq(NEW_ID, p.first, p.second, RTLIL::SigSpec(all_cases_wire, all_cases_wire->width - 1)); - } - if (all_cases_wire->width == 1) - return all_cases_wire; - return module->ReduceOr(NEW_ID, all_cases_wire); - } - - - // ------------- - // Setup and run - // ------------- - - ShareWorker(ShareWorkerConfig config, RTLIL::Design *design, RTLIL::Module *module) : - config(config), design(design), module(module) - { - generic_ops.insert(config.generic_uni_ops.begin(), config.generic_uni_ops.end()); - generic_ops.insert(config.generic_bin_ops.begin(), config.generic_bin_ops.end()); - generic_ops.insert(config.generic_cbin_ops.begin(), config.generic_cbin_ops.end()); - - fwd_ct.setup_internals(); - - cone_ct.setup_internals(); - cone_ct.cell_types.erase("$mul"); - cone_ct.cell_types.erase("$mod"); - cone_ct.cell_types.erase("$div"); - cone_ct.cell_types.erase("$pow"); - cone_ct.cell_types.erase("$shl"); - cone_ct.cell_types.erase("$shr"); - cone_ct.cell_types.erase("$sshl"); - cone_ct.cell_types.erase("$sshr"); - - modwalker.setup(design, module); - - find_terminal_bits(); - find_shareable_cells(); - - if (shareable_cells.size() < 2) - return; - - log("Found %d cells in module %s that may be considered for resource sharing.\n", - SIZE(shareable_cells), log_id(module)); - - while (!shareable_cells.empty()) - { - RTLIL::Cell *cell = *shareable_cells.begin(); - shareable_cells.erase(cell); - - log(" Analyzing resource sharing options for %s:\n", log_id(cell)); - - const std::set> &cell_activation_patterns = find_cell_activation_patterns(cell, " "); - RTLIL::SigSpec cell_activation_signals = bits_from_activation_patterns(cell_activation_patterns); - - if (cell_activation_patterns.empty()) { - log(" Cell is never active. Sharing is pointless, we simply remove it.\n"); - cells_to_remove.insert(cell); - continue; - } - - if (cell_activation_patterns.count(std::pair())) { - log(" Cell is always active. Therefore no sharing is possible.\n"); - continue; - } - - log(" Found %d activation_patterns using ctrl signal %s.\n", SIZE(cell_activation_patterns), log_signal(cell_activation_signals)); - - std::vector candidates; - find_shareable_partners(candidates, cell); - - if (candidates.empty()) { - log(" No candidates found.\n"); - continue; - } - - log(" Found %d candidates:", SIZE(candidates)); - for (auto c : candidates) - log(" %s", log_id(c)); - log("\n"); - - for (auto other_cell : candidates) - { - log(" Analyzing resource sharing with %s:\n", log_id(other_cell)); - - const std::set> &other_cell_activation_patterns = find_cell_activation_patterns(other_cell, " "); - RTLIL::SigSpec other_cell_activation_signals = bits_from_activation_patterns(other_cell_activation_patterns); - - if (other_cell_activation_patterns.empty()) { - log(" Cell is never active. Sharing is pointless, we simply remove it.\n"); - shareable_cells.erase(other_cell); - cells_to_remove.insert(other_cell); - continue; - } - - if (other_cell_activation_patterns.count(std::pair())) { - log(" Cell is always active. Therefore no sharing is possible.\n"); - shareable_cells.erase(other_cell); - continue; - } - - log(" Found %d activation_patterns using ctrl signal %s.\n", - SIZE(other_cell_activation_patterns), log_signal(other_cell_activation_signals)); - - const std::set &cell_forbidden_controls = find_forbidden_controls(cell); - const std::set &other_cell_forbidden_controls = find_forbidden_controls(other_cell); - - std::set union_forbidden_controls; - union_forbidden_controls.insert(cell_forbidden_controls.begin(), cell_forbidden_controls.end()); - union_forbidden_controls.insert(other_cell_forbidden_controls.begin(), other_cell_forbidden_controls.end()); - - if (!union_forbidden_controls.empty()) - log(" Forbidden control signals for this pair of cells: %s\n", log_signal(union_forbidden_controls)); - - std::set> filtered_cell_activation_patterns; - std::set> filtered_other_cell_activation_patterns; - - filter_activation_patterns(filtered_cell_activation_patterns, cell_activation_patterns, union_forbidden_controls); - filter_activation_patterns(filtered_other_cell_activation_patterns, other_cell_activation_patterns, union_forbidden_controls); - - optimize_activation_patterns(filtered_cell_activation_patterns); - optimize_activation_patterns(filtered_other_cell_activation_patterns); - - ezDefaultSAT ez; - SatGen satgen(&ez, &modwalker.sigmap); - - std::set sat_cells; - std::set bits_queue; - - std::vector cell_active, other_cell_active; - RTLIL::SigSpec all_ctrl_signals; - - for (auto &p : filtered_cell_activation_patterns) { - log(" Activation pattern for cell %s: %s = %s\n", log_id(cell), log_signal(p.first), log_signal(p.second)); - cell_active.push_back(ez.vec_eq(satgen.importSigSpec(p.first), satgen.importSigSpec(p.second))); - all_ctrl_signals.append(p.first); - } - - for (auto &p : filtered_other_cell_activation_patterns) { - log(" Activation pattern for cell %s: %s = %s\n", log_id(other_cell), log_signal(p.first), log_signal(p.second)); - other_cell_active.push_back(ez.vec_eq(satgen.importSigSpec(p.first), satgen.importSigSpec(p.second))); - all_ctrl_signals.append(p.first); - } - - for (auto &bit : cell_activation_signals.to_sigbit_vector()) - bits_queue.insert(bit); - - for (auto &bit : other_cell_activation_signals.to_sigbit_vector()) - bits_queue.insert(bit); - - while (!bits_queue.empty()) - { - std::set portbits; - modwalker.get_drivers(portbits, bits_queue); - bits_queue.clear(); - - for (auto &pbit : portbits) - if (sat_cells.count(pbit.cell) == 0 && cone_ct.cell_known(pbit.cell->type)) { - if (config.opt_fast && modwalker.cell_outputs[pbit.cell].size() >= 4) - continue; - // log(" Adding cell %s (%s) to SAT problem.\n", log_id(pbit.cell), log_id(pbit.cell->type)); - bits_queue.insert(modwalker.cell_inputs[pbit.cell].begin(), modwalker.cell_inputs[pbit.cell].end()); - satgen.importCell(pbit.cell); - sat_cells.insert(pbit.cell); - } - - if (config.opt_fast && sat_cells.size() > 100) - break; - } - - if (!ez.solve(ez.expression(ez.OpOr, cell_active))) { - log(" According to the SAT solver the cell %s is never active. Sharing is pointless, we simply remove it.\n", log_id(cell)); - cells_to_remove.insert(cell); - break; - } - - if (!ez.solve(ez.expression(ez.OpOr, other_cell_active))) { - log(" According to the SAT solver the cell %s is never active. Sharing is pointless, we simply remove it.\n", log_id(other_cell)); - cells_to_remove.insert(other_cell); - shareable_cells.erase(other_cell); - continue; - } - - ez.non_incremental(); - - all_ctrl_signals.sort_and_unify(); - std::vector sat_model = satgen.importSigSpec(all_ctrl_signals); - std::vector sat_model_values; - - ez.assume(ez.AND(ez.expression(ez.OpOr, cell_active), ez.expression(ez.OpOr, other_cell_active))); - - log(" Size of SAT problem: %d cells, %d variables, %d clauses\n", - SIZE(sat_cells), ez.numCnfVariables(), ez.numCnfClauses()); - - if (ez.solve(sat_model, sat_model_values)) { - log(" According to the SAT solver this pair of cells can not be shared.\n"); - log(" Model from SAT solver: %s = %d'", log_signal(all_ctrl_signals), SIZE(sat_model_values)); - for (int i = SIZE(sat_model_values)-1; i >= 0; i--) - log("%c", sat_model_values[i] ? '1' : '0'); - log("\n"); - continue; - } - - log(" According to the SAT solver this pair of cells can be shared.\n"); - shareable_cells.erase(other_cell); - - int cell_select_score = 0; - int other_cell_select_score = 0; - - for (auto &p : filtered_cell_activation_patterns) - cell_select_score += p.first.size(); - - for (auto &p : filtered_other_cell_activation_patterns) - other_cell_select_score += p.first.size(); - - RTLIL::Cell *supercell; - if (cell_select_score <= other_cell_select_score) { - RTLIL::SigSpec act = make_cell_activation_logic(filtered_cell_activation_patterns); - supercell = make_supercell(cell, other_cell, act); - log(" Activation signal for %s: %s\n", log_id(cell), log_signal(act)); - } else { - RTLIL::SigSpec act = make_cell_activation_logic(filtered_other_cell_activation_patterns); - supercell = make_supercell(other_cell, cell, act); - log(" Activation signal for %s: %s\n", log_id(other_cell), log_signal(act)); - } - - log(" New cell: %s (%s)\n", log_id(supercell), log_id(supercell->type)); - - std::set> supercell_activation_patterns; - supercell_activation_patterns.insert(filtered_cell_activation_patterns.begin(), filtered_cell_activation_patterns.end()); - supercell_activation_patterns.insert(filtered_other_cell_activation_patterns.begin(), filtered_other_cell_activation_patterns.end()); - optimize_activation_patterns(supercell_activation_patterns); - activation_patterns_cache[supercell] = supercell_activation_patterns; - shareable_cells.insert(supercell); - - cells_to_remove.insert(cell); - cells_to_remove.insert(other_cell); - break; - } - } - - if (!cells_to_remove.empty()) { - log("Removing %d cells in module %s:\n", SIZE(cells_to_remove), log_id(module)); - for (auto c : cells_to_remove) { - log(" Removing cell %s (%s).\n", log_id(c), log_id(c->type)); - module->remove(c); - } - } - - log_assert(recursion_state.empty()); - } -}; - -struct SharePass : public Pass { - SharePass() : Pass("share", "perform sat-based resource sharing") { } - virtual void help() - { - // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| - log("\n"); - log(" share [options] [selection]\n"); - log("\n"); - log("This pass merges shareable resources into a single resource. A SAT solver\n"); - log("is used to determine if two resources are share-able.\n"); - log("\n"); - log(" -force\n"); - log(" Per default the selection of cells that is considered for sharing is\n"); - log(" narrowed using a list of cell types. With this option all selected\n"); - log(" cells are considered for resource sharing.\n"); - log("\n"); - log(" IMPORTANT NOTE: If the -all option is used then no cells with internal\n"); - log(" state must be selected!\n"); - log("\n"); - log(" -aggressive\n"); - log(" Per default some heuristics are used to reduce the number of cells\n"); - log(" considered for resource sharing to only large resources. This options\n"); - log(" turns this heuristics off, resulting in much more cells being considered\n"); - log(" for resource sharing.\n"); - log("\n"); - log(" -fast\n"); - log(" Only consider the simple part of the control logic in SAT solving, resulting\n"); - log(" in much easier SAT problems at the cost of maybe missing some oportunities\n"); - log(" for resource sharing.\n"); - log("\n"); - } - virtual void execute(std::vector args, RTLIL::Design *design) - { - ShareWorkerConfig config; - - config.opt_force = false; - config.opt_aggressive = false; - config.opt_fast = false; - - config.generic_uni_ops.insert("$not"); - // config.generic_uni_ops.insert("$pos"); - // config.generic_uni_ops.insert("$bu0"); - config.generic_uni_ops.insert("$neg"); - - config.generic_cbin_ops.insert("$and"); - config.generic_cbin_ops.insert("$or"); - config.generic_cbin_ops.insert("$xor"); - config.generic_cbin_ops.insert("$xnor"); - - config.generic_bin_ops.insert("$shl"); - config.generic_bin_ops.insert("$shr"); - config.generic_bin_ops.insert("$sshl"); - config.generic_bin_ops.insert("$sshr"); - - config.generic_bin_ops.insert("$lt"); - config.generic_bin_ops.insert("$le"); - config.generic_bin_ops.insert("$eq"); - config.generic_bin_ops.insert("$ne"); - config.generic_bin_ops.insert("$eqx"); - config.generic_bin_ops.insert("$nex"); - config.generic_bin_ops.insert("$ge"); - config.generic_bin_ops.insert("$gt"); - - config.generic_cbin_ops.insert("$add"); - config.generic_cbin_ops.insert("$mul"); - - config.generic_bin_ops.insert("$sub"); - config.generic_bin_ops.insert("$div"); - config.generic_bin_ops.insert("$mod"); - // config.generic_bin_ops.insert("$pow"); - - config.generic_uni_ops.insert("$logic_not"); - config.generic_cbin_ops.insert("$logic_and"); - config.generic_cbin_ops.insert("$logic_or"); - - log_header("Executing SHARE pass (SAT-based resource sharing).\n"); - - size_t argidx; - for (argidx = 1; argidx < args.size(); argidx++) { - if (args[argidx] == "-force") { - config.opt_force = true; - continue; - } - if (args[argidx] == "-aggressive") { - config.opt_aggressive = true; - continue; - } - if (args[argidx] == "-fast") { - config.opt_fast = true; - continue; - } - break; - } - extra_args(args, argidx, design); - - for (auto &mod_it : design->modules_) - if (design->selected(mod_it.second)) - ShareWorker(config, design, mod_it.second); - } -} SharePass; - -PRIVATE_NAMESPACE_END - -- cgit v1.2.3 From 27a1bfbec62c8467cd14a8d44cf4a8a046576b91 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 1 Sep 2014 11:45:47 +0200 Subject: Fixes in old SAT example.ys --- passes/sat/example.ys | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'passes') diff --git a/passes/sat/example.ys b/passes/sat/example.ys index 11f5b924b..cc72faac0 100644 --- a/passes/sat/example.ys +++ b/passes/sat/example.ys @@ -1,13 +1,14 @@ read_verilog example.v proc; opt_clean +echo on sat -set y 1'b1 example001 sat -set y 1'b1 example002 sat -set y_sshl 8'hf0 -set y_sshr 8'hf0 -set sh 4'd3 example003 -sat -set y 1'b1 example004 +sat -set y 1'b1 -ignore_unknown_cells example004 sat -show rst,counter -set-at 3 y 1'b1 -seq 4 example004 -sat -prove y 1'b0 -show rst,counter,y example004 -sat -prove y 1'b0 -show rst,counter,y -set-at 1 rst 1'b1 -seq 1 example004 +sat -prove y 1'b0 -show rst,counter,y -ignore_unknown_cells example004 +sat -prove y 1'b0 -tempinduct -show rst,counter,y -set-at 1 rst 1'b1 -seq 1 example004 -- cgit v1.2.3 From 826fdb34d8933120f022e92bfec508588b9191de Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 1 Sep 2014 15:36:29 +0200 Subject: Added "techmap -autoproc" --- passes/techmap/techmap.cc | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) (limited to 'passes') diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 660f1b388..43a94d976 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -70,6 +70,7 @@ struct TechmapWorker bool assert_mode; bool flatten_mode; bool recursive_mode; + bool autoproc_mode; TechmapWorker() { @@ -77,6 +78,7 @@ struct TechmapWorker assert_mode = false; flatten_mode = false; recursive_mode = false; + autoproc_mode = false; } std::string constmap_tpl_name(SigMap &sigmap, RTLIL::Module *tpl, RTLIL::Cell *cell, bool verbose) @@ -148,7 +150,11 @@ struct TechmapWorker log("Technology map yielded processes:\n"); for (auto &it : tpl->processes) log(" %s",RTLIL::id2cstr(it.first)); - log_error("Technology map yielded processes -> this is not supported.\n"); + if (autoproc_mode) { + Pass::call_on_module(tpl->design, tpl, "proc"); + log_assert(SIZE(tpl->processes) == 0); + } else + log_error("Technology map yielded processes -> this is not supported (use -autoproc to run 'proc' automatically).\n"); } std::string orig_cell_name; @@ -726,6 +732,9 @@ struct TechmapPass : public Pass { log(" depth-first algorithm. both methods should yield equivialent results,\n"); log(" but may differ in performance.\n"); log("\n"); + log(" -autoproc\n"); + log(" Automatically call \"proc\" on implementations that contain processes.\n"); + log("\n"); log(" -assert\n"); log(" this option will cause techmap to exit with an error if it can't map\n"); log(" a selected cell. only cell types that end on an underscore are accepted\n"); @@ -831,7 +840,10 @@ struct TechmapPass : public Pass { size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { if (args[argidx] == "-map" && argidx+1 < args.size()) { - map_files.push_back(args[++argidx]); + if (args[argidx+1].substr(0, 2) == "+/") + map_files.push_back(proc_share_dirname() + args[++argidx].substr(2)); + else + map_files.push_back(args[++argidx]); continue; } if (args[argidx] == "-share_map" && argidx+1 < args.size()) { @@ -862,6 +874,10 @@ struct TechmapPass : public Pass { worker.recursive_mode = true; continue; } + if (args[argidx] == "-autoproc") { + worker.autoproc_mode = true; + continue; + } break; } extra_args(args, argidx, design); -- cgit v1.2.3 From c7f81e4e49b3c2be1280cd0895170a5d89d9c444 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 1 Sep 2014 15:37:21 +0200 Subject: Added "test_cell -simlib -v" --- passes/tests/test_cell.cc | 37 +++++++++++++++++++++++++++++-------- 1 file changed, 29 insertions(+), 8 deletions(-) (limited to 'passes') diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index d9554bcf7..7f9f1f9b8 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -100,17 +100,17 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type, cell->check(); } -static void run_eval_test(RTLIL::Design *design) +static void run_eval_test(RTLIL::Design *design, bool verbose) { RTLIL::Module *gold_mod = design->module("\\gold"); RTLIL::Module *gate_mod = design->module("\\gate"); ConstEval gold_ce(gold_mod), gate_ce(gate_mod); - log("Eval testing: "); + log("Eval testing:%c", verbose ? '\n' : ' '); for (int i = 0; i < 64; i++) { - log("."); + log(verbose ? "\n" : "."); gold_ce.clear(); gate_ce.clear(); @@ -138,7 +138,8 @@ static void run_eval_test(RTLIL::Design *design) in_value.bits[i] = RTLIL::Sx; } - // log("%s: %s\n", log_id(gold_wire), log_signal(in_value)); + if (verbose) + log("%s: %s\n", log_id(gold_wire), log_signal(in_value)); gold_ce.set(gold_wire, in_value); gate_ce.set(gate_wire, in_value); @@ -179,11 +180,13 @@ static void run_eval_test(RTLIL::Design *design) if (gold_gate_mismatch) log_error("Mismatch in output %s: gold:%s != gate:%s\n", log_id(gate_wire), log_signal(gold_outval), log_signal(gate_outval)); - // log("%s: %s\n", log_id(gold_wire), log_signal(gold_outval)); + if (verbose) + log("%s: %s\n", log_id(gold_wire), log_signal(gold_outval)); } } - log(" ok.\n"); + if (!verbose) + log(" ok.\n"); } struct TestCellPass : public Pass { @@ -212,6 +215,12 @@ struct TestCellPass : public Pass { log(" -map {filename}\n"); log(" pass this option to techmap.\n"); log("\n"); + log(" -simplib\n"); + log(" use \"techmap -map +/simlib.v -max_iter 2 -autoproc\"\n"); + log("\n"); + log(" -v\n"); + log(" print additional debug information to the console\n"); + log("\n"); } virtual void execute(std::vector args, RTLIL::Design*) { @@ -219,6 +228,7 @@ struct TestCellPass : public Pass { std::string techmap_cmd = "techmap -assert"; std::string ilang_file; xorshift32_state = 0; + bool verbose = false; int argidx; for (argidx = 1; argidx < SIZE(args); argidx++) @@ -240,6 +250,14 @@ struct TestCellPass : public Pass { num_iter = 1; continue; } + if (args[argidx] == "-simlib") { + techmap_cmd = "techmap -map +/simlib.v -max_iter 2 -autoproc"; + continue; + } + if (args[argidx] == "-v") { + verbose = true; + continue; + } break; } @@ -350,9 +368,12 @@ struct TestCellPass : public Pass { else create_gold_module(design, cell_type, cell_types.at(cell_type)); Pass::call(design, stringf("copy gold gate; %s gate; opt gate", techmap_cmd.c_str())); - Pass::call(design, "miter -equiv -flatten -make_outputs -ignore_gold_x gold gate miter; dump gold"); + Pass::call(design, "miter -equiv -flatten -make_outputs -ignore_gold_x gold gate miter"); + if (verbose) + Pass::call(design, "dump gate"); + Pass::call(design, "dump gold"); Pass::call(design, "sat -verify -enable_undef -prove trigger 0 -show-inputs -show-outputs miter"); - run_eval_test(design); + run_eval_test(design, verbose); delete design; } } -- cgit v1.2.3 From 630befdf6d58ab5f7c4ca1ea77c86df7b88ee259 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 1 Sep 2014 16:36:04 +0200 Subject: Added $alu support to test_cell --- passes/tests/test_cell.cc | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index 7f9f1f9b8..7c7d6b7fd 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -95,6 +95,27 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type, cell->setPort("\\Y", wire); } + if (cell_type == "$alu") + { + wire = module->addWire("\\CI"); + wire->port_input = true; + cell->setPort("\\CI", wire); + + wire = module->addWire("\\BI"); + wire->port_input = true; + cell->setPort("\\BI", wire); + + wire = module->addWire("\\X"); + wire->width = SIZE(cell->getPort("\\Y")); + wire->port_output = true; + cell->setPort("\\X", wire); + + wire = module->addWire("\\CO"); + wire->width = SIZE(cell->getPort("\\Y")); + wire->port_output = true; + cell->setPort("\\CO", wire); + } + module->fixup_ports(); cell->fixup_parameters(); cell->check(); @@ -317,7 +338,7 @@ struct TestCellPass : public Pass { // cell_types["$assert"] = "A"; cell_types["$lut"] = "*"; - // cell_types["$alu"] = "*"; + cell_types["$alu"] = "ABSY"; for (; argidx < SIZE(args); argidx++) { -- cgit v1.2.3 From 9f00a0cd2d972a5fc4a75f8c1bdba723a5f66b7d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 2 Sep 2014 03:28:46 +0200 Subject: Using "xdot" instead of "yosys-svgviewer" in show command --- passes/cmds/show.cc | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'passes') diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index 3468eae78..6ab0e1ba1 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -751,8 +751,8 @@ struct ShowPass : public Pass { if (worker.page_counter == 0) log_cmd_error("Nothing there to show.\n"); - if (format != "dot") { - std::string cmd = stringf("dot -T%s -o '%s' '%s'", format.empty() ? "svg" : format.c_str(), out_file.c_str(), dot_file.c_str()); + if (format != "dot" && !format.empty()) { + std::string cmd = stringf("dot -T%s -o '%s' '%s'", format.c_str(), out_file.c_str(), dot_file.c_str()); log("Exec: %s\n", cmd.c_str()); if (system(cmd.c_str()) != 0) log_cmd_error("Shell command failed!\n"); @@ -765,8 +765,7 @@ struct ShowPass : public Pass { log_cmd_error("Shell command failed!\n"); } else if (format.empty()) { - std::string svgviewer = proc_self_dirname() + "yosys-svgviewer"; - std::string cmd = stringf("fuser -s '%s' || '%s' '%s' &", out_file.c_str(), svgviewer.c_str(), out_file.c_str()); + std::string cmd = stringf("fuser -s '%s' || xdot '%s' < '%s' &", dot_file.c_str(), dot_file.c_str(), dot_file.c_str()); log("Exec: %s\n", cmd.c_str()); if (system(cmd.c_str()) != 0) log_cmd_error("Shell command failed!\n"); -- cgit v1.2.3 From 37fe7c7bdfd65071311049ce4287ef235797096e Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 2 Sep 2014 04:03:06 +0200 Subject: Removed references to yosys-svgviewer from docs --- passes/cmds/show.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'passes') diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index 6ab0e1ba1..0451ebc29 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -598,8 +598,8 @@ struct ShowPass : public Pass { log(" -notitle\n"); log(" do not add the module name as graph title to the dot file\n"); log("\n"); - log("When no is specified, SVG is used. When no and is\n"); - log("specified, 'yosys-svgviewer' is used to display the schematic.\n"); + log("When no is specified, 'dot' is used. When no and is\n"); + log("specified, 'xdot' is used to display the schematic.\n"); log("\n"); log("The generated output files are '~/.yosys_show.dot' and '~/.yosys_show.',\n"); log("unless another prefix is specified using -prefix .\n"); -- cgit v1.2.3 From acd7a99aef0f698580dc6a6d202a79f36fdf5360 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 2 Sep 2014 17:28:13 +0200 Subject: Added SAT testing to test_cell eval stage --- passes/tests/test_cell.cc | 90 ++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 89 insertions(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index 7c7d6b7fd..de68ee7ec 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -19,6 +19,7 @@ */ #include "kernel/yosys.h" +#include "kernel/satgen.h" #include "kernel/consteval.h" #include @@ -123,11 +124,22 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type, static void run_eval_test(RTLIL::Design *design, bool verbose) { + log("Eval testing:%c", verbose ? '\n' : ' '); + RTLIL::Module *gold_mod = design->module("\\gold"); RTLIL::Module *gate_mod = design->module("\\gate"); ConstEval gold_ce(gold_mod), gate_ce(gate_mod); - log("Eval testing:%c", verbose ? '\n' : ' '); + ezDefaultSAT ez1, ez2; + SigMap sigmap(gold_mod); + SatGen satgen1(&ez1, &sigmap); + SatGen satgen2(&ez2, &sigmap); + satgen2.model_undef = true; + + for (auto cell : gold_mod->cells()) { + satgen1.importCell(cell); + satgen2.importCell(cell); + } for (int i = 0; i < 64; i++) { @@ -135,6 +147,9 @@ static void run_eval_test(RTLIL::Design *design, bool verbose) gold_ce.clear(); gate_ce.clear(); + RTLIL::SigSpec in_sig, in_val; + RTLIL::SigSpec out_sig, out_val; + for (auto port : gold_mod->ports) { RTLIL::Wire *gold_wire = gold_mod->wire(port); @@ -162,6 +177,9 @@ static void run_eval_test(RTLIL::Design *design, bool verbose) if (verbose) log("%s: %s\n", log_id(gold_wire), log_signal(in_value)); + in_sig.append(gold_wire); + in_val.append(in_value); + gold_ce.set(gold_wire, in_value); gate_ce.set(gate_wire, in_value); } @@ -203,6 +221,76 @@ static void run_eval_test(RTLIL::Design *design, bool verbose) if (verbose) log("%s: %s\n", log_id(gold_wire), log_signal(gold_outval)); + + out_sig.append(gold_wire); + out_val.append(gold_outval); + } + + if (verbose) + log("EVAL: %s\n", out_val.as_string().c_str()); + + std::vector sat1_in_sig = satgen1.importSigSpec(in_sig); + std::vector sat1_in_val = satgen1.importSigSpec(in_val); + + std::vector sat1_model = satgen1.importSigSpec(out_sig); + std::vector sat1_model_value; + + if (!ez1.solve(sat1_model, sat1_model_value, ez1.vec_eq(sat1_in_sig, sat1_in_val))) + log_error("Evaluating sat model 1 (no undef modeling) failed!\n"); + + if (verbose) { + log("SAT 1: "); + for (int i = SIZE(out_sig)-1; i >= 0; i--) + log("%c", sat1_model_value.at(i) ? '1' : '0'); + log("\n"); + } + + for (int i = 0; i < SIZE(out_sig); i++) { + if (out_val[i] != RTLIL::S0 && out_val[i] != RTLIL::S1) + continue; + if (out_val[i] == RTLIL::S0 && sat1_model_value.at(i) == false) + continue; + if (out_val[i] == RTLIL::S1 && sat1_model_value.at(i) == true) + continue; + log_error("Mismatch in sat model 1 (no undef modeling) output!\n"); + } + + std::vector sat2_in_def_sig = satgen2.importDefSigSpec(in_sig); + std::vector sat2_in_def_val = satgen2.importDefSigSpec(in_val); + + std::vector sat2_in_undef_sig = satgen2.importUndefSigSpec(in_sig); + std::vector sat2_in_undef_val = satgen2.importUndefSigSpec(in_val); + + std::vector sat2_model_def_sig = satgen2.importDefSigSpec(out_sig); + std::vector sat2_model_undef_sig = satgen2.importUndefSigSpec(out_sig); + + std::vector sat2_model; + sat2_model.insert(sat2_model.end(), sat2_model_def_sig.begin(), sat2_model_def_sig.end()); + sat2_model.insert(sat2_model.end(), sat2_model_undef_sig.begin(), sat2_model_undef_sig.end()); + + std::vector sat2_model_value; + + if (!ez2.solve(sat2_model, sat2_model_value, ez2.vec_eq(sat2_in_def_sig, sat2_in_def_val), ez2.vec_eq(sat2_in_undef_sig, sat2_in_undef_val))) + log_error("Evaluating sat model 2 (undef modeling) failed!\n"); + + if (verbose) { + log("SAT 2: "); + for (int i = SIZE(out_sig)-1; i >= 0; i--) + log("%c", sat2_model_value.at(SIZE(out_sig) + i) ? 'x' : sat2_model_value.at(i) ? '1' : '0'); + log("\n"); + } + + for (int i = 0; i < SIZE(out_sig); i++) { + if (sat2_model_value.at(SIZE(out_sig) + i)) { + if (out_val[i] != RTLIL::S0 && out_val[i] != RTLIL::S1) + continue; + } else { + if (out_val[i] == RTLIL::S0 && sat2_model_value.at(i) == false) + continue; + if (out_val[i] == RTLIL::S1 && sat2_model_value.at(i) == true) + continue; + } + log_error("Mismatch in sat model 2 (undef modeling) output!\n"); } } -- cgit v1.2.3 From 66bf2bb92eb102dbb6b942c0c09b90f3925621a7 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 2 Sep 2014 22:49:43 +0200 Subject: Added test_cell -vlog --- passes/tests/test_cell.cc | 81 +++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 79 insertions(+), 2 deletions(-) (limited to 'passes') diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index de68ee7ec..aead7b46f 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -122,7 +122,7 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type, cell->check(); } -static void run_eval_test(RTLIL::Design *design, bool verbose) +static void run_eval_test(RTLIL::Design *design, bool verbose, std::string uut_name, std::ofstream &vlog_file) { log("Eval testing:%c", verbose ? '\n' : ' '); @@ -141,6 +141,35 @@ static void run_eval_test(RTLIL::Design *design, bool verbose) satgen2.importCell(cell); } + if (vlog_file.is_open()) + { + vlog_file << stringf("\nmodule %s;\n", uut_name.c_str()); + + for (auto port : gold_mod->ports) { + RTLIL::Wire *wire = gold_mod->wire(port); + if (wire->port_input) + vlog_file << stringf(" reg [%d:0] %s;\n", SIZE(wire)-1, log_id(wire)); + else + vlog_file << stringf(" wire [%d:0] %s_expr, %s_noexpr;\n", SIZE(wire)-1, log_id(wire), log_id(wire)); + } + + vlog_file << stringf(" %s_expr uut_expr(", uut_name.c_str()); + for (int i = 0; i < SIZE(gold_mod->ports); i++) + vlog_file << stringf("%s.%s(%s%s)", i ? ", " : "", log_id(gold_mod->ports[i]), log_id(gold_mod->ports[i]), + gold_mod->wire(gold_mod->ports[i])->port_input ? "" : "_expr"); + vlog_file << stringf(");\n"); + + vlog_file << stringf(" %s_expr uut_noexpr(", uut_name.c_str()); + for (int i = 0; i < SIZE(gold_mod->ports); i++) + vlog_file << stringf("%s.%s(%s%s)", i ? ", " : "", log_id(gold_mod->ports[i]), log_id(gold_mod->ports[i]), + gold_mod->wire(gold_mod->ports[i])->port_input ? "" : "_noexpr"); + vlog_file << stringf(");\n"); + + vlog_file << stringf(" task run;\n"); + vlog_file << stringf(" begin\n"); + vlog_file << stringf(" $display(\"%s\");\n", uut_name.c_str()); + } + for (int i = 0; i < 64; i++) { log(verbose ? "\n" : "."); @@ -182,8 +211,14 @@ static void run_eval_test(RTLIL::Design *design, bool verbose) gold_ce.set(gold_wire, in_value); gate_ce.set(gate_wire, in_value); + + if (vlog_file.is_open()) + vlog_file << stringf(" %s = 'b%s;\n", log_id(gold_wire), in_value.as_string().c_str()); } + if (vlog_file.is_open()) + vlog_file << stringf(" #1;\n"); + for (auto port : gold_mod->ports) { RTLIL::Wire *gold_wire = gold_mod->wire(port); @@ -224,6 +259,13 @@ static void run_eval_test(RTLIL::Design *design, bool verbose) out_sig.append(gold_wire); out_val.append(gold_outval); + + if (vlog_file.is_open()) { + vlog_file << stringf(" $display(\"[%s %s] %s expected: %%b, expr: %%b, noexpr: %%b\", %d'b%s, %s_expr, %s_noexpr);\n", + log_signal(in_sig), log_signal(in_val), log_id(gold_wire), SIZE(gold_outval), gold_outval.as_string().c_str(), log_id(gold_wire), log_id(gold_wire)); + vlog_file << stringf(" if (%s_expr !== %d'b%s) begin $display(\"ERROR\"); $finish; end\n", log_id(gold_wire), SIZE(gold_outval), gold_outval.as_string().c_str()); + vlog_file << stringf(" if (%s_noexpr !== %d'b%s) begin $display(\"ERROR\"); $finish; end\n", log_id(gold_wire), SIZE(gold_outval), gold_outval.as_string().c_str()); + } } if (verbose) @@ -294,6 +336,12 @@ static void run_eval_test(RTLIL::Design *design, bool verbose) } } + if (vlog_file.is_open()) { + vlog_file << stringf(" end\n"); + vlog_file << stringf(" endtask\n"); + vlog_file << stringf("endmodule\n"); + } + if (!verbose) log(" ok.\n"); } @@ -330,6 +378,9 @@ struct TestCellPass : public Pass { log(" -v\n"); log(" print additional debug information to the console\n"); log("\n"); + log(" -vlog {filename}\n"); + log(" create a verilog test bench to test simlib and write_verilog\n"); + log("\n"); } virtual void execute(std::vector args, RTLIL::Design*) { @@ -337,6 +388,7 @@ struct TestCellPass : public Pass { std::string techmap_cmd = "techmap -assert"; std::string ilang_file; xorshift32_state = 0; + std::ofstream vlog_file; bool verbose = false; int argidx; @@ -367,6 +419,12 @@ struct TestCellPass : public Pass { verbose = true; continue; } + if (args[argidx] == "-vlog" && argidx+1 < SIZE(args)) { + vlog_file.open(args[++argidx], std::ios_base::trunc); + if (!vlog_file.is_open()) + log_cmd_error("Failed to open output file `%s'.\n", args[argidx].c_str()); + continue; + } break; } @@ -468,6 +526,8 @@ struct TestCellPass : public Pass { if (selected_cell_types.empty()) log_cmd_error("No cell type to test specified.\n"); + std::vector task_names; + for (auto cell_type : selected_cell_types) for (int i = 0; i < num_iter; i++) { @@ -482,9 +542,26 @@ struct TestCellPass : public Pass { Pass::call(design, "dump gate"); Pass::call(design, "dump gold"); Pass::call(design, "sat -verify -enable_undef -prove trigger 0 -show-inputs -show-outputs miter"); - run_eval_test(design, verbose); + std::string uut_name = stringf("uut_%s_%d", cell_type.substr(1).c_str(), i); + if (vlog_file.is_open()) { + Pass::call(design, stringf("copy gold %s_expr; select %s_expr", uut_name.c_str(), uut_name.c_str())); + Backend::backend_call(design, &vlog_file, "", "verilog -selected"); + Pass::call(design, stringf("copy gold %s_noexpr; select %s_noexpr", uut_name.c_str(), uut_name.c_str())); + Backend::backend_call(design, &vlog_file, "", "verilog -selected -noexpr"); + task_names.push_back(uut_name + ".run"); + } + run_eval_test(design, verbose, uut_name, vlog_file); delete design; } + + if (vlog_file.is_open()) { + vlog_file << "\nmodule testbench;\n"; + vlog_file << " initial begin\n"; + for (auto &task : task_names) + vlog_file << " " << task << ";\n"; + vlog_file << " end\n"; + vlog_file << "endmodule\n"; + } } } TestCellPass; -- cgit v1.2.3 From f1869667cac35e897c0531c05074f3c77bfa5db9 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 2 Sep 2014 23:21:15 +0200 Subject: Improvements in "test_cell -vlog" --- passes/tests/test_cell.cc | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) (limited to 'passes') diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index aead7b46f..627c2f7d4 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -178,6 +178,7 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, std::string uut_n RTLIL::SigSpec in_sig, in_val; RTLIL::SigSpec out_sig, out_val; + std::string vlog_pattern_info; for (auto port : gold_mod->ports) { @@ -212,8 +213,12 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, std::string uut_n gold_ce.set(gold_wire, in_value); gate_ce.set(gate_wire, in_value); - if (vlog_file.is_open()) + if (vlog_file.is_open()) { vlog_file << stringf(" %s = 'b%s;\n", log_id(gold_wire), in_value.as_string().c_str()); + if (!vlog_pattern_info.empty()) + vlog_pattern_info += " "; + vlog_pattern_info += stringf("%s=%s", log_id(gold_wire), log_signal(in_value)); + } } if (vlog_file.is_open()) @@ -261,8 +266,8 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, std::string uut_n out_val.append(gold_outval); if (vlog_file.is_open()) { - vlog_file << stringf(" $display(\"[%s %s] %s expected: %%b, expr: %%b, noexpr: %%b\", %d'b%s, %s_expr, %s_noexpr);\n", - log_signal(in_sig), log_signal(in_val), log_id(gold_wire), SIZE(gold_outval), gold_outval.as_string().c_str(), log_id(gold_wire), log_id(gold_wire)); + vlog_file << stringf(" $display(\"[%s] %s expected: %%b, expr: %%b, noexpr: %%b\", %d'b%s, %s_expr, %s_noexpr);\n", + vlog_pattern_info.c_str(), log_id(gold_wire), SIZE(gold_outval), gold_outval.as_string().c_str(), log_id(gold_wire), log_id(gold_wire)); vlog_file << stringf(" if (%s_expr !== %d'b%s) begin $display(\"ERROR\"); $finish; end\n", log_id(gold_wire), SIZE(gold_outval), gold_outval.as_string().c_str()); vlog_file << stringf(" if (%s_noexpr !== %d'b%s) begin $display(\"ERROR\"); $finish; end\n", log_id(gold_wire), SIZE(gold_outval), gold_outval.as_string().c_str()); } -- cgit v1.2.3 From 5733f4a39d56388e531b6c1471f56c3efb023f31 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 3 Sep 2014 13:43:37 +0200 Subject: Fixed "test_cells -vlog" --- passes/tests/test_cell.cc | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'passes') diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index 627c2f7d4..dce768048 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -531,7 +531,7 @@ struct TestCellPass : public Pass { if (selected_cell_types.empty()) log_cmd_error("No cell type to test specified.\n"); - std::vector task_names; + std::vector uut_names; for (auto cell_type : selected_cell_types) for (int i = 0; i < num_iter; i++) @@ -553,7 +553,7 @@ struct TestCellPass : public Pass { Backend::backend_call(design, &vlog_file, "", "verilog -selected"); Pass::call(design, stringf("copy gold %s_noexpr; select %s_noexpr", uut_name.c_str(), uut_name.c_str())); Backend::backend_call(design, &vlog_file, "", "verilog -selected -noexpr"); - task_names.push_back(uut_name + ".run"); + uut_names.push_back(uut_name); } run_eval_test(design, verbose, uut_name, vlog_file); delete design; @@ -561,9 +561,11 @@ struct TestCellPass : public Pass { if (vlog_file.is_open()) { vlog_file << "\nmodule testbench;\n"; + for (auto &uut : uut_names) + vlog_file << stringf(" %s %s ();\n", uut.c_str(), uut.c_str()); vlog_file << " initial begin\n"; - for (auto &task : task_names) - vlog_file << " " << task << ";\n"; + for (auto &uut : uut_names) + vlog_file << " " << uut << ".run;\n"; vlog_file << " end\n"; vlog_file << "endmodule\n"; } -- cgit v1.2.3 From 8927aa6148f5575b2da9bfb76afb4af076fe18f3 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 4 Sep 2014 02:07:52 +0200 Subject: Removed $bu0 cell type --- passes/cmds/stat.cc | 2 +- passes/opt/opt_const.cc | 10 ++++------ passes/opt/share.cc | 1 - passes/opt/wreduce.cc | 6 +++--- passes/techmap/simplemap.cc | 13 +------------ passes/tests/test_cell.cc | 1 - 6 files changed, 9 insertions(+), 24 deletions(-) (limited to 'passes') diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc index dea24227f..19cdaa621 100644 --- a/passes/cmds/stat.cc +++ b/passes/cmds/stat.cc @@ -99,7 +99,7 @@ namespace if (width_mode) { - if (cell_type.in("$not", "$pos", "$bu0", "$neg", + if (cell_type.in("$not", "$pos", "$neg", "$logic_not", "$logic_and", "$logic_or", "$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool", "$lut", "$and", "$or", "$xor", "$xnor", diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index ad6961872..d315dba35 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -181,7 +181,7 @@ static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool com log("\n"); } - cover_list("opt.opt_const.fine.group", "$not", "$pos", "$bu0", "$and", "$or", "$xor", "$xnor", cell->type.str()); + cover_list("opt.opt_const.fine.group", "$not", "$pos", "$and", "$or", "$xor", "$xnor", cell->type.str()); module->remove(cell); did_something = true; @@ -236,7 +236,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (do_fine) { - if (cell->type == "$not" || cell->type == "$pos" || cell->type == "$bu0" || + if (cell->type == "$not" || cell->type == "$pos" || cell->type == "$and" || cell->type == "$or" || cell->type == "$xor" || cell->type == "$xnor") if (group_cell_inputs(module, cell, true, cell->type != "$pos", assign_map)) goto next_cell; @@ -586,7 +586,6 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (!keepdc) { - bool identity_bu0 = false; bool identity_wrt_a = false; bool identity_wrt_b = false; @@ -607,7 +606,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo RTLIL::SigSpec b = assign_map(cell->getPort("\\B")); if (b.is_fully_const() && b.as_bool() == false) - identity_wrt_a = true, identity_bu0 = true; + identity_wrt_a = true; } if (cell->type == "$mul") @@ -646,7 +645,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cell->parameters.at("\\A_SIGNED") = cell->parameters.at("\\B_SIGNED"); } - cell->type = identity_bu0 ? "$bu0" : "$pos"; + cell->type = "$pos"; cell->unsetPort("\\B"); cell->parameters.erase("\\B_WIDTH"); cell->parameters.erase("\\B_SIGNED"); @@ -840,7 +839,6 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo FOLD_2ARG_CELL(pow) FOLD_1ARG_CELL(pos) - FOLD_1ARG_CELL(bu0) FOLD_1ARG_CELL(neg) // be very conservative with optimizing $mux cells as we do not want to break mux trees diff --git a/passes/opt/share.cc b/passes/opt/share.cc index 5f3cf4214..c372ed78a 100644 --- a/passes/opt/share.cc +++ b/passes/opt/share.cc @@ -923,7 +923,6 @@ struct SharePass : public Pass { config.generic_uni_ops.insert("$not"); // config.generic_uni_ops.insert("$pos"); - // config.generic_uni_ops.insert("$bu0"); config.generic_uni_ops.insert("$neg"); config.generic_cbin_ops.insert("$and"); diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc index 2269859d1..321a1aa55 100644 --- a/passes/opt/wreduce.cc +++ b/passes/opt/wreduce.cc @@ -37,7 +37,7 @@ struct WreduceConfig WreduceConfig() { - supported_cell_types << "$not" << "$pos" << "$bu0" << "$neg"; + supported_cell_types << "$not" << "$pos" << "$neg"; supported_cell_types << "$and" << "$or" << "$xor" << "$xnor"; supported_cell_types << "$shl" << "$shr" << "$sshl" << "$sshr" << "$shift" << "$shiftx"; supported_cell_types << "$lt" << "$le" << "$eq" << "$ne" << "$eqx" << "$nex" << "$ge" << "$gt"; @@ -181,7 +181,7 @@ struct WreduceWorker int max_port_a_size = cell->hasPort("\\A") ? SIZE(cell->getPort("\\A")) : -1; int max_port_b_size = cell->hasPort("\\B") ? SIZE(cell->getPort("\\B")) : -1; - if (cell->type.in("$not", "$pos", "$bu0", "$neg", "$and", "$or", "$xor", "$add", "$sub")) { + if (cell->type.in("$not", "$pos", "$neg", "$and", "$or", "$xor", "$add", "$sub")) { max_port_a_size = std::min(max_port_a_size, SIZE(cell->getPort("\\Y"))); max_port_b_size = std::min(max_port_b_size, SIZE(cell->getPort("\\Y"))); } @@ -216,7 +216,7 @@ struct WreduceWorker } } - if (cell->type.in("$pos", "$bu0", "$add", "$mul", "$and", "$or", "$xor")) + if (cell->type.in("$pos", "$add", "$mul", "$and", "$or", "$xor")) { bool is_signed = cell->getParam("\\A_SIGNED").as_bool(); diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc index f5d9bbeef..f8d5d4584 100644 --- a/passes/techmap/simplemap.cc +++ b/passes/techmap/simplemap.cc @@ -45,16 +45,6 @@ static void simplemap_pos(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::SigSpec sig_a = cell->getPort("\\A"); RTLIL::SigSpec sig_y = cell->getPort("\\Y"); - sig_a.extend(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool()); - - module->connect(RTLIL::SigSig(sig_y, sig_a)); -} - -static void simplemap_bu0(RTLIL::Module *module, RTLIL::Cell *cell) -{ - RTLIL::SigSpec sig_a = cell->getPort("\\A"); - RTLIL::SigSpec sig_y = cell->getPort("\\Y"); - sig_a.extend_u0(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool()); module->connect(RTLIL::SigSig(sig_y, sig_a)); @@ -386,7 +376,6 @@ void simplemap_get_mappers(std::map Date: Thu, 4 Sep 2014 08:55:58 +0200 Subject: Fixed "opt_const -fine" for $pos cells --- passes/opt/opt_const.cc | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) (limited to 'passes') diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index d315dba35..f9b78c053 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -85,7 +85,7 @@ static void replace_cell(SigMap &assign_map, RTLIL::Module *module, RTLIL::Cell did_something = true; } -static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutative, bool extend_u0, SigMap &sigmap) +static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutative, SigMap &sigmap) { std::string b_name = cell->hasPort("\\B") ? "\\B" : "\\A"; @@ -96,13 +96,8 @@ static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool com RTLIL::SigSpec sig_b = sigmap(cell->getPort(b_name)); RTLIL::SigSpec sig_y = sigmap(cell->getPort("\\Y")); - if (extend_u0) { - sig_a.extend_u0(sig_y.size(), a_signed); - sig_b.extend_u0(sig_y.size(), b_signed); - } else { - sig_a.extend(sig_y.size(), a_signed); - sig_b.extend(sig_y.size(), b_signed); - } + sig_a.extend_u0(sig_y.size(), a_signed); + sig_b.extend_u0(sig_y.size(), b_signed); std::vector bits_a = sig_a, bits_b = sig_b, bits_y = sig_y; @@ -238,7 +233,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo { if (cell->type == "$not" || cell->type == "$pos" || cell->type == "$and" || cell->type == "$or" || cell->type == "$xor" || cell->type == "$xnor") - if (group_cell_inputs(module, cell, true, cell->type != "$pos", assign_map)) + if (group_cell_inputs(module, cell, true, assign_map)) goto next_cell; if (cell->type == "$reduce_and") -- cgit v1.2.3 From 79cbf9067c07ed810b3466174278d77b9a05b46d Mon Sep 17 00:00:00 2001 From: Ruben Undheim Date: Sat, 6 Sep 2014 08:47:06 +0200 Subject: Corrected spelling mistakes found by lintian --- passes/cmds/scc.cc | 2 +- passes/cmds/select.cc | 4 ++-- passes/cmds/splice.cc | 4 ++-- passes/cmds/splitnets.cc | 2 +- passes/fsm/fsm_recode.cc | 2 +- passes/hierarchy/hierarchy.cc | 8 ++++---- passes/memory/memory_share.cc | 2 +- passes/opt/opt_clean.cc | 4 ++-- passes/sat/sat.cc | 2 +- 9 files changed, 15 insertions(+), 15 deletions(-) (limited to 'passes') diff --git a/passes/cmds/scc.cc b/passes/cmds/scc.cc index 8c039e3e9..5224f5bc9 100644 --- a/passes/cmds/scc.cc +++ b/passes/cmds/scc.cc @@ -216,7 +216,7 @@ struct SccPass : public Pass { log("\n"); log(" -all_cell_types\n"); log(" Usually this command only considers internal non-memory cells. With\n"); - log(" this option set, all cells are considered. For unkown cells all ports\n"); + log(" this option set, all cells are considered. For unknown cells all ports\n"); log(" are assumed to be bidirectional 'inout' ports.\n"); log("\n"); log(" -set_attr \n"); diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index 2d49e85ed..4c540ca67 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -985,7 +985,7 @@ struct SelectPass : public Pass { log(" (i.e. select all cells connected to selected wires and select all\n"); log(" wires connected to selected cells) The rules specify which cell\n"); log(" ports to use for this. the syntax for a rule is a '-' for exclusion\n"); - log(" and a '+' for inclusion, followed by an optional comma seperated\n"); + log(" and a '+' for inclusion, followed by an optional comma separated\n"); log(" list of cell types followed by an optional comma separated list of\n"); log(" cell ports in square brackets. a rule can also be just a cell or wire\n"); log(" name that limits the expansion (is included but does not go beyond).\n"); @@ -1089,7 +1089,7 @@ struct SelectPass : public Pass { continue; } if (arg.size() > 0 && arg[0] == '-') - log_cmd_error("Unkown option %s.\n", arg.c_str()); + log_cmd_error("Unknown option %s.\n", arg.c_str()); select_stmt(design, arg); sel_str += " " + arg; } diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc index ca71f7d8d..d03aaf3b5 100644 --- a/passes/cmds/splice.cc +++ b/passes/cmds/splice.cc @@ -251,12 +251,12 @@ struct SplicePass : public Pass { log("\n"); log(" -sel_by_cell\n"); log(" only select the cell ports to rewire by the cell. if the selection\n"); - log(" contains a cell, than all cell inputs are rewired, if neccessary.\n"); + log(" contains a cell, than all cell inputs are rewired, if necessary.\n"); log("\n"); log(" -sel_by_wire\n"); log(" only select the cell ports to rewire by the wire. if the selection\n"); log(" contains a wire, than all cell ports driven by this wire are wired,\n"); - log(" if neccessary.\n"); + log(" if necessary.\n"); log("\n"); log(" -sel_any_bit\n"); log(" it is sufficient if the driver of any bit of a cell port is selected.\n"); diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc index cef0a272e..344b03fc2 100644 --- a/passes/cmds/splitnets.cc +++ b/passes/cmds/splitnets.cc @@ -76,7 +76,7 @@ struct SplitnetsPass : public Pass { log(" -format char1[char2[char3]]\n"); log(" the first char is inserted between the net name and the bit index, the\n"); log(" second char is appended to the netname. e.g. -format () creates net\n"); - log(" names like 'mysignal(42)'. the 3rd character is the range seperation\n"); + log(" names like 'mysignal(42)'. the 3rd character is the range separation\n"); log(" character when creating multi-bit wires. the default is '[]:'.\n"); log("\n"); log(" -ports\n"); diff --git a/passes/fsm/fsm_recode.cc b/passes/fsm/fsm_recode.cc index ea10cdf80..873ee7a16 100644 --- a/passes/fsm/fsm_recode.cc +++ b/passes/fsm/fsm_recode.cc @@ -55,7 +55,7 @@ static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fs log("Recoding FSM `%s' from module `%s' using `%s' encoding:\n", cell->name.c_str(), module->name.c_str(), encoding.c_str()); if (encoding != "none" && encoding != "one-hot" && encoding != "binary" && encoding != "auto") { - log(" unkown encoding `%s': using auto instead.\n", encoding.c_str()); + log(" unknown encoding `%s': using auto instead.\n", encoding.c_str()); encoding = "auto"; } diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 2f28afb25..14bf8d1bd 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -216,7 +216,7 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla int idx = it.second.first, num = it.second.second; if (design->modules_.count(cell->type) == 0) - log_error("Array cell `%s.%s' of unkown type `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); + log_error("Array cell `%s.%s' of unknown type `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); RTLIL::Module *mod = design->modules_[cell->type]; @@ -232,7 +232,7 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla } } if (mod->wires_.count(portname) == 0) - log_error("Array cell `%s.%s' connects to unkown port `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(conn.first)); + log_error("Array cell `%s.%s' connects to unknown port `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(conn.first)); int port_size = mod->wires_.at(portname)->width; if (conn_size == port_size) continue; @@ -294,7 +294,7 @@ struct HierarchyPass : public Pass { log(" hierarchy [-check] [-top ]\n"); log(" hierarchy -generate \n"); log("\n"); - log("In parametric designs, a module might exists in serveral variations with\n"); + log("In parametric designs, a module might exists in several variations with\n"); log("different parameter values. This pass looks at all modules in the current\n"); log("design an re-runs the language frontends for the parametric modules as\n"); log("needed.\n"); @@ -309,7 +309,7 @@ struct HierarchyPass : public Pass { log("\n"); log(" -libdir \n"); log(" search for files named .v in the specified directory\n"); - log(" for unkown modules and automatically run read_verilog for each\n"); + log(" for unknown modules and automatically run read_verilog for each\n"); log(" unknown module.\n"); log("\n"); log(" -keep_positionals\n"); diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index ace6eeaf1..3ae0cd2c7 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -720,7 +720,7 @@ struct MemorySharePass : public Pass { log(" address, then this feedback path is converted to a write port with\n"); log(" byte/part enable signals.\n"); log("\n"); - log(" - When multiple write ports access the same adress then this is converted\n"); + log(" - When multiple write ports access the same address then this is converted\n"); log(" to a single write port with a more complex data and/or enable logic path.\n"); log("\n"); log(" - When multiple write ports are never accessed at the same time (a SAT\n"); diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index cc4fe4cc8..5046752f9 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -367,10 +367,10 @@ struct CleanPass : public Pass { log("\n"); log("This is identical to 'opt_clean', but less verbose.\n"); log("\n"); - log("When commands are seperated using the ';;' token, this command will be executed\n"); + log("When commands are separated using the ';;' token, this command will be executed\n"); log("between the commands.\n"); log("\n"); - log("When commands are seperated using the ';;;' token, this command will be executed\n"); + log("When commands are separated using the ';;;' token, this command will be executed\n"); log("in -purge mode between the commands.\n"); log("\n"); } diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 08ae9e929..fd0abf4a5 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -874,7 +874,7 @@ struct SatPass : public Pass { log(" -set-def-at \n"); log(" -set-any-undef-at \n"); log(" -set-all-undef-at \n"); - log(" add undef contraints in the given timestep.\n"); + log(" add undef constraints in the given timestep.\n"); log("\n"); log(" -set-init \n"); log(" set the initial value for the register driving the signal to the value\n"); -- cgit v1.2.3 From e1743b3bac8c86f3cf857892dabf66bec5573a7a Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 6 Sep 2014 11:46:07 +0200 Subject: Added "test_cell -script" --- passes/tests/test_cell.cc | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index f82bbfeb3..26aad4354 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -380,6 +380,9 @@ struct TestCellPass : public Pass { log(" -simplib\n"); log(" use \"techmap -map +/simlib.v -max_iter 2 -autoproc\"\n"); log("\n"); + log(" -script {script_file}\n"); + log(" instead of calling \"techmap\", call \"script {script_file}\".\n"); + log("\n"); log(" -v\n"); log(" print additional debug information to the console\n"); log("\n"); @@ -416,6 +419,10 @@ struct TestCellPass : public Pass { num_iter = 1; continue; } + if (args[argidx] == "-script" && argidx+1 < SIZE(args)) { + techmap_cmd = "script " + args[++argidx]; + continue; + } if (args[argidx] == "-simlib") { techmap_cmd = "techmap -map +/simlib.v -max_iter 2 -autoproc"; continue; @@ -540,7 +547,7 @@ struct TestCellPass : public Pass { Frontend::frontend_call(design, NULL, std::string(), "ilang " + ilang_file); else create_gold_module(design, cell_type, cell_types.at(cell_type)); - Pass::call(design, stringf("copy gold gate; %s gate; opt gate", techmap_cmd.c_str())); + Pass::call(design, stringf("copy gold gate; cd gate; %s; cd ..; opt -fast gate", techmap_cmd.c_str())); Pass::call(design, "miter -equiv -flatten -make_outputs -ignore_gold_x gold gate miter"); if (verbose) Pass::call(design, "dump gate"); -- cgit v1.2.3 From b847ec8a0bfb3b729278f1132ae2819676498ee7 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 6 Sep 2014 15:47:46 +0200 Subject: Added $macc cell type --- passes/tests/test_cell.cc | 55 +++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 53 insertions(+), 2 deletions(-) (limited to 'passes') diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index 26aad4354..96f08de4b 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -21,6 +21,7 @@ #include "kernel/yosys.h" #include "kernel/satgen.h" #include "kernel/consteval.h" +#include "kernel/macc.h" #include static uint32_t xorshift32_state = 123456789; @@ -38,6 +39,53 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type, RTLIL::Cell *cell = module->addCell("\\UUT", cell_type); RTLIL::Wire *wire; + if (cell_type == "$macc") + { + Macc macc; + int width = 1 + xorshift32(16); + int depth = 1 + xorshift32(6); + int mulbits = 0; + + RTLIL::Wire *wire_a = module->addWire("\\A"); + wire_a->width = 0; + wire_a->port_input = true; + + for (int i = 0; i < depth; i++) + { + int size_a = xorshift32(width) + 1; + int size_b = xorshift32(width) + 1; + + if (mulbits + size_a*size_b > 256 || xorshift32(2) == 1) + size_b = 0; + else + mulbits += size_a*size_b; + + Macc::port_t this_port; + + wire_a->width += size_a; + this_port.in_a = RTLIL::SigSpec(wire_a, wire_a->width - size_a, size_a); + + wire_a->width += size_b; + this_port.in_b = RTLIL::SigSpec(wire_a, wire_a->width - size_b, size_b); + + this_port.is_signed = xorshift32(2) == 1; + this_port.do_subtract = xorshift32(2) == 1; + macc.ports.push_back(this_port); + } + + wire = module->addWire("\\B"); + wire->width = xorshift32(xorshift32(16)+1); + wire->port_input = true; + macc.bit_ports = wire; + + wire = module->addWire("\\Y"); + wire->width = width; + wire->port_output = true; + cell->setPort("\\Y", wire); + + macc.to_cell(cell); + } + if (cell_type == "$lut") { int width = 1 + xorshift32(6); @@ -440,8 +488,10 @@ struct TestCellPass : public Pass { break; } - if (xorshift32_state == 0) - xorshift32_state = time(NULL); + if (xorshift32_state == 0) { + xorshift32_state = time(NULL) & 0x7fffffff; + log("Rng seed value: %d\n", int(xorshift32_state)); + } std::map cell_types; std::vector selected_cell_types; @@ -496,6 +546,7 @@ struct TestCellPass : public Pass { cell_types["$lut"] = "*"; cell_types["$alu"] = "ABSY"; + cell_types["$macc"] = "*"; for (; argidx < SIZE(args); argidx++) { -- cgit v1.2.3 From fa64942018a39085301d7f24832ad0ad7b0d22f1 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 6 Sep 2014 19:44:11 +0200 Subject: Added $macc SAT model --- passes/tests/test_cell.cc | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) (limited to 'passes') diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index 96f08de4b..edab51eb2 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -42,9 +42,9 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type, if (cell_type == "$macc") { Macc macc; - int width = 1 + xorshift32(16); + int width = 1 + xorshift32(8); int depth = 1 + xorshift32(6); - int mulbits = 0; + int mulbits_a = 0, mulbits_b = 0; RTLIL::Wire *wire_a = module->addWire("\\A"); wire_a->width = 0; @@ -55,10 +55,11 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type, int size_a = xorshift32(width) + 1; int size_b = xorshift32(width) + 1; - if (mulbits + size_a*size_b > 256 || xorshift32(2) == 1) + if (mulbits_a + size_a*size_b <= 96 && mulbits_b + size_a + size_b <= 16 && xorshift32(2) == 1) { + mulbits_a += size_a * size_b; + mulbits_b += size_a + size_b; + } else size_b = 0; - else - mulbits += size_a*size_b; Macc::port_t this_port; -- cgit v1.2.3 From 9329a768181d3765a08c3b264c8b0031b732c0d4 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 6 Sep 2014 20:30:46 +0200 Subject: Various bug fixes (related to $macc model testing) --- passes/tests/test_cell.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index edab51eb2..c69bd123b 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -262,7 +262,7 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, std::string uut_n gold_ce.set(gold_wire, in_value); gate_ce.set(gate_wire, in_value); - if (vlog_file.is_open()) { + if (vlog_file.is_open() && SIZE(in_value) > 0) { vlog_file << stringf(" %s = 'b%s;\n", log_id(gold_wire), in_value.as_string().c_str()); if (!vlog_pattern_info.empty()) vlog_pattern_info += " "; -- cgit v1.2.3 From 15b3c54fea80b7ccfd02c66c28ed38c610e23254 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 7 Sep 2014 17:05:41 +0200 Subject: Added "test_cell -nosat" --- passes/tests/test_cell.cc | 132 +++++++++++++++++++++++++--------------------- 1 file changed, 73 insertions(+), 59 deletions(-) (limited to 'passes') diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index c69bd123b..a38023d14 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -53,7 +53,7 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type, for (int i = 0; i < depth; i++) { int size_a = xorshift32(width) + 1; - int size_b = xorshift32(width) + 1; + int size_b = depth > 4 ? 0 : xorshift32(width) + 1; if (mulbits_a + size_a*size_b <= 96 && mulbits_b + size_a + size_b <= 16 && xorshift32(2) == 1) { mulbits_a += size_a * size_b; @@ -75,7 +75,7 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type, } wire = module->addWire("\\B"); - wire->width = xorshift32(xorshift32(16)+1); + wire->width = xorshift32(mulbits_a ? xorshift32(4)+1 : xorshift32(16)+1); wire->port_input = true; macc.bit_ports = wire; @@ -171,7 +171,7 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type, cell->check(); } -static void run_eval_test(RTLIL::Design *design, bool verbose, std::string uut_name, std::ofstream &vlog_file) +static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std::string uut_name, std::ofstream &vlog_file) { log("Eval testing:%c", verbose ? '\n' : ' '); @@ -185,10 +185,11 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, std::string uut_n SatGen satgen2(&ez2, &sigmap); satgen2.model_undef = true; - for (auto cell : gold_mod->cells()) { - satgen1.importCell(cell); - satgen2.importCell(cell); - } + if (!nosat) + for (auto cell : gold_mod->cells()) { + satgen1.importCell(cell); + satgen2.importCell(cell); + } if (vlog_file.is_open()) { @@ -325,68 +326,71 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, std::string uut_n if (verbose) log("EVAL: %s\n", out_val.as_string().c_str()); - std::vector sat1_in_sig = satgen1.importSigSpec(in_sig); - std::vector sat1_in_val = satgen1.importSigSpec(in_val); + if (!nosat) + { + std::vector sat1_in_sig = satgen1.importSigSpec(in_sig); + std::vector sat1_in_val = satgen1.importSigSpec(in_val); - std::vector sat1_model = satgen1.importSigSpec(out_sig); - std::vector sat1_model_value; + std::vector sat1_model = satgen1.importSigSpec(out_sig); + std::vector sat1_model_value; - if (!ez1.solve(sat1_model, sat1_model_value, ez1.vec_eq(sat1_in_sig, sat1_in_val))) - log_error("Evaluating sat model 1 (no undef modeling) failed!\n"); + if (!ez1.solve(sat1_model, sat1_model_value, ez1.vec_eq(sat1_in_sig, sat1_in_val))) + log_error("Evaluating sat model 1 (no undef modeling) failed!\n"); - if (verbose) { - log("SAT 1: "); - for (int i = SIZE(out_sig)-1; i >= 0; i--) - log("%c", sat1_model_value.at(i) ? '1' : '0'); - log("\n"); - } + if (verbose) { + log("SAT 1: "); + for (int i = SIZE(out_sig)-1; i >= 0; i--) + log("%c", sat1_model_value.at(i) ? '1' : '0'); + log("\n"); + } - for (int i = 0; i < SIZE(out_sig); i++) { - if (out_val[i] != RTLIL::S0 && out_val[i] != RTLIL::S1) - continue; - if (out_val[i] == RTLIL::S0 && sat1_model_value.at(i) == false) - continue; - if (out_val[i] == RTLIL::S1 && sat1_model_value.at(i) == true) - continue; - log_error("Mismatch in sat model 1 (no undef modeling) output!\n"); - } + for (int i = 0; i < SIZE(out_sig); i++) { + if (out_val[i] != RTLIL::S0 && out_val[i] != RTLIL::S1) + continue; + if (out_val[i] == RTLIL::S0 && sat1_model_value.at(i) == false) + continue; + if (out_val[i] == RTLIL::S1 && sat1_model_value.at(i) == true) + continue; + log_error("Mismatch in sat model 1 (no undef modeling) output!\n"); + } - std::vector sat2_in_def_sig = satgen2.importDefSigSpec(in_sig); - std::vector sat2_in_def_val = satgen2.importDefSigSpec(in_val); + std::vector sat2_in_def_sig = satgen2.importDefSigSpec(in_sig); + std::vector sat2_in_def_val = satgen2.importDefSigSpec(in_val); - std::vector sat2_in_undef_sig = satgen2.importUndefSigSpec(in_sig); - std::vector sat2_in_undef_val = satgen2.importUndefSigSpec(in_val); + std::vector sat2_in_undef_sig = satgen2.importUndefSigSpec(in_sig); + std::vector sat2_in_undef_val = satgen2.importUndefSigSpec(in_val); - std::vector sat2_model_def_sig = satgen2.importDefSigSpec(out_sig); - std::vector sat2_model_undef_sig = satgen2.importUndefSigSpec(out_sig); + std::vector sat2_model_def_sig = satgen2.importDefSigSpec(out_sig); + std::vector sat2_model_undef_sig = satgen2.importUndefSigSpec(out_sig); - std::vector sat2_model; - sat2_model.insert(sat2_model.end(), sat2_model_def_sig.begin(), sat2_model_def_sig.end()); - sat2_model.insert(sat2_model.end(), sat2_model_undef_sig.begin(), sat2_model_undef_sig.end()); + std::vector sat2_model; + sat2_model.insert(sat2_model.end(), sat2_model_def_sig.begin(), sat2_model_def_sig.end()); + sat2_model.insert(sat2_model.end(), sat2_model_undef_sig.begin(), sat2_model_undef_sig.end()); - std::vector sat2_model_value; + std::vector sat2_model_value; - if (!ez2.solve(sat2_model, sat2_model_value, ez2.vec_eq(sat2_in_def_sig, sat2_in_def_val), ez2.vec_eq(sat2_in_undef_sig, sat2_in_undef_val))) - log_error("Evaluating sat model 2 (undef modeling) failed!\n"); + if (!ez2.solve(sat2_model, sat2_model_value, ez2.vec_eq(sat2_in_def_sig, sat2_in_def_val), ez2.vec_eq(sat2_in_undef_sig, sat2_in_undef_val))) + log_error("Evaluating sat model 2 (undef modeling) failed!\n"); - if (verbose) { - log("SAT 2: "); - for (int i = SIZE(out_sig)-1; i >= 0; i--) - log("%c", sat2_model_value.at(SIZE(out_sig) + i) ? 'x' : sat2_model_value.at(i) ? '1' : '0'); - log("\n"); - } + if (verbose) { + log("SAT 2: "); + for (int i = SIZE(out_sig)-1; i >= 0; i--) + log("%c", sat2_model_value.at(SIZE(out_sig) + i) ? 'x' : sat2_model_value.at(i) ? '1' : '0'); + log("\n"); + } - for (int i = 0; i < SIZE(out_sig); i++) { - if (sat2_model_value.at(SIZE(out_sig) + i)) { - if (out_val[i] != RTLIL::S0 && out_val[i] != RTLIL::S1) - continue; - } else { - if (out_val[i] == RTLIL::S0 && sat2_model_value.at(i) == false) - continue; - if (out_val[i] == RTLIL::S1 && sat2_model_value.at(i) == true) - continue; + for (int i = 0; i < SIZE(out_sig); i++) { + if (sat2_model_value.at(SIZE(out_sig) + i)) { + if (out_val[i] != RTLIL::S0 && out_val[i] != RTLIL::S1) + continue; + } else { + if (out_val[i] == RTLIL::S0 && sat2_model_value.at(i) == false) + continue; + if (out_val[i] == RTLIL::S1 && sat2_model_value.at(i) == true) + continue; + } + log_error("Mismatch in sat model 2 (undef modeling) output!\n"); } - log_error("Mismatch in sat model 2 (undef modeling) output!\n"); } } @@ -432,6 +436,9 @@ struct TestCellPass : public Pass { log(" -script {script_file}\n"); log(" instead of calling \"techmap\", call \"script {script_file}\".\n"); log("\n"); + log(" -nosat\n"); + log(" do not check SAT model or run SAT equivalence checking\n"); + log("\n"); log(" -v\n"); log(" print additional debug information to the console\n"); log("\n"); @@ -447,6 +454,7 @@ struct TestCellPass : public Pass { xorshift32_state = 0; std::ofstream vlog_file; bool verbose = false; + bool nosat = false; int argidx; for (argidx = 1; argidx < SIZE(args); argidx++) @@ -476,6 +484,10 @@ struct TestCellPass : public Pass { techmap_cmd = "techmap -map +/simlib.v -max_iter 2 -autoproc"; continue; } + if (args[argidx] == "-nosat") { + nosat = true; + continue; + } if (args[argidx] == "-v") { verbose = true; continue; @@ -600,11 +612,13 @@ struct TestCellPass : public Pass { else create_gold_module(design, cell_type, cell_types.at(cell_type)); Pass::call(design, stringf("copy gold gate; cd gate; %s; cd ..; opt -fast gate", techmap_cmd.c_str())); - Pass::call(design, "miter -equiv -flatten -make_outputs -ignore_gold_x gold gate miter"); + if (!nosat) + Pass::call(design, "miter -equiv -flatten -make_outputs -ignore_gold_x gold gate miter"); if (verbose) Pass::call(design, "dump gate"); Pass::call(design, "dump gold"); - Pass::call(design, "sat -verify -enable_undef -prove trigger 0 -show-inputs -show-outputs miter"); + if (!nosat) + Pass::call(design, "sat -verify -enable_undef -prove trigger 0 -show-inputs -show-outputs miter"); std::string uut_name = stringf("uut_%s_%d", cell_type.substr(1).c_str(), i); if (vlog_file.is_open()) { Pass::call(design, stringf("copy gold %s_expr; select %s_expr", uut_name.c_str(), uut_name.c_str())); @@ -613,7 +627,7 @@ struct TestCellPass : public Pass { Backend::backend_call(design, &vlog_file, "", "verilog -selected -noexpr"); uut_names.push_back(uut_name); } - run_eval_test(design, verbose, uut_name, vlog_file); + run_eval_test(design, verbose, nosat, uut_name, vlog_file); delete design; } -- cgit v1.2.3 From 015dcdc84c5d0f9c899b520c9718ce32c9d2c8f7 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 7 Sep 2014 18:23:04 +0200 Subject: Added "maccmap" command --- passes/techmap/Makefile.inc | 1 + passes/techmap/maccmap.cc | 318 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 319 insertions(+) create mode 100644 passes/techmap/maccmap.cc (limited to 'passes') diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc index b49259a8a..da527ccfe 100644 --- a/passes/techmap/Makefile.inc +++ b/passes/techmap/Makefile.inc @@ -8,6 +8,7 @@ ifneq ($(SMALL),1) OBJS += passes/techmap/iopadmap.o OBJS += passes/techmap/hilomap.o OBJS += passes/techmap/extract.o +OBJS += passes/techmap/maccmap.o endif GENFILES += passes/techmap/techmap.inc diff --git a/passes/techmap/maccmap.cc b/passes/techmap/maccmap.cc new file mode 100644 index 000000000..49850c0a0 --- /dev/null +++ b/passes/techmap/maccmap.cc @@ -0,0 +1,318 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" +#include "kernel/macc.h" + +extern void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap = false); + +struct MaccmapWorker +{ + std::vector> bits; + RTLIL::Module *module; + int width; + + MaccmapWorker(RTLIL::Module *module, int width) : module(module), width(width) + { + bits.resize(width); + } + + void add(RTLIL::SigBit bit, int position) + { + if (position >= width || bit == RTLIL::S0) + return; + + if (bits.at(position).count(bit)) { + bits.at(position).erase(bit); + add(bit, position+1); + } else { + bits.at(position).insert(bit); + } + } + + void add(RTLIL::SigSpec a, bool is_signed, bool do_subtract) + { + a.extend(width, is_signed); + + if (do_subtract) { + a = module->Not(NEW_ID, a); + add(RTLIL::S1, 0); + } + + for (int i = 0; i < width; i++) + add(a[i], i); + } + + void add(RTLIL::SigSpec a, RTLIL::SigSpec b, bool is_signed, bool do_subtract) + { + if (SIZE(a) < SIZE(b)) + std::swap(a, b); + + a.extend(width, is_signed); + + if (SIZE(b) > width) + b.extend(width, is_signed); + + for (int i = 0; i < SIZE(b); i++) + if (is_signed && i+1 == SIZE(b)) + { + a = {module->Not(NEW_ID, a.extract(i, width-i)), RTLIL::SigSpec(0, i)}; + add(module->And(NEW_ID, a, RTLIL::SigSpec(b[i], width)), false, do_subtract); + add({b[i], RTLIL::SigSpec(0, i)}, false, do_subtract); + } + else + { + add(module->And(NEW_ID, a, RTLIL::SigSpec(b[i], width)), false, do_subtract); + a = {a.extract(0, width-1), RTLIL::S0}; + } + } + + void fulladd(RTLIL::SigSpec &in1, RTLIL::SigSpec &in2, RTLIL::SigSpec &in3, RTLIL::SigSpec &out1, RTLIL::SigSpec &out2) + { + RTLIL::SigSpec t1 = module->Xor(NEW_ID, in1, in2); + out1 = module->Xor(NEW_ID, t1, in3); + + RTLIL::SigSpec t2 = module->And(NEW_ID, in1, in2); + RTLIL::SigSpec t3 = module->And(NEW_ID, in3, t1); + out2 = module->Or(NEW_ID, t2, t3); + } + + int tree_bit_slots(int n) + { + #if 0 + int retval = 0; + while (n > 2) { + retval += n / 3; + n = 2*(n / 3) + (n % 3); + } + return retval; + #else + return std::max(n - 2, 0); + #endif + } + + RTLIL::SigSpec synth() + { + std::vector summands; + std::vector tree_sum_bits; + int unique_tree_bits = 0; + + while (1) + { + RTLIL::SigSpec summand(0, width); + bool got_data_bits = false; + + for (int i = 0; i < width; i++) + if (!bits.at(i).empty()) { + auto it = bits.at(i).begin(); + summand[i] = *it; + bits.at(i).erase(it); + got_data_bits = true; + } + + if (!got_data_bits) + break; + + summands.push_back(summand); + int free_bit_slots = tree_bit_slots(SIZE(summands)) - SIZE(tree_sum_bits); + + for (int i = 0; i < width && (1 << i) <= free_bit_slots; i++) + while (!bits.at(i).empty() && (1 << i) <= free_bit_slots) { + auto it = bits.at(i).begin(); + RTLIL::SigBit bit = *it; + bits.at(i).erase(it); + for (int k = 0; k < (1 << i); k++, free_bit_slots--) + tree_sum_bits.push_back(bit); + unique_tree_bits++; + } + } + + if (!tree_sum_bits.empty()) + log(" packed %d (%d) bits into adder tree\n", SIZE(tree_sum_bits), unique_tree_bits); + + if (SIZE(summands) == 0) + return RTLIL::SigSpec(0, width); + + if (SIZE(summands) == 1) + return summands.front(); + + while (SIZE(summands) > 2) + { + std::vector new_summands; + for (int i = 0; i < SIZE(summands); i += 3) + if (i+2 < SIZE(summands)) { + RTLIL::SigSpec in1 = summands[i]; + RTLIL::SigSpec in2 = summands[i+1]; + RTLIL::SigSpec in3 = summands[i+2]; + RTLIL::SigSpec out1, out2; + fulladd(in1, in2, in3, out1, out2); + RTLIL::SigBit extra_bit = RTLIL::S0; + if (!tree_sum_bits.empty()) { + extra_bit = tree_sum_bits.back(); + tree_sum_bits.pop_back(); + } + new_summands.push_back(out1); + new_summands.push_back({out2.extract(0, width-1), extra_bit}); + } else { + new_summands.push_back(summands[i]); + i -= 2; + } + summands.swap(new_summands); + } + + return module->Add(NEW_ID, summands.front(), summands.back()); + } +}; + +void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap) +{ + int width = SIZE(cell->getPort("\\Y")); + + Macc macc; + macc.from_cell(cell); + + RTLIL::SigSpec all_input_bits; + all_input_bits.append(cell->getPort("\\A")); + all_input_bits.append(cell->getPort("\\B")); + + if (all_input_bits.to_sigbit_set().count(RTLIL::Sx)) { + module->connect(cell->getPort("\\Y"), RTLIL::SigSpec(RTLIL::Sx, width)); + return; + } + + for (auto &port : macc.ports) + if (SIZE(port.in_b) == 0) + log(" %s %s (%d bits, %s)\n", port.do_subtract ? "sub" : "add", log_signal(port.in_a), + SIZE(port.in_a), port.is_signed ? "signed" : "unsigned"); + else + log(" %s %s * %s (%dx%d bits, %s)\n", port.do_subtract ? "sub" : "add", log_signal(port.in_a), log_signal(port.in_b), + SIZE(port.in_a), SIZE(port.in_b), port.is_signed ? "signed" : "unsigned"); + + if (SIZE(macc.bit_ports) != 0) + log(" add bits %s (%d bits)\n", log_signal(macc.bit_ports), SIZE(macc.bit_ports)); + + if (unmap) + { + typedef std::pair summand_t; + std::vector summands; + + for (auto &port : macc.ports) { + summand_t this_summand; + if (SIZE(port.in_b)) { + this_summand.first = module->addWire(NEW_ID, width); + module->addMul(NEW_ID, port.in_a, port.in_b, this_summand.first, port.is_signed); + } else if (SIZE(port.in_a) != width) { + this_summand.first = module->addWire(NEW_ID, width); + module->addPos(NEW_ID, port.in_a, this_summand.first, port.is_signed); + } else { + this_summand.first = port.in_a; + } + this_summand.second = port.do_subtract; + summands.push_back(this_summand); + } + + for (auto &bit : macc.bit_ports) + summands.push_back(summand_t(bit, false)); + + if (SIZE(summands) == 0) + summands.push_back(summand_t(RTLIL::SigSpec(0, width), false)); + + while (SIZE(summands) > 1) + { + std::vector new_summands; + for (int i = 0; i < SIZE(summands); i += 2) { + if (i+1 < SIZE(summands)) { + summand_t this_summand; + this_summand.first = module->addWire(NEW_ID, width); + this_summand.second = summands[i].second && summands[i+1].second; + if (summands[i].second == summands[i+1].second) + module->addAdd(NEW_ID, summands[i].first, summands[i+1].first, this_summand.first); + else if (summands[i].second) + module->addSub(NEW_ID, summands[i+1].first, summands[i].first, this_summand.first); + else if (summands[i+1].second) + module->addSub(NEW_ID, summands[i].first, summands[i+1].first, this_summand.first); + else + log_abort(); + new_summands.push_back(this_summand); + } else + new_summands.push_back(summands[i]); + } + summands.swap(new_summands); + } + + if (summands.front().second) + module->addNeg(NEW_ID, summands.front().first, cell->getPort("\\Y")); + else + module->connect(cell->getPort("\\Y"), summands.front().first); + } + else + { + MaccmapWorker worker(module, width); + + for (auto &port : macc.ports) + if (SIZE(port.in_b) == 0) + worker.add(port.in_a, port.is_signed, port.do_subtract); + else + worker.add(port.in_a, port.in_b, port.is_signed, port.do_subtract); + + for (auto &bit : macc.bit_ports) + worker.add(bit, 0); + + module->connect(cell->getPort("\\Y"), worker.synth()); + } +} + +struct MaccmapPass : public Pass { + MaccmapPass() : Pass("maccmap", "mapping macc cells") { } + virtual void help() + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" maccmap [-unmap] [selection]\n"); + log("\n"); + log("This pass maps $macc cells to yosys gate primitives. When the -unmap option is\n"); + log("used then the $macc cell is mapped to $and, $sub, etc. cells instead.\n"); + log("\n"); + } + virtual void execute(std::vector args, RTLIL::Design *design) + { + bool unmap_mode = false; + + log_header("Executing MACCMAP pass (map $macc cells).\n"); + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) { + if (args[argidx] == "-unmap") { + unmap_mode = true; + continue; + } + break; + } + extra_args(args, argidx, design); + + for (auto mod : design->selected_modules()) + for (auto cell : mod->selected_cells()) + if (cell->type == "$macc") { + log("Mapping %s.%s (%s).\n", log_id(mod), log_id(cell), log_id(cell->type)); + maccmap(mod, cell, unmap_mode); + mod->remove(cell); + } + } +} MaccmapPass; + -- cgit v1.2.3 From c50b841b292f82d2da1f106b4e56c5c05ac9fede Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 7 Sep 2014 18:23:37 +0200 Subject: Added 'techmap_maccmap' techmap attribute --- passes/techmap/techmap.cc | 72 ++++++++++++++++++++++++++++++++++------------- 1 file changed, 53 insertions(+), 19 deletions(-) (limited to 'passes') diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 43a94d976..93ba7c40b 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -31,6 +31,9 @@ // see simplemap.cc extern void simplemap_get_mappers(std::map &mappers); +// see maccmap.cc +extern void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap = false); + static void apply_prefix(std::string prefix, std::string &id) { if (id[0] == '\\') @@ -338,27 +341,35 @@ struct TechmapWorker if (!flatten_mode) { + std::string extmapper_name; + if (tpl->get_bool_attribute("\\techmap_simplemap")) + extmapper_name = "simplemap"; + + if (tpl->get_bool_attribute("\\techmap_maccmap")) + extmapper_name = "maccmap"; + + if (!extmapper_name.empty()) { cell->type = cell_type; if (extern_mode && !in_recursion) { - std::string m_name = stringf("$extern:simplemap:%s", log_id(cell->type)); + std::string m_name = stringf("$extern:%s:%s", extmapper_name.c_str(), log_id(cell->type)); for (auto &c : cell->parameters) m_name += stringf(":%s=%s", log_id(c.first), log_signal(c.second)); - RTLIL::Module *simplemap_module = design->module(m_name); + RTLIL::Module *extmapper_module = design->module(m_name); - if (simplemap_module == nullptr) + if (extmapper_module == nullptr) { - simplemap_module = design->addModule(m_name); - RTLIL::Cell *simplemap_cell = simplemap_module->addCell(cell->type, cell); + extmapper_module = design->addModule(m_name); + RTLIL::Cell *extmapper_cell = extmapper_module->addCell(cell->type, cell); int port_counter = 1; - for (auto &c : simplemap_cell->connections_) { - RTLIL::Wire *w = simplemap_module->addWire(c.first, SIZE(c.second)); + for (auto &c : extmapper_cell->connections_) { + RTLIL::Wire *w = extmapper_module->addWire(c.first, SIZE(c.second)); if (w->name == "\\Y" || w->name == "\\Q") w->port_output = true; else @@ -367,25 +378,45 @@ struct TechmapWorker c.second = w; } - simplemap_module->check(); + extmapper_module->check(); + + if (extmapper_name == "simplemap") { + log("Creating %s with simplemap.\n", log_id(extmapper_module)); + if (simplemap_mappers.count(extmapper_cell->type) == 0) + log_error("No simplemap mapper for cell type %s found!\n", log_id(extmapper_cell->type)); + simplemap_mappers.at(extmapper_cell->type)(extmapper_module, extmapper_cell); + } + + if (extmapper_name == "maccmap") { + log("Creating %s with maccmap.\n", log_id(extmapper_module)); + if (extmapper_cell->type != "$macc") + log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(extmapper_cell->type)); + maccmap(extmapper_module, extmapper_cell); + } - log("Creating %s with simplemap.\n", log_id(simplemap_module)); - if (simplemap_mappers.count(simplemap_cell->type) == 0) - log_error("No simplemap mapper for cell type %s found!\n", RTLIL::id2cstr(simplemap_cell->type)); - simplemap_mappers.at(simplemap_cell->type)(simplemap_module, simplemap_cell); - simplemap_module->remove(simplemap_cell); + extmapper_module->remove(extmapper_cell); } - log("%s %s.%s (%s) to %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(simplemap_module)); - cell->type = simplemap_module->name; + log("%s %s.%s (%s) to %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(extmapper_module)); + cell->type = extmapper_module->name; cell->parameters.clear(); } else { - log("%s %s.%s (%s) with simplemap.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type)); - if (simplemap_mappers.count(cell->type) == 0) - log_error("No simplemap mapper for cell type %s found!\n", RTLIL::id2cstr(cell->type)); - simplemap_mappers.at(cell->type)(module, cell); + log("%s %s.%s (%s) with %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), extmapper_name.c_str()); + + if (extmapper_name == "simplemap") { + if (simplemap_mappers.count(cell->type) == 0) + log_error("No simplemap mapper for cell type %s found!\n", RTLIL::id2cstr(cell->type)); + simplemap_mappers.at(cell->type)(module, cell); + } + + if (extmapper_name == "maccmap") { + if (cell->type != "$macc") + log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(cell->type)); + maccmap(module, cell); + } + module->remove(cell); cell = NULL; } @@ -752,6 +783,9 @@ struct TechmapPass : public Pass { log("When a module in the map file has the 'techmap_simplemap' attribute set, techmap\n"); log("will use 'simplemap' (see 'help simplemap') to map cells matching the module.\n"); log("\n"); + log("When a module in the map file has the 'techmap_maccmap' attribute set, techmap\n"); + log("will use 'maccmap' (see 'help maccmap') to map cells matching the module.\n"); + log("\n"); log("All wires in the modules from the map file matching the pattern _TECHMAP_*\n"); log("or *._TECHMAP_* are special wires that are used to pass instructions from\n"); log("the mapping module to the techmap command. At the moment the following special\n"); -- cgit v1.2.3 From 6747a7047e105b7dae79ed8b8e1111d1ff8888d2 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 8 Sep 2014 11:12:39 +0200 Subject: Added "test_cell -const" --- passes/tests/test_cell.cc | 47 +++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 45 insertions(+), 2 deletions(-) (limited to 'passes') diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index a38023d14..310c3bdfe 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -33,7 +33,7 @@ static uint32_t xorshift32(uint32_t limit) { return xorshift32_state % limit; } -static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type, std::string cell_type_flags) +static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type, std::string cell_type_flags, bool constmode) { RTLIL::Module *module = design->addModule("\\gold"); RTLIL::Cell *cell = module->addCell("\\UUT", cell_type); @@ -166,6 +166,41 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type, cell->setPort("\\CO", wire); } + if (constmode) + { + auto conn_list = cell->connections(); + for (auto &conn : conn_list) + { + RTLIL::SigSpec sig = conn.second; + + if (SIZE(sig) == 0 || sig[0].wire == nullptr || sig[0].wire->port_output) + continue; + + int n, m; + switch (xorshift32(5)) + { + case 0: + n = xorshift32(SIZE(sig) + 1); + for (int i = 0; i < n; i++) + sig[i] = xorshift32(2) == 1 ? RTLIL::S1 : RTLIL::S0; + break; + case 1: + n = xorshift32(SIZE(sig) + 1); + for (int i = n; i < SIZE(sig); i++) + sig[i] = xorshift32(2) == 1 ? RTLIL::S1 : RTLIL::S0; + break; + case 2: + n = xorshift32(SIZE(sig)); + m = xorshift32(SIZE(sig)); + for (int i = std::min(n, m); i < std::max(n, m); i++) + sig[i] = xorshift32(2) == 1 ? RTLIL::S1 : RTLIL::S0; + break; + } + + cell->setPort(conn.first, sig); + } + } + module->fixup_ports(); cell->fixup_parameters(); cell->check(); @@ -436,6 +471,9 @@ struct TestCellPass : public Pass { log(" -script {script_file}\n"); log(" instead of calling \"techmap\", call \"script {script_file}\".\n"); log("\n"); + log(" -const\n"); + log(" set some input bits to random constant values\n"); + log("\n"); log(" -nosat\n"); log(" do not check SAT model or run SAT equivalence checking\n"); log("\n"); @@ -454,6 +492,7 @@ struct TestCellPass : public Pass { xorshift32_state = 0; std::ofstream vlog_file; bool verbose = false; + bool constmode = false; bool nosat = false; int argidx; @@ -484,6 +523,10 @@ struct TestCellPass : public Pass { techmap_cmd = "techmap -map +/simlib.v -max_iter 2 -autoproc"; continue; } + if (args[argidx] == "-const") { + constmode = true; + continue; + } if (args[argidx] == "-nosat") { nosat = true; continue; @@ -610,7 +653,7 @@ struct TestCellPass : public Pass { if (cell_type == "ilang") Frontend::frontend_call(design, NULL, std::string(), "ilang " + ilang_file); else - create_gold_module(design, cell_type, cell_types.at(cell_type)); + create_gold_module(design, cell_type, cell_types.at(cell_type), constmode); Pass::call(design, stringf("copy gold gate; cd gate; %s; cd ..; opt -fast gate", techmap_cmd.c_str())); if (!nosat) Pass::call(design, "miter -equiv -flatten -make_outputs -ignore_gold_x gold gate miter"); -- cgit v1.2.3 From 1a88e47396305bd6b5ee2a7a91a1d014ebd37c10 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 8 Sep 2014 11:21:58 +0200 Subject: Trim msb/lsb zero bits from full adder in maccmap --- passes/techmap/maccmap.cc | 32 +++++++++++++++++++++++++++----- 1 file changed, 27 insertions(+), 5 deletions(-) (limited to 'passes') diff --git a/passes/techmap/maccmap.cc b/passes/techmap/maccmap.cc index 49850c0a0..a9c223fa8 100644 --- a/passes/techmap/maccmap.cc +++ b/passes/techmap/maccmap.cc @@ -85,12 +85,34 @@ struct MaccmapWorker void fulladd(RTLIL::SigSpec &in1, RTLIL::SigSpec &in2, RTLIL::SigSpec &in3, RTLIL::SigSpec &out1, RTLIL::SigSpec &out2) { - RTLIL::SigSpec t1 = module->Xor(NEW_ID, in1, in2); - out1 = module->Xor(NEW_ID, t1, in3); + int start_index = 0, stop_index = SIZE(in1); - RTLIL::SigSpec t2 = module->And(NEW_ID, in1, in2); - RTLIL::SigSpec t3 = module->And(NEW_ID, in3, t1); - out2 = module->Or(NEW_ID, t2, t3); + while (start_index < stop_index && in1[start_index] == RTLIL::S0 && in2[start_index] == RTLIL::S0 && in3[start_index] == RTLIL::S0) + start_index++; + + while (start_index < stop_index && in1[stop_index-1] == RTLIL::S0 && in2[stop_index-1] == RTLIL::S0 && in3[stop_index-1] == RTLIL::S0) + stop_index--; + + if (start_index == stop_index) + { + out1 = RTLIL::SigSpec(0, SIZE(in1)); + out2 = RTLIL::SigSpec(0, SIZE(in1)); + } + else + { + RTLIL::SigSpec out_zeros_lsb(0, start_index), out_zeros_msb(0, SIZE(in1)-stop_index); + + in1 = in1.extract(start_index, stop_index-start_index); + in2 = in2.extract(start_index, stop_index-start_index); + in3 = in3.extract(start_index, stop_index-start_index); + + RTLIL::SigSpec t1 = module->Xor(NEW_ID, in1, in2); + out1 = {out_zeros_msb, module->Xor(NEW_ID, t1, in3), out_zeros_lsb}; + + RTLIL::SigSpec t2 = module->And(NEW_ID, in1, in2); + RTLIL::SigSpec t3 = module->And(NEW_ID, in3, t1); + out2 = {out_zeros_msb, module->Or(NEW_ID, t2, t3), out_zeros_lsb}; + } } int tree_bit_slots(int n) -- cgit v1.2.3 From d46bac330520f91ee5bf8027abe98a8f9389f696 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 8 Sep 2014 12:15:39 +0200 Subject: Added "$fa" cell type --- passes/techmap/maccmap.cc | 22 ++++++++++++++++------ passes/tests/test_cell.cc | 31 +++++++++++++++++++++++++++++++ 2 files changed, 47 insertions(+), 6 deletions(-) (limited to 'passes') diff --git a/passes/techmap/maccmap.cc b/passes/techmap/maccmap.cc index a9c223fa8..c2dc9aa8a 100644 --- a/passes/techmap/maccmap.cc +++ b/passes/techmap/maccmap.cc @@ -106,12 +106,20 @@ struct MaccmapWorker in2 = in2.extract(start_index, stop_index-start_index); in3 = in3.extract(start_index, stop_index-start_index); - RTLIL::SigSpec t1 = module->Xor(NEW_ID, in1, in2); - out1 = {out_zeros_msb, module->Xor(NEW_ID, t1, in3), out_zeros_lsb}; - - RTLIL::SigSpec t2 = module->And(NEW_ID, in1, in2); - RTLIL::SigSpec t3 = module->And(NEW_ID, in3, t1); - out2 = {out_zeros_msb, module->Or(NEW_ID, t2, t3), out_zeros_lsb}; + int width = SIZE(in1); + RTLIL::Wire *w1 = module->addWire(NEW_ID, width); + RTLIL::Wire *w2 = module->addWire(NEW_ID, width); + + RTLIL::Cell *cell = module->addCell(NEW_ID, "$fa"); + cell->setParam("\\WIDTH", width); + cell->setPort("\\A", in1); + cell->setPort("\\B", in2); + cell->setPort("\\C", in3); + cell->setPort("\\Y", w1); + cell->setPort("\\X", w2); + + out1 = {out_zeros_msb, w1, out_zeros_lsb}; + out2 = {out_zeros_msb, w2, out_zeros_lsb}; } } @@ -198,6 +206,8 @@ struct MaccmapWorker summands.swap(new_summands); } + log_assert(tree_sum_bits.empty()); + return module->Add(NEW_ID, summands.front(), summands.back()); } }; diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index 310c3bdfe..72fb74d3a 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -39,6 +39,36 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type, RTLIL::Cell *cell = module->addCell("\\UUT", cell_type); RTLIL::Wire *wire; + if (cell_type == "$fa") + { + int width = 1 + xorshift32(8); + + wire = module->addWire("\\A"); + wire->width = width; + wire->port_input = true; + cell->setPort("\\A", wire); + + wire = module->addWire("\\B"); + wire->width = width; + wire->port_input = true; + cell->setPort("\\B", wire); + + wire = module->addWire("\\C"); + wire->width = width; + wire->port_input = true; + cell->setPort("\\C", wire); + + wire = module->addWire("\\X"); + wire->width = width; + wire->port_output = true; + cell->setPort("\\X", wire); + + wire = module->addWire("\\Y"); + wire->width = width; + wire->port_output = true; + cell->setPort("\\Y", wire); + } + if (cell_type == "$macc") { Macc macc; @@ -603,6 +633,7 @@ struct TestCellPass : public Pass { cell_types["$lut"] = "*"; cell_types["$alu"] = "ABSY"; cell_types["$macc"] = "*"; + cell_types["$fa"] = "*"; for (; argidx < SIZE(args); argidx++) { -- cgit v1.2.3 From af0c8873bbc13eea10b3d705061b4cf68fe27c17 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 8 Sep 2014 13:28:23 +0200 Subject: Added $lcu cell type --- passes/tests/test_cell.cc | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index 72fb74d3a..1fa90b540 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -69,6 +69,30 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type, cell->setPort("\\Y", wire); } + if (cell_type == "$lcu") + { + int width = 1 + xorshift32(8); + + wire = module->addWire("\\P"); + wire->width = width; + wire->port_input = true; + cell->setPort("\\P", wire); + + wire = module->addWire("\\G"); + wire->width = width; + wire->port_input = true; + cell->setPort("\\G", wire); + + wire = module->addWire("\\CI"); + wire->port_input = true; + cell->setPort("\\CI", wire); + + wire = module->addWire("\\CO"); + wire->width = width; + wire->port_output = true; + cell->setPort("\\CO", wire); + } + if (cell_type == "$macc") { Macc macc; @@ -477,7 +501,7 @@ struct TestCellPass : public Pass { log("\n"); log(" test_cell [options] {cell-types}\n"); log("\n"); - log("Tests the internal implementation of the given cell type (for example '$mux')\n"); + log("Tests the internal implementation of the given cell type (for example '$add')\n"); log("by comparing SAT solver, EVAL and TECHMAP implementations of the cell types..\n"); log("\n"); log("Run with 'all' instead of a cell type to run the test on all supported\n"); @@ -632,6 +656,7 @@ struct TestCellPass : public Pass { cell_types["$lut"] = "*"; cell_types["$alu"] = "ABSY"; + cell_types["$lcu"] = "*"; cell_types["$macc"] = "*"; cell_types["$fa"] = "*"; -- cgit v1.2.3 From aab0e3bf702640806c6e81d42e922f938b0e0085 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 14 Sep 2014 10:01:30 +0200 Subject: Cleanup in wreduce --- passes/opt/wreduce.cc | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) (limited to 'passes') diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc index 321a1aa55..9e43bb902 100644 --- a/passes/opt/wreduce.cc +++ b/passes/opt/wreduce.cc @@ -26,23 +26,20 @@ using namespace RTLIL; PRIVATE_NAMESPACE_BEGIN -static inline std::set &operator<<(std::set &set, IdString id) { - set.insert(id); - return set; -} - struct WreduceConfig { std::set supported_cell_types; WreduceConfig() { - supported_cell_types << "$not" << "$pos" << "$neg"; - supported_cell_types << "$and" << "$or" << "$xor" << "$xnor"; - supported_cell_types << "$shl" << "$shr" << "$sshl" << "$sshr" << "$shift" << "$shiftx"; - supported_cell_types << "$lt" << "$le" << "$eq" << "$ne" << "$eqx" << "$nex" << "$ge" << "$gt"; - supported_cell_types << "$add" << "$sub"; // << "$mul" << "$div" << "$mod" << "$pow" - supported_cell_types << "$mux" << "$pmux"; + supported_cell_types = { + "$not", "$pos", "$neg", + "$and", "$or", "$xor", "$xnor", + "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", + "$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt", + "$add", "$sub", // "$mul", "$div", "$mod", "$pow", + "$mux", "$pmux" + }; } }; -- cgit v1.2.3 From ff157fb74fc1b46408c075a0827adbca1b8c496e Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 14 Sep 2014 10:02:00 +0200 Subject: alumacc skeleton --- passes/techmap/Makefile.inc | 1 + passes/techmap/alumacc.cc | 63 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 64 insertions(+) create mode 100644 passes/techmap/alumacc.cc (limited to 'passes') diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc index da527ccfe..72998f87b 100644 --- a/passes/techmap/Makefile.inc +++ b/passes/techmap/Makefile.inc @@ -9,6 +9,7 @@ OBJS += passes/techmap/iopadmap.o OBJS += passes/techmap/hilomap.o OBJS += passes/techmap/extract.o OBJS += passes/techmap/maccmap.o +OBJS += passes/techmap/alumacc.o endif GENFILES += passes/techmap/techmap.inc diff --git a/passes/techmap/alumacc.cc b/passes/techmap/alumacc.cc new file mode 100644 index 000000000..0e2fe4e7f --- /dev/null +++ b/passes/techmap/alumacc.cc @@ -0,0 +1,63 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" +#include "kernel/macc.h" + +struct AlumaccWorker +{ + RTLIL::Module *module; + + AlumaccWorker(RTLIL::Module *module) : module(module) + { + } +}; + +struct AlumaccPass : public Pass { + AlumaccPass() : Pass("alumacc", "extract ALU and MACC cells") { } + virtual void help() + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" alumacc [selection]\n"); + log("\n"); + log("This pass translates arithmetic operations $add, $mul, $lt, etc. to $alu and\n"); + log("$macc cells.\n"); + log("\n"); + } + virtual void execute(std::vector args, RTLIL::Design *design) + { + log_header("Executing ALUMACC pass (create $alu and $macc cells).\n"); + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) { + // if (args[argidx] == "-foobar") { + // foobar_mode = true; + // continue; + // } + break; + } + extra_args(args, argidx, design); + + for (auto mod : design->selected_modules()) { + AlumaccWorker worker(mod); + } + } +} AlumaccPass; + -- cgit v1.2.3 From 0b72f0acb13e14d329cf408d22b636d61174eb8e Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 14 Sep 2014 10:45:28 +0200 Subject: Basic $macc extract in alumacc --- passes/techmap/alumacc.cc | 108 ++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 104 insertions(+), 4 deletions(-) (limited to 'passes') diff --git a/passes/techmap/alumacc.cc b/passes/techmap/alumacc.cc index 0e2fe4e7f..757dc7cf2 100644 --- a/passes/techmap/alumacc.cc +++ b/passes/techmap/alumacc.cc @@ -18,14 +18,112 @@ */ #include "kernel/yosys.h" +#include "kernel/sigtools.h" #include "kernel/macc.h" struct AlumaccWorker { RTLIL::Module *module; + SigMap sigmap; - AlumaccWorker(RTLIL::Module *module) : module(module) + struct maccnode_t { + Macc macc; + RTLIL::Cell *cell; + RTLIL::SigSpec y; + int users; + }; + + std::map bit_users; + std::map sig_macc; + + AlumaccWorker(RTLIL::Module *module) : module(module), sigmap(module) { } + + void count_bit_users() + { + for (auto port : module->ports) + for (auto bit : sigmap(module->wire(port))) + bit_users[bit]++; + + for (auto cell : module->cells()) + for (auto &conn : cell->connections()) + for (auto bit : sigmap(conn.second)) + bit_users[bit]++; + } + + void extract_macc() + { + for (auto cell : module->selected_cells()) + { + if (!cell->type.in("$pos", "$neg", "$add", "$sub", "$mul")) + continue; + + maccnode_t *n = new maccnode_t; + Macc::port_t new_port; + + n->cell = cell; + n->y = sigmap(cell->getPort("\\Y")); + n->users = 0; + + for (auto bit : n->y) + n->users = std::max(n->users, bit_users.at(bit) - 1); + + + if (cell->type.in("$pos", "$neg")) + { + new_port.in_a = sigmap(cell->getPort("\\A")); + new_port.is_signed = cell->getParam("\\A_SIGNED").as_bool(); + new_port.do_subtract = cell->type == "$neg"; + n->macc.ports.push_back(new_port); + } + + if (cell->type.in("$add", "$sub")) + { + new_port.in_a = sigmap(cell->getPort("\\A")); + new_port.is_signed = cell->getParam("\\A_SIGNED").as_bool(); + new_port.do_subtract = false; + n->macc.ports.push_back(new_port); + + new_port.in_a = sigmap(cell->getPort("\\B")); + new_port.is_signed = cell->getParam("\\B_SIGNED").as_bool(); + new_port.do_subtract = cell->type == "$sub"; + n->macc.ports.push_back(new_port); + } + + if (cell->type.in("$mul")) + { + new_port.in_a = sigmap(cell->getPort("\\A")); + new_port.in_b = sigmap(cell->getPort("\\B")); + new_port.is_signed = cell->getParam("\\A_SIGNED").as_bool(); + new_port.do_subtract = false; + n->macc.ports.push_back(new_port); + } + + log_assert(sig_macc.count(n->y) == 0); + sig_macc[n->y] = n; + } + } + + void replace_macc() { + for (auto &it : sig_macc) + { + auto n = it.second; + auto cell = module->addCell(NEW_ID, "$macc"); + n->macc.to_cell(cell); + cell->setPort("\\Y", n->y); + cell->fixup_parameters(); + module->remove(n->cell); + delete n; + } + + sig_macc.clear(); + } + + void run() + { + count_bit_users(); + extract_macc(); + replace_macc(); } }; @@ -55,9 +153,11 @@ struct AlumaccPass : public Pass { } extra_args(args, argidx, design); - for (auto mod : design->selected_modules()) { - AlumaccWorker worker(mod); - } + for (auto mod : design->selected_modules()) + if (!mod->has_processes_warn()) { + AlumaccWorker worker(mod); + worker.run(); + } } } AlumaccPass; -- cgit v1.2.3 From 7b16c63101d46274cb3b93907489c8403e5d9bc5 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 14 Sep 2014 11:21:37 +0200 Subject: Merge $macc cells in alumacc pass --- passes/techmap/alumacc.cc | 60 ++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 59 insertions(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/techmap/alumacc.cc b/passes/techmap/alumacc.cc index 757dc7cf2..5a15e8258 100644 --- a/passes/techmap/alumacc.cc +++ b/passes/techmap/alumacc.cc @@ -57,6 +57,8 @@ struct AlumaccWorker if (!cell->type.in("$pos", "$neg", "$add", "$sub", "$mul")) continue; + log(" creating $macc model for %s (%s).\n", log_id(cell), log_id(cell->type)); + maccnode_t *n = new maccnode_t; Macc::port_t new_port; @@ -67,7 +69,6 @@ struct AlumaccWorker for (auto bit : n->y) n->users = std::max(n->users, bit_users.at(bit) - 1); - if (cell->type.in("$pos", "$neg")) { new_port.in_a = sigmap(cell->getPort("\\A")); @@ -103,6 +104,60 @@ struct AlumaccWorker } } + void merge_macc() + { + while (1) + { + std::set delete_nodes; + + for (auto &it : sig_macc) + { + auto n = it.second; + + if (delete_nodes.count(n)) + continue; + + for (int i = 0; i < SIZE(n->macc.ports); i++) + { + auto &port = n->macc.ports[i]; + + if (SIZE(port.in_b) > 0 || sig_macc.count(port.in_a) == 0) + continue; + + auto other_n = sig_macc.at(port.in_a); + + if (other_n->users > 1) + continue; + + if (SIZE(other_n->y) != SIZE(n->y)) + continue; + + log(" merging $macc model for %s into %s.\n", log_id(other_n->cell), log_id(n->cell)); + + bool do_subtract = port.do_subtract; + for (int j = 0; j < SIZE(other_n->macc.ports); j++) { + if (do_subtract) + other_n->macc.ports[j].do_subtract = !other_n->macc.ports[j].do_subtract; + if (j == 0) + n->macc.ports[i--] = other_n->macc.ports[j]; + else + n->macc.ports.push_back(other_n->macc.ports[j]); + } + + delete_nodes.insert(other_n); + } + } + + if (delete_nodes.empty()) + break; + + for (auto n : delete_nodes) { + sig_macc.erase(n->y); + delete n; + } + } + } + void replace_macc() { for (auto &it : sig_macc) @@ -121,8 +176,11 @@ struct AlumaccWorker void run() { + log("Extracting $alu and $macc cells in module %s:\n", log_id(module)); + count_bit_users(); extract_macc(); + merge_macc(); replace_macc(); } }; -- cgit v1.2.3 From 0df1d9ad72ad16af6c1d2d0c5f412914f322e326 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 14 Sep 2014 13:23:44 +0200 Subject: Extract $alu cells in alumacc --- passes/techmap/alumacc.cc | 297 +++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 296 insertions(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/techmap/alumacc.cc b/passes/techmap/alumacc.cc index 5a15e8258..2a4f8178a 100644 --- a/passes/techmap/alumacc.cc +++ b/passes/techmap/alumacc.cc @@ -33,10 +33,78 @@ struct AlumaccWorker int users; }; + struct alunode_t + { + std::vector cells; + RTLIL::SigSpec a, b, c, y; + std::vector> cmp; + bool is_signed, invert_b; + + RTLIL::Cell *alu_cell; + RTLIL::SigSpec cached_lt, cached_gt, cached_eq, cached_ne; + RTLIL::SigSpec cached_cf, cached_of, cached_sf; + + RTLIL::SigSpec get_lt() { + if (SIZE(cached_lt) == 0) + cached_lt = is_signed ? alu_cell->module->Xor(NEW_ID, get_of(), get_sf()) : get_cf(); + return cached_lt; + } + + RTLIL::SigSpec get_gt() { + if (SIZE(cached_gt) == 0) + cached_gt = alu_cell->module->Not(NEW_ID, alu_cell->module->Or(NEW_ID, get_lt(), get_eq())); + return cached_gt; + } + + RTLIL::SigSpec get_eq() { + if (SIZE(cached_eq) == 0) + cached_eq = alu_cell->module->ReduceAnd(NEW_ID, alu_cell->getPort("\\X")); + return cached_eq; + } + + RTLIL::SigSpec get_ne() { + if (SIZE(cached_ne) == 0) + cached_ne = alu_cell->module->Not(NEW_ID, get_eq()); + return cached_ne; + } + + RTLIL::SigSpec get_cf() { + if (SIZE(cached_cf) == 0) { + cached_cf = alu_cell->getPort("\\CO"); + log_assert(SIZE(cached_cf) >= 1); + cached_cf = alu_cell->module->Not(NEW_ID, cached_cf[SIZE(cached_cf)-1]); + } + return cached_cf; + } + + RTLIL::SigSpec get_of() { + if (SIZE(cached_of) == 0) { + cached_of = {alu_cell->getPort("\\CO"), alu_cell->getPort("\\CI")}; + log_assert(SIZE(cached_of) >= 2); + cached_of = alu_cell->module->Xor(NEW_ID, cached_of[SIZE(cached_of)-1], cached_of[SIZE(cached_of)-2]); + } + return cached_of; + } + + RTLIL::SigSpec get_sf() { + if (SIZE(cached_sf) == 0) { + cached_sf = alu_cell->getPort("\\Y"); + cached_sf = cached_sf[SIZE(cached_sf)-1]; + } + return cached_sf; + } + }; + std::map bit_users; std::map sig_macc; + std::map> sig_alu; + int macc_counter, alu_counter; - AlumaccWorker(RTLIL::Module *module) : module(module), sigmap(module) { } + AlumaccWorker(RTLIL::Module *module) : module(module), sigmap(module) + { + macc_counter = 0; + alu_counter = 0; + } void count_bit_users() { @@ -158,12 +226,96 @@ struct AlumaccWorker } } + void macc_to_alu() + { + std::set delete_nodes; + + for (auto &it : sig_macc) + { + auto n = it.second; + RTLIL::SigSpec A, B, C = n->macc.bit_ports; + bool a_signed = false, b_signed = false; + bool subtract_b = false; + alunode_t *alunode; + + for (auto &port : n->macc.ports) + if (SIZE(port.in_b) > 0) { + goto next_macc; + } else if (SIZE(port.in_a) == 1 && !port.is_signed && !port.do_subtract) { + C.append(port.in_a); + } else if (SIZE(A) || port.do_subtract) { + if (SIZE(B)) + goto next_macc; + B = port.in_a; + b_signed = port.is_signed; + subtract_b = port.do_subtract; + } else { + if (SIZE(A)) + goto next_macc; + A = port.in_a; + a_signed = port.is_signed; + } + + if (!a_signed || !b_signed) { + if (SIZE(A) == SIZE(n->y)) + a_signed = false; + if (SIZE(B) == SIZE(n->y)) + b_signed = false; + if (a_signed != b_signed) + goto next_macc; + } + + if (SIZE(A) == 0 && SIZE(C) > 0) { + A = C[0]; + C.remove(0); + } + + if (SIZE(B) == 0 && SIZE(C) > 0) { + B = C[0]; + C.remove(0); + } + + if (subtract_b) + C.append(RTLIL::S1); + + if (SIZE(C) > 1) + goto next_macc; + + if (!subtract_b && B < A) + std::swap(A, B); + + log(" creating $alu model for $macc %s.\n", log_id(n->cell)); + + alunode = new alunode_t; + alunode->cells.push_back(n->cell); + alunode->is_signed = a_signed; + alunode->invert_b = subtract_b; + + alunode->a = A; + alunode->b = B; + alunode->c = C; + alunode->y = n->y; + + sig_alu[RTLIL::SigSig(A, B)].insert(alunode); + delete_nodes.insert(n); + next_macc:; + } + + for (auto n : delete_nodes) { + sig_macc.erase(n->y); + delete n; + } + } + void replace_macc() { + macc_counter += SIZE(sig_macc); + for (auto &it : sig_macc) { auto n = it.second; auto cell = module->addCell(NEW_ID, "$macc"); + log(" creating $macc cell for %s: %s\n", log_id(n->cell), log_id(cell)); n->macc.to_cell(cell); cell->setPort("\\Y", n->y); cell->fixup_parameters(); @@ -174,6 +326,144 @@ struct AlumaccWorker sig_macc.clear(); } + void extract_cmp_alu() + { + std::vector lge_cells, eq_cells; + + for (auto cell : module->selected_cells()) + { + if (cell->type.in("$lt", "$le", "$ge", "$gt")) + lge_cells.push_back(cell); + if (cell->type.in("$eq", "$eqx", "$ne", "$nex")) + eq_cells.push_back(cell); + } + + for (auto cell : lge_cells) + { + log(" creating $alu model for %s (%s):", log_id(cell), log_id(cell->type)); + + bool cmp_less = cell->type.in("$lt", "$le"); + bool cmp_equal = cell->type.in("$le", "$ge"); + bool is_signed = cell->getParam("\\A_SIGNED").as_bool(); + + RTLIL::SigSpec A = sigmap(cell->getPort("\\A")); + RTLIL::SigSpec B = sigmap(cell->getPort("\\B")); + RTLIL::SigSpec Y = sigmap(cell->getPort("\\Y")); + + if (B < A) { + cmp_less = !cmp_less; + std::swap(A, B); + } + + alunode_t *n = nullptr; + + for (auto node : sig_alu[RTLIL::SigSig(A, B)]) + if (node->is_signed == is_signed && node->invert_b && node->c == RTLIL::S1) { + n = node; + break; + } + + if (n == nullptr) { + n = new alunode_t; + n->a = A; + n->b = B; + n->c = RTLIL::S1; + n->y = module->addWire(NEW_ID, std::max(SIZE(A), SIZE(B))); + n->is_signed = is_signed; + n->invert_b = true; + sig_alu[RTLIL::SigSig(A, B)].insert(n); + log(" new $alu\n"); + } else { + log(" merged with %s.\n", log_id(n->cells.front())); + } + + n->cells.push_back(cell); + n->cmp.push_back(std::make_tuple(cmp_less, !cmp_less, cmp_equal, false, Y)); + } + + for (auto cell : eq_cells) + { + bool cmp_equal = cell->type.in("$eq", "$eqx"); + bool is_signed = cell->getParam("\\A_SIGNED").as_bool(); + + RTLIL::SigSpec A = sigmap(cell->getPort("\\A")); + RTLIL::SigSpec B = sigmap(cell->getPort("\\B")); + RTLIL::SigSpec Y = sigmap(cell->getPort("\\Y")); + + if (B < A) + std::swap(A, B); + + alunode_t *n = nullptr; + + for (auto node : sig_alu[RTLIL::SigSig(A, B)]) + if (node->is_signed == is_signed && node->invert_b && node->c == RTLIL::S1) { + n = node; + break; + } + + if (n != nullptr) { + log(" creating $alu model for %s (%s): merged with %s.\n", log_id(cell), log_id(cell->type), log_id(n->cells.front())); + n->cells.push_back(cell); + n->cmp.push_back(std::make_tuple(false, false, cmp_equal, !cmp_equal, Y)); + } + } + } + + void replace_alu() + { + alu_counter += SIZE(sig_alu); + + for (auto &it1 : sig_alu) + for (auto n : it1.second) + { + n->alu_cell = module->addCell(NEW_ID, "$alu"); + + log(" creating $alu cell for "); + for (int i = 0; i < SIZE(n->cells); i++) + log("%s%s", i ? ", ": "", log_id(n->cells[i])); + log(": %s\n", log_id(n->alu_cell)); + + RTLIL::Wire *x = module->addWire(NEW_ID, SIZE(n->y)); + RTLIL::Wire *co = module->addWire(NEW_ID, SIZE(n->y)); + + n->alu_cell->setPort("\\A", n->a); + n->alu_cell->setPort("\\B", n->b); + n->alu_cell->setPort("\\CI", SIZE(n->c) ? n->c : RTLIL::S0); + n->alu_cell->setPort("\\BI", n->invert_b ? RTLIL::S1 : RTLIL::S0); + n->alu_cell->setPort("\\Y", n->y); + n->alu_cell->setPort("\\X", x); + n->alu_cell->setPort("\\CO", co); + n->alu_cell->fixup_parameters(); + + for (auto &it : n->cmp) + { + bool cmp_lt = std::get<0>(it); + bool cmp_gt = std::get<1>(it); + bool cmp_eq = std::get<2>(it); + bool cmp_ne = std::get<3>(it); + RTLIL::SigSpec cmp_y = std::get<4>(it); + + RTLIL::SigSpec sig; + if (cmp_lt) sig.append(n->get_lt()); + if (cmp_gt) sig.append(n->get_gt()); + if (cmp_eq) sig.append(n->get_eq()); + if (cmp_ne) sig.append(n->get_ne()); + + if (SIZE(sig) > 1) + sig = module->ReduceOr(NEW_ID, sig); + + sig.extend(SIZE(cmp_y)); + module->connect(cmp_y, sig); + } + + for (auto c : n->cells) + module->remove(c); + delete n; + } + + sig_alu.clear(); + } + void run() { log("Extracting $alu and $macc cells in module %s:\n", log_id(module)); @@ -181,7 +471,12 @@ struct AlumaccWorker count_bit_users(); extract_macc(); merge_macc(); + macc_to_alu(); replace_macc(); + extract_cmp_alu(); + replace_alu(); + + log(" created %d $alu and %d $macc cells.\n", alu_counter, macc_counter); } }; -- cgit v1.2.3 From b34ca151853aa2b5052afd56269a53079e17429d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 14 Sep 2014 14:00:14 +0200 Subject: alumacc fix for $pos cells --- passes/techmap/alumacc.cc | 37 ++++++++++++++++++++++++------------- 1 file changed, 24 insertions(+), 13 deletions(-) (limited to 'passes') diff --git a/passes/techmap/alumacc.cc b/passes/techmap/alumacc.cc index 2a4f8178a..d6ee9e66c 100644 --- a/passes/techmap/alumacc.cc +++ b/passes/techmap/alumacc.cc @@ -281,7 +281,7 @@ struct AlumaccWorker if (SIZE(C) > 1) goto next_macc; - if (!subtract_b && B < A) + if (!subtract_b && B < A && SIZE(B)) std::swap(A, B); log(" creating $alu model for $macc %s.\n", log_id(n->cell)); @@ -309,13 +309,14 @@ struct AlumaccWorker void replace_macc() { - macc_counter += SIZE(sig_macc); - for (auto &it : sig_macc) { auto n = it.second; auto cell = module->addCell(NEW_ID, "$macc"); + macc_counter++; + log(" creating $macc cell for %s: %s\n", log_id(n->cell), log_id(cell)); + n->macc.to_cell(cell); cell->setPort("\\Y", n->y); cell->fixup_parameters(); @@ -350,7 +351,7 @@ struct AlumaccWorker RTLIL::SigSpec B = sigmap(cell->getPort("\\B")); RTLIL::SigSpec Y = sigmap(cell->getPort("\\Y")); - if (B < A) { + if (B < A && SIZE(B)) { cmp_less = !cmp_less; std::swap(A, B); } @@ -390,7 +391,7 @@ struct AlumaccWorker RTLIL::SigSpec B = sigmap(cell->getPort("\\B")); RTLIL::SigSpec Y = sigmap(cell->getPort("\\Y")); - if (B < A) + if (B < A && SIZE(B)) std::swap(A, B); alunode_t *n = nullptr; @@ -411,29 +412,38 @@ struct AlumaccWorker void replace_alu() { - alu_counter += SIZE(sig_alu); - for (auto &it1 : sig_alu) for (auto n : it1.second) { + if (SIZE(n->b) == 0 && SIZE(n->c) == 0 && SIZE(n->cmp) == 0) + { + n->alu_cell = module->addPos(NEW_ID, n->a, n->y, n->is_signed); + + log(" creating $pos cell for "); + for (int i = 0; i < SIZE(n->cells); i++) + log("%s%s", i ? ", ": "", log_id(n->cells[i])); + log(": %s\n", log_id(n->alu_cell)); + + goto delete_node; + } + n->alu_cell = module->addCell(NEW_ID, "$alu"); + alu_counter++; log(" creating $alu cell for "); for (int i = 0; i < SIZE(n->cells); i++) log("%s%s", i ? ", ": "", log_id(n->cells[i])); log(": %s\n", log_id(n->alu_cell)); - RTLIL::Wire *x = module->addWire(NEW_ID, SIZE(n->y)); - RTLIL::Wire *co = module->addWire(NEW_ID, SIZE(n->y)); - n->alu_cell->setPort("\\A", n->a); n->alu_cell->setPort("\\B", n->b); n->alu_cell->setPort("\\CI", SIZE(n->c) ? n->c : RTLIL::S0); n->alu_cell->setPort("\\BI", n->invert_b ? RTLIL::S1 : RTLIL::S0); n->alu_cell->setPort("\\Y", n->y); - n->alu_cell->setPort("\\X", x); - n->alu_cell->setPort("\\CO", co); - n->alu_cell->fixup_parameters(); + n->alu_cell->setPort("\\X", module->addWire(NEW_ID, SIZE(n->y))); + n->alu_cell->setPort("\\CO", module->addWire(NEW_ID, SIZE(n->y))); + n->alu_cell->fixup_parameters(n->is_signed, n->is_signed); + log_cell(n->alu_cell); for (auto &it : n->cmp) { @@ -456,6 +466,7 @@ struct AlumaccWorker module->connect(cmp_y, sig); } + delete_node: for (auto c : n->cells) module->remove(c); delete n; -- cgit v1.2.3 From 124e759280fecf9e8698b7e09c5d9e87d8fb3f96 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 14 Sep 2014 14:49:26 +0200 Subject: Added techmap_wrap attribute --- passes/techmap/techmap.cc | 33 ++++++++++++++++++++++++++++----- 1 file changed, 28 insertions(+), 5 deletions(-) (limited to 'passes') diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 93ba7c40b..8332e988f 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -349,22 +349,26 @@ struct TechmapWorker if (tpl->get_bool_attribute("\\techmap_maccmap")) extmapper_name = "maccmap"; + if (tpl->attributes.count("\\techmap_wrap")) + extmapper_name = "wrap"; + if (!extmapper_name.empty()) { cell->type = cell_type; - if (extern_mode && !in_recursion) + if ((extern_mode && !in_recursion) || extmapper_name == "wrap") { std::string m_name = stringf("$extern:%s:%s", extmapper_name.c_str(), log_id(cell->type)); for (auto &c : cell->parameters) m_name += stringf(":%s=%s", log_id(c.first), log_signal(c.second)); - RTLIL::Module *extmapper_module = design->module(m_name); + RTLIL::Design *extmapper_design = extern_mode && !in_recursion ? design : tpl->design; + RTLIL::Module *extmapper_module = extmapper_design->module(m_name); if (extmapper_module == nullptr) { - extmapper_module = design->addModule(m_name); + extmapper_module = extmapper_design->addModule(m_name); RTLIL::Cell *extmapper_cell = extmapper_module->addCell(cell->type, cell); int port_counter = 1; @@ -378,6 +382,7 @@ struct TechmapWorker c.second = w; } + extmapper_module->fixup_ports(); extmapper_module->check(); if (extmapper_name == "simplemap") { @@ -385,6 +390,7 @@ struct TechmapWorker if (simplemap_mappers.count(extmapper_cell->type) == 0) log_error("No simplemap mapper for cell type %s found!\n", log_id(extmapper_cell->type)); simplemap_mappers.at(extmapper_cell->type)(extmapper_module, extmapper_cell); + extmapper_module->remove(extmapper_cell); } if (extmapper_name == "maccmap") { @@ -392,14 +398,26 @@ struct TechmapWorker if (extmapper_cell->type != "$macc") log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(extmapper_cell->type)); maccmap(extmapper_module, extmapper_cell); + extmapper_module->remove(extmapper_cell); } - extmapper_module->remove(extmapper_cell); + if (extmapper_name == "wrap") { + std::string cmd_string = tpl->attributes.at("\\techmap_wrap").decode_string(); + log("Running \"%s\" on wrapper %s.\n", cmd_string.c_str(), log_id(extmapper_module)); + Pass::call_on_module(extmapper_design, extmapper_module, cmd_string); + log_continue = true; + } } - log("%s %s.%s (%s) to %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(extmapper_module)); cell->type = extmapper_module->name; cell->parameters.clear(); + + if (!extern_mode || in_recursion) { + tpl = extmapper_module; + goto use_wrapper_tpl; + } + + log("%s %s.%s (%s) to %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(extmapper_module)); } else { @@ -426,6 +444,7 @@ struct TechmapWorker break; } + use_wrapper_tpl: for (auto conn : cell->connections()) { if (conn.first.substr(0, 1) == "$") continue; @@ -786,6 +805,10 @@ struct TechmapPass : public Pass { log("When a module in the map file has the 'techmap_maccmap' attribute set, techmap\n"); log("will use 'maccmap' (see 'help maccmap') to map cells matching the module.\n"); log("\n"); + log("When a module in the map file has the 'techmap_wrap' attribute set, techmap\n"); + log("will create a wrapper for the cell and then run the command string that the\n"); + log("attribute is set to on the wrapper module.\n"); + log("\n"); log("All wires in the modules from the map file matching the pattern _TECHMAP_*\n"); log("or *._TECHMAP_* are special wires that are used to pass instructions from\n"); log("the mapping module to the techmap command. At the moment the following special\n"); -- cgit v1.2.3 From 014bb34e0ecd058545fafbf1dbb0ba5064714c1d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 14 Sep 2014 14:49:53 +0200 Subject: Various fixes/cleanups in alumacc and maccmap --- passes/techmap/alumacc.cc | 1 - passes/techmap/maccmap.cc | 12 +++++++++++- 2 files changed, 11 insertions(+), 2 deletions(-) (limited to 'passes') diff --git a/passes/techmap/alumacc.cc b/passes/techmap/alumacc.cc index d6ee9e66c..3fddcef13 100644 --- a/passes/techmap/alumacc.cc +++ b/passes/techmap/alumacc.cc @@ -443,7 +443,6 @@ struct AlumaccWorker n->alu_cell->setPort("\\X", module->addWire(NEW_ID, SIZE(n->y))); n->alu_cell->setPort("\\CO", module->addWire(NEW_ID, SIZE(n->y))); n->alu_cell->fixup_parameters(n->is_signed, n->is_signed); - log_cell(n->alu_cell); for (auto &it : n->cmp) { diff --git a/passes/techmap/maccmap.cc b/passes/techmap/maccmap.cc index c2dc9aa8a..e17231cb5 100644 --- a/passes/techmap/maccmap.cc +++ b/passes/techmap/maccmap.cc @@ -208,7 +208,17 @@ struct MaccmapWorker log_assert(tree_sum_bits.empty()); - return module->Add(NEW_ID, summands.front(), summands.back()); + RTLIL::Cell *c = module->addCell(NEW_ID, "$alu"); + c->setPort("\\A", summands.front()); + c->setPort("\\B", summands.back()); + c->setPort("\\CI", RTLIL::S0); + c->setPort("\\BI", RTLIL::S0); + c->setPort("\\Y", module->addWire(NEW_ID, width)); + c->setPort("\\X", module->addWire(NEW_ID, width)); + c->setPort("\\CO", module->addWire(NEW_ID, width)); + c->fixup_parameters(); + + return c->getPort("\\Y"); } }; -- cgit v1.2.3 From 7e156a541909ec857fbaa4a08940d0aaf0d27d4b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 14 Sep 2014 15:34:36 +0200 Subject: Fixed techmap_wrap for techmap_celltype --- passes/techmap/techmap.cc | 25 ++++++++++++++++--------- 1 file changed, 16 insertions(+), 9 deletions(-) (limited to 'passes') diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 8332e988f..ed466faa1 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -363,6 +363,9 @@ struct TechmapWorker for (auto &c : cell->parameters) m_name += stringf(":%s=%s", log_id(c.first), log_signal(c.second)); + if (extmapper_name == "wrap") + m_name += ":" + sha1(tpl->attributes.at("\\techmap_wrap").decode_string()); + RTLIL::Design *extmapper_design = extern_mode && !in_recursion ? design : tpl->design; RTLIL::Module *extmapper_module = extmapper_design->module(m_name); @@ -444,7 +447,6 @@ struct TechmapWorker break; } - use_wrapper_tpl: for (auto conn : cell->connections()) { if (conn.first.substr(0, 1) == "$") continue; @@ -511,16 +513,21 @@ struct TechmapWorker } } - std::pair> key(tpl_name, parameters); - if (techmap_cache.count(key) > 0) { - tpl = techmap_cache[key]; + if (0) { + use_wrapper_tpl:; + // do not register techmap_wrap modules with techmap_cache } else { - if (cell->parameters.size() != 0) { - derived_name = tpl->derive(map, parameters); - tpl = map->module(derived_name); - log_continue = true; + std::pair> key(tpl_name, parameters); + if (techmap_cache.count(key) > 0) { + tpl = techmap_cache[key]; + } else { + if (cell->parameters.size() != 0) { + derived_name = tpl->derive(map, parameters); + tpl = map->module(derived_name); + log_continue = true; + } + techmap_cache[key] = tpl; } - techmap_cache[key] = tpl; } if (flatten_mode) { -- cgit v1.2.3 From 2cbdbaad1f81f76422455901f1987d886fa10d19 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 15 Sep 2014 11:29:09 +0200 Subject: Fixed wreduce $shiftx handling --- passes/opt/wreduce.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc index 9e43bb902..58a6d1b0d 100644 --- a/passes/opt/wreduce.cc +++ b/passes/opt/wreduce.cc @@ -186,7 +186,7 @@ struct WreduceWorker bool port_a_signed = false; bool port_b_signed = false; - if (max_port_a_size >= 0) + if (max_port_a_size >= 0 && cell->type != "$shiftx") run_reduce_inport(cell, 'A', max_port_a_size, port_a_signed, did_something); if (max_port_b_size >= 0) -- cgit v1.2.3 From fcbda0741166bfbc3244f05f92e9cc5f925160e6 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 15 Sep 2014 12:00:19 +0200 Subject: Improved maccmap tree bit packing --- passes/techmap/maccmap.cc | 66 +++++++++++++++++++++++++++++++++++------------ 1 file changed, 50 insertions(+), 16 deletions(-) (limited to 'passes') diff --git a/passes/techmap/maccmap.cc b/passes/techmap/maccmap.cc index e17231cb5..2d625eefe 100644 --- a/passes/techmap/maccmap.cc +++ b/passes/techmap/maccmap.cc @@ -126,14 +126,14 @@ struct MaccmapWorker int tree_bit_slots(int n) { #if 0 - int retval = 0; + int retval = 1; while (n > 2) { retval += n / 3; n = 2*(n / 3) + (n % 3); } return retval; #else - return std::max(n - 2, 0); + return std::max(n - 1, 0); #endif } @@ -142,6 +142,7 @@ struct MaccmapWorker std::vector summands; std::vector tree_sum_bits; int unique_tree_bits = 0; + int count_tree_words = 0; while (1) { @@ -160,27 +161,55 @@ struct MaccmapWorker break; summands.push_back(summand); - int free_bit_slots = tree_bit_slots(SIZE(summands)) - SIZE(tree_sum_bits); - for (int i = 0; i < width && (1 << i) <= free_bit_slots; i++) - while (!bits.at(i).empty() && (1 << i) <= free_bit_slots) { - auto it = bits.at(i).begin(); - RTLIL::SigBit bit = *it; - bits.at(i).erase(it); - for (int k = 0; k < (1 << i); k++, free_bit_slots--) - tree_sum_bits.push_back(bit); - unique_tree_bits++; - } + while (1) + { + int free_bit_slots = tree_bit_slots(SIZE(summands)) - SIZE(tree_sum_bits); + + int max_depth = 0, max_position = 0; + for (int i = 0; i < width; i++) + if (max_depth <= SIZE(bits.at(i))) { + max_depth = SIZE(bits.at(i)); + max_position = i; + } + + if (max_depth == 0 || max_position > 4) + break; + + int required_bits = 0; + for (int i = 0; i <= max_position; i++) + if (SIZE(bits.at(i)) == max_depth) + required_bits += 1 << i; + + if (required_bits > free_bit_slots) + break; + + for (int i = 0; i <= max_position; i++) + if (SIZE(bits.at(i)) == max_depth) { + auto it = bits.at(i).begin(); + RTLIL::SigBit bit = *it; + for (int k = 0; k < (1 << i); k++, free_bit_slots--) + tree_sum_bits.push_back(bit); + bits.at(i).erase(it); + unique_tree_bits++; + } + + count_tree_words++; + } } if (!tree_sum_bits.empty()) - log(" packed %d (%d) bits into adder tree\n", SIZE(tree_sum_bits), unique_tree_bits); + log(" packed %d (%d) bits / %d words into adder tree\n", SIZE(tree_sum_bits), unique_tree_bits, count_tree_words); - if (SIZE(summands) == 0) + if (SIZE(summands) == 0) { + log_assert(tree_sum_bits.empty()); return RTLIL::SigSpec(0, width); + } - if (SIZE(summands) == 1) + if (SIZE(summands) == 1) { + log_assert(tree_sum_bits.empty()); return summands.front(); + } while (SIZE(summands) > 2) { @@ -206,7 +235,6 @@ struct MaccmapWorker summands.swap(new_summands); } - log_assert(tree_sum_bits.empty()); RTLIL::Cell *c = module->addCell(NEW_ID, "$alu"); c->setPort("\\A", summands.front()); @@ -218,6 +246,12 @@ struct MaccmapWorker c->setPort("\\CO", module->addWire(NEW_ID, width)); c->fixup_parameters(); + if (!tree_sum_bits.empty()) { + c->setPort("\\CI", tree_sum_bits.back()); + tree_sum_bits.pop_back(); + } + log_assert(tree_sum_bits.empty()); + return c->getPort("\\Y"); } }; -- cgit v1.2.3 From b470c480e97fe112810d04a6051d1029ce1e8c29 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 15 Sep 2014 12:22:03 +0200 Subject: Added the obvious optimizations to alumacc $macc generator --- passes/techmap/alumacc.cc | 1 + 1 file changed, 1 insertion(+) (limited to 'passes') diff --git a/passes/techmap/alumacc.cc b/passes/techmap/alumacc.cc index 3fddcef13..c52e0e4ca 100644 --- a/passes/techmap/alumacc.cc +++ b/passes/techmap/alumacc.cc @@ -317,6 +317,7 @@ struct AlumaccWorker log(" creating $macc cell for %s: %s\n", log_id(n->cell), log_id(cell)); + n->macc.optimize(SIZE(n->y)); n->macc.to_cell(cell); cell->setPort("\\Y", n->y); cell->fixup_parameters(); -- cgit v1.2.3 From b86410b2ab902b587cbd8f6b14c13caf684af725 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 15 Sep 2014 12:42:11 +0200 Subject: More aggressive $macc merging in alumacc --- passes/techmap/alumacc.cc | 38 +++++++++++++++++++++++++++++++++++++- 1 file changed, 37 insertions(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/techmap/alumacc.cc b/passes/techmap/alumacc.cc index c52e0e4ca..1115eead5 100644 --- a/passes/techmap/alumacc.cc +++ b/passes/techmap/alumacc.cc @@ -172,6 +172,42 @@ struct AlumaccWorker } } + static bool macc_may_overflow(Macc &macc, int width, bool is_signed) + { + std::vector port_sizes; + + for (auto &port : macc.ports) { + if (port.is_signed != is_signed) + return true; + if (!port.is_signed && port.do_subtract) + return true; + if (SIZE(port.in_b)) + port_sizes.push_back(SIZE(port.in_a) + SIZE(port.in_b)); + else + port_sizes.push_back(SIZE(port.in_a)); + } + + std::sort(port_sizes.begin(), port_sizes.end()); + + int acc_sum = 0, acc_shift = 0; + for (int sz : port_sizes) { + while ((sz - acc_shift) > 20) { + if (acc_sum & 1) + acc_sum++; + acc_sum = acc_sum >> 1; + acc_shift++; + } + acc_sum += (1 << (sz - acc_shift)) - 1; + } + + while (acc_sum) { + acc_sum = acc_sum >> 1; + acc_shift++; + } + + return acc_shift > width; + } + void merge_macc() { while (1) @@ -197,7 +233,7 @@ struct AlumaccWorker if (other_n->users > 1) continue; - if (SIZE(other_n->y) != SIZE(n->y)) + if (SIZE(other_n->y) != SIZE(n->y) && macc_may_overflow(other_n->macc, SIZE(other_n->y), port.is_signed)) continue; log(" merging $macc model for %s into %s.\n", log_id(other_n->cell), log_id(n->cell)); -- cgit v1.2.3 From ae02d9cb9a990bfbe76d056fd341d88a9a5f129c Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 16 Sep 2014 12:40:58 +0200 Subject: Fixed $memwr/$memrd order in memory_dff --- passes/memory/memory_dff.cc | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'passes') diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index cdd0b85e2..302ab3abf 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -169,12 +169,14 @@ static void handle_module(RTLIL::Module *module, bool flag_wr_only) if (cell->type == "$dff") dff_cells.push_back(cell); - for (auto cell : module->selected_cells()) { + for (auto cell : module->selected_cells()) if (cell->type == "$memwr" && !cell->parameters["\\CLK_ENABLE"].as_bool()) - handle_wr_cell(module, dff_cells, cell); - if (!flag_wr_only && cell->type == "$memrd" && !cell->parameters["\\CLK_ENABLE"].as_bool()) + handle_wr_cell(module, dff_cells, cell); + + if (!flag_wr_only) + for (auto cell : module->selected_cells()) + if (cell->type == "$memrd" && !cell->parameters["\\CLK_ENABLE"].as_bool()) handle_rd_cell(module, dff_cells, cell); - } } struct MemoryDffPass : public Pass { -- cgit v1.2.3 From 9ae559b9909a5042cb60b44b020d87b3d5b60b8b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 16 Sep 2014 12:45:05 +0200 Subject: Fixed $_NOR vs. $_NOR_ typo in abc.cc --- passes/abc/abc.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index fd56668cf..b18f88352 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -166,7 +166,7 @@ static void extract_cell(RTLIL::Cell *cell, bool keepff) return; } - if (cell->type.in("$_AND_", "$_NAND_", "$_OR_", "$_NOR", "$_XOR_", "$_XNOR_")) + if (cell->type.in("$_AND_", "$_NAND_", "$_OR_", "$_NOR_", "$_XOR_", "$_XNOR_")) { RTLIL::SigSpec sig_a = cell->getPort("\\A"); RTLIL::SigSpec sig_b = cell->getPort("\\B"); -- cgit v1.2.3 From 815fab9d7136506aec0d38300e68bd88810195d3 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 18 Sep 2014 12:57:37 +0200 Subject: Added "abc -fast" --- passes/abc/abc.cc | 37 +++++++++++++++++++++++++++++++------ 1 file changed, 31 insertions(+), 6 deletions(-) (limited to 'passes') diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index b18f88352..11818bf15 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -34,6 +34,11 @@ #define ABC_COMMAND_LUT "strash; scorr -v; ifraig -v; retime -v; strash; dch -vf; if -v" #define ABC_COMMAND_DFL "strash; scorr -v; ifraig -v; retime -v; strash; dch -vf; map -v" +#define ABC_FAST_COMMAND_LIB "strash; scorr -v; retime -v {D}; strash; map -v {D}" +#define ABC_FAST_COMMAND_CTR "strash; scorr -v; retime -v {D}; strash; map -v {D}; buffer -v; upsize -v {D}; dnsize -v {D}; stime -p" +#define ABC_FAST_COMMAND_LUT "strash; scorr -v; retime -v; strash; if -v" +#define ABC_FAST_COMMAND_DFL "strash; scorr -v; retime -v; strash; map -v" + #include "kernel/register.h" #include "kernel/sigtools.h" #include "kernel/log.h" @@ -479,7 +484,7 @@ static std::string fold_abc_cmd(std::string str) static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::string script_file, std::string exe_file, std::string liberty_file, std::string constr_file, bool cleanup, int lut_mode, bool dff_mode, std::string clk_str, - bool keepff, std::string delay_target) + bool keepff, std::string delay_target, bool fast_mode) { module = current_module; map_autoidx = autoidx++; @@ -512,11 +517,11 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std } else abc_command = stringf("source %s", script_file.c_str()); } else if (lut_mode) - abc_command = ABC_COMMAND_LUT; + abc_command = fast_mode ? ABC_FAST_COMMAND_LUT : ABC_COMMAND_LUT; else if (!liberty_file.empty()) - abc_command = constr_file.empty() ? ABC_COMMAND_LIB : ABC_COMMAND_CTR; + abc_command = constr_file.empty() ? (fast_mode ? ABC_FAST_COMMAND_LIB : ABC_COMMAND_LIB) : (fast_mode ? ABC_FAST_COMMAND_CTR : ABC_COMMAND_CTR); else - abc_command = ABC_COMMAND_DFL; + abc_command = fast_mode ? ABC_FAST_COMMAND_DFL : ABC_COMMAND_DFL; for (size_t pos = abc_command.find("{D}"); pos != std::string::npos; pos = abc_command.find("{D}", pos)) abc_command = abc_command.substr(0, pos) + delay_target + abc_command.substr(pos+3); @@ -1041,6 +1046,22 @@ struct AbcPass : public Pass { log(" otherwise:\n"); log("%s\n", fold_abc_cmd(ABC_COMMAND_DFL).c_str()); log("\n"); + log(" -fast\n"); + log(" use different default scripts that are slightly faster (at the cost\n"); + log(" of output quality):\n"); + log("\n"); + log(" for -liberty without -constr:\n"); + log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_LIB).c_str()); + log("\n"); + log(" for -liberty with -constr:\n"); + log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_CTR).c_str()); + log("\n"); + log(" for -lut:\n"); + log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_LUT).c_str()); + log("\n"); + log(" otherwise:\n"); + log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_DFL).c_str()); + log("\n"); log(" -liberty \n"); log(" generate netlists for the specified cell library (using the liberty\n"); log(" file format).\n"); @@ -1097,7 +1118,7 @@ struct AbcPass : public Pass { std::string exe_file = proc_self_dirname() + "yosys-abc"; std::string script_file, liberty_file, constr_file, clk_str, delay_target; - bool dff_mode = false, keepff = false, cleanup = true; + bool fast_mode = false, dff_mode = false, keepff = false, cleanup = true; int lut_mode = 0; size_t argidx; @@ -1138,6 +1159,10 @@ struct AbcPass : public Pass { lut_mode = atoi(args[++argidx].c_str()); continue; } + if (arg == "-fast") { + fast_mode = true; + continue; + } if (arg == "-dff") { dff_mode = true; continue; @@ -1168,7 +1193,7 @@ struct AbcPass : public Pass { if (mod_it.second->processes.size() > 0) log("Skipping module %s as it contains processes.\n", mod_it.second->name.c_str()); else - abc_module(design, mod_it.second, script_file, exe_file, liberty_file, constr_file, cleanup, lut_mode, dff_mode, clk_str, keepff, delay_target); + abc_module(design, mod_it.second, script_file, exe_file, liberty_file, constr_file, cleanup, lut_mode, dff_mode, clk_str, keepff, delay_target, fast_mode); } assign_map.clear(); -- cgit v1.2.3 From f56b92818b05c898740df76e0a15bf94ce533e17 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 18 Sep 2014 19:00:21 +0200 Subject: Do not run "scorr" in "abc -fast" --- passes/abc/abc.cc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'passes') diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index 11818bf15..d99eff7d7 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -34,10 +34,10 @@ #define ABC_COMMAND_LUT "strash; scorr -v; ifraig -v; retime -v; strash; dch -vf; if -v" #define ABC_COMMAND_DFL "strash; scorr -v; ifraig -v; retime -v; strash; dch -vf; map -v" -#define ABC_FAST_COMMAND_LIB "strash; scorr -v; retime -v {D}; strash; map -v {D}" -#define ABC_FAST_COMMAND_CTR "strash; scorr -v; retime -v {D}; strash; map -v {D}; buffer -v; upsize -v {D}; dnsize -v {D}; stime -p" -#define ABC_FAST_COMMAND_LUT "strash; scorr -v; retime -v; strash; if -v" -#define ABC_FAST_COMMAND_DFL "strash; scorr -v; retime -v; strash; map -v" +#define ABC_FAST_COMMAND_LIB "retime -v {D}; map -v {D}" +#define ABC_FAST_COMMAND_CTR "retime -v {D}; map -v {D}; buffer -v; upsize -v {D}; dnsize -v {D}; stime -p" +#define ABC_FAST_COMMAND_LUT "retime -v; if -v" +#define ABC_FAST_COMMAND_DFL "retime -v; map -v" #include "kernel/register.h" #include "kernel/sigtools.h" -- cgit v1.2.3 From f7bb8f244beff135aa2ef6c771bece45ce240c5d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 19 Sep 2014 11:13:10 +0200 Subject: Alphabetically sort port names in "show" output --- passes/cmds/show.cc | 3 +++ 1 file changed, 3 insertions(+) (limited to 'passes') diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index 0451ebc29..2218eded2 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -355,6 +355,9 @@ struct ShowWorker out_ports.push_back(conn.first); } + std::sort(in_ports.begin(), in_ports.end(), RTLIL::sort_by_id_str()); + std::sort(out_ports.begin(), out_ports.end(), RTLIL::sort_by_id_str()); + std::string label_string = "{{"; for (auto &p : in_ports) -- cgit v1.2.3 From 3aa003c8e9c207758797e533cb85514cdb0db2c6 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 19 Sep 2014 13:15:31 +0200 Subject: Using "NOT" instead of "INV" as cell name in default abc genlib file --- passes/abc/abc.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'passes') diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index d99eff7d7..75368e3ce 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -712,7 +712,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std fprintf(f, "GATE ZERO 1 Y=CONST0;\n"); fprintf(f, "GATE ONE 1 Y=CONST1;\n"); fprintf(f, "GATE BUF 1 Y=A; PIN * NONINV 1 999 1 0 1 0\n"); - fprintf(f, "GATE INV 1 Y=!A; PIN * INV 1 999 1 0 1 0\n"); + fprintf(f, "GATE NOT 1 Y=!A; PIN * INV 1 999 1 0 1 0\n"); fprintf(f, "GATE AND 1 Y=A*B; PIN * NONINV 1 999 1 0 1 0\n"); fprintf(f, "GATE NAND 1 Y=!(A*B); PIN * INV 1 999 1 0 1 0\n"); fprintf(f, "GATE OR 1 Y=A+B; PIN * NONINV 1 999 1 0 1 0\n"); @@ -854,7 +854,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std module->connect(conn); continue; } - if (c->type == "\\INV") { + if (c->type == "\\NOT") { RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_NOT_"); cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)])); cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)])); -- cgit v1.2.3 From 5827826098fd827c7ac964ed45e99f92d63d9267 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 19 Sep 2014 14:05:41 +0200 Subject: Small improvements in "abc" command handle_loops() function --- passes/abc/abc.cc | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) (limited to 'passes') diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index 75368e3ce..f1d56b23a 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -287,8 +287,9 @@ static void dump_loop_graph(FILE *f, int &nr, std::map> &edge log("Dumping loop state graph to slide %d.\n", ++nr); - fprintf(f, "digraph slide%d {\n", nr); - fprintf(f, " rankdir=\"LR\";\n"); + fprintf(f, "digraph \"slide%d\" {\n", nr); + fprintf(f, " label=\"slide%d\";\n", nr); + fprintf(f, " rankdir=\"TD\";\n"); std::set nodes; for (auto &e : edges) { @@ -375,10 +376,10 @@ static void handle_loops() int id2 = edge_it.first; RTLIL::Wire *w1 = signal_list[id1].bit.wire; RTLIL::Wire *w2 = signal_list[id2].bit.wire; - if (w1 != NULL) - continue; - else if (w2 == NULL) + if (w1 == NULL) id1 = id2; + else if (w2 == NULL) + continue; else if (w1->name[0] == '$' && w2->name[0] == '\\') id1 = id2; else if (w1->name[0] == '\\' && w2->name[0] == '$') @@ -387,7 +388,7 @@ static void handle_loops() id1 = id2; else if (edges[id1].size() > edges[id2].size()) continue; - else if (w2->name < w1->name) + else if (w2->name.str() < w1->name.str()) id1 = id2; } @@ -396,6 +397,8 @@ static void handle_loops() continue; } + log_assert(signal_list[id1].bit.wire != NULL); + std::stringstream sstr; sstr << "$abcloop$" << (autoidx++); RTLIL::Wire *wire = module->addWire(sstr.str()); -- cgit v1.2.3 From a7758ef953eccff9295ec9f152ec1b6bef831f89 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 19 Sep 2014 15:51:34 +0200 Subject: Added "test_abcloop" command --- passes/tests/Makefile.inc | 1 + passes/tests/test_abcloop.cc | 285 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 286 insertions(+) create mode 100644 passes/tests/test_abcloop.cc (limited to 'passes') diff --git a/passes/tests/Makefile.inc b/passes/tests/Makefile.inc index a60cfe66a..531943d78 100644 --- a/passes/tests/Makefile.inc +++ b/passes/tests/Makefile.inc @@ -1,4 +1,5 @@ OBJS += passes/tests/test_autotb.o OBJS += passes/tests/test_cell.o +OBJS += passes/tests/test_abcloop.o diff --git a/passes/tests/test_abcloop.cc b/passes/tests/test_abcloop.cc new file mode 100644 index 000000000..0a0ceb1d1 --- /dev/null +++ b/passes/tests/test_abcloop.cc @@ -0,0 +1,285 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2014 Clifford Wolf + * Copyright (C) 2014 Johann Glaser + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" +#include "kernel/satgen.h" + +static uint32_t xorshift32_state = 123456789; + +static uint32_t xorshift32(uint32_t limit) { + xorshift32_state ^= xorshift32_state << 13; + xorshift32_state ^= xorshift32_state >> 17; + xorshift32_state ^= xorshift32_state << 5; + return xorshift32_state % limit; +} + +static RTLIL::Wire *getw(std::vector &wires, RTLIL::Wire *w) +{ + while (1) { + int idx = xorshift32(SIZE(wires)); + if (wires[idx] != w && !wires[idx]->port_output) + return wires[idx]; + } +} + +static void test_abcloop() +{ + log("Rng seed value: %u\n", int(xorshift32_state)); + + RTLIL::Design *design = new RTLIL::Design; + RTLIL::Module *module = nullptr; + RTLIL::SigSpec in_sig, out_sig; + + bool truthtab[16][4]; + int create_cycles = 0; + + while (1) + { + module = design->addModule("\\uut"); + create_cycles++; + + in_sig = {}; + out_sig = {}; + + std::vector wires; + + for (int i = 0; i < 4; i++) { + RTLIL::Wire *w = module->addWire(stringf("\\i%d", i)); + w->port_input = true; + wires.push_back(w); + in_sig.append(w); + } + + for (int i = 0; i < 4; i++) { + RTLIL::Wire *w = module->addWire(stringf("\\o%d", i)); + w->port_output = true; + wires.push_back(w); + out_sig.append(w); + } + + for (int i = 0; i < 16; i++) { + RTLIL::Wire *w = module->addWire(stringf("\\t%d", i)); + wires.push_back(w); + } + + for (auto w : wires) + if (!w->port_input) + switch (xorshift32(12)) + { + case 0: + module->addNotGate(w->name.str() + "g", getw(wires, w), w); + break; + case 1: + module->addAndGate(w->name.str() + "g", getw(wires, w), getw(wires, w), w); + break; + case 2: + module->addNandGate(w->name.str() + "g", getw(wires, w), getw(wires, w), w); + break; + case 3: + module->addOrGate(w->name.str() + "g", getw(wires, w), getw(wires, w), w); + break; + case 4: + module->addNorGate(w->name.str() + "g", getw(wires, w), getw(wires, w), w); + break; + case 5: + module->addXorGate(w->name.str() + "g", getw(wires, w), getw(wires, w), w); + break; + case 6: + module->addXnorGate(w->name.str() + "g", getw(wires, w), getw(wires, w), w); + break; + case 7: + module->addMuxGate(w->name.str() + "g", getw(wires, w), getw(wires, w), getw(wires, w), w); + break; + case 8: + module->addAoi3Gate(w->name.str() + "g", getw(wires, w), getw(wires, w), getw(wires, w), w); + break; + case 9: + module->addOai3Gate(w->name.str() + "g", getw(wires, w), getw(wires, w), getw(wires, w), w); + break; + case 10: + module->addAoi4Gate(w->name.str() + "g", getw(wires, w), getw(wires, w), getw(wires, w), getw(wires, w), w); + break; + case 11: + module->addOai4Gate(w->name.str() + "g", getw(wires, w), getw(wires, w), getw(wires, w), getw(wires, w), w); + break; + } + + module->fixup_ports(); + Pass::call(design, "clean"); + + ezDefaultSAT ez; + SigMap sigmap(module); + SatGen satgen(&ez, &sigmap); + + for (auto c : module->cells()) { + bool ok = satgen.importCell(c); + log_assert(ok); + } + + std::vector in_vec = satgen.importSigSpec(in_sig); + std::vector inverse_in_vec = ez.vec_not(in_vec); + + std::vector out_vec = satgen.importSigSpec(out_sig); + + for (int i = 0; i < 16; i++) + { + std::vector assumptions; + for (int j = 0; j < SIZE(in_vec); j++) + assumptions.push_back((i & (1 << j)) ? in_vec.at(j) : inverse_in_vec.at(j)); + + std::vector results; + if (!ez.solve(out_vec, results, assumptions)) { + log("No stable solution for input %d found -> recreate module.\n", i); + goto recreate_module; + } + + for (int j = 0; j < 4; j++) + truthtab[i][j] = results[j]; + + assumptions.push_back(ez.vec_ne(out_vec, ez.vec_const(results))); + + std::vector results2; + if (ez.solve(out_vec, results2, assumptions)) { + log("Two stable solutions for input %d found -> recreate module.\n", i); + goto recreate_module; + } + } + break; + + recreate_module: + design->remove(module); + } + + log("Found viable UUT after %d cycles:\n", create_cycles); + Pass::call(design, "write_ilang"); + Pass::call(design, "abc"); + + log("\n"); + log("Pre- and post-abc truth table:\n"); + + ezDefaultSAT ez; + SigMap sigmap(module); + SatGen satgen(&ez, &sigmap); + + for (auto c : module->cells()) { + bool ok = satgen.importCell(c); + log_assert(ok); + } + + std::vector in_vec = satgen.importSigSpec(in_sig); + std::vector inverse_in_vec = ez.vec_not(in_vec); + + std::vector out_vec = satgen.importSigSpec(out_sig); + + bool found_error = false; + bool truthtab2[16][4]; + + for (int i = 0; i < 16; i++) + { + std::vector assumptions; + for (int j = 0; j < SIZE(in_vec); j++) + assumptions.push_back((i & (1 << j)) ? in_vec.at(j) : inverse_in_vec.at(j)); + + for (int j = 0; j < 4; j++) + truthtab2[i][j] = truthtab[i][j]; + + std::vector results; + if (!ez.solve(out_vec, results, assumptions)) { + log("No stable solution for input %d found.\n", i); + found_error = true; + continue; + } + + for (int j = 0; j < 4; j++) + truthtab2[i][j] = results[j]; + + assumptions.push_back(ez.vec_ne(out_vec, ez.vec_const(results))); + + std::vector results2; + if (ez.solve(out_vec, results2, assumptions)) { + log("Two stable solutions for input %d found -> recreate module.\n", i); + found_error = true; + } + } + + for (int i = 0; i < 16; i++) { + log("%3d ", i); + for (int j = 0; j < 4; j++) + log("%c", truthtab[i][j] ? '1' : '0'); + log(" "); + for (int j = 0; j < 4; j++) + log("%c", truthtab2[i][j] ? '1' : '0'); + for (int j = 0; j < 4; j++) + if (truthtab[i][j] != truthtab2[i][j]) { + found_error = true; + log(" !"); + break; + } + log("\n"); + } + + log_assert(found_error == false); + log("\n"); +} + +struct TestAbcloopPass : public Pass { + TestAbcloopPass() : Pass("test_abcloop", "automatically test handling of loops in abc command") { } + virtual void help() + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" test_abcloop [options]\n"); + log("\n"); + log("Test handling of logic loops in ABC.\n"); + log("\n"); + log(" -n {integer}\n"); + log(" create this number of circuits and test them (default = 100).\n"); + log("\n"); + log(" -s {positive_integer}\n"); + log(" use this value as rng seed value (default = unix time).\n"); + log("\n"); + } + virtual void execute(std::vector args, RTLIL::Design*) + { + int num_iter = 100; + xorshift32_state = 0; + + int argidx; + for (argidx = 1; argidx < SIZE(args); argidx++) + { + if (args[argidx] == "-n" && argidx+1 < SIZE(args)) { + num_iter = atoi(args[++argidx].c_str()); + continue; + } + if (args[argidx] == "-s" && argidx+1 < SIZE(args)) { + xorshift32_state = atoi(args[++argidx].c_str()); + continue; + } + break; + } + + if (xorshift32_state == 0) + xorshift32_state = time(NULL) & 0x7fffffff; + + for (int i = 0; i < num_iter; i++) + test_abcloop(); + } +} TestAbcloopPass; + -- cgit v1.2.3 From edf11c635a40c2cfb291089be509b2f31737958b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 21 Sep 2014 12:57:33 +0200 Subject: Assert on new logic loops in "share" pass --- passes/opt/share.cc | 48 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) (limited to 'passes') diff --git a/passes/opt/share.cc b/passes/opt/share.cc index c372ed78a..02e845846 100644 --- a/passes/opt/share.cc +++ b/passes/opt/share.cc @@ -21,6 +21,7 @@ #include "kernel/satgen.h" #include "kernel/sigtools.h" #include "kernel/modtools.h" +#include "kernel/utils.h" PRIVATE_NAMESPACE_BEGIN @@ -640,6 +641,48 @@ struct ShareWorker } + // ------------------------------------------------------------------------------------------------ + // Find SCCs (logic loops). This is only used to make sure that this pass does not introduce loops. + // ------------------------------------------------------------------------------------------------ + + bool module_has_scc() + { + SigMap sigmap(module); + + CellTypes ct; + ct.setup_internals(); + ct.setup_stdcells(); + + TopoSort toposort; + toposort.analyze_loops = false; + + std::map> cell_to_bits; + std::map> bit_to_cells; + + for (auto cell : module->cells()) + if (ct.cell_known(cell->type)) + for (auto &conn : cell->connections()) { + if (ct.cell_output(cell->type, conn.first)) + for (auto bit : sigmap(conn.second)) + cell_to_bits[cell].insert(bit); + else + for (auto bit : sigmap(conn.second)) + bit_to_cells[bit].insert(cell); + } + + for (auto &it : cell_to_bits) + { + RTLIL::Cell *c1 = it.first; + + for (auto bit : it.second) + for (auto c2 : bit_to_cells[bit]) + toposort.edge(c1, c2); + } + + return !toposort.sort(); + } + + // ------------- // Setup and run // ------------- @@ -647,6 +690,8 @@ struct ShareWorker ShareWorker(ShareWorkerConfig config, RTLIL::Design *design, RTLIL::Module *module) : config(config), design(design), module(module) { + bool before_scc = module_has_scc(); + generic_ops.insert(config.generic_uni_ops.begin(), config.generic_uni_ops.end()); generic_ops.insert(config.generic_bin_ops.begin(), config.generic_bin_ops.end()); generic_ops.insert(config.generic_cbin_ops.begin(), config.generic_cbin_ops.end()); @@ -879,6 +924,9 @@ struct ShareWorker } log_assert(recursion_state.empty()); + + bool after_scc = before_scc || module_has_scc(); + log_assert(before_scc == after_scc); } }; -- cgit v1.2.3 From 8d60754aefbded7b5742ceae2b34fb6b4dcda93d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 21 Sep 2014 13:52:39 +0200 Subject: Do not introduce new logic loops in "share" --- passes/opt/share.cc | 53 +++++++++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 47 insertions(+), 6 deletions(-) (limited to 'passes') diff --git a/passes/opt/share.cc b/passes/opt/share.cc index 02e845846..af2966bca 100644 --- a/passes/opt/share.cc +++ b/passes/opt/share.cc @@ -47,6 +47,8 @@ struct ShareWorker std::set cells_to_remove; std::set recursion_state; + std::map> to_drivers_edges; + // ------------------------------------------------------------------------------ // Find terminal bits -- i.e. bits that do not (exclusively) feed into a mux tree @@ -641,11 +643,11 @@ struct ShareWorker } - // ------------------------------------------------------------------------------------------------ - // Find SCCs (logic loops). This is only used to make sure that this pass does not introduce loops. - // ------------------------------------------------------------------------------------------------ + // ------------------------------------------------------------------------------------- + // Helper functions used to make sure that this pass does not introduce new logic loops. + // ------------------------------------------------------------------------------------- - bool module_has_scc() + bool module_has_scc(std::map> *edges = NULL) { SigMap sigmap(module); @@ -679,7 +681,32 @@ struct ShareWorker toposort.edge(c1, c2); } - return !toposort.sort(); + bool found_scc = !toposort.sort(); + if (edges) + *edges = std::move(toposort.database); + return found_scc; + } + + bool find_in_input_cone_worker(RTLIL::Cell *root, RTLIL::Cell *needle, std::set &stop) + { + if (root == needle) + return true; + + if (stop.count(root)) + return false; + + stop.insert(root); + + for (auto c : to_drivers_edges[root]) + if (find_in_input_cone_worker(c, needle, stop)) + return true; + return false; + } + + bool find_in_input_cone(RTLIL::Cell *root, RTLIL::Cell *needle) + { + std::set stop; + return find_in_input_cone_worker(root, needle, stop); } @@ -690,7 +717,7 @@ struct ShareWorker ShareWorker(ShareWorkerConfig config, RTLIL::Design *design, RTLIL::Module *module) : config(config), design(design), module(module) { - bool before_scc = module_has_scc(); + bool before_scc = module_has_scc(&to_drivers_edges); generic_ops.insert(config.generic_uni_ops.begin(), config.generic_uni_ops.end()); generic_ops.insert(config.generic_bin_ops.begin(), config.generic_bin_ops.end()); @@ -878,6 +905,17 @@ struct ShareWorker } log(" According to the SAT solver this pair of cells can be shared.\n"); + + if (find_in_input_cone(cell, other_cell)) { + log(" Sharing not possible: %s is in input cone of %s.\n", log_id(other_cell), log_id(cell)); + continue; + } + + if (find_in_input_cone(other_cell, cell)) { + log(" Sharing not possible: %s is in input cone of %s.\n", log_id(cell), log_id(other_cell)); + continue; + } + shareable_cells.erase(other_cell); int cell_select_score = 0; @@ -911,6 +949,9 @@ struct ShareWorker cells_to_remove.insert(cell); cells_to_remove.insert(other_cell); + + to_drivers_edges[cell].insert(to_drivers_edges[other_cell].begin(), to_drivers_edges[other_cell].end()); + to_drivers_edges[other_cell] = to_drivers_edges[cell]; break; } } -- cgit v1.2.3 From a6c08b40fe281a69e1e6cb369b73c55ab6192f45 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 21 Sep 2014 14:51:07 +0200 Subject: Still loop bug in "share": changed assert to warning --- passes/opt/share.cc | 38 +++++++++++++++++++++++++------------- 1 file changed, 25 insertions(+), 13 deletions(-) (limited to 'passes') diff --git a/passes/opt/share.cc b/passes/opt/share.cc index af2966bca..cdda29349 100644 --- a/passes/opt/share.cc +++ b/passes/opt/share.cc @@ -47,7 +47,9 @@ struct ShareWorker std::set cells_to_remove; std::set recursion_state; - std::map> to_drivers_edges; + SigMap topo_sigmap; + std::map> topo_cell_drivers; + std::map> topo_bit_drivers; // ------------------------------------------------------------------------------ @@ -647,10 +649,8 @@ struct ShareWorker // Helper functions used to make sure that this pass does not introduce new logic loops. // ------------------------------------------------------------------------------------- - bool module_has_scc(std::map> *edges = NULL) + bool module_has_scc() { - SigMap sigmap(module); - CellTypes ct; ct.setup_internals(); ct.setup_stdcells(); @@ -658,6 +658,9 @@ struct ShareWorker TopoSort toposort; toposort.analyze_loops = false; + topo_sigmap.set(module); + topo_bit_drivers.clear(); + std::map> cell_to_bits; std::map> bit_to_cells; @@ -665,10 +668,12 @@ struct ShareWorker if (ct.cell_known(cell->type)) for (auto &conn : cell->connections()) { if (ct.cell_output(cell->type, conn.first)) - for (auto bit : sigmap(conn.second)) + for (auto bit : topo_sigmap(conn.second)) { cell_to_bits[cell].insert(bit); + topo_bit_drivers[bit].insert(cell); + } else - for (auto bit : sigmap(conn.second)) + for (auto bit : topo_sigmap(conn.second)) bit_to_cells[bit].insert(cell); } @@ -682,8 +687,8 @@ struct ShareWorker } bool found_scc = !toposort.sort(); - if (edges) - *edges = std::move(toposort.database); + topo_cell_drivers = std::move(toposort.database); + return found_scc; } @@ -697,7 +702,7 @@ struct ShareWorker stop.insert(root); - for (auto c : to_drivers_edges[root]) + for (auto c : topo_cell_drivers[root]) if (find_in_input_cone_worker(c, needle, stop)) return true; return false; @@ -717,7 +722,7 @@ struct ShareWorker ShareWorker(ShareWorkerConfig config, RTLIL::Design *design, RTLIL::Module *module) : config(config), design(design), module(module) { - bool before_scc = module_has_scc(&to_drivers_edges); + bool before_scc = module_has_scc(); generic_ops.insert(config.generic_uni_ops.begin(), config.generic_uni_ops.end()); generic_ops.insert(config.generic_bin_ops.begin(), config.generic_bin_ops.end()); @@ -950,8 +955,12 @@ struct ShareWorker cells_to_remove.insert(cell); cells_to_remove.insert(other_cell); - to_drivers_edges[cell].insert(to_drivers_edges[other_cell].begin(), to_drivers_edges[other_cell].end()); - to_drivers_edges[other_cell] = to_drivers_edges[cell]; + for (auto bit : topo_sigmap(all_ctrl_signals)) + for (auto c : topo_bit_drivers[bit]) + topo_cell_drivers[cell].insert(c); + + topo_cell_drivers[cell].insert(topo_cell_drivers[other_cell].begin(), topo_cell_drivers[other_cell].end()); + topo_cell_drivers[other_cell] = topo_cell_drivers[cell]; break; } } @@ -967,7 +976,10 @@ struct ShareWorker log_assert(recursion_state.empty()); bool after_scc = before_scc || module_has_scc(); - log_assert(before_scc == after_scc); + if (before_scc != after_scc) + log("Warning: introduced topological logic loops!\n"); + // Pass::call_on_module(design, module, "scc;; show"); + // log_assert(before_scc == after_scc); } }; -- cgit v1.2.3 From b28be0759f46326d4d2a7ac74f1d1f79477435da Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 21 Sep 2014 15:13:06 +0200 Subject: Added "share -limit" --- passes/opt/share.cc | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/opt/share.cc b/passes/opt/share.cc index cdda29349..5ed9af009 100644 --- a/passes/opt/share.cc +++ b/passes/opt/share.cc @@ -27,6 +27,7 @@ PRIVATE_NAMESPACE_BEGIN struct ShareWorkerConfig { + int limit; bool opt_force; bool opt_aggressive; bool opt_fast; @@ -751,7 +752,7 @@ struct ShareWorker log("Found %d cells in module %s that may be considered for resource sharing.\n", SIZE(shareable_cells), log_id(module)); - while (!shareable_cells.empty()) + while (!shareable_cells.empty() && config.limit != 0) { RTLIL::Cell *cell = *shareable_cells.begin(); shareable_cells.erase(cell); @@ -959,6 +960,9 @@ struct ShareWorker for (auto c : topo_bit_drivers[bit]) topo_cell_drivers[cell].insert(c); + if (config.limit > 0) + config.limit--; + topo_cell_drivers[cell].insert(topo_cell_drivers[other_cell].begin(), topo_cell_drivers[other_cell].end()); topo_cell_drivers[other_cell] = topo_cell_drivers[cell]; break; @@ -1013,11 +1017,15 @@ struct SharePass : public Pass { log(" in much easier SAT problems at the cost of maybe missing some oportunities\n"); log(" for resource sharing.\n"); log("\n"); + log(" -limit N\n"); + log(" Only perform the first N merges, then stop. This is useful for debugging.\n"); + log("\n"); } virtual void execute(std::vector args, RTLIL::Design *design) { ShareWorkerConfig config; + config.limit = -1; config.opt_force = false; config.opt_aggressive = false; config.opt_fast = false; @@ -1073,6 +1081,10 @@ struct SharePass : public Pass { config.opt_fast = true; continue; } + if (args[argidx] == "-limit" && argidx+1 < args.size()) { + config.limit = atoi(args[++argidx].c_str()); + continue; + } break; } extra_args(args, argidx, design); -- cgit v1.2.3 From d6e2ace95be79274f8707a897e3ac265ab85b11a Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 21 Sep 2014 15:13:44 +0200 Subject: Logic loop bugfix for "share" pass --- passes/opt/share.cc | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) (limited to 'passes') diff --git a/passes/opt/share.cc b/passes/opt/share.cc index 5ed9af009..b91a67ee0 100644 --- a/passes/opt/share.cc +++ b/passes/opt/share.cc @@ -958,13 +958,17 @@ struct ShareWorker for (auto bit : topo_sigmap(all_ctrl_signals)) for (auto c : topo_bit_drivers[bit]) - topo_cell_drivers[cell].insert(c); + topo_cell_drivers[supercell].insert(c); + + topo_cell_drivers[supercell].insert(topo_cell_drivers[cell].begin(), topo_cell_drivers[cell].end()); + topo_cell_drivers[supercell].insert(topo_cell_drivers[other_cell].begin(), topo_cell_drivers[other_cell].end()); + + topo_cell_drivers[cell] = { supercell }; + topo_cell_drivers[other_cell] = { supercell }; if (config.limit > 0) config.limit--; - topo_cell_drivers[cell].insert(topo_cell_drivers[other_cell].begin(), topo_cell_drivers[other_cell].end()); - topo_cell_drivers[other_cell] = topo_cell_drivers[cell]; break; } } -- cgit v1.2.3 From 96e821dc6cf170168218fa4cddc7c9ddafd6f439 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 21 Sep 2014 19:36:56 +0200 Subject: Various improvements regarding logic loops in "share" results --- passes/opt/share.cc | 145 ++++++++++++++++++++++++++++++++++++++-------------- 1 file changed, 108 insertions(+), 37 deletions(-) (limited to 'passes') diff --git a/passes/opt/share.cc b/passes/opt/share.cc index b91a67ee0..e3b0159c0 100644 --- a/passes/opt/share.cc +++ b/passes/opt/share.cc @@ -44,6 +44,7 @@ struct ShareWorker CellTypes fwd_ct, cone_ct; ModWalker modwalker; + ModIndex mi; std::set cells_to_remove; std::set recursion_state; @@ -102,7 +103,7 @@ struct ShareWorker // Find shareable cells and compatible groups of cells // --------------------------------------------------- - std::set shareable_cells; + std::set> shareable_cells; void find_shareable_cells() { @@ -252,7 +253,7 @@ struct ShareWorker // Create replacement cell // ----------------------- - RTLIL::Cell *make_supercell(RTLIL::Cell *c1, RTLIL::Cell *c2, RTLIL::SigSpec act) + RTLIL::Cell *make_supercell(RTLIL::Cell *c1, RTLIL::Cell *c2, RTLIL::SigSpec act, std::set &supercell_aux) { log_assert(c1->type == c2->type); @@ -283,10 +284,12 @@ struct ShareWorker int a_width = std::max(a1.size(), a2.size()); int y_width = std::max(y1.size(), y2.size()); - if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->getPort("\\Y"); - if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->getPort("\\Y"); + a1.extend_u0(a_width, a_signed); + a2.extend_u0(a_width, a_signed); + + RTLIL::SigSpec a = module->addWire(NEW_ID, a_width); + supercell_aux.insert(module->addMux(NEW_ID, a2, a1, act, a)); - RTLIL::SigSpec a = module->Mux(NEW_ID, a2, a1, act); RTLIL::Wire *y = module->addWire(NEW_ID, y_width); RTLIL::Cell *supercell = module->addCell(NEW_ID, c1->type); @@ -296,12 +299,10 @@ struct ShareWorker supercell->setPort("\\A", a); supercell->setPort("\\Y", y); - RTLIL::SigSpec new_y1(y, 0, y1.size()); - RTLIL::SigSpec new_y2(y, 0, y2.size()); - - module->connect(RTLIL::SigSig(y1, new_y1)); - module->connect(RTLIL::SigSig(y2, new_y2)); + supercell_aux.insert(module->addPos(NEW_ID, y, y1)); + supercell_aux.insert(module->addPos(NEW_ID, y, y2)); + supercell_aux.insert(supercell); return supercell; } @@ -386,23 +387,27 @@ struct ShareWorker { a_width = std::max(y_width, a_width); - if (a1.size() < y1.size()) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, y1.size()), true)->getPort("\\Y"); - if (a2.size() < y2.size()) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, y2.size()), true)->getPort("\\Y"); + if (a1.size() < y1.size()) a1.extend_u0(y1.size(), true); + if (a2.size() < y2.size()) a2.extend_u0(y2.size(), true); - if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), false)->getPort("\\Y"); - if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), false)->getPort("\\Y"); + a1.extend_u0(a_width, false); + a2.extend_u0(a_width, false); } else { - if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->getPort("\\Y"); - if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->getPort("\\Y"); + a1.extend_u0(a_width, a_signed); + a2.extend_u0(a_width, a_signed); } - if (b1.size() != b_width) b1 = module->addPos(NEW_ID, b1, module->addWire(NEW_ID, b_width), b_signed)->getPort("\\Y"); - if (b2.size() != b_width) b2 = module->addPos(NEW_ID, b2, module->addWire(NEW_ID, b_width), b_signed)->getPort("\\Y"); + b1.extend_u0(b_width, b_signed); + b2.extend_u0(b_width, b_signed); + + RTLIL::SigSpec a = module->addWire(NEW_ID, a_width); + RTLIL::SigSpec b = module->addWire(NEW_ID, b_width); + + supercell_aux.insert(module->addMux(NEW_ID, a2, a1, act, a)); + supercell_aux.insert(module->addMux(NEW_ID, b2, b1, act, b)); - RTLIL::SigSpec a = module->Mux(NEW_ID, a2, a1, act); - RTLIL::SigSpec b = module->Mux(NEW_ID, b2, b1, act); RTLIL::Wire *y = module->addWire(NEW_ID, y_width); RTLIL::Cell *supercell = module->addCell(NEW_ID, c1->type); @@ -416,19 +421,18 @@ struct ShareWorker supercell->setPort("\\Y", y); supercell->check(); - RTLIL::SigSpec new_y1(y, 0, y1.size()); - RTLIL::SigSpec new_y2(y, 0, y2.size()); - - module->connect(RTLIL::SigSig(y1, new_y1)); - module->connect(RTLIL::SigSig(y2, new_y2)); + supercell_aux.insert(module->addPos(NEW_ID, y, y1)); + supercell_aux.insert(module->addPos(NEW_ID, y, y2)); + supercell_aux.insert(supercell); return supercell; } if (c1->type == "$memrd") { RTLIL::Cell *supercell = module->addCell(NEW_ID, c1); - module->connect(c2->getPort("\\DATA"), supercell->getPort("\\DATA")); + supercell_aux.insert(module->addPos(NEW_ID, supercell->getPort("\\DATA"), c2->getPort("\\DATA"))); + supercell_aux.insert(supercell); return supercell; } @@ -633,16 +637,21 @@ struct ShareWorker } } - RTLIL::SigSpec make_cell_activation_logic(const std::set> &activation_patterns) + RTLIL::SigSpec make_cell_activation_logic(const std::set> &activation_patterns, std::set &supercell_aux) { RTLIL::Wire *all_cases_wire = module->addWire(NEW_ID, 0); + for (auto &p : activation_patterns) { all_cases_wire->width++; - module->addEq(NEW_ID, p.first, p.second, RTLIL::SigSpec(all_cases_wire, all_cases_wire->width - 1)); + supercell_aux.insert(module->addEq(NEW_ID, p.first, p.second, RTLIL::SigSpec(all_cases_wire, all_cases_wire->width - 1))); } + if (all_cases_wire->width == 1) return all_cases_wire; - return module->ReduceOr(NEW_ID, all_cases_wire); + + RTLIL::Wire *result_wire = module->addWire(NEW_ID); + supercell_aux.insert(module->addReduceOr(NEW_ID, all_cases_wire, result_wire)); + return result_wire; } @@ -690,6 +699,13 @@ struct ShareWorker bool found_scc = !toposort.sort(); topo_cell_drivers = std::move(toposort.database); + if (found_scc && toposort.analyze_loops) + for (auto &loop : toposort.loops) { + log("### loop ###\n"); + for (auto &c : loop) + log("%s (%s)\n", log_id(c), log_id(c->type)); + } + return found_scc; } @@ -715,13 +731,52 @@ struct ShareWorker return find_in_input_cone_worker(root, needle, stop); } + bool is_part_of_scc(RTLIL::Cell *cell) + { + CellTypes ct; + ct.setup_internals(); + ct.setup_stdcells(); + + std::set queue, covered; + queue.insert(cell); + + while (!queue.empty()) + { + std::set new_queue; + + for (auto c : queue) { + if (!ct.cell_known(c->type)) + continue; + for (auto &conn : c->connections()) + if (ct.cell_input(c->type, conn.first)) + for (auto bit : conn.second) + for (auto &pi : mi.query_ports(bit)) + if (ct.cell_known(pi.cell->type) && ct.cell_output(pi.cell->type, pi.port)) + new_queue.insert(pi.cell); + covered.insert(c); + } + + queue.clear(); + for (auto c : new_queue) { + if (cells_to_remove.count(c)) + continue; + if (c == cell) + return true; + if (!covered.count(c)) + queue.insert(c); + } + } + + return false; + } + // ------------- // Setup and run // ------------- ShareWorker(ShareWorkerConfig config, RTLIL::Design *design, RTLIL::Module *module) : - config(config), design(design), module(module) + config(config), design(design), module(module), mi(module) { bool before_scc = module_has_scc(); @@ -934,18 +989,37 @@ struct ShareWorker other_cell_select_score += p.first.size(); RTLIL::Cell *supercell; + std::set supercell_aux; if (cell_select_score <= other_cell_select_score) { - RTLIL::SigSpec act = make_cell_activation_logic(filtered_cell_activation_patterns); - supercell = make_supercell(cell, other_cell, act); + RTLIL::SigSpec act = make_cell_activation_logic(filtered_cell_activation_patterns, supercell_aux); + supercell = make_supercell(cell, other_cell, act, supercell_aux); log(" Activation signal for %s: %s\n", log_id(cell), log_signal(act)); } else { - RTLIL::SigSpec act = make_cell_activation_logic(filtered_other_cell_activation_patterns); - supercell = make_supercell(other_cell, cell, act); + RTLIL::SigSpec act = make_cell_activation_logic(filtered_other_cell_activation_patterns, supercell_aux); + supercell = make_supercell(other_cell, cell, act, supercell_aux); log(" Activation signal for %s: %s\n", log_id(other_cell), log_signal(act)); } log(" New cell: %s (%s)\n", log_id(supercell), log_id(supercell->type)); + cells_to_remove.insert(cell); + cells_to_remove.insert(other_cell); + + for (auto c : supercell_aux) + if (is_part_of_scc(c)) + goto do_rollback; + + if (0) { + do_rollback: + log(" New topology contains loops! Rolling back..\n"); + cells_to_remove.erase(cell); + cells_to_remove.erase(other_cell); + shareable_cells.insert(other_cell); + for (auto cc : supercell_aux) + module->remove(cc); + continue; + } + std::set> supercell_activation_patterns; supercell_activation_patterns.insert(filtered_cell_activation_patterns.begin(), filtered_cell_activation_patterns.end()); supercell_activation_patterns.insert(filtered_other_cell_activation_patterns.begin(), filtered_other_cell_activation_patterns.end()); @@ -953,9 +1027,6 @@ struct ShareWorker activation_patterns_cache[supercell] = supercell_activation_patterns; shareable_cells.insert(supercell); - cells_to_remove.insert(cell); - cells_to_remove.insert(other_cell); - for (auto bit : topo_sigmap(all_ctrl_signals)) for (auto c : topo_bit_drivers[bit]) topo_cell_drivers[supercell].insert(c); -- cgit v1.2.3 From 13117bb346dd02d2345f716b4403239aebe3d0e2 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 21 Sep 2014 19:44:08 +0200 Subject: Re-enabled assert for new logic loops in "share" pass --- passes/opt/share.cc | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'passes') diff --git a/passes/opt/share.cc b/passes/opt/share.cc index e3b0159c0..74b049bb6 100644 --- a/passes/opt/share.cc +++ b/passes/opt/share.cc @@ -1055,10 +1055,7 @@ struct ShareWorker log_assert(recursion_state.empty()); bool after_scc = before_scc || module_has_scc(); - if (before_scc != after_scc) - log("Warning: introduced topological logic loops!\n"); - // Pass::call_on_module(design, module, "scc;; show"); - // log_assert(before_scc == after_scc); + log_assert(before_scc == after_scc); } }; -- cgit v1.2.3