From a038787c9b51e92440cac3a38801c08f66dbb3af Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 4 Feb 2015 18:52:54 +0100 Subject: Added onehot attribute --- passes/fsm/fsm_map.cc | 3 +++ passes/memory/memory_share.cc | 13 +++++++++++++ 2 files changed, 16 insertions(+) (limited to 'passes') diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc index a260653fb..155801a3a 100644 --- a/passes/fsm/fsm_map.cc +++ b/passes/fsm/fsm_map.cc @@ -224,6 +224,9 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) } } + if (encoding_is_onehot) + state_wire->set_bool_attribute("\\onehot"); + // generate next_state signal if (GetSize(fsm_data.state_table) == 1) diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index ec8df7598..a2f89f6d9 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -544,6 +544,7 @@ struct MemoryShareWorker // create SAT representation of common input cone of all considered EN signals + pool one_hot_wires; std::set sat_cells; std::set bits_queue; std::map port_to_sat_variable; @@ -560,6 +561,10 @@ struct MemoryShareWorker while (!bits_queue.empty()) { + for (auto bit : bits_queue) + if (bit.wire && bit.wire->get_bool_attribute("\\onehot")) + one_hot_wires.insert(bit.wire); + pool portbits; modwalker.get_drivers(portbits, bits_queue); bits_queue.clear(); @@ -572,6 +577,14 @@ struct MemoryShareWorker } } + for (auto wire : one_hot_wires) { + log(" Adding one-hot constraint for wire %s.\n", log_id(wire)); + vector ez_wire_bits = satgen.importSigSpec(wire); + for (int i : ez_wire_bits) + for (int j : ez_wire_bits) + if (i != j) ez.assume(ez.NOT(i), j); + } + log(" Common input cone for all EN signals: %d cells.\n", int(sat_cells.size())); for (auto cell : sat_cells) -- cgit v1.2.3