From ebb11bcea4ab5d2aed90d640904bf490a3285fb8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 13 Feb 2020 12:05:14 -0800
Subject: iopadmap: move \init attributes from outpad output to its input

---
 passes/techmap/iopadmap.cc | 23 ++++++++++++++++++++---
 1 file changed, 20 insertions(+), 3 deletions(-)

(limited to 'passes')

diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc
index 531ac2b99..b3ae5eafe 100644
--- a/passes/techmap/iopadmap.cc
+++ b/passes/techmap/iopadmap.cc
@@ -408,18 +408,35 @@ struct IopadmapPass : public Pass {
 				RTLIL::Wire *wire = it.first;
 				RTLIL::Wire *new_wire = module->addWire(NEW_ID, wire);
 				module->swap_names(new_wire, wire);
-				wire->attributes.clear();
 				for (int i = 0; i < wire->width; i++)
 				{
 					SigBit wire_bit(wire, i);
 					if (!it.second.count(i)) {
-						if (wire->port_output)
+						if (wire->port_output) {
 							module->connect(SigSpec(new_wire, i), SigSpec(wire, i));
-						else
+							wire->attributes.clear();
+						}
+						else {
 							module->connect(SigSpec(wire, i), SigSpec(new_wire, i));
+							wire->attributes.clear();
+
+						}
 					} else {
 						auto &new_conn = it.second.at(i);
 						new_conn.first->setPort(new_conn.second, RTLIL::SigSpec(new_wire, i));
+
+						// For cell outputs, move \init attributes from old wire to new wire
+						if (new_conn.first->output(new_conn.second)) {
+							auto it = wire->attributes.find(ID(init));
+							if (it != wire->attributes.end()) {
+								for (auto it2 = wire->attributes.begin(); it2 != wire->attributes.end(); )
+									if (it == it2)
+										++it2;
+									else
+										it2 = wire->attributes.erase(it2);
+								new_wire->attributes.erase(ID(init));
+							}
+						}
 					}
 				}
 
-- 
cgit v1.2.3


From 3d2a2e87992e1ecd3e724f379ce32044b7506aa3 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 13 Feb 2020 14:57:06 -0800
Subject: iopadmap: fixes as suggested by @mwkmwkmwk

---
 passes/techmap/iopadmap.cc | 30 +++++++++++-------------------
 1 file changed, 11 insertions(+), 19 deletions(-)

(limited to 'passes')

diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc
index b3ae5eafe..a6e4fac14 100644
--- a/passes/techmap/iopadmap.cc
+++ b/passes/techmap/iopadmap.cc
@@ -408,35 +408,27 @@ struct IopadmapPass : public Pass {
 				RTLIL::Wire *wire = it.first;
 				RTLIL::Wire *new_wire = module->addWire(NEW_ID, wire);
 				module->swap_names(new_wire, wire);
+				wire->attributes.clear();
 				for (int i = 0; i < wire->width; i++)
 				{
 					SigBit wire_bit(wire, i);
 					if (!it.second.count(i)) {
-						if (wire->port_output) {
+						if (wire->port_output)
 							module->connect(SigSpec(new_wire, i), SigSpec(wire, i));
-							wire->attributes.clear();
-						}
-						else {
+						else
 							module->connect(SigSpec(wire, i), SigSpec(new_wire, i));
-							wire->attributes.clear();
-
-						}
 					} else {
 						auto &new_conn = it.second.at(i);
 						new_conn.first->setPort(new_conn.second, RTLIL::SigSpec(new_wire, i));
+					}
+				}
 
-						// For cell outputs, move \init attributes from old wire to new wire
-						if (new_conn.first->output(new_conn.second)) {
-							auto it = wire->attributes.find(ID(init));
-							if (it != wire->attributes.end()) {
-								for (auto it2 = wire->attributes.begin(); it2 != wire->attributes.end(); )
-									if (it == it2)
-										++it2;
-									else
-										it2 = wire->attributes.erase(it2);
-								new_wire->attributes.erase(ID(init));
-							}
-						}
+				if (wire->port_output) {
+					auto jt = new_wire->attributes.find(ID(init));
+					// For output ports, move \init attributes from old wire to new wire
+					if (jt != new_wire->attributes.end()) {
+						wire->attributes[ID(init)] = std::move(jt->second);
+						new_wire->attributes.erase(jt);
 					}
 				}
 
-- 
cgit v1.2.3