From 16df8f5a323e6ac2ccdb33fa115c59c9c7c3d856 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 12 Nov 2019 14:26:02 +0100 Subject: Bugfix in fsm_detect Signed-off-by: Clifford Wolf --- passes/fsm/fsm_detect.cc | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) (limited to 'passes') diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc index 5ae991b28..61e6f8011 100644 --- a/passes/fsm/fsm_detect.cc +++ b/passes/fsm/fsm_detect.cc @@ -158,22 +158,24 @@ static void detect_fsm(RTLIL::Wire *wire) std::set cellport_list; sig2user.find(sig_q, cellport_list); + auto sig_q_bits = sig_q.to_sigbit_pool(); + for (auto &cellport : cellport_list) { RTLIL::Cell *cell = cellport.first; bool set_output = false, clr_output = false; - if (cell->type == "$ne") + if (cell->type.in("$ne", "$reduce_or", "$reduce_bool")) set_output = true; - if (cell->type == "$eq") + if (cell->type.in("$eq", "$logic_not", "$reduce_and")) clr_output = true; - if (!set_output && !clr_output) { - clr_output = true; + if (set_output || clr_output) { for (auto &port_it : cell->connections()) - if (port_it.first != "\\A" || port_it.first != "\\Y") - clr_output = false; + for (auto bit : assign_map(port_it.second)) + if (bit.wire != nullptr && !sig_q_bits.count(bit)) + goto next_cellport; } if (set_output || clr_output) { @@ -184,6 +186,7 @@ static void detect_fsm(RTLIL::Wire *wire) ce.set(sig, val); } } + next_cellport:; } SigSpec sig_y = sig_d, sig_undef; -- cgit v1.2.3 From 4be5a0fd7c1573f81c6c70a16601f7ce5ab87210 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 12 Nov 2019 17:31:30 +0100 Subject: Update fsm_detect bugfix Signed-off-by: Clifford Wolf --- passes/fsm/fsm_detect.cc | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'passes') diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc index 61e6f8011..fb3896669 100644 --- a/passes/fsm/fsm_detect.cc +++ b/passes/fsm/fsm_detect.cc @@ -173,9 +173,10 @@ static void detect_fsm(RTLIL::Wire *wire) if (set_output || clr_output) { for (auto &port_it : cell->connections()) - for (auto bit : assign_map(port_it.second)) - if (bit.wire != nullptr && !sig_q_bits.count(bit)) - goto next_cellport; + if (cell->input(port_it.first)) + for (auto bit : assign_map(port_it.second)) + if (bit.wire != nullptr && !sig_q_bits.count(bit)) + goto next_cellport; } if (set_output || clr_output) { -- cgit v1.2.3