From 4bfd2ef4f328b4a95918ed3e0d7a7e38406c4ae8 Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 22 Nov 2019 15:07:55 +0000 Subject: sv: Improve handling of wildcard port connections Signed-off-by: David Shah --- passes/hierarchy/hierarchy.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'passes') diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index c298a6600..fa4a8ea29 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -992,7 +992,7 @@ struct HierarchyPass : public Pass { if (wire->port_input && wire->attributes.count("\\defaultvalue")) defaults_db[module->name][wire->name] = wire->attributes.at("\\defaultvalue"); } - // Process SV implicit port connections + // Process SV implicit wildcard port connections std::set blackbox_derivatives; std::vector design_modules = design->modules(); @@ -1000,7 +1000,7 @@ struct HierarchyPass : public Pass { { for (auto cell : module->cells()) { - if (!cell->get_bool_attribute(ID(implicit_port_conns))) + if (!cell->get_bool_attribute(ID(wildcard_port_conns))) continue; Module *m = design->module(cell->type); @@ -1042,7 +1042,7 @@ struct HierarchyPass : public Pass { RTLIL::id2cstr(wire->name), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); cell->setPort(wire->name, parent_wire); } - cell->attributes.erase(ID(implicit_port_conns)); + cell->attributes.erase(ID(wildcard_port_conns)); } } -- cgit v1.2.3