From adc6efb58468a7e2f85f756d4a9d4686ad0a8c45 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 11 Apr 2019 12:34:51 -0700 Subject: Recognise default entry in case even if all cases covered (#931) --- passes/proc/proc_rmdead.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/proc/proc_rmdead.cc b/passes/proc/proc_rmdead.cc index 7c334e661..d2f8d9ead 100644 --- a/passes/proc/proc_rmdead.cc +++ b/passes/proc/proc_rmdead.cc @@ -34,7 +34,7 @@ void proc_rmdead(RTLIL::SwitchRule *sw, int &counter) for (size_t i = 0; i < sw->cases.size(); i++) { - bool is_default = GetSize(sw->cases[i]->compare) == 0 && (!pool.empty() || GetSize(sw->signal) == 0); + bool is_default = GetSize(sw->cases[i]->compare) == 0 || GetSize(sw->signal) == 0; for (size_t j = 0; j < sw->cases[i]->compare.size(); j++) { RTLIL::SigSpec sig = sw->cases[i]->compare[j]; -- cgit v1.2.3 From b3378745fd993f48b8114fb08e5019b34374ee72 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 15 Apr 2019 17:52:45 -0700 Subject: Revert "Recognise default entry in case even if all cases covered (fix for #931)" --- passes/proc/proc_rmdead.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'passes') diff --git a/passes/proc/proc_rmdead.cc b/passes/proc/proc_rmdead.cc index d2f8d9ead..7c334e661 100644 --- a/passes/proc/proc_rmdead.cc +++ b/passes/proc/proc_rmdead.cc @@ -34,7 +34,7 @@ void proc_rmdead(RTLIL::SwitchRule *sw, int &counter) for (size_t i = 0; i < sw->cases.size(); i++) { - bool is_default = GetSize(sw->cases[i]->compare) == 0 || GetSize(sw->signal) == 0; + bool is_default = GetSize(sw->cases[i]->compare) == 0 && (!pool.empty() || GetSize(sw->signal) == 0); for (size_t j = 0; j < sw->cases[i]->compare.size(); j++) { RTLIL::SigSpec sig = sw->cases[i]->compare[j]; -- cgit v1.2.3 From 4da4a6da2f65d04dbdb50b84310fd91e23348986 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 16 Apr 2019 11:07:51 -0700 Subject: Revert #895 --- passes/proc/proc_mux.cc | 28 ---------------------------- 1 file changed, 28 deletions(-) (limited to 'passes') diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc index bac2dc2cd..1329c1fef 100644 --- a/passes/proc/proc_mux.cc +++ b/passes/proc/proc_mux.cc @@ -340,7 +340,6 @@ RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, SnippetSwCache &swcache, d // evaluate in reverse order to give the first entry the top priority RTLIL::SigSpec initial_val = result; RTLIL::Cell *last_mux_cell = NULL; - bool shiftx = initial_val.is_fully_undef(); for (size_t i = 0; i < sw->cases.size(); i++) { int case_idx = sw->cases.size() - i - 1; RTLIL::CaseRule *cs2 = sw->cases[case_idx]; @@ -349,33 +348,6 @@ RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, SnippetSwCache &swcache, d append_pmux(mod, sw->signal, cs2->compare, value, last_mux_cell, sw, ifxmode); else result = gen_mux(mod, sw->signal, cs2->compare, value, result, last_mux_cell, sw, ifxmode); - - // Ignore output values which are entirely don't care - if (shiftx && !value.is_fully_undef()) { - // Keep checking if case condition is the same as the current case index - if (cs2->compare.size() == 1 && cs2->compare.front().is_fully_const()) - shiftx = (cs2->compare.front().as_int() == case_idx); - else - shiftx = false; - } - } - - // Transform into a $shiftx where possible - if (shiftx && last_mux_cell && last_mux_cell->type == "$pmux") { - // Create bit-blasted $shiftx-es that shifts by the address line used in the case statement - auto pmux_b_port = last_mux_cell->getPort("\\B"); - auto pmux_y_port = last_mux_cell->getPort("\\Y"); - int width = last_mux_cell->getParam("\\WIDTH").as_int(); - for (int i = 0; i < width; ++i) { - RTLIL::SigSpec a_port; - // Because we went in reverse order above, un-reverse $pmux's B port here - for (int j = pmux_b_port.size()/width-1; j >= 0; --j) - a_port.append(pmux_b_port.extract(j*width+i, 1)); - // Create a $shiftx that shifts by the address line used in the case statement - mod->addShiftx(NEW_ID, a_port, sw->signal, pmux_y_port.extract(i, 1)); - } - // Disconnect $pmux by replacing its output port with a floating wire - last_mux_cell->setPort("\\Y", mod->addWire(NEW_ID, width)); } } -- cgit v1.2.3