From fbf8bcf38f4cc6ea11f4b6461531deb17bd9765c Mon Sep 17 00:00:00 2001
From: Claire Xenia Wolf <claire@clairexen.net>
Date: Thu, 1 Dec 2022 01:59:16 +0100
Subject: Add insbuf -chain mode

Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
---
 passes/techmap/insbuf.cc | 40 ++++++++++++++++++++++++++++++++++++++--
 1 file changed, 38 insertions(+), 2 deletions(-)

(limited to 'passes/techmap')

diff --git a/passes/techmap/insbuf.cc b/passes/techmap/insbuf.cc
index 68c22c317..f288987a1 100644
--- a/passes/techmap/insbuf.cc
+++ b/passes/techmap/insbuf.cc
@@ -36,12 +36,16 @@ struct InsbufPass : public Pass {
 		log("        Use the given cell type instead of $_BUF_. (Notice that the next\n");
 		log("        call to \"clean\" will remove all $_BUF_ in the design.)\n");
 		log("\n");
+		log("    -chain\n");
+		log("        Chain buffer cells\n");
+		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
 		log_header(design, "Executing INSBUF pass (insert buffer cells for connected wires).\n");
 
 		IdString celltype = ID($_BUF_), in_portname = ID::A, out_portname = ID::Y;
+		bool chain_mode = false;
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)
@@ -53,6 +57,10 @@ struct InsbufPass : public Pass {
 				out_portname = RTLIL::escape_id(args[++argidx]);
 				continue;
 			}
+			if (arg == "-chain") {
+				chain_mode = true;
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
@@ -60,6 +68,8 @@ struct InsbufPass : public Pass {
 		for (auto module : design->selected_modules())
 		{
 			std::vector<RTLIL::SigSig> new_connections;
+			pool<Cell*> bufcells;
+			SigMap sigmap;
 
 			for (auto &conn : module->connections())
 			{
@@ -70,22 +80,48 @@ struct InsbufPass : public Pass {
 					SigBit lhs = conn.first[i];
 					SigBit rhs = conn.second[i];
 
-					if (lhs.wire && !design->selected(module, lhs.wire)) {
+					if (!lhs.wire || !design->selected(module, lhs.wire)) {
 						new_conn.first.append(lhs);
 						new_conn.second.append(rhs);
+						log("Skip %s: %s -> %s\n", log_id(module), log_signal(rhs), log_signal(lhs));
 						continue;
 					}
 
+					if (chain_mode && rhs.wire) {
+						rhs = sigmap(rhs);
+						SigBit outbit = sigmap(lhs);
+						sigmap.add(lhs, rhs);
+						sigmap.add(outbit);
+					}
+
 					Cell *cell = module->addCell(NEW_ID, celltype);
 					cell->setPort(in_portname, rhs);
 					cell->setPort(out_portname, lhs);
-					log("Added %s.%s: %s -> %s\n", log_id(module), log_id(cell), log_signal(rhs), log_signal(lhs));
+
+					log("Add %s/%s: %s -> %s\n", log_id(module), log_id(cell), log_signal(rhs), log_signal(lhs));
+					bufcells.insert(cell);
 				}
 
 				if (GetSize(new_conn.first))
 					new_connections.push_back(new_conn);
 			}
 
+			if (chain_mode) {
+				for (auto &cell : module->selected_cells()) {
+					if (bufcells.count(cell))
+						continue;
+					for (auto &port : cell->connections())
+						if (cell->input(port.first)) {
+							auto s = sigmap(port.second);
+							if (s == port.second)
+								continue;
+							log("Rewrite %s/%s/%s: %s -> %s\n", log_id(module), log_id(cell),
+									log_id(port.first), log_signal(port.second), log_signal(s));
+							cell->setPort(port.first, s);
+						}
+				}
+			}
+
 			module->new_connections(new_connections);
 		}
 	}
-- 
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