From edb3c9d0c4f0bc3a108ffebc01f02ff4d7354487 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 24 Dec 2014 09:51:17 +0100
Subject: Renamed extend() to extend_xx(), changed most users to extend_u0()

---
 passes/techmap/alumacc.cc   | 2 +-
 passes/techmap/maccmap.cc   | 6 +++---
 passes/techmap/simplemap.cc | 2 +-
 3 files changed, 5 insertions(+), 5 deletions(-)

(limited to 'passes/techmap')

diff --git a/passes/techmap/alumacc.cc b/passes/techmap/alumacc.cc
index 2e297a2c6..dcffed94d 100644
--- a/passes/techmap/alumacc.cc
+++ b/passes/techmap/alumacc.cc
@@ -501,7 +501,7 @@ struct AlumaccWorker
 				if (GetSize(sig) > 1)
 					sig = module->ReduceOr(NEW_ID, sig);
 
-				sig.extend(GetSize(cmp_y));
+				sig.extend_u0(GetSize(cmp_y));
 				module->connect(cmp_y, sig);
 			}
 
diff --git a/passes/techmap/maccmap.cc b/passes/techmap/maccmap.cc
index c487cc36a..ffbd6289d 100644
--- a/passes/techmap/maccmap.cc
+++ b/passes/techmap/maccmap.cc
@@ -49,7 +49,7 @@ struct MaccmapWorker
 
 	void add(RTLIL::SigSpec a, bool is_signed, bool do_subtract)
 	{
-		a.extend(width, is_signed);
+		a.extend_u0(width, is_signed);
 
 		if (do_subtract) {
 			a = module->Not(NEW_ID, a);
@@ -65,10 +65,10 @@ struct MaccmapWorker
 		if (GetSize(a) < GetSize(b))
 			std::swap(a, b);
 
-		a.extend(width, is_signed);
+		a.extend_u0(width, is_signed);
 
 		if (GetSize(b) > width)
-			b.extend(width, is_signed);
+			b.extend_u0(width, is_signed);
 
 		for (int i = 0; i < GetSize(b); i++)
 			if (is_signed && i+1 == GetSize(b))
diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc
index 2dcb5f3eb..c1c0f76a8 100644
--- a/passes/techmap/simplemap.cc
+++ b/passes/techmap/simplemap.cc
@@ -32,7 +32,7 @@ static void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell)
 	RTLIL::SigSpec sig_a = cell->getPort("\\A");
 	RTLIL::SigSpec sig_y = cell->getPort("\\Y");
 
-	sig_a.extend(GetSize(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
+	sig_a.extend_u0(GetSize(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
 
 	for (int i = 0; i < GetSize(sig_y); i++) {
 		RTLIL::Cell *gate = module->addCell(NEW_ID, "$_NOT_");
-- 
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