From ca8711644975c128d45fd8e9434439c1266c00ac Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 15 Aug 2014 02:40:46 +0200
Subject: More idstring sort_by_* helpers and fixed tpl ordering in techmap

---
 passes/techmap/techmap.cc | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'passes/techmap')

diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index a7f91e862..59173393c 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -251,7 +251,7 @@ struct TechmapWorker
 	}
 
 	bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, std::set<RTLIL::Cell*> &handled_cells,
-			const std::map<RTLIL::IdString, std::set<RTLIL::IdString>> &celltypeMap, bool in_recursion)
+			const std::map<RTLIL::IdString, std::set<RTLIL::IdString, RTLIL::sort_by_id_str>> &celltypeMap, bool in_recursion)
 	{
 		std::string mapmsg_prefix = in_recursion ? "Recursively mapping" : "Mapping";
 
@@ -898,7 +898,7 @@ struct TechmapPass : public Pass {
 		}
 		map->modules_.swap(modules_new);
 
-		std::map<RTLIL::IdString, std::set<RTLIL::IdString>> celltypeMap;
+		std::map<RTLIL::IdString, std::set<RTLIL::IdString, RTLIL::sort_by_id_str>> celltypeMap;
 		for (auto &it : map->modules_) {
 			if (it.second->attributes.count("\\techmap_celltype") && !it.second->attributes.at("\\techmap_celltype").bits.empty()) {
 				char *p = strdup(it.second->attributes.at("\\techmap_celltype").decode_string().c_str());
@@ -960,7 +960,7 @@ struct FlattenPass : public Pass {
 		TechmapWorker worker;
 		worker.flatten_mode = true;
 
-		std::map<RTLIL::IdString, std::set<RTLIL::IdString>> celltypeMap;
+		std::map<RTLIL::IdString, std::set<RTLIL::IdString, RTLIL::sort_by_id_str>> celltypeMap;
 		for (auto &it : design->modules_)
 			celltypeMap[it.first].insert(it.first);
 
-- 
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