From bf607df6d57c3976880004192129eff8b1c0d0a9 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 29 Dec 2013 17:39:49 +0100 Subject: Fixed undef extend for bitwise binary ops (bugs in simplemap and satgen) --- passes/techmap/simplemap.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'passes/techmap') diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc index 2480cf285..e06a80bbd 100644 --- a/passes/techmap/simplemap.cc +++ b/passes/techmap/simplemap.cc @@ -77,11 +77,11 @@ static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell) int width = cell->parameters.at("\\Y_WIDTH").as_int(); RTLIL::SigSpec sig_a = cell->connections.at("\\A"); - sig_a.extend(width, cell->parameters.at("\\A_SIGNED").as_bool()); + sig_a.extend_u0(width, cell->parameters.at("\\A_SIGNED").as_bool()); sig_a.expand(); RTLIL::SigSpec sig_b = cell->connections.at("\\B"); - sig_b.extend(width, cell->parameters.at("\\B_SIGNED").as_bool()); + sig_b.extend_u0(width, cell->parameters.at("\\B_SIGNED").as_bool()); sig_b.expand(); RTLIL::SigSpec sig_y = cell->connections.at("\\Y"); -- cgit v1.2.3