From b96ffed69b1445cadb4eee0cc5272dd8b1bc915e Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 8 Mar 2013 09:16:25 +0100 Subject: Automatically select new objects in abc and techmap passes --- passes/techmap/techmap.cc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'passes/techmap') diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index d959dbe1d..c05a96cd4 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -112,6 +112,7 @@ static bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL:: w->port_output = false; w->port_id = 0; module->wires[w->name] = w; + design->select(module, w); } for (auto &it : tpl->cells) { @@ -122,6 +123,7 @@ static bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL:: for (auto &it2 : c->connections) apply_prefix(cell_name, it2.second, module); module->cells[c->name] = c; + design->select(module, c); } for (auto &it : tpl->connections) { -- cgit v1.2.3