From 04e466d5e4ca4654495cb1044f6f200d817f63a2 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 9 Apr 2019 10:06:44 -0700 Subject: Add support for synth_xilinx -abc9 and ignore abc9 -dress opt --- passes/techmap/abc9.cc | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'passes/techmap') diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index da3d36354..6e2e349ee 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -1237,6 +1237,11 @@ struct Abc9Pass : public Pass { map_mux16 = true; continue; } + if (arg == "-dress") { + // TODO + abc_dress = true; + continue; + } if (arg == "-g" && argidx+1 < args.size()) { for (auto g : split_tokens(args[++argidx], ",")) { vector gate_list; -- cgit v1.2.3 From 941365b4bb9db6fac6b57230482c6be61aafc53a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 9 Apr 2019 10:09:43 -0700 Subject: Comment out --- passes/techmap/abc9.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'passes/techmap') diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 6e2e349ee..ec4a28d08 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -1239,7 +1239,7 @@ struct Abc9Pass : public Pass { } if (arg == "-dress") { // TODO - abc_dress = true; + //abc_dress = true; continue; } if (arg == "-g" && argidx+1 < args.size()) { -- cgit v1.2.3 From 88d43a519bd0ea9657baba8bf9bc6a845b6cf14d Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 12 Apr 2019 16:29:14 -0700 Subject: Use -map instead of -symbols for aiger --- passes/techmap/abc9.cc | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'passes/techmap') diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index ec4a28d08..17d082833 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -407,7 +407,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri handle_loops(design); - Pass::call(design, stringf("write_xaiger -O -symbols %s/input.aig; ", tempdir_name.c_str())); + Pass::call(design, stringf("write_xaiger -O -map %s/input.sym %s/input.aig; ", tempdir_name.c_str(), tempdir_name.c_str())); design->selection_stack.pop_back(); @@ -523,7 +523,8 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri bool builtin_lib = liberty_file.empty(); RTLIL::Design *mapped_design = new RTLIL::Design; //parse_blif(mapped_design, ifs, builtin_lib ? "\\DFF" : "\\_dff_", false, sop_mode); - AigerReader reader(mapped_design, ifs, "\\netlist", "" /* clk_name */, "" /* map_filename */, true /* wideports */); + buffer = stringf("%s/%s", tempdir_name.c_str(), "input.sym"); + AigerReader reader(mapped_design, ifs, "\\netlist", "" /* clk_name */, buffer.c_str() /* map_filename */, true /* wideports */); reader.parse_xaiger(); ifs.close(); -- cgit v1.2.3 From 482a60825b607880c5984b1b39e06e58c5f75ada Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 12 Apr 2019 18:16:50 -0700 Subject: abc to ignore __dummy_o__ and __const[01]__ when re-integrating --- passes/techmap/abc9.cc | 26 ++++++++++++++++++++------ 1 file changed, 20 insertions(+), 6 deletions(-) (limited to 'passes/techmap') diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 17d082833..52b1b6d35 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -319,10 +319,10 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri if (!cleanup) tempdir_name[0] = tempdir_name[4] = '_'; tempdir_name = make_temp_dir(tempdir_name); - log_header(design, "Extracting gate netlist of module `%s' to `%s/input.aig'..\n", + log_header(design, "Extracting gate netlist of module `%s' to `%s/input.xaig'..\n", module->name.c_str(), replace_tempdir(tempdir_name, tempdir_name, show_tempdir).c_str()); - std::string abc_script = stringf("read %s/input.aig; &get -n; ", tempdir_name.c_str()); + std::string abc_script = stringf("&read %s/input.xaig; &ps ", tempdir_name.c_str()); if (!liberty_file.empty()) { abc_script += stringf("read_lib -w %s; ", liberty_file.c_str()); @@ -407,7 +407,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri handle_loops(design); - Pass::call(design, stringf("write_xaiger -O -map %s/input.sym %s/input.aig; ", tempdir_name.c_str(), tempdir_name.c_str())); + Pass::call(design, stringf("write_xaiger -O -map %s/input.sym %s/input.xaig; ", tempdir_name.c_str(), tempdir_name.c_str())); design->selection_stack.pop_back(); @@ -546,9 +546,10 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri output_bits.insert({wire, i}); } else { - if (w->name.str() == "\\__dummy_o__") { - log("Don't call ABC as there is nothing to map.\n"); - goto cleanup; + if (w->name.in("\\__dummy_o__", "\\__const0__", "\\__const1__")) { + //log("Don't call ABC as there is nothing to map.\n"); + //goto cleanup; + continue; } // Attempt another wideports_split here because there @@ -874,6 +875,19 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri RTLIL::Wire *w = it.second; if (!w->port_input && !w->port_output) continue; + if (w->name == "\\__const0__") { + log_assert(w->port_output); + module->connect(w, RTLIL::S0); + continue; + } + if (w->name == "\\__const1__") { + log_assert(w->port_output); + module->connect(w, RTLIL::S1); + continue; + } + if (w->name == "\\__dummy_o__") + continue; + RTLIL::Wire *wire = module->wire(w->name); RTLIL::Wire *remap_wire = module->wire(remap_name(w->name)); RTLIL::SigSpec signal; -- cgit v1.2.3 From 9bfcd8006378dc0d81a1c902501a6efeb8406cba Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 12 Apr 2019 18:21:16 -0700 Subject: Handle __dummy_o__ and __const[01]__ in read_aiger not abc --- passes/techmap/abc9.cc | 22 ++++------------------ 1 file changed, 4 insertions(+), 18 deletions(-) (limited to 'passes/techmap') diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 52b1b6d35..edc07092b 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -546,11 +546,10 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri output_bits.insert({wire, i}); } else { - if (w->name.in("\\__dummy_o__", "\\__const0__", "\\__const1__")) { - //log("Don't call ABC as there is nothing to map.\n"); - //goto cleanup; - continue; - } + //if (w->name == "\\__dummy_o__") { + // log("Don't call ABC as there is nothing to map.\n"); + // goto cleanup; + //} // Attempt another wideports_split here because there // exists the possibility that different bits of a port @@ -875,19 +874,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri RTLIL::Wire *w = it.second; if (!w->port_input && !w->port_output) continue; - if (w->name == "\\__const0__") { - log_assert(w->port_output); - module->connect(w, RTLIL::S0); - continue; - } - if (w->name == "\\__const1__") { - log_assert(w->port_output); - module->connect(w, RTLIL::S1); - continue; - } - if (w->name == "\\__dummy_o__") - continue; - RTLIL::Wire *wire = module->wire(w->name); RTLIL::Wire *remap_wire = module->wire(remap_name(w->name)); RTLIL::SigSpec signal; -- cgit v1.2.3