From edc378072301dba7ee79dd1d64a825faf72a1d62 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 30 Sep 2019 17:20:12 -0700 Subject: techmap wires named _TECHMAP_REPLACE_. to create alias --- passes/techmap/techmap.cc | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'passes/techmap/techmap.cc') diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 08a1af2d5..8f8cff9fa 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -257,6 +257,12 @@ struct TechmapWorker w->add_strpool_attribute(ID(src), extra_src_attrs); } design->select(module, w); + + if (it.second->name.begins_with("\\_TECHMAP_REPLACE_.")) { + IdString replace_name = stringf("%s%s", orig_cell_name.c_str(), it.second->name.c_str() + strlen("\\_TECHMAP_REPLACE_")); + Wire *replace_w = module->addWire(replace_name, it.second); + module->connect(replace_w, w); + } } SigMap tpl_sigmap(tpl); @@ -1198,6 +1204,10 @@ struct TechmapPass : public Pass { log("\n"); log("A cell with the name _TECHMAP_REPLACE_ in the map file will inherit the name\n"); log("and attributes of the cell that is being replaced.\n"); + log("A wire with a name of the form `_TECHMAP_REPLACE_.` in the map file will\n"); + log("cause a new wire alias to be created with its name set to the original but with\n"); + log("its `_TECHMAP_REPLACE_' prefix to be substituted with the name of the cell being\n"); + log("replaced.\n"); log("\n"); log("See 'help extract' for a pass that does the opposite thing.\n"); log("\n"); -- cgit v1.2.3