From b4a4cb081de717a7f6de89914f8f5ffec959b0c3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= Date: Wed, 5 Aug 2020 12:28:18 +0200 Subject: techmap.CONSTMAP: Handle outputs before inputs. Fixes #2321. --- passes/techmap/techmap.cc | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) (limited to 'passes/techmap/techmap.cc') diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index c22ae8ef0..8d16a2bae 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -801,11 +801,31 @@ struct TechmapWorker } } + // Handle outputs first, as these cannot be remapped. for (auto &conn : cell->connections()) + { + Wire *twire = tpl->wire(conn.first); + if (!twire->port_output) + continue; + + for (int i = 0; i < GetSize(conn.second); i++) { + RTLIL::SigBit bit = sigmap(conn.second[i]); + RTLIL::SigBit tplbit(twire, i); + cellbits_to_tplbits[bit] = tplbit; + } + } + + // Now handle inputs, remapping as necessary. + for (auto &conn : cell->connections()) + { + Wire *twire = tpl->wire(conn.first); + if (twire->port_output) + continue; + for (int i = 0; i < GetSize(conn.second); i++) { RTLIL::SigBit bit = sigmap(conn.second[i]); - RTLIL::SigBit tplbit(tpl->wire(conn.first), i); + RTLIL::SigBit tplbit(twire, i); if (bit.wire == nullptr) { @@ -820,6 +840,7 @@ struct TechmapWorker else cellbits_to_tplbits[bit] = tplbit; } + } RTLIL::SigSig port_conn; for (auto &it : port_connmap) { -- cgit v1.2.3